R5F21335CNFP#30_技术文档

Datasheet

R8C/33C Group

RENESAS MCU

R01DS0008EJ0100

Rev 1.00

Aug. 24, 2010

1. Overview

1.1

Features

The R8C/33C Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions

for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high

speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.

Power consumption is low, and the supported operating modes allow additional power control. These MCUs are

designed to maximize EMI/EMS performance.

Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of

system components.

The R8C/33C Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.

1.1.1

Applications

Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 1 of 53

R8C/33C Group

1. Overview

1.1.2

Specifications

Tables 1.1 and 1.2 outline the Specifications for R8C/33C Group.

Table 1.1

Specifications for R8C/33C Group (1)

Item

CPU

Function

Specification

Central processing R8C CPU core

unit

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operation mode: Single-chip mode (address space: 1 Mbyte)

Refer to Table 1.3 Product List for R8C/33C Group.

Memory

ROM, RAM, Data

flash

Power Supply Voltage detection

• Power-on reset

Voltage

Detection

I/O Ports

circuit

• Voltage detection 3 (detection level of voltage detection 0 and voltage

detection 1 selectable)

Programmable I/O • Input-only: 1 pin

ports

• CMOS I/O ports: 27, selectable pull-up resistor

• High current drive ports: 27

Clock

Clock generation

circuits

4 circuits: XIN clock oscillation circuit,

XCIN clock oscillation circuit (32 kHz),

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip oscillator

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, low-speed clock, high-speed

on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode

Real-time clock (timer RE)

Interrupts

• Number of interrupt vectors: 69

• External Interrupt: 7 (INT × 3, Key input × 4)

• Priority levels: 7 levels

Watchdog Timer

• 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer selectable

• 1 channel

DTC (Data Transfer Controller)

• Activation sources: 23

• Transfer modes: 2 (normal mode, repeat mode)

Timer

Timer RA

Timer RB

8 bits × 1 (with 8-bit prescaler)

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

8 bits × 1 (with 8-bit prescaler)

Timer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode, programmable wait one-

shot generation mode

Timer RC

Timer RE

16 bits × 1 (with 4 capture/compare registers)

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

8 bits × 1

Real-time clock mode (count seconds, minutes, hours, days of week), output

compare mode

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Aug. 24, 2010

Page 2 of 53

R8C/33C Group

1. Overview

Table 1.2

Specifications for R8C/33C Group (2)

Item

Serial

Interface

Function

UART0, UART1

UART2

Specification

Clock synchronous serial I/O/UART × 2 channel

Clock synchronous serial I/O/UART, I²C mode (I²C-bus),

multiprocessor communication function

1 (shared with I²C-bus)

Synchronous Serial

Communication Unit (SSU)

I²C bus

1 (shared with SSU)

LIN Module

Hardware LIN: 1 (timer RA, UART0)

A/D Converter

10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

D/A Converter

Comparator B

Flash Memory

8-bit resolution × 2 circuits

2 circuits

• Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 10,000 times (data flash)

1,000 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function

• Background operation (BGO) function

Operating Frequency/Supply

Voltage

f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)

Current Consumption

Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)

Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))

Typ. 2.0 µA (VCC = 3.0 V, stop mode)

Operating Ambient Temperature

Package

-20 to 85°C (N version)

-40 to 85°C (D version) ⁽¹⁾

32-pin LQFP

Package code: PLQP0032GB-A (previous code: 32P6U-A)

Note:

1. Specify the D version if D version functions are to be used.

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Aug. 24, 2010

Page 3 of 53

R8C/33C Group

1. Overview

1.2

Product List

Table 1.3 lists Product List for R8C/33C Group, and Figure 1.1 shows a Part Number, Memory Size, and Package

of R8C/33C Group.

Table 1.3

Product List for R8C/33C Group

Current of Aug 2010

ROM Capacity

RAM

Capacity

Part No.

Package Type

Remarks

Program ROM

4 Kbytes

Data flash

1 Kbyte × 4

R5F21331CNFP

R5F21332CNFP

R5F21334CNFP

R5F21335CNFP

R5F21336CNFP

R5F21331CDFP

R5F21332CDFP

R5F21334CDFP

R5F21335CDFP

R5F21336CDFP

512 bytes

1 Kbyte

PLQP0032GB-A N version

8 Kbytes

PLQP0032GB-A

PLQP0032GB-A D version

PLQP0032GB-A

16 Kbytes

24 Kbytes

32 Kbytes

4 Kbytes

1.5 Kbytes

2 Kbytes

2.5 Kbytes

512 bytes

1 Kbyte

8 Kbytes

16 Kbytes

24 Kbytes

32 Kbytes

1.5 Kbytes

2 Kbytes

2.5 Kbytes

Part No. R 5 F 21 33 6 C N FP

Package type:

FP: PLQP0032GB-A (0.8 mm pin-pitch, 7 mm square body)

Classification

N: Operating ambient temperature -20°C to 85°C

D: Operating ambient temperature -40°C to 85°C

ROM capacity

1: 4 KB

2: 8 KB

4: 16 KB

5: 24 KB

6: 32 KB

R8C/33C Group

R8C/3x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

Figure 1.1

Part Number, Memory Size, and Package of R8C/33C Group

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R8C/33C Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a Block Diagram.

8

3

1

3

5

Port P0

Port P1

I/O ports

Peripheral functions

Port P2

Port P3

Port P4

UART or

System clock generation

circuit

clock synchronous serial I/O

Timers

(8 bits × 3)

Timer RA (8 bits × 1)

Timer RB (8 bits × 1)

Timer RC (16 bits × 1)

Timer RE (8 bits × 1)

XIN-XOUT

I²C bus or SSU

(8 bits × 1)

High-speed on-chip oscillator

Low-speed on-chip oscillator

XCIN-XCOUT

LIN module

Low-speed on-chip oscillator

for watchdog timer

Watchdog timer

(14 bits)

Comparator B

Voltage detection circuit

DTC

A/D converter

(10 bits × 12 channels)

D/A converter

(8 bits × 2)

Memory

R8C CPU core

ROM ⁽¹⁾

R0H

R1H

R0L

R1L

SB

USP

ISP

INTB

PC

FLG

R2

R3

RAM ⁽²⁾

A0

A1

FB

Multiplier

Notes:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

Figure 1.2

Block Diagram

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R8C/33C Group

1. Overview

1.4

Pin Assignment

Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outline the Pin Name Information by Pin Number.

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

P4_5/ADTRG/INT0(/RXD2/SCL2)

P3_1(/TRBO)

P2_0(/INT1/TRCIOB)

P0_7/AN0/DA1(/TRCIOC)

P0_6/AN1/DA0(/TRCIOD)

P0_5/AN2(/TRCIOB)

P0_4/AN3/TREO(/TRCIOB)

R8C/33C Group

P2_1(/TRCIOC)

P2_2(/TRCIOD)

P0_3/AN4(/CLK1/TRCIOB)

PLQP0032GB-A

(32P6U-A)

P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)

P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)

P3_5/SCL/SSCK(/CLK2/TRCIOD)

P0_2/AN5(/RXD1/TRCIOA/TRCTRG)

P0_1/AN6(/TXD1/TRCIOA/TRCTRG)

P0_0/AN7(/TRCIOA/TRCTRG)

(top view)

1

2

3

4

5

6

7

8

Notes:

1. Can be assigned to the pin in parentheses by a program.

2. Confirm the pin 1 position on the package by referring to the package dimensions.

Figure 1.3

Pin Assignment (Top View)

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Aug. 24, 2010

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R8C/33C Group

1. Overview

Table 1.4

Pin Name Information by Pin Number

I/O Pin Functions for Peripheral Modules

Number

A/D Converter,

D/A Converter,

Comparator B

I²C

bus

Control Pin

Port

Serial

Interface

Interrupt

Timer

SSU

1

2

3

P4_2

VREF

MODE

RESET

4

5

6

7

8

XOUT(/XCOUT) P4_7

VSS/AVSS

XIN(/XCIN)

VCC/AVCC

P4_6

P3_7

TRAO

(RXD2/SCL2/ SSO SDA

TXD2/SDA2)

9

P3_5

P3_4

(TRCIOD)

(CLK2)

SSCK SCL

SSI

10

(TRCIOC) (RXD2/SCL2/

TXD2/SDA2)

IVREF3

IVCMP3

11

P3_3

(TRCCLK)

INT3

(CTS2/RTS2) SCS

12

13

14

P2_2

P2_1

P2_0

(TRCIOD)

(TRCIOC)

(TRCIOB)

(INT1)

15

16

P3_1

P4_5

(TRBO)

(RXD2/SCL2)

INT0

INT1

ADTRG

IVCMP1

17

P1_7

(TRAIO)

18

19

P1_6

P1_5

(CLK0)

(RXD0)

IVREF1

(TRAIO)

(INT1)

KI3

20

21

P1_4

P1_3

(TRCCLK)

(TXD0)

TRBO

(/TRCIOC)

AN11

22

23

P1_2

P1_1

(TRCIOB)

AN10

AN9

KI2

KI1

(TRCIOA/

TRCTRG)

24

P1_0

(TRCIOD)

AN8

KI0

25

26

27

P0_7

P0_6

P0_5

(TRCIOC)

(TRCIOD)

(TRCIOB)

AN0/DA1

AN1/DA0

AN2

TREO

(/TRCIOB)

28

29

30

P0_4

P0_3

P0_2

AN3

AN4

AN5

(TRCIOB)

(CLK1)

(RXD1)

(TRCIOA/

TRCTRG)

(TRCIOA/

TRCTRG)

31

32

P0_1

P0_0

(TXD1)

AN6

AN7

(TRCIOA/

TRCTRG)

Note:

1. Can be assigned to the pin in parentheses by a program.

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Aug. 24, 2010

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R8C/33C Group

1. Overview

1.5

Pin Functions

Tables 1.5 and 1.6 list Pin Functions.

Table 1.5

Item

Pin Functions (1)

Pin Name

I/O Type

Description

Power supply input VCC, VSS

−

Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.

Analog power

supply input

AVCC, AVSS

Power supply for the A/D converter.

Connect a capacitor between AVCC and AVSS.

Reset input

MODE

RESET

MODE

XIN

I

Input “L” on this pin resets the MCU.

Connect this pin to VCC via a resistor.

XIN clock input

These pins are provided for XIN clock generation circuit I/O.

Connect a ceramic resonator or a crystal oscillator between

the XIN and XOUT pins ⁽¹⁾. To use an external clock, input it

to the XOUT pin and leave the XIN pin open.

XIN clock output

XCIN clock input

XOUT

XCIN

I/O

I

These pins are provided for XCIN clock generation circuit I/O.

Connect a crystal oscillator between the XCIN and XCOUT

pins ⁽¹⁾. To use an external clock, input it to the XCIN pin and

leave the XCOUT pin open.

XCIN clock output XCOUT

O

INT interrupt input INT0, INT1, INT3

I

INT interrupt input pins.

INT0 is timer RB, and RC input pin.

Key input interrupt

Timer RA

Key input interrupt input pins

KI0 to KI3

TRAIO

I/O

O

I

Timer RA I/O pin

TRAO

Timer RA output pin

Timer RB output pin

External clock input pin

External trigger input pin

Timer RC I/O pins

Timer RB

Timer RC

TRBO

TRCCLK

TRCTRG

I

TRCIOA, TRCIOB,

TRCIOC, TRCIOD

I/O

Timer RE

TREO

O

I/O

I

Divided clock output pin

Transfer clock I/O pins

Serial data input pins

Serial interface

CLK0, CLK1, CLK2

RXD0, RXD1, RXD2

TXD0, TXD1, TXD2

O

I

Serial data output pins

Transmission control input pin

CTS2

O

Reception control output pin

RTS2

SCL2

SDA2

SCL

I²C mode clock I/O pin

I²C mode data I/O pin

Clock I/O pin

I/O

I²C bus

SSU

SDA

SSI

Data I/O pin

Chip-select signal I/O pin

SCS

SSCK

SSO

I/O

Clock I/O pin

Data I/O pin

I: Input

Note:

O: Output

I/O: Input and output

1. Refer to the oscillator manufacturer for oscillation characteristics.

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R8C/33C Group

1. Overview

Table 1.6

Pin Functions (2)

Item

Pin Name

I/O Type

I

Description

Reference voltage VREF

Reference voltage input pin to A/D converter and D/A

converter

input

A/D converter

AN0 to AN11

I

Analog input pins to A/D converter

A/D external trigger input pin

ADTRG

D/A converter

Comparator B

DA0, DA1

O

I

D/A converter output pins

IVCMP1, IVCMP3

IVREF1, IVREF3

Comparator B analog voltage input pins

Comparator B reference voltage input pins

I

I/O port

P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_2,

P3_1,

P3_3 to P3_5,

P3_7,

I/O

CMOS I/O ports. Each port has an I/O select direction

register, allowing each pin in the port to be directed for input

or output individually.

Any port set to input can be set to use a pull-up resistor or not

by a program.

All ports can be used as LED drive ports.

P4_5 to P4_7

Input port

P4_2

I

Input-only port

I: Input

O: Output

I/O: Input and output

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R8C/33C Group

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

register bank. There are two sets of register bank.

b31

b15

b8b7

b0

R0H (high-order of R0) R0L (low-order of R0)

R1H (high-order of R1) R1L (low-order of R1)

R2

R3

Data registers ⁽¹⁾

R3

A0

Address registers ⁽¹⁾

A1

FB

Frame base register ⁽¹⁾

b19

b15

b0

Interrupt table register

Program counter

INTBH

INTBL

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

b19

PC

b15

b0

User stack pointer

Interrupt stack pointer

Static base register

USP

ISP

SB

b15

b0

Flag register

FLG

b15

b8

b7

IPL

U I O B S Z D C

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

Note:

1. These registers comprise a register bank. There are two register banks.

Figure 2.1

CPU Registers

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R8C/33C Group

2. Central Processing Unit (CPU)

2.1

Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split

into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are

analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is

analogous to R2R0.

2.2

Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also

used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-

bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the starting address of an interrupt vector table.

2.5

Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between

USP and ISP.

2.7

Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8

Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1

Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2

Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3

Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4

Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.

2.8.5

Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.

2.8.6

Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

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R8C/33C Group

2. Central Processing Unit (CPU)

2.8.7

Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8

Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

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R8C/33C Group

3. Memory

3.1

R8C/33C Group

Figure 3.1 is a Memory Map of R8C/33C Group. The R8C/33C Group has a 1-Mbyte address space from addresses

00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address

0FFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal

RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral

function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be

accessed by users.

00000h

SFR

(Refer to 4. Special

Function Registers

(SFRs))

002FFh

00400h

Internal RAM

0FFD8h

0FFDCh

0XXXXh

02C00h

Reserved area

SFR

Undefined instruction

(Refer to 4. Special Function

Registers (SFRs))

Overflow

02FFFh

03000h

BRK instruction

Internal ROM

(data flash) ⁽¹⁾

Address match

Single step

03FFFh

0YYYYh

Watchdog timer, oscillation stop detection, voltage monitor

Address break

(Reserved)

Reset

Internal ROM

(program ROM)

0FFFFh

ZZZZZh

0FFFFh

Internal ROM

(program ROM)

FFFFFh

Notes:

1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).

2. The blank areas are reserved and cannot be accessed by users.

Internal ROM

Part Number

Internal RAM

Address ZZZZZh

Size

Address 0YYYYh

Size

Address 0XXXXh

R5F21331CNFP, R5F21331CDFP

R5F21332CNFP, R5F21332CDFP

R5F21334CNFP, R5F21334CDFP

R5F21335CNFP, R5F21335CDFP

R5F21336CNFP, R5F21336CDFP

4 Kbytes

8 Kbytes

0F000h

0E000h

0C000h

0A000h

08000h

−

512 bytes

1 Kbyte

005FFh

007FFh

009FFh

00BFFh

00DFFh

16 Kbytes

24 Kbytes

32 Kbytes

1.5 Kbytes

2 Kbytes

2.5 Kbytes

Figure 3.1

Memory Map of R8C/33C Group

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R8C/33C Group

4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special

function registers and Table 4.13 lists the ID Code Areas and Option Function Select Area.

(1)

Table 4.1

SFR Information (1)

Address

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

Register

Symbol

After Reset

Processor Mode Register 0

Processor Mode Register 1

PM0

PM1

CM0

CM1

00h

System Clock Control Register 0

System Clock Control Register 1

Module Standby Control Register

System Clock Control Register 3

Protect Register

Reset Source Determination Register

Oscillation Stop Detection Register

Watchdog Timer Reset Register

Watchdog Timer Start Register

Watchdog Timer Control Register

00101000b

00100000b

00h

MSTCR

CM3

PRCR

RSTFR

OCD

WDTR

WDTS

WDTC

00h

(2)

0XXXXXXXb

00000100b

XXh

00111111b

High-Speed On-Chip Oscillator Control Register 7

FRA7

CSPR

When shipping

Count Source Protection Mode Register

00h

(3)

10000000b

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

High-Speed On-Chip Oscillator Control Register 0

High-Speed On-Chip Oscillator Control Register 1

High-Speed On-Chip Oscillator Control Register 2

On-Chip Reference Voltage Control Register

FRA0

FRA1

FRA2

OCVREFCR

00h

When shipping

00h

Clock Prescaler Reset Flag

CPSRF

FRA4

FRA5

FRA6

00h

High-Speed On-Chip Oscillator Control Register 4

High-Speed On-Chip Oscillator Control Register 5

High-Speed On-Chip Oscillator Control Register 6

When Shipping

High-Speed On-Chip Oscillator Control Register 3

Voltage Monitor Circuit Control Register

Voltage Monitor Circuit Edge Select Register

FRA3

CMPA

VCAC

When shipping

00h

Voltage Detect Register 1

Voltage Detect Register 2

VCA1

VCA2

00001000b

00h

00100000b

(4)

(5)

0035h

0036h

0037h

0038h

Voltage Detection 1 Level Select Register

Voltage Monitor 0 Circuit Control Register

Voltage Monitor 1 Circuit Control Register

VD1LS

VW0C

VW1C

00000111b

(4)

1100X010b

1100X011b

10001010b

(5)

0039h

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, Software reset, or watchdog timer

reset does not affect this bit.

3. The CSPROINI bit in the OFS register is set to 0.

4. The LVDAS bit in the OFS register is set to 1.

5. The LVDAS bit in the OFS register is set to 0.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 14 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.2

SFR Information (2)

Address

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

Register

Symbol

After Reset

10000010b

Voltage Monitor 2 Circuit Control Register

VW2C

Flash Memory Ready Interrupt Control Register

Timer RC Interrupt Control Register

FMRDYIC

TRCIC

XXXXX000b

Timer RE Interrupt Control Register

TREIC

XXXXX000b

UART2 Transmit Interrupt Control Register

UART2 Receive Interrupt Control Register

Key Input Interrupt Control Register

A/D Conversion Interrupt Control Register

SSU Interrupt Control Register / IIC bus Interrupt Control Register

S2TIC

S2RIC

KUPIC

ADIC

(2)

SSUIC / IICIC

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

S0TIC

S0RIC

S1TIC

S1RIC

XXXXX000b

Timer RA Interrupt Control Register

TRAIC

XXXXX000b

Timer RB Interrupt Control Register

INT1 Interrupt Control Register

INT3 Interrupt Control Register

TRBIC

INT1IC

INT3IC

XXXXX000b

XX00X000b

INT0 Interrupt Control Register

INT0IC

U2BCNIC

XX00X000b

XXXXX000b

UART2 Bus Collision Detection Interrupt Control Register

Voltage Monitor 1 Interrupt Control Register

Voltage Monitor 2 Interrupt Control Register

VCMP1IC

VCMP2IC

XXXXX000b

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. Selectable by the IICSEL bit in the SSUIICSR register.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 15 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.3

SFR Information (3)

Address

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h

00A1h

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

Register

Symbol

DTCTL

After Reset

DTC Activation Control Register

00h

DTC Activation Enable Register 0

DTC Activation Enable Register 1

DTC Activation Enable Register 2

DTC Activation Enable Register 3

DTCEN0

DTCEN1

DTCEN2

DTCEN3

00h

DTC Activation Enable Register 5

DTC Activation Enable Register 6

DTCEN5

DTCEN6

00h

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register

U0MR

U0BRG

U0TB

00h

XXh

UART0 Transmit Buffer Register

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

U0C0

U0C1

U0RB

00001000b

00000010b

XXh

00h

XXh

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Register

U2MR

U2BRG

U2TB

UART2 Transmit Buffer Register

XXh

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

U2C0

U2C1

U2RB

00001000b

00000010b

XXh

00h

UART2 Digital Filter Function Select Register

URXDF

UART2 Special Mode Register 5

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

U2SMR5

U2SMR4

U2SMR3

U2SMR2

U2SMR

00h

000X0X0Xb

X0000000b

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 16 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.4

SFR Information (4)

Address

Register

Symbol

After Reset

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

A/D Register 0

A/D Register 1

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

XXXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

000000XXb

XXh

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

000000XXb

XXh

000000XXb

A/D Mode Register

A/D Input Select Register

A/D Control Register 0

A/D Control Register 1

D/A0 Register

ADMOD

ADINSEL

ADCON0

ADCON1

DA0

00h

11000000b

00h

D/A1 Register

DA1

00h

D/A Control Register

DACON

00h

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

P0

P1

PD0

PD1

P2

XXh

00h

XXh

00h

XXh

Port P3 Register

P3

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

PD2

PD3

P4

Port P4 Direction Register

PD4

00h

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 17 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.5

SFR Information (5)

Address

0100h

0101h

0102h

0103h

0104h

0105h

0106h

0107h

0108h

0109h

010Ah

010Bh

010Ch

010Dh

010Eh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h

0119h

011Ah

011Bh

011Ch

011Dh

011Eh

011Fh

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

Register

Symbol

TRACR

TRAIOC

TRAMR

TRAPRE

TRA

LINCR2

LINCR

LINST

TRBCR

TRBOCR

TRBIOC

TRBMR

TRBPRE

TRBSC

TRBPR

After Reset

Timer RA Control Register

Timer RA I/O Control Register

Timer RA Mode Register

Timer RA Prescaler Register

Timer RA Register

LIN Control Register 2

LIN Control Register

LIN Status Register

00h

FFh

00h

FFh

Timer RB Control Register

Timer RB One-Shot Control Register

Timer RB I/O Control Register

Timer RB Mode Register

Timer RB Prescaler Register

Timer RB Secondary Register

Timer RB Primary Register

Timer RE Second Data Register / Counter Data Register

Timer RE Minute Data Register / Compare Data Register

Timer RE Hour Data Register

TRESEC

TREMIN

TREHR

TREWK

TRECR1

TRECR2

TRECSR

00h

Timer RE Day of Week Data Register

Timer RE Control Register 1

Timer RE Control Register 2

Timer RE Count Source Select Register

00001000b

Timer RC Mode Register

TRCMR

TRCCR1

TRCIER

TRCSR

TRCIOR0

TRCIOR1

TRC

01001000b

00h

Timer RC Control Register 1

Timer RC Interrupt Enable Register

Timer RC Status Register

Timer RC I/O Control Register 0

Timer RC I/O Control Register 1

Timer RC Counter

01110000b

10001000b

00h

FFh

Timer RC General Register A

Timer RC General Register B

Timer RC General Register C

Timer RC General Register D

TRCGRA

TRCGRB

TRCGRC

TRCGRD

FFh

Timer RC Control Register 2

TRCCR2

TRCDF

TRCOER

TRCADCR

00011000b

00h

01111111b

00h

Timer RC Digital Filter Function Select Register

Timer RC Output Master Enable Register

Timer RC Trigger Control Register

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 18 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.6

SFR Information (6)

Address

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

Register

Symbol

After Reset

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Register

U1MR

00h

XXh

U1BRG

U1TB

UART1 Transmit Buffer Register

UART1 Transmit/Receive Control Register 0

UART1 Transmit/Receive Control Register 1

UART1 Receive Buffer Register

U1C0

U1C1

U1RB

00001000b

00000010b

XXh

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 19 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.7

SFR Information (7)

Address

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

Register

Symbol

TRASR

TRBRCSR

TRCPSR0

TRCPSR1

After Reset

Timer RA Pin Select Register

Timer RB/RC Pin Select Register

Timer RC Pin Select Register 0

Timer RC Pin Select Register 1

00h

UART0 Pin Select Register

UART1 Pin Select Register

UART2 Pin Select Register 0

UART2 Pin Select Register 1

SSU/IIC Pin Select Register

U0SR

U1SR

U2SR0

U2SR1

SSUIICSR

00h

INT Interrupt Input Pin Select Register

I/O Function Pin Select Register

INTSR

PINSR

00h

SS Bit Counter Register

SSBR

SSTDR / ICDRT

SSTDRH

SSRDR / ICDRR

SSRDRH

SSCRH / ICCR1

SSCRL / ICCR2

SSMR / ICMR

SSER / ICIER

SSSR / ICSR

SSMR2 / SAR

11111000b

(2)

FFh

SS Transmit Data Register L / IIC bus Transmit Data Register

(2)

SS Transmit Data Register H

(2)

SS Receive Data Register L / IIC bus Receive Data Register

(2)

SS Receive Data Register H

(2)

00h

SS Control Register H / IIC bus Control Register 1

SS Control Register L / IIC bus Control Register 2

(2)

01111101b

00010000b / 00011000b

(2)

SS Mode Register / IIC bus Mode Register

(2)

00h

SS Enable Register / IIC bus Interrupt Enable Register

(2)

00h / 0000X000b

00h

SS Status Register / IIC bus Status Register

(2)

SS Mode Register 2 / Slave Address Register

Flash Memory Status Register

FST

10000X00b

Flash Memory Control Register 0

Flash Memory Control Register 1

Flash Memory Control Register 2

FMR0

FMR1

FMR2

00h

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. Selectable by the IICSEL bit in the SSUIICSR register.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 20 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.8

SFR Information (8)

Address

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

Register

Symbol

RMAD0

After Reset

Address Match Interrupt Register 0

XXh

0000XXXXb

00h

Address Match Interrupt Enable Register 0

Address Match Interrupt Register 1

AIER0

RMAD1

XXh

0000XXXXb

00h

Address Match Interrupt Enable Register 1

AIER1

Pull-Up Control Register 0

Pull-Up Control Register 1

PUR0

PUR1

00h

Port P1 Drive Capacity Control Register

Port P2 Drive Capacity Control Register

Drive Capacity Control Register 0

Drive Capacity Control Register 1

P1DRR

P2DRR

DRR0

00h

DRR1

Input Threshold Control Register 0

Input Threshold Control Register 1

VLT0

VLT1

00h

Comparator B Control Register 0

External Input Enable Register 0

INT Input Filter Select Register 0

Key Input Enable Register 0

INTCMP

INTEN

INTF

00h

KIEN

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 21 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.9

SFR Information (9)

Address

2C00h

2C01h

2C02h

2C03h

2C04h

2C05h

2C06h

2C07h

2C08h

2C09h

2C0Ah

:

Register

Symbol

After Reset

DTC Transfer Vector Area

DTC Control Data 0

XXh

:

2C3Ah

2C3Bh

2C3Ch

2C3Dh

2C3Eh

2C3Fh

2C40h

2C41h

2C42h

2C43h

2C44h

2C45h

2C46h

2C47h

2C48h

2C49h

2C4Ah

2C4Bh

2C4Ch

2C4Dh

2C4Eh

2C4Fh

2C50h

2C51h

2C52h

2C53h

2C54h

2C55h

2C56h

2C57h

2C58h

2C59h

2C5Ah

2C5Bh

2C5Ch

2C5Dh

2C5Eh

2C5Fh

2C60h

2C61h

2C62h

2C63h

2C64h

2C65h

2C66h

2C67h

2C68h

2C69h

2C6Ah

2C6Bh

2C6Ch

2C6Dh

2C6Eh

2C6Fh

DTCD0

DTC Control Data 1

DTC Control Data 2

DTC Control Data 3

DTC Control Data 4

DTC Control Data 5

DTCD1

DTCD2

DTCD3

DTCD4

DTCD5

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 22 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.10

SFR Information (10)

Address

2C70h

2C71h

2C72h

2C73h

2C74h

2C75h

2C76h

2C77h

2C78h

2C79h

2C7Ah

2C7Bh

2C7Ch

2C7Dh

2C7Eh

2C7Fh

2C80h

2C81h

2C82h

2C83h

2C84h

2C85h

2C86h

2C87h

2C88h

2C89h

2C8Ah

2C8Bh

2C8Ch

2C8Dh

2C8Eh

2C8Fh

2C90h

2C91h

2C92h

2C93h

2C94h

2C95h

2C96h

2C97h

2C98h

2C99h

2C9Ah

2C9Bh

2C9Ch

2C9Dh

2C9Eh

2C9Fh

2CA0h

2CA1h

2CA2h

2CA3h

2CA4h

2CA5h

2CA6h

2CA7h

2CA8h

2CA9h

2CAAh

2CABh

2CACh

2CADh

2CAEh

2CAFh

Register

Symbol

DTCD6

After Reset

DTC Control Data 6

XXh

DTC Control Data 7

DTC Control Data 8

DTC Control Data 9

DTC Control Data 10

DTC Control Data 11

DTC Control Data 12

DTC Control Data 13

DTCD7

DTCD8

DTCD9

DTCD10

DTCD11

DTCD12

DTCD13

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 23 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.11

SFR Information (11)

Address

2CB0h

2CB1h

2CB2h

2CB3h

2CB4h

2CB5h

2CB6h

2CB7h

2CB8h

2CB9h

2CBAh

2CBBh

2CBCh

2CBDh

2CBEh

2CBFh

2CC0h

2CC1h

2CC2h

2CC3h

2CC4h

2CC5h

2CC6h

2CC7h

2CC8h

2CC9h

2CCAh

2CCBh

2CCCh

2CCDh

2CCEh

2CCFh

2CD0h

2CD1h

2CD2h

2CD3h

2CD4h

2CD5h

2CD6h

2CD7h

2CD8h

2CD9h

2CDAh

2CDBh

2CDCh

2CDDh

2CDEh

2CDFh

2CE0h

2CE1h

2CE2h

2CE3h

2CE4h

2CE5h

2CE6h

2CE7h

2CE8h

2CE9h

2CEAh

2CEBh

2CECh

2CEDh

2CEEh

2CEFh

Register

Symbol

DTCD14

After Reset

DTC Control Data 14

XXh

DTC Control Data 15

DTC Control Data 16

DTC Control Data 17

DTC Control Data 18

DTC Control Data 19

DTC Control Data 20

DTC Control Data 21

DTCD15

DTCD16

DTCD17

DTCD18

DTCD19

DTCD20

DTCD21

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 24 of 53

R8C/33C Group

4. Special Function Registers (SFRs)

(1)

Table 4.12

SFR Information (12)

Address

2CF0h

2CF1h

2CF2h

2CF3h

2CF4h

2CF5h

2CF6h

2CF7h

2CF8h

2CF9h

2CFAh

2CFBh

2CFCh

2CFDh

2CFEh

2CFFh

2D00h

:

Register

Symbol

DTCD22

After Reset

DTC Control Data 22

XXh

DTC Control Data 23

DTCD23

2FFFh

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Table 4.13

ID Code Areas and Option Function Select Area

Address

Area Name

Symbol

After Reset

:

FFDBh

Option Function Select Register 2

OFS2

(Note 1)

(Note 2)

(Note 1)

:

FFDFh

:

FFE3h

:

FFEBh

:

FFEFh

:

FFF3h

:

FFF7h

:

FFFBh

:

FFFFh

ID1

ID2

ID3

ID4

ID5

ID6

ID7

Option Function Select Register

OFS

Notes:

1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select

area is set to FFh.

When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.

When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.

2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.

When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.

When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.

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5. Electrical Characteristics

Table 5.1

Absolute Maximum Ratings

Symbol

Parameter

Supply voltage

Condition

Rated Value

−0.3 to 6.5

Unit

V

VCC/AVCC

VI

Input voltage

−0.3 to VCC + 0.3

500

V

VO

Pd

Output voltage

V

Power dissipation

Operating ambient temperature

−40°C ≤ Topr ≤ 85°C

mW

°C

Topr

−20 to 85 (N version) /

−40 to 85 (D version)

Tstg

Storage temperature

−65 to 150

°C

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5. Electrical Characteristics

Table 5.2

Recommended Operating Conditions

Standard

Unit

Symbol

Parameter

Conditions

Min.

1.8

Typ.

−

0

−

Max.

5.5

VCC/AVCC Supply voltage

V

mA

VSS/AVSS Supply voltage

−

VIH

Input “H” voltage Other than CMOS input

CMOS Input level Input level selection 4.0 V ≤ VCC ≤ 5.5 V

0.8 VCC

0.5 VCC

0.55 VCC

0.65 VCC

VCC

0.2 VCC

input

switching

function

(I/O port)

: 0.35 VCC

2.7 V ≤ VCC < 4.0 V

1.8 V ≤ VCC < 2.7 V

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

: 0.5 VCC

2.7 V ≤ VCC < 4.0 V

1.8 V ≤ VCC < 2.7 V

0.7

0.8

V

CC

V

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

0.85 VCC

: 0.7 VCC

2.7 V ≤ VCC < 4.0 V

1.8 V ≤ VCC < 2.7 V

0.85 VCC

External clock input (XOUT)

1.2

0

VIL

Input “L” voltage Other than CMOS input

CMOS Input level Input level selection 4.0 V ≤ VCC ≤ 5.5 V

0

input

switching

function

(I/O port)

: 0.35 VCC

2.7 V ≤ VCC < 4.0 V

1.8 V ≤ VCC < 2.7 V

0

0.2

0.4

0.3

0.2

V

CC

0

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

0

: 0.5 VCC

2.7 V ≤ VCC < 4.0 V

1.8 V ≤ VCC < 2.7 V

0

Input level selection 4.0 V ≤ VCC ≤ 5.5 V

0

0.55 VCC

0.45 VCC

0.35 VCC

0.4

: 0.7 VCC

2.7 V ≤ VCC < 4.0 V

1.8 V ≤ VCC < 2.7 V

0

External clock input (XOUT)

0

IOH(sum) Peak sum output Sum of all pins IOH(peak)

“H” current

−

−160

IOH(sum) Average sum

output “H” current

Sum of all pins IOH(avg)

−

−80

mA

IOH(peak) Peak output “H”

current

Drive capacity Low

Drive capacity High

Drive capacity Low

Drive capacity High

−

−10

−40

−5

mA

IOH(avg)

Average output

“H” current

−20

160

IOL(sum)

Peak sum output Sum of all pins IOL(peak)

“L” current

Average sum

Sum of all pins IOL(avg)

−

80

mA

output “L” current

IOL(peak) Peak output “L”

current

Drive capacity Low

Drive capacity High

Drive capacity Low

Drive capacity High

−

10

40

5

mA

−

IOL(avg)

Average output

“L” current

−

mA

−

20

5

mA

f(XIN)

XIN clock input oscillation frequency

2.7 V ≤ VCC ≤ 5.5 V

1.8 V ≤ VCC < 2.7 V

1.8 V ≤ VCC ≤ 5.5 V

2.7 V ≤ VCC ≤ 5.5 V

−

MHz

kHz

MHz

−

32.768

−

f(XCIN)

XCIN clock input oscillation frequency

−

50

40

When used as the count source for timer RC ⁽³⁾

fOCO40M

32

fOCO-F fOCO-F frequency

2.7 V ≤ VCC ≤ 5.5 V

1.8 V ≤ VCC < 2.7 V

2.7 V ≤ VCC ≤ 5.5 V

1.8 V ≤ VCC < 2.7 V

2.7 V ≤ VCC ≤ 5.5 V

1.8 V ≤ VCC < 2.7 V

−

20

5

MHz

−

System clock frequency

CPU clock frequency

20

5

f(BCLK)

20

5

Notes:

1. VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. The average output current indicates the average value of current measured during 100 ms.

3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 V to 5.5 V.

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5. Electrical Characteristics

P0

P1

P2

P3

P4

30pF

Figure 5.1

Ports P0 to P4 Timing Measurement Circuit

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R8C/33C Group

5. Electrical Characteristics

Table 5.3

A/D Converter Characteristics

Standard

Unit

Symbol

Parameter

Conditions

Min.

−

Typ.

−

Max.

10

−

Resolution

Vref = AVCC

Bit

Absolute accuracy

10-bit mode

Vref = AVCC = 5.0 V

Vref = AVCC = 3.3 V

Vref = AVCC = 3.0 V

Vref = AVCC = 2.2 V

Vref = AVCC = 5.0 V

Vref = AVCC = 3.3 V

Vref = AVCC = 3.0 V

Vref = AVCC = 2.2 V

AN0 to AN7 input,

AN8 to AN11 input

−

±3

LSB

AN0 to AN7 input,

AN8 to AN11 input

−

±5

±2

LSB

AN0 to AN7 input,

AN8 to AN11 input

AN0 to AN7 input,

AN8 to AN11 input

8-bit mode

AN0 to AN7 input,

AN8 to AN11 input

AN0 to AN7 input,

AN8 to AN11 input

AN0 to AN7 input,

AN8 to AN11 input

AN0 to AN7 input,

AN8 to AN11 input

4.0 ≤ Vref = AVCC ≤ 5.5 V ⁽²⁾

3.2 ≤ Vref = AVCC ≤ 5.5 V ⁽²⁾

2.7 ≤ Vref = AVCC ≤ 5.5 V ⁽²⁾

2.2 ≤ Vref = AVCC ≤ 5.5 V ⁽²⁾

φAD

A/D conversion clock

2

−

20

16

10

5

MHz

kΩ

µs

2

−

2

−

Tolerance level impedance

Conversion time

−

3

−

tCONV

10-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz

2.2

0.8

−

8-bit mode

Vref = AVCC = 5.0 V, φAD = 20 MHz

φAD = 20 MHz

−

µs

tSAMP

IVref

Vref

Sampling time

−

µs

Vref current

Vcc = 5 V, XIN = f1 = φAD = 20 MHz

45

−

µA

V

Reference voltage

Analog input voltage ⁽³⁾

2.2

0

AVCC

Vref

1.49

VIA

−

V

OCVREF On-chip reference voltage

2 MHz ≤ φAD ≤ 4 MHz

1.19

1.34

V

Notes:

1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise

specified.

2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-current-

consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.

3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in

8-bit mode.

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5. Electrical Characteristics

Table 5.4

D/A Converter Characteristics

Standard

Unit

Symbol

Parameter

Condition

Min.

−

Typ.

−

Max.

8

−

Resolution

Bit

LSB

µs

−

Absolute accuracy

Setup time

−

2.5

3

tsu

RO

IVref

−

Output resistor

−

6

−

kΩ

Reference power input current

(Note 2)

−

1.5

mA

Notes:

1. VCC/AVCC = Vref = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.

The resistor ladder of the A/D converter is not included.

Table 5.5

Comparator B Electrical Characteristics

Standard

Symbol

Vref

Parameter

Condition

Unit

Min.

0

Typ.

−

Max.

VCC − 1.4

VCC + 0.3

100

IVREF1, IVREF3 input reference voltage

IVCMP1, IVCMP3 input voltage

Offset

V

VI

−0.3

−

5

mV

µs

µA

Comparator output delay time ⁽²⁾

Comparator operating current

td

VI = Vref ± 100 mV

VCC = 5.0 V

−

0.1

17.5

−

ICMP

−

Notes:

1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. When the digital filter is disabled.

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5. Electrical Characteristics

Table 5.6

Flash Memory (Program ROM) Electrical Characteristics

Standard

Unit

Symbol

Parameter

Conditions

Min.

Typ.

−

Max.

−

Program/erase endurance ⁽²⁾

Byte program time

1,000 ⁽³⁾

−

times

µs

−

80

0.3

−

500

−

Block erase time

s

td(SR-SUS)

Time delay from suspend request until

suspend

5+CPU clock

× 3 cycles

ms

−

Interval from erase start/restart until

following suspend request

0

−

µs

Time from suspend until erase restart

30+CPUclock

× 1 cycle

td(CMDRST-

READY)

Time from when command is forcibly

terminated until reading is enabled

30+CPUclock

× 1 cycle

−

Program, erase voltage

Read voltage

2.7

1.8

0

−

5.5

60

−

V

Program, erase temperature

Data hold time ⁽⁷⁾

°C

Ambient temperature = 55°C

20

year

Notes:

1. VCC = 2.7 to 5.5 V and Topr = 0 to 60°C, unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte

writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit

the number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

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5. Electrical Characteristics

Table 5.7

Flash Memory (Data flash Block A to Block D) Electrical Characteristics

Standard

Typ.

−

Symbol

Parameter

Conditions

Unit

Min.

10,000

−

Max.

−

Program/erase endurance ⁽²⁾

(3)

−

times

Byte program time

160

1,500

µs

(program/erase endurance ≤ 1,000 times)

−

Byte program time

(program/erase endurance > 1,000 times)

−

0

−

300

0.2

0.3

1,500

µs

s

−

Block erase time

(program/erase endurance ≤ 1,000 times)

1

−

Block erase time

(program/erase endurance > 1,000 times)

s

td(SR-SUS)

Time delay from suspend request until

suspend

−

5+CPU clock

× 3 cycles

ms

µs

−

Interval from erase start/restart until

following suspend request

−

Time from suspend until erase restart

30+CPUclock

× 1 cycle

td(CMDRST-

READY)

Time from when command is forcibly

terminated until reading is enabled

30+CPUclock

× 1 cycle

−

Program, erase voltage

Read voltage

2.7

1.8

−

5.5

85

−

V

−20 ⁽⁷⁾

Program, erase temperature

°C

Data hold time ⁽⁸⁾

Ambient temperature = 55 °C

20

year

Notes:

1. VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte

writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further

reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the

number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. −40°C for D version.

8. The data hold time includes time that the power supply is off or the clock is not supplied.

Suspend request

(FMR21 bit)

FST7 bit

FST6 bit

Clock-dependent

Fixed time

time

Access restart

td(SR-SUS)

FST6, FST7: Bit in FST register

FMR21: Bit in FMR2 register

Figure 5.2

Time delay until Suspend

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5. Electrical Characteristics

Table 5.8

Voltage Detection 0 Circuit Electrical Characteristics

Standard

Unit

Symbol

Parameter

Condition

Min.

1.80

2.15

2.70

3.55

−

Typ.

1.90

2.35

2.85

3.80

6

Max.

2.05

2.50

3.05

4.05

150

Voltage detection level Vdet0_0 ⁽²⁾

Voltage detection level Vdet0_1 ⁽²⁾

Voltage detection level Vdet0_2 ⁽²⁾

Voltage detection level Vdet0_3 ⁽²⁾

Voltage detection 0 circuit response time ⁽⁴⁾

Vdet0

V

−

At the falling of Vcc from 5 V

µs

to (Vdet0_0 − 0.1) V

−

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit

operation starts ⁽³⁾

VCA25 = 1, VCC = 5.0 V

−

1.5

−

µA

µs

td(E-A)

−

100

Notes:

1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.

3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

register to 0.

4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.

Table 5.9

Voltage Detection 1 Circuit Electrical Characteristics

Standard

Typ.

2.20

2.35

2.50

2.65

2.80

2.95

3.10

3.25

3.40

3.55

3.70

3.85

4.00

4.15

4.30

4.45

0.07

Symbol

Parameter

Condition

Unit

Min.

2.00

2.15

2.30

2.45

2.60

2.75

2.85

3.00

3.15

3.30

3.45

3.60

3.75

3.90

4.05

4.20

−

Max.

2.40

2.55

2.70

2.85

3.00

3.15

3.40

3.55

3.70

3.85

4.00

4.15

4.30

4.45

4.60

4.75

−

Voltage detection level Vdet1_0 ⁽²⁾

Voltage detection level Vdet1_1 ⁽²⁾

Voltage detection level Vdet1_2 ⁽²⁾

Voltage detection level Vdet1_3 ⁽²⁾

Voltage detection level Vdet1_4 ⁽²⁾

Voltage detection level Vdet1_5 ⁽²⁾

Voltage detection level Vdet1_6 ⁽²⁾

Voltage detection level Vdet1_7 ⁽²⁾

Voltage detection level Vdet1_8 ⁽²⁾

Voltage detection level Vdet1_9 ⁽²⁾

Voltage detection level Vdet1_A ⁽²⁾

Voltage detection level Vdet1_B ⁽²⁾

Voltage detection level Vdet1_C ⁽²⁾

Voltage detection level Vdet1_D ⁽²⁾

Voltage detection level Vdet1_E ⁽²⁾

Voltage detection level Vdet1_F ⁽²⁾

Vdet1

At the falling of VCC

V

−

Hysteresis width at the rising of Vcc in voltage

detection 1 circuit

Vdet1_0 to Vdet1_5

selected

Vdet1_6 to Vdet1_F

selected

−

0.10

60

−

V

Voltage detection 1 circuit response time ⁽³⁾

At the falling of Vcc from

150

µs

5 V to (Vdet1_0 − 0.1) V

−

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit operation

starts ⁽⁴⁾

VCA26 = 1, VCC = 5.0 V

−

1.7

−

µA

µs

td(E-A)

−

100

Notes:

1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.

3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.

4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

register to 0.

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5. Electrical Characteristics

Table 5.10

Voltage Detection 2 Circuit Electrical Characteristics

Standard

Unit

Symbol

Parameter

Condition

Min.

3.70

−

Typ.

4.00

0.10

Max.

4.30

−

Vdet2

Voltage detection level Vdet2_0

At the falling of VCC

V

−

Hysteresis width at the rising of Vcc in voltage detection

2 circuit

Voltage detection 2 circuit response time ⁽²⁾

−

At the falling of Vcc from

−

20

150

µs

5 V to (Vdet2_0 − 0.1) V

−

Voltage detection circuit self power consumption

Waiting time until voltage detection circuit operation

starts ⁽³⁾

VCA27 = 1, VCC = 5.0 V

−

1.7

−

µA

µs

td(E-A)

−

100

Notes:

1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

register to 0.

(2)

Table 5.11

Power-on Reset Circuit

Standard

Symbol

Parameter

Condition

Unit

Min.

0

Typ.

Max.

50,000 mV/msec

(1)

trth

External power VCC rise gradient

−

Notes:

1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.

(1)

Vdet0

trth

External

Power VCC

0.5 V

(2)

Voltage detection 0

circuit response time

tw(por)

Internal

reset signal

1

× 32

fOCO-S

Notes:

1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit of User’s Manual: Hardware (REJ09B0570) for details.

2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable

a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain

tw(por) for 1 ms or more.

Figure 5.3

Power-on Reset Circuit Electrical Characteristics

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5. Electrical Characteristics

Table 5.12

High-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Typ.

Symbol

Parameter

Condition

Unit

Min.

38.4

Max.

41.6

−

High-speed on-chip oscillator frequency after

reset

VCC = 1.8 V to 5.5 V

−20°C ≤ Topr ≤ 85°C

40

MHz

VCC = 1.8 V to 5.5 V

−40°C ≤ Topr ≤ 85°C

38.0

35.389

35.020

30.72

30.40

40

42.0

MHz

High-speed on-chip oscillator frequency when

VCC = 1.8 V to 5.5 V

the FRA4 register correction value is written into −20°C ≤ Topr ≤ 85°C

36.864 38.338 MHz

36.864 38.707 MHz

the FRA1 register and the FRA5 register

correction value into the FRA3 register ⁽²⁾

VCC = 1.8 V to 5.5 V

−40°C ≤ Topr ≤ 85°C

High-speed on-chip oscillator frequency when

VCC = 1.8 V to 5.5 V

the FRA6 register correction value is written into −20°C ≤ Topr ≤ 85°C

32

33.28

33.60

MHz

the FRA1 register and the FRA7 register

correction value into the FRA3 register

VCC = 1.8 V to 5.5 V

−40°C ≤ Topr ≤ 85°C

−

Oscillation stability time

VCC = 5.0 V, Topr = 25°C

−

0.5

3

ms

Self power consumption at oscillation

400

−

µA

Notes:

1. VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in

UART mode.

Table 5.13

Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard

Typ.

125

Symbol

fOCO-S

Parameter

Condition

Unit

Min.

60

−

Max.

250

100

−

Low-speed on-chip oscillator frequency

Oscillation stability time

kHz

µs

−

VCC = 5.0 V, Topr = 25°C

30

Self power consumption at oscillation

−

2

µA

Note:

1. VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

Table 5.14

Power Supply Circuit Timing Characteristics

Standard

Symbol

Parameter

Condition

Unit

Min.

Typ.

Max.

td(P-R)

Time for internal power supply stabilization during

power-on⁽²⁾

−

2,000

µs

Notes:

1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25°C.

2. Waiting time until the internal power supply generation circuit stabilizes during power-on.

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5. Electrical Characteristics

(1)

Table 5.15

Timing Requirements of Synchronous Serial Communication Unit (SSU)

Standard

Symbol

Parameter

Conditions

Unit

Min.

Typ.

−

Max.

−

(2)

tSUCYC

tHI

SSCK clock cycle time

SSCK clock “H” width

SSCK clock “L” width

4

tCYC

0.4

−

0.6

1

tSUCYC

tLO

0.4

−

(2)

tRISE

SSCK clock rising

time

Master

Slave

−

tCYC

−

1

µs

(2)

tFALL

SSCK clock falling

time

Master

Slave

−

1

tCYC

−

100

−

1

µs

tSU

SSO, SSI data input setup time

SSO, SSI data input hold time

−

ns

(2)

tH

1

−

tCYC

tLEAD

Slave

1tCYC + 50

−

ns

SCS setup time

SCS hold time

tLAG

1tCYC + 50

−

(2)

tOD

tSA

SSO, SSI data output delay time

SSI slave access time

−

1

tCYC

2.7 V ≤ VCC ≤ 5.5 V

1.8 V ≤ VCC < 2.7 V

2.7 V ≤ VCC ≤ 5.5 V

1.8 V ≤ VCC < 2.7 V

1.5tCYC + 100

1.5tCYC + 200

1.5tCYC + 100

1.5tCYC + 200

ns

tOR

SSI slave out open time

Notes:

1. VCC = 1.8 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. 1tCYC = 1/f1(s)

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5. Electrical Characteristics

4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH

SCS (output)

VIL or VOL

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

4-Wire Bus Communication Mode, Master, CPHS = 0

VIL or VOL

SCS (output)

VIL or VOL

tHI

tFALL

tRISE

SSCK (output)

(CPOS = 1)

tLO

tHI

SSCK (output)

(CPOS = 0)

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

CPHS, CPOS: Bits in SSMR register

Figure 5.4

I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)

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5. Electrical Characteristics

4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH

VIL or VOL

SCS (input)

tHI

tFALL

tRISE

tLEAD

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

SSI (output)

tSU

tH

tSA

tOD

tOR

4-Wire Bus Communication Mode, Slave, CPHS = 0

VIH or VOH

SCS (input)

VIL or VOL

tHI

tFALL

tRISE

tLEAD

tLAG

SSCK (input)

(CPOS = 1)

tLO

tHI

SSCK (input)

(CPOS = 0)

tLO

tSUCYC

SSO (input)

tSU

tH

SSI (output)

tSA

tOD

tOR

CPHS, CPOS: Bits in SSMR register

Figure 5.5

I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)

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5. Electrical Characteristics

tHI

VIH or VOH

VIL or VOL

SSCK

tLO

tSUCYC

SSO (output)

SSI (input)

tOD

tSU

tH

Figure 5.6

I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous

Communication Mode)

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5. Electrical Characteristics

2

(1)

Table 5.16

Timing Requirements of I C bus Interface

Standard

Symbol

Parameter

SCL input cycle time

Condition

Unit

Min.

12t^CYC+ 600 ⁽²⁾

3t^CYC+ 300 ⁽²⁾

5t^CYC+ 500 ⁽²⁾

−

Typ.

−

Max.

−

t^SCL

ns

t^SCLH

t^SCLL

t^sf

SCL input “H” width

−

SCL input “L” width

−

SCL, SDA input fall time

−

300

(2)

t^SP

SCL, SDA input spike pulse rejection time

SDA input bus-free time

−

1tCYC

(2)

t^BUF

t^STAH

t^STAS

t^STOP

t^SDAS

t^SDAH

−

5t^CYC

(2)

Start condition input hold time

Retransmit start condition input setup time

Stop condition input setup time

Data input setup time

−

3t^CYC

(2)

−

3t^CYC

(2)

−

3t^CYC

1t^CYC+ 40 ⁽²⁾

10

−

Data input hold time

−

Notes:

1. VCC = 1.8 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. 1t^CYC= 1/f1(s)

VIH

SDA

VIL

tBUF

tSTAH

tSP

tSTOP

tSCLH

tSTAS

SCL

P⁽²⁾

S⁽¹⁾

tsf

Sr⁽³⁾

P⁽²⁾

tSCLL

tsr

tSDAS

tSCL

tSDAH

Notes:

1. Start condition

2. Stop condition

3. Retransmit start condition

2

Figure 5.7

I/O Timing of I C bus Interface

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5. Electrical Characteristics

Table 5.17

Electrical Characteristics (1) [4.2 V ≤ Vcc ≤ 5.5 V]

Standard

Unit

Symbol

Parameter

Condition

Min.

Drive capacity High VCC = 5 V IOH = −20 mA VCC − 2.0

Typ.

−

Max.

VCC

2.0

0.5

−

V^OH

Output

“H” voltage

Other than XOUT

V

Drive capacity Low V^CC= 5 V IOH = −5 mA

V^CC= 5 V IOH = −200 µA

VCC − 2.0

−

XOUT

1.0

−

V^OL

Output

“L” voltage

Other than XOUT

Drive capacity High VCC = 5 V IOL = 20 mA

Drive capacity Low V^CC= 5 V IOL = 5 mA

−

XOUT

V^CC= 5 V

IOL = 200 µA

−

V^T+-VT-

Hysteresis

0.1

1.2

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRCTRG, TRCCLK,

ADTRG,

RXD0, RXD1, RXD2,

CLK0, CLK1, CLK2,

SSI, SCL, SDA, SSO

0.1

1.2

−

V

RESET

I^IH

I^IL

Input “H” current

Input “L” current

VI = 5 V, VCC = 5.0 V

VI = 0 V, VCC = 5.0 V

−

5.0

−5.0

100

−

µA

R^PULLUPPull-up resistance

25

−

50

0.3

kΩ

MΩ

RfXIN

Feedback

resistance

XIN

RfXCIN

Feedback

resistance

XCIN

−

8

−

MΩ

VRAM

RAM hold voltage

During stop mode

1.8

−

V

Note:

1. 4.2 V ≤ VCC ≤ 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.

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5. Electrical Characteristics

Table 5.18

Electrical Characteristics (2) [3.3 V ≤ Vcc ≤ 5.5 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Standard

Typ.

6.5

Symbol

Parameter

Condition

Unit

mA

Min.

−

Max.

15

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 20 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN = 16 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

I^CC

Power supply

current

High-speed

clock mode

(VCC = 3.3 to 5.5 V)

Single-chip mode,

output pins are

open, other pins

are V^SS

−

5.3

3.6

3.0

2.2

1.5

7.0

3.0

1

12.5

−

mA

−

XIN clock off

High-speed

on-chip

oscillator mode

15

−

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

−

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-16

MSTIIC = MSTTRD = MSTTRC = 1

XIN clock off

Low-speed

on-chip

oscillator mode

Low-speed

clock mode

−

90

85

400

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

XIN clock off

−

47

15

4

−

100

90

−

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Wait mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral clock off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

3.5

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Stop mode

−

2.0

5.0

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

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R8C/33C Group

5. Electrical Characteristics

Timing Requirements

(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C)

Table 5.19

External Clock Input (XOUT, XCIN)

Standard

Unit

Symbol

Parameter

Min.

50

24

14

7

Max.

t^c(XOUT)

XOUT input cycle time

XOUT input “H” width

XOUT input “L” width

XCIN input cycle time

XCIN input “H” width

XCIN input “L” width

−

ns

µs

t^WH(XOUT)

t^WL(XOUT)

t^c(XCIN)

t^WH(XCIN)

t^WL(XCIN)

7

VCC = 5 V

tC(XOUT), tC(XCIN)

tWH(XOUT),

tWH(XCIN)

External Clock

Input

tWL(XOUT), tWL(XCIN)

Figure 5.8

External Clock Input Timing Diagram when VCC = 5 V

Table 5.20

TRAIO Input

Standard

Max.

Symbol

Parameter

Unit

Min.

100

40

t^c(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

t^WH(TRAIO)

t^WL(TRAIO)

40

tC(TRAIO)

VCC = 5 V

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.9

TRAIO Input Timing Diagram when VCC = 5 V

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5. Electrical Characteristics

Table 5.21

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

200

100

−

Max.

tc(CK)

CLKi input cycle time

CLKi input “H” width

CLKi input “L” width

TXDi output delay time

TXDi hold time

−

ns

tW(CKH)

tW(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

−

50

−

0

RXDi input setup time

RXDi input hold time

50

−

90

−

i = 0 to 2

VCC = 5 V

tC(CK)

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 to 2

Figure 5.10

Serial Interface Timing Diagram when VCC = 5 V

Table 5.22

External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)

Standard

Symbol

Parameter

Unit

Min.

Max.

250 ⁽¹⁾

250 ⁽²⁾

tW(INH)

tW(INL)

−

ns

INTi input “H” width, KIi input “H” width

INTi input “L” width, KIi input “L” width

−

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 5 V

INTi input

(i = 0, 1, 3)

tW(INL)

KIi input

(i = 0 to 3)

tW(INH)

Figure 5.11

Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when Vcc

= 5 V

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5. Electrical Characteristics

Table 5.23

Electrical Characteristics (3) [2.7 V ≤ Vcc < 4.2 V]

Standard

Unit

Symbol

Parameter

Condition

Min.

Typ.

−

Max.

VCC

0.5

−

VOH

Output “H” voltage Other than XOUT

Drive capacity High IOH = −5 mA

Drive capacity Low IOH = −1 mA

IOH = −200 µA

VCC − 0.5

V

VCC − 0.5

−

XOUT

1.0

−

VOL

Output “L” voltage Other than XOUT

Drive capacity High IOL = 5 mA

Drive capacity Low IOL = 1 mA

IOL = 200 µA

−

XOUT

−

VT+-VT-

Hysteresis

VCC = 3.0 V

0.1

0.4

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRCTRG, TRCCLK,

ADTRG,

RXD0, RXD1, RXD2,

CLK0, CLK1, CLK2,

SSI, SCL, SDA, SSO

VCC = 3.0 V

0.1

0.5

−

V

RESET

IIH

IIL

Input “H” current

Input “L” current

VI = 3 V, VCC = 3.0 V

VI = 0 V, VCC = 3.0 V

−

4.0

−4.0

168

−

µA

RPULLUP Pull-up resistance

42

−

84

0.3

kΩ

MΩ

RfXIN

Feedback

resistance

XIN

RfXCIN

Feedback

resistance

XCIN

−

8

−

MΩ

VRAM

Note:

RAM hold voltage

During stop mode

1.8

−

V

1. 2.7 V ≤ VCC < 4.2 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise

specified.

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R8C/33C Group

5. Electrical Characteristics

Table 5.24

Electrical Characteristics (4) [2.7 V ≤ Vcc < 3.3 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Standard

Typ.

3.5

Symbol

Parameter

Condition

Unit

mA

Min.

−

Max.

10

ICC

Power supply current High-speed XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

(VCC = 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are VSS

clock mode

Low-speed on-chip oscillator on = 125 kHz

No division

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

1.5

7.0

3.0

4.0

1.5

1

7.5

15

−

mA

High-speed XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

−

High-speed on-chip oscillator on fOCO-F = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

−

High-speed on-chip oscillator on fOCO-F = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

−

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-16

MSTIIC = MSTTRD = MSTTRC = 1

Low-speed XIN clock off

−

90

80

390

400

µA

High-speed on-chip oscillator off

on-chip

oscillator

mode

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

Low-speed XIN clock off

High-speed on-chip oscillator off

clock mode

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

XIN clock off

−

40

−

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

Wait mode

XIN clock off

−

15

4

90

80

−

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

XIN clock off

3.5

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral clock

off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

Stop mode

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

−

2.0

5.0

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

R01DS0008EJ0100 Rev 1.00

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R8C/33C Group

5. Electrical Characteristics

Timing requirements

(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C)

Table 5.25

External Clock Input (XOUT, XCIN)

Standard

Unit

Symbol

Parameter

Min.

50

24

14

7

Max.

tc(XOUT)

XOUT input cycle time

XOUT input “H” width

XOUT input “L” width

XCIN input cycle time

XCIN input “H” width

XCIN input “L” width

−

ns

µs

tWH(XOUT)

tWL(XOUT)

tc(XCIN)

tWH(XCIN)

tWL(XCIN)

7

tC(XOUT), tC(XCIN)

VCC = 3 V

tWH(XOUT),

tWH(XCIN)

External Clock Input

tWL(XOUT), tWL(XCIN)

Figure 5.12

External Clock Input Timing Diagram when VCC = 3 V

Table 5.26

TRAIO Input

Standard

Max.

Symbol

Parameter

Unit

Min.

300

120

tc(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

tWH(TRAIO)

tWL(TRAIO)

VCC = 3 V

tC(TRAIO)

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.13

TRAIO Input Timing Diagram when VCC = 3 V

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R8C/33C Group

5. Electrical Characteristics

Table 5.27

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

300

150

−

Max.

tc(CK)

CLKi input cycle time

CLKi input “H” width

CLKi Input “L” width

TXDi output delay time

TXDi hold time

−

ns

tW(CKH)

tW(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

−

80

−

0

RXDi input setup time

RXDi input hold time

70

−

90

−

i = 0 to 2

tC(CK)

VCC = 3 V

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 to 2

Figure 5.14

Serial Interface Timing Diagram when VCC = 3 V

Table 5.28

External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)

Standard

Symbol

Parameter

Unit

Min.

Max.

380 ⁽¹⁾

380 ⁽²⁾

tW(INH)

tW(INL)

−

ns

INTi input “H” width, KIi input “H” width

INTi input “L” width, KIi input “L” width

−

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 3 V

INTi input

(i = 0, 1, 3)

tW(INL)

KIi input

(i = 0 to 3)

tW(INH)

Figure 5.15

Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when Vcc

= 3 V

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 48 of 53

R8C/33C Group

5. Electrical Characteristics

Table 5.29

Electrical Characteristics (5) [1.8 V ≤ Vcc < 2.7 V]

Standard

Unit

Symbol

Parameter

Condition

Min.

Typ.

Max.

VCC

0.5

−

VOH

Output “H” voltage Other than XOUT

Drive capacity High IOH = −2 mA

Drive capacity Low IOH = −1 mA

IOH = −200 µA

VCC − 0.5

−

V

VCC − 0.5

XOUT

1.0

−

VOL

Output “L” voltage Other than XOUT

Drive capacity High IOL = 2 mA

Drive capacity Low IOL = 1 mA

IOL = 200 µA

−

XOUT

−

VT+-VT-

Hysteresis

0.05

0.20

INT0, INT1, INT3,

KI0, KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRCTRG, TRCCLK,

ADTRG,

RXD0, RXD1, RXD2,

CLK0, CLK1, CLK2,

SSI, SCL, SDA, SSO

0.05

0.2

−

V

RESET

IIH

IIL

Input “H” current

Input “L” current

VI = 2.2 V, VCC = 2.2 V

VI = 0 V, VCC = 2.2 V

−

4.0

−4.0

300

−

µA

RPULLUP Pull-up resistance

70

−

140

0.3

kΩ

MΩ

RfXIN

Feedback

resistance

XIN

RfXCIN

Feedback

resistance

XCIN

−

8

−

MΩ

VRAM

Note:

RAM hold voltage

During stop mode

1.8

−

V

1. 1.8 V ≤ VCC < 2.7 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 49 of 53

R8C/33C Group

5. Electrical Characteristics

Table 5.30

Electrical Characteristics (6) [1.8 V ≤ Vcc < 2.7 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Standard

Symbol

Parameter

Power supply current High-speed

Condition

Unit

mA

Min.

Typ.

2.2

Max.

ICC

XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

−

(VCC = 1.8 to 2.7 V)

Single-chip mode,

output pins are open,

other pins are VSS

clock mode

XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

−

0.8

2.5

1.7

1

−

10

−

mA

High-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 5 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

XIN clock off

High-speed on-chip oscillator on fOCO-F = 5 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

XIN clock off

−

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-16

MSTIIC = MSTTRD = MSTTRC = 1

Low-speed

on-chip

oscillator

mode

XIN clock off

−

90

80

300

350

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

Low-speed

clock mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

XIN clock off

−

40

15

4

−

90

80

−

µA

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

Wait mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

XIN clock off

3.5

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral

clock off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

Stop mode

XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

−

2.0

5.0

5

µA

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

−

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 50 of 53

R8C/33C Group

5. Electrical Characteristics

Timing requirements

(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C)

Table 5.31

External Clock Input (XOUT, XCIN)

Standard

Unit

Symbol

Parameter

Min.

200

90

14

7

Max.

tc(XOUT)

XOUT input cycle time

XOUT input “H” width

XOUT input “L” width

XCIN input cycle time

XCIN input “H” width

XCIN input “L” width

−

ns

µs

tWH(XOUT)

tWL(XOUT)

tc(XCIN)

tWH(XCIN)

tWL(XCIN)

7

tC(XOUT), tC(XCIN)

VCC = 2.2 V

tWH(XOUT),

tWH(XCIN)

External Clock Input

tWL(XOUT), tWL(XCIN)

Figure 5.16

External Clock Input Timing Diagram when VCC = 2.2 V

Table 5.32

TRAIO Input

Standard

Max.

Symbol

Parameter

Unit

Min.

500

200

tc(TRAIO)

TRAIO input cycle time

TRAIO input “H” width

TRAIO input “L” width

−

ns

tWH(TRAIO)

tWL(TRAIO)

−

tC(TRAIO)

VCC = 2.2 V

tWH(TRAIO)

TRAIO input

tWL(TRAIO)

Figure 5.17

TRAIO Input Timing Diagram when VCC = 2.2 V

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 51 of 53

R8C/33C Group

5. Electrical Characteristics

Table 5.33

Serial Interface

Standard

Unit

Symbol

Parameter

Min.

800

400

−

Max.

tc(CK)

CLKi input cycle time

CLKi input “H” width

CLKi input “L” width

TXDi output delay time

TXDi hold time

−

ns

tW(CKH)

tW(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

−

200

−

0

RXDi input setup time

RXDi input hold time

150

90

−

i = 0 to 2

VCC = 2.2 V

tC(CK)

tW(CKH)

CLKi

tW(CKL)

th(C-Q)

TXDi

RXDi

td(C-Q)

tsu(D-C)

th(C-D)

i = 0 to 2

Figure 5.18

Serial Interface Timing Diagram when VCC = 2.2 V

Table 5.34

External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)

Standard

Symbol

Parameter

Unit

Min.

Max.

1000 ⁽¹⁾

1000 ⁽²⁾

tW(INH)

tW(INL)

−

ns

INTi input “H” width, KIi input “H” width

INTi input “L” width, KIi input “L” width

−

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 2.2 V

INTi input

(i = 0, 1, 3)

tW(INL)

KIi input

(i = 0 to 3)

tW(INH)

Figure 5.19

Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when Vcc

= 2.2 V

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 52 of 53

R8C/33C Group

Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of

the Renesas Electronics website.

JEITA Package Code

P-LQFP32-7x7-0.80

RENESAS Code

PLQP0032GB-A

Previous Code

32P6U-A

MASS[Typ.]

0.2g

H_D

*1

D

24

17

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

16

25

bp

b₁

Dimension in Millimeters

Reference

Symbol

Min Nom Max

D

E

6.9 7.0 7.1

1.4

Terminal cross section

32

9

A₂

H_D

H_E

A

8.8 9.0 9.2

1.7

1

8

Z_D

Index mark

A₁

b_p

b₁

c

0.1 0.2

0

0.32 0.37 0.42

0.35

F

c

0.09

0.20

0.145

0.125

S

c₁

L

L₁

0°

8°

e

0.8

Detail F

y

S

x

0.20

0.10

*3

b_p

x

e

y

Z_D

Z_E

L

0.7

0.3 0.5 0.7

1.0

L₁

R01DS0008EJ0100 Rev 1.00

Aug. 24, 2010

Page 53 of 53

REVISION HISTORY

R8C/33C Group Datasheet

Description

Summary

Rev.

Date

Page

−

0.01

1.00

Sep. 01, 2009

Aug. 24, 2010

First Edition issued

All

4

“Preliminary” and “Under development” deleted

Table1.3 revised

26 to 52 “5. Electrical Characteristics” added

All trademarks and registered trademarks are the property of their respective owners.

C - 1

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to

be disclosed by Renesas Electronics such as that disclosed through our website.

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technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

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The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

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Colophon 1.0


型号：	R5F21335CNFP#30
厂家：	RENESAS TECHNOLOGY CORP
描述：	R5F21335CNFP#30 时钟外围集成电路
文件：	总56页 (文件大小：516K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F21335CNFP#30 [RENESAS]

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