R5F213NCTNBX [RENESAS]
Electronic household appliances, office equipment, audio equipment, consumer equipment; 电子家用电器,办公设备,音频设备,消费类设备型号: | R5F213NCTNBX |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Electronic household appliances, office equipment, audio equipment, consumer equipment |
文件: | 总58页 (文件大小:564K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
R8C/3NT Group
RENESAS MCU
R01DS0047EJ0100
Rev.1.00
Jan 25, 2011
1. Overview
1.1
Features
The R8C/3NT Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
A sensor control unit is also integrated, enabling detection of the floating capacitance of the electrostatic capacitive
touch electrode.
The R8C/3NT Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 1 of 55
R8C/3NT Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/3NT Group.
Table 1.1
Specifications for R8C/3NT Group (1)
Item
CPU
Function
Specification
Central processing R8C CPU core
unit
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM,
Data flash
Refer to Table 1.3 Product List for R8C/3NT Group
Power Supply Voltage detection
• Power-on reset
Voltage
Detection
circuit
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
I/O Ports
Clock
Programmable I/O • Input-only: 1 pin
ports
• CMOS I/O ports: 43, selectable pull-up resistor
• High current drive ports: 43
Clock generation
circuits
• 4 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupts
• Interrupt Vectors: 69
• External: 9 sources (INT × 5, key input × 4)
• Priority levels: 7 levels
Watchdog Timer
• 14 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
DTC (Data Transfer Controller)
• 1 channel
• Activation sources: 32
• Transfer modes: 2 (normal mode, repeat mode)
Timer
Timer RA
Timer RB
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait one-
shot generation mode
Timer RC
Timer RE
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 2 of 55
R8C/3NT Group
1. Overview
Table 1.2
Specifications for R8C/3NT Group (2)
Item
Function
Specification
Serial
Interface
UART0, UART1
UART2
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O, UART
4 circuits (shared with I2C bus)
Synchronous Serial
Communication Unit (SSU)
I2C bus
4 circuits (shared with SSU)
Sensor Control Unit
A/D Converter
System CH × 3, electrostatic capacitive touch detection × 5
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
Flash Memory
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance:10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function (data flash)
Operating Frequency/Supply
Voltage
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)
Current consumption
Typ. 7.0 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 4.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 2.0 µA (VCC = 3.0 V, stop mode)
Operating Ambient Temperature
Package
−20 to 85°C (N version)
48-pin WPP
Package code: SWBG0048LA-A
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 3 of 55
R8C/3NT Group
1. Overview
1.2
Product List
Table 1.3 lists Product List for R8C/3NT Group. Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/3NT Group.
Table 1.3
Product List for R8C/3NT Group
Current of Jan 2011
ROM Capacity
RAM
Capacity
Part No.
Package Type
Remarks
Program ROM
48 Kbytes
Data flash
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
1 Kbyte × 4
R5F213N7TNBX
R5F213N8TNBX
R5F213NATNBX
R5F213NCTNBX
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
SWBG0048LA-A N version
64 Kbytes
SWBG0048LA-A
SWBG0048LA-A
SWBG0048LA-A
96 Kbytes
128 Kbytes
Part No. R 5 F 21 3N C T N BX
Package type:
BX: WPP (Resin-coated bottom)
Classification
N: Operating ambient temperature −20°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/3NT Group
R8C/3x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/3NT Group
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 4 of 55
R8C/3NT Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows a Block Diagram.
8
8
5
1
8
6
8
Port P0
Port P1
Port P2
Port P3
Port P6
I/O ports
Port P4
Peripheral functions
UART or
System clock generation
circuit
clock synchronous serial I/O
Timers
(8 bits × 3)
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
XIN-XOUT
I2C bus or SSU
(8 bits × 4)
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Sensor control unit
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
Voltage detection circuit
DTC
A/D converter
(10 bits × 12 channels)
Memory
R8C CPU core
ROM (1)
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
R2
R3
RAM (2)
A0
A1
FB
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
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Jan 25, 2011
Page 5 of 55
R8C/3NT Group
1. Overview
1.4
Pin Assignment
Figure 1.3 shows Pin Assignment. Table 1.4 outlines the Pin Name Information by Pin Number.
TOP VIEW (Top View of Board)
*Solder Balls on Bottom Side
WPP Solder Ball Side
A2
B2
C2
D2
E2
F2
G2
2
A3
B3
C3
D3
E3
F3
G3
3
A4
B4
C4
D4
E4
F4
G4
4
A5
B5
C5
D5
E5
F5
G5
5
A6
B6
C6
D6
E6
F6
G6
6
A7
B7
C7
D7
E7
F7
G7
7
A7
B7
C7
D7
E7
F7
G7
7
A6
B6
C6
D6
E6
F6
G6
6
A5
B5
C5
D5
E5
F5
G5
5
A4
B4
C4
D4
E4
F4
G4
4
A3
B3
C3
D3
E3
F3
G3
3
A2
B2
C2
D2
E2
F2
G2
2
A
B
C
D
E
F
B1
C1
D1
E1
F1
G1
1
B1
C1
D1
E1
F1
G1
1
G
Figure 1.3
Pin Assignment
Pin
Number
Pin
Number
Pin Name
Pin Name
1
2
3
—
5
P2_6
VREF/P4_2
D
E
6
7
1
2
P2_5/SSO_1/SDA_1
P4_4(/XCOUT)
VSS/AVSS
P4_6/XIN
P2_4/SSCK_1/SCL_1
4
P0_3/AN4(/CLK1/TRCIOB)/CH0
P0_4/AN3/TREO(/TRCIOB)/CH1
A
5
6
VCC/AVCC
3
P1_0/KI0/AN8(/TRCIOD)
P3_5(/TRCIOD/CLK2)/SSCK_0/SCL_0
P6_3(/TXD1)/SSCK_3/SCL_3
P6_1/SCS_3
7
1
2
4
5
6
P1_5(/RXD0/TRAIO/INT1)
P2_1(/TRCIOC)
P2_3/SSI_1
3
7
P3_0(/TRAO/INT3)
P2_2(/TRCIOD)/SCS_1
P0_5/AN2(/TRCIOB)/CH2
P0_6/AN1(/TRCIOD)/CH3
B
4
5
P4_3(/XCIN)
1
2
P4_7/XOUT
P3_7(/RXD2/TXD2)/TRAO/SSO_0/SDA_0
6
7
1
2
3
4
5
6
P1_2/KI2/AN10(/TRCIOB)
P1_7/INT1(/TRAIO)
P3_4(/TRCIOC/RXD2/TXD2)/SSI_0
P0_0/AN7(/TRCIOA/TRCTRG)/CHxC
P6_4(/RXD1)/SSO_3/SDA_3
P6_2(/CLK1)/SSI_3
F
P6_5/INT4(/CLK2/CLK1/TRCIOB)/SSI_2
P6_7(/INT3/TRCIOD)/SSO_2/SDA_2
3
4
5
7
1
2
P2_0(/INT1/TRCIOB)
C
D
MODE
P0_7/AN0(/TRCIOC)/CH4
RESET
P1_1/KI1/AN9(/TRCIOA/TRCTRG)
P1_3/KI3/AN11/TRBO(/TRCIOC)
P1_6(/CLK0)/INT2
6
7
1
2
3
4
5
6
7
P3_3/INT3(/TRCCLK/CTS2/RTS2)/SCS_0
P2_7/SCS_2
G
P0_2/AN5/RXD1(/TRCIOA/TRCTRG)/CHxA
P4_5/INT0(/RXD2)/ADTRG
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)/CHxB
P6_6/INT2(/TXD2/TRCIOC)/SSCK_2/SCL_2
P3_1(/TRBO)
3
4
P6_0(/TREO/INT2)
P1_4(/TXD0/TRCCLK)
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 6 of 55
R8C/3NT Group
1. Overview
Table 1.4
Pin Name Information by Pin Number
I/O Pin Functions for Peripheral Modules
Pin Number
Control Pin Port
Serial
Interface
48-pin WPP
Pin Assignment
I2C bus
A/D
SCU
Interrupt
Timer
SSU
1
2
3
P4_2
VREF
(XCOUT)
VSS/AVSS
XIN
P4_4
P4_6
A
4
5
6
7
1
2
VCC/AVCC
P3_5
P6_3
(TRCIOD)
(TRAO)
(CLK2)
(TXD1)
SSCK_0 SCL_0
SSCK_3 SCL_3
P6_1
SCS_3
3
4
5
6
7
1
2
3
4
5
P3_0
P4_3
P4_7
P3_7
P3_4
P0_0
P6_4
P6_2
(INT3)
B
(XCIN)
XOUT
TRAO
(TRCIOC)
(RXD2/TXD2)
(RXD2/TXD2)
SSO_0 SDA_0
SSI_0
(TRCIOA/TRCTRG)
AN7
CHxC
(RXD1)
(CLK1)
SSO_3 SDA_3
SSI_3
MODE
C
D
E
RESET
6
P3_3
INT3
(TRCCLK)
(CTS2/RTS2)
SCS_0
SCS_2
7
1
2
3
4
5
6
7
1
2
3
P2_7
P0_2
P0_1
(TRCIOA/TRCTRG)
(TRCIOA/TRCTRG)
RXD1
AN5
AN6
CHxA
CHxB
(TXD1)
P6_0
P1_4
P2_6
P2_5
P2_4
P0_3
P0_4
(INT2)
(TREO)
(TRCCLK)
(TXD0)
SSO_1 SDA_1
SSCK_1 SCL_1
(TRCIOB)
(CLK1)
(RXD0)
AN4
AN3
CH0
CH1
TREO(/TRCIOB)
P1_0
KI0
(TRCIOD)
AN8
4
5
6
7
1
2
3
P1_5
P2_1
P2_3
(INT1)
(TRAIO)
(TRCIOC)
SSI_1
P2_2
P0_5
P0_6
(TRCIOD)
(TRCIOB)
(TRCIOD)
SCS_1
AN2
AN1
CH2
CH3
P1_2
P1_7
P6_5
P6_7
KI2
(TRCIOB)
(TRAIO)
AN10
4
5
6
7
1
2
3
4
5
6
7
INT1
F
INT4
(TRCIOB)
(TRCIOD)
(CLK1/CLK2)
SSI_2
(INT3)
(INT1)
SSO_2 SDA_2
P2_0
P0_7
(TRCIOB)
(TRCIOC)
AN0
AN9
CH4
P1_1
P1_3
P1_6
P4_5
KI1
KI3
(TRCIOA/TRCTRG)
TRBO(/TRCIOC)
AN11
G
(INT2)
INT0
INT2
(CLK0)
(RXD2)
(TXD2)
ADTRG
P6_6
P3_1
(TRCIOC)
(TRBO)
SSCK_2 SCL_2
Note:
1. Can be assigned to the pin in parentheses by a program.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 7 of 55
R8C/3NT Group
1. Overview
1.5
Pin Functions
Tables 1.5 and 1.6 list Pin Functions.
Table 1.5
Item
Pin Functions (1)
Pin Name
I/O Type
—
Description
Power supply input VCC, VSS
Apply 1.8 to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
—
I
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
Input “L” on this pin resets the MCU.
Connect this pin to VCC via a resistor.
RESET
MODE
XIN
MODE
I
I
XIN clock input
XIN clock output
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins. (1)
XOUT
I/O
To use an external clock, input it to the XOUT pin and leave
the XIN pin open.
XCIN clock input
XCIN
I
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins. (1)
XCIN clock output XCOUT
O
To use an external clock, input it to the XCIN pin and leave
the XCOUT pin open.
I
I
INT interrupt input INT0 to INT4
INT interrupt input pins.
Key input interrupt
Timer RA
Key input interrupt input pins.
KI0 to KI3
TRAIO
I/O
O
O
I
Timer RA I/O pin.
TRAO
Timer RA output pin.
Timer RB output pin.
External clock input pin.
External trigger input pin.
Timer RC I/O pins.
Timer RB
Timer RC
TRBO
TRCCLK
TRCTRG
I
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RE
TREO
O
I/O
I
Divided clock output pin.
Transfer clock I/O pins.
Serial data input pins.
Serial interface
CLK0, CLK1, CLK2
RXD0, RXD1, RXD2
TXD0, TXD1, TXD2
O
I
Serial data output pins.
Transmission control input pin.
CTS2
RTS2
O
Reception control output pin.
I: Input
Note:
O: Output
I/O: Input and output
1. Refer to the oscillator manufacturer for oscillation characteristics.
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Jan 25, 2011
Page 8 of 55
R8C/3NT Group
1. Overview
Table 1.6
Pin Functions (2)
Item
SSU
Pin Name
SSI_i
I/O Type
I/O
Description
Data I/O pin.
I/O
Chip-select signal I/O pin.
SCS_i
SSCK_i
SSO_i
SCL_i
SDA_i
I/O
I/O
I/O
I/O
I
Clock I/O pin.
Data I/O pin.
I2C bus
Clock I/O pin
Data I/O pin
Reference voltage VREF
Reference voltage input pin to A/D converter.
input
A/D converter
AN0 to AN11
ADTRG
I
I
Analog input pins to A/D converter.
AD external trigger input pin.
Sensor control unit CHxA, CHxB, CHxC
CH0 to CH4
I/O
I
Control pins for electrostatic capacitive touch detection
Electrostatic capacitive touch detection pins
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_7,
P6_0 to P6_7
I/O
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Input port
i = 0 to 3
P4_2
I
Input-only port.
I: Input
O: Output
I/O: Input and output
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Jan 25, 2011
Page 9 of 55
R8C/3NT Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R2
R3
Data registers (1)
R3
A0
Address registers (1)
A1
FB
Frame base register (1)
b19
b15
b0
b0
Interrupt table register
Program counter
INTBH
INTBL
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
PC
b15
b0
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b15
b0
b0
Flag register
FLG
b15
b8
b7
IPL
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
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Jan 25, 2011
Page 10 of 55
R8C/3NT Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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Jan 25, 2011
Page 11 of 55
R8C/3NT Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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Jan 25, 2011
Page 12 of 55
R8C/3NT Group
3. Memory
3. Memory
3.1
R8C/3NT Group
Figure 3.1 is a Memory Map of R8C/3NT Group. The R8C/3NT Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with
address 0FFFFh. For example, a 64-Kbyte internal ROM area is allocated addresses 04000h to 13FFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal
RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces
within the SFRs are reserved and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0FFD8h
0XXXXh
Reserved area
02C00h
SFR (2)
(Refer to 4. Special Function
0FFDCh
Undefined instruction
Registers (SFRs))
02FFFh
03000h
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.
3. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Internal RAM
Part Number
Size
Address 0YYYYh Address ZZZZZh
Size
Address 0XXXXh
013FFh
R5F213N7TNBX
R5F213N8TNBX
R5F213NATNBX
R5F213NCTNBX
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
04000h
04000h
04000h
04000h
–
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
13FFFh
1BFFFh
23FFFh
01BFFh
023FFh
02BFFh
Figure 3.1
Memory Map of R8C/3NT Group
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 13 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.14 list the special
function registers. Table 4.15 lists the ID Code Areas and Option Function Select Area.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
PM0
PM1
CM0
CM1
00h
00h
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
00101000b
00100000b
00h
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
(2)
0XXXXXXXb
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
CSPR
When shipping
Count Source Protection Mode Register
00h
(3)
10000000b
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
Clock Prescaler Reset Flag
CPSRF
FRA4
FRA5
FRA6
00h
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
When shipping
When shipping
When shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
(4)
00h
(5)
00100000b
0035h
0036h
0037h
0038h
Voltage Detection 1 Level Select Register
Voltage Monitor 0 Circuit Control Register
VD1LS
VW0C
00000111b
(4)
1100X010b
(5)
1100X011b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
10001010b
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer
reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 14 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.2
SFR Information (2)
Address
Register
Symbol
After Reset
10000010b
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Voltage Monitor 2 Circuit Control Register
VW2C
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
INT4 Interrupt Control Register
Timer RC Interrupt Control Register
INT4IC
TRCIC
XX00X000b
XXXXX000b
Timer RE Interrupt Control Register
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSU0IC/IIC0IC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU0 Interrupt Control Register/IIC0 bus Interrupt Control Register
(2)
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RA Interrupt Control Register
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
Sensor Control Unit Interrupt Control Register
SCUIC
XXXXX000b
Voltage Monitor 1 Interrupt Control Register
Voltage Monitor 2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
(2)
(2)
(2)
SSU1IC/IIC1IC
SSU2IC/IIC2IC
SSU3IC/IIC3IC
XXXXX000b
XXXXX000b
XXXXX000b
SSU1 Interrupt Control Register/IIC1 bus Interrupt Control Register
SSU2 Interrupt Control Register/IIC2 bus Interrupt Control Register
SSU3 Interrupt Control Register/IIC3 bus Interrupt Control Register
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by IIC0SEL, IIC1SEL, IIC2SEL, and IIC3SEL bits in the SSUIICSR register.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 15 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.3
SFR Information (3)
Address
Register
Symbol
DTCTL
After Reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
DTC Activation Control Register
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTC Activation Enable Register 4
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
00h
00h
00h
00h
00h
00h
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
XXh
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
00001000b
00000010b
XXh
XXh
00h
UART2 Digital Filter Function Select Register
URXDF
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 16 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.4
SFR Information (4)
Address
Register
Symbol
After Reset
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
A/D Register 0
A/D Register 1
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
000000XXb
A/D Mode Register
ADMOD
ADINSEL
ADCON0
ADCON1
00h
11000000b
00h
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
P0
P1
PD0
PD1
P2
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
Port P4 Direction Register
Port P6 Register
PD4
P6
00h
XXh
00h
Port P6 Direction Register
PD6
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 17 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.5
SFR Information (5)
Address
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
After Reset
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
00h
00h
00h
FFh
FFh
Timer RB Control Register
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
00h
FFh
FFh
FFh
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
00001000b
Timer RC Mode Register
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
01001000b
00h
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Timer RC General Register A
Timer RC General Register B
Timer RC General Register C
Timer RC General Register D
TRCGRA
TRCGRB
TRCGRC
TRCGRD
FFh
Timer RC Control Register 2
TRCCR2
TRCDF
TRCOER
TRCADCR
00011000b
00h
01111111b
00h
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 18 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.6
SFR Information (6)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
Register
Symbol
After Reset
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 19 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.7
SFR Information (7)
Address
Register
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
After Reset
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Timer RA Pin Select Register
Timer RB/RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
00h
00h
00h
00h
Timer Pin Select Register
TIMSR
00h
UART0 Pin Select Register
UART1 Pin Select Register
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU/IIC Pin Select Register
U0SR
U1SR
U2SR0
U2SR1
SSUIICSR
LVMR1
INTSR
PINSR
LVMR
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
F8h
FFh
FFh
FFh
FFh
00h
Low-Voltage Signal Mode Control Register 1
INT Interrupt Input Pin Select Register
I/O Function Pin Select Register
Low-Voltage Signal Mode Control Register
I/O Function Pin Select Register 1
PINSR1
PINSR2
SS0BR
I/O Function Pin Select Register 2
SS0 Bit Counter Register
(2)
SS0TDR / IC0DRT
SS0TDRH
SS0RDR / IC0DRR
SS0RDRH
SS0CRH / IC0CR1
SS0CRL / IC0CR2
SS0MR / IC0MR
SS0ER / IC0IER
SS0SR / IC0SR
SS0MR2 / SAR
SS0 Transmit Data Register L / IIC_0 bus Transmit Data Register
(2)
SS0 Transmit Data Register H
(2)
SS0 Receive Data Register L / IIC_0 bus Receive Data Register
(2)
SS0 Receive Data Register H
(2)
SS0 Control Register H / IIC_0 bus Control Register 1
SS0 Control Register L / IIC_0 bus Control Register 2
SS0 Mode Register / IIC_0 bus Mode Register
SS0 Enable Register / IIC_0 bus Interrupt Enable Register
SS0 Status Register / IIC_0 bus Status Register
SS0 Mode Register 2 / Slave Address Register
(2)
01111101b
00010000b / 00011000b
(2)
(2)
00h
(2)
00h / 0000X000b
00h
(2)
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
00h
00h
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IIC0SEL bit in the SSUIICSR register.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 20 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.8
SFR Information (8)
Address
Register
Symbol
RMAD0
After Reset
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Address Match Interrupt Register 0
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
Address Match Interrupt Enable Register 1
AIER1
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
00h
00h
Port P1 Drive Capacity Control Register
Port P2 Drive Capacity Control Register
Drive Capacity Control Register 0
Drive Capacity Control Register 1
P1DRR
P2DRR
DRR0
00h
00h
00h
00h
DRR1
Input Threshold Control Register 0
Input Threshold Control Register 1
VLT0
VLT1
00h
00h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
Key Input Enable Register 0
INTEN
INTEN1
INTF
INTF1
KIEN
00h
00h
00h
00h
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 21 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.9
SFR Information (9)
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
Register
Symbol
After Reset
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
SS1 Bit Counter Register
SS1 Transmit Data Register L / IIC_1 bus Transmit Data Register
SS1 Transmit Data Register H
SS1 Receive Data Register L / IIC_1 bus Receive Data Register
SS1 Receive Data Register H
SS1 Control Register H / IIC_1 bus Control Register 1
SS1 Control Register L / IIC_1 bus Control Register 2
SS1 Mode Register / IIC1 bus Mode Register
SS1BR
SS1TDR/IC1DRT
SS1TDRH
SS1RDR/IC1DRR
SS1RDRH
SS1CRH/IC1CR1
SS1CRL/IC1CR2
SS1MR/IC1MR
SS1ER/IC1IER
SS1SR/IC1SR
SS1MR2/SAR1
F8h
FFh
FFh
FFh
FFh
00h
(2)
(2)
(2)
(2)
(2)
(2)
01111101b
00010000b/00011000b
00h
00h/0000X000b
00h
(2)
(2)
SS1 Enable Register / IIC_1 bus Interrupt Enable Register
SS1 Status Register / IIC_1 bus Status Register
SS1 Mode Register 2 / Slave Address Register
(2)
(2)
SS2 Bit Counter Register
SS2 Transmit Data Register L / IIC_2 bus Transmit Data Register
SS2 Transmit Data Register H
SS2 Receive Data Register L / IIC_2 bus Receive Data Register
SS2 Receive Data Register H
SS2 Control Register H / IIC_2 bus Control Register 1
SS2 Control Register L / IIC_2 bus Control Register 2
SS2 Mode Register / IIC_2 bus Mode Register
SS2BR
SS2TDR/IC2DRT
SS2TDRH
SS2RDR/IC2DRR
SS2RDRH
SS2CRH/IC2CR1
SS2CRL/IC2CR2
SS2MR/IC2MR
SS2ER/IC2IER
SS2SR/IC2SR
SS2MR2/SAR2
F8h
FFh
FFh
FFh
FFh
00h
(3)
(3)
(3)
(3)
(3)
(3)
01111101b
00010000b/00011000b
00h
00h/0000X000b
00h
(3)
(3)
SS2 Enable Register / IIC_2 bus Interrupt Enable Register
SS2 Status Register / IIC_2 bus Status Register
SS2 Mode Register 2 / Slave Address Register
(3)
(3)
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IIC1SEL bit in the SSUIICSR register.
3. Selectable by the IIC2SEL bit in the SSUIICSR register.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 22 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.10
SFR Information (10)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
Register
Symbol
After Reset
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
SS3 Bit Counter Register
SS3 Transmit Data Register L / IIC_3 bus Transmit Data Register
SS3 Transmit Data Register H
SS3 Receive Data Register L / IIC_3 bus Receive Data Register
SS3 Receive Data Register H
SS3 Control Register H / IIC_3 bus Control Register 1
SS3 Control Register L / IIC_3 bus Control Register 2
SS3 Mode Register / IIC_3 bus Mode Register
SS3BR
SS3TDR/IC3DRT
SS3TDRH
SS3RDR/IC3DRR
SS3RDRH
SS3CRH/IC3CR1
SS3CRL/IC3CR2
SS3MR/IC3MR
SS3ER/IC3IER
SS3SR/IC3SR
SS3MR2/SAR3
F8h
FFh
FFh
FFh
FFh
00h
(2)
(2)
(2)
(2)
(2)
(2)
01111101b
00010000b/00011000b
00h
00h/0000X000b
00h
(2)
(2)
SS3 Enable Register / IIC_3 bus Interrupt Enable Register
SS3 Status Register / IIC_3 bus Status Register
SS3 Mode Register 2 / Slave Address Register
(2)
(2)
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IIC3SEL bit in the SSUIICSR register.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 23 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.11
SFR Information (9)
Address
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
:
Register
Symbol
SCUCR0
After Reset
SCU Control Register 0
SCU Mode Register
00h
00h
SCUMR
SCTCR0
SCTCR1
SCTCR2
SCTCR3
SCHCR
SCUCHC
SCUFR
SCUSTC
SCSCSR
SCUSCC
SCU Timing Control Register 0
SCU Timing Control Register 1
SCU Timing Control Register 2
SCU Timing Control Register 3
SCU Channel Control Register
SCU Channel Control Counter
SCU Flag Register
00000011b
00000001b
00010000b
00h
00h
00h
00h
00h
SCU Status Counter
SCU Secondary Counter Set Register
SCU Secondary Counter
00000111b
00000111b
SCU Destination Address Register
SCU Data Buffer Register
SCU Primary Counter
SCUDAR
SCUDBR
SCUPRC
00h
00001100b
00h
00h
00h
00h
Touch Sensor Input Enable Register 0
TSIER0
00h
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
XXh
XXh
XXh
XXh
XXh
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Control Data 0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
DTCD0
DTC Control Data 1
DTCD1
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 24 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.12
SFR Information (10)
Address
Register
Symbol
DTCD2
After Reset
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
DTC Control Data 2
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 3
DTCD3
DTCD4
DTCD5
DTCD6
DTCD7
DTCD8
DTCD9
DTC Control Data 4
DTC Control Data 5
DTC Control Data 6
DTC Control Data 7
DTC Control Data 8
DTC Control Data 9
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 25 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.13
SFR Information (11)
Address
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
Register
Symbol
DTCD10
After Reset
DTC Control Data 10
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 11
DTC Control Data 12
DTC Control Data 13
DTC Control Data 14
DTC Control Data 15
DTC Control Data 16
DTC Control Data 17
DTCD11
DTCD12
DTCD13
DTCD14
DTCD15
DTCD16
DTCD17
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 26 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
(1)
Table 4.14
SFR Information (12)
Address
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
:
Register
Symbol
DTCD18
After Reset
DTC Control Data 18
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DTC Control Data 19
DTC Control Data 20
DTC Control Data 21
DTC Control Data 22
DTC Control Data 23
DTCD19
DTCD20
DTCD21
DTCD22
DTCD23
2FFFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 27 of 55
R8C/3NT Group
4. Special Function Registers (SFRs)
Table 4.15
ID Code Areas and Option Function Select Area
Address
Area Name
Symbol
After Reset
(Note 1)
:
FFDBh
Option Function Select Register 2
OFS2
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
ID1
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 1)
ID2
ID3
ID4
ID5
ID6
ID7
Option Function Select Register
OFS
Notes:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 28 of 55
R8C/3NT Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated Value
−0.3 to 6.5
Unit
V
VCC/AVCC Supply voltage
VI
Input voltage
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
500
V
VO
Pd
Output voltage
V
Power dissipation
−20°C ≤ Topr ≤ 85°C
mW
°C
°C
Topr
Tstg
Operating ambient temperature
Storage temperature
−20 to 85 (N version)
−65 to 150
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 29 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.2
Recommended Operating Conditions (1)
Standard
Unit
Symbol
Parameter
Conditions
Min.
1.8
Typ.
—
0
Max.
5.5
VCC/AVCC Supply voltage
VSS/AVSS Supply voltage
VIH Input “H” voltage Other than CMOS input
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
—
—
0.8 VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VCC
CMOS Inputlevel Input level selection: 4.0 V ≤ VCC ≤ 5.5 V 0.5 VCC
VCC
input
switching 0.35 VCC
function
(I/O port)
2.7 V ≤ VCC < 4.0 V 0.55 VCC
1.8 V ≤ VCC < 2.7 V 0.65 VCC
VCC
VCC
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V 0.65 VCC
VCC
0.5 VCC
2.7 V ≤ VCC < 4.0 V 0.7 VCC
1.8 V ≤ VCC < 2.7 V 0.8 VCC
VCC
VCC
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V 0.85 VCC
VCC
0.7 VCC
2.7 V ≤ VCC < 4.0 V 0.85 VCC
VCC
1.8 V ≤ VCC < 2.7 V 0.85 VCC
VCC
External clock input (XOUT)
1.2
0
VCC
VIL
Input “L” voltage Other than CMOS input
0.2 VCC
0.2 VCC
0.2 VCC
0.2 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.55 VCC
0.45 VCC
0.35 VCC
0.4
CMOS Inputlevel Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
0
0
input
switching 0.35 VCC
function
(I/O port)
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
0
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
0
0.5 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
0
0
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
0
0.7 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
0
0
External clock input (XOUT)
0
IOH(sum)
IOH(sum)
IOH(peak)
Peak sum output “H”
Sum of all pins IOH(peak)
—
−160
current
Average sum output “H”
current
Sum of all pins IOH(avg)
—
—
−80
mA
Peak output “H” current
Drive capacity Low
Drive capacity High
Drive capacity Low
Drive capacity High
Sum of all pins IOL(peak)
—
—
—
—
—
—
—
—
—
—
−10
−40
−5
mA
mA
mA
mA
mA
IOH(avg)
Average output “H”
current
−20
160
IOL(sum)
IOL(sum)
IOL(peak)
Peak sum output “L”
current
Average sum output “L”
current
Sum of all pins IOL(avg)
—
—
80
mA
Peak output “L” current
Drive capacity Low
Drive capacity High
Drive capacity Low
Drive capacity High
—
—
—
—
—
—
—
32
—
—
—
—
—
—
—
—
10
40
5
mA
mA
IOL(avg)
f(XIN)
Average output “L”
current
—
mA
—
20
20
5
mA
XIN clock input oscillation frequency
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.8 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
—
MHz
MHz
kHz
—
f(XCIN)
XCIN clock input oscillation frequency
When used as the count source for timer RC (3)
fOCO-F frequency
32.768
—
50
40
20
5
fOCO40M
fOCO-F
MHz
MHz
MHz
MHz
MHz
MHz
MHz
—
—
—
System clock frequency
CPU clock frequency
—
20
5
—
f(BCLK)
—
20
5
—
Notes:
1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 to 5.5 V.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 30 of 55
R8C/3NT Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
P6
10 pF
Figure 5.1
Ports P0 to P4, P6 Timing Measurement Circuit
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 31 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.3
A/D Converter Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min.
—
Typ.
—
Max.
10
—
—
Resolution
Vref = AVCC
Bit
Absolute accuracy
10-bit mode Vref = AVCC = 5.0 V AN0 to AN7 input,
AN8 to AN11 input
—
—
±3
LSB
Vref = AVCC = 3.3 V AN0 to AN7 input,
AN8 to AN11 input
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±5
±5
±5
±2
±2
±2
±2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Vref = AVCC = 3.0 V AN0 to AN7 input,
AN8 to AN11 input
Vref = AVCC = 2.2 V AN0 to AN7 input,
AN8 to AN11 input
8-bit mode
Vref = AVCC = 5.0 V AN0 to AN7 input,
AN8 to AN11 input
Vref = AVCC = 3.3 V AN0 to AN7 input,
AN8 to AN11 input
Vref = AVCC = 3.0 V AN0 to AN7 input,
AN8 to AN11 input
Vref = AVCC = 2.2 V AN0 to AN7 input,
AN8 to AN11 input
4.0 V ≤ Vref = AVCC ≤ 5.5 V (2)
3.2 V ≤ Vref = AVCC ≤ 5.5 V (2)
2.7 V ≤ Vref = AVCC ≤ 5.5 V (2)
2.2 V ≤ Vref = AVCC ≤ 5.5 V (2)
φAD
A/D conversion clock
2
2
2
2
—
—
—
—
3
20
16
10
5
MHz
MHz
MHz
MHz
kΩ
µs
—
Tolerance level impedance
Conversion time
tCONV
10-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz
2.2
2.2
0.8
—
—
—
—
45
—
—
1.34
—
—
8-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
φAD = 20 MHz
µs
tSAMP
IVref
Vref
Sampling time
—
µs
Vref current
VCC = 5.0 V, XIN = f1 = φAD = 20 MHz
—
µA
V
Reference voltage
Analog input voltage (3)
2.2
0
AVCC
Vref
1.49
VIA
V
OCVREF On-chip reference voltage
2 MHz ≤ φAD ≤ 4 MHz
1.19
V
Notes:
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-current-
consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
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Page 32 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.4
Flash Memory (Program ROM) Electrical Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min.
1,000 (3)
—
Typ.
—
Max.
—
Program/erase endurance (2)
Byte program time
—
—
—
times
µs
80
TBD
TBD
Block erase time
—
0.3
—
s
td(SR-SUS) Time delay from suspend request until
suspend
—
5 + CPU clock
× 3 cycles
ms
—
Interval from erase start/restart until
following suspend request
0
—
−
—
—
−
—
µs
µs
µs
—
Time from suspend until erase restart
30 + CPU clock
× 1 cycle
td(CMDRST Time from when command is forcibly
-READY)
30 + CPU clock
× 1 cycle
stopped until reading is enabled
—
—
—
—
Program, erase voltage
Read voltage
2.7
1.8
0
—
—
—
—
5.5
5.5
60
—
V
V
Program, erase temperature
Data hold time (7)
°C
Ambient temperature = 55 °C
20
year
Notes:
1. VCC = 2.7 to 5.5 V and Topr = 0 to 60 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
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Page 33 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.5
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Standard
Typ.
Symbol
Parameter
Conditions
Unit
Min.
10,000 (3)
—
Max.
—
Program/erase endurance (2)
—
—
—
times
Byte program time
160
TBD
µs
(program/erase endurance ≤ 1,000 times)
—
—
—
Byte program time
(program/erase endurance > 1,000 times)
—
—
—
—
0
300
0.2
0.3
TBD
µs
s
Block erase time
(program/erase endurance ≤ 1,000 times)
1
1
Block erase time
(program/erase endurance > 1,000 times)
s
td(SR-SUS) Time delay from suspend request until
suspend
—
—
—
−
5 + CPU clock
× 3 cycles
ms
µs
µs
µs
—
Interval from erase start/restart until
following suspend request
—
—
Time from suspend until erase restart
—
−
30 + CPU clock
× 1 cycle
td(CMDRST Time from when command is forcibly
-READY)
30 + CPU clock
× 1 cycle
stopped until reading is enabled
—
—
—
—
Program, erase voltage
Read voltage
2.7
1.8
−20
20
—
—
—
—
5.5
5.5
85
—
V
V
Program, erase temperature
Data hold time (7)
°C
Ambient temperature = 55 °C
year
Notes:
1. VCC = 2.7 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Clock-dependent
Fixed time
time
Access restart
td(SR-SUS)
FST6, FST7: Bit in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
R01DS0047EJ0100 Rev.1.00
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Page 34 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.6
Voltage Detection 0 Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Condition
Min.
TBD
TBD
TBD
TBD
—
Typ.
1.90
2.35
2.85
3.80
6
Max.
TBD
TBD
TBD
TBD
TBD
Voltage detection level Vdet0_0 (2)
Voltage detection level Vdet0_1 (2)
Voltage detection level Vdet0_2 (2)
Voltage detection level Vdet0_3 (2)
Voltage detection 0 circuit response time (4)
Vdet0
V
V
V
V
—
At the falling of VCC from
µs
5.0 V to (Vdet0_0 − 0.1) V
—
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts (3)
VCA25 = 1, VCC = 5.0 V
—
—
1.5
—
—
µA
µs
td(E-A)
TBD
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version).
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.7
Voltage Detection 1 Circuit Electrical Characteristics
Standard
Typ.
2.20
2.35
2.50
2.65
2.80
2.95
3.10
3.25
3.40
3.55
3.70
3.85
4.00
4.15
4.30
4.45
0.07
Symbol
Vdet1
Parameter
Condition
Unit
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
Max.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
Voltage detection level Vdet1_0 (2)
Voltage detection level Vdet1_1 (2)
Voltage detection level Vdet1_2 (2)
Voltage detection level Vdet1_3 (2)
Voltage detection level Vdet1_4 (2)
Voltage detection level Vdet1_5 (2)
Voltage detection level Vdet1_6 (2)
Voltage detection level Vdet1_7 (2)
Voltage detection level Vdet1_8 (2)
Voltage detection level Vdet1_9 (2)
Voltage detection level Vdet1_A (2)
Voltage detection level Vdet1_B (2)
Voltage detection level Vdet1_C (2)
Voltage detection level Vdet1_D (2)
Voltage detection level Vdet1_E (2)
Voltage detection level Vdet1_F (2)
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
At the falling of VCC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
—
—
Hysteresis width at the rising of VCC in voltage
detection 1 circuit
Vdet1_0 to Vdet1_5
selected
Vdet1_6 to Vdet1_F
selected
—
—
0.10
60
—
V
Voltage detection 1 circuit response time (3)
At the falling of VCC from
TBD
µs
5.0 V to (Vdet1_0 − 0.1) V
—
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts (4)
VCA26 = 1, VCC = 5.0 V
—
—
1.7
—
—
µA
µs
td(E-A)
TBD
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version).
2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
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Jan 25, 2011
Page 35 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.8
Voltage Detection 2 Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Condition
Min.
TBD
—
Typ.
4.00
0.10
Max.
TBD
—
Vdet2
—
Voltage detection level Vdet2_0
At the falling of VCC
V
V
Hysteresis width at the rising of VCC in voltage
detection 2 circuit
Voltage detection 2 circuit response time (2)
—
At the falling of VCC from
—
20
150
µs
5.0 V to (Vdet2_0 − 0.1) V
—
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts (3)
VCA27 = 1, VCC = 5.0 V
—
—
1.7
—
—
µA
µs
td(E-A)
100
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
(2)
Table 5.9
Power-on Reset Circuit
Standard
Typ.
Symbol
Parameter
Condition
Unit
Min.
0
Max.
50,000 mV/msec
(1)
trth
Notes:
1. The measurement condition is Topr = −20 to 85 °C (N version), unless otherwise specified.
External power VCC rise gradient
—
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
(1)
(1)
Vdet0
Vdet0
trth
trth
External
Power VCC
0.5 V
(2)
Voltage detection 0
circuit response time
tw(por)
Internal
reset signal
1
1
× 32
× 32
fOCO-S
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
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Jan 25, 2011
Page 36 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.10
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Typ.
Symbol
Parameter
Condition
Unit
Min.
—
Max.
—
—
High-speed on-chip oscillator frequency after
reset
VCC = 5.0 V, Topr = 25 °C
40
MHz
High-speed on-chip oscillator frequency when the VCC = 5.0 V, Topr = 25 °C
FRA4 register correction value is written into the
FRA1 register and the FRA5 register correction
value into the FRA3 register (2)
—
36.864
32
—
MHz
MHz
High-speed on-chip oscillator frequency when the VCC = 5.0 V, Topr = 25 °C
FRA6 register correction value is written into the
FRA1 register and the FRA7 register correction
value into the FRA3 register
—
—
—
—
Oscillation stability time
VCC = 5.0 V, Topr = 25 °C
VCC = 5.0 V, Topr = 25 °C
—
—
TBD
400
—
—
ms
Self power consumption at oscillation
µA
Notes:
1. VCC = 5.0 V and Topr = 25 °C, unless otherwise specified.
2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.11
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Typ.
125
Symbol
Parameter
Condition
Unit
Min.
60
Max.
250
TBD
—
fOCO-S
Low-speed on-chip oscillator frequency
Oscillation stability time
kHz
µs
—
—
VCC = 5.0 V, Topr = 25 °C
VCC = 5.0 V, Topr = 25 °C
—
30
Self power consumption at oscillation
—
2
µA
Note:
1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
Table 5.12
Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
td(P-R)
Parameter
Condition
Unit
Min.
—
Max.
Time for internal power supply stabilization during
power-on (2)
—
2,000
µs
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25 °C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 37 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.13
Timing Requirements of Synchronous Serial Communication Unit (SSU)
Standard
Symbol
Parameter
Conditions
Unit
Min.
4
Typ.
—
Max.
—
0.6
0.6
1
(2)
tSUCYC
SSCK_i clock cycle time
SSCK_i clock “H” width
SSCK_i clock “L” width
SSCK_i clock rising Master
tCYC
tHI
0.4
0.4
—
—
tSUCYC
tSUCYC
tLO
—
(2)
tRISE
—
tCYC
time
Slave
—
—
1
µs
(2)
tFALL
tSU
SSCK_i clock falling Master
—
—
1
tCYC
time
Slave
—
—
1
µs
SSO_i, SSI_i data input setup During low-voltage signal mode
100
—
—
ns
time
VCC = 3.0 V,
Minimum input voltage = 1.65 V,
external pull-up resistor = 510 Ω (3)
(2)
tH
SSO_i, SSI_i data input hold
time
1
—
—
tCYC
tLEAD
tLAG
tOD
Slave
Slave
1tCYC + 50
1tCYC + 50
—
—
—
—
—
—
1
ns
ns
SCS_i setup time
SCS_i hold time
(2)
SSO_i, SSI_i data output delay
time
tCYC
tSA
tOR
SSI_i slave access time
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
—
—
—
—
—
—
—
—
1.5tCYC + 100
1.5tCYC + 200
1.5tCYC + 100
1.5tCYC + 200
ns
ns
ns
ns
SSI_i slave out open time
i = 0 to 3
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
f1 ≤ 10 MHz is required when the noise filter is used in low-voltage signal mode.
3. These indicate the measurement conditions in low-voltage signal mode.
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Page 38 of 55
R8C/3NT Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS_i (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK_i (output)
(CPOS = 1)
tLO
tHI
SSCK_i (output)
(CPOS = 0)
tLO
tSUCYC
SSO_i (output)
SSI_i (input)
tOD
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS_i (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK_i (output)
(CPOS = 1)
tLO
tHI
SSCK_i (output)
(CPOS = 0)
tLO
tSUCYC
SSO_i (output)
SSI_i (input)
tOD
tSU
tH
CPHS, CPOS: Bits in SSiMR register
i = 0 to 3
Figure 5.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 39 of 55
R8C/3NT Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
VIL or VOL
SCS_i (input)
tHI
tFALL
tRISE
tLEAD
tLAG
SSCK_i (input)
(CPOS = 1)
tLO
tHI
SSCK_i (input)
(CPOS = 0)
tLO
tSUCYC
SSO_i (input)
SSI_i (output)
tSU
tH
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS_i (input)
VIL or VOL
tHI
tFALL
tRISE
tLEAD
tLAG
SSCK_i (input)
(CPOS = 1)
tLO
tHI
SSCK_i (input)
(CPOS = 0)
tLO
tSUCYC
SSO_i (input)
tSU
tH
SSI_i (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSiMR register
i = 0 to 3
Figure 5.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
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5. Electrical Characteristics
tHI
VIH or VOH
VIL or VOL
SSCK_i
tLO
tSUCYC
SSO_i (output)
SSI_i (input)
tOD
tSU
tH
i = 0 to 3
Figure 5.6
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
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Jan 25, 2011
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5. Electrical Characteristics
2
Table 5.14
Timing Requirements of I C bus Interface
Standard
Symbol
Parameter
Condition
Unit
Min.
12tCYC + 600
3tCYC + 300
5tCYC + 500
—
Typ.
—
Max.
—
(2)
(2)
(2)
tSCL
tSCLH
tSCLL
tsf
SCL_i input cycle time
SCL_i input “H” width
ns
ns
ns
ns
ns
—
—
SCL_i input “L” width
—
—
SCL_i, SDA_i input fall time
—
300
(2)
tSP
SCL_i, SDA_i input spike pulse rejection
time
—
—
1tCYC
(2)
tBUF
SDA_i input bus-free time
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
5tCYC
(2)
tSTAH
tSTAS
tSTOP
tSDAS
tSDAH
Start condition input hold time
Retransmit start condition input setup time
Stop condition input setup time
Data input setup time
3tCYC
(2)
3tCYC
(2)
3tCYC
(2)
1tCYC + 40
Data input hold time
10
i = 0 to 3
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA_i
VIL
tBUF
tSTAH
tSP
tSTOP
tSCLH
tSTAS
SCL_i
P (2)
S (1)
tSf
Sr (3)
P (2)
tSCLL
tSr
tSDAS
tSCL
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
i = 0 to 3
2
Figure 5.7
I/O Timing of I C bus Interface
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R8C/3NT Group
5. Electrical Characteristics
Table 5.15
Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V]
Standard
Unit
Symbol
Parameter
Condition
VCC = 5 V
Min.
Typ. Max.
VOH
Output “H” Other than XOUT
voltage
Drive capacity High
Drive capacity Low
VCC – 2.0
—
VCC
V
IOH = −20 mA
Maximum number of
I/Os = 4
VCC = 5 V
VCC – 2.0
—
VCC
V
IOH = −5 mA
Maximum number of
I/Os = 16
XOUT
VCC = 5 V
IOH = −200 µA
1.0
—
—
—
VCC
2.0
V
V
VOL
Output “L” Other than XOUT
voltage
Drive capacity High
VCC = 5 V
IOL = 20 mA
Maximum number of
I/Os = 4
Drive capacity Low
VCC = 5 V
—
—
2.0
V
IOL = 5 mA
Maximum number of
I/Os = 16
XOUT
VCC = 5 V
IOL = 200 µA
—
—
0.5
—
V
V
VT+-VT-
Hysteresis
VCC = 5.0 V
0.1
1.2
INT0, INT1, INT2, INT3,
INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
CTS2, SSCK_i, SCS_i,
SSI_i, SCL_i, SDA_i,
SSO_i (i = 0 to 3)
0.1
1.2
—
V
RESET
IIH
Input “H” current
Input “L” current
Pull-up resistance
VI = 5 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
—
—
25
—
—
—
5.0
−5.0
100
—
µA
µA
IIL
RPULLUP
RfXIN
50
0.3
kΩ
MΩ
Feedback XIN
resistance
RfXCIN
Feedback XCIN
resistance
—
8
—
—
MΩ
VRAM
Note:
RAM hold voltage
During stop mode
1.8
—
V
1. 4.2 V ≤ VCC ≤ 5.5 V, Topr = −20 to 85 °C (N version), and f(XIN) = 20 MHz, unless otherwise specified.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 43 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.16
Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V]
(Topr = −20 to 85 °C (N version), unless otherwise specified.)
Standard
Unit
Symbol
Parameter
Power supply current High-speed
(VCC = 3.3 to 5.5 V) clock mode
Single-chip mode,
output pins are open,
other pins are VSS
Condition
Min.
—
Typ. Max.
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
ICC
6.5
5.3
3.6
3.0
2.2
1.5
7.0
3.0
1
1.5
12.5
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
—
—
—
—
—
—
—
—
—
—
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
—
—
—
XIN clock off
High-speed
on-chip
oscillator mode
15
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1
XIN clock off
Low-speed
on-chip
oscillator mode
Low-speed
clock mode
90
400
400
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
85
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
FMR27 = 1, VCA20 = 0
XIN clock off
—
47
—
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
Wait mode
—
—
—
—
—
15
4
100
90
µA
µA
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
3.5
2.0
15
—
XIN clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Stop mode
5.0
—
XIN clock off, Topr = 85 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 44 of 55
R8C/3NT Group
5. Electrical Characteristics
Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V, Topr = 25 °C)
Table 5.17
External Clock Input (XOUT, XCIN)
Standard
Symbol
Parameter
Unit
Min.
Max.
—
tc(XOUT)
XOUT input cycle time
50
24
24
41
7
ns
ns
ns
µs
µs
µs
tWH(XOUT) XOUT input “H” width
tWL(XOUT) XOUT input “L” width
—
—
tc(XCIN)
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
—
tWH(XCIN)
tWL(XCIN)
—
7
—
tC(XOUT), tC(XCIN)
VCC = 5 V
tWH(XOUT),
tWH(XCIN)
External clock input
tWL(XOUT), tWL(XCIN)
Figure 5.8
External Clock Input Timing Diagram when VCC = 5 V
Table 5.18
TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
—
tc(TRAIO)
TRAIO input cycle time
ns
ns
ns
tWH(TRAIO) TRAIO input “H” width
tWL(TRAIO) TRAIO input “L” width
—
40
—
tC(TRAIO)
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 45 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.19
Serial Interface
Standard
Unit
Symbol
Parameter
Condition
Min.
200
100
100
—
Max.
—
tc(CK)
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
When an external clock is selected
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
th(C-Q)
tsu(D-C)
th(C-D)
—
—
90
—
0
RXDi input setup time
RXDi input hold time
TXDi output delay time
RXDi input setup time
RXDi input hold time
10
—
90
—
When an internal clock is selected
—
10
—
90
90
—
i = 0 to 2
tC(CK)
VCC = 5 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 to 2
Figure 5.10
Table 5.20
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
Standard
Symbol
Parameter
Unit
Min.
Max.
(1)
tW(INH)
—
—
ns
ns
250
250
INTi input “H” width, KIi input “H” width
INTi input “L” width, KIi input “L” width
(2)
tW(INL)
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
tW(INH)
Figure 5.11
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 5 V
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 46 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.21
Electrical Characteristics (3) [2.7 V ≤ VCC < 4.2 V]
Standard
Unit
Symbol
Parameter
Condition
Min.
Typ. Max.
VOH
Output “H” voltage Other than XOUT
Drive capacity High VCC = 3 V
VCC – 0.7
—
VCC
V
IOH = −5 mA
Maximum number
of I/Os = 4
Drive capacity Low VCC = 3 V
VCC – 0.7
—
VCC
V
IOH = −1 mA
Maximum number
of I/Os = 16
XOUT
IOH = −200 µA
1.0
—
—
—
VCC
0.7
V
V
VOL
Output “L” voltage Other than XOUT
Drive capacity High VCC = 3 V
IOL = 5 mA
Maximum number
of I/Os = 4
Drive capacity Low VCC = 3 V
—
—
0.7
V
IOL = 1 mA
Maximum number
of I/Os = 16
XOUT
IOL = 200 µA
—
—
0.5
—
V
V
VT+-VT-
Hysteresis
VCC = 3.0 V
0.1
0.4
INT0, INT1, INT2, INT3,
INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
CTS2, SSCK_i, SCS_i,
SSI_i, SCL_i, SDA_i,
SSO_i (i = 0 to 3)
VCC = 3.0 V
0.1
0.5
—
V
RESET
IIH
Input “H” current
Input “L” current
Pull-up resistance
VI = 3 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
—
—
42
—
—
—
4.0
µA
IIL
−4.0 µA
RPULLUP
RfXIN
84
0.3
168
—
kΩ
Feedback
resistance
XIN
MΩ
RfXCIN
Feedback
resistance
XCIN
—
8
—
—
MΩ
VRAM
Note:
RAM hold voltage
During stop mode
1.8
—
V
1. 2.7 V ≤ VCC < 4.2 V, Topr = −20 to 85 °C (N version), and f(XIN) = 10 MHz, unless otherwise specified.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 47 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.22
Electrical Characteristics (4) [2.7 V ≤ VCC ≤ 3.3 V]
(Topr = −20 to 85 °C (N version), unless otherwise specified.)
Standard
Unit
Symbol
Parameter
Power supply current High-speed
(VCC = 2.7 to 3.3 V) clock mode
Single-chip mode,
output pins are open,
other pins are VSS
Condition
Min.
—
Typ. Max.
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
ICC
3.5
1.5
7.0
3.0
4.0
1.5
1
10
7.5
15
mA
mA
mA
mA
mA
mA
mA
µA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
—
—
—
—
—
—
—
—
XIN clock off
High-speed
on-chip
oscillator mode
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1
XIN clock off
Low-speed
on-chip
oscillator mode
90
390
400
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
Low-speed
clock mode
80
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
FMR27 = 1, VCA20 = 0
XIN clock off
—
40
—
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
Wait mode
—
—
—
—
—
15
4
90
80
—
µA
µA
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
3.5
2.0
15
XIN clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Stop mode
5.0
—
XIN clock off, Topr = 85 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 48 of 55
R8C/3NT Group
5. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V, Topr = 25 °C)
Table 5.23
External Clock Input (XOUT, XCIN)
Standard
Symbol
Parameter
Unit
Min.
Max.
—
tc(XOUT)
XOUT input cycle time
50
24
24
14
7
ns
ns
ns
µs
µs
µs
tWH(XOUT) XOUT input “H” width
tWL(XOUT) XOUT input “L” width
—
—
tc(XCIN)
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
—
tWH(XCIN)
tWL(XCIN)
—
7
—
tC(XOUT), tC(XCIN)
VCC = 3 V
tWH(XOUT),
tWH(XCIN)
External clock input
tWL(XOUT), tWL(XCIN)
Figure 5.12
External Clock Input Timing Diagram when VCC = 3 V
Table 5.24
TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
300
120
120
Max.
—
tc(TRAIO)
TRAIO input cycle time
ns
ns
ns
tWH(TRAIO) TRAIO input “H” width
tWL(TRAIO) TRAIO input “L” width
—
—
tC(TRAIO)
VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 49 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.25
Serial Interface
Standard
Unit
Symbol
Parameter
Condition
Min.
300
150
150
—
Max.
—
tc(CK)
CLKi input cycle time
CLKi input “H” width
When an external clock is selected
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
th(C-Q)
tsu(D-C)
th(C-D)
—
CLKi Input “L” width
TXDi output delay time
TXDi hold time
—
120
—
0
RXDi input setup time
RXDi input hold time
TXDi output delay time
RXDi input setup time
RXDi input hold time
30
—
90
—
When an internal clock is selected
—
30
—
120
90
—
i = 0 to 2
tC(CK)
VCC = 3 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 to 2
Figure 5.14
Table 5.26
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
Standard
Symbol
Parameter
Unit
Min.
Max.
(1)
tW(INH)
—
—
ns
ns
380
380
INTi input “H” width, KIi input “H” width
INTi input “L” width, KIi input “L” width
(2)
tW(INL)
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
tW(INH)
Figure 5.15
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 3 V
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 50 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.27
Electrical Characteristics (5) [1.8 V ≤ VCC < 2.7 V]
Standard
Unit
Symbol
Parameter
Condition
Min.
Typ. Max.
VOH
Output “H” voltage Other than XOUT
Drive capacity High VCC = 1.8 V
VCC – 0.5
—
VCC
V
IOH = −2 mA
Maximum number
of I/Os = 4
Drive capacity Low VCC = 1.8 V
VCC – 0.5
—
VCC
V
IOH = −1 mA
Maximum number
of I/Os = 16
XOUT
IOH = −200 µA
1.0
—
—
—
VCC
0.5
V
V
VOL
Output “L” voltage Other than XOUT
Drive capacity High VCC = 1.8 V
IOL = 2 mA
Maximum number
of I/Os = 4
Drive capacity Low VCC = 1.8 V
IOL = 1 mA
—
—
0.5
V
Maximum number
of I/Os = 16
XOUT
IOL = 200 µA
—
—
0.5
—
V
V
VT+-VT-
Hysteresis
VCC = 2.2 V
0.05
0.20
NT0, INT1, INT2, INT3,
INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
CTS2, SSCK_i, SCS_i,
SSI_i, SCL_i, SDA_i,
SSO_i (i = 0 to 3)
0.05
0.20
—
V
RESET
IIH
Input “H” current
Input “L” current
Pull-up resistance
VI = 2.2 V, VCC = 2.2 V
VI = 0 V, VCC = 2.2 V
VI = 0 V, VCC = 2.2 V
—
—
70
—
—
—
4.0
µA
IIL
−4.0 µA
RPULLUP
RfXIN
140 300
kΩ
Feedback
resistance
XIN
0.3
—
—
—
MΩ
RfXCIN
Feedback
resistance
XCIN
—
8
MΩ
VRAM
Note:
RAM hold voltage
During stop mode
1.8
—
V
1. 1.8 V ≤ VCC < 2.7 V, Topr = −20 to 85 °C (N version), and f(XIN) = 5 MHz, unless otherwise specified.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 51 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.28
Electrical Characteristics (6) [1.8 V ≤ VCC < 2.7 V]
(Topr = −20 to 85 °C (N version), unless otherwise specified.)
Standard
Unit
Symbol
Parameter
Power supply current High-speed
(VCC = 1.8 to 2.7 V) clock mode
Single-chip mode,
output pins are open,
other pins are VSS
Condition
Min.
—
Typ. Max.
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
ICC
2.2
0.8
2.5
1.7
1
—
mA
mA
mA
mA
mA
µA
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
—
—
—
—
—
—
—
XIN clock off
High-speed
on-chip
oscillator mode
10
High-speed on-chip oscillator on fOCO-F = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
—
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1
XIN clock off
Low-speed
on-chip
oscillator mode
90
80
300
350
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
Low-speed
clock mode
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
FMR27 = 1, VCA20 = 0
XIN clock off
—
40
—
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
Wait mode
—
—
—
—
—
15
4
90
80
—
5
µA
µA
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
3.5
2.0
15
XIN clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Stop mode
XIN clock off, Topr = 85 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
—
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 52 of 55
R8C/3NT Group
5. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V, Topr = 25 °C)
Table 5.29
External Clock Input (XOUT, XCIN)
Standard
Symbol
Parameter
Unit
Min.
Max.
—
tc(XOUT)
XOUT input cycle time
200
90
90
14
7
ns
ns
ns
µs
µs
µs
tWH(XOUT) XOUT input “H” width
tWL(XOUT) XOUT input “L” width
—
—
tc(XCIN)
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
—
tWH(XCIN)
tWL(XCIN)
—
7
—
tC(XOUT), tC(XCIN)
VCC = 2.2 V
tWH(XOUT),
tWH(XCIN)
External clock input
tWL(XOUT), tWL(XCIN)
Figure 5.16
External Clock Input Timing Diagram when VCC = 2.2 V
Table 5.30
TRAIO Input
Standard
Symbol
Parameter
Unit
Min.
500
200
200
Max.
—
tc(TRAIO)
TRAIO input cycle time
ns
ns
ns
tWH(TRAIO) TRAIO input “H” width
tWL(TRAIO) TRAIO input “L” width
—
—
tC(TRAIO)
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.17
TRAIO Input Timing Diagram when VCC = 2.2 V
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 53 of 55
R8C/3NT Group
5. Electrical Characteristics
Table 5.31
Serial Interface
Standard
Unit
Symbol
Parameter
Condition
Min.
800
400
400
—
Max.
—
tc(CK)
CLKi input cycle time
CLKi input “H” width
When an external clock is selected
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
th(C-Q)
tsu(D-C)
th(C-D)
—
CLKi Input “L” width
TXDi output delay time
TXDi hold time
—
200
—
0
RXDi input setup time
RXDi input hold time
TXDi output delay time
RXDi input setup time
RXDi input hold time
150
90
—
—
When an internal clock is selected
—
200
—
150
90
—
i = 0 to 2
tC(CK)
VCC = 2.2 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
i = 0 to 2
Figure 5.18
Table 5.32
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
Standard
Symbol
Parameter
Unit
Min.
Max.
(1)
tW(INH)
—
—
ns
ns
1,000
1,000
INTi input “H” width, KIi input “H” width
INTi input “L” width, KIi input “L” width
(2)
tW(INL)
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
tW(INH)
Figure 5.19
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 2.2 V
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 54 of 55
R8C/3NT Group
Package Dimensions
Package Dimensions
Underfill is applied to this package. Evaluate its strength under the environment that actual product modules are used.
A
A
B
B
C
D
E
F
G
7 6 5 4 3 2 1
4 ×
0.03
48-φ0.28±0.03
φ0.05 M S AB
S
SEATING PLANE
0.06 S
C area
C area
Notes
1. Pin pitches are specified by the pin center positions.
2. Datum A and B indicate the center of the ball grid.
R01DS0047EJ0100 Rev.1.00
Jan 25, 2011
Page 55 of 55
REVISION HISTORY
R8C/3NT Group Datasheet
Description
Summary
Rev.
Date
Page
—
All
1
0.01 May 17, 2010
1.00 Jan 25, 2011
First Edition issued
“PRELIMINARY” and “Under development” deleted
1.1 “A sensor control unit is ... capacitive touch electrode.” added
2
Table 1.1 revised
Table 1.2 revised
Table 1.3 revised
Table 4.2 revised
Table 4.7 revised
Table 4.9 revised
Table 4.10 revised
3
4
15
20
22
23
29 to 54 5. Electrical Characteristics added
55 Package Dimensions “Preliminary” deleted
All trademarks and registered trademarks are the property of their respective owners.
C - 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
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