R5F35636DFF [RENESAS]
RENESAS MCU; 瑞萨MCU型号: | R5F35636DFF |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | RENESAS MCU |
文件: | 总85页 (文件大小:603K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M16C/5LD Group, M16C/56D Group
RENESAS MCU
REJ03B0307-0110
Rev.1.10
Dec 01, 2009
1. Overview
1.1
Features
The M16C/5LD Group, M16C/56D Group’s MCUs are single-chip control units that utilize high-
performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5LD Group,
M16C/56D Group are available in 64-pin and 80-pin plastic molded LQFP packages. These MCUs
employ sophisticated instructions for a high level of efficiency and they are capable of executing
instructions at high speed. In addition, the CPU core boasts a multiplier and DMAC for high-speed
operation processing which makes it adequate for controlling office equipment, home appliances, and
industrial equipment.
The M16C/5LD Group has one CAN module, which makes it suitable for factory automation LAN system.
1.1.1
Applications
Factory automation LAN system, audio components, cameras, televisions, household appliances,
office equipment, communication devices, mobile devices, industrial equipment, and other applications.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 1 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
1.2
Specifications
Table 1.1 to Table 1.4 list specifications of the M16C/5LD Group, M16C/56D Group.
Table 1.1
Item
Specifications (80-pin Version) (1/2)
Function
Specification
CPU
Central processing unit M16C/60 Series CPU Core (Multiplier: 16 × 16 ꢀ 32 bits, Multiply-accumulate
unit: 16 × 16 + 32 ꢀ 32 bits)
• Basic instructions: 91
• Minimum instruction execution time:
31.25 ns (f(BCLK) = 32 MHz, VCC = 3.0 to 5.5 V)
40ns (f(BCLK) = 25MHz, VCC = 2.7 to 5.5V)
• Operating mode: Single-chip mode
Memory
ROM, RAM, data flash See Table 1.5. and Table 1.6
Voltage
Detection
Voltage detector
• 2 voltage detect points
Clock
Clock generator
• 4 circuits (Main clock, sub clock, PLL frequency synthesizer, 125-kHz on-
chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation detection
• Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
• Low-power consumption modes: Wait mode, stop mode
• Real time clock
I/O Ports
Interrupts
Programmable I/O
ports
• 71 CMOS inputs/outputs, a pull-up resistor selectable
• Interrupt vectors: 70
• External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
• Interrupt priority levels: 7 levels
Watchdog Timer
DMA
• 15 bits × 1 (with prescaler)
• Automatic reset start function selectable
• 125-kHz on-chip oscillator for watchdog timer
DMAC
• 4 channels, Cycle-steal transfer mode
• Trigger sources: 42
• Transfer modes: 2 (single transfer, repeat transfer)
Timers
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-phase
encoder input) × 3
Programmable output mode × 3
Timer B
16-bit timer × 3
Timer mode, event counter mode, pulse frequency measurement mode,
pulse-width measurement mode
Timer function for three- Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used)
phase motor control
On-chip dead time timer
• 16-bit timer × 1 (base timer)
• I/O: 8 channels
Timer S (Input capture/
output compare)
Task monitoring timer
Real-time clock
16-bit timer ×1 channel
Count: seconds, minutes, hours, weeks
Serial
Interface
UART0 to UART4
4 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)(1)
A/D Converter
10-bit resolution × 27 channels (A/D circuit)
10-bit resolution × 4 channels (A/D1 circuit)
Note:
1. IEBus is a trademark of NEC Electronics Corporation.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 2 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.2
Specifications (80-pin Version) (2/2)
Function
Item
Specification
CRC Calculator
•1 circuit
•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
•MSB/LSB selectable
Multi-master I2C-bus interface
CAN Module
1 channel
32-slot message buffer × 1 channel (M16C/5LD Group only)
Flash Memory
• Programming and erasure supply voltage: 2.7 to 5.5 V
• Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
• Program security: ROM code protect, ID code check
Debug Functions
On-board flash rewrite function, address match × 4
Operating Frequency/Power Supply 32 MHz / 3.0 to 5.5 V
Voltage
25 MHz / 2.7 to 5.5 V
Operating Temperature
Package
-40°C to 85°C
80-pin plastic mold LQFP: PLQP0080KB-A (Previous package code: 80P6Q-A)
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 3 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.3
Specifications (64-pin Version) (1/2)
Function
Central processing M16C/60 Series CPU Core (Multiplier: 16 × 16 ꢀ 32 bits, Multiply-accumulate
Item
CPU
Specification
unit
unit: 16 × 16 + 32 ꢀ 32 bits)
•Basic instructions: 91
•Minimum instruction execution time:
31.25 ns (f(BCLK) = 32 MHz, VCC = 3.0 to 5.5 V)
40ns (f(BCLK) = 25MHz, VCC = 2.7 to 5.5V)
•Operating mode: Single-chip mode
See Table 1.5. and Table 1.6
Memory
ROM, RAM, data
flash
Voltage
Voltage detector
2 voltage detect points
Detection
Clock
Clock generator
•4 circuits (Main clock, sub clock, PLL frequency synthesizer, 125-kHz on-chip
oscillator)
•Oscillation stop detector: Main clock oscillator stop/re-oscillation detection
•Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable
•Low-power consumption modes: Wait mode, stop mode
•Real time clock
I/O Ports
Interrupts
Programmable I/O
ports
• 55 CMOS inputs/outputs, a pull-up resistor selectable
•Interrupt vectors: 70
•External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
•Interrupt priority levels: 7 levels
Watchdog Timer
DMA
•15 bits × 1 (with prescaler)
•Automatic reset start function selectable
•125-kHz on-chip oscillator for watchdog timer
DMAC
•4 channels, Cycle-steal transfer mode
•Trigger sources: 40
•Transfer modes: 2 (single transfer, repeat transfer)
Timer
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-phase encoder
input) × 3
Programmable output mode × 3
Timer B
16-bit timer × 3
Timer mode, event counter mode, pulse frequency measurement mode, pulse-
width measurement mode
Timer function for
Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used)
three-phase motor On-chip dead time timer
control
Timer S (Input
capture/output
compare)
•16-bit timer × 1 (base timer)
•I/O: 8 channels
Task monitoring
timer
16-bit timer ×1 channel
Real-time clock
Count: seconds, minutes, hours, weeks
Serial Interface UART0 to UART3
3 channels (UART, clock synchronous serial interface)
1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)(1)
A/D Converter
10-bit resolution × 16 channels (A/D circuit)
10-bit resolution × 4 channels (A/D1 circuit)
Note:
1. IEBus is a trademark of NEC Electronics Corporation.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 4 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.4
Specifications (64-pin Version) (2/2)
Function
Item
Specification
CRC Calculator
•1 circuit
•CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
•MSB/LSB selectable
Multi-master I2C-bus interface
CAN Module
1 channel
32-slot message buffer × 1 channel (M16C/5LD Group only)
Flash Memory
•Programming and erasure supply voltage: 2.7 to 5.5 V
•Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
•Program security: ROM code protect, ID code check
Debug Functions
On-board flash rewrite function, address match × 4
Operating Frequency/Power Supply 32 MHz / 3.0 to 5.5 V
Voltage
25 MHz / 2.7 to 5.5 V
Operating Temperature
Package
-40°C to 85°C
64-pin plastic mold LQFP: PLQP0064KB-A (Previous package code: 64P6Q-A)
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 5 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
1.3
Product List
Table 1.5 shows product information on the M16C/5LD Group, M16C/56D Group. Figure 1.1 shows part
numbers, memory sizes, and packages. Figure 1.2 shows marking drawing (top view).
Table 1.5
Product List of M16C/5LD Group
As of Dec.2009
ROM Capacity
RAM
Capacity
Part Number
Package Name
PLQP0064KB-A
Remarks
CAN
Program
ROM 1
Program
ROM 2
Data flash
4 Kbytes
x 2 blocks
R5F35L30DFF
64 Kbytes
96 Kbytes
16 Kbytes
16 Kbytes
4 Kbytes
8 Kbytes
R5F35L23DFE
R5F35L33DFF
R5F35L26DFE
R5F35L36DFF
R5F35L2EDFE
R5F35L3EDFF
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
4 Kbytes
x 2 blocks
1 channel
4 Kbytes
x 2 blocks
128 Kbytes 16 Kbytes
256 Kbytes 16 Kbytes
12 Kbytes
20 Kbytes
4 Kbytes
x 2 blocks
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
Table 1.6
Product List of M16C/56D Group
As of Dec.2009
ROM Capacity
RAM
Capacity
Part Number
Package Name
PLQP0064KB-A
Remarks
CAN
N/A
Program
ROM 1
Program
ROM 2
Data flash
4 Kbytes
x 2 blocks
R5F35630DFF
64 Kbytes
96 Kbytes
16 Kbytes
16 Kbytes
4 Kbytes
8 Kbytes
R5F35623DFE
R5F35633DFF
R5F35626DFE
R5F35636DFF
R5F3562EDFE
R5F3563EDFF
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0080KB-A
PLQP0064KB-A
4 Kbytes
x 2 blocks
4 Kbytes
x 2 blocks
128 Kbytes 16 Kbytes
256 Kbytes 16 Kbytes
12 Kbytes
20 Kbytes
4 Kbytes
x 2 blocks
(D): Under development
(P): Under planning
The old package names are as follows:
PLQP0080KB-A: 80P6Q-A
PLQP0064KB-A: 64P6Q-A
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 6 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
MCU Part No. R 5 F 3 5L 2 0 D FE
Package type
FE: PLQP0080KB-A (80P6Q-A)
FF: PLQP0064KB-A (64P6Q-A)
Property code
D: Operating temperature -40°C to 85°C
Memory capacity
Program ROM 1/RAM
0: 64 Kbytes/4 Kbytes
3: 96 Kbytes/8 Kbytes
6: 128 Kbytes/12 Kbytes
E: 256 Kbytes/20 Kbytes
Pin
2: 80-pin
3: 64-pin
Group Name
5L: M16C/5LD Group
56: M16C/56D Group
16-bit MCU
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Correspondence of Part Number, Memory Size, and Package
M 1 6 C
Part number
(See Figure 1.1 “Correspondence of Part Number, Memory Size, and Package”.)
R 5 F 3 5 L 2 0 D F E
X X X X X X X
Seven digit date code
Figure 1.2
Marking Diagram of Flash Memory Version (Top View)
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 7 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
1.4
Block Diagram
Figure 1.3 shows a block diagram of M16C/5LD Group, M16C/56D Group 80-pin package. Figure 1.4
shows a block diagram of the M16C/5LD Group, M16C/56D Group 64-pin package.
8
8
8
8
I/O ports
Port P0
Port P1
Port P2
Port P3
Peripherals
UART/clock synchronous
serial interface
Clock generator
XIN-XOUT
XCIN-XCOUT
Timer (16-bit)
Output (timer A): 5
Input (timer B): 3
(8-bit x 5 channels)
125-kHz on-chip oscillator
PLL frequency synthesizer
DMAC
(4 channels)
Three-phase motor control
circuit
125-kHz on-chip oscillator
dedicated to watchdog timer
Multi-master I2C bus
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
CAN module
(32-slot message buffer,
1 channel)
CRC calculator
(CCITT, CRC-16)
(M16C/5LD Group only)
Voltage detector
Power-on reset
Task monitoring timer
(1 channel)
On-chip debugger
Real-time clock
(8-bit x 1 channel)
Memory
M16C/60 Series CPU core
A/D converter
(10-bit x 27 channels) (A/D circuit)
(10-bit x 4 channels) (A/D1 circuit)
(1)
(2)
ROM
RAM
R0H
R1H
R0L
R1L
SB
USP
ISP
R2
R3
Watchdog timer
(15 bits)
R3
INTB
PC
A0
A1
FB
Multiplier
FLG
FB
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type
Figure 1.3
M16C/5LD Group, M16C/56D Group 80-Pin Block Diagram
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 8 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
4
3
8
4
I/O ports
Port P0
Port P1
Port P2
Port P3
Peripherals
UART/clock synchronous
serial interface
Clock generator
XIN-XOUT
XCIN-XCOUT
Timer (16-bit)
Output (timer A): 5
Input (timer B): 3
(8-bit x 4 channels)
125-kHz on-chip oscillator
PLL frequency synthesizer
DMAC
(4 channels)
Three-phase motor control
circuit
Multi-master I2C bus
125-kHz on-chip oscillator
dedicated to watchdog timer
Timer S
(Input capture/output compare)
Time measurement: 8 channels
Waveform generating: 8 channels
CAN module
(32-slot message buffer,
1 channel)
CRC calculator
(CCITT, CRC-16)
(M16C/5LD Group only)
Task monitoring timer
(1 channel)
Voltage detector
Power-on reset
Real-time clock
(8-bit x 1 channel)
On-chip debugger
A/D converter
(10-bit x 16 channels) (A/D circuit)
(10-bit x 4 channels) (A/D1 circuit)
Memory
M16C/60 Series CPU core
(1)
ROM
R0H
R1H
R0L
R1L
SB
USP
ISP
Watchdog timer
(15 bits)
(2)
R2
R3
RAM
R3
INTB
PC
A0
A1
FB
Multiplier
FLG
FB
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.4
M16C/5LD Group, M16C/56D Group 64-Pin Block Diagram
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 9 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
1.5
Pin Assignments
Figure 1.5 shows the pin assignments for 80-pin package, and Table 1.7 and Table 1.8 list pin names for
80-pin package.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P0_6 / AN0_6
P0_5 / AN0_5
P0_4 / AN0_4
P0_3 / AN0_3
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
AVSS
P6_3 / TXD0
P3_0 / CLK3
P3_1 / RXD3
P3_2 / TXD3
P3_3 / CTS3 / RTS3
P3_4
P3_5
P3_6
P3_7
P6_4 / CTS1 / RTS1
P6_5 / CLK1
P6_6 / RXD1
P6_7 / TXD1
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
P7_2 / CLK2 / TA1OUT / V / RXD1
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
P7_4 / TA2OUT / W
P7_5 / TA2IN / W
M16C/5LD Group
M16C/56D Group
PLQP0080KB-A
(80P6Q-A)
(Top view)
P10_0 / AN_0
VREF
AVCC
P9_7 / AN2_7 / RXD4
P9_6 / AN2_6 / TXD4
P7_6 / TA3OUT
Note:
1. There are pins CTX0 and CRX0 only in the M16C/5LD group.
Figure 1.5
Pin Assignment for 80-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual pins
after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 10 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.7
Pin Names, 80-Pin Package (1/2)
Multi-
master
I2C-bus
pin
Inter-
rupt
Pin
Pin Control
Analog
Pin
Port
Timer Pin
Timer S Pin
UART/CAN Pin
No.
pin
1
2
3
4
5
6
7
8
9
P9_5
P9_3
P9_2
P9_1
CLK4
AN2_5
AN2_4
AN3_2
AN3_1
AN3_0
CTX0 (1)
CRX0 (1)
TB2IN
TB1IN
TB0IN
CLKOUT P9_0
CNVSS
XCIN
P8_7
XCOUT P8_6
RESET
10 XOUT
11 VSS
12 XIN
13 VCC
14
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P3_0
P6_3
NMI
SD
ZP
15
INT2
INT1
INT0
16
17
18
TA4IN/U
TA4OUT/U
TA3IN
19
20
21
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN
22
23
24
CTS2/RTS2/TXD1
CLK2/RXD1
RXD2/SCL2/CLK1
TXD2/SDA2/CTS1/RTS1
TXD1
25
26
TA0OUT
27
28
29
RXD1
30
CLK1
31
CTS1/RTS1
32
33
34
35
36
CTS3/RTS3
TXD3
37
38
RXD3
39
CLK3
40
TXD0
Note 1. There are pins CTX0 and CRX0 only in the M16C/5LD Group.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 11 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.8
Pin Names, 80-Pin Package (2/2)
Multi-
master
I2C-bus
pin
Inter-
rupt
Pin
Pin Control
Analog
Pin
Port
Timer Pin
Timer S Pin
UART/CAN Pin
No.
pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
P6_2
P6_1
P6_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
RXD0
CLK0
RTCOUT
CTS0/RTS0
OUTC1_7/INPC1_7
OUTC1_6/INPC1_6
OUTC1_5/INPC1_5
OUTC1_4/INPC1_4
OUTC1_3/INPC1_3
OUTC1_2/INPC1_2
OUTC1_1/INPC1_1
OUTC1_0/INPC1_0
INPC1_7
SCLMM
SDAMM
IDU
IDW
IDV
INT5
INT4
INT3
ADTRG
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN_7
KI3
KI2
KI1
KI0
AN_6
AN_5
AN_4
AN_3
AN_2
AN_1
75 AVSS
76
P10_0
AN_0
77 VREF
78 AVCC
79
P9_7
P9_6
RXD4
TXD4
AN2_7
AN2_6
80
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 12 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
Figure 1.6 shows the pin assignments for 64-pin package and Table 1.9 and Table 1.10 list pin names for
64-pin package.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P3_0 / CLK3
P3_1 / RXD3
P3_2 / TXD3
P3_3 / CTS3 / RTS3
P6_4 / RTS1 / CTS1
P6_5 / CLK1
P6_6 / RXD1
P6_7 / TXD1
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
P7_2 / CLK2 / TA1OUT / V / RXD1
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
P7_4 / TA2OUT / W
P7_5 / TA2IN / W
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
M16C/5LD Group
M16C/56D Group
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
PLQP0064KB-A
(64P6Q-A)
VREF
AVCC
(Top view)
P9_3 / AN2_4 /CTX0 (1)
P9_2 / AN3_1 / TB2IN / CRX0 (1)
P7_6 / TA3OUT
P7_7 / TA3IN
Note:
1. There are pins CTX0 and CRX0 only in the M16C/5LD group.
Figure 1.6
Pin Assignment for 64-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual pins
after reset. When the PACR register is not set, signals are not input or output for some of the pins.
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M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.9
Pin Names, 64-Pin Package (1/2)
Multi-
master
I2C-bus
pin
Inter-
rupt
Pin
Pin Control
Analog
Pin
Port
Timer Pin
Timer S Pin
UART/CAN Pin
No.
pin
1
2
3
4
5
6
7
8
9
P9_1
TB1IN
AN3_1
AN3_0
CLKOUT P9_0
CNVSS
TB0IN
XCIN
P8_7
XCOUT P8_6
RESET
XOUT
VSS
XIN
10 VCC
11
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P3_3
P3_2
P3_1
P3_0
P6_3
P6_2
P6_1
P6_0
P2_7
P2_6
P2_5
P2_4
SD
NMI
ZP
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
INT2
INT1
INT0
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN
CTS2/RTS2/TXD1
CLK2/RXD1
RXD2/SCL2/CLK1
TXD2/SDA2/CTS1/RTS1
TXD1
TA0OUT
RXD1
CLK1
CTS1/RTS1
CTS3/RTS3
TXD3
RXD3
CLK3
TXD0
RXD0
CLK0
RTCOUT
CTS0/RTS0
OUTC1_7/INPC1_7
OUTC1_6/INPC1_6
OUTC1_5/INPC1_5
OUTC1_4/INPC1_4
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M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.10
Pin Names, 64-Pin Package (2/2)
Multi-
master
I2C-bus
pin
Inter-
rupt
Pin
Pin Control
Port
Timer Pin
Timer S Pin
UART/CAN Pin
Analog Pin
No.
pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
OUTC1_3/INPC1_3
OUTC1_2/INPC1_2
OUTC1_1/INPC1_1
OUTC1_0/INPC1_0
INPC1_7
SCLMM
SDAMM
IDU
INT5
INT4
INT3
IDW
IDV
ADTRG
AN0_3
AN0_2
AN0_1
AN0_0
AN_7
KI3
KI2
KI1
KI0
AN_6
AN_5
AN_4
AN_3
AN_2
AN_1
59 AVSS
60
P10_0
AN_0
61 VREF
62 AVCC
63
CTX0 (1)
CRX0 (1)
P9_3
P9_2
AN2_4
AN3_2
TB2IN
64
Note 1. There are pins CTX0 and CRX0 only in the M16C/5LD Group.
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M16C/5LD Group, M16C/56D Group
1. Overview
1.6
Pin Functions
Table 1.11
Pin Functions (64-Pin and 80-Pin Packages)
Signal Name
Pin Name
VCC, VSS
I/O
I
Description
Power supply
Apply 2.7 V to 5.5 V to VCC pin and 0 V to VSS pin.
Analog power
supply
AVCC,
AVSS
Power supply for the A/D converter. AVCC and AVSS should be
connected to VCC and VSS, respectively.
I
Reset input
RESET
CNVSS
XIN
I
I
I
Low active input pin. Driving this low resets the MCU.
Connect the CNVSS to VSS.
CNVSS
Main clock input
Main clock output
Input/output pin for the main clock oscillator. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. (1) To apply
an external clock, connect it to XIN and leave XOUT open. When
XIN is not used, connect XIN to VCC pin and leave XOUT open.
XOUT
O
Sub clock input
Sub clock output
Clock output
XCIN
I
Input/output for the sub clock oscillator. Connect a crystal oscillator
between XCIN and XCOUT.
XCOUT
CLKOUT
O
This pin outputs the clock having the same frequency as f1, f8, f32,
or fC.
O
I
INT interrupt input INT0 to INT5
Low active input pins for INT interrupt. INT2 is used to input Z-phase
of timer A.
NMI input
NMI
I
I
Low active input pin for NMI interrupt.
Low active Input pins for the key input interrupt
Timers A0 to A4 input/output pins
Key input interrupt KI0 to KI3
Timer A
TA0OUT to
TA4OUT
I/O
TA0IN to TA4IN
ZP
I
I
Timers A0 to A4 input pins
Input pin for Z-phase
Timer B
TB0IN to TB2IN
I
Timers B0 to B2 input pins
Three-phase motor U,U,V,V,W,W
O
I
Output pins for three-phase motor control timers
Input pins for three-phase motor control timers
Output pin for real time clock
control timer
IDU, IDW, IDV, SD
RTCOUT
Real time clock
Serial interface
O
I
CTS0 to CTS3
RTS0 to RTS3
CLK0 to CLK3
RXD0 to RXD3
TXD0 to TXD3
SDA2
Input pins to control data transmission
Output pins to control data reception
O
I/O Transfer clock input/output pins
I
Serial data input pins
Serial data output pins
O
I2C mode
I/O Serial data input/output pin
SCL2
I/O Transfer clock input/output pin
Multi-master I2C
bus
SDAMM
Serial data input/output pin
I/O
SCLMM
Transfer clock input/output pin
Note 1. Please contact the oscillator manufacturer for oscillation characteristic.
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M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.12
Pin Functions (64-Pin and 80-Pin Packages)
Signal Name
Pin Name
I/O
Description
Reference voltage VREF
input
Reference voltage input pin for the A/D converter.
I
I
A/D converter
AN_0 to AN_7
Analog input pins for the A/D converter
AN0_0 to AN0_3
AN2_4
I
AN3_0 to AN3_2
ADTRG
I
I
Low active input pin for an external A/D trigger
Input pins for time measurement function
Timer S
INPC1_0 to
INPC1_7
OUTC1_0 to
OUTC1_7
Output pins for waveform generating function
O
CAN Module (1)
I/O port
CRX0
CTX0
I
Input pin for CAN communication
Output pin for CAN communication
O
P0_0 to P0_3
P1_5 to P1_7
P2_0 to P2_7
P3_0 to P3_3
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_7
P9_0 to P9_3
P10_0 to P10_7
CMOS I/O ports. A direction register determines whether each pin is
used as an input port or an output port. Pull-up resistor is selectable
for every unit of 4 input ports.
I/O
Note 1. There is Can module only in the M16C/5LD group.
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Page 17 of 83
M16C/5LD Group, M16C/56D Group
1. Overview
Table 1.13
Pin Functions (80-Pin Package Only)
Pin Name I/O
CLK4 I/O Transfer clock input/output pin
Signal Name
Description
Serial Interface
RXD4
TXD4
I
Serial data input pin
O
Serial data output pin
A/D converter
I/O port
AN0_4 to AN0_7
AN2_0 to AN2_3
AN2_5 to AN2_7
Analog input pins for the A/D converter
I
P0_4 to P0_7
P1_0 to P1_4
P3_4 to P3_7
P9_5 to P9_7
CMOS I/O ports. A direction register determines whether
each pin is used as an input port or an output port. Pull-up
resistor is selectable for every unit of 4 input ports.
I/O
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M16C/5LD Group, M16C/56D Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of thirteen
configure a register bank. There are two sets of register banks.
b31
b15
b8b7
b0
R0H(high-order bits of R0) R0L (low-order bits of R0)
R2
R3
R1H(high-order bits of R1) R1L (low-order bits of R1)
Data registers (1)
R2
R3
A0
A1
FB
Address registers (1)
Frame base registers (1)
b19
b15
b0
Interrupt table register
Program counter
INTBH
INTBL
INTBH is the 4 high-order bits of INTB register and
INTBL is the 16 low-order bits
b19
b0
PC
b15
b0
USP
User stack pointer
Interrupt stack pointer
Static base register
ISP
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
IPL
U
I
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers configure a register bank. There are two register banks.
Figure 2.1
Central Processing Unit Registers
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Page 19 of 83
M16C/5LD Group, M16C/56D Group
2. Central Processing Unit (CPU)
2.1
2.1.1
General Purpose Registers
Data Registers (R0, R1, R2, and R3)
The R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic and logic operations. R0 and
R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit
data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same
applies to R3R1.
2.1.2
Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic and
logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.1.3
Frame Base Register (FB)
FB is a 16-bit register used for FB relative addressing.
2.1.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.1.5
Program Counter (PC)
PC is a 20-bit register that indicates the address of the next instruction to be executed.
2.1.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, each have 16 bits. The U flag is used to switch between USP
and ISP.
2.1.7
Static Base Register (SB)
SB is a 16-bit register used for SB-relative addressing.
2.1.8
Flag Register (FLG)
FLG is a 11-bit register that indicates the CPU state.
2.1.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit that has been generated by the arithmetic/logic unit.
2.1.8.2
Debug Flag (D Flag)
The D flag is for debugging purposes only. Set it to 0.
2.1.8.3
Zero Flag (Z Flag)
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise it becomes 0.
2.1.8.4
Sign Flag (S Flag)
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise it becomes 0.
2.1.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
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M16C/5LD Group, M16C/56D Group
2. Central Processing Unit (CPU)
2.1.8.6
Overflow Flag (O Flag)
The O flag becomes set to 1 when an arithmetic operation results in an overflow; otherwise it becomes
0.
2.1.8.7
Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag is 0 when an
interrupt request is acknowledged.
2.1.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt number 0 to 31 is executed.
2.1.8.9
Processor Interrupt Priority Level (IPL)
IPL is a 3-bit register and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has a higher priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Areas
Only write 0 to bits assigned as reserved areas. The read value is undefined.
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M16C/5LD Group, M16C/56D Group
3. Memory
3. Memory
Special Function Registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to
0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved,
so do not access any blank spaces.
The internal RAM is allocated from address 00400h to superior direction. For example, a 8-Kbyte internal
RAM is addressed from 00400h to 023FFh. The internal RAM is used not only for data storage but also for
stack area when subroutines are called or when interrupt request are acknowledged.
The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1,
and program ROM 2.
The data flash is addressed from 0E000h to 0FFFFh. This data flash space is used not only for data storage
but also for program storage.
Program ROM 2 is assigned addresses 10000h to 13FFFh. Program ROM 1 is assigned addresses
FFFFFh to inferior direction. For example, the 64-Kbyte program ROM 1 space has addresses F0000h to
FFFFFh.
The special page vectors are assigned addresses FFE00h to FFFD7h. They are used for the JMPS
instruction and JSRS instruction. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for
details.
The fixed vector table for interrupts, ID code write address, OFS1 address and OSF2 address are assigned
addresses FFFDBh to FFFFFh.
The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table
for interrupts.
00000h
00400h
SFRs
Internal RAM
XXXXXh
Reserved
0D000h
0D800h
0E000h
SFRs
Reserved
13000h
On-chip debugger
monitor area
Internal ROM
(Data flash)
13FF0h
13FFFh
10000h
14000h
Internal ROM
(Program ROM 2)
Internal RAM
User boot code area
Capacity
XXXXXh
013FFh
023FFh
033FFh
053FFh
4 Kbytes
8 Kbytes
12 Kbytes
20 Kbytes
Relocatable vector table
Reserved
256 bytes beginning with the start
address set in the INTB register
Internal ROM
FFE00h
Special page vector
table
Capacity
64 Kbytes
96 Kbytes
128 Kbytes
256 Kbytes
YYYYYh
F0000h
E8000h
E0000h
C0000h
FFFD8h
FFFDBh
Reserved
YYYYYh
FFFFFh
Internal ROM
(Program ROM 1)
Fixed vector table
ID code address
OFS1 address, OFS2
address
FFFFFh
Notes:
1. Do not access the reserved areas.
2. The figure above applies under the following conditions:
-The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash)
-The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled)
Figure 3.1
Memory Map
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Page 22 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
4.1
SFRs
An SFR is a control register for a peripheral function. Table 4.1 SFR List (1) to Table 4.35 SFR List (35) list
SFR information.
Table 4.1
SFR List (1)
Address
0000h
0001h
0002h
0003h
Register
Symbol
Reset Value
0004h Processor Mode Register 0
0005h Processor Mode Register 1
0006h System Clock Control Register 0
0007h System Clock Control Register 1
0008h
PM0
PM1
CM0
CM1
00h
0000 1000b
0100 1000b
0010 0000b
0009h
000Ah Protect Register
000Bh
PRCR
CM2
00h
(2)
Oscillation Stop Detection Register
000Ch
000Dh
000Eh
000Fh
0X00 0010b
0010h Program 2 Area Control Register
PRG2C
PCLKR
XXXX XX00b
0000 0011b
0011h
0012h Peripheral Clock Select Register
0013h
0014h
0015h Clock Prescaler Reset Flag
CPSRF
0XXX XXXXb
0016h
0017h
(3)
Reset Source Determine Register
Voltage Detector 2 Flag Register
0018h
0019h
RSTFR
VCR1
XX0X 001Xb (Hardware Reset)
(1)
0000 1000b
(1, 4)
000X 0000b
001X 0000b
001Ah Voltage Detector Operation Enable Register
VCR2
(1, 5)
001Bh
001Ch PLL Control Register 0
PLC0
PM2
0X01 X010b
XX00 0X01b
001Dh
001Eh Processor Mode Register 2
001Fh
X: Undefined
Blanks are reserved. No access is allowed.
Notes:
1. Software reset, watchdog timer reset, oscillation stop detection reset, and voltage monitor 2 reset do
not affect registers: VCR1 and VCR2.
2. Oscillation stop detection reset does not affect bits CM20, CM21, and CM27.
3. The state of the bits in the RSTFR register depends on the reset type.
4. When the LVDAS bit of address OFS1 is 1 at hardware reset.
5. This value shows the value after a voltage monitor 0 reset, power-on reset or when the LVDAS bit of
address OFS1 is 0 at hardware reset.
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M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.2
SFR List (2)
Address
0020h
0021h
0022h
0023h
0024h
0025h
Register
Symbol
Reset Value
0026h Voltage Monitor Function Select Register
0027h
VWCE
VD2LS
00h
0000 0100b
(1)
Voltage Detector 2 Level Select Register
0028h
0029h
(2, 3)
1100 1X10b
1100 1X11b
002Ah Voltage Monitor 0 Control Register
VW0C
VW2C
(2, 4)
002Bh
(2, 5)
Voltage Monitor 2 Control Register
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
1000 0X10b
X: Undefined
Blanks are reserved. No access is allowed.
Notes:
1. Hardware reset, power-on reset, voltage monitor 0 reset, or voltage monitor 2 reset.
2. Software reset, watchdog timer reset, oscillation stop detection reset, voltage monitor 0 reset, and
voltage monitor 2 reset do not affect the VW0C register or bits VW2C2 and VW2C3 in the VW2C
register.
3. When the LVDAS bit of address OFS1 is 1 at hardware reset.
4. This value shows the value after a voltage monitor 0 reset, power-on reset, or when the LVDAS bit of
address OFS1 is 0 at hardware reset.
5. Hardware reset, power-on reset, or voltage monitor 0 reset.
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M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.3
SFR List (3)
Address
0040h
0041h
0042h
0043h
Register
Symbol
Reset Value
XX00 X000b
0044h INT3 Interrupt Control Register
0045h
INT3IC
INT5IC
0046h
0047h
0048h INT5 Interrupt Control Register
0049h INT4 Interrupt Control Register
XX00 X000b
XX00 X000b
INT4IC
BCNIC,
TMOSIC
DM0IC
UART2 Bus Collision Detection Interrupt Control Register,
Task Monitoring Timer Interrupt Control Register
004Ah
XXXX X000b
004Bh DMA0 Interrupt Control Register
004Ch DMA1 Interrupt Control Register
XXXX X000b
XXXX X000b
DM1IC
Key Input Interrupt Control Register, A/D 1 Conversion Interrupt
Control Register
004Dh
KUPIC, ADEIC
XXXX X000b
004Eh A/D Conversion Interrupt Control Register
004Fh UART2 Transmit Interrupt Control Register
0050h UART2 Receive Interrupt Control Register
0051h UART0 Transmit Interrupt Control Register
0052h UART0 Receive Interrupt Control Register
0053h UART1 Transmit Interrupt Control Register
0054h UART1 Receive Interrupt Control Register
0055h Timer A0 Interrupt Control Register
0056h Timer A1 Interrupt Control Register
0057h Timer A2 Interrupt Control Register
0058h Timer A3 Interrupt Control Register
0059h Timer A4 Interrupt Control Register
005Ah Timer B0 Interrupt Control Register
005Bh Timer B1 Interrupt Control Register
005Ch Timer B2 Interrupt Control Register
005Dh INT0 Interrupt Control Register
005Eh INT1 Interrupt Control Register
005Fh INT2 Interrupt Control Register
0060h
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XX00 X000b
XX00 X000b
XX00 X000b
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h DMA2 Interrupt Control Register
006Ah DMA3 Interrupt Control Register
006Bh
DM2IC
DM3IC
XXXX X000b
XXXX X000b
006Ch
006Dh
006Eh
S4TIC,
RTCCIC
UART4 Transmit Interrupt Control Register,
006Fh
XXXX X000b
Real-Time Clock Compare Interrupt Control Register
X: Undefined
Blanks are reserved. No access is allowed.
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M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.4
SFR List (4)
Address
Register
Symbol
S4RIC
C0WIC
Reset Value
XXXX X000b
XXXX X000b
0070h UART4 Receive Interrupt Control Register
0071h CAN0 Wakeup Interrupt Control Register
UART3 Transmit Interrupt Control Register,
CAN0 Error Interrupt Control Register
S3TIC,
C0EIC
0072h
XXXX X000b
0073h UART3 Receive Interrupt Control Register
0074h Real-Time Clock Cycle Interrupt Control Register
0075h CAN0 Receive Completion Interrupt Control Register
0076h CAN0 Transmit Completion Interrupt Control Register
0077h CAN0 Receive FIFO Interrupt Control Register
0078h CAN0 Transmit FIFO Interrupt Control Register
0079h IC/OC Interrupt 0 Control Register
S3RIC
RTCTIC
C0RIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
C0TIC
C0FRIC
C0FTIC
ICOC0IC
ICOCH0IC
ICOC1IC,
IICIC
ICOCH1IC,
SCLDAIC
ICOCH2IC
ICOCH3IC
BTIC
007Ah IC/OC Channel 0 Interrupt Control Register
IC/OC Interrupt 1 Control Register,
I2C-bus Interface Interrupt Control Register
007Bh
XXXX X000b
XXXX X000b
IC/OC Channel 1 Interrupt Control Register,
SCL/SDA Interrupt Control Register
007Ch
007Dh IC/OC Channel 2 Interrupt Control Register
007Eh IC/OC Channel 3 Interrupt Control Register
007Fh IC/OC Base Timer Interrupt Control Register
XXXX X000b
XXXX X000b
XXXX X000b
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h to
012Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 26 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.5
SFR List (5)
Address
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
Reset Value
0140h A/D1 Register 0
AD10
AD11
AD12
AD13
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
0141h
0142h A/D1 Register 1
0143h
0144h A/D1 Register 2
0145h
0146h A/D1 Register 3
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h A/D1 Trigger Control Register
AD1TRGCON
AD1CON2
XXXX 00XXb
0000 X00Xb
0153h
0154h A/D1 Control Register 2
0155h
0156h A/D1 Control Register 0
AD1CON0
AD1CON1
0000 0XXXb
0000 X000b
0157h A/D1 Control Register 1
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 27 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.6
SFR List (6)
Address
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
Register
Symbol
Reset Value
XXh
XXh
0Xh
0181h DMA0 Source Pointer
SAR0
0182h
0183h
0184h
XXh
XXh
0Xh
0185h DMA0 Destination Pointer
DAR0
TCR0
0186h
0187h
0188h
XXh
XXh
DMA0 Transfer Counter
0189h
018Ah
018Bh
018Ch DMA0 Control Register
DM0CON
0000 0X00b
018Dh
018Eh
018Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 28 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.7
SFR List (7)
Address
0190h
Register
Symbol
SAR1
Reset Value
XXh
0191h DMA1 Source Pointer
XXh
0192h
0Xh
0193h
0194h
XXh
XXh
0Xh
0195h DMA1 Destination Pointer
DAR1
TCR1
0196h
0197h
0198h
XXh
XXh
DMA1 Transfer Counter
0199h
019Ah
019Bh
019Ch DMA1 Control Register
DM1CON
0000 0X00b
019Dh
019Eh
019Fh
01A0h
XXh
XXh
0Xh
01A1h DMA2 Source Pointer
SAR2
01A2h
01A3h
01A4h
XXh
XXh
0Xh
01A5h DMA2 Destination Pointer
DAR2
TCR2
01A6h
01A7h
01A8h
XXh
XXh
DMA2 Transfer Counter
01A9h
01AAh
01ABh
01ACh DMA2 Control Register
DM2CON
0000 0X00b
01ADh
01AEh
01AFh
01B0h
XXh
XXh
0Xh
01B1h DMA3 Source Pointer
SAR3
01B2h
01B3h
01B4h
XXh
XXh
0Xh
01B5h DMA3 Destination Pointer
DAR3
TCR3
01B6h
01B7h
01B8h
XXh
XXh
DMA3 Transfer Counter
01B9h
01BAh
01BBh
01BCh DMA3 Control Register
DM3CON
0000 0X00b
01BDh
01BEh
01BFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 29 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.8
SFR List (8)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
Register
Symbol
TB01
Reset Value
XXh
Timer B0-1 Register
Timer B1-1 Register
Timer B2-1 Register
XXh
XXh
XXh
XXh
TB11
TB21
XXh
01C6h Pulse Period/Width Measurement Mode Function Select Register 1
PPWFS1
XXXX X000b
01C7h
01C8h Timer B Count Source Select Register 0
01C9h Timer B Count Source Select Register 1
TBCS0
TBCS1
00h
X0h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h Timer A Count Source Select Register 0
01D1h Timer A Count Source Select Register 1
01D2h Timer A Count Source Select Register 2
TACS0
TACS1
TACS2
00h
00h
X0h
01D3h
01D4h 16-Bit Pulse Width Modulation Mode Function Select Register
01D5h Timer A Waveform Output Function Select Register
PWMFS
TAPOFS
0XX0 X00Xb
XXX0 0000b
01D6h
01D7h
01D8h Timer A Output Waveform Change Enable Register
01D9h
01DAh Three-Phase Protect Control Register
TAOW
TPRC
XXX0 X00Xb
00h
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 30 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.9
SFR List (9)
Address
01F0h
01F1h
Register
Symbol
TMOS
Reset Value
XXh
Task Monitor Timer Register
XXh
01F2h Task Monitor Timer Count Start Flag
TMOSSR
TMOSCS
TMOSPR
XXXX XXX0b
XXXX 0000b
00h
01F3h Task Monitor Timer Count Source Select Register
01F4h Task Monitor Timer Protect Register
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h Interrupt Source Select Register 3
IFSR3A
IFSR2A
IFSR
00h
00h
00h
0206h Interrupt Source Select Register 2
0207h Interrupt Source Select Register
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh Address Match Interrupt Enable Register
AIER
XXXX XX00b
XXXX XX00b
00h
020Fh Address Match Interrupt Enable Register 2
AIER2
0210h
0211h Address Match Interrupt Register 0
RMAD0
RMAD1
RMAD2
RMAD3
00h
0212h
X0h
0213h
0214h
00h
00h
X0h
0215h Address Match Interrupt Register 1
0216h
0217h
0218h
00h
00h
X0h
0219h Address Match Interrupt Register 2
021Ah
021Bh
021Ch
00h
00h
X0h
021Dh Address Match Interrupt Register 3
021Eh
021Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 31 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.10
SFR List (10)
Address
Register
Symbol
FMR0
Reset Value
0000 0001b (Other
than user boot mode)
0010 0001b (User boot
mode)
0220h Flash Memory Control Register 0
0221h Flash Memory Control Register 1
FMR1
FMR2
FMR3
00X0 XX0Xb
XXXX 0000b
XXXX 0000b
0222h Flash Memory Control Register 2
0223h Flash Memory Control Register 3
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h Flash Memory Control Register 6
FMR6
XX0X XX00b
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h UART0 Transmit/Receive Mode Register
0249h UART0 Bit Rate Register
U0MR
00h
XXh
U0BRG
024Ah
XXh
UART0 Transmit Buffer Register
024Bh
U0TB
XXh
024Ch UART0 Transmit/Receive Control Register 0
024Dh UART0 Transmit/Receive Control Register 1
U0C0
U0C1
0000 1000b
0000 0010b
XXh
024Eh
UART0 Receive Buffer Register
024Fh
U0RB
XXh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 32 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.11
SFR List (11)
Address
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
Register
Symbol
Reset Value
0258h UART1 Transmit/Receive Mode Register
0259h UART1 Bit Rate Register
U1MR
00h
XXh
U1BRG
025Ah
XXh
UART1 Transmit Buffer Register
025Bh
U1TB
XXh
025Ch UART1 Transmit/Receive Control Register 0
025Dh UART1 Transmit/Receive Control Register 1
U1C0
U1C1
0000 1000b
0000 0010b
XXh
025Eh
UART1 Receive Buffer Register
025Fh
U1RB
XXh
0260h
0261h
0262h
0263h
0264h UART2 Special Mode Register 4
0265h UART2 Special Mode Register 3
0266h UART2 Special Mode Register 2
0267h UART2 Special Mode Register
0268h UART2 Transmit/Receive Mode Register
0269h UART2 Bit Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
U2BRG
XXh
026Ah
XXh
UART2 Transmit Buffer Register
026Bh
U2TB
XXh
026Ch UART2 Transmit/Receive Control Register 0
026Dh UART2 Transmit/Receive Control Register 1
U2C0
U2C1
0000 1000b
0000 0010b
XXh
026Eh
UART2 Receive Buffer Register
026Fh
U2RB
XXh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 33 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.12
SFR List (12)
Address
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
Register
Symbol
Reset Value
0298h UART4 Transmit/Receive Mode Register
0299h UART4 Bit Rate Register
U4MR
00h
XXh
U4BRG
029Ah
XXh
UART4 Transmit Buffer Register
029Bh
U4TB
XXh
029Ch UART4 Transmit/Receive Control Register 0
029Dh UART4 Transmit/Receive Control Register 1
U4C0
U4C1
0000 1000b
0000 0010b
XXh
029Eh
UART4 Receive Buffer Register
029Fh
U4RB
XXh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h UART3 Transmit/Receive Mode Register
02A9h UART3 Bit Rate Register
U3MR
00h
XXh
U3BRG
02AAh
XXh
UART3 Transmit Buffer Register
02ABh
U3TB
XXh
02ACh UART3 Transmit/Receive Control Register 0
02ADh UART3 Transmit/Receive Control Register 1
U3C0
U3C1
0000 1000b
0000 0010b
XXh
02AEh
UART3 Receive Buffer Register
02AFh
U3RB
XXh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 34 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.13
SFR List (13)
Address
Register
Symbol
S00
Reset Value
XXh
02B0h I2C0 Data Shift Register
02B1h
02B2h I2C0 Address Register 0
02B3h I2C0 Control Register 0
02B4h I2C0 Clock Control Register
S0D0
S1D0
S20
0000 000Xb
0000 0000b
00h
02B5h I2C0 Start/Stop Condition Control Register
02B6h I2C0 Control Register 1
02B7h I2C0 Control Register 2
02B8h I2C0 Status Register 0
02B9h I2C0 Status Register 1
02BAh I2C0 Address Register 1
02BBh I2C0 Address Register 2
02BCh
S2D0
S3D0
S4D0
S10
0001 1010b
0011 0000b
0000 0000b
0001 000Xb
XXXX X000b
0000 000Xb
0000 000Xb
S11
S0D1
S0D2
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
XXh
XXh
Time Measurement Register 0
Waveform Generation Register 0
G1TM0
G1PO0
XXh
Time Measurement Register 1
Waveform Generation Register 1
G1TM1
G1PO1
XXh
XXh
Time Measurement Register 2
Waveform Generation Register 2
G1TM2
G1PO2
XXh
XXh
Time Measurement Register 3
Waveform Generation Register 3
G1TM3
G1PO3
XXh
XXh
Time Measurement Register 4
Waveform Generation Register 4
G1TM4
G1PO4
XXh
XXh
Time Measurement Register 5
Waveform Generation Register 5
G1TM5
G1PO5
XXh
XXh
Time Measurement Register 6
Waveform Generation Register 6
G1TM6
G1PO6
XXh
XXh
Time Measurement Register 7
Waveform Generation Register 7
G1TM7
G1PO7
XXh
02D0h Waveform Generation Control Register 0
02D1h Waveform Generation Control Register 1
02D2h Waveform Generation Control Register 2
02D3h Waveform Generation Control Register 3
02D4h Waveform Generation Control Register 4
02D5h Waveform Generation Control Register 5
02D6h Waveform Generation Control Register 6
02D7h Waveform Generation Control Register 7
02D8h Time Measurement Control Register 0
02D9h Time Measurement Control Register 1
02DAh Time Measurement Control Register 2
02DBh Time Measurement Control Register 3
02DCh Time Measurement Control Register 4
02DDh Time Measurement Control Register 5
02DEh Time Measurement Control Register 6
02DFh Time Measurement Control Register 7
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
0X00 XX00b
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 35 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.14
SFR List (14)
Address
02E0h
Register
Symbol
G1BT
Reset Value
XXh
XXh
00h
Base Timer Register
02E1h
02E2h Base Timer Control Register 0
02E3h Base Timer Control Register 1
02E4h Time Measurement Prescaler Register 6
02E5h Time Measurement Prescaler Register 7
02E6h Function Enable Register
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
00h
00h
00h
00h
02E7h Function Select Register
G1FS
00h
02E8h
XXh
XXh
00h
Base Timer Reset Register
02E9h
G1BTRR
G1DV
02EAh Count Source Divide Register
02EBh
02ECh Waveform Output Master Enable Register
G1OER
00h
02EDh
02EEh Timer S I/O Control Register 0
G1IOR0
G1IOR1
G1IR
00h
00h
XXh
00h
00h
02EFh Timer S I/O Control Register 1
02F0h Interrupt Request Register
02F1h Interrupt Enable Register 0
G1IE0
G1IE1
02F2h Interrupt Enable Register 1
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh NMI Digital Debounce Register
02FFh P1_7 Digital Debounce Register
NDDR
FFh
FFh
P17DDR
0300h
0301h
0302h
XXh
XXh
Timer A1-1 Register
0303h
TA11
TA21
TA41
0304h
XXh
Timer A2-1 Register
0305h
XXh
0306h
XXh
Timer A4-1 Register
0307h
XXh
0308h Three-Phase PWM Control Register 0
0309h Three-Phase PWM Control Register 1
030Ah Three-Phase Output Buffer Register 0
030Bh Three-Phase Output Buffer Register 1
030Ch Dead Time Timer
INVC0
INVC1
IDB0
00h
00h
XX11 1111b
XX11 1111b
XXh
IDB1
DTT
030Dh Timer B2 Interrupt Generating Frequency Set Counter
030Eh Position-Data-Retain Function Control Register
030Fh
ICTB2
PDRF
XXh
XXXX 0000b
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 36 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.15
SFR List (15)
Address
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
Register
Symbol
Reset Value
0318h Port Function Control Register
PFCR
0011 1111b
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0320h Count Start Flag
0321h
TABSR
00h
0322h One-Shot Start Flag
0323h Trigger Select Register
0324h Increment/Decrement Flag
0325h
ONSF
TRGSR
UDF
00h
00h
00h
0326h
XXh
XXh
Timer A0 Register
0327h
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
0328h
XXh
Timer A1 Register
0329h
XXh
032Ah
XXh
Timer A2 Register
032Bh
XXh
032Ch
XXh
Timer A3 Register
032Dh
XXh
032Eh
XXh
Timer A4 Register
032Fh
XXh
0330h
XXh
Timer B0 Register
0331h
XXh
0332h
XXh
Timer B1 Register
0333h
XXh
0334h
XXh
Timer B2 Register
0335h
XXh
0336h Timer A0 Mode Register
0337h Timer A1 Mode Register
0338h Timer A2 Mode Register
0339h Timer A3 Mode Register
033Ah Timer A4 Mode Register
033Bh Timer B0 Mode Register
033Ch Timer B1 Mode Register
033Dh Timer B2 Mode Register
033Eh Timer B2 Special Mode Register
033Fh
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00h
00h
00h
00h
00h
00XX 0000b
00XX 0000b
00XX 0000b
X000 0000b
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 37 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.16
SFR List (16)
Address
Register
Symbol
RTCSEC
RTCMIN
RTCHR
Reset Value
00h
0340h Real-Time Clock Second Data Register
0341h Real-Time Clock Minute Data Register
X000 0000b
XX00 0000b
XXXX X000b
0000 X00Xb
X000 0000b
XXX0 0000b
0342h Real-Time Clock Hour Data Register
0343h Real-Time Clock Day Data Register
RTCWK
RTCCR1
RTCCR2
RTCCSR
0344h Real-Time Clock Control Register 1
0345h Real-Time Clock Control Register 2
0346h Real-Time Clock Count Source Select Register
0347h
0348h Real-Time Clock Second Compare Data Register
RTCCSEC
RTCCMIN
RTCCHR
X000 0000b
X000 0000b
X000 0000b
0349h Real-Time Clock Minute Compare Data Register
034Ah Real-Time Clock Hour Compare Data Register
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h Pull-Up Control Register 0
PUR0
PUR1
PUR2
00h
00h
00h
0361h Pull-Up Control Register 1
0362h Pull-Up Control Register 2
0363h
0364h
0365h
0366h Port Control Register
PCR
0XX0 0XX0b
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 38 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.17
SFR List (17)
Address
Register
Symbol
PACR
Reset Value
0XXX X000b
0370h Pin Assignment Control Register
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
(1)
Count Source Protect Mode Register
037Ch
CSPR
WDTR
WDTS
WDC
00h
037Dh Watchdog Timer Refresh Register
XXh
XXh
037Eh Watchdog Timer Start Register
037Fh Watchdog Timer Control Register
00XX XXXXb
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h DMA2 Source Select Register
DM2SL
DM3SL
00h
00h
0391h
0392h DMA3 Source Select Register
0393h
0394h
0395h
0396h
0397h
0398h DMA0 Source Select Register
DM0SL
DM1SL
00h
00h
0399h
039Ah DMA1 Source Select Register
039Bh
039Ch
039Dh
039Eh
039Fh
X: Undefined
Blanks are reserved. No access is allowed.
Note:
1. When the CSPROINI bit of the OFS1 address is 0, the reset value is 1000 0000b.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 39 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.18
SFR List (18)
Address
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
Register
Symbol
Reset Value
XXXX XXXXb
00XX XXXXb
0XXX XXX0b
SFR Snoop Address Register
CRCSAR
CRCMR
03B5h
03B6h CRC Mode Register
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
XXh
XXh
XXh
CRC Data Register
03BDh
CRCD
CRCIN
03BEh CRC Input Register
03BFh
03C0h
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
A/D Register 0
03C1h
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
03C2h
A/D Register 1
03C3h
03C4h
A/D Register 2
03C5h
03C6h
A/D Register 3
03C7h
03C8h
A/D Register 4
03C9h
03CAh
A/D Register 5
03CBh
03CCh
A/D Register 6
03CDh
03CEh
A/D Register 7
03CFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 40 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.19
SFR List (19)
Address
03D0h
03D1h
Register
Symbol
Reset Value
03D2h A/D Trigger Control Register
ADTRGCON
ADCON2
XXXX 00XXb
0000 X00Xb
03D3h
03D4h A/D Control Register 2
03D5h
03D6h A/D Control Register 0
ADCON0
ADCON1
0000 0XXXb
0000 X000b
03D7h A/D Control Register 1
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h Port P0 Register
03E1h Port P1 Register
03E2h Port P0 Direction Register
03E3h Port P1 Direction Register
03E4h Port P2 Register
03E5h Port P3 Register
03E6h Port P2 Direction Register
03E7h Port P3 Direction Register
03E8h
P0
P1
XXh
XXh
00h
00h
XXh
XXh
00h
00h
PD0
PD1
P2
P3
PD2
PD3
03E9h
03EAh
03EBh
03ECh Port P6 Register
03EDh Port P7 Register
03EEh Port P6 Direction Register
03EFh Port P7 Direction Register
03F0h Port P8 Register
03F1h Port P9 Register
03F2h Port P8 Direction Register
03F3h Port P9 Direction Register
03F4h Port P10 Register
03F5h
P6
P7
XXh
XXh
PD6
PD7
P8
00h
00h
XXh
P9
XXh
PD8
PD9
P10
00h
000X 0000b
XXh
03F6h Port P10 Direction Register
03F7h
PD10
00h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
0400h to
D4FFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 41 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.20
SFR List (20)
Address
D500h
D501h
D502h
D503h
D504h
D505h
D506h
D507h
D508h
D509h
D50Ah
D50Bh
D50Ch
D50Dh
D50Eh
D50Fh
D510h
D511h
D512h
D513h
D514h
D515h
D516h
D517h
D518h
D519h
D51Ah
D51Bh
D51Ch
D51Dh
D51Eh
D51Fh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 0: Message Identifier
CAN0 Mailbox 0: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB0
CAN0 Mailbox 0: Data Field
CAN0 Mailbox 0: Time Stamp
CAN0 Mailbox 1: Message Identifier
CAN0 Mailbox 1: Data Length
CAN0 Mailbox 1: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB1
CAN0 Mailbox 1: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 42 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.21
SFR List (21)
Address
D520h
D521h
D522h
D523h
D524h
D525h
D526h
D527h
D528h
D529h
D52Ah
D52Bh
D52Ch
D52Dh
D52Eh
D52Fh
D530h
D531h
D532h
D533h
D534h
D535h
D536h
D537h
D538h
D539h
D53Ah
D53Bh
D53Ch
D53Dh
D53Eh
D53Fh
D540h
D541h
D542h
D543h
D544h
D545h
D546h
D547h
D548h
D549h
D54Ah
D54Bh
D54Ch
D54Dh
D54Eh
D54Fh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 2: Message Identifier
CAN0 Mailbox 2: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB2
CAN0 Mailbox 2: Data Field
CAN0 Mailbox 2: Time Stamp
CAN0 Mailbox 3: Message Identifier
CAN0 Mailbox 3: Data Length
CAN0 Mailbox 3: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB3
CAN0 Mailbox 3: Time Stamp
CAN0 Mailbox 4: Message Identifier
CAN0 Mailbox 4: Data Length
CAN0 Mailbox 4: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB4
CAN0 Mailbox 4: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 43 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.22
SFR List (22)
Address
D550h
D551h
D552h
D553h
D554h
D555h
D556h
D557h
D558h
D559h
D55Ah
D55Bh
D55Ch
D55Dh
D55Eh
D55Fh
D560h
D561h
D562h
D563h
D564h
D565h
D566h
D567h
D568h
D569h
D56Ah
D56Bh
D56Ch
D56Dh
D56Eh
D56Fh
D570h
D571h
D572h
D573h
D574h
D575h
D576h
D577h
D578h
D579h
D57Ah
D57Bh
D57Ch
D57Dh
D57Eh
D57Fh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 5: Message Identifier
CAN0 Mailbox 5: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB5
CAN0 Mailbox 5: Data Field
CAN0 Mailbox 5: Time Stamp
CAN0 Mailbox 6: Message Identifier
CAN0 Mailbox 6: Data Length
CAN0 Mailbox 6: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB6
CAN0 Mailbox 6: Time Stamp
CAN0 Mailbox 7: Message Identifier
CAN0 Mailbox 7: Data Length
CAN0 Mailbox 7: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB7
CAN0 Mailbox 7: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 44 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.23
SFR List (23)
Address
D580h
D581h
D582h
D583h
D584h
D585h
D586h
D587h
D588h
D589h
D58Ah
D58Bh
D58Ch
D58Dh
D58Eh
D58Fh
D590h
D591h
D592h
D593h
D594h
D595h
D596h
D597h
D598h
D599h
D59Ah
D59Bh
D59Ch
D59Dh
D59Eh
D59Fh
D5A0h
D5A1h
D5A2h
D5A3h
D5A4h
D5A5h
D5A6h
D5A7h
D5A8h
D5A9h
D5AAh
D5ABh
D5ACh
D5ADh
D5AEh
D5AFh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 8: Message Identifier
CAN0 Mailbox 8: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB8
CAN0 Mailbox 8: Data Field
CAN0 Mailbox 8: Time Stamp
CAN0 Mailbox 9: Message Identifier
CAN0 Mailbox 9: Data Length
CAN0 Mailbox 9: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB9
CAN0 Mailbox 9: Time Stamp
CAN0 Mailbox 10: Message Identifier
CAN0 Mailbox 10: Data Length
CAN0 Mailbox 10: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB10
CAN0 Mailbox 10: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 45 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.24
SFR List (24)
Address
D5B0h
D5B1h
D5B2h
D5B3h
D5B4h
D5B5h
D5B6h
D5B7h
D5B8h
D5B9h
D5BAh
D5BBh
D5BCh
D5BDh
D5BEh
D5BFh
D5C0h
D5C1h
D5C2h
D5C3h
D5C4h
D5C5h
D5C6h
D5C7h
D5C8h
D5C9h
D5CAh
D5CBh
D5CCh
D5CDh
D5CEh
D5CFh
D5D0h
D5D1h
D5D2h
D5D3h
D5D4h
D5D5h
D5D6h
D5D7h
D5D8h
D5D9h
D5DAh
D5DBh
D5DCh
D5DDh
D5DEh
D5DFh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 11: Message Identifier
CAN0 Mailbox 11: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB11
CAN0 Mailbox 11: Data Field
CAN0 Mailbox 11: Time Stamp
CAN0 Mailbox 12: Message Identifier
CAN0 Mailbox 12: Data Length
CAN0 Mailbox 12: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB12
CAN0 Mailbox 12: Time Stamp
CAN0 Mailbox 13: Message Identifier
CAN0 Mailbox 13: Data Length
CAN0 Mailbox 13: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB13
CAN0 Mailbox 13: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 46 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.25
SFR List (25)
Address
D5E0h
D5E1h
D5E2h
D5E3h
D5E4h
D5E5h
D5E6h
D5E7h
D5E8h
D5E9h
D5EAh
D5EBh
D5ECh
D5EDh
D5EEh
D5EFh
D5F0h
D5F1h
D5F2h
D5F3h
D5F4h
D5F5h
D5F6h
D5F7h
D5F8h
D5F9h
D5FAh
D5FBh
D5FCh
D5FDh
D5FEh
D5FFh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 14: Message Identifier
CAN0 Mailbox 14: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB14
CAN0 Mailbox 14: Data Field
CAN0 Mailbox 14: Time Stamp
CAN0 Mailbox 15: Message Identifier
CAN0 Mailbox 15: Data Length
CAN0 Mailbox 15: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB15
CAN0 Mailbox 15: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 47 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.26
SFR List (26)
Address
D600h
D601h
D602h
D603h
D604h
D605h
D606h
D607h
D608h
D609h
D60Ah
D60Bh
D60Ch
D60Dh
D60Eh
D60Fh
D610h
D611h
D612h
D613h
D614h
D615h
D616h
D617h
D618h
D619h
D61Ah
D61Bh
D61Ch
D61Dh
D61Eh
D61Fh
D620h
D621h
D622h
D623h
D624h
D625h
D626h
D627h
D628h
D629h
D62Ah
D62Bh
D62Ch
D62Dh
D62Eh
D62Fh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 16: Message Identifier
CAN0 Mailbox 16: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB16
CAN0 Mailbox 16: Data Field
CAN0 Mailbox 16: Time Stamp
CAN0 Mailbox 17: Message Identifier
CAN0 Mailbox 17: Data Length
CAN0 Mailbox 17: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB17
CAN0 Mailbox 17: Time Stamp
CAN0 Mailbox 18: Message Identifier
CAN0 Mailbox 18: Data Length
CAN0 Mailbox 18: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB18
CAN0 Mailbox 18: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 48 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.27
SFR List (27)
Address
D630h
D631h
D632h
D633h
D634h
D635h
D636h
D637h
D638h
D639h
D63Ah
D63Bh
D63Ch
D63Dh
D63Eh
D63Fh
D640h
D641h
D642h
D643h
D644h
D645h
D646h
D647h
D648h
D649h
D64Ah
D64Bh
D64Ch
D64Dh
D64Eh
D64Fh
D650h
D651h
D652h
D653h
D654h
D655h
D656h
D657h
D658h
D659h
D65Ah
D65Bh
D65Ch
D65Dh
D65Eh
D65Fh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 19: Message Identifier
CAN0 Mailbox 19: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB19
CAN0 Mailbox 19: Data Field
CAN0 Mailbox 19: Time Stamp
CAN0 Mailbox 20: Message Identifier
CAN0 Mailbox 20: Data Length
CAN0 Mailbox 20: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB20
CAN0 Mailbox 20: Time Stamp
CAN0 Mailbox 21: Message Identifier
CAN0 Mailbox 21: Data Length
CAN0 Mailbox 21: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB21
CAN0 Mailbox 21: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 49 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.28
SFR List (28)
Address
D660h
D661h
D662h
D663h
D664h
D665h
D666h
D667h
D668h
D669h
D66Ah
D66Bh
D66Ch
D66Dh
D66Eh
D66Fh
D670h
D671h
D672h
D673h
D674h
D675h
D676h
D677h
D678h
D679h
D67Ah
D67Bh
D67Ch
D67Dh
D67Eh
D67Fh
D680h
D681h
D682h
D683h
D684h
D685h
D686h
D687h
D688h
D689h
D68Ah
D68Bh
D68Ch
D68Dh
D68Eh
D68Fh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 22: Message Identifier
CAN0 Mailbox 22: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB22
CAN0 Mailbox 22: Data Field
CAN0 Mailbox 22: Time Stamp
CAN0 Mailbox 23: Message Identifier
CAN0 Mailbox 23: Data Length
CAN0 Mailbox 23: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB23
CAN0 Mailbox 23: Time Stamp
CAN0 Mailbox 24: Message Identifier
CAN0 Mailbox 24: Data Length
CAN0 Mailbox 24: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB24
CAN0 Mailbox 24: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 50 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.29
SFR List (29)
Address
D690h
D691h
D692h
D693h
D694h
D695h
D696h
D697h
D698h
D699h
D69Ah
D69Bh
D69Ch
D69Dh
D69Eh
D69Fh
D6A0h
D6A1h
D6A2h
D6A3h
D6A4h
D6A5h
D6A6h
D6A7h
D6A8h
D6A9h
D6AAh
D6ABh
D6ACh
D6ADh
D6AEh
D6AFh
D6B0h
D6B1h
D6B2h
D6B3h
D6B4h
D6B5h
D6B6h
D6B7h
D6B8h
D6B9h
D6BAh
D6BBh
D6BCh
D6BDh
D6BEh
D6BFh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 25: Message Identifier
CAN0 Mailbox 25: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB25
CAN0 Mailbox 25: Data Field
CAN0 Mailbox 25: Time Stamp
CAN0 Mailbox 26: Message Identifier
CAN0 Mailbox 26: Data Length
CAN0 Mailbox 26: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB26
CAN0 Mailbox 26: Time Stamp
CAN0 Mailbox 27: Message Identifier
CAN0 Mailbox 27: Data Length
CCAN0 Mailbox 27: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB27
CAN0 Mailbox 27: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 51 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.30
SFR List (30)
Address
D6C0h
D6C1h
D6C2h
D6C3h
D6C4h
D6C5h
D6C6h
D6C7h
D6C8h
D6C9h
D6CAh
D6CBh
D6CCh
D6CDh
D6CEh
D6CFh
D6D0h
D6D1h
D6D2h
D6D3h
D6D4h
D6D5h
D6D6h
D6D7h
D6D8h
D6D9h
D6DAh
D6DBh
D6DCh
D6DDh
D6DEh
D6DFh
D6E0h
D6E1h
D6E2h
D6E3h
D6E4h
D6E5h
D6E6h
D6E7h
D6E8h
D6E9h
D6EAh
D6EBh
D6ECh
D6EDh
D6EEh
D6EFh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 28: Message Identifier
CAN0 Mailbox 28: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB28
CAN0 Mailbox 28: Data Field
CAN0 Mailbox 28: Time Stamp
CAN0 Mailbox 29: Message Identifier
CAN0 Mailbox 29: Data Length
CAN0 Mailbox 29: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB29
CAN0 Mailbox 29: Time Stamp
CAN0 Mailbox 30: Message Identifier
CAN0 Mailbox 30: Data Length
CAN0 Mailbox 30: Data Field
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB30
CAN0 Mailbox 30: Time Stamp
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 52 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.31
SFR List (31)
Address
D6F0h
D6F1h
D6F2h
D6F3h
D6F4h
D6F5h
D6F6h
D6F7h
D6F8h
D6F9h
D6FAh
D6FBh
D6FCh
D6FDh
D6FEh
D6FFh
D700h
D701h
D702h
D703h
D704h
D705h
D706h
D707h
D708h
D709h
D70Ah
D70Bh
D70Ch
D70Dh
D70Eh
D70Fh
D710h
D711h
D712h
D713h
D714h
D715h
D716h
D717h
D718h
D719h
D71Ah
D71Bh
D71Ch
D71Dh
D71Eh
D71Fh
X: Undefined
Register
Symbol
Reset Value
XXh
XXh
CAN0 Mailbox 31: Message Identifier
CAN0 Mailbox 31: Data Length
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0MB31
CAN0 Mailbox 31: Data Field
CAN0 Mailbox 31: Time Stamp
CAN0 Mask Register 0
C0MKR0
C0MKR1
C0MKR2
C0MKR3
C0MKR4
C0MKR5
C0MKR6
C0MKR7
CAN0 Mask Register 1
CAN0 Mask Register 2
CAN0 Mask Register 3
CAN0 Mask Register 4
CAN0 Mask Register 5
CAN0 Mask Register 6
CAN0 Mask Register 7
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 53 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.32
SFR List (32)
Address
D720h
D721h
D722h
D723h
D724h
D725h
D726h
D727h
D728h
D729h
D72Ah
D72Bh
D72Ch
D72Dh
D72Eh
D72Fh
D730h
D731h
D732h
D733h
D734h
D735h
D736h
D737h
D738h
D739h
D73Ah
D73Bh
D73Ch
D73Dh
D73Eh
D73Fh
D740h
D741h
D742h
D743h
D744h
D745h
D746h
D747h
D748h
D749h
D74Ah
D74Bh
D74Ch
D74Dh
D74Eh
D74Fh
Register
Symbol
Reset Value
XXh
XXh
CAN0 FIFO Receive ID Compare Register 0
CAN0 FIFO Receive ID Compare Register 1
CAN0 Mask Invalid Register
C0FIDCR0
XXh
XXh
XXh
XXh
C0FIDCR1
C0MKIVLR
C0MIER
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Mailbox Interrupt Enable Register
XXh
XXh
D750h to
D77Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 54 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.33
SFR List (33)
Address
D780h
D781h
D782h
D783h
D784h
D785h
D786h
D787h
D788h
D789h
D78Ah
D78Bh
D78Ch
D78Dh
D78Eh
D78Fh
D790h
D791h
D792h
D793h
D794h
D795h
D796h
D797h
D798h
D799h
D79Ah
D79Bh
D79Ch
D79Dh
D79Eh
D79Fh
D7A0h
D7A1h
D7A2h
D7A3h
D7A4h
D7A5h
D7A6h
D7A7h
D7A8h
D7A9h
Register
Symbol
Reset Value
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
D7AAh CAN0 Message Control Register 10
D7ABh CAN0 Message Control Register 11
D7ACh CAN0 Message Control Register 12
D7ADh CAN0 Message Control Register 13
D7AEh CAN0 Message Control Register 14
D7AFh
CAN0 Message Control Register 15
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 55 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.34
SFR List (34)
Address
D7B0h
D7B1h
D7B2h
D7B3h
D7B4h
D7B5h
D7B6h
D7B7h
D7B8h
D7B9h
Register
Symbol
Reset Value
00h
CAN0 Message Control Register 16
CAN0 Message Control Register 17
CAN0 Message Control Register 18
CAN0 Message Control Register 19
CAN0 Message Control Register 20
CAN0 Message Control Register 21
CAN0 Message Control Register 22
CAN0 Message Control Register 23
CAN0 Message Control Register 24
CAN0 Message Control Register 25
C0MCTL16
C0MCTL17
C0MCTL18
C0MCTL19
C0MCTL20
C0MCTL21
C0MCTL22
C0MCTL23
C0MCTL24
C0MCTL25
C0MCTL26
C0MCTL27
C0MCTL28
C0MCTL29
C0MCTL30
C0MCTL31
00h
00h
00h
00h
00h
00h
00h
00h
00h
D7BAh CAN0 Message Control Register 26
D7BBh CAN0 Message Control Register 27
D7BCh CAN0 Message Control Register 28
D7BDh CAN0 Message Control Register 29
D7BEh CAN0 Message Control Register 30
00h
00h
00h
00h
00h
D7BFh
D7C0h
D7C1h
D7C2h
D7C3h
D7C4h
D7C5h
D7C6h
D7C7h
D7C8h
D7C9h
CAN0 Message Control Register 31
00h
0000 0101b
00h
CAN0 Control Register
C0CTLR
C0STR
0000 0101b
00h
CAN0 Status Register
00h
CAN0 Bit Configuration Register
C0BCR
00h
00h
CAN0 Clock Select Register
C0CLKR
C0RFCR
C0RFPCR
C0TFCR
C0TFPCR
C0EIER
00h
CAN0 Receive FIFO Control Register
CAN0 Receive FIFO Pointer Control Register
1000 0000b
XXh
D7CAh CAN0 Transmit FIFO Control Register
D7CBh CAN0 Transmit FIFO pointer Control Register
D7CCh CAN0 Error Interrupt Enable Register
D7CDh CAN0 Error Interrupt Source Judge Register
D7CEh CAN0 Receive Error Count Register
D7CFh CAN0 Transmit Error Count Register
1000 0000b
XXh
00h
C0EIFR
00h
C0RECR
C0TECR
C0ECSR
C0CSSR
C0MSSR
C0MSMR
00h
00h
D7D0h
D7D1h
D7D2h
D7D3h
D7D4h
D7D5h
D7D6h
D7D7h
D7D8h
D7D9h
D7DAh
D7DBh
D7DCh
D7DDh
D7DEh
D7DFh
X: Undefined
CAN0 Error Code Store Register
00h
CAN0 Channel Search Support Register
CAN0 Mailbox Search Status Register
CAN0 Mailbox Search Mode Register
XXh
1000 0000b
0000 0000b
00h
CAN0 Time Stamp Register
C0TSR
00h
XXh
CAN0 Acceptance Filter Support Register
CAN0 Test Control Register
C0AFSR
C0TCR
XXh
00h
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 56 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
Table 4.35
SFR List (35)
Address
D7E0h
D7E1h
D7E2h
D7E3h
D7E4h
D7E5h
D7E6h
D7E7h
D7E8h
D7E9h
D7EAh
D7EBh
D7ECh
D7EDh
D7EEh
D7EFh
D7F0h
D7F1h
D7F2h
D7F3h
D7F4h
D7F5h
D7F6h
D7F7h
D7F8h
D7F9h
D7FAh
D7FBh
D7FCh
D7FDh
D7FEh
D7FFh
X: Undefined
Register
Symbol
Reset Value
Blanks are reserved. No access is allowed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 57 of 83
M16C/5LD Group, M16C/56D Group
4. Special Function Registers (SFRs)
4.2
4.2.1
Notes on SFRs
Register Settings
Table 4.36 lists Registers with Write-Only Bits and registers whose function differs between reading and
writing. Set these registers with immediate values. When establishing the next value by altering the
existing value, write the existing value to the RAM as well as to the registers. Transfer the next value to
the register after making changes in the RAM.
Table 4.36
Registers with Write-Only Bits
Address
Register Name
UART0 Bit Rate Register
Symbol
U0BRG
U0TB
U1BRG
U1TB
U2BRG
U2TB
U4BRG
U4TB
U3BRG
U3TB
S3D0
S10
0249h
024Bh to 024Ah
0259h
UART0 Transmit Buffer Register
UART1 Bit Rate Register
025Bh to 025Ah
0269h
UART1 Transmit Buffer Register
UART2 Bit Rate Register
026Bh to 026Ah
0299h
UART2 Transmit Buffer Register
UART4 Bit Rate Register
029Bh to 029Ah
02A9h
UART4 Transmit Buffer Register
UART3 Bit Rate Register
02ABh to 02AAh
02B6h
UART3 Transmit Buffer Register
I2C0 Control Register 1
02B8h
I2C0 Status Register 0
0303h to 0302h
0305h to 0304h
0307h to 0306h
030Ah
TA11
Timer A1-1 Register
TA21
Timer A2-1 Register
TA41
Timer A4-1 Register
IDB0
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
030Bh
IDB1
030Ch
DTT
030Dh
ICTB2
TA0
Timer B2 Interrupt Generating Frequency Set Counter
Timer A0 Register
0327h to 0326h
0329h to 0328h
032Bh to 032Ah
032Dh to 032Ch
032Fh to 032Eh
037Dh
TA1
Timer A1 Register
TA2
Timer A2 Register
TA3
Timer A3 Register
TA4
Timer A4 Register
WDTR
WDTS
C0RFPCR
C0TFPCR
Watchdog Timer Refresh Register
Watchdog Timer Start Register
CAN0 Receive FIFO Pointer Control Register
CAN0 Transmit FIFO pointer Control Register
037Eh
D7C9h
D7CBh
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 58 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5. Electrical Characteristics
5.1
5.1.1
Electrical Characteristics (Common to 3 V and 5 V)
Absolute Maximum Rating
Table 5.1
Absolute Maximum Ratings
Symbol
Characteristic
Condition
Value
Unit
V
V
Supply voltage
V
= AV
= AV
-0.3 to 6.5
-0.3 to 6.5
CC
CC
CC
CC
AV
Analog supply voltage
V
V
CC
CC
−0.3 to V + 0.1 (1)
V
Analog reference voltage
V
REF
CC
V
Input voltage P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to
P8_7, P9_0 to P9_3, P9_5
to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS,
VREF
I
-0.3 to VCC + 0.3
V
V
P
Output
voltage
P0_0 to P0_7, P1_0 to
P1_7, P2_0 to P2_7, P3_0
to P3_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to
P8_7, P9_0 to P9_3, P9_5
to P9_7, P10_0 to P10_7
XOUT
O
-0.3 to VCC + 0.3
V
Power
consumption
d
-40°C ≤ T ≤ 85°C
300
mW
opr
T
Operating
temperature
range
While CPU operation
-40 to 85
0 to 60
opr
While flash memory
program and erase
operation
Programming area
Data area
°C
°C
-40 to 85
T
Storage temperature range
-65 to 150
stg
Note:
1. Maximum value is 6.5 V.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 59 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.1.2
Recommended Operating Conditions
Table 5.2
Operating Conditions (1)
VCC = 2.7 V to 5.5 V, Topr = -40 to 85 °C unless otherwise specified.
Symbol Characteristic
VCC
Value
Unit
Min.
3.0
Typ.
Max.
5.5
Supply voltage
V
V
V
V
AVCC
VSS
Analog supply voltage
Ground voltage
VCC
0
AVSS
VIH
Analog ground voltage
0
High level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
0.7 VCC
VCC
input voltage to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
V
XIN, RESET, CNVSS
0.8 VCC
0.7 VCC
2.1
VCC
VCC
VCC
When I2C-bus input level selected
SDAMM, SCLMM
V
V
When SMBUS input level selected
VIL
Low level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
0.3 VCC
input voltage to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
0
V
XIN, RESET, CNVSS
0.2 VCC
0.3 VCC
0.8
0
0
0
V
V
V
When I2C-bus input level selected
SDAMM, SCLMM
When SMBUS input level selected
IOH(sum)
High peak Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to
80.0
output
current
mA
mA
P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to
P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7
IOH(peak)
High level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
peak output to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
-10.0
P9_7, P10_0 to P10_7
current
IOH(avg)
High level
average
output
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
-5.0
mA
current (1)
IOL(sum)
Low peak
output
current
Sum of IOL(peak) atP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0
to P9_3, P9_5 to P9_7, P10_0 to P10_7
-80.0
10.0
mA
mA
IOL(peak)
Low level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
peak output to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
current
P9_7, P10_0 to P10_7
IOL(avg)
Low level
average
output
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
5.0
mA
current (1)
Main clock input oscillation frequency (2)
Sub clock oscillation oscillator frequency
f(XIN)
2
20
50
25
32
32
2
MHz
kHz
f(XCIN)
f(PLL)
32.768
PLL clock oscillation frequency (2)
10
10
2
VCC = 2.7 V to 5.5 V
VCC = 3.0 V to 5.5 V
MHz
MHz
ms
f(BCLK)
tsu(PLL)
CPU operation frequency
Wait time to stabilize PLL frequency
synthesizer
VCC = 5.0 V
VCC = 3.0 V
3
Notes:
1.
2.
The mean output current is the mean value within 100ms.
Refer to “Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency”” for the relationship between main
clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 60 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
PLL clock oscillation frequency
Main clock input oscillation frequency
32.0
25.0
20.0
10.0
10.0
0.0
2.0
0.0
2.7 3.0
5.5
2.7
5.5
Vcc [V] (main clock: no division)
Vcc [V] (PLL clock oscillation)
Figure 5.1
Table 5.3
Main clock input oscillation frequency, PLL clock oscillation frequency
(1)
Recommended Operating Conditions (2/2)
VCC = 2.7 to 5.5 V, VSS = 0 V, and Topr = -40 to 85°C unless otherwise specified.
The ripple voltage must not excess Vr(VCC) and/or dVr(VCC)/dt.
Standard
Typ.
Symbol
Vr(VCC)
Parameter
Unit
Min.
Max.
0.5
Allowable ripple voltage
Vp-p
Vp-p
V/ms
V/ms
VCC = 5.0 V
VCC = 3.0 V
VCC = 5.0 V
VCC = 3.0 V
0.3
0.3
0.3
dVr(VCC)/dt Ripple voltage falling gradient
Note:
1. The device is operationally guaranteed under these operating conditions.
V CC
Vr(VCC)
Figure 5.2
Ripple Waveform
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 61 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.1.3
A/D Conversion Characteristics
.
(1, 3)
Table 5.4
A/D Conversion Characteristics
V
= AV = V
= 3.0 to 5.5 V, V = AV = 0 V at T = -40 to 85°C unless otherwise specified
SS SS opr
CC
Symbol
—–
CC
REF
Standard
Typ.
Parameter
Measuring Condition
Unit
Min.
Max.
10
Resolution
VREF = VCC
Bits
LSB
LSB
LSB
LSB
Integral Non-Linearity Error
VREF = VCC = 5.0 V (2)
VREF = VCC = 3.3 V (2)
VREF = VCC = 5.0 V (2)
INL
±3
±5
±3
±5
—–
φAD
Absolute Accuracy
VREF = VCC = 3.3 V (2)
4.0 V ≤ VCC ≤ 5.5 V
3.2 V ≤ VCC ≤ 4.0 V
3.0 V ≤ VCC ≤ 3.2 V
A/D operating clock frequency
2
2
2
25
16
10
MHz
MHz
MHz
kΩ
—–
Tolerance Level Impedance
3
(2)
(2)
(2)
DNL
±1
±3
±3
LSB
Differential Non-Linearity Error
—–
LSB
LSB
μs
Offset Error
—–
Gain Error
tCONV
10-bit Conversion Time
VREF = VCC = 5V,
1.60
φAD = 25 MHz
tsamp
VREF
VIA
Sampling time
0.6
3.0
0
μs
V
Reference Voltage
Analog Input Voltage (4)
VCC
VREF
V
Notes:
1. Use when AV = V
CC
CC
2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input
ports and connect them to V . See Figure 5.3 “A/D Accuracy Measure Circuit”.
SS
3. This applies when using A/D1 circuits, with the ADSTBY bit for the unused A/D converter set to 0
(A/D operation stopped (standby)).
4. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
AN
Analog input
P0 to P10
AN: One of the analog input pin
P0 to P10: I/O pins other than AN
Figure 5.3
A/D Accuracy Measure Circuit
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 62 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.1.4
Flash Memory Electrical Characteristics
Table 5.5
CPU Clock When Operating Flash Memory (f(BCLK))
VCC = 2.7 to 5.5 V, at Topr = -40 to 85°C unless otherwise specified.
Standard
Unit
Symbol
Parameter
CPU rewrite mode
Conditions
Min.
Typ.
Max.
10 (1)
5 (3)
35
-
MHz
MHz
kHz
f(SLOW_R)
Slow read mode
-
-
Low current consumption read mode
fC(32.768)
16 (2)
20 (2)
2.7 V < VCC ≤ 3.0 V
3.0 V < VCC ≤ 5.5 V
Data flash read
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub
clock as the CPU clock source, a wait is not necessary.
Table 5.6
Flash Memory (Program ROM 1, 2) Electrical Characteristics
VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
Standard
Typ.
Symbol
Parameter
Conditions
Unit
Min.
Max.
Program and erase cycles (1, 3, 4)
Two words program time
Lock bit program time
1,000 (2)
-
-
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
times
μs
150
70
4000
3000
3.0
V
CC = 3.3 V, Topr = 25°C
CC = 3.3 V, Topr = 25°C
μs
-
Block erase time
V
0.2
s
td(SR-SUS)
Time delay from suspend request
until suspend
5 + CPU clock
× 3 cycles
ms
-
-
-
Interval from erase start/restart
until following suspend request
0
μs
Suspend interval necessary for
auto-erasure to complete (7)
ms
20
Time from suspend until erase
restart
30 + CPU
clock × 1 cycle
μs
-
Program, erase voltage
Read voltage
2.7
2.7
0
5.5
5.5
60
V
V
-
Topr= -40 to 85°C
-
Program, erase temperature
°C
μs
tPS
-
Flash Memory Circuit Stabilization Wait Time
Ambient temperature = 55°C
50
Data hold time (6)
20
year
Notes:
1.
Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 1,000),
each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word data 16,384 times, each to
a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once
without erasing the block (rewrite prohibited).
2.
3.
Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. It is advisable to
retain data on the erasure cycles of each block and limit the number of erase operations to a certain number.
If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
4.
5.
6.
7.
Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
The data hold time includes time that the power supply is off or the clock is not supplied.
After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase
sequence cannot be completed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 63 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
Table 5.7
Flash Memory (Data Flash) Electrical Characteristics
VCC = 2.7 to 5.5 V at Topr = -40 to 85°C, unless otherwise specified.
Standard
Unit
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Program and erase cycles (1, 3, 4)
Two words program time
Lock bit program time
10,000 (2)
-
-
-
-
VCC = 3.3 V, Topr = 25°C
VCC = 3.3 V, Topr = 25°C
times
μs
300
140
0.2
4000
3000
3.0
VCC = 3.3 V, Topr = 25°C
μs
Block erase time
VCC = 3.3 V, Topr = 25°C
s
td(SR-SUS)
Time delay from suspend request
until suspend
5 + CPU clock
× 3 cycles
ms
-
-
-
Interval from erase start/restart until
following suspend request
0
μs
Suspend interval necessary for
auto-erasure to complete (7)
ms
20
Time from suspend until erase
restart
30 + CPU
clock × 1 cycle
μs
-
Program, erase voltage
Read voltage
2.7
2.7
−40
5.5
5.5
85
V
V
-
-
Program, erase temperature
°C
μs
tPS
Flash Memory Circuit Stabilization Wait Time
Ambient temperature = 55 °C
50
Data hold time (6)
-
20
year
Notes:
1. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program and erase failure rate information should contact their Renesas technical support
representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7.
After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request,
the erase sequence cannot be completed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 64 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.1.5
Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.8
Voltage Detector 0 Electrical Characteristics
The measurement condition is VCC = 2.7 to 5.5 V, Topr = -40 to 85°C, unless otherwise specified.
Standard
Symbol
Vdet0
Parameter
Condition
Unit
V
Min.
2.70
Typ. Max.
Voltage detection level Vdet0
When VCC is falling.
2.85
3.00
td(E-A)
Waiting time until voltage detector operation
starts (1)
100
μs
Notes:
1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
Table 5.9
Voltage Detector 2 Electrical Characteristics
The measurement condition is VCC = 2.7 to 5.5 V, Topr = -40 to 85°C, unless otherwise specified.
Standard
Symbol
Vdet2
Parameter
Condition
Unit
V
Min.
3.51
Typ. Max.
When VCC is falling
3.81
4.11
Voltage detection level Vdet2_4
-
Hysteresis width at the rising of VCC in voltage
detector 2
0.15
V
Waiting time until voltage detector operation starts (1)
td(E-A)
100
μs
1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 65 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
Table 5.10
Power-On Reset Circuit
The measurement condition is Topr = -40 to 85°C, unless otherwise specified.
Standard
Unit
Symbol
trth
Parameter
Condition
Min.
2.0
Typ.
Max.
External power VCC rise gradient
External power VCC fall gradient
50000 mV/ms
50000 mV/ms
tfth
Voltage at which power-on reset enabled (1)
Hold time at which power-on reset enabled
Vpor
tw(por)
0.1
V
1.0
ms
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address
to 0.
Vdet0
Vdet0
trth
trth
V
CC
External Power
tfth
Vpor
tw(por)
Internal
reset signal
1
1
× 128
× 128
fOCO-S
fOCO-S
Figure 5.4
Table 5.11
Power-On Reset Circuit Electrical Characteristics
Power Supply Circuit Timing Characteristics
Standard
Symbol
td(P-R)
Parameter
Measuring Condition
Unit
ms
Min. Typ. Max.
Time for Internal Power Supply Stabilization VCC = 3.0 V to 5.5V
During Powering-On
5
td(R-S)
STOP Release Time
300
150
μs
μs
td(W-S)
Low Power Mode Wait Mode Release Time
Note:
1. When V
= 5 V.
CC
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 66 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
Recommended
operating
voltage
td(P-R)
VCC
Time to stabilize internal supply
voltage during powering-on
td(P-R)
CPU clock
(a) Interrupt to exit fromstop mode
(b) Interrupt to exit fromwait mode
td(R-S)
STOPrelease time
td(W-S)
Low power consumption
mode wait mode exit time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
td(E-A)
VC25, VC27
Low voltage detection
circuit operation start time
Stop
Operate
Low voltage detection circuit
td(E-A)
Figure 5.5
Power Supply Circuit Timing Diagram
5.1.6
Oscillation Circuit Electrical Characteristics
Table 5.12
125kHz On-chip Oscillator Oscillation Circuit Electrical Characteristics
VCC = 2.7 to 5.5 V, Topr = −40 to 85°C, unless otherwise specified
Value
Typ.
Unit
Condition
Symbol
fOCO-S
Characteristic
Min.
100
Max.
150
125-kHz on-chip oscillator oscillation
frequency
125
kHz
tsu(fOCO-S) Wait time until 125 kHz on-chip
oscillator stabilizes
2.7 V ≤ VCC ≤ 5.5 V
20
μs
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 67 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.2
5.2.1
Electrical Characteristics (V = 5 V)
CC
Electrical Characteristics
VCC = 5 V
Table 5.13
Electrical Characteristics (1)
VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Standard
Typ.
Symbol
OH
Parameter
Measuring Condition
Unit
V
Min.
Max.
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7,
P10_0 to P10_7
V
V
I
I
=−5 mA
V
2.0
V
HIGH Output Voltage
HIGH Output Voltage
OH
CC−
CC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7,
P10_0 to P10_7
= −200 μA
V
−0.3
V
V
OH
OH
OH
CC−
CC
I
I
= −1 mA
V
V
−2.0
V
HIGH POWER
OH
CC−
CC
HIGH Output Voltage XOUT
HIGH Output Voltage XCOUT
V
V
= −0.5 mA
−2.0
V
LOW POWER
HIGH POWER
LOW POWER
OH
CC−
CC
V
With no load applied
With no load applied
2.5
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7,
P10_0 to P10_7
V
V
I
= 5 mA
LOW Output Voltage
LOW Output Voltage
2.0
V
V
OL
OL
OL
OL
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7,
P10_0 to P10_7
I
= 200 μA
0.45
I
I
= 1 mA
HIGH POWER
2.0
2.0
OL
LOW Output Voltage XOUT
LOW Output Voltage XCOUT
V
V
= 0.5 mA
LOW POWER
HIGH POWER
LOW POWER
OL
V
OL
With no load applied
With no load applied
0
0
TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT5,
NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2,
CLK0 to CLK4, TA0OUT to TA4OUT,
V +-V
Hysteresis
0.2
2.5
V
T
T-
KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV,
SD, INPC1_0 to INPC1_7, CRX0
V
V
-V
Hysteresis
Hysteresis
RESET
0.2
0.2
2.5
0.8
V
V
T+ T-
-V
XIN
T+ T-
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7,
P10_0 to P10_7
I
V
V
= 5 V
= 0 V
HIGH Input Current
LOW Input Current
5.0
μA
IH
I
I
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7,
P10_0 to P10_7
I
−5.0
μA
kΩ
IL
XIN, RESET, CNVSS
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7,
P10_0 to P10_7
Pull-Up
Resistance
R
V = 0 V
I
30
50
170
PULLUP
R
R
V
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
1.5
15
MΩ
MΩ
V
fXIN
fXCIN
At stop mode
2.0
RAM
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 68 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 5 V
Table 5.14
Electrical Characteristics (2)
T
= −40 to 85°C unless otherwise specified.
opr
Standard
Unit
Symbol
Parameter
Measuring Condition
f(BCLK) = 32MHz,
Min. Typ. Max.
28
20
16
42
30
mA
mA
mA
XIN = 8 MHz (square wave), PLL multiply-by-8
125-kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
High speed mode
XIN = 20 MHz (square wave),
125-KHz on-chip oscillator operates
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125-KHz on-chip oscillator operates
Main clock stops
125-kHz on-chip oscillator operates
Divide-by-8
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
Power Supply
Current
(VCC =4.2V to 5.5
125-kHz on-chip oscillator
mode
150
500
μA
V)
ICC
In single-chip
mode, the output
pins are open and
other pins are
VSS
f(BCLK) = 32 kHz
On Flash memory (1)
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
Low power mode
160
20
μA
μA
μA
Main clock stops
125-kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
Wait mode
Stop mode
Main clock stops
125-kHz on-chip oscillator operates
Peripheral clock operates
Topr = 85°C
50
Topr = 25°C
18
45
30
μA
μA
Topr = 85°C
f
(BCLK) = 10 MHz, PM17 = 1 (one wait)
During flash memory
program
20.0
30.0
mA
mA
VCC = 5.0 V
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 5.0 V
During flash memory
erase
Idet2
Idet0
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current
3
6
μA
μA
Note:
1. This indicates the memory in which the program to be executed exists.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 69 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 5 V
5.2.2
Timing Requirements (Peripheral Functions and Others)
(VCC = 5 V, VSS = 0 V, at Topr = -40 to 85°C unless otherwise specified)
5.2.2.1
Reset Input (RESET Input)
Table 5.15
Reset Input (RESET Input)
Parameter
Standard
Symbol
tw(RSTL)
Unit
Min.
10
Max.
RESET input low pulse width
μs
RESET input
tw(RTSL)
Figure 5.6
Reset Input (RESET Input)
5.2.2.2
External Clock Input
(1)
Table 5.16
External Clock Input (XIN Input)
Standard
Min. Max.
Symbol
Parameter
Unit
tc
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
50
20
20
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
9
9
tf
External Clock Fall Time
Note:
1. The condition is V = 3.0V to 5.0V
CC
XIN input
tf
tr
tw(H)
tw(L)
tc
Figure 5.7
External Clock Input (XIN Input)
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 70 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
CC
SS
opr
5.2.2.3
Timer A Input
Table 5.17
Timer A Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TA)
TAiIN Input Cycle Time
100
40
ns
ns
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
tw(TAL)
TAiIN Input LOW Pulse Width
40
Table 5.18
Timer A Input (Gating Input in Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
400
200
200
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.19
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
200
100
100
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.20
Timer A Input (External Trigger Input in Pulse Width Modulation Mode and
Programmable Output Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
Figure 5.8
Timer A Input
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 71 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
CC
SS
opr
Table 5.21
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Unit
Symbol
tc(TA)
Parameter
Min.
Max.
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
800
200
200
ns
ns
ns
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
Two-phase pulse input in event counter mode
TAiIN input
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.9
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 72 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
CC
SS
opr
5.2.2.4
Timer B Input
Table 5.22
Timer B Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
100
40
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.23
Timer B Input (Pulse Period Measurement Mode)
Standard
Unit
Symbol
Parameter
Min.
400
200
200
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.24
Timer B Input (Pulse Width Measurement Mode)
Standard
Unit
Symbol
Parameter
Min.
400
200
200
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
Figure 5.10 Timer B Input
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 73 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
opr
CC
SS
5.2.2.5
Serial Interface
Table 5.25
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
200
100
100
Max.
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
ns
ns
ns
ns
0
RXDi Input Setup Time
RXDi Input Hold Time
70
90
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.11 Serial Interface
5.2.2.6
External Interrupt INTi Input
Table 5.26
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
tw(INL)
INTi input
tw(INH)
Figure 5.12 External Interrupt INTi Input
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 74 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements
(V = 5 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
opr
CC
SS
2
5.2.2.7
Multi-master I C-bus
2
Table 5.27
Multi-master I C-bus
Standard Clock Mode
High-speed Clock Mode
Unit
Symbol
Parameter
Min.
4.7
4.0
4.7
Max.
Min.
Max.
tBUF
Bus free time
1.3
μs
μs
μs
ns
μs
μs
ns
ns
μs
μs
tHD;STA
tLOW
tR
Hold time in start condition
Hold time in SCL clock 0 status
SCL, SDA signals’ rising time
Data hold time
0.6
1.3
1000
300
20 + 0.1 Cb
300
0.9
tHD;DAT
tHIGH
fF
0
0
0.6
Hold time in SCL clock 1 status
SCL, SDA signals’ falling time
Data setup time
4.0
20 + 0.1 Cb
100
300
tsu;DAT
tsu;STA
tsu;STO
250
4.7
4.0
Setup time in restart condition
Stop condition setup time
0.6
0.6
SDA
tsu;STO
tHD;STA
tBUF
tLOW
tR
tF
p
Sr
p
s
SCL
tHD;STA
tHD;DTA tHIGH
tsu;DTA
tsu;STA
2
Figure 5.13 Multi-master I C-bus
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 75 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.3
5.3.1
Electrical Characteristics (V = 3 V)
CC
Electrical Characteristics
VCC = 3 V
Table 5.28
Electrical Characteristics (1)
V
= 2.7 to 3.3V, V = 0 V at T = −40 to 85°C, f
=25MHz unless otherwise specified.
CC
SS
opr
(BCLK)
Standard
Typ.
Symbol
Parameter
Measuring Condition
Unit
V
Min.
Max.
VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7, P9_0 to
P9_3, P9_5 to P9_7, P10_0 to P10_7
HIGH
Output
Voltage
VOH
IOH = −1 mA
VCC−0.5
I
OH = −0.1 mA
OH = −50 μA
VCC−0.5
VCC−0.5
VCC
VCC
HIGH POWER
HIGH Output Voltage XOUT
HIGH Output Voltage XCOUT
V
V
I
LOW POWER
VOH
VOL
VOL
HIGH POWER With no load applied
LOW POWER With no load applied
2.5
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7, P9_0 to
P9_3, P9_5 to P9_7, P10_0 to P10_7
LOW
Output
Voltage
IOL = 1mA
0.5
V
IOL = 0.1mA
HIGH POWER
0.5
0.5
LOW Output Voltage XOUT
LOW Output Voltage XCOUT
V
V
IOL = 50μA
LOW POWER
HIGH POWER With no load applied
LOW POWER With no load applied
0
0
TA0IN to TA4IN, TB0IN to TB2IN, INT0
to INT5, NMI, ADTRG, CTS0 to CTS3,
SCL2, SDA2, CLK0 to CLK4, TA0OUT
to TA4OUT, KI0 to KI3, RXD0 to RXD4,
VT+-VT-
Hysteresis
1.8
V
ZP, IDU, IDW, IDV, SD, INPC1_0 to
INPC1_7, CRX0
VT+-VT-
T+-VT-
Hysteresis RESET
1.8
0.8
V
V
V
Hysteresis
XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7, P9_0 to
P9_3, P9_5 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
HIGH Input
Current
IIH
VI = 3V
4.0
μA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7, P9_0 to
P9_3, P9_5 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS
LOW Input
Current
IIL
VI = 0V
VI = 0V
−4.0
μA
kΩ
P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P6_0 to P6_7,
Resistance P7_0 to P7_7, P8_0 to P8_7, P9_0 to
P9_3, P9_5 to P9_7, P10_0 to P10_7
Pull-Up
RPULLUP
50
100
500
RfXIN
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
3.0
25
MΩ
MΩ
V
RfXCIN
VRAM
At stop mode
2.0
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 76 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 3 V
Table 5.29
Electrical Characteristics (2)
Topr = −40 to 85°C unless otherwise specified.
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
f(BCLK) = 25MHz,
26
19
15
40
28
mA
mA
mA
XIN = 8 MHz (square wave), PLL multiply-by-8
125-kHz on-chip oscillator operates
f(BCLK) = 20 MHz,
High speed mode
XIN = 20 MHz (square wave),
125-kHz on-chip oscillator operates
f(BCLK) = 16 MHz,
XIN = 16 MHz (square wave),
125-kHz on-chip oscillator operates
Main clock stops
125-kHz on-chip oscillator operates
Divide-by-8
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
125-kHz on-chip oscillator
mode
150
500
μA
Power Supply
Current
(VCC = 3.0 V to 3.6
f(BCLK) = 32 kHz
On Flash memory (1)
FMR22 = FMR23 = 1 (Low-current
consumption read mode)
V)
Low power mode
160
20
μA
μA
μA
ICC
In single-chip
mode, the output
pins are open and
other pins are
VSS
Main clock stops
125-kHz on-chip oscillator operates
Peripheral clock operates
Topr = 25°C
Wait mode
Stop mode
Main clock stops
125-kHz on-chip oscillator operates
Peripheral clock operates
Topr = 85°C
50
Topr = 25°C
17
45
27
μA
μA
Topr = 85°C
f
(BCLK) = 10 MHz, PM17 = 1 (one wait)
During flash memory
program
20.0
30.0
mA
mA
VCC = 3.0 V
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC = 3.0 V
During flash memory
erase
Idet2
Idet0
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current
3
6
μA
μA
Note:
1. This indicates the memory in which the program to be executed exists.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 77 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 3 V
5.3.2
Timing Requirements (Peripheral Functions and Others)
(VCC = 3 V, VSS = 0 V, at Topr = -40 to 85°C unless otherwise specified)
5.3.2.1
Reset Input (RESET Input)
Table 5.30
Reset Input (RESET Input)
Parameter
Standard
Symbol
tw(RSTL)
Unit
Min.
10
Max.
RESET input low pulse width
μs
RESET input
tw(RTSL)
Figure 5.14 Reset Input (RESET Input)
5.3.2.2
External Clock Input
(1)
Table 5.31
External Clock Input (XIN input)
Standard
Min. Max.
Symbol
Parameter
Unit
tc
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
50
20
20
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
9
9
tf
External Clock Fall Time
Note:
1. The condition is V = 2.7V to 3.0V.
CC
XIN input
tf
tr
tw(H)
tw(L)
tc
Figure 5.15 External Clock Input (XIN Input)
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 78 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
opr
CC
SS
5.3.2.3
Timer A Input
Table 5.32
Timer A Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(TA)
TAiIN Input Cycle Time
150
60
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
60
Table 5.33
Timer A Input (Gating Input in Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
600
300
300
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.34
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Max.
Symbol
Parameter
Unit
Min.
300
150
150
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.35
Timer A Input (External Trigger Input in Pulse Width Modulation Mode and
Programmable Output Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
Figure 5.16 Timer A Input
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 79 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
opr
CC
SS
Table 5.36
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Unit
Symbol
tc(TA)
Parameter
Min.
Max.
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
2
μs
ns
ns
t
500
500
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
Two-phase pulse input in event counter mode
TAiIN input
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.17 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 80 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
CC
SS
opr
5.3.2.4
Timer B Input
Table 5.37
Timer B Input (Counter Input in Event Counter Mode)
Standard
Unit
Symbol
Parameter
Min.
150
60
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
60
300
120
120
tw(TBH)
tw(TBL)
Table 5.38
Timer B Input (Pulse Period Measurement Mode)
Standard
Unit
Symbol
Parameter
Min.
600
300
300
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.39
Timer B Input (Pulse Width Measurement Mode)
Standard
Unit
Symbol
Parameter
Min.
600
300
300
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
Figure 5.18 Timer B Input
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 81 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
CC
SS
opr
5.3.2.5
Serial Interface
Table 5.40
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
300
150
150
Max.
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
160
ns
ns
ns
ns
0
RXDi Input Setup Time
RXDi Input Hold Time
100
90
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
RXDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.19 Serial Interface
5.3.2.6
External Interrupt INTi Input
Table 5.41
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
tw(INL)
INTi input
tw(INH)
Figure 5.20 External Interrupt INTi Input
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 82 of 83
M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
VCC = 3 V
Timing Requirements
(V = 3 V, V = 0 V, at T = −40 to 85°C unless otherwise specified)
CC
SS
opr
2
5.3.2.7
Multi-master I C-bus
2
Table 5.42
Multi-master I C-bus
Standard Clock Mode
High-speed Clock Mode
Unit
Symbol
Parameter
Min.
4.7
4.0
4.7
Max.
Min.
Max.
tBUF
Bus free time
1.3
μs
μs
μs
ns
μs
μs
ns
ns
μs
μs
tHD;STA
tLOW
tR
Hold time in start condition
Hold time in SCL clock 0 status
SCL, SDA signals’ rising time
Data hold time
0.6
1.3
1000
300
20 + 0.1 Cb
300
0.9
tHD;DAT
tHIGH
fF
0
0
0.6
Hold time in SCL clock 1 status
SCL, SDA signals’ falling time
Data setup time
4.0
20 + 0.1 Cb
100
300
tsu;DAT
tsu;STA
tsu;STO
250
4.7
4.0
Setup time in restart condition
Stop condition setup time
0.6
0.6
SDA
tsu;STO
tHD;STA
tBUF
tLOW
tR
tF
p
Sr
p
s
SCL
tHD;STA
tHD;DTA tHIGH
tsu;DTA
tsu;STA
2
Figure 5.21 Multi-master I C-bus
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 83 of 83
REVISION HISTORY M16C/5LD Group, M16C/56D Group Datasheet
Rev.
1.10
Date
Page
—
Revision History
Dec. 01, 2009
First Edition issued
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