R5F565N7FGFP_技术文档

Features

Datasheet

RX65N Group, RX651 Group

R01DS0276EJ0230

Rev.2.30

Renesas MCUs

Jun 20, 2019

120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory

(supportive of the dual bank function), 640-KB SRAM, various communications interfaces including Ethernet MAC,

SD host interface (optional), SD slave interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption

functions (optional), CMOS camera interface, Graphic-LCD controller, 2D drawing engine

Features

PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch

PLQP0144KA-B 20 × 20 mm, 0.5-mm pitch

PLQP0100KB-B 14 × 14 mm, 0.5-mm pitch

PLQP0064KB-C 10 × 10 mm, 0.5-mm pitch

■ 32-bit RXv2 CPU core

 Max. operating frequency: 120 MHz

Capable of 240 DMIPS in operation at 120 MHz

 Single precision 32-bit IEEE-754 floating point

PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch

 Two types of multiply-and-accumulation unit (between memories

PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch

PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch

and between registers)

 32-bit multiplier (fastest instruction execution takes one CPU clock

cycle)

 Divider (fastest instruction execution takes two CPU clock cycles)

 Fast interrupt

PLBG0176GA-A 13 × 13mm, 0.8-mm pitch

PTBG0064KB-A 4.5 × 4.5mm, 0.5-mm pitch

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions: Ultra-compact code

 Supports the memory protection unit (MPU)

 JTAG and FINE (one-line) debugging interfaces

■ Various communications interfaces

 Ethernet MAC (1 channel)

■ Low-power design and architecture

 Operation from a single 2.7- to 3.6-V supply

 Low power consumption: A product that supports all peripheral

functions draws only 0.19 mA/MHz (Typ.).

 RTC is capable of operation from a dedicated power supply.

 Four low-power modes

 PHY layer (1 channel) for host/function or OTG controller

(1 channel) with full-speed USB 2.0 transfer

 CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up

to 2 channels)

 SCIg and SCIh with multiple functionalities (up to 11 channels)

Choose from among asynchronous mode, clock-synchronous mode,

smart-card interface mode, simplified SPI, simplified I²C, and

extended serial mode.

 SCIi with 16-byte transmission and reception FIFOs (up to 2

channels)

 I²C bus interface for transfer at up to 1 Mbps (up to 3 channels)

 Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)

 Parallel data capture unit (PDC) for the CMOS camera interface

 Graphic-LCD controller (GLCDC)

■ On-chip code flash memory

 Supports versions with up to 2 Mbytes of ROM

 No wait cycles at up to 50 MHz or when the ROM cache is hit, one-

wait state at up to 100 MHz, two-wait state at above 100 MHz

 User code is programmable by on-board or off-board programming.

 Programming/erasing as background operations (BGOs)

 A dual-bank structure allows exchanging the start-up bank.

■ On-chip data flash memory

 32 Kbytes, reprogrammable up to 100,000 times

 Programming/erasing as background operations (BGOs)

 2D drawing engine (DRW2D)

 SD host interface (optional: 1 channel) with a 1- or 4-bit SD bus for

use with SD memory or SDIO

 SD slave interface (optional: 1 channel) with a 1- or 4-bit SD bus for

use with SD host interface

 MMCIF with 1-, 4-, or 8-bit transfer bus width

■ On-chip SRAM, no wait states

 256K/640 Kbytes of SRAM (no wait states)

 8 Kbytes of standby RAM (backup on deep software standby)

■ External address space

 Buses for full-speed data transfer (max. operating frequency of 60

MHz)

 8 CS areas

 8-, 16-, or 32-bit bus space is selectable per area

 Independent SDRAM area (128 Mbytes)

■ Data transfer

 DMACAa: 8 channels

 DTCb: 1 channel

 EXDMAC: 2 channels

 DMAC for the Ethernet controller: 1 channel

■ Reset and supply management

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Up to 25 extended-function timers

 16-bit TPUa, MTU3a

 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2

channels)

■ Clock functions

 External crystal resonator or internal PLL for operation at 8 to 24

MHz

■ 12-bit A/D converter

 Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)

 Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20

MHz



Self diagnosis, detection of analog input disconnection

 120-kHz clock for the IWDTa

■ 12-bit D/A converter: 2 channels

■ Real-time clock

 Adjustment functions (30 seconds, leap year, and error)

■ Temperature sensor for measuring temperature

within the chip



Real-time clock counting and binary counting modes are selectable

 Time capture function

(for capturing times in response to event-signal input)

■ Encryption functions (optional)

 AES (key lengths: 128, 192, and 256 bits)

 Trusted Secure IP (TSIP)

■ Independent watchdog timer

 120-kHz (1/2 LOCO frequency) clock operation

■ Up to 136 pins for general I/O ports

 5-V tolerance, open drain, input pull-up, switchable driving ability

■ Useful functions for IEC60730 compliance

 Oscillation-stoppage detection, frequency measurement, CRCA,

IWDTa, self-diagnostic function for the A/D converter, etc.

 Register write protection function can protect values in important

registers against overwriting.

■ Operating temp. range

 D-version: –40C to +85C

 G-version: –40C to +105C

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RX65N Group, RX651 Group

1. Overview

1.

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different

packages.

Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the

modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details,

see Table 1.2, Code Flash Memory Capacity and Comparison of Functions for Different Packages.

Table 1.1

Outline of Specifications (1/10)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 120 MHz

 32-bit RX CPU (RXv2)

 Minimum instruction execution time: One instruction per state (cycle of the system

clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 Basic instructions: 75

 Floating-point instructions: 11

 DSP instructions: 23

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32 / 32 → 32 bits

 Barrel shifter: 32 bits

FPU

 Single precision (32-bit) floating point

 Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory

Code flash memory

 Capacity: 512 Kbytes/768 Kbytes/1 Mbyte/1.5 Mbytes/2 Mbytes

 50 MHz  No-wait cycle access

100 MHz  1-wait cycle access

100 MHz  2-wait cycle access

 Instructions hitting the ROM cache or operand = 120 MHz: No-wait access

 On-board programming: Four types

 Off-board programming (parallel programmer mode)

 Instructions are executable only for the program stored in the TM target area by using

the Trusted Memory (TM) function and protection against data reading is realized.

 A dual-bank structure allows programming during reading or exchanging the start-up

areas

Data flash memory

 Capacity: 32 Kbytes

 Programming/erasing: 100,000 times

Unique ID

RAM

 16-byte unique ID for the device

 Capacity: 256 Kbytes (Products with 1 Mbyte of code flash memory or less)

RAM: 256 Kbytes

 Capacity: 640 Kbytes (Products with at least 1.5 Mbytes of code flash memory)

RAM: 256 Kbytes

Expansion RAM: 384 Kbytes

 120 MHz, no-wait access

Standby RAM

 Capacity: 8 Kbytes

 Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access

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1. Overview

Table 1.1

Outline of Specifications (2/10)

Classification

Module/Function

Description

Operating modes

 Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (for the SCI interface)

Boot mode (for the USB interface)

Boot mode (for the FINE interface)

 Selection of operating mode by register setting

Single-chip mode

On-chip ROM disabled extended mode

On-chip ROM enabled extended mode

 Endian selectable

Clock

Clock generation circuit  Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL

frequency synthesizer, and IWDT-dedicated on-chip oscillator

 The peripheral module clocks can be set to frequencies above that of the system clock.

 Main-clock oscillation stoppage detection

 Separate frequency-division and multiplication settings for the system clock (ICLK),

peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and

external bus clock (BCLK)

The CPU and other bus masters run in synchronization with the system clock (ICLK): Up

to 120 MHz

Peripheral modules of MTU3, RSPI, SCIi, ETHERC, EDMAC, AES, GLCDC, and

DRW2D run in synchronization with PCLKA, which operates at up to 120 MHz.

Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz

ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz

ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz

Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz

Devices connected to the external bus run in synchronization with the external bus clock

(BCLK): Up to 60 MHz

 Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a

reference clock of the PLL circuit

Reset

Nine types of reset

 RES# pin reset: Generated when the RES# pin is driven low.

 Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =

AVCC1 rises.

 Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Deep software standby reset: Generated in response to an interrupt to trigger release

from deep software standby.

 Independent watchdog timer reset: Generated when the independent watchdog timer

underflows, or a refresh error occurs.

 Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh

error occurs.

 Software reset: Generated by register setting.

Power-on reset

If the RES# pin is at the high level when power is supplied, an internal reset is generated.

After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified

period has elapsed, the reset is cancelled.

Voltage detection circuit (LVDA)

Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an

internal reset or interrupt.

 Voltage detection circuit 0

Capable of generating an internal reset

The option-setting memory can be used to select enabling or disabling of the reset.

Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V)

 Voltage detection circuits 1 and 2

Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V)

Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)

Capable of generating an internal reset

 Two types of timing are selectable for release from reset

An internal interrupt can be requested.

 Detection of voltage rising above and falling below thresholds is selectable.

 Maskable or non-maskable interrupt is selectable

Voltage detection monitoring

Event linking

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1. Overview

Table 1.1

Outline of Specifications (3/10)

Classification

Module/Function

Low power consumption  Module stop function

function  Four low power consumption modes

Sleep mode, all-module clock stop mode, software standby mode, and deep software

standby mode

Description

Low power

consumption

Battery backup function  When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied

to keep the real-time clock (RTC) operating.

Interrupt

Interrupt controller

(ICUB)

 Peripheral function interrupts: 262 sources

 External interrupts: 16 (pins IRQ0 to IRQ15)

 Software interrupts: 2 sources

 Non-maskable interrupts: 7 sources

 Sixteen levels specifiable for the order of priority

 Method of interrupt source selection:

The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128

vectors are selected from among the other 123 sources.)

External bus extension

 The external address space can be divided into eight areas (CS0 to CS7), each with

independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7)

A chip-select signal (CS0# to CS7#) can be output for each area.

Each area is specifiable as an 8-, 16-, or 32-bit bus space.

The data arrangement in each area is selectable as little or big endian (only for data).

 SDRAM interface connectable

 Bus format: Separate bus, multiplex bus

 Wait control

 Write buffer facility

DMA

DMA controller

 8 channels

(DMACAa)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

EXDMA controller

(EXDMACa)

 2 channels

Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster

transfer

 Single-address transfer enabled with the EDACKn signal

 Request sources: Software trigger, external DMA requests (EDREQn), and interrupt

requests from peripheral functions

Data transfer controller

(DTCb)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Request sources: External interrupts and interrupt requests from peripheral functions

 Sequence transfer

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RX65N Group, RX651 Group

1. Overview

Table 1.1

Outline of Specifications (4/10)

Classification

Module/Function

Description

I/O ports

Programmable I/O ports  I/O ports for the 177-pin TFLGA, 176-pin LFBGA, and 176-pin LFQFP

I/O pins: 136

Input pin: 1

Pull-up resistors: 136

Open-drain outputs: 136

5-V tolerance: 19

 I/O ports for the 145-pin TFLGA and 144-pin LFQFP

I/O pins: 111

Input pin: 1

Pull-up resistors: 111

Open-drain outputs: 111

5-V tolerance: 18

 I/O ports for the 100-pin TFLGA and 100-pin LFQFP

I/O pins: 78

Input pin: 1

Pull-up resistors: 78

Open-drain outputs: 78

5-V tolerance: 17

 I/O ports for the 64-pin TFBGA

I/O pins: 41

Input pin: 1

Pull-up resistors: 41

Open-drain outputs: 41

5-V tolerance: 8

 I/O ports for the 64-pin LFQFP

I/O pins: 42

Input pin: 1

Pull-up resistors: 42

Open-drain outputs: 42

5-V tolerance: 8

Event link controller (ELC)

 Event signals such as interrupt request signals can be interlinked with the operation of

functions such as timer counting, eliminating the need for intervention by the CPU to

control the functions.

 83 internal event signals can be freely combined for interlinked operation with

connected functions.

 Event signals from peripheral modules can be used to change the states of output pins

(of ports B and E).

 Changes in the states of pins (of ports B and E) being used as inputs can be interlinked

with the operation of peripheral modules.

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1. Overview

Table 1.1

Outline of Specifications (5/10)

Classification

Module/Function

Description

Timers

16-bit timer pulse unit

(TPUa)

 (16 bits × 6 channels) × 1 unit

 Maximum of 16 pulse-input/output possible

 Select from among seven or eight counter-input clock signals for each channel

 Input capture/output compare function

 Output of PWM waveforms in up to 15 phases in PWM mode

 Support for buffered operation, phase-counting mode (two phase encoder input) and

cascade-connected operation (32 bits × 2 channels) depending on the channel.

 PPG output trigger can be generated

 Capable of generating conversion start triggers for the A/D converters

 Digital filtering of signals from the input capture pins

 Event linking by the ELC

Multifunction timer pulse  9 channels (16 bits × 8 channels, 32 bits × 1 channel)

unit (MTU3a)

 Maximum of 28 pulse-input/output and 3 pulse-input possible

 Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/

2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,

MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)

14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8,

12 are available for channel 2, and 10 are available for channel 5.

 Input capture function

 39 output compare/input capture registers

 Counter clear operation (synchronous clearing by compare match/input capture)

 Simultaneous writing to multiple timer counters (TCNT)

 Simultaneous register input/output by synchronous counter operation

 Buffered operation

 Support for cascade-connected operation

 43 interrupt sources

 Automatic transfer of register data

 Pulse output mode

Toggle/PWM/complementary PWM/reset-synchronized PWM

 Complementary PWM output mode

Outputs non-overlapping waveforms for controlling 3-phase inverters

Automatic specification of dead times

PWM duty cycle: Selectable as any value from 0% to 100%

Delay can be applied to requests for A/D conversion.

Non-generation of interrupt requests at peak or trough values of counters can be

selected.

Double buffer configuration

 Reset synchronous PWM mode

Three phases of positive and negative PWM waveforms can be output with desired duty

cycles.

 Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)

 Counter functionality for dead-time compensation

 Generation of triggers for A/D converter conversion

 A/D converter start triggers can be skipped

 Digital filter function for signals on the input capture and external counter clock pins

 PPG output trigger can be generated

 Event linking by the ELC

Port output enable 3

(POE3a)

 Control of the high-impedance state of the MTU3 waveform output pins

 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#

 Initiation on detection of short-circuited outputs (detection of simultaneous PWM output

to the active level)

 Initiation by oscillation-stoppage detection or software

 Additional programming of output control target pins is enabled

Programmable pulse

generator (PPG)

 (4 bits × 4 groups) × 2 units

 Pulse output with the MTU3 or TPU output as a trigger

 Maximum of 32 pulse-output possible

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RX65N Group, RX651 Group

1. Overview

Table 1.1

Outline of Specifications (6/10)

Classification

Module/Function

Description

Timers

8-bit timers (TMRb)

 (8 bits × 2 channels) × 2 units

 Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,

PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Generation of triggers for A/D converter conversion

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

 Event linking by the ELC

Compare match timer

(CMT)

 (16 bits × 2 channels) × 2 units

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Event linking by the ELC

Compare match timer W  (32 bits × 1 channel) × 2 units

(CMTW)  Compare-match, input-capture input, and output-comparison output are available.

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

 Event linking by the ELC

Realtime clock (RTCd)*⁴ Clock sources: Main clock, sub clock

 Selection of the 32-bit binary count in time count/second unit possible

 Clock and calendar functions

 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

 Battery backup operation

 Time-capture facility for three values

 Event linking by the ELC

Watchdog timer (WDTA)  14 bits × 1 channel

 Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,

PCLKB/512, PCLKB/2048, PCLKB/8192)

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256

 Window function: The positions where the window starts and ends are specifiable (the

window defines the timing with which refreshing is enabled and disabled).

 Event linking by the ELC

Communication Ethernet controller

 Input and output of Ethernet/IEEE 802.3 frames

 Transfer at 10 or 100 Mbps

function

(ETHERC)

 Full- and half-duplex modes

 MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as

defined in IEEE 802.3u

 Detection of Magic Packets^TM*¹or output of a “wake-on-LAN” signal (WOL)

 Compliance with flow control as defined in IEEE 802.3x standards

DMA controller for

Ethernet controller

(EDMACa)

 Alleviation of CPU load by the descriptor control method

 Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes

USB 2.0 FS host/

 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS

function module (USBb)  One port

 Compliance with the USB 2.0 specification

 Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)

 Both self-powered mode and bus-powered mode are supported

 OTG (On the Go) operation is possible (low-speed is not supported)

 Incorporates 2 Kbytes of RAM as a transfer buffer

 External pull-up and pull-down resistors are not required

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1. Overview

Table 1.1

Outline of Specifications (7/10)

Classification

Module/Function

Description

Communication Serial communications

 13 channels (SCIg: 10 channels + SCIh: 1 channel + SCIi: 2 channels)

 SCIg, SCIh, SCIi

function

interfaces

(SCIg, SCIh, SCIi)

Serial communications modes: Asynchronous, clock synchronous, and smart-card

interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Start-bit detection: Level or edge detection is selectable.

Simple I²C

Simple SPI

9-bit transfer mode

Bit rate modulation

Double-speed mode

 SCIg, SCIh

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Event linking by the ELC (only on channel 5)

 SCIh

Supports the serial communications protocol, which contains the start frame and

information frame

Supports the LIN format

 SCIi

Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the

transmission and reception unit

I²C bus interface (RIICa)  3 channels (only channel 0 can be used in fast-mode plus)

Communication formats

I²C bus format/SMBus format

Supports the multi-master

Max. transfer rate: 1 Mbps (channel 0)

 Event linking by the ELC

CAN module (CAN)

 2 channels

 Compliance with the ISO11898-1 specification (standard frame and extended frame)

 32 mailboxes per channel

Serial peripheral

interface (RSPIc)

 3 channels

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or to 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with

each frame having up to 32 bits)

Transit/receive data can be swapped in byte units

 Buffered structure

Double buffers for both transmission and reception

 RSPCK can be stopped with the receive buffer full for master reception.

 Event linking by the ELC

Quad serial peripheral

interface (QSPI)

 1 channel

 Connectable with serial flash memory equipped with multiple input and output lines (i.e.

for single, dual, or quad operation)

 Programmable bit length and selectable active sense and phase of the clock signal

 Sequential execution of transfer

 LSB or MSB first is selectable

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1. Overview

Table 1.1

Outline of Specifications (8/10)

Classification

Module/Function

Description

SD host interface (SDHI)*³

 1 channel

 Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode (12.5 MB/s)

 One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)

 SD specifications

Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported)

Part E1: SDIO Specification Ver. 3.00

 Error checking: CRC7 for commands and CRC16 for data

 Interrupt requests: Card access interrupt, SDIO access interrupt, card detection

interrupt, SD buffer access interrupt

 DMA transfer requests: SD_BUF write and SD_BUF read

 Support for card detection and write protection

SD slave interface (SDSI)*³

MMC host interface (MMCIF)

 1 channel

 Compliant with the SDIO Card Specification Ver.2.00 (CSA is not supported)

 1-bit SD/4-bit SD/SPI mode

 SDIO Proprietary command is supported

 SD/SPI Mandatory command is supported

 Interrupt requests: 6

 1 channel

 Transfer speed: Data transfer mode (30 MB/s), backward compatible mode (25 MB/s)

 Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported)

 Interface for Multimedia Cards (MMCs)

 Device buses: Support for 1-, 4-, and 8-bit MMC buses

 Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation

interrupt, MMCIF buffer access interrupt

 DMA transfer requests: CE_DATA write and CE_DATA read

 Support for card detection, boot operation, high priority interrupt (HPI)

Parallel data capture unit (PDC)

Graphic-LCD controller (GLCDC)

2D drawing engine (DRW2D)

 1 channel

 Acquisition of synchronization through external 8-bit horizontal and vertical

synchronization signals

 Setting of the image size when clipping of the output for a one-frame image is required

 1 channel

 Various data formats and LCD panels are supported

 Superposition of 3 planes (single-color background, graphic 1, graphic 2)

 32- and 16-bpp graphics data and 8-, 4-, and 1-bit CLUT data formats are supported

 1 channel

 Vector drawing (straight lines, triangles, and circles)

 Bit blitting (with support for filling, copying, stretching, and rotation)

 Bus master function for input and output of frame buffer data

32-, 16-, and 8-bit pixel graphics data are supported

 Bus master function for input of texture data

Input of texture data (32, 24, 16, 8, 4, 2, or 1 bit) are supported.

Run length encoding is supported

A CLUT is installed and index data can be converted into color data

 Two rendering modes are supported (register mode and display list mode)

 Performance counting

 Interrupts in response to completion of rendering and processing of the display list

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 9 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.1

Outline of Specifications (9/10)

Classification

Module/Function

Description

12-bit A/D converter (S12ADFa)

 12 bits × 2 units (unit 0: 8 channels; unit 1: 21 channels)

 12-bit resolution (switchable between 8, 10, and 12 bits)

 Conversion time

0.48 μs per channel (for 12-bit conversion)

0.45 μs per channel (for 10-bit conversion)

0.42 μs per channel (for 8-bit conversion)

 Operating mode

Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)

Group priority control (only for 3 group scan mode)

 Sample-and-hold function

Common sample-and-hold circuit included

In addition, channel-dedicated sample-and-hold function (3 channels: in unit 0 only)

included

 Sampling variable

Sampling time can be set up for each channel.

 Digital comparison

Method: Comparison to detect voltages above or below thresholds and window

comparison

Measurement: Comparison of two results of conversion or comparison of a value in the

comparison register and a result of conversion

 Self-diagnostic function

The self-diagnostic function internally generates three analog input voltages

(unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: AVSS1, AVCC1 × 1/2, AVCC1)

 Double trigger mode (A/D conversion data duplicated)

 Detection of analog input disconnection

 Three ways to start A/D conversion

Software trigger, timer (MTU3, TMR, TPU) trigger, external trigger

 Event linking by the ELC

12-bit D/A converter (R12DA)

 2 channels

 12-bit resolution

 Output voltage: 0.2 V to AVCC1 – 0.2 V (buffered output), 0 V to AVCC1 (unbuffered

output)

 Buffered output or unbuffered output can be selected.

 Event linking by the ELC

Temperature sensor

 1 channel

 Relative precision: ± 1°C

 The voltage of the temperature is converted into a digital value by the 12-bit A/D

converter (unit 1).

Safety

Memory protection unit

 Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to

(MPU)

FFFF FFFFh.

 Minimum protection unit: 16 bytes

 Reading from, writing to, and enabling the execution access can be specified for each

area.

 An access exception occurs when the detected access is not in the permitted area.

Trusted Memory (TM)

Function

 Programs in the TM target area in the code flash memory are protected against reading

 Instruction fetching by the CPU is the only form of access to these areas when the TM

function is enabled.

Register write protection  Protects important registers from being overwritten for in case a program runs out of

function control.

CRC calculator (CRCA)  Generation of CRC codes for 8-/32-bit data

8-bit data

Selectable from the following three polynomials

X⁸+ X²+ X + 1, X¹⁶+ X¹⁵+ X²+ 1, X¹⁶+ X¹²+ X⁵+ 1

32-bit data

Selectable from the following two polynomials

X

³²+ X²⁶+ X²³+ X²²+ X¹⁶+ X¹²+ X¹¹+ X¹⁰+ X⁸+ X⁷+ X⁵+ X⁴+ X²+ X + 1,

X³²+ X²⁸+ X²⁷+ X²⁶+ X²⁵+ X²³+ X²²+ X²⁰+ X¹⁹+ X¹⁸+ X¹⁴+ X¹³+ X¹¹+ X¹⁰+ X⁹+

X⁸+ X⁶+ 1

 Generation of CRC codes for use with LSB-first or MSB-first communications is

selectable

Main clock oscillation

stop detection

 Main clock oscillation stop detection: Available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 10 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.1

Outline of Specifications (10/10)

Classification

Module/Function

Description

Safety

Clock frequency

accuracy measurement

circuit (CAC)

 Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and

high-speed on-chip oscillators, IWDT-dedicated on-chip oscillator, and PCLKB, and

generates interrupts when the setting range is exceeded.

Data operation circuit

(DOC)

 The function to compare, add, or subtract 16-bit data

Encryption

function

AESa*²

 Key lengths: 128, 192, and 256 bits

 Support for CFB, OFB, and CMAC operating modes

 Speed of calculations:

128-bit key length in 22 cycles

192-bit key length in 26 cycles

256-bit key length in 30 cycles

 Compliant with FIPS PUB 197

True random number

generator (RNG)*²

 Length of random numbers: 16 bits

 Generation of random-number-generated interrupts after a number is generated

 Random number generation time: 1.9 ms (typ)

Trusted Secure IP

(TSIP)*²

 Security algorithm

Common key encryption: AES (compliant with NIST FIPS PUB 197), 3DES, ARC4

Non-common key encryption: RSA

 Other features

TRNG (true-random number generator)

Hash value generation: SHA1, SHA224, SHA256, GHASH

Prevention from illicit copying of a key

Operating frequency

Power supply voltage

Up to 120 MHz

VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7  VREFH0  AVCC0,

V_BATT= 2.0 to 3.6 V

Operating temperature

Package

D-version: –40 to +85°C

G-version: –40 to +105°C*⁵

177-pin TFLGA (PTLG0177KA-A)

176-pin LFBGA (PLBG0176GA-A)

176-pin LFQFP (PLQP0176KB-A)

145-pin TFLGA (PTLG0145KA-A)

144-pin LFQFP (PLQP0144KA-B)

100-pin TFLGA (PTLG0100JA-A)

100-pin LFQFP (PLQP0100KB-B)

64-pin TFBGA (PTBG0064KB-A)

64-pin LFQFP (PLQP0064KB-C)

Debugging interface

JTAG and FINE interfaces

Note 1. Magic Packet^TMis a registered trademark of Advanced Micro Devices, Inc.

Note 2. The product part number differs according to whether or not the MCU includes the encryption function.

Note 3. The product part number differs according to whether or not the MCU includes an SDHI (SD host interface)/SDSI (SD slave

interface) (products with 1 Mbyte of code flash memory or less).

Note 4. When the realtime clock is not used, initialize the registers in the time clock according to description in section 31.6.7,

Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware.

Note 5. Please contact us if you are using a G-version product.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 11 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.2

Code Flash Memory Capacity and Comparison of Functions for Different Packages (1/2)

Products Products with 1 Mbyte of code

flash memory or less

Products with at least 1.5 Mbytes of code

flash memory

Package 145Pins,

177Pins, 145Pins,

176 Pins 144 Pins

100 Pins

64 Pins

100 Pins

64 Pins

Functions

144 Pins

Code Flash

Memory

Code Flash Memory Capacity

512 Kbytes/768 Kbytes

/1 Mbyte

1.5 Mbytes/2 Mbytes

Dual bank function

BGO function

Not available

Available

Data Flash Memory

RAM

32 Kbytes

640 Kbytes

256 Kbytes

(256 Kbytes + 384 Kbytes of expansion RAM)

External bus

DMA

External bus width

Not

available

32/16/8

bits

Not

available

16/8 bits

SDRAM area controller

DMA controller

Available

Not available

Available

Not available

Ch. 0 to 7

Available

Data transfer controller

EXDMA controller

Ch. 0 and 1

Not

Ch. 0 and 1

Not

available

Timers

16-bit timer pulse unit

Ch. 0 to 5

Ch. 0 to 8

Available

Multi-function timer pulse unit 3

Port output enable 3

Programmable pulse generator

Ch. 0 and 1

Not

Ch. 0 and 1

Not

available

8-bit timers

Ch. 0 to 3

Ch. 0 and 1

Available

Compare match timer

Compare match timer W

Realtime clock

Watchdog timer

Independent watchdog timer

Communication Ethernet controller

function

Ch. 0 (only for

RX65N group)

Not

available

Ch. 0 (only for RX65N group)

Ch. 0

Not

available

DMA Controller for the Ethernet

Controller

Ch. 0 (only for

RX65N group)

Not

available

Not

available

USB 2.0 FS host/function

module

Ch. 0

Ch. 0*¹

Serial communications

interfaces (SCIg)

Ch. 0 to 9 Ch. 0 to

3, 5, 6, 8

Ch. 1 to

3, 5, 8

and 9

Ch. 0 to 9

Ch. 0 to

3, 5, 6, 8

and 9

Ch. 1 to

3, 5, 8

and 9

Serial communications

interfaces (SCIh)

Ch. 12

Ch. 10 and 11

Serial communications

interfaces (SCIi)

I²C bus interfaces

Serial peripheral interface

CAN module

Ch. 0 and 2

Ch. 0 to 2

Ch. 0 and

2

Ch. 0 and

1

Ch. 0 and

1

Ch. 0 and 1

Not

Ch. 0 and 1

Not

available

Quad serial peripheral interface

SD host interface

Ch. 0

Available

SD slave interface

Available

Not

Available

Not

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 12 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.2

Code Flash Memory Capacity and Comparison of Functions for Different Packages (2/2)

Products Products with 1 Mbyte of code

flash memory or less

Products with at least 1.5 Mbytes of code

flash memory

Package 145Pins,

177Pins, 145Pins,

176 Pins 144 Pins

100 Pins

64 Pins

100 Pins

64 Pins

Functions

144 Pins

Communication MMC host interface

function

Available

Not

available

Available

Not

available

Parallel data capture unit

Available

Not available

Available

Not available

Graphics

Graphic-LCD controller

Not available

Not

available

2D drawing engine

Not available

Available

Not

available

12-bit A/D converter

AN000 to AN000 to AN000 to

AN000 to 007

(unit 0: 8 channels)

AN100 to 120

AN000 to AN000 to

007 003

(unit 0: 8 (unit 0: 4

007 (unit

0: 8

007

003

(unit 0: 8 (unit 0: 4

channels) channels) channels) (unit 1: 21 channels) channels) channels)

AN100 to AN100 to

AN106,

107, 110

to 113

AN100 to

113

(unit 1:

14

AN106,

107, 110

to 113

120

(unit 1:

21

113

(unit 1:

14

(unit 1: 6

channels) channels) channels)

channels) channels)

12-bit D/A converter

Ch. 0 and 1

Ch. 1*²

Ch. 0 and 1

Available

Ch. 1*²

Temperature sensor

CRC calculator

Available

Data operation circuit

Clock frequency accuracy measurement circuit

Encryption

AES

Available*³

Incorporated in the Trusted Secure IP

Available

RNG

Available*³

Trusted Secure IP

Not available

Event link controller

Available

Off-board programming

(parallel programmer mode)

Available

Not avail-

able

Available

Not avail-

able

Note 1. Only supports the function controller.

Note 2. Not provided on the 64-pin TFBGA.

Note 3. Regarding the public release of this module, an exchange of non-disclosure agreement is necessary. For details, contact your

Renesas sales agency.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 13 of 246

RX65N Group, RX651 Group

1. Overview

1.2

List of Products

Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.

Table 1.3

List of Products (1/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX65N R5F565NEDDFC PLQP0176KB-A 2 M

(D ver-

640 K

32 K

120 MHz

Not

available

Available

–40 to +85

sion)

R5F565NEHDFC PLQP0176KB-A 2 M

640 K

32 K

120 MHz

Available

–40 to +85

R5F565NCDDFC PLQP0176KB-A 1.5 M

Not

available

R5F565NCHDFC PLQP0176KB-A 1.5 M

R5F565NEDDFB PLQP0144KA-B 2 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F565NEHDFB PLQP0144KA-B 2 M

R5F565NCDDFB PLQP0144KA-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F565NCHDFB PLQP0144KA-B 1.5 M

640 K

256 K

32 K

120 MHz

Available

–40 to +85

R5F565N9ADFB

R5F565N9BDFB

R5F565N9EDFB

R5F565N9FDFB

R5F565N7ADFB

R5F565N7BDFB

R5F565N7EDFB

R5F565N7FDFB

R5F565N4ADFB

R5F565N4BDFB

R5F565N4EDFB

R5F565N4FDFB

PLQP0144KA-B 1 M

PLQP0144KA-B 768 K

PLQP0144KA-B 512 K

Not

included

available

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

R5F565NEDDFP PLQP0100KB-B 2 M

32 K

Not

Available

available

R5F565NEHDFP PLQP0100KB-B 2 M

R5F565NCDDFP PLQP0100KB-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F565NCHDFP PLQP0100KB-B 1.5 M

640 K

256 K

32 K

120 MHz

Available

–40 to +85

R5F565N9ADFP

R5F565N9BDFP

R5F565N9EDFP

R5F565N9FDFP

PLQP0100KB-B 1 M

Not

included

Not

available

Not

available

Not

available

256 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

Not

included

Available

Not

available

Not

available

Not

Available

Not

included

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 14 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (2/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX65N R5F565N7ADFP

(D ver-

PLQP0100KB-B 768 K

PLQP0100KB-B 512 K

256 K

Not

included

120 MHz

Not

available

Not

available

Not

available

–40 to +85

sion)

R5F565N7BDFP

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

R5F565N7EDFP

R5F565N7FDFP

R5F565N4ADFP

R5F565N4BDFP

R5F565N4EDFP

R5F565N4FDFP

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

R5F565NEDDBG PLBG0176GA-A 2 M

32 K

Not

Available

available

R5F565NEHDBG PLBG0176GA-A 2 M

R5F565NCDDBG PLBG0176GA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F565NCHDBG PLBG0176GA-A 1.5 M

R5F565NEDDLC PTLG0177KA-A 2 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F565NEHDLC PTLG0177KA-A 2 M

R5F565NCDDLC PTLG0177KA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F565NCHDLC PTLG0177KA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

R5F565NEDDLK

R5F565NEHDLK

PTLG0145KA-A 2 M

Not

available

640 K

32 K

120 MHz

Available

–40 to +85

R5F565NCDDLK PTLG0145KA-A 1.5 M

R5F565NCHDLK PTLG0145KA-A 1.5 M

Not

available

640 K

256 K

32 K

120 MHz

Available

–40 to +85

R5F565N9ADLK

R5F565N9BDLK

R5F565N9EDLK

R5F565N9FDLK

R5F565N7ADLK

R5F565N7BDLK

R5F565N7EDLK

R5F565N7FDLK

R5F565N4ADLK

R5F565N4BDLK

PTLG0145KA-A 1 M

PTLG0145KA-A 768 K

PTLG0145KA-A 512 K

Not

included

available

256 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

Available

Not

included

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 15 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (3/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX65N R5F565N4EDLK

(D ver-

PTLG0145KA-A 512 K

PTLG0100JA-A 2 M

256 K

Not

included

120 MHz

Available

Not

available

Not

available

–40 to +85

sion)

R5F565N4FDLK

256 K

640 K

Not

included

120 MHz

Available

Not

available

R5F565NEDDLJ

32 K

Not

Available

available

R5F565NEHDLJ

R5F565NCDDLJ

PTLG0100JA-A 2 M

PTLG0100JA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F565NCHDLJ

R5F565N9ADLJ

PTLG0100JA-A 1.5 M

PTLG0100JA-A 1 M

640 K

256 K

32 K

120 MHz

Available

–40 to +85

Not

included

available

R5F565N9BDLJ

R5F565N9EDLJ

R5F565N9FDLJ

R5F565N7ADLJ

R5F565N7BDLJ

R5F565N7EDLJ

R5F565N7FDLJ

R5F565N4ADLJ

R5F565N4BDLJ

R5F565N4EDLJ

R5F565N4FDLJ

PTLG0100JA-A 1 M

PTLG0100JA-A 768 K

PTLG0100JA-A 512 K

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

–40 to +105

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

RX65N R5F565NEDGFC PLQP0176KB-A 2 M

(G ver-

32 K

Not

available

Available

sion)

R5F565NEHGFC PLQP0176KB-A 2 M

640 K

32 K

120 MHz

Available

–40 to +105

R5F565NCDGFC PLQP0176KB-A 1.5 M

Not

available

R5F565NCHGFC PLQP0176KB-A 1.5 M

R5F565NEDGFB PLQP0144KA-B 2 M

640 K

32 K

120 MHz

Available

–40 to +105

Not

available

R5F565NEHGFB PLQP0144KA-B 2 M

R5F565NCDGFB PLQP0144KA-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +105

Not

available

R5F565NCHGFB PLQP0144KA-B 1.5 M

640 K

256 K

32 K

120 MHz

Available

–40 to +105

R5F565N9AGFB

R5F565N9BGFB

R5F565N9EGFB

R5F565N9FGFB

PLQP0144KA-B 1 M

Not

included

Not

available

Not

available

Not

available

256 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +105

Not

included

Available

Not

available

Not

available

Not

Available

Not

included

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 16 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (4/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX65N R5F565N7AGFB

(G ver-

PLQP0144KA-B 768 K

PLQP0144KA-B 512 K

256 K

Not

included

120 MHz

Not

available

Not

available

Not

available

–40 to +105

sion)

R5F565N7BGFB

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

R5F565N7EGFB

R5F565N7FGFB

R5F565N4AGFB

R5F565N4BGFB

R5F565N4EGFB

R5F565N4FGFB

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

R5F565NEDGFP PLQP0100KB-B 2 M

32 K

Not

Available

available

R5F565NEHGFP PLQP0100KB-B 2 M

R5F565NCDGFP PLQP0100KB-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +105

Not

available

R5F565NCHGFP PLQP0100KB-B 1.5 M

640 K

256 K

32 K

120 MHz

Available

–40 to +105

R5F565N9AGFP

R5F565N9BGFP

R5F565N9EGFP

R5F565N9FGFP

R5F565N7AGFP

R5F565N7BGFP

R5F565N7EGFP

R5F565N7FGFP

R5F565N4AGFP

R5F565N4BGFP

R5F565N4EGFP

R5F565N4FGFP

PLQP0100KB-B 1 M

PLQP0100KB-B 768 K

PLQP0100KB-B 512 K

Not

included

available

256 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +105

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

Available

Not

included

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 17 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (5/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX651 R5F5651EDDFC

(D ver-

PLQP0176KB-A 2 M

640 K

32 K

120 MHz

Not

available

Available

–40 to +85

sion)

R5F5651EHDFC

PLQP0176KB-A 2 M

PLQP0176KB-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

R5F5651CDDFC

Not

available

R5F5651CHDFC

R5F5651EDDFB

PLQP0176KB-A 1.5 M

PLQP0144KA-B 2 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F5651EHDFB

R5F5651CDDFB

PLQP0144KA-B 2 M

PLQP0144KA-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F5651CHDFB

R5F56519ADFB

PLQP0144KA-B 1.5 M

PLQP0144KA-B 1 M

640 K

256 K

32 K

120 MHz

Available

–40 to +85

Not

included

available

R5F56519BDFB

R5F56519EDFB

R5F56519FDFB

R5F56517ADFB

R5F56517BDFB

R5F56517EDFB

R5F56517FDFB

R5F56514ADFB

R5F56514BDFB

R5F56514EDFB

R5F56514FDFB

R5F5651EDDFP

PLQP0144KA-B 1 M

PLQP0144KA-B 768 K

PLQP0144KA-B 512 K

PLQP0100KB-B 2 M

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

32 K

Not

Available

available

R5F5651EHDFP

R5F5651CDDFP

PLQP0100KB-B 2 M

PLQP0100KB-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F5651CHDFP

R5F56519ADFP

PLQP0100KB-B 1.5 M

PLQP0100KB-B 1 M

640 K

256 K

32 K

120 MHz

Available

–40 to +85

Not

included

available

R5F56519BDFP

R5F56519EDFP

R5F56519FDFP

R5F56517ADFP

R5F56517BDFP

PLQP0100KB-B 1 M

PLQP0100KB-B 768 K

256 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

Available

Not

included

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 18 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (6/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX651 R5F56517EDFP

(D ver-

PLQP0100KB-B 768 K

PLQP0100KB-B 512 K

256 K

Not

included

120 MHz

Available

Not

available

Not

available

–40 to +85

sion)

R5F56517FDFP

256 K

640 K

Not

included

120 MHz

Available

Not

available

R5F56514ADFP

R5F56514BDFP

R5F56514EDFP

R5F56514FDFP

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Available*

Not

available

1

R5F5651EDDFM PLQP0064KB-C 2 M

32 K

Not

Available

available

1

R5F5651EHDFM PLQP0064KB-C 2 M

R5F5651CDDFM PLQP0064KB-C 1.5 M

640 K

32 K

120 MHz

Available

Available*

Available

–40 to +85

Not

Available*

available

1

R5F5651CHDFM PLQP0064KB-C 1.5 M

640 K

256 K

32 K

120 MHz

Available

Available*

Available

–40 to +85

R5F56519BDFM

R5F56519FDFM

R5F56517BDFM

R5F56517FDFM

R5F56514BDFM

R5F56514FDFM

PLQP0064KB-C 1 M

PLQP0064KB-C 768 K

PLQP0064KB-C 512 K

Not

included

Not

available

Available*

Not

available

1

256 K

640 K

Not

included

120 MHz

Available

Available*

Available

Not

available

–40 to +85

Not

included

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

included

Available

Not

available

R5F5651EDDBG PLBG0176GA-A 2 M

32 K

Not

Available

available

R5F5651EHDBG PLBG0176GA-A 2 M

R5F5651CDDBG PLBG0176GA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F5651CHDBG PLBG0176GA-A 1.5 M

640 K

32 K

120 MHz

Available

Available*

Available

–40 to +85

1

R5F5651EDDBP

PTBG0064KB-A 2 M

Not

available

1

R5F5651EHDBP

R5F5651CDDBP

PTBG0064KB-A 2 M

PTBG0064KB-A 1.5 M

640 K

32 K

120 MHz

Available

Available*

Available

–40 to +85

Not

Available*

available

1

R5F5651CHDBP

R5F56519BDBP

PTBG0064KB-A 1.5 M

PTBG0064KB-A 1 M

640 K

256 K

32 K

120 MHz

Available

Available*

Available

–40 to +85

Not

Available*

Not

included

available

1

R5F56519FDBP

R5F56517BDBP

R5F56517FDBP

R5F56514BDBP

R5F56514FDBP

PTBG0064KB-A 1 M

PTBG0064KB-A 768 K

PTBG0064KB-A 512 K

256 K

Not

included

120 MHz

Available

Available*

Not

available

–40 to +85

Not

included

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

Available

Not

included

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 19 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (7/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX651 R5F5651EDDLC

(D ver-

PTLG0177KA-A 2 M

640 K

32 K

120 MHz

Not

available

Available

–40 to +85

sion)

R5F5651EHDLC

PTLG0177KA-A 2 M

PTLG0177KA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

R5F5651CDDLC

Not

available

R5F5651CHDLC

R5F5651EDDLK

PTLG0177KA-A 1.5 M

PTLG0145KA-A 2 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F5651EHDLK

R5F5651CDDLK

PTLG0145KA-A 2 M

PTLG0145KA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F5651CHDLK

R5F56519ADLK

PTLG0145KA-A 1.5 M

PTLG0145KA-A 1 M

640 K

256 K

32 K

120 MHz

Available

–40 to +85

Not

included

available

R5F56519BDLK

R5F56519EDLK

R5F56519FDLK

R5F56517ADLK

R5F56517BDLK

R5F56517EDLK

R5F56517FDLK

R5F56514ADLK

R5F56514BDLK

R5F56514EDLK

R5F56514FDLK

R5F5651EDDLJ

PTLG0145KA-A 1 M

PTLG0145KA-A 768 K

PTLG0145KA-A 512 K

PTLG0100JA-A 2 M

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

32 K

Not

Available

available

R5F5651EHDLJ

R5F5651CDDLJ

PTLG0100JA-A 2 M

PTLG0100JA-A 1.5 M

640 K

32 K

120 MHz

Available

–40 to +85

Not

available

R5F5651CHDLJ

R5F56519ADLJ

PTLG0100JA-A 1.5 M

PTLG0100JA-A 1 M

640 K

256 K

32 K

120 MHz

Available

–40 to +85

Not

included

available

R5F56519BDLJ

R5F56519EDLJ

R5F56519FDLJ

R5F56517ADLJ

R5F56517BDLJ

PTLG0100JA-A 1 M

PTLG0100JA-A 768 K

256 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +85

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

Available

Not

included

available

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 20 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (8/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX651 R5F56517EDLJ

(D ver-

PTLG0100JA-A 768 K

PTLG0100JA-A 512 K

PLQP0176KB-A 2 M

256 K

Not

included

120 MHz

Available

Not

available

Not

available

–40 to +85

–40 to +105

sion)

R5F56517FDLJ

256 K

640 K

Not

included

120 MHz

Available

Not

available

R5F56514ADLJ

R5F56514BDLJ

R5F56514EDLJ

R5F56514FDLJ

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

RX651 R5F5651EDGFC

(G ver-

32 K

Not

available

Available

sion)

R5F5651EHGFC

640 K

32 K

120 MHz

Available

–40 to +105

R5F5651CDGFC PLQP0176KB-A 1.5 M

R5F5651CHGFC PLQP0176KB-A 1.5 M

Not

available

640 K

32 K

120 MHz

Available

–40 to +105

R5F5651EDGFB

PLQP0144KA-B 2 M

Not

available

R5F5651EHGFB

R5F5651CDGFB

PLQP0144KA-B 2 M

PLQP0144KA-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +105

Not

available

R5F5651CHGFB

R5F56519AGFB

PLQP0144KA-B 1.5 M

PLQP0144KA-B 1 M

640 K

256 K

32 K

120 MHz

Available

–40 to +105

Not

included

available

R5F56519BGFB

R5F56519EGFB

R5F56519FGFB

R5F56517AGFB

R5F56517BGFB

R5F56517EGFB

R5F56517FGFB

R5F56514AGFB

R5F56514BGFB

R5F56514EGFB

R5F56514FGFB

R5F5651EDGFP

PLQP0144KA-B 1 M

PLQP0144KA-B 768 K

PLQP0144KA-B 512 K

PLQP0100KB-B 2 M

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

–40 to +105

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

32 K

Not

Available

available

R5F5651EHGFP

R5F5651CDGFP

PLQP0100KB-B 2 M

PLQP0100KB-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +105

Not

available

R5F5651CHGFP

PLQP0100KB-B 1.5 M

640 K

32 K

120 MHz

Available

–40 to +105

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 21 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.3

List of Products (9/9)

CodeFlash

Memory

Capacity

(byte(s))

Data Flash

Memory

Capacity Capacity

RAM

Operating

Frequency Encryption

(Max.)

Operating

tempera-

SDHI/SDSI Dual bank ture (°C)

Group Part No.

Package

(byte(s))

Module

RX651 R5F56519AGFP

(G ver-

PLQP0100KB-B 1 M

PLQP0100KB-B 768 K

PLQP0100KB-B 512 K

256 K

Not

included

120 MHz

Not

available

Not

available

Not

available

–40 to +105

sion)

R5F56519BGFP

256 K

640 K

Not

included

120 MHz

Not

available

Available

Not

available

R5F56519EGFP

R5F56519FGFP

R5F56517AGFP

R5F56517BGFP

R5F56517EGFP

R5F56517FGFP

R5F56514AGFP

R5F56514BGFP

R5F56514EGFP

R5F56514FGFP

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

available

Not

included

Not

available

Available

Not

available

Not

included

Available

Not

available

Not

available

Not

included

Available

Available*

Not

available

1

R5F5651EDGFM PLQP0064KB-C 2 M

32 K

Not

Available

available

1

R5F5651EHGFM PLQP0064KB-C 2 M

R5F5651CDGFM PLQP0064KB-C 1.5 M

640 K

32 K

120 MHz

Available

Available*

Available

–40 to +105

Not

Available*

available

1

R5F5651CHGFM PLQP0064KB-C 1.5 M

640 K

256 K

32 K

120 MHz

Available

Available*

Available

–40 to +105

R5F56519BGFM

R5F56519FGFM

R5F56517BGFM

R5F56517FGFM

R5F56514BGFM

R5F56514FGFM

PLQP0064KB-C 1 M

PLQP0064KB-C 768 K

PLQP0064KB-C 512 K

Not

included

Not

available

Available*

Not

available

1

256 K

Not

included

120 MHz

Available

Available*

Not

available

–40 to +105

Not

included

Not

available

Not

available

Not

included

Available

Not

available

Not

included

Not

available

Not

available

Not

Available

Not

included

available

Note 1. Only SDHI is available.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 22 of 246

RX65N Group, RX651 Group

1. Overview

R

5

F 5 6 5 N E

H

D F C

Package type, number of pins, and pin pitch

FC: LFQFP/176/0.50

BG: LFBGA/176/0.80

LC: TFLGA/177/0.50

FB: LFQFP/144/0.50

LK: TFLGA/145/0.50

FP: LFQFP/100/0.50

LJ: TFLGA/100/0.65

FM: LFQFP/64/0.50

BP: TFBGA/64/0.50

D: Operating peripheral temperature:

–40 to +85°C

G: Operating peripheral temperature:

–40 to +105°C

A: Encryption module not included,

SDHI/SDSI module not included,

dual-bank structure not supported

B: Encryption module not included,

SDHI/SDSI module included,

dual-bank structure not supported

D: Encryption module not included,

SDHI/SDSI module included,

dual-bank structure

E: Encryption module included,

SDHI/SDSI module not included,

dual-bank structure not supported

F: Encryption module included,

SDHI/SDSI module included,

dual-bank structure not supported

H: Encryption module included,

SDHI/SDSI module included,

dual-bank structure

Code flash memory, RAM, and data flash memory capacity

4: 512 Kbytes/256 Kbytes/Not included

7: 768 Kbytes/256 Kbytes/Not included

9: 1 Mbyte/256 Kbytes/Not included

C: 1.5 Mbytes/640 Kbytes/32 Kbytes

E: 2 Mbytes/640 Kbytes/32 Kbytes

Group name

5N: RX65N Group

51: RX651 Group

Series name

RX600 Series

Type of memory

F: Flash memory version

Renesas MCU

Renesas semiconductor product

Figure 1.1

How to Read the Product Part Number

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 23 of 246

RX65N Group, RX651 Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a block diagram.

Encryption functions^*1

Standby RAM

QSPI

AESa

RNG

SDHI^*1

MMCIF

Trusted Secure IP

PDC

WDTA

IWDTa

Data Flash

ELC

SCIi × 2 channels

RSPIc × 3 channels

MTU3a × 9 channels

ETHERC × 1 channel

CAC

DOC

CRCA

SCIg × 10 channels

SCIh × 1 channel

USBb × 1 port

CAN × 2 channels

POE3a

EDMACa ×

1 channel

Port 0

Port 1

Port 2

SDSI^*1

TPUa × 6 channels (unit 0)

GLCDC

DRW2D

PPG (unit 0)

PPG (unit 1)

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port J

Extended

RAM

TMRb × 2 channels (unit 0)

TMRb × 2 channels (unit 1)

CMT × 2 channels (unit 0)

CMT × 2 channels (unit 1)

RAM

ROM

ICUB

DTCb

CMTW × 1 channel (unit 0)

CMTW × 1 channel (unit 1)

RTCd

DMACAa ×

8 channels

RIICa × 3 channels

12-bit A/D converter × 8 channels (unit 0)

12-bit A/D converter × 21 channels (unit 1)

RX CPU

MPU

12-bit D/A converter × 2 channels

Temperature sensor

Clock

generation

circuit

EXDMACa

BSC

External bus

ETHERC:

EDMACa:

ICUB:

Ethernet controller

DMA controller for ethernet controller

Interrupt controller

Data transfer controller

DMA controller

EXDMA controller

Bus controller

Watchdog timer

Independent watchdog timer

CRC (cyclic redundancy check) calculator

PDC:

CAN:

Parallel data capture unit

CAN module

MTU3a:

POE3a:

TPUa:

PPG:

TMRb:

CMT:

CMTW:

RTCd:

RIICa:

DOC:

Multi-function timer pulse unit 3

Port output enable 3

16-bit timer pulse unit

Programmable pulse generator

8-bit timer

DTCb

DMACAa:

EXDMACa:

BSC:

WDTA:

IWDTa:

CRCA:

Compare match timer

Compare match timer W

Realtime clock

SCIg, SCIh, SCIi:Serial communications interface

I²C bus interface

USBb:

RSPIc:

MPU:

QSPI:

SDHI:

SDSI:

MMCIF:

USB2.0 FS host/function module

Serial peripheral interface

Memory protection unit

Data operation circuit

CAC:

AESa:

RNG:

Clock frequency accuracy measurement circuit

*1

AES

*1

Quad serial peripheral interface

True random number generator

*1

SD host interface

GLCDC: Graphic-LCD controller

DRW2D: 2D drawing engine

Trusted Secure IP: Encryption engine

*1

SD slave interface

*1

MMC host interface

Note 1. Optional

Figure 1.2

Block Diagram

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Page 24 of 246

RX65N Group, RX651 Group

1. Overview

1.4

Pin Functions

Table 1.4 lists the pin functions.

Table 1.4

Pin Functions (1/8)

Pin Name

Classifications

I/O

Description

Digital power supply

VCC

Input

Power supply pin. Connect this pin to the system power supply.

Connect the pin to VSS via a 0.1-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

VCL

Input

Connect this pin to VSS via a 0.22-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

VSS

Input

Ground pin. Connect it to the system power supply (0 V).

Backup power pin

VBATT

XTAL

Clock

Output Pins for a crystal resonator. An external clock signal can be

input through the EXTAL pin.

EXTAL

BCLK

SDCLK

XCOUT

XCIN

Input

Output Outputs the external bus clock for external devices.

Output Outputs the SDRAM-dedicated clock.

Output Input/output pins for the sub clock oscillator. Connect a crystal

resonator between XCOUT and XCIN.

Input

Clock frequency accuracy CACREF

measurement

Input

Reference clock input pin for the clock frequency accuracy

measurement circuit

Operating mode control

MD

Pin for setting the operating mode. The signal level on this pin

must not be changed during operation.

UB

Input

USB boot mode enable pin

UPSEL

Selects the power supply method in USB boot mode.

The low level selects self-powered mode and the high level

selects bus-powered mode.

System control

RES#

EMLE

Input

Reset signal input pin. This LSI enters the reset state when this

signal goes low.

Input pin for the on-chip emulator enable signal. When the on-

chip emulator is used, this pin should be driven high. When not

used, it should be driven low.

BSCANP

Input

Boundary scan enable pin. Boundary scan is enabled when this

pin goes high. When not used, it should be driven low.

On-chip emulator

FINED

TRST#

TMS

I/O

Fine interface pin

Input

Output

On-chip emulator or boundary scan pins. When the EMLE pin is

driven high, these pins are dedicated for the on-chip emulator.

TDI

TCK

TDO

TRCLK

Output This pin outputs the clock for synchronization with the trace

data.

TRSYNC

TRSYNC1

Output These pins indicate that output from the TRDATA0 to TRDATA7

pins is valid.

TRDATA0

TRDATA1

TRDATA2

TRDATA3

TRDATA4

TRDATA5

TRDATA6

TRDATA7

Output These pins output the trace information.

Address bus

Data bus

A0 to A23

D0 to D31

Output Output pins for the address

I/O Input and output pins for the bidirectional data bus

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RX65N Group, RX651 Group

1. Overview

Table 1.4

Pin Functions (2/8)

Pin Name

Classifications

Multiplexed bus

Bus control

I/O

Description

A0/D0 to A15/D15

I/O

Address/data multiplexed bus

RD#

Output Strobe signal which indicates that reading from the external bus

interface space is in progress

WR#

Output Strobe signal which indicates that writing to the external bus

interface space is in progress, in 1-write strobe mode

WR0# to WR3#

Output Strobe signals which indicate that either group of data bus pins

(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in

writing to the external bus interface space, in byte strobe mode

BC0# to BC3#

ALE

Output Strobe signals which indicate that either group of data bus pins

(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in

access to the external bus interface space, in 1-write strobe

mode

Output Address latch signal when address/data multiplexed bus is

selected

WAIT#

Input

Input pin for wait request signals in access to the external space

CS0# to CS7#

CKE

Output Select signals for CS areas

Output SDRAM clock enable signal

Output SDRAM chip select signal

SDCS#

RAS#

Output SDRAM row address strobe signal

Output SDRAM column address strove signal

Output SDRAM write enable pin

CAS#

WE#

DQM0 to DQM3

EDREQ0, EDREQ1

EDACK0, EDACK1

NMI

Output SDRAM I/O data mask enable signals

EXDMA controller

Interrupt

Input

External DMA transfer request pins

Output Single address transfer acknowledge signals

Input

Non-maskable interrupt request pin

Maskable interrupt request pins

IRQ0 to IRQ15, IRQ0-DS to

IRQ15-DS

Multi-function timer pulse MTIOC0A, MTIOC0B,

I/O

The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins

unit 3

MTIOC0C, MTIOC0D

MTIOC1A, MTIOC1B

I/O

The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins

MTIOC2A, MTIOC2B

I/O

The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins

MTIOC3A, MTIOC3B,

MTIOC3C, MTIOC3D

I/O

The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins

MTIOC4A, MTIOC4B,

MTIOC4C, MTIOC4D

I/O

The TGRA4 to TGRD4 input capture input/output compare

output/PWM output pins

MTIC5U, MTIC5V, MTIC5W

Input

I/O

The TGRU5, TGRV5, and TGRW5 input capture input/dead

time compensation input pins

MTIOC6A, MTIOC6B,

MTIOC6C, MTIOC6D

The TGRA6 to TGRD6 input capture input/output compare

output/PWM output pins

MTIOC7A, MTIOC7B,

MTIOC7C, MTIOC7D

I/O

The TGRA7 to TGRD7 input capture input/output compare

output/PWM output pins

MTIOC8A, MTIOC8B,

MTIOC8C, MTIOC8D

I/O

The TGRA8 to TGRD8 input capture input/output compare

output/PWM output pins

MTCLKA, MTCLKB,

MTCLKC, MTCLKD

Input

Input pins for external clock signals or for phase counting mode

clock signals

Port output enable 3

POE0#, POE4#, POE8#,

POE10#, POE11#

Input pins for request signals to place the MTU in the high

impedance state

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RX65N Group, RX651 Group

1. Overview

Table 1.4

Pin Functions (3/8)

Pin Name

Classifications

I/O

Description

16-bit timer pulse unit

TIOCA0, TIOCB0,

TIOCC0, TIOCD0

I/O

The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins

TIOCA1, TIOCB1

I/O

The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins

TIOCA2, TIOCB2

I/O

The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins

TIOCA3, TIOCB3,

TIOCC3, TIOCD3

I/O

The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins

TIOCA4, TIOCB4

I/O

The TGRA4 and TGRB4 input capture input/output compare

output/PWM output pins

TIOCA5, TIOCB5

I/O

The TGRA5 and TGRB5 input capture input/output compare

output/PWM output pins

TCLKA, TCLKB,

TCLKC, TCLKD

Input

Input pins for external clock signals or for phase counting mode

clock signals

Programmable pulse

generator

PO0 to PO31

Output Output pins for the pulse signals

8-bit timer

TMO0 to TMO3

TMCI0 to TMCI3

TMRI0 to TMRI3

TIC0 to TIC3

Output Compare match output pins

Input

Input pins for external clocks to be input to the counter

Input pins for the counter reset

Compare match timer W

Input pins for CMTW

TOC0 to TOC3

Output Output pins for CMTW

Serial communications

interface (SCIg)

 Asynchronous mode/clock synchronous mode

SCK0 to SCK9

RXD0 to RXD9

TXD0 to TXD9

CTS0# to CTS9#

RTS0# to RTS9#

I/O

Input/output pins for the clock

Input pins for received data

Input

Output Output pins for transmitted data

Input Input pins for controlling the start of transmission and reception

Output Output pins for controlling the start of transmission and

reception

 Simple I²C mode

SSCL0 to SSCL9

SSDA0 to SSDA9

 Simple SPI mode

SCK0 to SCK9

I/O

Input/output pins for the I²C clock

Input/output pins for the I²C data

I/O

Input/output pins for the clock

SMISO0 to SMISO9

SMOSI0 to SMOSI9

SS0# to SS9#

I/O

Input/output pins for slave transmission of data

Input/output pins for master transmission of data

Chip-select input pins

I/O

Input

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RX65N Group, RX651 Group

1. Overview

Table 1.4

Pin Functions (4/8)

Pin Name

Classifications

I/O

Description

Serial communications

interface (SCIh)

 Asynchronous mode/clock synchronous mode

SCK12

I/O

Input/output pin for the clock

Input pin for received data

RXD12

Input

TXD12

Output Output pin for transmitted data

Input Input pin for controlling the start of transmission and reception

Output Output pin for controlling the start of transmission and reception

CTS12#

RTS12#

 Simple I²C mode

SSCL12

I/O

Input/output pin for the I²C clock

Input/output pin for the I²C data

SSDA12

 Simple SPI mode

SCK12

I/O

Input/output pin for the clock

SMISO12

SMOSI12

SS12#

I/O

Input/output pin for slave transmission of data

Input/output pin for master transmission of data

Chip-select input pin

I/O

Input

 Extended serial mode

RXDX12

Input

Input pin for received data

TXDX12

Output Output pin for transmitted data

I/O Input/output pin for received or transmitted data

SIOX12

Serial communications

interface (SCIi)

 Asynchronous mode/clock synchronous mode

SCK10 and SCK11

RXD10 and RXD11

TXD10 and TXD11

CTS10# and CTS11#

RTS10# and RTS11#

 Simple I²C mode

SSCL10 and SSCL11

SSDA10 and SSDA11

 Simple SPI mode

SCK10 and SCK11

SMISO10 and SMISO11

SMOSI10 and SMOSI11

SS10# and SS11#

I/O

Input/output pin for the clock

Input pin for received data

Input

Output Output pin for transmitted data

Input Input pin for controlling the start of transmission and reception

Output Output pin for controlling the start of transmission and reception

I/O

Input/output pin for the I²C clock

Input/output pin for the I²C data

I/O

Input/output pin for the clock

I/O

Input/output pin for slave transmission of data

Input/output pin for master transmission of data

Chip-select input pin

I/O

Input

I/O

I²C bus interface

SCL0[FM+], SCL1, SCL2,

SCL2-DS

Input/output pins for clocks. Bus can be directly driven by

the N-channel open drain

SDA0[FM+], SDA1, SDA2,

SDA2-DS

I/O

Input/output pins for data. Bus can be directly driven by

the N-channel open drain

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RX65N Group, RX651 Group

1. Overview

Table 1.4

Pin Functions (5/8)

Pin Name

Classifications

I/O

Description

Ethernet controller

REF50CK0

Input

50-MHz reference clocks. These pins input reference signals for

transmission/reception timings in RMII mode.

RMII0_CRS_DV

Input

Indicate that there are carrier detection signals and valid

receive data on RMII0_RXD1 and RMII0_RXD0 in RMII mode.

RMII0_TXD0, RMII0_TXD1

RMII0_RXD0, RMII0_RXD1

RMII0_TXD_EN

Output 2-bit transmit data in RMII mode

Input 2-bit receive data in RMII mode

Output Output pins for data transmit enable signals in RMII mode

RMII0_RX_ER

Input

Indicate an error has occurred during reception of data in RMII

mode.

ET0_CRS

Input

Carrier detection/data reception enable pins

ET0_RX_DV

Indicate that there are valid receive data on ET0_ERXD3 to

ET0_ERXD0.

ET0_EXOUT

Output General-purpose external output pins

Input Input link status from the PHY-LSI.

Output 4 bits of MII transmit data

Input 4 bits of MII receive data

ET0_LINKSTA

ET0_ETXD0 to ET0_ETXD3

ET0_ERXD0 to ET0_ERXD3

ET0_TX_EN

Output Transmit enable pins. Function as signals indicating that

transmit data is ready on ET0_ETXD3 to ET0_ETXD0.

ET0_TX_ER

ET0_RX_ER

ET0_TX_CLK

Output Transmit error pins. Function as signals notifying the PHY-LSI of

an error during transmission.

Input

Receive error pins. Function as signals to recognize an error

during reception.

Input

Transmit clock pins. These pins input reference signals for

output timings from ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0,

and ET0_TX_ER.

ET0_RX_CLK

Input

Receive clock pins. These pins input reference signals for input

timings to ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and

ET0_RX_ER.

ET0_COL

ET0_WOL

ET0_MDC

Input collision detection signals.

Output Receive Magic packets.

Output Output reference clock signals for information transfer via

ET0_MDIO.

ET0_MDIO

I/O

Input or output bidirectional signals for exchange of

management information between this MCU and the PHY-LSI.

USB 2.0 host/function

module

VCC_USB

Input

I/O

Power supply pin

VSS_USB

Ground pin

USB0_DP

Input or output USB transceiver D+ data.

Input or output USB transceiver D- data.

USB0_DM

I/O

USB0_EXICEN

USB0_ID

Output Connect to the OTG power IC.

Input Connect to the OTG power IC.

Output USB VBUS power enable pins

USB0_VBUSEN

USB0_OVRCURA/

USB0_OVRCURB

Input

USB overcurrent pins

USB0_VBUS

Input

USB cable connection/disconnection detection input pin

Input pins

CAN module

CRX0, CRX1, CRX1-DS

CTX0, CTX1

Output Output pins

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RX65N Group, RX651 Group

1. Overview

Table 1.4

Pin Functions (6/8)

Pin Name

Classifications

I/O

Description

Serial peripheral interface RSPCKA-A/RSPCKA-B/

RSPCKB-A/RSPCKB-B/

I/O

Clock input/output pins

RSPCKC-A/RSPCKC-B

MOSIA-A/MOSIA-B/

MOSIB-A/MOSIB-B/

MOSIC-A/MOSIC-B

I/O

Input or output data output from the master

Input or output data output from the slave

Input or output pins for slave selection

MISOA-A/MISOA-B/

MISOB-A/MISOB-B/

MISOC-A/MISOC-B

SSLA0-A/SSLA0-B/

SSLB0-A/SSLB0-B/

SSLC0-A/SSLC0-B

SSLA1-A/SSLA1-B/

SSLB1-A/SSLB1-B/

SSLC1-A/SSLC1-B,

SSLA2-A/SSLA2-B/

SSLB2-A/SSLB2-B/

SSLC2-A/SSLC2-B,

SSLA3-A/SSLA3-B/

SSLB3-A/SSLB3-B/

SSLC3-A/SSLC3-B

Output Output pins for slave selection

Quad serial peripheral

interface

QSPCLK-A/QSPCLK-B

QSSL-A/QSSL-B

Output QSPI clock output pins

Output QSPI slave output pins

QMO-A/QMO-B,

QIO0-A/QIO0-B

I/O

Master transmit data/data 0

Master input data/data 1

Data 2, data 3

QMI-A/QMI-B,

QIO1-A/QIO1-B

QIO2-A/QIO2-B,

QIO3-A/QIO3-B

MMC host interface

MMC_CLK-A/

MMC_CLK-B

Output MMC clock pins

MMC_CMD-A/

MMC_CMD-B

I/O

Command/response pins

MMC_D7-A/MMC_D7-B to

MMC_D0-A/MMC_D0-B

I/O

Transmit data/receive data

Card detection pins

MMC_CD-A/MMC_CD-B

Input

MMC_RES#-A/MMC_RES#-B Output MMC reset output pins

SD host interface

SDHI_CLK-A/SDHI_CLK-B/

SDHI_CLK-C

Output SD clock output pins

SDHI_CMD-A/SDHI_CMD-B/

SDHI_CMD-C

I/O

SD command output, response input signal pins

SDHI_D3-A/SDHI_D3-B/

SDHI_D3-C to SDHI_D0-A/

SDHI_D0-B/SDHI_D0-C

SD data bus pins

SDHI_CD

Input

I/O

SD card detection pin

SDHI_WP

SD write-protect signal

SD slave interface

SDSI_CLK-A/SDSI_CLK-B

SDSI_CMD-A/SDSI_CMD-B

SD clock input pins

SD command input, response output signal pins

SD data bus pins

SDSI_D3-A/SDSI_D3-B,

SDSI_D2-A/SDSI_D2-B,

SDSI_D1-A/SDSI_D1-B,

SDSI_D0-A/SDSI_D0-B

I/O

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RX65N Group, RX651 Group

1. Overview

Table 1.4

Pin Functions (7/8)

Pin Name

Classifications

I/O

Description

Parallel data capture unit PIXCLK

Input

Image transfer clock pin

Vertical synchronization signal pin

Horizontal synchronization signal pin

8-bit image data pins

VSYNC

HSYNC

PIXD0 to PIXD7

PCKO

Output Output pin for dot clock

Output Panel clock output pins

Output Control signal output pins

Graphic-LCD controller

LCD_CLK-A, LCD_CLK-B

LCD_TCON3-A/

LCD_TCON3-B to

LCD_TCON0-A/

LCD_TCON0-B

LCD_DATA23-A/

LCD_DATA23-B to

LCD_DATA0-A/

LCD_DATA0-B

Output LCD signal output pins

LCD_EXTCLK-A,

LCD_EXTCLK-B

Input

Panel clock source input pins

Realtime clock

RTCOUT

Output Output pin for 1-Hz/64-Hz clock

RTCIC0 to RTCIC2

Input

Time capture event input pins

12-bit A/D converter

AN000 to AN007,

AN100 to AN120

Input pins for the analog signals to be processed by the A/D

converter

ADTRG0#, ADTRG1#

Input

Input pins for the external trigger signals that start the A/D

conversion

ANEX0

Output Extended analog output pin

Input Extended analog input pin

ANEX1

12-bit D/A converter

Analog power supply

DA0, DA1

Output Output pins for the analog signals to be processed by the D/A

converter

AVCC0

AVSS0

Input

Analog voltage supply pin for the 12-bit A/D converter (unit 0).

Connect this pin to a branch from the VCC power supply.

Connect the pin to AVSS0 via a 0.1-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

Analog ground pin for the 12-bit A/D converter (unit 0). Connect

this pin to a branch from the VSS ground power supply.

Connect the pin to AVCC0 via a 0.1-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

VREFH0

VREFL0

AVCC1

Input

Analog reference voltage supply pin for the 12-bit A/D converter

(unit 0). Connect this pin to VCC if the 12-bit A/D converter is

not to be used.

Analog reference ground pin for the 12-bit A/D converter (unit

0). Connect this pin to VSS if the 12-bit A/D converter is not to

be used.

Analog voltage supply and reference voltage supply pin for the

12-bit A/D converter (unit 1) and D/A converter. This pin also

supplies the analog voltage to the temperature sensor. Connect

this pin to a branch from the VCC power supply. Connect the

pin to AVSS1 via a 0.1-μF multilayer ceramic capacitor. The

capacitor should be placed close to the pin.

AVSS1

Input

Analog voltage supply and reference voltage supply pin for the

12-bit A/D converter (unit 1) and D/A converter. This pin also

supplies the analog ground voltage to the temperature sensor.

Connect this pin to a branch from the VSS ground power

supply. Connect the pin to AVCC1 via a 0.1-μF multilayer

ceramic capacitor. The capacitor should be placed close to the

pin.

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RX65N Group, RX651 Group

1. Overview

Table 1.4

Pin Functions (8/8)

Pin Name

Classifications

I/O

Description

I/O ports

P00 to P03, P05, P07

6-bit input/output pins

8-bit input/output pins

8-bit input/output pins (P35: input pin)

8-bit input/output pins

6-bit input/output pins

8-bit input/output pins

5-bit input/output pins

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P80 to P87

P90 to P97

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE7

PF0 to PF5

PG0 to PG7

PJ0 to PJ3, PJ5

Note:

Note the following regarding pin names. For details, see section 1.5, Pin Assignments.

- When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group.

All RSPI, QSPI, SDHI, MMC, GLCDC AC timings are measured in combination with the pins in the same group.

- When the pin functions have “-DS” appended to their names, they can also be used as triggers for release from deep software

standby.

- RIIC pin functions that have [FM+] appended to their names support fast-mode plus.

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RX65N Group, RX651 Group

1. Overview

1.5

Pin Assignments

Figure 1.3 to Figure 1.11 show the pin assignments. Table 1.5 to Table 1.12 show the lists of pins and pin functions.

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

15

14

13

12

11

10

9

PE2

PE3

P70

P65

P67

VSS

VCC

PG7

PA6

PB0

P72

PB4

VSS

VCC

PC1

15

14

13

12

11

10

9

PE1

P63

PE0

P64

VSS

PG1

PD4

P96

PD1

P92

P91

P47

P41

VSS

PE4

P62

VCC

PG0

PD3

PD2

PD0

P90

P45

P43

PE7

VCC

PE5

P61

PD7

PD5

VSS

P95

P93

P44

P00

P03

P02

PG3

PG2

PE6

PA0

PG4

P66

PA1

PG6

PG5

PA2

PA3

PA4

PA7

VSS

PA5

VCC

P71

PB2

PB1

PB3

PB6

PB5

PB7

P77

P81

PC5

P50

P55

P85

PJ1

PJ2

P86

P24

P26

P73

PC0

PC3

P82

PC7

P51

P54

P84

PJ0

P12

P15

P22

P23

P75

PC2

PC4

PC6

P83

P52

P10

P57

P74

P76

P80

VCC

VSS

P53

P11

P56

P60

PD6

P97

VCC

P94

RX65N Group, RX651 Group

PTLG0177KA-A

8

(177-Pin TFLGA)

(Upper Perspective View)

7

VSS

7

VSS_

USB

USB0_

DP

6

VCC

P46

6

VCC_ USB0_

USB

5

NC

5

DM

4

P42

VSS BSCANP PF4

MD/

P35

RES#

VSS

PF3

P34

VCC

PF1

PF2

P32

P25

PF0

P30

P14

P13

4

3

VREFL0

AVCC0

P40 VREFH0

PF5

PJ3

P87

P17

P16

P20

3

FINED

2

P07

AVCC1

EMLE

VCL

XCOUT

2

1

AVSS0

A

P05

B

AVSS1

C

P01

D

PJ5

E

VBATT

F

XCIN

G

XTAL

H

EXTAL

J

P33

K

P31

L

P27

M

VCC

N

VSS

P

P21

R

1

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.5, List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA).

Figure 1.3

Pin Assignment (177-Pin TFLGA)

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RX65N Group, RX651 Group

1. Overview

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

15

14

13

12

11

10

9

PE2

PE3

P70

P65

P67

VSS

VCC

PG7

PA6

PB0

P72

PB4

VSS

VCC

PC1

P74

P76

P80

VCC

VSS

P53

P11

P56

15

14

13

12

11

10

9

PE1

P63

PE0

P64

VSS

PG1

PD4

P96

PD1

P92

P91

P47

P41

VSS

PE4

P62

VCC

PG0

PD3

PD2

PD0

P90

P45

P43

PE7

VCC

PE5

P61

PD7

PD5

VSS

P95

P93

P44

P00

P03

P02

PG3

PG2

PE6

PA0

PG4

P66

PA1

PG6

PG5

PA2

PA3

PA4

PA7

VSS

PA5

VCC

P71

PB2

PB1

PB3

PB6

PB5

PB7

P77

P81

PC5

P50

P55

P85

PJ1

PJ2

P86

P24

P26

P73

PC0

PC3

P82

PC7

P51

P54

P84

PJ0

P12

P15

P22

P23

P75

PC2

PC4

PC6

P83

P52

P10

P57

P60

PD6

P97

VCC

P94

RX65N Group, RX651 Group

PTBG0176GA-A

8

(176-Pin LFBGA)

(Upper Perspective View)

7

VSS

7

VSS_

USB

USB0_

DP

6

VCC

P46

6

VCC_ USB0_

USB

5

DM

4

P42

VSS BSCANP PF4

MD/

P35

RES#

VSS

PF3

P34

VCC

PF1

PF2

P32

P25

PF0

P30

P14

P13

4

3

VREFL0

AVCC0

P40 VREFH0

PF5

PJ3

P87

P17

P16

P20

3

FINED

2

P07

AVCC1

EMLE

VCL

XCOUT

2

1

AVSS0

A

P05

B

AVSS1

C

P01

D

PJ5

E

VBATT

F

XCIN

G

XTAL

H

EXTAL

J

P33

K

P31

L

P27

M

VCC

N

VSS

P

P21

R

1

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.5, List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA).

Figure 1.4

Pin Assignment (176-Pin LFBGA)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 34 of 246

RX65N Group, RX651 Group

1. Overview

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

PE2

PE1

PE0

P64

P63

P62

P61

VSS

P60

VCC

PD7

PG1

PD6

PG0

PD5

PD4

P97

PD3

VSS

P96

VCC

PD2

P95

PD1

P94

PD0

P93

P92

P91

P74

P75

PC2

P76

P77

PC3

PC4

P80

P81

P82

PC5

PC6

PC7

VCC

P83

VSS

P50

P51

P52

P53

P10

P11

RX65N Group, RX651 Group

PLQP0176KB-A

P54

P55

P56

P57

P84

P85

PJ0

PJ1

(176-pin LFQFP)

(Top view)

VSS

P90

VCC

P47

P46

P45

P44

P43

P42

P41

PJ2

VSS_USB

USB0_DP

USB0_DM

VCC_USB

P12

P13

P14

P15

P86

P16

P87

P17

P20

VREFL0

P40

VREFH0

AVCC0

P07

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.6, List of Pin and Pin Functions (176-Pin LFQFP).

Figure 1.5

Pin Assignment (176-Pin LFQFP)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 35 of 246

RX65N Group, RX651 Group

1. Overview

A

B

C

D

E

F

G

H

J

K

L

M

N

13

12

11

10

9

PE3

PE4

VSS

PE6

P67

PA2

PA4

PA7

PB1

PB5

VSS

VCC

P74

13

12

11

10

9

PE1

P62

VSS

PD6

PD2

P92

P90

P45

P42

P40

P07

PE2

P61

P70

PE0

PE5

VCC

PE7

P64

P60

PD5

P93

VCC

P01

P03

PF5

P65

P66

PA0

PA1

VSS

PA3

VCC

PA6

PA5

PB0

P71

P72

PB2

PB4

PB3

PB6

PB7

P76

P80

VCC

P51

P53

P54

P15

P31

P26

P73

PC2

PC4

PC5

P83

P52

P56

P13

P24

P16

P23

PC1

PC0

P77

P81

PC6

P50

P75

PC3

P82

PC7

VSS

P55

VCC

PD4

P63

PD7

RX65N Group, RX651

Group

PTLG0145KA-A

(145-Pin TFLGA)

(Upper Perspective View)

8

PD0

PD3

8

7

P91

PD1

7

VSS_

USB

USB0_

DP

6

P47

VSS

P46

6

VCC_

USB

USB0_

DM

5

P43

P44

5

4

VREFL0

P05

P41

EMLE

PJ5

VBATT BSCANP

P35

VSS

VCC

P30

P32

P33

P12

P86

P17

P14

P87

P20

4

MD/

PJ3

3

VREFH0

P02

3

FINED

2

AVCC0

VCL

XCOUT

RES#

2

1

AVSS0

A

AVCC1

B

AVSS1

C

P00

D

VSS

E

XCIN

F

XTAL

G

EXTAL

H

P34

J

P27

K

P25

L

P22

M

P21

N

1

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.7, List of Pin and Pin Functions (145-Pin TFLGA).

Figure 1.6

Pin Assignment (145-Pin TFLGA)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 36 of 246

RX65N Group, RX651 Group

1. Overview

109

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

PE2

P74

110

PE1

P75

PC2

P76

P77

PC3

PC4

P80

111

PE0

112

P64

113

P63

114

P62

115

P61

116

VSS

117

P81

P82

PC5

PC6

PC7

P60

118

VCC

119

PD7

120

PD6

121

PD5

122

PD4

VCC

P83

123

PD3

124

PD2

VSS

P50

P51

P52

P53

P54

P55

P56

125

PD1

RX65N Group, RX651 Group

PLQP0144KA-B

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

PD0

P93

P92

P91

(144-pin LFQFP)

(Top view)

VSS

P90

VCC

VSS_USB

USB0_DP

USB0_DM

P47

P46

VCC_USB

P12

P45

P44

P13

P43

P14

P42

P15

P41

VREFL0

P86

P40

VREFH0

AVCC0

P07

P16

P87

P17

P20

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.8, List of Pin and Pin Functions (144-Pin LFQFP).

Figure 1.7

Pin Assignment (144-Pin LFQFP)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 37 of 246

RX65N Group, RX651 Group

1. Overview

RX65N Group, RX651 Group

PTLG0100JA-A (100-Pin TFLGA)

(Upper Perspective View)

A

B

C

D

E

F

G

H

J

K

10

9

PE2

PE3

PE4

PA0

PA3

VSS

VCC

PB7

PC1

PC2

10

9

PE1

PE0

PD7

PD6

PE5

PD5

PA1

PE7

PA5

PA4

PA6

PA2

P41

PA7

PB0

PB2

PB3

P12

P32

P35

VCC

PB1

PB4

PB5

P52

P53

P27

P30

P31

PB6

PC6

PC7

P54

P55

P15

P16

P25

PC0

PC4

P50

PC3

PC5

P51

8

7

PD4

PD3

PD2

PE6

7

VCC_

USB

USB0_

DP

6

PD0

PD1

P47

P46

6

VSS_

USB

USB0_

DM

5

P43

P44

P42

P45

5

4

VREFL0

P07

P40

VREFH0

PJ3

VBATT

P34

P13

P17

P21

P14

P20

P22

4

MD/

3

AVCC0

AVSS0

RES#

VSS

3

FINED

2

AVCC1

AVSS1

XCOUT

2

1

P05

A

EMLE

B

VCL

C

XCIN

D

XTAL

E

EXTAL

F

P33

G

P26

H

P24

J

P23

K

1

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.9, List of Pin and Pin Functions (100-Pin TFLGA).

Figure 1.8

Pin Assignment (100-Pin TFLGA)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 38 of 246

RX65N Group, RX651 Group

1. Overview

76

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

PE2

PC2

PC3

77

PE1

78

PE0

PC4

79

PD7

PC5

80

PD6

PC6

81

PD5

PC7

82

PD4

P50

83

PD3

P51

84

PD2

P52

85

PD1

P53

RX65N Group, RX651 Group

PLQP0100KB-B

86

PD0

P54

87

P47

P55

88

P46

VSS_USB

USB0_DP

USB0_DM

VCC_USB

P12

89

(100-pin LFQFP)

(Top view)

P45

90

P44

91

P43

92

P42

93

P41

P13

94

VREFL0

P14

95

P40

P15

96

VREFH0

P16

97

AVCC0

P17

98

P07

P20

99

AVSS0

P21

100

P05

P22

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.10, List of Pin and Pin Functions (100-Pin LFQFP).

Figure 1.9

Pin Assignment (100-Pin LFQFP)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 39 of 246

RX65N Group, RX651 Group

1. Overview

RX651 Group

PTBG0064KB-A (64-Pin TFBGA)

(Upper Perspective View)

A

B

C

D

E

F

G

H

8

7

6

5

4

3

2

1

PE2

PE0

PE6

PE7

PA4

VSS

PB5

PC0

PC1

8

7

6

5

4

3

2

1

PE1

PD6

PA1

PD5

PA2

PA6

VCC

PA7

PB6

PB7

P53

P12

P35

VCC

PC5

PC7

PC4

PC6

PD7

PD2

PD3

PD4

P43

BSCANP

P13

VSS_USB USB0_DP

VCC_USB USB0_DM

VREFL0

VREFH0

AVSS0

P42

P41

P40

AVCC0

AVSS1

MD/FINED

VBATT

RES#

XCOUT

P34

P30

P31

P16

P17

VSS

AVCC1

A

EMLE

B

VCL

C

XCIN

D

XTAL

E

EXTAL

F

P27

G

P26

H

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.11, List of Pin and Pin Functions (64-Pin TFBGA).

Figure 1.10

Pin Assignment (64-Pin TFBGA)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 40 of 246

RX65N Group, RX651 Group

1. Overview

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

PE0

PC4

PD7

PD6

PC5

PC6

PD5

PC7

PD4

P53

PD3

VSS_USB

USB0_DP

USB0_DM

VCC_USB

P12

RX651 Group

PLQP0064KB-C

(64-pin LFQFP)

(Top view)

PD2

P43

P42

P41

VREFL0

P40

P13

P16

VREFH0

AVCC0

AVSS0

P05

P17

P27

P26

P31

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration,

see Table 1.12, List of Pin and Pin Functions (64-Pin LFQFP).

Figure 1.11

Pin Assignment (64-Pin LFQFP)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 41 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (1/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

A1

A2

A3

A4

AVSS0

AVCC0

VREFL0

P42

P46

IRQ10-

DS

AN002

AN006

A5

IRQ14-

DS

A6

A7

VCC

VSS

A8

P94

D20/A20

A9

VCC

A10

A11

TRSYNC1

P97

PD6

D23/A23

D6[A6/D6]

MTIC5V/

MTIOC8A/

POE4#

SSLC2-A

QMO-B/QIO0-B/

SDHI_D0-B/

MMC_D0-B

LCD_DA

TA18-B

IRQ6

AN106

A12

A13

P60

P63

CS0#

CAS#/

D2[A2/D2]/

CS3#

A14

PE1

D9[A9/D9]/

D1[A1/D1]

MTIOC4C/

MTIOC3B/

PO18

TXD12/

MMC_D5-B

MMC_D6-B

LCD_DA

TA15-B

ANEX1

SMOSI12/

SSDA12/

TXDX12/

SIOX12/SSLB2-

B

A15

PE2

D10[A10/

D10]/D2[A2/ PO23/TIC3

D2]

MTIOC4A/

RXD12/

LCD_DA

TA14-B

IRQ7-DS AN100

SMISO12/

SSCL12/

RXDX12/SSLB3-

B

B1

B2

P05

P07

IRQ13

IRQ15

DA1

ADTRG0

#

B3

B4

B5

P40

P41

P47

IRQ8-DS AN000

IRQ9-DS AN001

IRQ15-

DS

AN007

B6

B7

P91

P92

D17/A17

SCK7

AN115

AN116

D18/A18

POE4#

RXD7/SMISO7/

SSCL7

B8

PD1

D1[A1/D1]

MTIOC4B/

POE0#

MOSIC-A/CTX0

LCD_DA

TA23-B

IRQ1

IRQ4

AN109

B9

TRDATA5

P96

PD4

D22/A22

B10

D4[A4/D4]

MTIOC8B/

POE11#

SSLC0-A

QSSL-B/

SDHI_CMD-B/

MMC_CMD-B

LCD_DA

TA20-B

AN112

B11

B12

B13

TRDATA7

VSS

PG1

D25

P64

PE0

WE#/D3[A3/

D3]/CS4#

B14

D8[A8/D8]/

D0[A0/D0]

MTIOC3D

SCK12/SSLB1-B MMC_D4-B

LCD_DA

TA16-B

ANEX0

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 42 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (2/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

B15

PE3

D11[A11/

D11]/D3[A3/

D3]

MTIOC4B/

PO26/TOC3/

POE8#

ET0_ERXD3/

CTS12#/

RTS12#/SS12#

MMC_D7-B

LCD_DA

TA13-B

AN101

C1

C2

C3

C4

AVSS1

AVCC1

VREFH0

P43

P45

P90

PD0

PD2

PD3

PG0

IRQ11-

DS

AN003

AN005

AN114

AN108

AN110

AN111

C5

C6

C7

C8

C9

IRQ13-

DS

D16/A16

D0[A0/D0]

D2[A2/D2]

D3[A3/D3]

D24

TXD7/SMOSI7/

SSDA7

POE4#

LCD_EX

TCLK-B

IRQ0

IRQ2

IRQ3

MTIOC4D/TIC2 MISOC-A/CRX0

QIO2-B/SDHI_D2-

B/MMC_D2-B

LCD_DA

TA22-B

MTIOC8D/

TOC2/POE8#

RSPCKC-A

QIO3-B/SDHI_D3-

B/MMC_D3-B

LCD_DA

TA21-B

C10

C11

C12

TRDATA6

VCC

P62

PE4

RAS#/

D1[A1/D1]/

CS2#

C13

D12[A12/

D12]/D4[A4/ MTIOC1A/

D4]

MTIOC4D/

ET0_ERXD2/

SSLB0-B

LCD_DA

TA12-B

AN102

AN119

PO28

C14

C15

D1

VSS

P70

P01

SDCLK

TMCI0

TMCI1

RXD6/SMISO6/

SSCL6

IRQ9

D2

D3

D4

P02

P03

P00

SCK6

IRQ10

IRQ11

IRQ8

AN120

DA0

TMRI0

POE0#

TXD6/SMOSI6/

SSDA6

AN118

D5

D6

P44

P93

P95

IRQ12-

DS

AN004

AN117

D19/A19

D21/A21

CTS7#/RTS7#/

SS7#

D7

D8

D9

TRDATA4

VSS

PD5

PD7

P61

PE5

D5[A5/D5]

D7[A7/D7]

MTIC5W/

MTIOC8C/

POE10#

SSLC1-A

SSLC3-A

QSPCLK-B/

SDHI_CLK-B/

MMC_CLK-B

LCD_DA

TA19-B

IRQ5

IRQ7

AN113

AN107

D10

D11

D12

D13

MTIC5U/

POE0#

QMI-B/QIO1-B/

SDHI_D1-B/

MMC_D1-B

LCD_DA

TA17-B

SDCS#/

D0[A0/D0]/

CS1#

D13[A13/

D13]/D5[A5/ MTIOC2B

D5]

MTIOC4C/

ET0_RX_CLK/

REF50CK0/

RSPCKB-B

LCD_DA

TA11-B

IRQ5

AN103

VCC

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 43 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (3/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

D14

PE7

D15[A15/

D15]/D7[A7/ TOC1

D7]

MTIOC6A/

MISOB-B

SDHI_WP/

MMC_RES#-B

LCD_DA

TA9-B

IRQ7

AN105

D15

E1

P65

PJ5

CKE/CS5#

POE8#

CTS2#/RTS2#/

SS2#

E2

E3

EMLE

PF5

PE6

IRQ4

IRQ6

E4

VSS

NC

E5 *¹

E12

D14[A14/

D14]/D6[A6/

D6]

MTIOC6C/TIC1 MOSIB-B

SDHI_CD/

MMC_CD-B

LCD_DA

TA10-B

AN104

E13

E14

E15

F1

TRDATA0

TRDATA1

PG2

PG3

P67

D26

D27

DQM1/CS7# MTIOC7C

IRQ15

VBATT

VCL

F2

F3

PJ3

EDACK1

MTIOC3C

ET0_EXOUT/

CTS6#/RTS6#/

SS6#/CTS0#/

RTS0#/SS0#

F4

BSCANP

TRSYNC

F12

F13

F14

P66

PG4

PA0

DQM0/CS6# MTIOC7D

D28

DQM2/

MTIOC4A/

MTIOC6D/

ET0_TX_EN/

RMII0_TXD_EN/

LCD_DA

TA8-B

BC0#/A0

TIOCA0/PO16/ SSLA1-B

CACREF

F15

G1

VSS

XCIN

G2

XCOUT

MD/FINED

TRST#

TRCLK

TRDATA2

G3

G4

PF4

PG5

PG6

PA1

G12

G13

G14

D29

D30

DQM3/A1

MTIOC0B/

MTCLKC/

ET0_WOL/

SCK5/SSLA2-B

LCD_DA

TA7-B

IRQ11

MTIOC7B/

TIOCB0/PO17

G15

H1

VCC

XTAL

VSS

P37

H2

H3

RES#

UPSEL

H4

P35

PA4

NMI

H12

A4

MTIC5U/

MTCLKA/

TIOCA1/

ET0_MDC/TXD5/

SMOSI5/SSDA5/

SSLA0-B

LCD_DA

TA4-B

IRQ5-DS

TMRI0/PO20

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 44 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (4/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

H13

PA3

A3

MTIOC0D/

MTCLKD/

TIOCD0/

ET0_MDIO/

RXD5/SMISO5/

SSCL5

LCD_DA

TA5-B

IRQ6-DS

TCLKB/PO19

H14

PA2

A2

MTIOC7A/

PO18

RXD5/SMISO5/

SSCL5/SSLA3-B

LCD_DA

TA6-B

H15

J1

TRDATA3

EXTAL

VCC

PG7

P36

D31

J2

J3

P34

MTIOC0A/

TMCI3/PO12/

POE10#

ET0_LINKSTA/

SCK6/SCK0

IRQ4

J4

TMS

VSS

PF3

PA5

J12

A5

MTIOC6B/

TIOCB1/PO21

ET0_LINKSTA/

RSPCKA-B

LCD_DA

TA3-B

J13

J14

PA7

PA6

A7

A6

TIOCB2/PO23

ET0_WOL/

MISOA-B

LCD_DA

TA1-B

J15

MTIC5V/

MTCLKB/

TIOCA2/

ET0_EXOUT/

CTS5#/RTS5#/

SS5#/MOSIA-B

LCD_DA

TA2-B

TMCI3/PO22/

POE10#

K1

P33

P32

EDREQ1

MTIOC0D/

TIOCD0/

TMRI3/PO11/

POE4#/

RXD6/SMISO6/

SSCL6/RXD0/

SMISO0/SSCL0/

CRX0

PCKO

IRQ3-DS

IRQ2-DS

POE11#

K2

MTIOC0C/

TIOCC0/

TMO3/PO10/

RTCIC2/

TXD6/SMOSI6/

SSDA6/TXD0/

SMOSI0/SSDA0/

CTX0/

VSYNC

RTCOUT/

POE0#/

USB0_VBUSEN

POE10#

K3

TDI

PF2

RXD1/SMISO1/

SSCL1

K4

TCK

PF1

PB2

SCK1

K12

A10

TIOCC3/

TCLKC/PO26

ET0_RX_CLK/

REF50CK0/

SDSI_D2-B

LCD_TC

ON2-B

CTS4#/RTS4#/

SS4#/CTS6#/

RTS6#/SS6#

K13

K14

K15

P71

PB0

A18/CS1#

A8

ET0_MDIO

VCC

MTIC5W/

TIOCA3/PO24

ET0_ERXD1/

RMII0_RXD1/

RXD4/SMISO4/

SSCL4/RXD6/

SMISO6/SSCL6

LCD_DA

TA0-B

IRQ12

L1

L2

P31

P30

MTIOC4D/

TMCI2/PO9/

RTCIC1

CTS1#/RTS1#/

SS1#/SSLB0-A

IRQ1-DS

IRQ0-DS

MTIOC4B/

TMRI3/PO8/

RTCIC0/

RXD1/SMISO1/

SSCL1/MISOB-A

POE8#

L3

TDO

PF0

TXD1/SMOSI1/

SSDA1

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 45 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (5/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

L4

P25

CS5#/

EDACK1

MTIOC4C/

MTCLKB/

RXD3/SMISO3/

SSCL3

SDHI_CD/HSYNC

ADTRG0

#

TIOCA4/PO5

L12

PB6

A14

MTIOC3D/

TIOCA5/PO30

ET0_ETXD1/

RMII0_TXD1/

RXD9/SMISO9/

SSCL9/

SDSI_D0-B

SMISO11/

SSCL11/RXD11

L13

L14

PB3

PB1

A11

A9

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/TMO0/

PO27/POE11#

ET0_RX_ER/

RMII0_RX_ER/

SCK4/SCK6

SDSI_D3-B

LCD_TC

ON1-B

MTIOC0C/

MTIOC4C/

TIOCB3/

ET0_ERXD0/

RMII0_RXD0/

TXD4/SMOSI4/

SSDA4/TXD6/

SMOSI6/SSDA6

LCD_TC

ON3-B

IRQ4-DS

TMCI0/PO25

L15

M1

M2

P72

P27

P26

A19/CS2#

CS7#

ET0_MDC

LCD_DA

TA23-A

MTIOC2B/

TMCI3/PO7

SCK1/RSPCKB-

A

CS6#

MTIOC2A/

TMO1/PO6

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/SS3#/

MOSIB-A

M3

P24

CS4#/

EDREQ1

MTIOC4A/

MTCLKA/

TIOCB4/

SCK3/

USB0_VBUSEN

SDHI_WP/PIXCLK

PIXD1

TMRI1/PO4

M4

M5

M6

M7

M8

P86

PJ2

PJ1

P85

P55

MTIOC4D/

TIOCA0

SMISO10/

SSCL10/RXD10

TXD8/SMOSI8/

SSDA8/SSLC3-B

LCD_TC

ON2-A

MTIOC6A

RXD8/SMISO8/

SSCL8/SSLC2-B

LCD_TC

ON3-A

MTIOC6C/

TIOCC0

LCD_DA

TA1-A

D0[A0/D0]/

EDREQ0/

WAIT#

MTIOC4D/

TMO3

ET0_EXOUT/

TXD7/SMOSI7/

SSDA7/MISOC-

B/CRX1

LCD_DA

TA5-A

IRQ10

M9

P50

PC5

WR0#/WR#

TXD2/SMOSI2/

SSDA2/SSLB1-A

M10

D3[A3/D3]/

A21/CS2#/

WAIT#

MTIOC3B/

MTCLKD/

TMRI2/PO29

ET0_ETXD2/

SCK8/SCK10/

RSPCKA-A

MMC_D5-A

LCD_DA

TA11-A

M11

M12

M13

P81

P77

PB7

EDACK0

MTIOC3D/

PO27

ET0_ETXD0/

RMII0_TXD0/

SMISO10/

QIO3-A/SDHI_CD/

MMC_D3-A

LCD_DA

TA13-A

SSCL10/RXD10

CS7#

PO23

ET0_RX_ER/

RMII0_RX_ER/

SMOSI11/

QSPCLK-A/

LCD_DA

TA17-A

SDHI_CLK-A/

SDSI_CLK-A/

MMC_CLK-A

SSDA11/TXD11

A15

MTIOC3B/

ET0_CRS/

SDSI_D1-B

TIOCB5/PO31

RMII0_CRS_DV/

TXD9/SMOSI9/

SSDA9/

SMOSI11/

SSDA11/TXD11

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 46 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (6/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

M14

PB5

A13

MTIOC2A/

MTIOC1B/

TIOCB4/

ET0_ETXD0/

RMII0_TXD0/

SCK9/SCK11

SDSI_CLK-B

LCD_CL

K-B

TMRI1/PO29/

POE4#

M15

PB4

A12

TIOCA4/PO28

ET0_TX_EN/

SDSI_CMD-B

LCD_TC

ON0-B

RMII0_TXD_EN/

CTS9#/RTS9#/

SS9#/SS11#/

CTS11#/RTS11#

N1

N2

VCC

P23

P22

EDACK0

EDREQ0

MTIOC3D/

MTCLKD/

TIOCD3/PO3

TXD3/SMOSI3/

SSDA3/CTS0#/

RTS0#/SS0#

SDHI_D1-C/PIXD7

SDHI_D0-C/PIXD6

N3

N4

MTIOC3B/

MTCLKC/

TIOCC3/

SCK0/

USB0_OVRCUR

B

TMO0/PO2

P15

P12

MTIOC0B/

MTCLKB/

TIOCB2/

TCLKB/TMCI2/

PO13

RXD1/SMISO1/

SSCL1/SCK3/

CRX1-DS

PIXD0

IRQ5

IRQ2

N5

WR3#/BC3# MTIC5U/

TMCI1

RXD2/SMISO2/

SSCL2/

LCD_TC

ON1-A

SCL0[FM+]

N6

N7

N8

PJ0

P84

P54

MTIOC6B

MTIOC6D

SCK8/SSLC1-B

LCD_DA

TA0-A

LCD_DA

TA2-A

D1[A1/D1]/

EDACK0/

ALE

MTIOC4B/

TMCI1

ET0_LINKSTA/

CTS2#/RTS2#/

SS2#/MOSIC-B/

CTX1

LCD_DA

TA6-A

N9

P51

PC7

WR1#/

BC1#/

WAIT#

SCK2/SSLB2-A

N10

UB

A23/CS0#

MTIOC3A/

MTCLKB/

TMO2/PO31/

TOC0/

ET0_COL/TXD8/ MMC_D7-A

SMOSI8/SSDA8/

SMOSI10/

SSDA10/TXD10/

MISOA-A

LCD_DA

TA9-A

IRQ14

CACREF

N11

N12

P82

PC3

EDREQ1

A19

MTIOC4A/

PO28

ET0_ETXD1/

RMII0_TXD1/

SMOSI10/

MMC_D4-A

LCD_DA

TA12-A

SSDA10/TXD10

MTIOC4D/

TCLKB/PO24

ET0_TX_ER/

TXD5/SMOSI5/

SSDA5

QMO-A/QIO0-A/

SDHI_D0-A/

SDSI_D0-A/

MMC_D0-A

LCD_DA

TA16-A

N13

N14

PC0

P73

A16

MTIOC3C/

TCLKC/PO17

ET0_ERXD3/

CTS5#/RTS5#/

SS5#/SSLA1-A

IRQ14

CS3#

PO16

ET0_WOL

LCD_EX

TCLK-A

N15

P1

VSS

P2

P17

MTIOC3A/

MTIOC3B/

MTIOC4B/

TIOCB0/

SCK1/TXD3/

SMOSI3/SSDA3/

SDA2-DS

SDHI_D3-C/PIXD3

IRQ7

ADTRG1

#

TCLKD/TMO1/

PO15/POE8#

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 47 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (7/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

P3

P87

MTIOC4C/

TIOCA2

SMOSI10/

SSDA10/TXD10

SDHI_D2-C/PIXD2

P4

P14

MTIOC3A/

MTCLKA/

TIOCB5/

TCLKA/TMRI2/

PO15

CTS1#/RTS1#/

SS1#/CTX1/

USB0_OVRCUR

A

LCD_CL

K-A

IRQ4

P5

P6

P7

VCC_USB

VSS_USB

P57

P10

P52

P83

RXD7/SMISO7/

SSCL7/SSLC0-B

LCD_DA

TA3-A

P8

P9

ALE

MTIC5W/

TMRI3

IRQ0

RD#

RXD2/SMISO2/

SSCL2/SSLB3-A

P10

EDACK1

MTIOC4C

ET0_CRS/

LCD_DA

TA8-A

RMII0_CRS_DV/

SCK10/SS10#/

CTS10#

P11

P12

PC6

PC4

D2[A2/D2]/

A22/CS1#

MTIOC3C/

MTCLKA/

TMCI2/PO30/

TIC0

ET0_ETXD3/

RXD8/SMISO8/

SSCL8/

SMISO10/

SSCL10/RXD10/

MOSIA-A

MMC_D6-A

LCD_DA

TA10-A

IRQ13

A20/CS3#

MTIOC3D/

MTCLKC/

TMCI1/PO25/

POE0#

ET0_TX_CLK/

SCK5/CTS8#/

RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-

A

QMI-A/QIO1-A/

SDHI_D1-A/

SDSI_D1-A/

MMC_D1-A

LCD_DA

TA15-A

P13

P14

PC2

P75

A18

MTIOC4B/

TCLKA/PO21

ET0_RX_DV/

RXD5/SMISO5/

SSCL5/SSLA3-A MMC_CD-A

SDHI_D3-A/

SDSI_D3-A/

LCD_DA

TA19-A

CS5#

PO20

ET0_ERXD0/

RMII0_RXD0/

SCK11/RTS11#

SDHI_D2-A/

SDSI_D2-A/

MMC_RES#-A

LCD_DA

TA20-A

P15

R1

VCC

P21

MTIOC1B/

MTIOC4A/

TIOCA3/

RXD0/SMISO0/

SSCL0/SCL1/

USB0_EXICEN

SDHI_CLK-C/

PIXD5

IRQ9

TMCI0/PO1

R2

R3

P20

P16

MTIOC1A/

TIOCB3/

TMRI0/PO0

TXD0/SMOSI0/

SSDA0/SDA1/

USB0_ID

SDHI_CMD-C/

PIXD4

IRQ8

IRQ6

MTIOC3C/

MTIOC3D/

TIOCB1/

TXD1/SMOSI1/

SSDA1/RXD3/

SMISO3/SSCL3/

SCL2-DS/

ADTRG0

#

TCLKC/TMO2/

PO14/RTCOUT USB0_VBUSEN/

USB0_VBUS/

USB0_OVRCUR

B

R4

P13

WR2#/BC2# MTIOC0B/

TXD2/SMOSI2/

LCD_TC

ON0-A

IRQ3

ADTRG1

#

TIOCA5/TMO3/ SSDA2/

PO13

SDA0[FM+]

R5

R6

R7

USB0_DM

USB0_DP

P56

P11

EDACK1

MTIOC3C/

TIOCA1

SCK7/RSPCKC-

B

LCD_DA

TA4-A

R8

MTIC5V/TMCI3 SCK2

LCD_DA

TA7-A

IRQ1

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 48 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.5

List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (8/8)

Memory Interface

Number

Timer

Communication Camera Interface

177-Pin

TFLGA

176-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

R9

P53*²

BCLK

R10

R11

R12

VSS

VCC

P80

P76

EDREQ0

CS6#

MTIOC3B/

PO26

ET0_TX_EN/

RMII0_TXD_EN/ MMC_D2-A

SCK10/RTS10#

QIO2-A/SDHI_WP/ LCD_DA

TA14-A

R13

PO22

ET0_RX_CLK/

REF50CK0/

SMISO11/

QSSL-A/

LCD_DA

TA18-A

SDHI_CMD-A/

SDSI_CMD-A/

MMC_CMD-A

SSCL11/RXD11

R14

R15

P74

PC1

A20/CS4#

A17

PO19

ET0_ERXD1/

RMII0_RXD1/

SS11#/CTS11#

LCD_DA

TA21-A

MTIOC3A/

TCLKD/PO18

ET0_ERXD2/

SCK5/SSLA2-A

LCD_DA

TA22-A

IRQ12

Note 1. The 176-pin LFBGA does not include the E5 pin.

Note 2. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 49 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (1/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

1

2

3

4

5

6

7

AVSS0

AVCC1

AVSS1

P05

IRQ13

IRQ11

DA1

DA0

P03

P02

P01

TMCI1

TMCI0

SCK6

IRQ10

IRQ9

AN120

AN119

RXD6/SMISO6/

SSCL6

8

P00

PF5

TMRI0

TXD6/SMOSI6/

SSDA6

IRQ8

IRQ4

AN118

9

10

11

EMLE

VSS

PJ5

PJ3

POE8#

CTS2#/RTS2#/

SS2#

12

13

EDACK1

MTIOC3C

ET0_EXOUT/

CTS6#/RTS6#/

SS6#/CTS0#/

RTS0#/SS0#

14

15

16

17

18

19

20

21

22

23

24

25

26

27

VCL

VBATT

NC

TRST#

MD/FINED

XCIN

PF4

XCOUT

RES#

XTAL

P37

P36

VSS

EXTAL

VCC

UPSEL

P35

P34

NMI

MTIOC0A/

TMCI3/PO12/

POE10#

ET0_LINKSTA/

SCK6/SCK0

IRQ4

28

29

P33

P32

EDREQ1

MTIOC0D/

TIOCD0/

TMRI3/PO11/

POE4#/

RXD6/SMISO6/

SSCL6/RXD0/

SMISO0/SSCL0/

CRX0

PCKO

IRQ3-DS

IRQ2-DS

POE11#

MTIOC0C/

TIOCC0/

TMO3/PO10/

RTCIC2/

TXD6/SMOSI6/

SSDA6/TXD0/

SMOSI0/SSDA0/

CTX0/

VSYNC

RTCOUT/

POE0#/

USB0_VBUSEN

POE10#

30

31

TMS

TDI

PF3

PF2

RXD1/SMISO1/

SSCL1

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 50 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (2/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

32

P31

MTIOC4D/

TMCI2/PO9/

RTCIC1

CTS1#/RTS1#/

SS1#/SSLB0-A

IRQ1-DS

33

P30

MTIOC4B/

TMRI3/PO8/

RTCIC0/

RXD1/SMISO1/

SSCL1/MISOB-A

IRQ0-DS

POE8#

34

35

TCK

TDO

PF1

PF0

SCK1

TXD1/SMOSI1/

SSDA1

36

37

P27

P26

CS7#

CS6#

MTIOC2B/

TMCI3/PO7

SCK1/RSPCKB-

A

MTIOC2A/

TMO1/PO6

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/SS3#/

MOSIB-A

38

P25

P24

CS5#/

EDACK1

MTIOC4C/

MTCLKB/

TIOCA4/PO5

RXD3/SMISO3/

SSCL3

SDHI_CD/HSYNC

SDHI_WP/PIXCLK

ADTRG0

#

39

40

VCC

VSS

CS4#/

EDREQ1

MTIOC4A/

MTCLKA/

TIOCB4/

SCK3/

USB0_VBUSEN

TMRI1/PO4

41

42

P23

P22

EDACK0

EDREQ0

MTIOC3D/

MTCLKD/

TIOCD3/PO3

TXD3/SMOSI3/

SSDA3/CTS0#/

RTS0#/SS0#

SDHI_D1-C/PIXD7

SDHI_D0-C/PIXD6

43

44

MTIOC3B/

MTCLKC/

TIOCC3/

SCK0/

USB0_OVRCUR

B

TMO0/PO2

P21

MTIOC1B/

MTIOC4A/

TIOCA3/

RXD0/SMISO0/

SSCL0/SCL1/

USB0_EXICEN

SDHI_CLK-C/

PIXD5

IRQ9

TMCI0/PO1

45

46

P20

P17

MTIOC1A/

TIOCB3/

TMRI0/PO0

TXD0/SMOSI0/

SSDA0/SDA1/

USB0_ID

SDHI_CMD-C/

PIXD4

IRQ8

IRQ7

MTIOC3A/

MTIOC3B/

MTIOC4B/

TIOCB0/

SCK1/TXD3/

SMOSI3/SSDA3/

SDA2-DS

SDHI_D3-C/PIXD3

ADTRG1

#

TCLKD/TMO1/

PO15/POE8#

47

48

P87

P16

MTIOC4C/

TIOCA2

SMOSI10/

SSDA10/TXD10

SDHI_D2-C/PIXD2

MTIOC3C/

MTIOC3D/

TIOCB1/

TXD1/SMOSI1/

SSDA1/RXD3/

SMISO3/SSCL3/

SCL2-DS/

IRQ6

ADTRG0

#

TCLKC/TMO2/

PO14/RTCOUT USB0_VBUSEN/

USB0_VBUS/

USB0_OVRCUR

B

49

50

P86

P15

MTIOC4D/

TIOCA0

SMISO10/

SSCL10/RXD10

PIXD1

PIXD0

MTIOC0B/

MTCLKB/

TIOCB2/

RXD1/SMISO1/

SSCL1/SCK3/

CRX1-DS

IRQ5

TCLKB/TMCI2/

PO13

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 51 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (3/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

51

P14

MTIOC3A/

MTCLKA/

TIOCB5/

TCLKA/TMRI2/

PO15

CTS1#/RTS1#/

SS1#/CTX1/

USB0_OVRCUR

A

LCD_CL

K-A

IRQ4

52

53

P13

P12

WR2#/BC2# MTIOC0B/

PO13

TXD2/SMOSI2/

TIOCA5/TMO3/ SSDA2/

LCD_TC

ON0-A

IRQ3

IRQ2

ADTRG1

#

SDA0[FM+]

WR3#/

BC3#

MTIC5U/

TMCI1

RXD2/SMISO2/

SSCL2/

LCD_TC

ON1-A

SCL0[FM+]

54

55

56

57

58

VCC_USB

VSS_USB

USB0_DM

USB0_DP

PJ2

PJ1

PJ0

P85

P84

P57

P56

P55

TXD8/SMOSI8/

SSDA8/SSLC3-B

LCD_TC

ON2-A

59

60

61

62

63

64

65

MTIOC6A

MTIOC6B

RXD8/SMISO8/

SSCL8/SSLC2-B

LCD_TC

ON3-A

SCK8/SSLC1-B

LCD_DA

TA0-A

MTIOC6C/

TIOCC0

LCD_DA

TA1-A

MTIOC6D

LCD_DA

TA2-A

RXD7/SMISO7/

SSCL7/SSLC0-B

LCD_DA

TA3-A

EDACK1

MTIOC3C/

TIOCA1

SCK7/RSPCKC-

B

LCD_DA

TA4-A

D0[A0/D0]/

EDREQ0/

WAIT#

MTIOC4D/

TMO3

ET0_EXOUT/

TXD7/SMOSI7/

SSDA7/MISOC-

B/CRX1

LCD_DA

TA5-A

IRQ10

66

P54

D1[A1/D1]/

EDACK0/

ALE

MTIOC4B/

TMCI1

ET0_LINKSTA/

CTS2#/RTS2#/

SS2#/MOSIC-B/

CTX1

LCD_DA

TA6-A

67

68

P11

P10

MTIC5V/TMCI3 SCK2

LCD_DA

TA7-A

IRQ1

IRQ0

ALE

MTIC5W/

TMRI3

69

70

P53*¹

P52

BCLK

RD#

RXD2/SMISO2/

SSCL2/SSLB3-A

71

P51

P50

WR1#/

BC1#/

WAIT#

SCK2/SSLB2-A

72

73

WR0#/WR#

TXD2/SMOSI2/

SSDA2/SSLB1-A

VSS

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 52 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (4/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

74

P83

EDACK1

MTIOC4C

ET0_CRS/

LCD_DA

TA8-A

RMII0_CRS_DV/

SCK10/SS10#/

CTS10#

75

76

VCC

UB

PC7

PC6

A23/CS0#

MTIOC3A/

MTCLKB/

TMO2/PO31/

TOC0/

ET0_COL/TXD8/ MMC_D7-A

SMOSI8/SSDA8/

SMOSI10/

SSDA10/TXD10/

MISOA-A

LCD_DA

TA9-A

IRQ14

IRQ13

CACREF

77

D2[A2/D2]/

A22/CS1#

MTIOC3C/

MTCLKA/

TMCI2/PO30/

TIC0

ET0_ETXD3/

RXD8/SMISO8/

SSCL8/

MMC_D6-A

LCD_DA

TA10-A

SMISO10/

SSCL10/RXD10/

MOSIA-A

78

79

PC5

P82

D3[A3/D3]/

A21/CS2#/

WAIT#

MTIOC3B/

MTCLKD/

TMRI2/PO29

ET0_ETXD2/

SCK8/SCK10/

RSPCKA-A

MMC_D5-A

MMC_D4-A

LCD_DA

TA11-A

EDREQ1

MTIOC4A/

PO28

ET0_ETXD1/

RMII0_TXD1/

SMOSI10/

LCD_DA

TA12-A

SSDA10/TXD10

80

P81

EDACK0

MTIOC3D/

PO27

ET0_ETXD0/

RMII0_TXD0/

SMISO10/

QIO3-A/SDHI_CD/

MMC_D3-A

LCD_DA

TA13-A

SSCL10/RXD10

81

82

P80

PC4

EDREQ0

MTIOC3B/

PO26

ET0_TX_EN/

RMII0_TXD_EN/ MMC_D2-A

SCK10/RTS10#

QIO2-A/SDHI_WP/ LCD_DA

TA14-A

A20/CS3#

MTIOC3D/

MTCLKC/

TMCI1/PO25/

POE0#

ET0_TX_CLK/

SCK5/CTS8#/

RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-

A

QMI-A/QIO1-A/

SDHI_D1-A/

SDSI_D1-A/

MMC_D1-A

LCD_DA

TA15-A

83

84

85

PC3

P77

P76

A19

MTIOC4D/

TCLKB/PO24

ET0_TX_ER/

TXD5/SMOSI5/

SSDA5

QMO-A/QIO0-A/

SDHI_D0-A/

SDSI_D0-A/

MMC_D0-A

LCD_DA

TA16-A

CS7#

CS6#

PO23

PO22

ET0_RX_ER/

RMII0_RX_ER/

SMOSI11/

QSPCLK-A/

LCD_DA

TA17-A

SDHI_CLK-A/

SDSI_CLK-A/

MMC_CLK-A

SSDA11/TXD11

ET0_RX_CLK/

REF50CK0/

SMISO11/

QSSL-A/

LCD_DA

TA18-A

SDHI_CMD-A/

SDSI_CMD-A/

MMC_CMD-A

SSCL11/RXD11

86

87

88

89

PC2

P75

P74

PC1

A18

MTIOC4B/

TCLKA/PO21

ET0_RX_DV/

RXD5/SMISO5/

SSCL5/SSLA3-A MMC_CD-A

SDHI_D3-A/

SDSI_D3-A/

LCD_DA

TA19-A

CS5#

A20/CS4#

A17

PO20

PO19

ET0_ERXD0/

RMII0_RXD0/

SCK11/RTS11#

SDHI_D2-A/

SDSI_D2-A/

MMC_RES#-A

LCD_DA

TA20-A

ET0_ERXD1/

RMII0_RXD1/

SS11#/CTS11#

LCD_DA

TA21-A

MTIOC3A/

TCLKD/PO18

ET0_ERXD2/

SCK5/SSLA2-A

LCD_DA

TA22-A

IRQ12

IRQ14

90

91

VCC

PC0

A16

MTIOC3C/

TCLKC/PO17

ET0_ERXD3/

CTS5#/RTS5#/

SS5#/SSLA1-A

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 53 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (5/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

92

93

VSS

P73

CS3#

A15

PO16

ET0_WOL

LCD_EX

TCLK-A

94

PB7

MTIOC3B/

TIOCB5/PO31

ET0_CRS/

SDSI_D1-B

SDSI_D0-B

RMII0_CRS_DV/

TXD9/SMOSI9/

SSDA9/

SMOSI11/

SSDA11/TXD11

95

PB6

A14

MTIOC3D/

TIOCA5/PO30

ET0_ETXD1/

RMII0_TXD1/

RXD9/SMISO9/

SSCL9/

SMISO11/

SSCL11/RXD11

96

97

PB5

PB4

PB3

PB2

PB1

A13

A12

A11

A10

A9

MTIOC2A/

MTIOC1B/

TIOCB4/

TMRI1/PO29/

POE4#

ET0_ETXD0/

RMII0_TXD0/

SCK9/SCK11

SDSI_CLK-B

SDSI_CMD-B

SDSI_D3-B

SDSI_D2-B

LCD_CL

K-B

TIOCA4/PO28

ET0_TX_EN/

LCD_TC

ON0-B

RMII0_TXD_EN/

CTS9#/RTS9#/

SS9#/SS11#/

CTS11#/RTS11#

98

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/TMO0/

PO27/POE11#

ET0_RX_ER/

RMII0_RX_ER/

SCK4/SCK6

LCD_TC

ON1-B

99

TIOCC3/

TCLKC/PO26

ET0_RX_CLK/

REF50CK0/

CTS4#/RTS4#/

SS4#/CTS6#/

RTS6#/SS6#

LCD_TC

ON2-B

100

101

MTIOC0C/

MTIOC4C/

TIOCB3/

ET0_ERXD0/

RMII0_RXD0/

TXD4/SMOSI4/

SSDA4/TXD6/

SMOSI6/SSDA6

LCD_TC

ON3-B

IRQ4-DS

TMCI0/PO25

P72

P71

PB0

A19/CS2#

A18/CS1#

A8

ET0_MDC

LCD_DA

TA23-A

102

103

104

ET0_MDIO

VCC

VSS

MTIC5W/

TIOCA3/PO24

ET0_ERXD1/

RMII0_RXD1/

RXD4/SMISO4/

SSCL4/RXD6/

SMISO6/SSCL6

LCD_DA

TA0-B

IRQ12

105

106

PA7

PA6

A7

A6

TIOCB2/PO23

ET0_WOL/

MISOA-B

LCD_DA

TA1-B

107

108

MTIC5V/

MTCLKB/

TIOCA2/

TMCI3/PO22/

POE10#

ET0_EXOUT/

CTS5#/RTS5#/

SS5#/MOSIA-B

LCD_DA

TA2-B

PA5

A5

MTIOC6B/

TIOCB1/PO21

ET0_LINKSTA/

RSPCKA-B

LCD_DA

TA3-B

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 54 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (6/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

109

PA4

A4

MTIC5U/

MTCLKA/

TIOCA1/

ET0_MDC/TXD5/

SMOSI5/SSDA5/

SSLA0-B

LCD_DA

TA4-B

IRQ5-DS

TMRI0/PO20

110

PA3

A3

MTIOC0D/

MTCLKD/

TIOCD0/

ET0_MDIO/

RXD5/SMISO5/

SSCL5

LCD_DA

TA5-B

IRQ6-DS

TCLKB/PO19

111

112

TRDATA3

TRDATA2

PG7

PA2

D31

A2

MTIOC7A/

PO18

RXD5/SMISO5/

SSCL5/SSLA3-B

LCD_DA

TA6-B

113

114

PG6

PA1

D30

DQM3/A1

MTIOC0B/

MTCLKC/

ET0_WOL/

SCK5/SSLA2-B

LCD_DA

TA7-B

IRQ11

MTIOC7B/

TIOCB0/PO17

115

116

117

118

VCC

TRCLK

VSS

PG5

PA0

D29

DQM2/

BC0#/A0

MTIOC4A/

MTIOC6D/

ET0_TX_EN/

RMII0_TXD_EN/

LCD_DA

TA8-B

TIOCA0/PO16/ SSLA1-B

CACREF

119

120

121

122

123

124

125

TRSYNC

TRDATA1

TRDATA0

PG4

P67

PG3

P66

PG2

P65

PE7

D28

DQM1/CS7# MTIOC7C

IRQ15

D27

DQM0/CS6# MTIOC7D

D26

CKE/CS5#

D15[A15/

D15]/D7[A7/ TOC1

D7]

MTIOC6A/

MISOB-B

SDHI_WP/

MMC_RES#-B

LCD_DA

TA9-B

IRQ7

IRQ6

AN105

AN104

126

PE6

D14[A14/

D14]/D6[A6/

D6]

MTIOC6C/TIC1 MOSIB-B

SDHI_CD/

MMC_CD-B

LCD_DA

TA10-B

127

128

129

130

VCC

VSS

P70

PE5

PE4

PE3

PE2

SDCLK

D13[A13/

D13]/D5[A5/ MTIOC2B

D5]

MTIOC4C/

ET0_RX_CLK/

REF50CK0/

RSPCKB-B

LCD_DA

TA11-B

IRQ5

AN103

AN102

AN101

131

132

133

D12[A12/

D12]/D4[A4/ MTIOC1A/

D4]

MTIOC4D/

ET0_ERXD2/

SSLB0-B

LCD_DA

TA12-B

PO28

D11[A11/

D11]/D3[A3/

D3]

MTIOC4B/

PO26/TOC3/

POE8#

ET0_ERXD3/

CTS12#/

RTS12#/SS12#

MMC_D7-B

MMC_D6-B

LCD_DA

TA13-B

D10[A10/

D10]/D2[A2/ PO23/TIC3

D2]

MTIOC4A/

RXD12/

LCD_DA

TA14-B

IRQ7-DS AN100

SMISO12/

SSCL12/

RXDX12/SSLB3-

B

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 55 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (7/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

134

PE1

D9[A9/D9]/

D1[A1/D1]

MTIOC4C/

MTIOC3B/

PO18

TXD12/

MMC_D5-B

LCD_DA

TA15-B

ANEX1

SMOSI12/

SSDA12/

TXDX12/

SIOX12/SSLB2-

B

135

PE0

D8[A8/D8]/

D0[A0/D0]

MTIOC3D

SCK12/SSLB1-B MMC_D4-B

LCD_DA

TA16-B

ANEX0

136

137

P64

P63

WE#/D3[A3/

D3]/CS4#

CAS#/

D2[A2/D2]/

CS3#

138

139

P62

P61

RAS#/

D1[A1/D1]/

CS2#

SDCS#/

D0[A0/D0]/

CS1#

140

141

142

143

VSS

VCC

P60

PD7

CS0#

D7[A7/D7]

MTIC5U/

POE0#

SSLC3-A

SSLC2-A

QMI-B/QIO1-B/

SDHI_D1-B/

MMC_D1-B

LCD_DA

TA17-B

IRQ7

IRQ6

AN107

AN106

144

145

TRDATA7

TRDATA6

PG1

PD6

D25

D6[A6/D6]

MTIC5V/

MTIOC8A/

POE4#

QMO-B/QIO0-B/

SDHI_D0-B/

MMC_D0-B

LCD_DA

TA18-B

146

147

PG0

PD5

D24

D5[A5/D5]

MTIC5W/

MTIOC8C/

POE10#

SSLC1-A

SSLC0-A

QSPCLK-B/

SDHI_CLK-B/

MMC_CLK-B

LCD_DA

TA19-B

IRQ5

IRQ4

AN113

AN112

148

PD4

D4[A4/D4]

MTIOC8B/

POE11#

QSSL-B/

SDHI_CMD-B/

MMC_CMD-B

LCD_DA

TA20-B

149

150

TRSYNC1

P97

PD3

D23/A23

D3[A3/D3]

MTIOC8D/

TOC2/POE8#

RSPCKC-A

QIO3-B/SDHI_D3-

B/MMC_D3-B

LCD_DA

TA21-B

IRQ3

AN111

151

152

153

154

VSS

TRDATA5

VCC

P96

PD2

D22/A22

D2[A2/D2]

MTIOC4D/TIC2 MISOC-A/CRX0

QIO2-B/SDHI_D2-

B/MMC_D2-B

LCD_DA

TA22-B

IRQ2

IRQ1

IRQ0

AN110

AN109

155

156

TRDATA4

P95

PD1

D21/A21

D1[A1/D1]

MTIOC4B/

POE0#

MOSIC-A/CTX0

LCD_DA

TA23-B

157

158

P94

PD0

D20/A20

D0[A0/D0]

POE4#

POE0#

LCD_EX

TCLK-B

AN108

AN117

159

P93

D19/A19

CTS7#/RTS7#/

SS7#

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 56 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFQFP) (8/8)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

176-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

160

P92

D18/A18

POE4#

RXD7/SMISO7/

SSCL7

AN116

161

162

163

P91

P90

D17/A17

SCK7

AN115

VSS

VCC

D16/A16

TXD7/SMOSI7/

SSDA7

AN114

164

165

P47

P46

P45

P44

P43

P42

P41

IRQ15-

DS

AN007

AN006

AN005

AN004

AN003

AN002

166

167

168

169

170

IRQ14-

DS

IRQ13-

DS

IRQ12-

DS

IRQ11-

DS

IRQ10-

DS

171

172

173

174

175

176

IRQ9-DS AN001

VREFL0

P40

IRQ8-DS AN000

VREFH0

AVCC0

P07

IRQ15

ADTRG0

#

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 57 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (1/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

145-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

A1

A2

AVSS0

P07

IRQ15

ADTRG0

#

A3

A4

P40

P42

IRQ8-DS AN000

IRQ10-

DS

AN002

AN005

AN114

AN116

AN110

AN106

A5

A6

A7

A8

A9

P45

P90

P92

PD2

PD6

IRQ13-

DS

A16

TXD7/SMOSI7/

SSDA7

A18

POE4#

RXD7/SMISO7/

SSCL7

D2[A2/D2]

D6[A6/D6]

MTIOC4D/TIC2 MISOC-A/CRX0

QIO2-B/SDHI_D2-

B/MMC_D2-B

LCD_DA

TA22-B*¹

IRQ2

IRQ6

MTIC5V/

MTIOC8A/

POE4#

SSLC2-A

QMO-B/QIO0-B/

SDHI_D0-B/

MMC_D0-B

LCD_DA

TA18-B*¹

A10

A11

VSS

P62

PE1

RAS#/

D1[A1/D1]*¹/

CS2#

A12

D9[A9/D9]/

MTIOC4C/

TXD12/

MMC_D5-B

MMC_D7-B

LCD_DA

TA15-B*¹

ANEX1

AN101

D1[A1/D1]*¹MTIOC3B/

PO18

SMOSI12/

SSDA12/

TXDX12/

SIOX12/SSLB2-

B

A13

PE3

D11[A11/

D11]/D3[A3/

D3]*¹

MTIOC4B/

PO26/TOC3/

POE8#

ET0_ERXD3/

CTS12#/

RTS12#/SS12#

LCD_DA

TA13-B*¹

B1

B2

B3

B4

B5

AVCC1

AVCC0

P05

IRQ13

DA1

VREFL0

P43

P47

IRQ11-

DS

AN003

AN007

B6

IRQ15-

DS

B7

B8

P91

PD0

A17

SCK7

AN115

AN108

D0[A0/D0]

POE4#

LCD_EX

TCLK-B

IRQ0

IRQ4

1

*

B9

PD4

D4[A4/D4]

MTIOC8B/

POE11#

SSLC0-A

QSSL-B/

SDHI_CMD-B/

MMC_CMD-B

LCD_DA

TA20-B*¹

AN112

B10

B11

VCC

P61

PE2

SDCS#/

D0[A0/D0]*¹/

CS1#

B12

D10[A10/

MTIOC4A/

D10]/D2[A2/ PO23/TIC3

RXD12/

MMC_D6-B

LCD_DA

TA14-B*¹

IRQ7-DS AN100

SMISO12/

SSCL12/

RXDX12/SSLB3-

B

D2]*¹

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 58 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (2/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

145-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

B13

PE4

D12[A12/

D12]/D4[A4/ MTIOC1A/

D4]*¹

MTIOC4D/

ET0_ERXD2/

SSLB0-B

LCD_DA

TA12-B*¹

AN102

PO28

C1

C2

C3

C4

C5

AVSS1

P02

TMCI1

SCK6

IRQ10

AN120

VREFH0

P41

P46

IRQ9-DS AN001

IRQ14-

DS

AN006

C6

C7

VSS

PD1

PD3

PD7

D1[A1/D1]

D3[A3/D3]

D7[A7/D7]

MTIOC4B/

POE0#

MOSIC-A/CTX0

RSPCKC-A

SSLC3-A

LCD_DA

TA23-B*¹

IRQ1

IRQ3

IRQ7

AN109

AN111

AN107

C8

C9

MTIOC8D/

TOC2/POE8#

QIO3-B/SDHI_D3-

B/MMC_D3-B

LCD_DA

TA21-B*¹

MTIC5U/

POE0#

QMI-B/QIO1-B/

SDHI_D1-B/

MMC_D1-B

LCD_DA

TA17-B*¹

C10

C11

P63

CAS#/

D2[A2/D2]*¹/

CS3#

PE0

P70

D8[A8/D8]/

D0[A0/D0]*¹

MTIOC3D

TMRI0

SCK12/SSLB1-B MMC_D4-B

LCD_DA

TA16-B*¹

ANEX0

AN118

C12

C13

D1

SDCLK

VSS

P00

TXD6/SMOSI6/

SSDA6

IRQ8

D2

D3

D4

PF5

P03

P01

IRQ4

IRQ11

IRQ9

DA0

TMCI0

POE0#

RXD6/SMISO6/

SSCL6

AN119

D5

D6

VCC

P93

PD5

A19

CTS7#/RTS7#/

SS7#

AN117

AN113

D7

D5[A5/D5]

MTIC5W/

MTIOC8C/

POE10#

SSLC1-A

QSPCLK-B/

SDHI_CLK-B/

MMC_CLK-B

LCD_DA

TA19-B*¹

IRQ5

IRQ7

D8

D9

P60

P64

CS0#

WE#/D3[A3/

D3]*¹/CS4#

D10

PE7

D15[A15/

MTIOC6A/

D15]/D7[A7/ TOC1

MISOB-B

SDHI_WP/

MMC_RES#-B

LCD_DA

TA9-B*¹

AN105

D7]*¹

D11

D12

VCC

PE5

PE6

D13[A13/

D13]/D5[A5/ MTIOC2B

D5]*¹

MTIOC4C/

ET0_RX_CLK/

REF50CK0/

RSPCKB-B

LCD_DA

TA11-B*¹

IRQ5

IRQ6

AN103

AN104

D13

D14[A14/

D14]/D6[A6/

D6]*¹

MTIOC6C/TIC1 MOSIB-B

SDHI_CD/

MMC_CD-B

LCD_DA

TA10-B*¹

E1

E2

E3

VSS

VCL

PJ5

POE8#

CTS2#/RTS2#/

SS2#

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 59 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (3/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

145-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

E4

E5

EMLE

P44

PA0

IRQ12-

DS

AN004

E10

BC0#/A0

MTIOC4A/

MTIOC6D/

ET0_TX_EN/

RMII0_TXD_EN/

LCD_DA

TA8-B*¹

TIOCA0/PO16/ SSLA1-B

CACREF

E11

E12

E13

F1

P66

P65

P67

DQM0/CS6# MTIOC7D

CKE/CS5#

DQM1/CS7# MTIOC7C

IRQ15

XCIN

F2

XCOUT

F3

PJ3

PA3

PA1

EDACK1

MTIOC3C

ET0_EXOUT/

CTS6#/RTS6#/

SS6#/CTS0#/

RTS0#/SS0#

F4

VBATT

VSS

F10

A3

MTIOC0D/

MTCLKD/

TIOCD0/

ET0_MDIO/

RXD5/SMISO5/

SSCL5

LCD_DA

TA5-B*¹

IRQ6-DS

IRQ11

TCLKB/PO19

F11

F12

A1

A2

MTIOC0B/

MTCLKC/

MTIOC7B/

TIOCB0/PO17

ET0_WOL/

SCK5/SSLA2-B

LCD_DA

TA7-B*¹

F13

PA2

P37

MTIOC7A/

PO18

RXD5/SMISO5/

SSCL5/SSLA3-B

LCD_DA

TA6-B*¹

G1

G2

XTAL

RES#

G3

MD/FINED

BSCANP

G4

G10

PA5

PA6

A5

A6

MTIOC6B/

TIOCB1/PO21

ET0_LINKSTA/

RSPCKA-B

LCD_DA

TA3-B*¹

G11

MTIC5V/

MTCLKB/

TIOCA2/

ET0_EXOUT/

CTS5#/RTS5#/

SS5#/MOSIA-B

LCD_DA

TA2-B*¹

TMCI3/PO22/

POE10#

G12

G13

VCC

PA4

P36

A4

MTIC5U/

MTCLKA/

TIOCA1/

ET0_MDC/TXD5/

SMOSI5/SSDA5/

SSLA0-B

LCD_DA

TA4-B*¹

IRQ5-DS

TMRI0/PO20

H1

H2

EXTAL

VCC

H3

VSS

H4

UPSEL

P35

P72

P71

NMI

H10

H11

A19/CS2#

A18/CS1#

ET0_MDC

ET0_MDIO

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 60 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (4/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

145-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

H12

PB0

A8

MTIC5W/

TIOCA3/PO24

ET0_ERXD1/

RMII0_RXD1/

RXD4/SMISO4/

SSCL4/RXD6/

SMISO6/SSCL6

LCD_DA

TA0-B*¹

IRQ12

H13

J1

PA7

P34

A7

TIOCB2/PO23

ET0_WOL/

MISOA-B

LCD_DA

TA1-B*¹

TRST#

MTIOC0A/

TMCI3/PO12/

POE10#

ET0_LINKSTA/

SCK6/SCK0

IRQ4

J2

J3

P33

P32

EDREQ1

MTIOC0D/

TIOCD0/

TMRI3/PO11/

POE4#/

RXD6/SMISO6/

SSCL6/RXD0/

SMISO0/SSCL0/

CRX0

PCKO

IRQ3-DS

POE11#

MTIOC0C/

TIOCC0/

TMO3/PO10/

RTCIC2/

RTCOUT/

POE0#/

TXD6/SMOSI6/

SSDA6/TXD0/

SMOSI0/SSDA0/

CTX0/

VSYNC

IRQ2-DS

IRQ0-DS

USB0_VBUSEN

POE10#

J4

TDI

P30

PB3

MTIOC4B/

TMRI3/PO8/

RTCIC0/

RXD1/SMISO1/

SSCL1/MISOB-A

POE8#

J10

A11

A12

A10

A9

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/TMO0/

PO27/POE11#

ET0_RX_ER/

RMII0_RX_ER/

SCK4/SCK6

SDSI_D3-B

SDSI_CMD-B

SDSI_D2-B

LCD_TC

ON1-B*¹

J11

J12

J13

PB4

PB2

PB1

TIOCA4/PO28

ET0_TX_EN/

LCD_TC

ON0-B*¹

RMII0_TXD_EN/

CTS9#/RTS9#/

SS9#/SS11#/

CTS11#/RTS11#

TIOCC3/

TCLKC/PO26

ET0_RX_CLK/

REF50CK0/

CTS4#/RTS4#/

SS4#/CTS6#/

RTS6#/SS6#

LCD_TC

ON2-B*¹

MTIOC0C/

MTIOC4C/

TIOCB3/

ET0_ERXD0/

RMII0_RXD0/

TXD4/SMOSI4/

SSDA4/TXD6/

SMOSI6/SSDA6

LCD_TC

ON3-B*¹

IRQ4-DS

TMCI0/PO25

K1

K2

TCK

TDO

P27

P26

CS7#

CS6#

MTIOC2B/

TMCI3/PO7

SCK1/RSPCKB-

A

MTIOC2A/

TMO1/PO6

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/SS3#/

MOSIB-A

K3

K4

TMS

P31

P15

MTIOC4D/

TMCI2/PO9/

RTCIC1

CTS1#/RTS1#/

SS1#/SSLB0-A

IRQ1-DS

IRQ5

MTIOC0B/

MTCLKB/

TIOCB2/

RXD1/SMISO1/

SSCL1/SCK3/

CRX1-DS

PIXD0

TCLKB/TMCI2/

PO13

K5

K6

TRDATA2

P54

ALE/

MTIOC4B/

ET0_LINKSTA/

CTS2#/RTS2#/

SS2#/CTX1

D1[A1/D1]*¹/ TMCI1

EDACK0

P53*²

BCLK

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 61 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (5/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

145-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

K7

P51

WR1#/

BC1#/

WAIT#

SCK2/SSLB2-A

K8

K9

VCC

TRDATA0

P80

P76

EDREQ0

CS6#

MTIOC3B/

PO26

ET0_TX_EN/

RMII0_TXD_EN/ MMC_D2-A

SCK10/RTS10#

QIO2-A/SDHI_WP/

K10

K11

TRDATA6

PO22

ET0_RX_CLK/

REF50CK0/

SMISO11/

QSSL-A/

SDHI_CMD-A/

SDSI_CMD-A/

MMC_CMD-A

SSCL11/RXD11

PB7

PB6

PB5

A15

A14

A13

MTIOC3B/

TIOCB5/PO31

ET0_CRS/

SDSI_D1-B

SDSI_D0-B

SDSI_CLK-B

RMII0_CRS_DV/

TXD9/SMOSI9/

SSDA9/

SMOSI11/

SSDA11/TXD11

K12

K13

MTIOC3D/

TIOCA5/PO30

ET0_ETXD1/

RMII0_TXD1/

RXD9/SMISO9/

SSCL9/

SMISO11/

SSCL11/RXD11

MTIOC2A/

MTIOC1B/

TIOCB4/

ET0_ETXD0/

RMII0_TXD0/

SCK9/SCK11

LCD_CL

K-B*¹

TMRI1/PO29/

POE4#

L1

L2

L3

P25

P23

P16

CS5#/

EDACK1

MTIOC4C/

MTCLKB/

TIOCA4/PO5

RXD3/SMISO3/

SSCL3

SDHI_CD*¹/

HSYNC

ADTRG0

#

EDACK0

MTIOC3D/

MTCLKD/

TIOCD3/PO3

TXD3/SMOSI3/

SSDA3/CTS0#/

RTS0#/SS0#

SDHI_D1-C*¹/

PIXD7

MTIOC3C/

MTIOC3D/

TIOCB1/

TXD1/SMOSI1/

SSDA1/RXD3/

SMISO3/SSCL3/

SCL2-DS/

IRQ6

ADTRG0

#

TCLKC/TMO2/

PO14/RTCOUT USB0_VBUSEN/

USB0_VBUS/

USB0_OVRCUR

B

L4

L5

P24

P13

CS4#/

EDREQ1

MTIOC4A/

MTCLKA/

TIOCB4/

SCK3/

USB0_VBUSEN

SDHI_WP*¹/

PIXCLK

TMRI1/PO4

MTIOC0B/

TIOCA5/TMO3/ SSDA2/

TXD2/SMOSI2/

IRQ3

ADTRG1

#

PO13

SDA0[FM+]

L6

L7

L8

P56

P52

P83

EDACK1

RD#

MTIOC3C/

TIOCA1

SCK7*¹

RXD2/SMISO2/

SSCL2/SSLB3-A

TRCLK

EDACK1

MTIOC4C

ET0_CRS/

RMII0_CRS_DV/

SCK10/SS10#/

CTS10#

L9

PC5

PC4

D3[A3/D3]*¹/ MTIOC3B/

ET0_ETXD2/

SCK8/SCK10/

RSPCKA-A

MMC_D5-A

A21/CS2#/

WAIT#

MTCLKD/

TMRI2/PO29

L10

A20/CS3#

MTIOC3D/

MTCLKC/

TMCI1/PO25/

POE0#

ET0_TX_CLK/

SCK5/CTS8#/

RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-

A

QMI-A/QIO1-A/

SDHI_D1-A/

SDSI_D1-A/

MMC_D1-A

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 62 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (6/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

145-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

L11

PC2

A18

MTIOC4B/

TCLKA/PO21

ET0_RX_DV/

RXD5/SMISO5/

SDHI_D3-A/

SDSI_D3-A/

SSCL5/SSLA3-A MMC_CD-A

L12

L13

M1

TRDATA4

VSS

P73

P22

CS3#

PO16

ET0_WOL

EDREQ0

MTIOC3B/

MTCLKC/

TIOCC3/

SCK0/

SDHI_D0-C*¹/

USB0_OVRCUR PIXD6

B

TMO0/PO2

M2

P17

MTIOC3A/

MTIOC3B/

MTIOC4B/

TIOCB0/

SCK1/TXD3/

SMOSI3/SSDA3/ PIXD3

SDA2-DS

SDHI_D3-C*¹/

IRQ7

ADTRG1

#

TCLKD/TMO1/

PO15/POE8#

M3

M4

P86

P12

MTIOC4D/

TIOCA0

SMISO10/

SSCL10/RXD10

PIXD1

TMCI1

RXD2/SMISO2/

SSCL2/

IRQ2

SCL0[FM+]

M5

M6

M7

VCC_USB

VSS_USB

P50

PC6

WR0#/WR#

TXD2/SMOSI2/

SSDA2/SSLB1-A

M8

D2[A2/D2]*¹/ MTIOC3C/

A22/CS1#

ET0_ETXD3/

RXD8/SMISO8/

SSCL8/

MMC_D6-A

IRQ13

MTCLKA/

TMCI2/PO30/

TIC0

SMISO10/

SSCL10/RXD10/

MOSIA-A

M9

TRDATA1

TRDATA7

P81

P77

EDACK0

CS7#

MTIOC3D/

PO27

ET0_ETXD0/

RMII0_TXD0/

SMISO10/

QIO3-A/SDHI_CD/

MMC_D3-A

SSCL10/RXD10

M10

PO23

ET0_RX_ER/

RMII0_RX_ER/

SMOSI11/

QSPCLK-A/

SDHI_CLK-A/

SDSI_CLK-A/

MMC_CLK-A

SSDA11/TXD11

M11

M12

PC0

PC1

A16

A17

MTIOC3C/

TCLKC/PO17

ET0_ERXD3/

CTS5#/RTS5#/

SS5#/SSLA1-A

IRQ14

IRQ12

MTIOC3A/

ET0_ERXD2/

TCLKD/PO18

SCK5/SSLA2-A

M13

N1

VCC

P21

P20

MTIOC1B/

MTIOC4A/

TIOCA3/

RXD0/SMISO0/

SSCL0/SCL1*¹/

USB0_EXICEN

SDHI_CLK-C*¹/

PIXD5

IRQ9

IRQ8

TMCI0/PO1

N2

MTIOC1A/

TIOCB3/

TMRI0/PO0

TXD0/SMOSI0/

SSDA0/SDA1*¹/

USB0_ID

SDHI_CMD-C*¹/

PIXD4

N3

N4

P87

P14

MTIOC4C/

TIOCA2

SMOSI10/

SSDA10/TXD10

SDHI_D2-C*¹/

PIXD2

MTIOC3A/

MTCLKA/

TIOCB5/

TCLKA/TMRI2/

PO15

CTS1#/RTS1#/

SS1#/CTX1/

USB0_OVRCUR

A

IRQ4

N5

N6

USB0_DM

USB0_DP

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 63 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.7

List of Pin and Pin Functions (145-Pin TFLGA) (7/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

145-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

N7

TRDATA3

P55

D0[A0/D0]*¹/ MTIOC4D/

ET0_EXOUT/

TXD7*¹/

IRQ10

WAIT#/

TMO3

EDREQ0

SMOSI7*¹/

SSDA7*¹/CRX1

N8

N9

VSS

UB

PC7

A23/CS0#

MTIOC3A/

MTCLKB/

TMO2/PO31/

TOC0/

ET0_COL/TXD8/ MMC_D7-A

SMOSI8/SSDA8/

SMOSI10/

SSDA10/TXD10/

MISOA-A

IRQ14

CACREF

N10

N11

TRSYNC

P82

PC3

EDREQ1

A19

MTIOC4A/

PO28

ET0_ETXD1/

RMII0_TXD1/

SMOSI10/

MMC_D4-A

SSDA10/TXD10

MTIOC4D/

TCLKB/PO24

ET0_TX_ER/

TXD5/SMOSI5/

SSDA5

QMO-A/QIO0-A/

SDHI_D0-A/

SDSI_D0-A/

MMC_D0-A

N12

N13

TRSYNC1

TRDATA5

P75

P74

CS5#

PO20

PO19

ET0_ERXD0/

RMII0_RXD0/

SCK11/RTS11#

SDHI_D2-A/

SDSI_D2-A/

MMC_RES#-A

A20/CS4#

ET0_ERXD1/

RMII0_RXD1/

SS11#/CTS11#

Note 1. These pins are only enabled for products with 2 or 1.5 Mbytes of code flash memory.

Note 2. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 64 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.8

List of Pin and Pin Functions (144-Pin LFQFP) (1/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

144-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

1

2

3

4

5

6

7

AVSS0

AVCC1

AVSS1

P05

IRQ13

IRQ11

DA1

DA0

P03

P02

P01

TMCI1

TMCI0

SCK6

IRQ10

IRQ9

AN120

AN119

RXD6/SMISO6/

SSCL6

8

P00

PF5

TMRI0

TXD6/SMOSI6/

SSDA6

IRQ8

IRQ4

AN118

9

10

11

EMLE

VSS

PJ5

PJ3

POE8#

CTS2#/RTS2#/

SS2#

12

13

EDACK1

MTIOC3C

ET0_EXOUT/

CTS6#/RTS6#/

SS6#/CTS0#/

RTS0#/SS0#

14

15

16

17

18

19

20

21

22

23

24

25

VCL

VBATT

MD/FINED

XCIN

XCOUT

RES#

XTAL

P37

P36

VSS

EXTAL

VCC

UPSEL

TRST#

P35

P34

NMI

MTIOC0A/

TMCI3/PO12/

POE10#

ET0_LINKSTA/

SCK6/SCK0

IRQ4

26

27

P33

P32

EDREQ1

MTIOC0D/

TIOCD0/

TMRI3/PO11/

POE4#/

RXD6/SMISO6/

SSCL6/RXD0/

SMISO0/SSCL0/

CRX0

PCKO

IRQ3-DS

IRQ2-DS

POE11#

MTIOC0C/

TIOCC0/

TMO3/PO10/

RTCIC2/

TXD6/SMOSI6/

SSDA6/TXD0/

SMOSI0/SSDA0/

CTX0/

VSYNC

RTCOUT/

POE0#/

USB0_VBUSEN

POE10#

28

29

TMS

TDI

P31

P30

MTIOC4D/

TMCI2/PO9/

RTCIC1

CTS1#/RTS1#/

SS1#/SSLB0-A

IRQ1-DS

IRQ0-DS

MTIOC4B/

TMRI3/PO8/

RTCIC0/

RXD1/SMISO1/

SSCL1/MISOB-A

POE8#

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 65 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.8

List of Pin and Pin Functions (144-Pin LFQFP) (2/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

144-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

30

TCK

P27

CS7#

MTIOC2B/

TMCI3/PO7

SCK1/RSPCKB-

A

31

TDO

P26

CS6#

MTIOC2A/

TMO1/PO6

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/SS3#/

MOSIB-A

32

33

P25

P24

CS5#/

EDACK1

MTIOC4C/

MTCLKB/

TIOCA4/PO5

RXD3/SMISO3/

SSCL3

SDHI_CD*¹/

HSYNC

ADTRG0

#

CS4#/

EDREQ1

MTIOC4A/

MTCLKA/

TIOCB4/

SCK3/

USB0_VBUSEN

SDHI_WP*¹/

PIXCLK

TMRI1/PO4

34

35

P23

P22

EDACK0

EDREQ0

MTIOC3D/

MTCLKD/

TIOCD3/PO3

TXD3/SMOSI3/

SSDA3/CTS0#/

RTS0#/SS0#

SDHI_D1-C*¹/

PIXD7

MTIOC3B/

MTCLKC/

TIOCC3/

SCK0/

SDHI_D0-C*¹/

USB0_OVRCUR PIXD6

B

TMO0/PO2

36

P21

MTIOC1B/

MTIOC4A/

TIOCA3/

RXD0/SMISO0/

SSCL0/SCL1*¹/

USB0_EXICEN

SDHI_CLK-C*¹/

PIXD5

IRQ9

TMCI0/PO1

37

38

P20

P17

MTIOC1A/

TIOCB3/

TMRI0/PO0

TXD0/SMOSI0/

SSDA0/SDA1*¹/

USB0_ID

SDHI_CMD-C*¹/

PIXD4

IRQ8

IRQ7

MTIOC3A/

MTIOC3B/

MTIOC4B/

TIOCB0/

SCK1/TXD3/

SMOSI3/SSDA3/ PIXD3

SDA2-DS

SDHI_D3-C*¹/

ADTRG1

#

TCLKD/TMO1/

PO15/POE8#

39

40

P87

P16

MTIOC4C/

TIOCA2

SMOSI10/

SSDA10/TXD10

SDHI_D2-C*¹/

PIXD2

MTIOC3C/

MTIOC3D/

TIOCB1/

TXD1/SMOSI1/

SSDA1/RXD3/

SMISO3/SSCL3/

SCL2-DS/

IRQ6

ADTRG0

#

TCLKC/TMO2/

PO14/RTCOUT USB0_VBUSEN/

USB0_VBUS/

USB0_OVRCUR

B

41

42

P86

P15

MTIOC4D/

TIOCA0

SMISO10/

SSCL10/RXD10

PIXD1

PIXD0

MTIOC0B/

MTCLKB/

TIOCB2/

TCLKB/TMCI2/

PO13

RXD1/SMISO1/

SSCL1/SCK3/

CRX1-DS

IRQ5

IRQ4

43

P14

MTIOC3A/

MTCLKA/

TIOCB5/

TCLKA/TMRI2/

PO15

CTS1#/RTS1#/

SS1#/CTX1/

USB0_OVRCUR

A

44

45

P13

P12

MTIOC0B/

TIOCA5/TMO3/ SSDA2/

PO13

TXD2/SMOSI2/

IRQ3

IRQ2

ADTRG1

#

SDA0[FM+]

TMCI1

RXD2/SMISO2/

SSCL2/

SCL0[FM+]

46

47

48

VCC_USB

USB0_DM

USB0_DP

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 66 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.8

List of Pin and Pin Functions (144-Pin LFQFP) (3/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

144-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

49

50

VSS_USB

TRDATA3

TRDATA2

P56

P55

EDACK1

MTIOC3C/

TIOCA1

SCK7*¹

51

D0[A0/D0]*¹/ MTIOC4D/

WAIT#/

EDREQ0

ET0_EXOUT/

TXD7*¹/

IRQ10

TMO3

SMOSI7*¹/

SSDA7*¹/CRX1

52

P54

ALE/D1[A1/

D1]*¹/

EDACK0

MTIOC4B/

TMCI1

ET0_LINKSTA/

CTS2#/RTS2#/

SS2#/CTX1

53

54

P53*²

P52

BCLK

RD#

RXD2/SMISO2/

SSCL2/SSLB3-A

55

56

P51

P50

WR1#/

BC1#/

WAIT#

SCK2/SSLB2-A

WR0#/WR#

TXD2/SMOSI2/

SSDA2/SSLB1-A

57

58

VSS

TRCLK

P83

EDACK1

MTIOC4C

ET0_CRS/

RMII0_CRS_DV/

SCK10/SS10#/

CTS10#

59

60

VCC

UB

PC7

PC6

A23/CS0#

MTIOC3A/

MTCLKB/

TMO2/PO31/

TOC0/

ET0_COL/TXD8/ MMC_D7-A

SMOSI8/SSDA8/

SMOSI10/

SSDA10/TXD10/

MISOA-A

IRQ14

IRQ13

CACREF

61

D2[A2/D2]*¹/ MTIOC3C/

A22/CS1#

ET0_ETXD3/

RXD8/SMISO8/

SSCL8/

MMC_D6-A

MTCLKA/

TMCI2/PO30/

TIC0

SMISO10/

SSCL10/RXD10/

MOSIA-A

62

63

PC5

P82

D3[A3/D3]*¹/ MTIOC3B/

ET0_ETXD2/

SCK8/SCK10/

RSPCKA-A

MMC_D5-A

MMC_D4-A

A21/CS2#/

WAIT#

MTCLKD/

TMRI2/PO29

TRSYNC

TRDATA1

TRDATA0

EDREQ1

MTIOC4A/

PO28

ET0_ETXD1/

RMII0_TXD1/

SMOSI10/

SSDA10/TXD10

64

P81

EDACK0

MTIOC3D/

PO27

ET0_ETXD0/

RMII0_TXD0/

SMISO10/

QIO3-A/SDHI_CD/

MMC_D3-A

SSCL10/RXD10

65

66

P80

PC4

EDREQ0

MTIOC3B/

PO26

ET0_TX_EN/

RMII0_TXD_EN/ MMC_D2-A

SCK10/RTS10#

QIO2-A/SDHI_WP/

A20/CS3#

MTIOC3D/

MTCLKC/

TMCI1/PO25/

POE0#

ET0_TX_CLK/

SCK5/CTS8#/

RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-

A

QMI-A/QIO1-A/

SDHI_D1-A/

SDSI_D1-A/

MMC_D1-A

67

68

PC3

P77

A19

MTIOC4D/

TCLKB/PO24

ET0_TX_ER/

TXD5/SMOSI5/

SSDA5

QMO-A/QIO0-A/

SDHI_D0-A/

SDSI_D0-A/

MMC_D0-A

TRDATA7

CS7#

PO23

ET0_RX_ER/

RMII0_RX_ER/

SMOSI11/

QSPCLK-A/

SDHI_CLK-A/

SDSI_CLK-A/

MMC_CLK-A

SSDA11/TXD11

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 67 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.8

List of Pin and Pin Functions (144-Pin LFQFP) (4/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

144-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

69

TRDATA6

P76

CS6#

PO22

ET0_RX_CLK/

REF50CK0/

SMISO11/

QSSL-A/

SDHI_CMD-A/

SDSI_CMD-A/

MMC_CMD-A

SSCL11/RXD11

70

71

72

73

PC2

P75

P74

PC1

A18

MTIOC4B/

TCLKA/PO21

ET0_RX_DV/

RXD5/SMISO5/

SSCL5/SSLA3-A MMC_CD-A

SDHI_D3-A/

SDSI_D3-A/

TRSYNC1

TRDATA5

CS5#

A20/CS4#

A17

PO20

PO19

ET0_ERXD0/

RMII0_RXD0/

SCK11/RTS11#

SDHI_D2-A/

SDSI_D2-A/

MMC_RES#-A

ET0_ERXD1/

RMII0_RXD1/

SS11#/CTS11#

MTIOC3A/

TCLKD/PO18

ET0_ERXD2/

SCK5/SSLA2-A

IRQ12

IRQ14

74

75

VCC

PC0

A16

MTIOC3C/

TCLKC/PO17

ET0_ERXD3/

CTS5#/RTS5#/

SS5#/SSLA1-A

76

77

78

VSS

TRDATA4

P73

PB7

CS3#

A15

PO16

ET0_WOL

MTIOC3B/

TIOCB5/PO31

ET0_CRS/

SDSI_D1-B

SDSI_D0-B

RMII0_CRS_DV/

TXD9/SMOSI9/

SSDA9/

SMOSI11/

SSDA11/TXD11

79

PB6

A14

MTIOC3D/

TIOCA5/PO30

ET0_ETXD1/

RMII0_TXD1/

RXD9/SMISO9/

SSCL9/

SMISO11/

SSCL11/RXD11

80

81

82

83

84

PB5

PB4

PB3

PB2

PB1

A13

A12

A11

A10

A9

MTIOC2A/

MTIOC1B/

TIOCB4/

TMRI1/PO29/

POE4#

ET0_ETXD0/

RMII0_TXD0/

SCK9/SCK11

SDSI_CLK-B

SDSI_CMD-B

SDSI_D3-B

SDSI_D2-B

LCD_CL

K-B*¹

TIOCA4/PO28

ET0_TX_EN/

LCD_TC

ON0-B*¹

RMII0_TXD_EN/

CTS9#/RTS9#/

SS9#/SS11#/

CTS11#/RTS11#

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/TMO0/

PO27/POE11#

ET0_RX_ER/

RMII0_RX_ER/

SCK4/SCK6

LCD_TC

ON1-B*¹

TIOCC3/

TCLKC/PO26

ET0_RX_CLK/

REF50CK0/

CTS4#/RTS4#/

SS4#/CTS6#/

RTS6#/SS6#

LCD_TC

ON2-B*¹

MTIOC0C/

MTIOC4C/

TIOCB3/

ET0_ERXD0/

RMII0_RXD0/

TXD4/SMOSI4/

SSDA4/TXD6/

SMOSI6/SSDA6

LCD_TC

ON3-B*¹

IRQ4-DS

TMCI0/PO25

85

86

P72

P71

A19/CS2#

A18/CS1#

ET0_MDC

ET0_MDIO

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 68 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.8

List of Pin and Pin Functions (144-Pin LFQFP) (5/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

144-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

87

PB0

A8

MTIC5W/

TIOCA3/PO24

ET0_ERXD1/

RMII0_RXD1/

RXD4/SMISO4/

SSCL4/RXD6/

SMISO6/SSCL6

LCD_DA

TA0-B*¹

IRQ12

88

89

PA7

PA6

A7

A6

TIOCB2/PO23

ET0_WOL/

MISOA-B

LCD_DA

TA1-B*¹

MTIC5V/

MTCLKB/

TIOCA2/

ET0_EXOUT/

CTS5#/RTS5#/

SS5#/MOSIA-B

LCD_DA

TA2-B*¹

TMCI3/PO22/

POE10#

90

PA5

PA4

A5

A4

MTIOC6B/

TIOCB1/PO21

ET0_LINKSTA/

RSPCKA-B

LCD_DA

TA3-B*¹

91

92

VCC

VSS

MTIC5U/

MTCLKA/

TIOCA1/

ET0_MDC/TXD5/

SMOSI5/SSDA5/

SSLA0-B

LCD_DA

TA4-B*¹

IRQ5-DS

IRQ6-DS

TMRI0/PO20

93

94

PA3

A3

MTIOC0D/

MTCLKD/

TIOCD0/

ET0_MDIO/

RXD5/SMISO5/

SSCL5

LCD_DA

TA5-B*¹

TCLKB/PO19

95

96

PA2

PA1

A2

A1

MTIOC7A/

PO18

RXD5/SMISO5/

SSCL5/SSLA3-B

LCD_DA

TA6-B*¹

MTIOC0B/

MTCLKC/

ET0_WOL/

SCK5/SSLA2-B

LCD_DA

TA7-B*¹

IRQ11

MTIOC7B/

TIOCB0/PO17

97

PA0

BC0#/A0

MTIOC4A/

MTIOC6D/

ET0_TX_EN/

RMII0_TXD_EN/

LCD_DA

TA8-B*¹

TIOCA0/PO16/ SSLA1-B

CACREF

98

99

P67

P66

P65

PE7

DQM1/CS7# MTIOC7C

DQM0/CS6# MTIOC7D

CKE/CS5#

IRQ15

100

101

D15[A15/

MTIOC6A/

MISOB-B

SDHI_WP/

MMC_RES#-B

LCD_DA

TA9-B*¹

IRQ7

IRQ6

AN105

AN104

D15]/D7[A7/ TOC1

D7]*¹

102

PE6

D14[A14/

D14]/D6[A6/

D6]*¹

MTIOC6C/TIC1 MOSIB-B

SDHI_CD/

MMC_CD-B

LCD_DA

TA10-B*¹

103

104

105

106

VCC

VSS

P70

PE5

PE4

PE3

PE2

SDCLK

D13[A13/

D13]/D5[A5/ MTIOC2B

D5]*¹

MTIOC4C/

ET0_RX_CLK/

REF50CK0/

RSPCKB-B

LCD_DA

TA11-B*¹

IRQ5

AN103

AN102

AN101

107

108

109

D12[A12/

D12]/D4[A4/ MTIOC1A/

D4]*¹

MTIOC4D/

ET0_ERXD2/

SSLB0-B

LCD_DA

TA12-B*¹

PO28

D11[A11/

D11]/D3[A3/

D3]*¹

MTIOC4B/

PO26/TOC3/

POE8#

ET0_ERXD3/

CTS12#/

RTS12#/SS12#

MMC_D7-B

MMC_D6-B

LCD_DA

TA13-B*¹

D10[A10/

D10]/D2[A2/ PO23/TIC3

D2]*¹

MTIOC4A/

RXD12/

LCD_DA

TA14-B*¹

IRQ7-DS AN100

SMISO12/

SSCL12/

RXDX12/SSLB3-

B

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 69 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.8

List of Pin and Pin Functions (144-Pin LFQFP) (6/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

144-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

110

PE1

D9[A9/D9]/

MTIOC4C/

TXD12/

MMC_D5-B

LCD_DA

TA15-B*¹

ANEX1

D1[A1/D1]*¹MTIOC3B/

PO18

SMOSI12/

SSDA12/

TXDX12/

SIOX12/SSLB2-

B

111

112

113

PE0

P64

P63

D8[A8/D8]/

MTIOC3D

SCK12/SSLB1-B MMC_D4-B

LCD_DA

TA16-B*¹

ANEX0

D0[A0/D0]*¹

WE#/D3[A3/

D3]*¹/CS4#

CAS#/

D2[A2/D2]*¹/

CS3#

114

115

P62

P61

RAS#/

D1[A1/D1]*¹/

CS2#

SDCS#/

D0[A0/D0]*¹/

CS1#

116

117

118

119

VSS

VCC

P60

PD7

PD6

PD5

PD4

CS0#

D7[A7/D7]

D6[A6/D6]

D5[A5/D5]

D4[A4/D4]

MTIC5U/

POE0#

SSLC3-A

SSLC2-A

SSLC1-A

SSLC0-A

RSPCKC-A

QMI-B/QIO1-B/

SDHI_D1-B/

MMC_D1-B

LCD_DA

TA17-B*¹

IRQ7

IRQ6

IRQ5

IRQ4

AN107

AN106

AN113

AN112

120

121

122

MTIC5V/

MTIOC8A/

POE4#

QMO-B/QIO0-B/

SDHI_D0-B/

MMC_D0-B

LCD_DA

TA18-B*¹

MTIC5W/

MTIOC8C/

POE10#

QSPCLK-B/

SDHI_CLK-B/

MMC_CLK-B

LCD_DA

TA19-B*¹

MTIOC8B/

POE11#

QSSL-B/

SDHI_CMD-B/

MMC_CMD-B

LCD_DA

TA20-B*¹

123

124

125

126

PD3

PD2

PD1

PD0

D3[A3/D3]

D2[A2/D2]

D1[A1/D1]

D0[A0/D0]

MTIOC8D/

TOC2/POE8#

QIO3-B/SDHI_D3-

B/MMC_D3-B

LCD_DA

TA21-B*¹

IRQ3

IRQ2

IRQ1

IRQ0

AN111

AN110

AN109

AN108

MTIOC4D/TIC2 MISOC-A/CRX0

QIO2-B/SDHI_D2-

B/MMC_D2-B

LCD_DA

TA22-B*¹

MTIOC4B/

POE0#

MOSIC-A/CTX0

LCD_DA

TA23-B*¹

POE4#

LCD_EX

TCLK-B

1

*

127

128

P93

P92

P91

A19

A18

A17

POE0#

POE4#

CTS7#/RTS7#/

SS7#

AN117

AN116

AN115

RXD7/SMISO7/

SSCL7

129

130

131

SCK7

VSS

VCC

P90

A16

TXD7/SMOSI7/

SSDA7

AN114

132

133

P47

P46

P45

IRQ15-

DS

AN007

AN006

AN005

134

135

IRQ14-

DS

IRQ13-

DS

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 70 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.8

List of Pin and Pin Functions (144-Pin LFQFP) (7/7)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

144-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF, PDC)

A/D

I/O Port

GLCDC

Interrupt D/A

136

137

138

P44

IRQ12-

DS

AN004

AN003

AN002

P43

P42

P41

IRQ11-

DS

IRQ10-

DS

139

140

141

142

143

144

IRQ9-DS AN001

VREFL0

P40

IRQ8-DS AN000

VREFH0

AVCC0

P07

IRQ15

ADTRG0

#

Note 1. These pins are only enabled for products with 2 or 1.5 Mbytes of code flash memory.

Note 2. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 71 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.9

List of Pin and Pin Functions (100-Pin TFLGA) (1/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

A1

A2

A3

P05

IRQ13

DA1

AVCC1

P07

IRQ15

ADTRG0

#

A4

A5

VREFL0

P43

PD0

IRQ11-

DS

AN003

AN108

A6

A7

D0[A0/D0]

D4[A4/D4]

POE4#

LCD_EX

TCLK-B

IRQ0

1

*

PD4

MTIOC8B/

POE11#

SSLC0-A

QSSL-B/

SDHI_CMD-B/

MMC_CMD-B

LCD_DA

TA20-B*¹

IRQ4

AN112

A8

A9

PE0

PE1

D8[A8/D8]/

MTIOC3D

SCK12/SSLB1-B MMC_D4-B

LCD_DA

TA16-B*¹

ANEX0

ANEX1

D0[A0/D0]*¹

D9[A9/D9]/

D1[A1/D1]*¹MTIOC3B/

PO18

MTIOC4C/

TXD12/

MMC_D5-B

MMC_D6-B

LCD_DA

TA15-B*¹

SMOSI12/

SSDA12/

TXDX12/

SIOX12/SSLB2-

B

A10

PE2

D10[A10/

D10]/D2[A2/ PO23/TIC3

D2]*¹

MTIOC4A/

RXD12/

LCD_DA

TA14-B*¹

IRQ7-DS AN100

SMISO12/

SSCL12/

RXDX12/SSLB3-

B

B1

B2

B3

B4

B5

EMLE

AVSS0

AVCC0

P40

P44

IRQ8-DS AN000

IRQ12-

DS

AN004

AN109

AN111

AN106

B6

B7

B8

PD1

PD3

PD6

D1[A1/D1]

D3[A3/D3]

D6[A6/D6]

MTIOC4B/

POE0#

MOSIC-A/CTX0

RSPCKC-A

SSLC2-A

LCD_DA

TA23-B*¹

IRQ1

IRQ3

IRQ6

MTIOC8D/

TOC2/POE8#

QIO3-B/SDHI_D3-

B/MMC_D3-B

LCD_DA

TA21-B*¹

MTIC5V/

MTIOC8A/

POE4#

QMO-B/QIO0-B/

SDHI_D0-B/

MMC_D0-B

LCD_DA

TA18-B*¹

B9

PD7

PE3

D7[A7/D7]

MTIC5U/

POE0#

SSLC3-A

QMI-B/QIO1-B/

SDHI_D1-B/

MMC_D1-B

LCD_DA

TA17-B*¹

IRQ7

AN107

AN101

B10

D11[A11/

D11]/D3[A3/

D3]*¹

MTIOC4B/

PO26/TOC3/

POE8#

ET0_ERXD3/

CTS12#/

RTS12#/SS12#

MMC_D7-B

LCD_DA

TA13-B*¹

C1

C2

C3

VCL

AVSS1

PJ3

EDACK1

MTIOC3C

ET0_EXOUT/

CTS6#/RTS6#/

SS6#/CTS0#/

RTS0#/SS0#

C4

C5

VREFH0

P42

P47

IRQ10-

DS

AN002

AN007

C6

IRQ15-

DS

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 72 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.9

List of Pin and Pin Functions (100-Pin TFLGA) (2/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

C7

PD2

D2[A2/D2]

MTIOC4D/TIC2 MISOC-A/CRX0

QIO2-B/SDHI_D2-

B/MMC_D2-B

LCD_DA

TA22-B*¹

IRQ2

AN110

C8

PD5

PE5

PE4

D5[A5/D5]

MTIC5W/

MTIOC8C/

POE10#

SSLC1-A

QSPCLK-B/

SDHI_CLK-B/

MMC_CLK-B

LCD_DA

TA19-B*¹

IRQ5

AN113

C9

D13[A13/

D13]/D5[A5/ MTIOC2B

D5]*¹

MTIOC4C/

ET0_RX_CLK/

REF50CK0/

RSPCKB-B

LCD_DA

TA11-B*¹

IRQ5

AN103

AN102

C10

D12[A12/

D12]/D4[A4/ MTIOC1A/

D4]*¹

MTIOC4D/

ET0_ERXD2/

SSLB0-B

LCD_DA

TA12-B*¹

PO28

D1

D2

D3

D4

D5

XCIN

XCOUT

MD/FINED

VBATT

P45

P46

PE6

IRQ13-

DS

AN005

AN006

AN104

D6

D7

IRQ14-

DS

D14[A14/

D14]/D6[A6/

D6]*¹

MTIOC6C/TIC1 MOSIB-B

SDHI_CD/

MMC_CD-B

LCD_DA

TA10-B*¹

IRQ6

IRQ7

IRQ11

D8

D9

PE7

PA1

D15[A15/

D15]/D7[A7/ TOC1

D7]*¹

MTIOC6A/

MISOB-B

SDHI_WP/

MMC_RES#-B

LCD_DA

TA9-B*¹

AN105

A1

MTIOC0B/

ET0_WOL/

LCD_DA

TA7-B*¹

MTCLKC/

SCK5/SSLA2-B

MTIOC7B/

TIOCB0/PO17

D10

PA0

P37

BC0#/A0

MTIOC4A/

MTIOC6D/

TIOCA0/PO16/ SSLA1-B

CACREF

ET0_TX_EN/

RMII0_TXD_EN/

LCD_DA

TA8-B*¹

E1

E2

E3

E4

XTAL

VSS

RES#

TRST#

P34

MTIOC0A/

TMCI3/PO12/

POE10#

ET0_LINKSTA/

SCK6/SCK0

IRQ4

E5

E6

P41

PA2

IRQ9-DS AN001

A2

A6

MTIOC7A/

PO18

RXD5/SMISO5/

SSCL5/SSLA3-B

LCD_DA

TA6-B*¹

E7

PA6

MTIC5V/

MTCLKB/

TIOCA2/

ET0_EXOUT/

CTS5#/RTS5#/

SS5#/MOSIA-B

LCD_DA

TA2-B*¹

TMCI3/PO22/

POE10#

E8

PA4

A4

MTIC5U/

MTCLKA/

TIOCA1/

ET0_MDC/TXD5/

SMOSI5/SSDA5/

SSLA0-B

LCD_DA

TA4-B*¹

IRQ5-DS

IRQ6-DS

TMRI0/PO20

E9

PA5

PA3

A5

A3

MTIOC6B/

TIOCB1/PO21

ET0_LINKSTA/

RSPCKA-B

LCD_DA

TA3-B*¹

E10

MTIOC0D/

MTCLKD/

TIOCD0/

ET0_MDIO/

RXD5/SMISO5/

SSCL5

LCD_DA

TA5-B*¹

TCLKB/PO19

F1

EXTAL

P36

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 73 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.9

List of Pin and Pin Functions (100-Pin TFLGA) (3/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

F2

F3

F4

VCC

UPSEL

P35

P32

NMI

MTIOC0C/

TIOCC0/

TMO3/PO10/

RTCIC2/

TXD6/SMOSI6/

SSDA6/TXD0/

SMOSI0/SSDA0/

CTX0/

IRQ2-DS

RTCOUT/

POE0#/

USB0_VBUSEN

POE10#

F5

F6

P12

PB3

TMCI1

RXD2/SMISO2/

SSCL2/

SCL0[FM+]

IRQ2

A11

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/TMO0/

PO27/POE11#

ET0_RX_ER/

RMII0_RX_ER/

SCK6

SDSI_D3-B

SDSI_D2-B

LCD_TC

ON1-B*¹

F7

F8

F9

PB2

PB0

PA7

P33

A10

TIOCC3/

TCLKC/PO26

ET0_RX_CLK/

REF50CK0/

CTS6#/RTS6#/

SS6#

LCD_TC

ON2-B*¹

A8

MTIC5W/

TIOCA3/PO24

ET0_ERXD1/

RMII0_RXD1/

RXD6/SMISO6/

SSCL6

LCD_DA

TA0-B*¹

IRQ12

A7

TIOCB2/PO23

ET0_WOL/

MISOA-B

LCD_DA

TA1-B*¹

F10

G1

VSS

EDREQ1

MTIOC0D/

TIOCD0/

TMRI3/PO11/

POE4#/

RXD6/SMISO6/

SSCL6/RXD0/

SMISO0/SSCL0/

CRX0

IRQ3-DS

POE11#

G2

G3

TMS

TDI

P31

P30

MTIOC4D/

TMCI2/PO9/

RTCIC1

CTS1#/RTS1#/

SS1#/SSLB0-A

IRQ1-DS

IRQ0-DS

MTIOC4B/

TMRI3/PO8/

RTCIC0/

RXD1/SMISO1/

SSCL1/MISOB-A

POE8#

G4

TCK

P27

CS7#

MTIOC2B/

TMCI3/PO7

SCK1/RSPCKB-

A

G5

G6

P53*²

P52

BCLK

RD#

RXD2/SMISO2/

SSCL2/SSLB3-A

G7

PB5

PB4

PB1

A13

A12

A9

MTIOC2A/

MTIOC1B/

TIOCB4/

TMRI1/PO29/

POE4#

ET0_ETXD0/

RMII0_TXD0/

SCK9/SCK11

SDSI_CLK-B

SDSI_CMD-B

LCD_CL

K-B*¹

G8

TIOCA4/PO28

ET0_TX_EN/

LCD_TC

ON0-B*¹

RMII0_TXD_EN/

CTS9#/RTS9#/

SS9#/SS11#/

CTS11#/RTS11#

G9

MTIOC0C/

MTIOC4C/

TIOCB3/

ET0_ERXD0/

RMII0_RXD0/

TXD6/SMOSI6/

SSDA6

LCD_TC

ON3-B*¹

IRQ4-DS

TMCI0/PO25

G10

VCC

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 74 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.9

List of Pin and Pin Functions (100-Pin TFLGA) (4/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

H1

TDO

P26

CS6#

MTIOC2A/

TMO1/PO6

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/SS3#/

MOSIB-A

H2

H3

P25

P16

CS5#/

EDACK1

MTIOC4C/

MTCLKB/

TIOCA4/PO5

RXD3/SMISO3/

SSCL3

ADTRG0

#

MTIOC3C/

MTIOC3D/

TIOCB1/

TXD1/SMOSI1/

SSDA1/RXD3/

SMISO3/SSCL3/

SCL2-DS/

IRQ6

ADTRG0

#

TCLKC/TMO2/

PO14/RTCOUT USB0_VBUSEN/

USB0_VBUS/

USB0_OVRCUR

B

H4

P15

MTIOC0B/

MTCLKB/

TIOCB2/

RXD1/SMISO1/

SSCL1/SCK3/

CRX1-DS

IRQ5

TCLKB/TMCI2/

PO13

H5

H6

H7

P55

P54

PC7

D0[A0/D0]*¹/ MTIOC4D/

ET0_EXOUT/

CRX1

IRQ10

WAIT#/

TMO3

EDREQ0

ALE/D1[A1/

D1]*¹/

MTIOC4B/

TMCI1

ET0_LINKSTA/

CTS2#/RTS2#/

SS2#/CTX1

EDACK0

UB

A23/CS0#

MTIOC3A/

MTCLKB/

TMO2/PO31/

TOC0/

ET0_COL/TXD8/

SMOSI8/SSDA8/

SMOSI10/

SSDA10/TXD10/

MISOA-A

IRQ14

IRQ13

CACREF

H8

H9

PC6

PB6

PB7

D2[A2/D2]*¹/ MTIOC3C/

ET0_ETXD3/

RXD8/SMISO8/

SSCL8/

SMISO10/

SSCL10/RXD10/

MOSIA-A

A22/CS1#

MTCLKA/

TMCI2/PO30/

TIC0

A14

MTIOC3D/

ET0_ETXD1/

RMII0_TXD1/

RXD9/SMISO9/

SSCL9/

SMISO11/

SSCL11/RXD11

SDSI_D0-B

SDSI_D1-B

TIOCA5/PO30

H10

A15

MTIOC3B/

ET0_CRS/

TIOCB5/PO31

RMII0_CRS_DV/

TXD9/SMOSI9/

SSDA9/

SMOSI11/

SSDA11/TXD11

J1

J2

J3

P24

P21

P17

CS4#/

EDREQ1

MTIOC4A/

MTCLKA/

TIOCB4/

SCK3/

USB0_VBUSEN

TMRI1/PO4

MTIOC1B/

MTIOC4A/

TIOCA3/

RXD0/SMISO0/

SSCL0/SCL1*¹/

USB0_EXICEN

IRQ9

IRQ7

TMCI0/PO1

MTIOC3A/

MTIOC3B/

MTIOC4B/

TIOCB0/

SCK1/TXD3/

SMOSI3/SSDA3/

SDA2-DS

ADTRG1

#

TCLKD/TMO1/

PO15/POE8#

J4

J5

P13

MTIOC0B/

TIOCA5/TMO3/ SSDA2/

PO13 SDA0[FM+]

TXD2/SMOSI2/

IRQ3

ADTRG1

#

VSS_USB

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 75 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.9

List of Pin and Pin Functions (100-Pin TFLGA) (5/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

TFLGA

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

J6

J7

VCC_USB

P50

PC4

WR0#/WR#

A20/CS3#

TXD2/SMOSI2/

SSDA2/SSLB1-A

J8

MTIOC3D/

MTCLKC/

TMCI1/PO25/

POE0#

ET0_TX_CLK/

SCK5/CTS8#/

RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-

A

J9

PC0

A16

MTIOC3C/

TCLKC/PO17

ET0_ERXD3/

CTS5#/RTS5#/

SS5#/SSLA1-A

IRQ14

IRQ12

J10

K1

PC1

P23

A17

MTIOC3A/

TCLKD/PO18

ET0_ERXD2/

SCK5/SSLA2-A

EDACK0

MTIOC3D/

MTCLKD/

TIOCD3/PO3

TXD3/SMOSI3/

SSDA3/CTS0#/

RTS0#/SS0#

K2

P22

EDREQ0

MTIOC3B/

MTCLKC/

TIOCC3/

SCK0/

USB0_OVRCUR

B

TMO0/PO2

K3

K4

P20

P14

MTIOC1A/

TIOCB3/

TMRI0/PO0

TXD0/SMOSI0/

SSDA0/SDA1*¹/

USB0_ID

IRQ8

IRQ4

MTIOC3A/

MTCLKA/

TIOCB5/

TCLKA/TMRI2/

PO15

CTS1#/RTS1#/

SS1#/CTX1/

USB0_OVRCUR

A

K5

K6

K7

USB0_DM

USB0_DP

P51

PC5

PC3

PC2

WR1#/

BC1#/

WAIT#

SCK2/SSLB2-A

K8

K9

D3[A3/D3]*¹/ MTIOC3B/

A21/CS2#/

WAIT#

ET0_ETXD2/

SCK8/SCK10/

RSPCKA-A

MTCLKD/

TMRI2/PO29

A19

A18

MTIOC4D/

TCLKB/PO24

ET0_TX_ER/

TXD5/SMOSI5/

SSDA5

K10

MTIOC4B/

ET0_RX_DV/

TCLKA/PO21

RXD5/SMISO5/

SSCL5/SSLA3-A

Note 1. These pins are only enabled for products with 2 or 1.5 Mbytes of code flash memory.

Note 2. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 76 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.10

List of Pin and Pin Functions (100-Pin LFQFP) (1/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

1

2

3

4

AVCC1

EMLE

AVSS1

PJ3

EDACK1

MTIOC3C

ET0_EXOUT/

CTS6#/RTS6#/

SS6#/CTS0#/

RTS0#/SS0#

5

6

VCL

VBATT

MD/FINED

XCIN

7

8

9

XCOUT

RES#

XTAL

10

11

12

13

14

15

16

P37

P36

VSS

EXTAL

VCC

UPSEL

TRST#

P35

P34

NMI

MTIOC0A/

TMCI3/PO12/

POE10#

ET0_LINKSTA/

SCK6/SCK0

IRQ4

17

18

P33

P32

EDREQ1

MTIOC0D/

TIOCD0/

TMRI3/PO11/

POE4#/

RXD6/SMISO6/

SSCL6/RXD0/

SMISO0/SSCL0/

CRX0

IRQ3-DS

IRQ2-DS

POE11#

MTIOC0C/

TIOCC0/

TMO3/PO10/

RTCIC2/

TXD6/SMOSI6/

SSDA6/TXD0/

SMOSI0/SSDA0/

CTX0/

RTCOUT/

POE0#/

USB0_VBUSEN

POE10#

19

20

TMS

TDI

P31

P30

MTIOC4D/

TMCI2/PO9/

RTCIC1

CTS1#/RTS1#/

SS1#/SSLB0-A

IRQ1-DS

IRQ0-DS

MTIOC4B/

TMRI3/PO8/

RTCIC0/

RXD1/SMISO1/

SSCL1/MISOB-A

POE8#

21

22

TCK

TDO

P27

P26

CS7#

CS6#

MTIOC2B/

TMCI3/PO7

SCK1/RSPCKB-

A

MTIOC2A/

TMO1/PO6

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/SS3#/

MOSIB-A

23

24

P25

P24

CS5#/

EDACK1

MTIOC4C/

MTCLKB/

TIOCA4/PO5

RXD3/SMISO3/

SSCL3

ADTRG0

#

CS4#/

EDREQ1

MTIOC4A/

MTCLKA/

TIOCB4/

SCK3/

USB0_VBUSEN

TMRI1/PO4

25

P23

EDACK0

MTIOC3D/

MTCLKD/

TIOCD3/PO3

TXD3/SMOSI3/

SSDA3/CTS0#/

RTS0#/SS0#

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 77 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.10

List of Pin and Pin Functions (100-Pin LFQFP) (2/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

26

P22

EDREQ0

MTIOC3B/

MTCLKC/

TIOCC3/

SCK0/

USB0_OVRCUR

B

TMO0/PO2

27

P21

MTIOC1B/

MTIOC4A/

TIOCA3/

RXD0/SMISO0/

SSCL0/SCL1*¹/

USB0_EXICEN

IRQ9

TMCI0/PO1

28

29

P20

P17

MTIOC1A/

TIOCB3/

TMRI0/PO0

TXD0/SMOSI0/

SSDA0/SDA1*¹/

USB0_ID

IRQ8

IRQ7

MTIOC3A/

MTIOC3B/

MTIOC4B/

TIOCB0/

SCK1/TXD3/

SMOSI3/SSDA3/

SDA2-DS

ADTRG1

#

TCLKD/TMO1/

PO15/POE8#

30

P16

MTIOC3C/

MTIOC3D/

TIOCB1/

TXD1/SMOSI1/

SSDA1/RXD3/

SMISO3/SSCL3/

SCL2-DS/

IRQ6

ADTRG0

#

TCLKC/TMO2/

PO14/RTCOUT USB0_VBUSEN/

USB0_VBUS/

USB0_OVRCUR

B

31

32

P15

P14

MTIOC0B/

MTCLKB/

TIOCB2/

TCLKB/TMCI2/

PO13

RXD1/SMISO1/

SSCL1/SCK3/

CRX1-DS

IRQ5

IRQ4

MTIOC3A/

MTCLKA/

TIOCB5/

TCLKA/TMRI2/

PO15

CTS1#/RTS1#/

SS1#/CTX1/

USB0_OVRCUR

A

33

34

P13

P12

MTIOC0B/

TIOCA5/TMO3/ SSDA2/

PO13

TXD2/SMOSI2/

IRQ3

IRQ2

ADTRG1

#

SDA0[FM+]

TMCI1

RXD2/SMISO2/

SSCL2/

SCL0[FM+]

35

36

37

38

39

VCC_USB

VSS_USB

USB0_DM

USB0_DP

P55

P54

D0[A0/D0]*¹/ MTIOC4D/

ET0_EXOUT/

CRX1

IRQ10

WAIT#/

TMO3

EDREQ0

40

ALE/D1[A1/

D1]*¹/

MTIOC4B/

TMCI1

ET0_LINKSTA/

CTS2#/RTS2#/

SS2#/CTX1

EDACK0

41

42

P53*²

P52

BCLK

RD#

RXD2/SMISO2/

SSCL2/SSLB3-A

43

44

P51

P50

WR1#/

BC1#/

WAIT#

SCK2/SSLB2-A

WR0#/WR#

TXD2/SMOSI2/

SSDA2/SSLB1-A

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 78 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.10

List of Pin and Pin Functions (100-Pin LFQFP) (3/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

45

UB

PC7

A23/CS0#

MTIOC3A/

MTCLKB/

TMO2/PO31/

TOC0/

ET0_COL/TXD8/

SMOSI8/SSDA8/

SMOSI10/

SSDA10/TXD10/

MISOA-A

IRQ14

CACREF

46

PC6

D2[A2/D2]*¹/ MTIOC3C/

ET0_ETXD3/

RXD8/SMISO8/

SSCL8/

IRQ13

A22/CS1#

MTCLKA/

TMCI2/PO30/

TIC0

SMISO10/

SSCL10/RXD10/

MOSIA-A

47

48

PC5

PC4

D3[A3/D3]*¹/ MTIOC3B/

ET0_ETXD2/

SCK8/SCK10/

RSPCKA-A

A21/CS2#/

WAIT#

MTCLKD/

TMRI2/PO29

A20/CS3#

MTIOC3D/

MTCLKC/

TMCI1/PO25/

POE0#

ET0_TX_CLK/

SCK5/CTS8#/

RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-

A

49

50

PC3

PC2

A19

A18

MTIOC4D/

TCLKB/PO24

ET0_TX_ER/

TXD5/SMOSI5/

SSDA5

MTIOC4B/

ET0_RX_DV/

TCLKA/PO21

RXD5/SMISO5/

SSCL5/SSLA3-A

51

52

PC1

PC0

A17

A16

MTIOC3A/

TCLKD/PO18

ET0_ERXD2/

SCK5/SSLA2-A

IRQ12

IRQ14

MTIOC3C/

TCLKC/PO17

ET0_ERXD3/

CTS5#/RTS5#/

SS5#/SSLA1-A

53

PB7

A15

MTIOC3B/

TIOCB5/PO31

ET0_CRS/

SDSI_D1-B

SDSI_D0-B

RMII0_CRS_DV/

TXD9/SMOSI9/

SSDA9/

SMOSI11/

SSDA11/TXD11

54

PB6

A14

MTIOC3D/

TIOCA5/PO30

ET0_ETXD1/

RMII0_TXD1/

RXD9/SMISO9/

SSCL9/

SMISO11/

SSCL11/RXD11

55

56

57

PB5

PB4

PB3

A13

A12

A11

MTIOC2A/

MTIOC1B/

TIOCB4/

TMRI1/PO29/

POE4#

ET0_ETXD0/

RMII0_TXD0/

SCK9/SCK11

SDSI_CLK-B

SDSI_CMD-B

SDSI_D3-B

SDSI_D2-B

LCD_CL

K-B*¹

TIOCA4/PO28

ET0_TX_EN/

LCD_TC

ON0-B*¹

RMII0_TXD_EN/

CTS9#/RTS9#/

SS9#/SS11#/

CTS11#/RTS11#

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/TMO0/

PO27/POE11#

ET0_RX_ER/

RMII0_RX_ER/

SCK6

LCD_TC

ON1-B*¹

58

59

PB2

PB1

A10

A9

TIOCC3/

TCLKC/PO26

ET0_RX_CLK/

REF50CK0/

CTS6#/RTS6#/

SS6#

LCD_TC

ON2-B*¹

MTIOC0C/

MTIOC4C/

TIOCB3/

ET0_ERXD0/

RMII0_RXD0/

TXD6/SMOSI6/

SSDA6

LCD_TC

ON3-B*¹

IRQ4-DS

TMCI0/PO25

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 79 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.10

List of Pin and Pin Functions (100-Pin LFQFP) (4/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

60

61

VCC

PB0

A8

MTIC5W/

TIOCA3/PO24

ET0_ERXD1/

RMII0_RXD1/

RXD6/SMISO6/

SSCL6

LCD_DA

TA0-B*¹

IRQ12

62

63

VSS

PA7

PA6

A7

A6

TIOCB2/PO23

ET0_WOL/

MISOA-B

LCD_DA

TA1-B*¹

64

MTIC5V/

MTCLKB/

TIOCA2/

ET0_EXOUT/

CTS5#/RTS5#/

SS5#/MOSIA-B

LCD_DA

TA2-B*¹

TMCI3/PO22/

POE10#

65

66

PA5

PA4

A5

A4

MTIOC6B/

TIOCB1/PO21

ET0_LINKSTA/

RSPCKA-B

LCD_DA

TA3-B*¹

MTIC5U/

MTCLKA/

TIOCA1/

ET0_MDC/TXD5/

SMOSI5/SSDA5/

SSLA0-B

LCD_DA

TA4-B*¹

IRQ5-DS

IRQ6-DS

TMRI0/PO20

67

PA3

A3

MTIOC0D/

MTCLKD/

TIOCD0/

ET0_MDIO/

RXD5/SMISO5/

SSCL5

LCD_DA

TA5-B*¹

TCLKB/PO19

68

69

PA2

PA1

A2

A1

MTIOC7A/

PO18

RXD5/SMISO5/

SSCL5/SSLA3-B

LCD_DA

TA6-B*¹

MTIOC0B/

MTCLKC/

ET0_WOL/

SCK5/SSLA2-B

LCD_DA

TA7-B*¹

IRQ11

MTIOC7B/

TIOCB0/PO17

70

PA0

BC0#/A0

D15[A15/

MTIOC4A/

MTIOC6D/

TIOCA0/PO16/ SSLA1-B

CACREF

ET0_TX_EN/

RMII0_TXD_EN/

LCD_DA

TA8-B*¹

71

72

73

74

75

76

PE7

PE6

PE5

PE4

PE3

PE2

MTIOC6A/

MISOB-B

SDHI_WP/

MMC_RES#-B

LCD_DA

TA9-B*¹

IRQ7

IRQ6

IRQ5

AN105

AN104

AN103

AN102

AN101

D15]/D7[A7/ TOC1

D7]*¹

D14[A14/

D14]/D6[A6/

D6]*¹

MTIOC6C/TIC1 MOSIB-B

SDHI_CD/

MMC_CD-B

LCD_DA

TA10-B*¹

D13[A13/

D13]/D5[A5/ MTIOC2B

D5]*¹

MTIOC4C/

ET0_RX_CLK/

REF50CK0/

RSPCKB-B

LCD_DA

TA11-B*¹

D12[A12/

D12]/D4[A4/ MTIOC1A/

D4]*¹

MTIOC4D/

ET0_ERXD2/

SSLB0-B

LCD_DA

TA12-B*¹

PO28

D11[A11/

D11]/D3[A3/

D3]*¹

MTIOC4B/

PO26/TOC3/

POE8#

ET0_ERXD3/

CTS12#/

RTS12#/SS12#

MMC_D7-B

MMC_D6-B

LCD_DA

TA13-B*¹

D10[A10/

D10]/D2[A2/ PO23/TIC3

D2]*¹

MTIOC4A/

RXD12/

LCD_DA

TA14-B*¹

IRQ7-DS AN100

SMISO12/

SSCL12/

RXDX12/SSLB3-

B

77

78

PE1

PE0

D9[A9/D9]/

MTIOC4C/

TXD12/

MMC_D5-B

LCD_DA

TA15-B*¹

ANEX1

D1[A1/D1]*¹MTIOC3B/

PO18

SMOSI12/

SSDA12/

TXDX12/

SIOX12/SSLB2-

B

D8[A8/D8]/

D0[A0/D0]*¹

MTIOC3D

SCK12/SSLB1-B MMC_D4-B

LCD_DA

TA16-B*¹

ANEX0

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 80 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.10

List of Pin and Pin Functions (100-Pin LFQFP) (5/5)

Memory Interface

Number

Timer

Communication Camera Interface

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

Power Supply

Clock System

Control

Bus

EXDMAC

SDRAMC

(ETHERC, SCI,

RSPI, RIIC,

CAN, USB)

100-Pin

LFQFP

(QSPI, SDHI, SDSI,

MMCIF)

A/D

I/O Port

GLCDC

Interrupt D/A

79

80

81

82

PD7

D7[A7/D7]

D6[A6/D6]

D5[A5/D5]

D4[A4/D4]

MTIC5U/

POE0#

SSLC3-A

SSLC2-A

SSLC1-A

SSLC0-A

RSPCKC-A

QMI-B/QIO1-B/

SDHI_D1-B/

MMC_D1-B

LCD_DA

TA17-B*¹

IRQ7

IRQ6

IRQ5

IRQ4

AN107

AN106

AN113

AN112

PD6

PD5

PD4

MTIC5V/

MTIOC8A/

POE4#

QMO-B/QIO0-B/

SDHI_D0-B/

MMC_D0-B

LCD_DA

TA18-B*¹

MTIC5W/

MTIOC8C/

POE10#

QSPCLK-B/

SDHI_CLK-B/

MMC_CLK-B

LCD_DA

TA19-B*¹

MTIOC8B/

POE11#

QSSL-B/

SDHI_CMD-B/

MMC_CMD-B

LCD_DA

TA20-B*¹

83

84

85

86

PD3

PD2

PD1

PD0

D3[A3/D3]

D2[A2/D2]

D1[A1/D1]

D0[A0/D0]

MTIOC8D/

TOC2/POE8#

QIO3-B/SDHI_D3-

B/MMC_D3-B

LCD_DA

TA21-B*¹

IRQ3

IRQ2

IRQ1

IRQ0

AN111

AN110

AN109

AN108

MTIOC4D/TIC2 MISOC-A/CRX0

QIO2-B/SDHI_D2-

B/MMC_D2-B

LCD_DA

TA22-B*¹

MTIOC4B/

POE0#

MOSIC-A/CTX0

LCD_DA

TA23-B*¹

POE4#

LCD_EX

TCLK-B

1

*

87

88

89

90

91

92

P47

P46

P45

P44

P43

P42

P41

IRQ15-

DS

AN007

AN006

AN005

AN004

AN003

AN002

IRQ14-

DS

IRQ13-

DS

IRQ12-

DS

IRQ11-

DS

IRQ10-

DS

93

94

95

96

97

98

IRQ9-DS AN001

VREFL0

P40

IRQ8-DS AN000

VREFH0

AVCC0

P07

P05

IRQ15

IRQ13

ADTRG0

#

99

AVSS0

100

DA1

Note 1. These pins are only enabled for products with 2 or 1.5 Mbytes of code flash memory.

Note 2. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 81 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.11

List of Pin and Pin Functions (64-Pin TFBGA) (1/2)

Number

Timer

Communication

Memory Interface

(QSPI, SDHI)

Power Supply

Clock System

Control

(MTU, TPU, TMR,

RTC, CMTW, POE,

CAC)

64-Pin

TFBGA

(SCI, RSPI, RIIC,

USB)

A/D

D/A

I/O Port

Interrupt

A1

A2

A3

A4

A5

A6

AVCC1

AVSS0

VREFH0

VREFL0

PD2

PD7

MTIOC4D/TIC2

MTIC5U/POE0#

QIO2-B/SDHI_D2-B

IRQ2

IRQ7

AN110

AN107

QMI-B/QIO1-B/

SDHI_D1-B

A7

A8

PE0

PE2

MTIOC3D

SCK12

ANEX0

MTIOC4A/TIC3

RXD12/SSCL12/

RXDX12

IRQ7-DS

B1

B2

B3

B4

B5

EMLE

AVSS1

AVCC0

P42

PD3

IRQ10-DS

IRQ3

AN002

AN111

MTIOC8D/TOC2/

POE8#

QIO3-B/SDHI_D3-B

B6

B7

PD6

PE1

PE6

MTIC5V/MTIOC8A/

POE4#

QMO-B/QIO0-B/

SDHI_D0-B

IRQ6

AN106

ANEX1

MTIOC4C/MTIOC3B

TXD12/SSDA12/

TXDX12/SIOX12

B8

C1

C2

C3

C4

C5

MTIOC6C/TIC1

SDHI_CD

IRQ6

VCL

VBATT

MD/FINED

P41

PD4

IRQ9-DS

AN001

AN112

MTIOC8B/POE11#

QSSL-B/SDHI_CMD- IRQ4

B

C6

C7

PD5

PA1

PE7

MTIC5W/MTIOC8C/

POE10#

QSPCLK-B/

SDHI_CLK-B

IRQ5

IRQ11

IRQ7

AN113

MTIOC0B/MTCLKC/

MTIOC7B/TIOCB0

SCK5

C8

D1

D2

D3

D4

D5

D6

MTIOC6A/TOC1

SDHI_WP

XCIN

XCOUT

RES#

P40

P43

PA6

IRQ8-DS

AN000

AN003

IRQ11-DS

MTIC5V/MTCLKB/

TIOCA2/TMCI3/

POE10#

CTS5#/RTS5#/SS5#

D7

D8

PA2

PA4

P37

MTIOC7A

RXD5/SMISO5/

SSCL5

MTIC5U/MTCLKA/

TIOCA1/TMRI0

TXD5/SMOSI5/

SSDA5

IRQ5-DS

E1

E2

E3

XTAL

VSS

TRST#

P34

P13

MTIOC0A/TMCI3/

POE10#

IRQ4

IRQ3

E4

E5

MTIOC0B/TIOCA5/

TMO3

TXD2/SSDA2/

SDA0[FM+]

ADTRG1#

BSCANP

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 82 of 246

RX65N Group, RX651 Group

1. Overview

Table 1.11

List of Pin and Pin Functions (64-Pin TFBGA) (2/2)

Number

Timer

Communication

Memory Interface

(QSPI, SDHI)

Power Supply

Clock System

Control

(MTU, TPU, TMR,

RTC, CMTW, POE,

CAC)

64-Pin

TFBGA

(SCI, RSPI, RIIC,

USB)

A/D

D/A

I/O Port

Interrupt

E6

E7

E8

F1

F2

F3

F4

PA7

TIOCB2

VCC

VSS

EXTAL

VCC

P36

UPSEL

P35

P12

NMI

TMCI1

RXD2/SSCL2/

SCL0[FM+]

IRQ2

F5

F6

P53

PB7

MTIOC3B/TIOCB5

MTIOC3D/TIOCA5

TXD9/SSDA9/

SSDA11/TXD11

F7

F8

PB6

PB5

RXD9/SSCL9/

SSCL11/RXD11

MTIOC2A/MTIOC1B/ SCK9/SCK11

TIOCB4/TMRI1/

POE4#

G1

G2

TCK

TMS

P27

P31

MTIOC2B/TMCI3

SCK1/RSPCKB-A

MTIOC4D/TMCI2/

RTCIC1

CTS1#/RTS1#/SS1#/

SSLB0-A

IRQ1-DS

IRQ0-DS

G3

TDI

P30

MTIOC4B/TMRI3/

RTCIC0/POE8#

RXD1/SMISO1/

SSCL1/MISOB-A

G4

G5

G6

VCC_USB

VSS_USB

UB

PC7

PC5

MTIOC3A/MTCLKB/

TMO2/TOC0/

CACREF

TXD8/SMOSI8/

SSDA8/SMOSI10/

SSDA10/TXD10/

MISOA-A

IRQ14

G7

MTIOC3B/MTCLKD/

TMRI2

SCK8/SCK10/

RSPCKA-A

G8

H1

PC0

P26

MTIOC3C/TCLKC

MTIOC2A/TMO1

SSLA1-A

TDO

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/MOSIB-A

H2

H3

P17

P16

MTIOC3A/MTIOC3B/

MTIOC4B/TIOCB0/

TCLKD/TMO1/

POE8#

SCK1/TXD3/SSDA3/

SDA2-DS

IRQ7

IRQ6

ADTRG1#

ADTRG0#

MTIOC3C/MTIOC3D/ TXD1/SMOSI1/

TIOCB1/TCLKC/

TMO2/RTCOUT

SSDA1/RXD3/

SSCL3/SCL2-DS/

USB0_VBUS

H4

H5

H6

USB0_DM

USB0_DP

PC6

MTIOC3C/MTCLKA/

TMCI2/TIC0

RXD8/SMISO8/

SSCL8/SMISO10/

SSCL10/RXD10/

MOSIA-A

IRQ13

IRQ12

H7

H8

PC4

PC1

MTIOC3D/MTCLKC/

TMCI1/POE0#

CTS8#/RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-A

MTIOC3A/TCLKD

SSLA2-A

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RX65N Group, RX651 Group

1. Overview

Table 1.12

List of Pin and Pin Functions (64-Pin LFQFP) (1/2)

Number

Timer

Communication

Memory Interface

(QSPI, SDHI)

Power Supply

Clock System

Control

(MTU, TPU, TMR,

RTC, CMTW, POE,

CAC)

64-Pin

LFQFP

(SCI, RSPI, RIIC,

USB)

A/D

D/A

I/O Port

Interrupt

1

2

AVCC1

EMLE

AVSS1

VCL

3

4

5

VBATT

MD/FINED

XCIN

6

7

8

XCOUT

RES#

9

10

11

12

13

14

15

XTAL

P37

P36

VSS

EXTAL

VCC

UPSEL

TRST#

P35

P34

NMI

MTIOC0A/TMCI3/

POE10#

IRQ4

16

17

18

TDI

P30

P31

P26

MTIOC4B/TMRI3/

RTCIC0/POE8#

RXD1/SMISO1/

SSCL1/MISOB-A

IRQ0-DS

IRQ1-DS

TMS

TDO

MTIOC4D/TMCI2/

RTCIC1

CTS1#/RTS1#/SS1#/

SSLB0-A

MTIOC2A/TMO1

TXD1/SMOSI1/

SSDA1/CTS3#/

RTS3#/MOSIB-A

19

20

TCK

P27

P17

MTIOC2B/TMCI3

SCK1/RSPCKB-A

MTIOC3A/MTIOC3B/

MTIOC4B/TIOCB0/

TCLKD/TMO1/

POE8#

SCK1/TXD3/SSDA3/

SDA2-DS

IRQ7

IRQ6

ADTRG1#

ADTRG0#

ADTRG1#

21

P16

MTIOC3C/MTIOC3D/ TXD1/SMOSI1/

TIOCB1/TCLKC/

TMO2/RTCOUT

SSDA1/RXD3/

SSCL3/SCL2-DS/

USB0_VBUS

22

23

P13

P12

MTIOC0B/TIOCA5/

TMO3

TXD2/SSDA2/

SDA0[FM+]

IRQ3

IRQ2

TMCI1

RXD2/SSCL2/

SCL0[FM+]

24

25

26

27

28

29

VCC_USB

USB0_DM

USB0_DP

VSS_USB

UB

P53

PC7

MTIOC3A/MTCLKB/

TMO2/TOC0/

CACREF

TXD8/SMOSI8/

SSDA8/SMOSI10/

SSDA10/TXD10/

MISOA-A

IRQ14

IRQ13

30

PC6

MTIOC3C/MTCLKA/

TMCI2/TIC0

RXD8/SMISO8/

SSCL8/SMISO10/

SSCL10/RXD10/

MOSIA-A

31

32

PC5

PC4

MTIOC3B/MTCLKD/

TMRI2

SCK8/SCK10/

RSPCKA-A

MTIOC3D/MTCLKC/

TMCI1/POE0#

CTS8#/RTS8#/SS8#/

SS10#/CTS10#/

RTS10#/SSLA0-A

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1. Overview

Table 1.12

List of Pin and Pin Functions (64-Pin LFQFP) (2/2)

Number

Timer

Communication

Memory Interface

(QSPI, SDHI)

Power Supply

Clock System

Control

(MTU, TPU, TMR,

RTC, CMTW, POE,

CAC)

64-Pin

LFQFP

(SCI, RSPI, RIIC,

USB)

A/D

D/A

I/O Port

PC1

Interrupt

IRQ12

33

34

35

MTIOC3A/TCLKD

MTIOC3C/TCLKC

MTIOC3B/TIOCB5

SSLA2-A

SSLA1-A

PC0

IRQ14

PB7

TXD9/SSDA9/

SSDA11/TXD11

36

37

PB6

PB5

MTIOC3D/TIOCA5

RXD9/SSCL9/

SSCL11/RXD11

MTIOC2A/MTIOC1B/ SCK9/SCK11

TIOCB4/TMRI1/

POE4#

38

39

40

41

VCC

VSS

PA7

PA6

TIOCB2

MTIC5V/MTCLKB/

TIOCA2/TMCI3/

POE10#

CTS5#/RTS5#/SS5#

42

43

44

PA4

PA2

PA1

MTIC5U/MTCLKA/

TIOCA1/TMRI0

TXD5/SMOSI5/

SSDA5

IRQ5-DS

IRQ11

MTIOC7A

RXD5/SMISO5/

SSCL5

MTIOC0B/MTCLKC/

MTIOC7B/TIOCB0

SCK5

45

46

47

PE7

PE6

PE2

MTIOC6A/TOC1

MTIOC6C/TIC1

MTIOC4A/TIC3

SDHI_WP

SDHI_CD

IRQ7

IRQ6

RXD12/SSCL12/

RXDX12

IRQ7-DS

48

PE1

MTIOC4C/MTIOC3B

TXD12/SSDA12/

TXDX12/SIOX12

ANEX1

49

50

PE0

PD7

MTIOC3D

SCK12

ANEX0

AN107

MTIC5U/POE0#

QMI-B/QIO1-B/

SDHI_D1-B

IRQ7

IRQ6

IRQ5

51

52

53

54

PD6

PD5

PD4

PD3

MTIC5V/MTIOC8A/

POE4#

QMO-B/QIO0-B/

SDHI_D0-B

AN106

AN113

AN112

AN111

MTIC5W/MTIOC8C/

POE10#

QSPCLK-B/

SDHI_CLK-B

MTIOC8B/POE11#

QSSL-B/SDHI_CMD- IRQ4

B

MTIOC8D/TOC2/

POE8#

QIO3-B/SDHI_D3-B

IRQ3

55

56

57

58

59

60

61

62

63

64

PD2

P43

P42

P41

MTIOC4D/TIC2

QIO2-B/SDHI_D2-B

IRQ2

AN110

AN003

AN002

AN001

IRQ11-DS

IRQ10-DS

IRQ9-DS

VREFL0

P40

IRQ8-DS

AN000

VREFH0

AVCC0

AVSS0

P05

IRQ13

DA1

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RX65N Group, RX651 Group

2. CPU

2.

CPU

Figure 2.1 shows register set of the CPU.

Control register

b31

General-purpose register

b31

b0

R0 (SP)^*1

ISP (Interrupt stack pointer)

USP (User stack pointer)

R1

R2

INTB (Interrupt table register)

R3

R4

PC (Program counter)

R5

PSW (Processor status word)

BPC (Backup PC)

R6

R7

R8

BPSW (Backup PSW)

R9

R10

R11

R12

R13

R14

R15

FINTV (Fast interrupt vector register)

FPSW (Floating-point status word)

EXTB (Exception table register)

DSP instruction register

b71

b0

ACC0 (Accumulator 0)

ACC1 (Accumulator 1)

Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to

the value of the U bit in the PSW.

Figure 2.1

Register Set of the CPU

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2. CPU

2.1

General-Purpose Registers (R0 to R15)

This CPU has sixteen 32-bit general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address

registers.

R0, a general-purpose register, also functions as the stack pointer (SP).

The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the

stack pointer select bit (U) in the processor status word (PSW).

2.2

Control Registers

(1) Interrupt Stack Pointer (ISP) / User Stack Pointer (USP)

The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).

Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the

processor status word (PSW).

(2) Exception Table Register (EXTB)

The exception table register (EXTB) specifies the address where the exception vector table starts.

(3) Interrupt Table Register (INTB)

The interrupt table register (INTB) specifies the address where the interrupt vector table starts.

(4) Program Counter (PC)

The program counter (PC) indicates the address of the instruction being executed.

(5) Processor Status Word (PSW)

The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.

(6) Backup PC (BPC)

The backup PC (BPC) is provided to speed up response to interrupts.

After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.

(7) Backup PSW (BPSW)

The backup PSW (BPSW) is provided to speed up response to interrupts.

After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The

allocation of bits in the BPSW corresponds to that in the PSW.

(8) Fast Interrupt Vector Register (FINTV)

The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.

The FINTV register specifies a branch destination address when a fast interrupt has been generated.

(9) Floating-Point Status Word (FPSW)

The floating-point status word (FPSW) indicates the results of floating-point operations.

When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified

by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the

occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has

been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V).

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2. CPU

2.3

Accumulator

The accumulator (ACC0 or ACC1) is a 72-bit register used for DSP instructions. The accumulator is handled as a 96-bit

register for reading and writing. At this time, when bits 95 to 72 of the accumulator are read, the value where the value of

bit 71 is sign extended is read. Writing to bits 95 to 72 of the accumulator is ignored. ACC0 is also used for the multiply

and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in

ACC0 is modified by execution of the instruction.

Use the MVTACGU, MVTACHI, and MVTACLO instructions for writing to the accumulator. The MVTACGU,

MVTACHI, and MVTACLO instructions write data to bits 95 to 64, the higher-order 32 bits (bits 63 to 32), and the

lower-order 32 bits (bits 31 to 0), respectively.

Use the MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions for reading data from the accumulator. The

MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions read data from the guard bits (bits 95 to 64), higher-

order 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 16), and the lower-order 32 bits (bits 31 to 0), respectively.

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3. Address Space

3.

Address Space

3.1

Address Space

This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,

linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.

Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the

operating mode and states of control bits.

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3. Address Space

On-chip ROM enabled

extended mode

On-chip ROM disabled

Single-chip mode*¹

extended mode

0000 0000h

0004 0000h

0000 0000h

0004 0000h

0000 0000h

0004 0000h

On-chip RAM*⁵

Reserved area*²

On-chip RAM*⁵

Reserved area*²

On-chip RAM*⁵

Reserved area*²

0008 0000h

000A 4000h

000A 6000h

0008 0000h

000A 4000h

000A 6000h

0008 0000h

000A 4000h

000A 6000h

Peripheral I/O registers

Standby RAM

Peripheral I/O registers

Standby RAM

Peripheral I/O registers

Standby RAM

Peripheral I/O registers

0010 0000h

On-chip ROM

(data flash memory)*⁵

0010 8000h

Reserved area*²

007E 0000h

007F 0004h

007E 0000h

007F 0004h

FACI command issuing area

Reserved area*²

FACI command issuing area

Reserved area*²

007F C000h

0080 0000h

007F C000h

0080 0000h

Peripheral I/O registers

0080 0000h

0086 0000h

On-chip expansion RAM*⁵

Reserved area*²

0086 0000h

0100 0000h

Reserved area*²

0100 0000h

External address space

(CS area)

External address space

(CS area)

0800 0000h

1000 0000h

0800 0000h

1000 0000h

External address space

(SDRAM area)

External address space

(SDRAM area)

Reserved area*²

FF00 0000h

FE7F 5D00h

FE7F 5D80h

FE7F 5D00h

FE7F 5D80h

On-chip ROM (option-setting memory)*³

Reserved area*²

On-chip ROM (option-setting memory)*³

Reserved area*²

FE7F 7D70h

FE7F 7DA0h

FFE0 0000h

FE7F 7D70h

FE7F 7DA0h

FFE0 0000h

External address space

(CS area)

On-chip ROM (read only)*³

Reserved area*²

On-chip ROM (read only)*³

Reserved area*²

On-chip ROM

4,

5

(code flash memory) *^3,

* *

4,

5

(code flash memory)*^3,

* *

FFFF FFFFh

Note 1. The address space in boot mode is the same as the address space in single-chip mode.

Note 2. Reserved areas should not be accessed.

Note 3. The access cycle is 1 cycle, 2 cycles, and 3 cycles while the ROMWT[1:0] bits are 00b, 01b, and 10b respectively.

Note 4. The on-chip ROM (code flash memory) can be used in linear mode, where the user area forms a single area, or in dual mode,

where the user area is divided into two banks. For details, refer to section 59.2, Structure of Memory in section 59, Flash

Memory in the User’s Manual: Hardware.

Note 5. The capacities of the code flash memory, data flash memory, and RAM differ depending on the products.

Code Flash Memory

Address

Data Flash Memory

RAM

Dual mode

(BANKSEL.BANKSWP[2:0]

= 111b)

Capacity

Address

Capacity

Address

Linear mode

2 Mbytes

FFE0 0000h to

FFFF FFFFh

bank 1:

FFE0 0000h to FFEF FFFFh

32 Kbytes

0010 0000h to

0010 7FFFh

640 Kbytes 0000 0000h to

0003 FFFFh

bank 0:

FFF0 0000h to FFFF FFFFh

0080 0000h to

0085 FFFFh

1.5 Mbytes FFE8 0000h to

FFFF FFFFh

bank 1:

FFE4 0000h to FFEF FFFFh

32 Kbytes

0010 0000h to

0010 7FFFh

640 Kbytes 0000 0000h to

0003 FFFFh

bank 0:

FFF4 0000h to FFFF FFFFh

0080 0000h to

0085 FFFFh

1 Mbyte

FFF0 0000h to

FFFF FFFFh

256 Kbytes 0000 0000h to

0003 FFFFh

—

768 Kbytes FFF4 0000h to

FFFF FFFFh

256 Kbytes 0000 0000h to

0003 FFFFh

512 Kbytes FFF8 0000h to

FFFF FFFFh

256 Kbytes 0000 0000h to

0003 FFFFh

Figure 3.1

Memory Map in Each Operating Mode

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3. Address Space

3.2

External Address Space

The external address space is divided into CS areas (CS0 to CS7) and SDRAM area (SDCS). The CS areas are divided

into up to eight areas (CS0 to CS7), each corresponding to the CSn# signal output from a CSn# (n = 0 to 7) pin.

Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) and SDRAM area (SDCS)

in on-chip ROM disabled extended mode.

0100 0000h

0000 0000h

RAM

Reserved area^*1

Peripheral I/O registers

Standby RAM

0004 0000h

0008 0000h

000A 4000h

000A 6000h

CS7 (16 Mbytes)

CS6 (16 Mbytes)

CS5 (16 Mbytes)

CS4 (16 Mbytes)

CS3 (16 Mbytes)

CS2 (16 Mbytes)

CS1 (16 Mbytes)

01FF FFFFh

0200 0000h

Peripheral I/O registers

0010 0000h

Reserved area^*1

02FF FFFFh

0300 0000h

0080 0000h

0086 0000h

Expansion RAM^*2

Reserved area^*1

03FF FFFFh

0400 0000h

0100 0000h

External address space

(CS area)

04FF FFFFh

0500 0000h

0800 0000h

1000 0000h

05FF FFFFh

0600 0000h

External address space

(SDRAM area)

06FF FFFFh

0700 0000h

07FF FFFFh

0800 0000h

Reserved area^*1

SDCS (128 Mbytes)

0FFF FFFFh

FF00 0000h

FFFF FFFFh

External address space^*3

(CS area)

CS0 (16 Mbytes)

FFFF FFFFh

Note 1. Reserved areas should not be accessed.

Note 2. This area is only included in products with at least 1.5 Mbytes of code flash memory.

Note 3. The CS0 area is disabled in on-chip ROM enabled extended mode.

In this mode, the address space for addresses above 1000 0000h is as shown in figure on this

section, Memory Map in Each Operating Mode.

Figure 3.2

Correspondence between External Address Spaces and CS Areas

(In On-Chip ROM Disabled Extended Mode)

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4. I/O Registers

4.

I/O Registers

This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on

writing to registers are also given at the end.

(1) I/O register addresses (address order)



Registers are listed from the lower allocation addresses.

Registers are classified according to module symbols.

The number of access cycles indicates the number of cycles based on the specified reference clock.

Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses

must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and

subsequent operations cannot be guaranteed.

(2) Notes on writing to I/O registers

When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.

This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the

operation.

As described in the following examples, special care is required for the cases in which the subsequent instruction must be

executed after the post-update I/O register value is actually reflected.

[Examples of cases requiring special care]



The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the

ICU (interrupt request enable bit) set to 0.



A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power

consumption state.

In the above cases, after writing to an I/O register, wait until the write operation is completed using the following

procedure and then execute the subsequent instruction.

(a) Write to an I/O register.

(b) Read the value from the I/O register to a general register.

(c) Execute the operation using the value read.

(d) Execute the subsequent instruction.

[Instruction examples]



Byte-size I/O registers

MOV.L #SFR_ADDR, R1

MOV.B #SFR_DATA, [R1]

CMP [R1].UB, R1

;; Next process



Word-size I/O registers

MOV.L #SFR_ADDR, R1

MOV.W #SFR_DATA, [R1]

CMP [R1].W, R1

;; Next process

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4. I/O Registers



Longword-size I/O registers

MOV.L #SFR_ADDR, R1

MOV.L #SFR_DATA, [R1]

CMP [R1].L, R1

;; Next process

If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely

completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary

to read or execute operation for all the registers that were written to.

(3) Number of Access Cycles to I/O Registers

For the number of I/O register access cycles, refer to Table 4.1, List of I/O Registers (Address Order).

1

The number of access cycles to I/O registers is obtained by following equation.*

Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +

Number of divided clock synchronization cycles +

Number of bus cycles for internal peripheral busses 1 to 6

The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.

When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except

for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.

The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK

(or FCLK, BCLK) or bus access timing.

In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the

sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will

be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of

access states shown in Table 4.1.

When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the

ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described

on an ICLK basis.

In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided

clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of

access cycles shown in Table 4.1.

Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction fetching

to the external memory or bus access from the different bus master (DMAC or DTC).

(4) Notes on Sleep Mode and Mode Transitions

During sleep mode or mode transitions, do not write to the registers related to system control (indicated by 'SYSTEM' in

the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).

(5) Restrictions in Relation to RMPA and String-Manipulation Instructions

The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited, and

operation is not guaranteed if this restriction is not observed.

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4. I/O Registers

4.1

I/O Register Addresses (Address Order)

Table 4.1

List of I/O Registers (Address Order) (1 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

16

0008 0000h

SYSTE Mode Monitor Register

M

MDMONR

3 ICLK

Operating

Modes

3 ICLK

0008 0006h

0008 0008h

0008 000Ch

SYSTE System Control Register 0

M

SYSCR0

SYSCR1

SBYCR

Operating

Modes

SYSTE System Control Register 1

M

Operating

Modes

SYSTE Standby Control Register

M

Low

Power

Consumpt

ion

32

3 ICLK

0008 0010h

0008 0014h

0008 0018h

0008 001Ch

SYSTE Module Stop Control Register A

M

MSTPCRA

MSTPCRB

MSTPCRC

MSTPCRD

Low

Power

Consumpt

ion

SYSTE Module Stop Control Register B

M

Low

Power

Consumpt

ion

SYSTE Module Stop Control Register C

M

Low

Power

Consumpt

ion

SYSTE Module Stop Control Register D

M

Low

Power

Consumpt

ion

32

16

8

32

16

8

3 ICLK

0008 0020h

0008 0024h

0008 0026h

0008 0028h

0008 002Ah

0008 0030h

0008 0032h

0008 0033h

0008 0034h

0008 0035h

0008 0036h

0008 0037h

0008 003Ch

SYSTE System Clock Control Register

M

SCKCR

Clock

Generatio

n Circuit

SYSTE System Clock Control Register 2

M

SCKCR2

SCKCR3

PLLCR

Clock

Generatio

n Circuit

SYSTE System Clock Control Register 3

M

Clock

Generatio

n Circuit

SYSTE PLL Control Register

M

Clock

Generatio

n Circuit

SYSTE PLL Control Register 2

M

PLLCR2

BCKCR

Clock

Generatio

n Circuit

8

SYSTE External Bus Clock Control Register

M

Clock

Generatio

n Circuit

8

SYSTE Main Clock Oscillator Control Register

M

MOSCCR

SOSCCR

LOCOCR

Clock

Generatio

n Circuit

8

SYSTE Sub-Clock Oscillator Control Register

M

Clock

Generatio

n Circuit

8

SYSTE Low-Speed On-Chip Oscillator Control Register

M

Clock

Generatio

n Circuit

8

SYSTE IWDT-Dedicated On-Chip Oscillator Control Register ILOCOCR

M

Clock

Generatio

n Circuit

8

SYSTE High-Speed On-Chip Oscillator Control Register

M

HOCOCR

Clock

Generatio

n Circuit

8

SYSTE High-Speed On-Chip Oscillator Control Register 2

M

HOCOCR2

OSCOVFSR

Clock

Generatio

n Circuit

8

SYSTE Oscillation Stabilization Flag Register

M

Clock

Generatio

n Circuit

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 94 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (2 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

3 ICLK

0008 0040h

SYSTE Oscillation Stop Detection Control Register

M

OSTDCR

OSTDSR

OPCCR

Clock

Generatio

n Circuit

3 ICLK

0008 0041h

0008 00A0h

SYSTE Oscillation Stop Detection Status Register

M

Clock

Generatio

n Circuit

SYSTE Operating Power Control Register

M

Low

Power

Consumpt

ion

8

3 ICLK

0008 00A1h

SYSTE Sleep Mode Return Clock Source Switching Register RSTCKCR

M

Low

Power

Consumpt

ion

8

3 ICLK

0008 00A2h

0008 00A3h

SYSTE Main Clock Oscillator Wait Control Register

M

MOSCWTCR

SOSCWTCR

Clock

Generatio

n Circuit

SYSTE Sub-Clock Oscillator Wait Control Register

M

Clock

Generatio

n Circuit

8

16

8

16

8

3 ICLK

0008 00C0h

0008 00C2h

0008 00E0h

0008 00E1h

0008 00E2h

0008 00E3h

0008 03FEh

SYSTE Reset Status Register 2

M

RSTSR2

SWRR

Resets

LVDA

SYSTE Software Reset Register

M

SYSTE Voltage Monitoring 1 Circuit Control Register 1

M

LVD1CR1

LVD1SR

LVD2CR1

LVD2SR

PRCR

8

SYSTE Voltage Monitoring 1 Circuit Status Register

M

8

SYSTE Voltage Monitoring 2 Circuit Control Register 1

M

8

SYSTE Voltage Monitoring 2 Circuit Status Register

M

16

SYSTE Protect Register

M

Register

Write

Protection

Function

16

8

16

8

2 ICLK

0008 1000h

0008 1004h

0008 101Ch

FLASH ROM Cache Enable Register

FLASH ROM Cache Invalidate Register

ROMCE

ROMCIV

ROMWT

Flash

SYSTE ROM Wait Cycle Setting Register

M

Clock

Generatio

n Circuit

8

2 ICLK

0008 1200h

0008 1201h

0008 1204h

0008 1208h

0008 1240h

RAM

RAM Operating Mode Control Register

RAM Error Status Register

RAMMODE

RAMSTS

RAM

8

RAM Protection Register

RAMPRCR

RAMECAD

32

8

32

8

RAM Error Address Capture Register

Expansion RAM Operating Mode Control Register

EXRAMMOD

E

8

2 ICLK

0008 1241h

0008 1244h

0008 1248h

0008 1300h

0008 1304h

0008 1308h

0008 130Ah

0008 1310h

0008 2000h

0008 2004h

0008 2008h

0008 200Ch

0008 2010h

0008 2013h

RAM

BSC

Expansion RAM Error Status Register

Expansion RAM Protection Register

Expansion RAM Error Address Capture Register

Bus Error Status Clear Register

Bus Error Monitoring Enable Register

Bus Error Status Register 1

EXRAMSTS

EXRAMPRCR

EXRAMECAD

BERCLR

BEREN

RAM

32

8

32

8

RAM

Buses

8

Buses

8

BERSR1

BERSR2

BUSPRI

Buses

16

32

16

8

16

32

16

8

Bus Error Status Register 2

Buses

Bus Priority Control Register

Buses

DMAC0 DMA Source Address Register

DMAC0 DMA Destination Address Register

DMAC0 DMA Transfer Count Register

DMAC0 DMA Block Transfer Count Register

DMAC0 DMA Transfer Mode Register

DMAC0 DMA Interrupt Setting Register

DMSAR

DMACAa

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 95 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (3 / 60)

Number of Access Cycles

ICLK ≥ PCLK

2 ICLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

DMACAa

16

32

8

16

32

8

0008 2014h

0008 2018h

0008 201Ch

0008 201Dh

0008 201Eh

0008 201Fh

0008 2040h

0008 2044h

0008 2048h

0008 204Ch

0008 2050h

0008 2053h

0008 2054h

0008 205Ch

0008 205Dh

0008 205Eh

0008 205Fh

0008 2080h

0008 2084h

0008 2088h

0008 208Ch

0008 2090h

0008 2093h

0008 2094h

0008 209Ch

0008 209Dh

0008 209Eh

0008 209Fh

0008 20C0h

0008 20C4h

0008 20C8h

DMAC0 DMA Address Mode Register

DMAC0 DMA Offset Register

DMAMD

DMOFR

DMCNT

DMREQ

DMSTS

DMCSL

DMSAR

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

DMAC0 DMA Transfer Enable Register

DMAC0 DMA Software Start Register

DMAC0 DMA Status Register

8

DMAC0 DMA Request Source Flag Control Register

DMAC1 DMA Source Address Register

DMAC1 DMA Destination Address Register

DMAC1 DMA Transfer Count Register

DMAC1 DMA Block Transfer Count Register

DMAC1 DMA Transfer Mode Register

DMAC1 DMA Interrupt Setting Register

DMAC1 DMA Address Mode Register

DMAC1 DMA Transfer Enable Register

DMAC1 DMA Software Start Register

DMAC1 DMA Status Register

32

16

8

32

16

8

16

8

16

8

DMAMD

DMCNT

DMREQ

DMSTS

DMCSL

DMSAR

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

8

DMAC1 DMA Request Source Flag Control Register

DMAC2 DMA Source Address Register

DMAC2 DMA Destination Address Register

DMAC2 DMA Transfer Count Register

DMAC2 DMA Block Transfer Count Register

DMAC2 DMA Transfer Mode Register

DMAC2 DMA Interrupt Setting Register

DMAC2 DMA Address Mode Register

DMAC2 DMA Transfer Enable Register

DMAC2 DMA Software Start Register

DMAC2 DMA Status Register

32

16

8

32

16

8

16

8

16

8

DMAMD

DMCNT

DMREQ

DMSTS

DMCSL

DMSAR

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

8

DMAC2 DMA Request Source Flag Control Register

DMAC3 DMA Source Address Register

DMAC3 DMA Destination Address Register

DMAC3 DMA Transfer Count Register

32

16

8

32

16

8

0008 20CCh DMAC3 DMA Block Transfer Count Register

0008 20D0h

0008 20D3h

0008 20D4h

DMAC3 DMA Transfer Mode Register

DMAC3 DMA Interrupt Setting Register

DMAC3 DMA Address Mode Register

16

8

16

8

DMAMD

DMCNT

DMREQ

DMSTS

DMCSL

DMSAR

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

0008 20DCh DMAC3 DMA Transfer Enable Register

0008 20DDh DMAC3 DMA Software Start Register

0008 20DEh DMAC3 DMA Status Register

8

0008 20DFh DMAC3 DMA Request Source Flag Control Register

32

16

8

32

16

8

0008 2100h

0008 2104h

0008 2108h

0008 210Ch

0008 2110h

0008 2113h

0008 2114h

0008 211Ch

0008 211Dh

0008 211Eh

0008 211Fh

DMAC4 DMA Source Address Register

DMAC4 DMA Destination Address Register

DMAC4 DMA Transfer Count Register

DMAC4 DMA Block Transfer Count Register

DMAC4 DMA Transfer Mode Register

DMAC4 DMA Interrupt Setting Register

DMAC4 DMA Address Mode Register

DMAC4 DMA Transfer Enable Register

DMAC4 DMA Software Start Register

DMAC4 DMA Status Register

16

8

16

8

DMAMD

DMCNT

DMREQ

DMSTS

DMCSL

8

DMAC4 DMA Request Source Flag Control Register

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 96 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (4 / 60)

Number of Access Cycles

ICLK ≥ PCLK

2 ICLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

DMACAa

DTCb

32

16

8

32

16

8

0008 2140h

0008 2144h

0008 2148h

0008 214Ch

0008 2150h

0008 2153h

0008 2154h

0008 215Ch

0008 215Dh

0008 215Eh

0008 215Fh

0008 2180h

0008 2184h

0008 2188h

0008 218Ch

0008 2190h

0008 2193h

0008 2194h

0008 219Ch

0008 219Dh

0008 219Eh

0008 219Fh

0008 21C0h

0008 21C4h

0008 21C8h

DMAC5 DMA Source Address Register

DMAC5 DMA Destination Address Register

DMAC5 DMA Transfer Count Register

DMAC5 DMA Block Transfer Count Register

DMAC5 DMA Transfer Mode Register

DMAC5 DMA Interrupt Setting Register

DMAC5 DMA Address Mode Register

DMAC5 DMA Transfer Enable Register

DMAC5 DMA Software Start Register

DMAC5 DMA Status Register

DMSAR

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

2 ICLK

16

8

16

8

2 ICLK

DMAMD

DMCNT

DMREQ

DMSTS

DMCSL

DMSAR

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

2 ICLK

8

2 ICLK

8

2 ICLK

8

2 ICLK

DMAC5 DMA Request Source Flag Control Register

DMAC6 DMA Source Address Register

DMAC6 DMA Destination Address Register

DMAC6 DMA Transfer Count Register

DMAC6 DMA Block Transfer Count Register

DMAC6 DMA Transfer Mode Register

DMAC6 DMA Interrupt Setting Register

DMAC6 DMA Address Mode Register

DMAC6 DMA Transfer Enable Register

DMAC6 DMA Software Start Register

DMAC6 DMA Status Register

32

16

8

32

16

8

2 ICLK

16

8

16

8

2 ICLK

DMAMD

DMCNT

DMREQ

DMSTS

DMCSL

DMSAR

DMDAR

DMCRA

DMCRB

DMTMD

DMINT

2 ICLK

8

2 ICLK

8

2 ICLK

8

2 ICLK

DMAC6 DMA Request Source Flag Control Register

DMAC7 DMA Source Address Register

DMAC7 DMA Destination Address Register

DMAC7 DMA Transfer Count Register

32

16

8

32

16

8

2 ICLK

0008 21CCh DMAC7 DMA Block Transfer Count Register

2 ICLK

0008 21D0h

0008 21D3h

0008 21D4h

DMAC7 DMA Transfer Mode Register

DMAC7 DMA Interrupt Setting Register

DMAC7 DMA Address Mode Register

2 ICLK

16

8

16

8

2 ICLK

DMAMD

DMCNT

DMREQ

DMSTS

DMCSL

DMAST

DMIST

2 ICLK

0008 21DCh DMAC7 DMA Transfer Enable Register

0008 21DDh DMAC7 DMA Software Start Register

0008 21DEh DMAC7 DMA Status Register

8

2 ICLK

8

2 ICLK

8

2 ICLK

0008 21DFh DMAC7 DMA Request Source Flag Control Register

8

2 ICLK

0008 2200h

0008 2204h

0008 2400h

0008 2404h

0008 2408h

0008 240Ch

0008 240Eh

0008 2410h

0008 2414h

0008 2416h

0008 2418h

0008 2800h

DMAC DMAC Module Start Register

8

2 ICLK

DMAC DMAC74 Interrupt Status Monitor Register

8

2 ICLK

DTC

DTC Control Register

DTCCR

DTCVBR

DTCADMOD

DTCST

32

8

32

8

2 ICLK

DTC Vector Base Register

DTC Address Mode Register

DTC Module Start Register

DTC Status Register

DTCb

2 ICLK

DTCb

8

2 ICLK

DTCb

16

32

8

16

32

8

2 ICLK

DTCSTS

DTCIBR

DTCOR

DTCSQE

DTCDISP

EDMSAR

DTCb

2 ICLK

DTC Index Table Base Register

DTC Operation Register

DTCb

2 ICLK

DTCb

16

32

16

32

2 ICLK

DTC Sequence Transfer Enable Register

DTC Address Displacement Register

DTCb

2 ICLK

DTCb

1, 2 BCLK

EXDMA EXDMA Source Address Register

C0

EXDMAC

a

32

1, 2 BCLK

0008 2804h

0008 2808h

EXDMA EXDMA Destination Address Register

C0

EDMDAR

EDMCRA

EXDMAC

a

EXDMA EXDMA Transfer Count Register

C0

EXDMAC

a

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 97 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (5 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

16

8

16

8

1, 2 BCLK

0008 280Ch

EXDMA EXDMA Block Transfer Count Register

C0

EDMCRB

EDMTMD

EDMOMD

EDMINT

EXDMAC

a

1, 2 BCLK

0008 2810h

0008 2812h

0008 2813h

0008 2814h

0008 2818h

0008 281Ch

0008 281Dh

0008 281Eh

0008 2820h

0008 2821h

0008 2822h

0008 2840h

0008 2844h

0008 2848h

0008 284Ch

0008 2850h

0008 2852h

0008 2853h

0008 2854h

0008 285Ch

0008 285Dh

0008 285Eh

0008 2860h

0008 2861h

0008 2862h

0008 2A00h

EXDMA EXDMA Transfer Mode Register

C0

EXDMAC

a

EXDMA EXDMA Output Setting Register

C0

EXDMAC

a

8

EXDMA EXDMA Interrupt Setting Register

C0

EXDMAC

a

32

8

32

8

EXDMA EXDMA Address Mode Register

C0

EDMAMD

EDMOFR

EDMCNT

EDMREQ

EDMSTS

EDMRMD

EDMERF

EDMPRF

EDMSAR

EDMDAR

EDMCRA

EDMCRB

EDMTMD

EDMOMD

EDMINT

EXDMAC

a

EXDMA EXDMA Offset Register

C0

EXDMAC

a

EXDMA EXDMA Transfer Enable Register

C0

EXDMAC

a

8

EXDMA EXDMA Software Start Register

C0

EXDMAC

a

8

EXDMA EXDMA Status Register

C0

EXDMAC

a

8

EXDMA EXDMA External Request Sense Mode Register

C0

EXDMAC

a

8

EXDMA EXDMA External Request Flag Register

C0

EXDMAC

a

8

EXDMA EXDMA Peripheral Request Flag Register

C0

EXDMAC

a

32

16

8

32

16

8

EXDMA EXDMA Source Address Register

C1

EXDMAC

a

EXDMA EXDMA Destination Address Register

C1

EXDMAC

a

EXDMA EXDMA Transfer Count Register

C1

EXDMAC

a

EXDMA EXDMA Block Transfer Count Register

C1

EXDMAC

a

EXDMA EXDMA Transfer Mode Register

C1

EXDMAC

a

EXDMA EXDMA Output Setting Register

C1

EXDMAC

a

8

EXDMA EXDMA Interrupt Setting Register

C1

EXDMAC

a

32

8

32

8

EXDMA EXDMA Address Mode Register

C1

EDMAMD

EDMCNT

EDMREQ

EDMSTS

EDMRMD

EDMERF

EDMPRF

EDMAST

CLSBR0

CLSBR1

CLSBR2

CLSBR3

EXDMAC

a

EXDMA EXDMA Transfer Enable Register

C1

EXDMAC

a

8

EXDMA EXDMA Software Start Register

C1

EXDMAC

a

8

EXDMA EXDMA Status Register

C1

EXDMAC

a

8

EXDMA EXDMA External Request Sense Mode Register

C1

EXDMAC

a

8

EXDMA EXDMA External Request Flag Register

C1

EXDMAC

a

8

EXDMA EXDMA Peripheral Request Flag Register

C1

EXDMAC

a

8

EXDMA EXDMAC Module Start Register

C

EXDMAC

a

32

0008 2BE0h EXDMA Cluster Buffer Register 0

C

EXDMAC

a

0008 2BE4h EXDMA Cluster Buffer Register 1

C

EXDMAC

a

0008 2BE8h EXDMA Cluster Buffer Register 2

C

EXDMAC

a

0008 2BECh EXDMA Cluster Buffer Register 3

C

EXDMAC

a

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 98 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (6 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

32

1, 2 BCLK

0008 2BF0h

EXDMA Cluster Buffer Register 4

C

CLSBR4

CLSBR5

CLSBR6

CLSBR7

EXDMAC

a

1, 2 BCLK

0008 2BF4h

0008 2BF8h

EXDMA Cluster Buffer Register 5

C

EXDMAC

a

EXDMA Cluster Buffer Register 6

C

EXDMAC

a

0008 2BFCh EXDMA Cluster Buffer Register 7

C

EXDMAC

a

16

32

16

32

16

32

16

32

16

32

16

32

16

32

16

32

16

8

16

32

16

32

16

32

16

32

16

32

16

32

16

32

16

32

16

8

1, 2 BCLK

0008 3002h

0008 3004h

0008 3008h

0008 3012h

0008 3014h

0008 3018h

0008 3022h

0008 3024h

0008 3028h

0008 3032h

0008 3034h

0008 3038h

0008 3042h

0008 3044h

0008 3048h

0008 3052h

0008 3054h

0008 3058h

0008 3062h

0008 3064h

0008 3068h

0008 3072h

0008 3074h

0008 3078h

0008 3802h

0008 380Ah

0008 3812h

0008 381Ah

0008 3822h

0008 382Ah

0008 3832h

0008 383Ah

0008 3842h

0008 384Ah

0008 3852h

0008 385Ah

0008 3862h

0008 386Ah

0008 3872h

0008 387Ah

0008 3880h

0008 3C00h

0008 3C01h

BSC

CS0 Mode Register

CS0MOD

CS0WCR1

CS0WCR2

CS1MOD

CS1WCR1

CS1WCR2

CS2MOD

CS2WCR1

CS2WCR2

CS3MOD

CS3WCR1

CS3WCR2

CS4MOD

CS4WCR1

CS4WCR2

CS5MOD

CS5WCR1

CS5WCR2

CS6MOD

CS6WCR1

CS6WCR2

CS7MOD

CS7WCR1

CS7WCR2

CS0CR

Buses

CS0 Wait Control Register 1

CS0 Wait Control Register 2

CS1 Mode Register

CS1 Wait Control Register 1

CS1 Wait Control Register 2

CS2 Mode Register

CS2 Wait Control Register 1

CS2 Wait Control Register 2

CS3 Mode Register

CS3 Wait Control Register 1

CS3 Wait Control Register 2

CS4 Mode Register

CS4 Wait Control Register 1

CS4 Wait Control Register 2

CS5 Mode Register

CS5 Wait Control Register 1

CS5 Wait Control Register 2

CS6 Mode Register

CS6 Wait Control Register 1

CS6 Wait Control Register 2

CS7 Mode Register

CS7 Wait Control Register 1

CS7 Wait Control Register 2

CS0 Control Register

CS0 Recovery Cycle Register

CS1 Control Register

CS0REC

CS1CR

CS1 Recovery Cycle Register

CS2 Control Register

CS1REC

CS2CR

CS2 Recovery Cycle Register

CS3 Control Register

CS2REC

CS3CR

CS3 Recovery Cycle Register

CS4 Control Register

CS3REC

CS4CR

CS4 Recovery Cycle Register

CS5 Control Register

CS4REC

CS5CR

CS5 Recovery Cycle Register

CS6 Control Register

CS5REC

CS6CR

CS6 Recovery Cycle Register

CS7 Control Register

CS6REC

CS7CR

CS7 Recovery Cycle Register

CS Recovery Cycle Insertion Enable Register

SDC Control Register

CS7REC

CSRECEN

SDCCR

8

SDC Mode Register

SDCMOD

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 99 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (7 / 60)

Number of Access Cycles

ICLK ≥ PCLK

1, 2 BCLK

1 ICLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

Buses

MPU

ICUB

8

0008 3C02h

0008 3C10h

0008 3C14h

0008 3C16h

0008 3C20h

0008 3C24h

0008 3C40h

0008 3C44h

0008 3C48h

0008 3C50h

0008 6400h

0008 6404h

0008 6408h

0008 640Ch

0008 6410h

0008 6414h

0008 6418h

0008 641Ch

0008 6420h

0008 6424h

0008 6428h

0008 642Ch

0008 6430h

0008 6434h

0008 6438h

0008 643Ch

0008 6500h

0008 6504h

0008 6508h

0008 650Ch

0008 6514h

0008 6520h

0008 6524h

0008 6526h

0008 6528h

0008 652Ch

BSC

MPU

SDRAM Access Mode Register

SDAMOD

SDSELF

SDRFCR

SDRFEN

SDICR

8

SDRAM Self-Refresh Control Register

SDRAM Refresh Control Register

SDRAM Auto-Refresh Control Register

SDRAM Initialization Sequence Control Register

SDRAM Initialization Register

16

8

16

8

16

8

16

8

SDIR

SDRAM Address Register

SDADR

32

16

8

32

16

8

SDRAM Timing Register

SDTR

SDRAM Mode Register

SDMOD

SDSR

SDRAM Status Register

32

16

32

8

32

16

32

8

Region-0 Start Page Number Register

Region-0 End Page Number Register

Region-1 Start Page Number Register

Region-1 End Page Number Register

Region-2 Start Page Number Register

Region-2 End Page Number Register

Region-3 Start Page Number Register

Region-3 End Page Number Register

Region-4 Start Page Number Register

Region-4 End Page Number Register

Region-5 Start Page Number Register

Region-5 End Page Number Register

Region-6 Start Page Number Register

Region-6 End Page Number Register

Region-7 Start Page Number Register

Region-7 End Page Number Register

Memory-Protection Enable Register

Background Access Control Register

Memory-Protection Error Status-Clearing Register

Memory-Protection Error Status Register

Data Memory-Protection Error Address Register

Region Search Address Register

Region Search Operation Register

Region Invalidation Operation Register

Instruction-Hit Region Register

RSPAGE0

REPAGE0

RSPAGE1

REPAGE1

RSPAGE2

REPAGE2

RSPAGE3

REPAGE3

RSPAGE4

REPAGE4

RSPAGE5

REPAGE5

RSPAGE6

REPAGE6

RSPAGE7

REPAGE7

MPEN

1 ICLK

MPBAC

1 ICLK

MPECLR

MPESTS

MPDEA

1 ICLK

MPSA

1 ICLK

MPOPS

MPOPI

1 ICLK

MHITI

1 ICLK

Data-Hit Region Register

MHITD

2 ICLK

0008 7010h to ICU

0008 70FFh

Interrupt Request Register 016 to Interrupt Request

Register 255

IR016 to

IR255

8

2 ICLK

0008711Ahto ICU

0008 71FFh

DTC Transfer Request Enable Register 026 to DTC

Transfer Request Enable Register 255

DTCER026 to

DTCER255

ICUB

0008 7202h to ICU

0008 721Fh

Interrupt Request Enable Register 02 to Interrupt

Request Enable Register 1F

IER02 to

IER1F

8

2 ICLK

0008 72E0h

0008 72E1h

0008 72F0h

ICU

Software Interrupt Generation Register

Software Interrupt 2 Generation Register

Fast Interrupt Set Register

SWINTR

SWINT2R

FIR

ICUB

16

8

16

8

0008 7300h to ICU

0008 73FFh

Interrupt Source Priority Register 000 to Interrupt

Source Priority Register 255

IPR000 to

IPR255

8

2 ICLK

0008 7400h

0008 7404h

0008 7408h

0008 740Ch

ICU

DMAC Trigger Select Register 0

DMAC Trigger Select Register 1

DMAC Trigger Select Register 2

DMAC Trigger Select Register 3

DMRSR0

DMRSR1

DMRSR2

DMRSR3

ICUB

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 100 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (8 / 60)

Number of Access Cycles

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK ≥ PCLK

ICLK < PCLK

8

2 ICLK

0008 7410h

0008 7414h

0008 7418h

0008 741Ch

ICU

DMAC Trigger Select Register 4

DMRSR4

DMRSR5

DMRSR6

DMRSR7

ICUB

2 ICLK

DMAC Trigger Select Register 5

ICUB

2 ICLK

DMAC Trigger Select Register 6

ICUB

2 ICLK

DMAC Trigger Select Register 7

ICUB

2 ICLK

0008 7500h to ICU

0008 750Fh

IRQ Control Register 0 to IRQ Control Register 15

IRQCR0 to

IRQCR15

ICUB

8

2 ICLK

0008 7520h

0008 7521h

0008 7528h

0008 752Ah

0008 7580h

0008 7581h

0008 7582h

0008 7583h

0008 7590h

0008 7594h

0008 7600h

ICU

IRQ Pin Digital Filter Enable Register 0

IRQ Pin Digital Filter Enable Register 1

IRQ Pin Digital Filter Setting Register 0

IRQ Pin Digital Filter Setting Register 1

Non-Maskable Interrupt Status Register

Non-Maskable Interrupt Enable Register

Non-Maskable Interrupt Status Clear Register

NMI Pin Interrupt Control Register

IRQFLTE0

IRQFLTE1

IRQFLTC0

IRQFLTC1

NMISR

ICUB

16

8

16

8

NMIER

8

NMICLR

NMICR

8

NMI Pin Digital Filter Enable Register

NMI Pin Digital Filter Setting Register

Group BE0 Interrupt Request Register

NMIFLTE

NMIFLTC

GRPBE0

8

32

2 ICLK to

1 PCLKB

2 ICLK

32

8

32

8

2 ICLK to

1 PCLKB

2 ICLK

0008 7630h

0008 7634h

0008 7638h

0008 7640h

0008 7670h

0008 7674h

0008 7678h

0008 7680h

0008 7700h

0008 7701h

0008 7702h

0008 7703h

0008 7704h

0008 7705h

0008 7706h

0008 7707h

0008 7708h

0008 7709h

0008 770Ah

0008 770Bh

0008 7780h

ICU

Group BL0 Interrupt Request Register

Group BL1 Interrupt Request Register

Group BL2 Interrupt Request Register

Group BE0 Interrupt Request Enable Register

Group BL0 Interrupt Request Enable Register

Group BL1 Interrupt Request Enable Register

Group BL2 Interrupt Request Enable Register

Group BE0 Interrupt Clear Register

GRPBL0

GRPBL1

GRPBL2

GENBE0

GENBL0

GENBL1

GENBL2

GCRBE0

ICUB

2 ICLK to

1 PCLKB

2 ICLK to

1 PCLKB

2 ICLK to

1 PCLKB

2 ICLK to

1 PCLKB

2 ICLK to

1 PCLKB

2 ICLK to

1 PCLKB

2 ICLK to

1 PCLKB

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Request Register 0 PIBR0

Software Configurable Interrupt B Request Register 1 PIBR1

Software Configurable Interrupt B Request Register 2 PIBR2

Software Configurable Interrupt B Request Register 3 PIBR3

Software Configurable Interrupt B Request Register 4 PIBR4

Software Configurable Interrupt B Request Register 5 PIBR5

Software Configurable Interrupt B Request Register 6 PIBR6

Software Configurable Interrupt B Request Register 7 PIBR7

Software Configurable Interrupt B Request Register 8 PIBR8

Software Configurable Interrupt B Request Register 9 PIBR9

Software Configurable Interrupt B Request Register A PIBRA

Software Configurable Interrupt B Request Register B PIBRB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

8

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X128

SLIBXR128

8

2 ICLK to

1 PCLKB

2 ICLK

0008 7781h

0008 7782h

ICU

Software Configurable Interrupt B Source Select

Register X129

SLIBXR129

SLIBXR130

ICUB

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X130

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 101 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (9 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2 ICLK to

1 PCLKB

2 ICLK

0008 7783h

ICU

Software Configurable Interrupt B Source Select

Register X131

SLIBXR131

SLIBXR132

SLIBXR133

SLIBXR134

SLIBXR135

SLIBXR136

SLIBXR137

SLIBXR138

SLIBXR139

SLIBXR140

SLIBXR141

SLIBXR142

SLIBXR143

SLIBR144

SLIBR145

SLIBR146

SLIBR147

SLIBR148

SLIBR149

SLIBR150

SLIBR151

SLIBR152

SLIBR153

SLIBR154

SLIBR155

SLIBR156

SLIBR157

SLIBR158

SLIBR159

SLIBR160

SLIBR161

ICUB

2 ICLK to

1 PCLKB

2 ICLK

0008 7784h

0008 7785h

0008 7786h

0008 7787h

0008 7788h

0008 7789h

0008 778Ah

0008 778Bh

0008 778Ch

0008 778Dh

0008 778Eh

0008 778Fh

0008 7790h

0008 7791h

0008 7792h

0008 7793h

0008 7794h

0008 7795h

0008 7796h

0008 7797h

0008 7798h

0008 7799h

0008 779Ah

0008 779Bh

0008 779Ch

0008 779Dh

0008 779Eh

0008 779Fh

0008 77A0h

0008 77A1h

Software Configurable Interrupt B Source Select

Register X132

ICUB

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X133

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X134

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X135

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X136

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X137

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X138

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X139

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X140

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X141

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X142

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register X143

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 144

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 145

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 146

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 147

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 148

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 149

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 150

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 151

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 152

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 153

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 154

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 155

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 156

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 157

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 158

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 159

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 160

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 161

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 102 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (10 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2 ICLK to

1 PCLKB

2 ICLK

0008 77A2h

ICU

Software Configurable Interrupt B Source Select

Register 162

SLIBR162

SLIBR163

SLIBR164

SLIBR165

SLIBR166

SLIBR167

SLIBR168

SLIBR169

SLIBR170

SLIBR171

SLIBR172

SLIBR173

SLIBR174

SLIBR175

SLIBR176

SLIBR177

SLIBR178

SLIBR179

SLIBR180

SLIBR181

SLIBR182

SLIBR183

SLIBR184

SLIBR185

SLIBR186

SLIBR187

SLIBR188

SLIBR189

SLIBR190

SLIBR191

SLIBR192

ICUB

2 ICLK to

1 PCLKB

2 ICLK

0008 77A3h

0008 77A4h

0008 77A5h

0008 77A6h

0008 77A7h

0008 77A8h

0008 77A9h

Software Configurable Interrupt B Source Select

Register 163

ICUB

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 164

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 165

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 166

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 167

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 168

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 169

2 ICLK to

1 PCLKB

0008 77AAh ICU

0008 77ABh ICU

0008 77ACh ICU

0008 77ADh ICU

0008 77AEh ICU

Software Configurable Interrupt B Source Select

Register 170

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 171

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 172

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 173

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 174

2 ICLK to

1 PCLKB

0008 77AFh

0008 77B0h

0008 77B1h

0008 77B2h

0008 77B3h

0008 77B4h

0008 77B5h

0008 77B6h

0008 77B7h

0008 77B8h

0008 77B9h

ICU

Software Configurable Interrupt B Source Select

Register 175

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 176

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 177

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 178

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 179

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 180

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 181

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 182

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 183

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 184

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 185

2 ICLK to

1 PCLKB

0008 77BAh ICU

0008 77BBh ICU

0008 77BCh ICU

0008 77BDh ICU

0008 77BEh ICU

Software Configurable Interrupt B Source Select

Register 186

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 187

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 188

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 189

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 190

2 ICLK to

1 PCLKB

0008 77BFh

0008 77C0h

ICU

Software Configurable Interrupt B Source Select

Register 191

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 192

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 103 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (11 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2 ICLK to

1 PCLKB

2 ICLK

0008 77C1h

ICU

Software Configurable Interrupt B Source Select

Register 193

SLIBR193

SLIBR194

SLIBR195

SLIBR196

SLIBR197

SLIBR198

SLIBR199

SLIBR200

SLIBR201

SLIBR202

SLIBR203

SLIBR204

SLIBR205

SLIBR206

SLIBR207

ICUB

2 ICLK to

1 PCLKB

2 ICLK

0008 77C2h

0008 77C3h

0008 77C4h

0008 77C5h

0008 77C6h

0008 77C7h

0008 77C8h

0008 77C9h

Software Configurable Interrupt B Source Select

Register 194

ICUB

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 195

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 196

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 197

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 198

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 199

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 200

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 201

2 ICLK to

1 PCLKB

0008 77CAh ICU

0008 77CBh ICU

0008 77CCh ICU

0008 77CDh ICU

0008 77CEh ICU

0008 77CFh ICU

Software Configurable Interrupt B Source Select

Register 202

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 203

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 204

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 205

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 206

2 ICLK to

1 PCLKB

Software Configurable Interrupt B Source Select

Register 207

32

8

32

8

2 ICLK to

1 PCLKA

2 ICLK

0008 7830h

0008 7834h

0008 7870h

0008 7874h

0008 7900h

0008 7901h

0008 7902h

0008 7903h

0008 7904h

0008 7905h

0008 790Bh

0008 79D0h

ICU

Group AL0 Interrupt Request Register

GRPAL0

GRPAL1

GENAL0

GENAL1

ICUB

2 ICLK to

1 PCLKA

Group AL1 Interrupt Request Register

2 ICLK to

1 PCLKA

Group AL0 Interrupt Request Enable Register

Group AL1 Interrupt Request Enable Register

2 ICLK to

1 PCLKA

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Request Register 0 PIAR0

Software Configurable Interrupt A Request Register 1 PIAR1

Software Configurable Interrupt A Request Register 2 PIAR2

Software Configurable Interrupt A Request Register 3 PIAR3

Software Configurable Interrupt A Request Register 4 PIAR4

Software Configurable Interrupt A Request Register 5 PIAR5

Software Configurable Interrupt A Request Register B PIARB

8

2 ICLK to

1 PCLKA

8

2 ICLK to

1 PCLKA

8

2 ICLK to

1 PCLKA

8

2 ICLK to

1 PCLKA

8

2 ICLK to

1 PCLKA

8

2 ICLK to

1 PCLKA

8

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 208

SLIAR208

8

2 ICLK to

1 PCLKA

2 ICLK

0008 79D1h

0008 79D2h

0008 79D3h

0008 79D4h

0008 79D5h

0008 79D6h

ICU

Software Configurable Interrupt A Source Select

Register 209

SLIAR209

SLIAR210

SLIAR211

SLIAR212

SLIAR213

SLIAR214

ICUB

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 210

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 211

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 212

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 213

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 214

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 104 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (12 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2 ICLK to

1 PCLKA

2 ICLK

0008 79D7h

ICU

Software Configurable Interrupt A Source Select

Register 215

SLIAR215

SLIAR216

SLIAR217

SLIAR218

SLIAR219

SLIAR220

SLIAR221

SLIAR222

SLIAR223

SLIAR224

SLIAR225

SLIAR226

SLIAR227

SLIAR228

SLIAR229

SLIAR230

SLIAR231

SLIAR232

SLIAR233

SLIAR234

SLIAR235

SLIAR236

SLIAR237

SLIAR238

SLIAR239

SLIAR240

SLIAR241

SLIAR242

SLIAR243

SLIAR244

SLIAR245

ICUB

2 ICLK to

1 PCLKA

2 ICLK

0008 79D8h

0008 79D9h

Software Configurable Interrupt A Source Select

Register 216

ICUB

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 217

2 ICLK to

1 PCLKA

0008 79DAh ICU

0008 79DBh ICU

0008 79DCh ICU

0008 79DDh ICU

0008 79DEh ICU

0008 79DFh ICU

Software Configurable Interrupt A Source Select

Register 218

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 219

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 220

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 221

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 222

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 223

2 ICLK to

1 PCLKA

0008 79E0h

0008 79E1h

0008 79E2h

0008 79E3h

0008 79E4h

0008 79E5h

0008 79E6h

0008 79E7h

0008 79E8h

0008 79E9h

ICU

Software Configurable Interrupt A Source Select

Register 224

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 225

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 226

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 227

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 228

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 229

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 230

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 231

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 232

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 233

2 ICLK to

1 PCLKA

0008 79EAh ICU

0008 79EBh ICU

0008 79ECh ICU

0008 79EDh ICU

0008 79EEh ICU

Software Configurable Interrupt A Source Select

Register 234

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 235

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 236

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 237

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 238

2 ICLK to

1 PCLKA

0008 79EFh

0008 79F0h

0008 79F1h

0008 79F2h

0008 79F3h

0008 79F4h

0008 79F5h

ICU

Software Configurable Interrupt A Source Select

Register 239

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 240

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 241

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 242

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 243

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 244

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 245

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 105 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (13 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2 ICLK to

1 PCLKA

2 ICLK

0008 79F6h

ICU

Software Configurable Interrupt A Source Select

Register 246

SLIAR246

SLIAR247

SLIAR248

SLIAR249

SLIAR250

SLIAR251

SLIAR252

SLIAR253

SLIAR254

SLIAR255

SLIPRCR

SELEXDR

ICUB

2 ICLK to

1 PCLKA

2 ICLK

0008 79F7h

0008 79F8h

0008 79F9h

0008 79FAh

0008 79FBh

Software Configurable Interrupt A Source Select

Register 247

ICUB

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 248

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 249

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 250

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 251

2 ICLK to

1 PCLKA

0008 79FCh ICU

0008 79FDh ICU

Software Configurable Interrupt A Source Select

Register 252

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 253

2 ICLK to

1 PCLKA

0008 79FEh

0008 79FFh

0008 7A00h

0008 7A01h

ICU

Software Configurable Interrupt A Source Select

Register 254

2 ICLK to

1 PCLKA

Software Configurable Interrupt A Source Select

Register 255

2 ICLK to

1 PCLKA/B

Software Configurable Interrupt Source Select

Register Write Protect Register

2 ICLK to

1 PCLKA/B

EXDMAC Trigger Select Register

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 8000h

0008 8002h

0008 8004h

0008 8006h

0008 8008h

0008 800Ah

0008 800Ch

0008 8010h

0008 8012h

0008 8014h

0008 8016h

0008 8018h

0008 801Ah

0008 801Ch

0008 8020h

0008 8022h

0008 8024h

0008 8026h

0008 8030h

0008 8032h

0008 8034h

0008 8036h

0008 8038h

0008 8040h

0008 8042h

0008 8044h

0008 8045h

0008 8046h

0008 8048h

0008 805Ch

0008 8100h

CMT

CMT0

CMT1

CMT

CMT2

CMT3

WDT

IWDT

DA

Compare Match Timer Start Register 0

Compare Match Timer Control Register

Compare Match Counter

CMSTR0

CMCR

CMT

CMCNT

CMCOR

CMCR

CMT

Compare Match Constant Register

Compare Match Timer Control Register

Compare Match Counter

CMT

CMCNT

CMCOR

CMSTR1

CMCR

CMT

Compare Match Constant Register

Compare Match Timer Start Register 1

Compare Match Timer Control Register

Compare Match Counter

CMT

CMCNT

CMCOR

CMCR

CMT

Compare Match Constant Register

Compare Match Timer Control Register

Compare Match Counter

CMT

CMCNT

CMCOR

WDTRR

WDTCR

WDTSR

WDTRCR

IWDTRR

IWDTCR

IWDTSR

IWDTRCR

IWDTCSTPR

DADR0

CMT

Compare Match Constant Register

WDT Refresh Register

CMT

WDTA

IWDTa

R12DA

TPUa

16

8

16

8

WDT Control Register

WDT Status Register

WDT Reset Control Register

IWDT Refresh Register

8

16

8

16

8

IWDT Control Register

IWDT Status Register

IWDT Reset Control Register

IWDT Count Stop Control Register

D/A Data Register 0

8

16

8

16

8

DA

D/A Data Register 1

DADR1

DA

D/A Control Register

DACR

8

DA

Data Register Format Select Register

D/A A/D Synchronous Start Control Register

D/A Output Amplifier Control Register

DADPR

DAADSCR

DAAMPCR

8

DA

8

DA

8

DA

D/A Output Amplifier Stabilization Wait Control Register DAASWCR

Timer Start Register TSTR

8

TPUA

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 106 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (14 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

TPUa

8

2, 3 PCLKB

2 ICLK

0008 8101h

0008 8108h

0008 8109h

0008 810Ah

0008 810Bh

0008 810Ch

0008 810Dh

0008 8110h

0008 8111h

0008 8112h

0008 8113h

0008 8114h

0008 8115h

0008 8116h

0008 8118h

0008 811Ah

0008 811Ch

0008 811Eh

0008 8120h

0008 8121h

0008 8122h

0008 8124h

0008 8125h

0008 8126h

0008 8128h

0008 812Ah

0008 8130h

0008 8131h

0008 8132h

0008 8134h

0008 8135h

0008 8136h

0008 8138h

0008 813Ah

0008 8140h

0008 8141h

0008 8142h

0008 8143h

0008 8144h

0008 8145h

0008 8146h

0008 8148h

0008 814Ah

0008 814Ch

0008 814Eh

0008 8150h

0008 8151h

0008 8152h

0008 8154h

0008 8155h

TPUA

TPU0

TPU1

TPU2

TPU3

TPU4

TPU5

TPU0

TPU1

TPU2

TPU3

TPU4

Timer Synchronous Register

TSYR

NFCR

TCR

2 ICLK

Noise Filter Control Register

Timer Control Register

Timer Mode Register

8

TMDR

TIORH

TIORL

TIER

8

Timer I/O Control Register H

Timer I/O Control Register L

Timer Interrupt Enable Register

Timer Status Register

8

TSR

16

8

16

8

Timer Counter

TCNT

TGRA

TGRB

TGRC

TGRD

TCR

Timer General Register A

Timer General Register B

Timer General Register C

Timer General Register D

Timer Control Register

Timer Mode Register

8

TMDR

TIOR

TIER

8

Timer I/O Control Register

Timer Interrupt Enable Register

Timer Status Register

8

TSR

16

8

16

8

Timer Counter

TCNT

TGRA

TGRB

TCR

Timer General Register A

Timer General Register B

Timer Control Register

Timer Mode Register

8

TMDR

TIOR

TIER

8

Timer I/O Control Register

Timer Interrupt Enable Register

Timer Status Register

8

TSR

16

8

16

8

Timer Counter

TCNT

TGRA

TGRB

TCR

Timer General Register A

Timer General Register B

Timer Control Register

Timer Mode Register

8

TMDR

TIORH

TIORL

TIER

8

Timer I/O Control Register H

Timer I/O Control Register L

Timer Interrupt Enable Register

Timer Status Register

8

TSR

16

8

16

8

Timer Counter

TCNT

TGRA

TGRB

TGRC

TGRD

TCR

Timer General Register A

Timer General Register B

Timer General Register C

Timer General Register D

Timer Control Register

Timer Mode Register

8

TMDR

TIOR

TIER

8

Timer I/O Control Register

Timer Interrupt Enable Register

Timer Status Register

8

TSR

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 107 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (15 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

TPUa

PPG

TMR

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 8156h

0008 8158h

0008 815Ah

0008 8160h

0008 8161h

0008 8162h

0008 8164h

0008 8165h

0008 8166h

0008 8168h

0008 816Ah

0008 81E6h

0008 81E7h

0008 81E8h

0008 81E9h

TPU4

TPU5

PPG0

Timer Counter

TCNT

TGRA

TGRB

TCR

2 ICLK

Timer General Register A

Timer General Register B

Timer Control Register

Timer Mode Register

8

TMDR

TIOR

8

Timer I/O Control Register

Timer Interrupt Enable Register

Timer Status Register

8

TIER

8

TSR

16

8

16

8

Timer Counter

TCNT

Timer General Register A

Timer General Register B

PPG Output Control Register

PPG Output Mode Register

Next Data Enable Register H

Next Data Enable Register L

Output Data Register H

Output Data Register L

Next Data Register H

TGRA

TGRB

PCR

8

PMR

8

NDERH

NDERL

PODRH

PODRL

NDRH

NDRL

NDRH2

NDRL2

PTRSLR

PCR

8

0008 81EAh PPG0

0008 81EBh PPG0

0008 81ECh PPG0

0008 81EDh PPG0

0008 81EEh PPG0

8

Next Data Register L

8

Next Data Register H2

Next Data Register L2

8

0008 81EFh

0008 81F0h

0008 81F6h

0008 81F7h

0008 81F8h

0008 81F9h

0008 81FAh

0008 81FBh

PPG0

PPG1

8

PPG Trigger Select Register

PPG Output Control Register

PPG Output Mode Register

Next Data Enable Register H

Next Data Enable Register L

Output Data Register H

Output Data Register L

Next Data Register H

8

PMR

8

NDERH

NDERL

PODRH

PODRL

NDRH

NDRL

NDRH2

NDRL2

TCR

8

0008 81FCh PPG1

0008 81FDh PPG1

8

Next Data Register L

8

0008 81FEh

0008 81FFh

0008 8200h

0008 8201h

0008 8202h

0008 8203h

0008 8204h

0008 8205h

0008 8206h

0008 8207h

0008 8208h

0008 8209h

0008 820Ah

0008 820Bh

0008 820Ch

0008 820Dh

PPG1

TMR0

TMR1

TMR0

TMR1

TMR0

Next Data Register H2

Next Data Register L2

8

Timer Control Register

Timer Control/Status Register

Time Constant Register A

8

TCR

8

TCSR

TCORA

TCORB

TCNT

8

16

8

16

8

TMR01 Time Constant Register A

TMR1

TMR0

Time Constant Register A

Time Constant Register B

8

16

8

16

8

TMR01 Time Constant Register B

TMR1

TMR0

Time Constant Register B

Timer Counter

8

16

8

16

8

TMR01 Timer Counter

TCNT

TMR1

TMR0

Timer Counter

TCNT

8

Timer Counter Control Register

TCCR

TCSTR

16

8

16

8

TMR01 Timer Counter Control Register

TMR1

TMR0

TMR1

Timer Counter Control Register

Timer Counter Start Register

8

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 108 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (16 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

TMR

CRCA

8

2, 3 PCLKB

2 ICLK

0008 8210h

0008 8211h

0008 8212h

0008 8213h

0008 8214h

0008 8215h

0008 8216h

0008 8217h

0008 8218h

0008 8219h

0008 821Ah

0008 821Bh

0008 821Ch

0008 821Dh

0008 8280h

0008 8284h

0008 8288h

TMR2

TMR3

TMR2

TMR3

TMR2

Timer Control Register

TCR

2 ICLK

Timer Control Register

TCR

8

Timer Control/Status Register

Time Constant Register A

TCSR

8

TCSR

8

TCORA

TCORB

TCNT

16

8

16

8

TMR23 Time Constant Register A

TMR3

TMR2

Time Constant Register A

Time Constant Register B

8

16

8

16

8

TMR23 Time Constant Register B

TMR3

TMR2

Time Constant Register B

Timer Counter

8

16

8

16

8

TMR23 Timer Counter

TCNT

TMR3

TMR2

Timer Counter

TCNT

8

Timer Counter Control Register

TCCR

16

8

16

8

TMR23 Timer Counter Control Register

TCCR

TMR3

TMR2

TMR3

CRC

Timer Counter Control Register

Timer Counter Start Register

CRC Control Register

TCCR

8

TCSTR

CRCCR

CRCDIR

CRCDOR

8

32

8, 32

CRC

CRC Data Input Register

CRC Data Output Register

8, 16,

32

CRC

2

8

2, 3 PCLKB

2 ICLK

0008 8300h

0008 8301h

0008 8302h

0008 8303h

0008 8304h

0008 8305h

0008 8306h

0008 8307h

0008 8308h

0008 8309h

0008 830Ah

0008 830Bh

0008 830Ch

0008 830Dh

0008 830Eh

0008 830Fh

0008 8310h

0008 8311h

0008 8312h

0008 8313h

0008 8320h

0008 8321h

0008 8322h

0008 8323h

0008 8324h

0008 8325h

0008 8326h

0008 8327h

RIIC0

RIIC1

I C-bus Control Register 1

ICCR1

ICCR2

ICMR1

ICMR2

ICMR3

ICFER

ICSER

ICIER

RIICa

2

I C-bus Control Register 2

2

I C-bus Mode Register 1

2

I C-bus Mode Register 2

2

I C-bus Mode Register 3

2

I C-bus Function Enable Register

2

I C-bus Status Enable Register

2

I C-bus Interrupt Enable Register

2

I C-bus Status Register 1

ICSR1

ICSR2

SARL0

SARU0

SARL1

SARU1

SARL2

SARU2

ICBRL

ICBRH

ICDRT

ICDRR

ICCR1

ICCR2

ICMR1

ICMR2

ICMR3

ICFER

ICSER

ICIER

2

I C-bus Status Register 2

Slave Address Register L0

Slave Address Register U0

Slave Address Register L1

Slave Address Register U1

Slave Address Register L2

Slave Address Register U2

2

I C-bus Bit Rate Low-Level Register

2

I C-bus Bit Rate High-Level Register

2

I C-bus Transmit Data Register

2

I C-bus Receive Data Register

2

I C-bus Control Register 1

2

I C-bus Control Register 2

2

I C-bus Mode Register 1

2

I C-bus Mode Register 2

2

I C-bus Mode Register 3

2

I C-bus Function Enable Register

2

I C-bus Status Enable Register

2

I C-bus Interrupt Enable Register

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 109 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (17 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

RIICa

MMCIF

2

8

2, 3 PCLKB

2 ICLK

0008 8328h

0008 8329h

0008 832Ah

0008 832Bh

0008 832Ch

0008 832Dh

0008 832Eh

0008 832Fh

0008 8330h

0008 8331h

0008 8332h

0008 8333h

0008 8340h

0008 8341h

0008 8342h

0008 8343h

0008 8344h

0008 8345h

0008 8346h

0008 8347h

0008 8348h

0008 8349h

0008 834Ah

0008 834Bh

0008 834Ch

0008 834Dh

0008 834Eh

0008 834Fh

0008 8350h

0008 8351h

0008 8352h

0008 8353h

0008 8500h

0008 8508h

0008 850Ch

RIIC1

RIIC2

I C-bus Status Register 1

ICSR1

ICSR2

SARL0

SARU0

SARL1

SARU1

SARL2

SARU2

ICBRL

ICBRH

ICDRT

ICDRR

ICCR1

ICCR2

ICMR1

ICMR2

ICMR3

ICFER

ICSER

ICIER

2

2 ICLK

I C-bus Status Register 2

8

Slave Address Register L0

Slave Address Register U0

Slave Address Register L1

Slave Address Register U1

Slave Address Register L2

Slave Address Register U2

8

2

8

I C-bus Bit Rate Low-Level Register

2

8

I C-bus Bit Rate High-Level Register

2

8

I C-bus Transmit Data Register

2

8

I C-bus Receive Data Register

2

8

I C-bus Control Register 1

2

8

I C-bus Control Register 2

2

8

I C-bus Mode Register 1

2

8

I C-bus Mode Register 2

2

8

I C-bus Mode Register 3

2

8

I C-bus Function Enable Register

2

8

I C-bus Status Enable Register

2

8

I C-bus Interrupt Enable Register

2

8

I C-bus Status Register 1

ICSR1

ICSR2

SARL0

SARU0

SARL1

SARU1

SARL2

SARU2

ICBRL

ICBRH

ICDRT

ICDRR

CECMDSET

CEARG

2

8

I C-bus Status Register 2

8

Slave Address Register L0

Slave Address Register U0

Slave Address Register L1

Slave Address Register U1

Slave Address Register L2

Slave Address Register U2

8

2

8

I C-bus Bit Rate Low-Level Register

2

8

I C-bus Bit Rate High-Level Register

2

8

I C-bus Transmit Data Register

2

8

I C-bus Receive Data Register

32

MMCIF Command Setting Register

MMCIF Argument Register

MMCIF Automatically Issued CMD12 Argument Register

CEARGCMD

12

32

2, 3 PCLKB

2 ICLK

0008 8510h

0008 8514h

MMCIF Command Control Register

CECMDCTRL

MMCIF

MMCIF Transfer Block Setting Register

CEBLOCKSE

T

32

2, 3 PCLKB

2 ICLK

0008 8518h

0008 851Ch

0008 8520h

0008 8524h

0008 8528h

0008 852Ch

0008 8530h

MMCIF Clock Control Register

CECLKCTRL

CEBUFACC

CERESP3

CERESP2

CERESP1

CERESP0

MMCIF

MMCIF Buffer Access Setting Register

MMCIF Response Register 3

MMCIF Response Register 2

MMCIF Response Register 1

MMCIF Response Register 0

MMCIF Automatically Issued CMD12 Response Register

CERESPCM

D12

32

2, 3 PCLKB

2 ICLK

0008 8534h

0008 853Ch

0008 8540h

0008 8544h

MMCIF Data Register

CEDATA

CEBOOT

CEINT

MMCIF

MMCIF Boot Operation Setting Register

MMCIF Interrupt Status Flag Register

MMCIF Interrupt Request Enable Register

CEINTEN

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 110 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (18 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

32

2, 3 PCLKB

2 ICLK

0008 8548h

MMCIF Status Register 1

CEHOSTSTS

1

MMCIF

32

2, 3 PCLKB

2 ICLK

0008 854Ch

MMCIF Status Register 2

CEHOSTSTS

2

MMCIF

32

2, 3 PCLKB

2 ICLK

0008 8570h

0008 8574h

MMCIF MMC Detection and Port Control Register

MMCIF Special Mode Setting Register

CEDETECT

MMCIF

CEADDMOD

E

32

16

32

16

2, 3 PCLKB

2 ICLK

0008 857Ch

0008 9000h

0008 9004h

0008 9008h

MMCIF Version Register

CEVERSION

ADCSR

MMCIF

S12AD A/D Control Register

S12AD A/D Channel Select Register A0

S12ADFa

ADANSA0

ADADS0

S12AD A/D-Converted Value Addition/Average Function

Channel Select Register 0

8

2, 3 PCLKB

2 ICLK

0008 900Ch

S12AD A/D-Converted Value Addition/Average Count Select ADADC

Register

S12ADFa

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 900Eh

0008 9010h

0008 9014h

0008 9018h

0008 901Eh

0008 9020h

0008 9022h

0008 9024h

0008 9026h

0008 9028h

0008 902Ah

0008 902Ch

0008 902Eh

0008 9063h

S12AD A/D Control Extended Register

S12AD A/D Conversion Start Trigger Select Register

S12AD A/D Channel Select Register B0

S12AD A/D Data Duplication Register

S12AD A/D Self-Diagnosis Data Register

S12AD A/D Data Register 0

ADCER

ADSTRGR

ADANSB0

ADDBLDR

ADRD

S12ADFa

ADDR0

S12AD A/D Data Register 1

ADDR1

S12AD A/D Data Register 2

ADDR2

S12AD A/D Data Register 3

ADDR3

S12AD A/D Data Register 4

ADDR4

S12AD A/D Data Register 5

ADDR5

S12AD A/D Data Register 6

ADDR6

S12AD A/D Data Register 7

ADDR7

S12AD A/D Conversion Time Setting Protection Release

Register

ADSAMPR

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 9066h

0008 906Eh

0008 907Ah

0008 907Ch

S12AD A/D Sample-and-Hold Circuit Control Register

S12AD A/D Conversion Time Setting Register

ADSHCR

ADSAM

S12ADFa

S12AD A/D Disconnection Detection Control Register

ADDISCR

ADSHMSR

8

S12AD A/D Sample-and-Hold Operating Mode Select

Register

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 9080h

0008 9084h

0008 9086h

0008 908Ch

S12AD A/D Group Scan Priority Control Register

S12AD A/D Data Duplication Register A

S12AD A/D Data Duplication Register B

ADGSPCR

ADDBLDRA

ADDBLDRB

ADWINMON

S12ADFa

S12AD A/D Comparison Function Window A/B Status

Monitoring Register

16

2, 3 PCLKB

2 ICLK

0008 9090h

0008 9094h

S12AD A/D Comparison Function Control Register

ADCMPCR

S12ADFa

S12AD A/D Comparison Function Window A Channel Select ADCMPANSR

Register 0

0

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 9098h

0008 909Ch

0008 909Eh

0008 90A0h

0008 90A6h

0008 90A8h

S12AD A/D Comparison Function Window A Comparison

Condition Setting Register 0

ADCMPLR0

S12ADFa

S12AD A/D Comparison Function Window A Lower Level

Setting Register

ADCMPDR0

ADCMPDR1

S12AD A/D Comparison Function Window A Upper Level

Setting Register

S12AD A/D Comparison Function Window A Channel Status ADCMPSR0

Register 0

S12AD A/D Comparison Function Window B Channel Select ADCMPBNS

Register

R

16

S12AD A/D Comparison Function Window B Lower Level

Setting Register

ADWINLLB

0008 90AAh S12AD A/D Comparison Function Window B Upper Level

Setting Register

ADWINULB

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 111 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (19 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

2 ICLK

0008 90ACh S12AD A/D Comparison Function Window B Channel Status ADCMPBSR

Register

S12ADFa

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 90D4h

0008 90D9h

0008 90E0h

0008 90E1h

0008 90E2h

0008 90E3h

0008 90E4h

0008 90E5h

0008 90E6h

0008 90E7h

0008 9100h

0008 9104h

0008 9106h

0008 9108h

S12AD A/D Channel Select Register C0

S12AD A/D Group C Trigger Select Register

S12AD A/D Sampling State Register 0

S12AD A/D Sampling State Register 1

S12AD A/D Sampling State Register 2

S12AD A/D Sampling State Register 3

S12AD A/D Sampling State Register 4

S12AD A/D Sampling State Register 5

S12AD A/D Sampling State Register 6

S12AD A/D Sampling State Register 7

S12AD1 A/D Control Register

ADANSC0

ADGCTRGR

ADSSTR0

ADSSTR1

ADSSTR2

ADSSTR3

ADSSTR4

ADSSTR5

ADSSTR6

ADSSTR7

ADCSR

S12ADFa

8

16

S12AD1 A/D Channel Select Register A0

S12AD1 A/D Channel Select Register A1

ADANSA0

ADANSA1

ADADS0

S12AD1 A/D-Converted Value Addition/Average Function

Channel Select Register 0

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 910Ah

0008 910Ch

S12AD1 A/D-Converted Value Addition/Average Function

Channel Select Register 1

ADADS1

S12ADFa

S12AD1 A/D-Converted Value Addition/Average Count Select ADADC

Register

16

2, 3 PCLKB

2 ICLK

0008 910Eh

0008 9110h

0008 9112h

0008 9114h

0008 9116h

0008 9118h

0008 911Ah

0008 911Ch

0008 911Eh

0008 9120h

0008 9122h

0008 9124h

0008 9126h

0008 9128h

0008 912Ah

0008 912Ch

0008 912Eh

0008 9130h

0008 9132h

0008 9134h

0008 9136h

0008 9138h

0008 913Ah

0008 913Ch

0008 913Eh

0008 9140h

0008 9142h

0008 9144h

0008 9146h

0008 9148h

S12AD1 A/D Control Extended Register

S12AD1 A/D Conversion Start Trigger Select Register

S12AD1 A/D Conversion Extended Input Control Register

S12AD1 A/D Channel Select Register B0

S12AD1 A/D Channel Select Register B1

S12AD1 A/D Data Duplication Register

S12AD1 A/D Temperature Sensor Data Register

S12AD1 A/D Internal Reference Voltage Data Register

S12AD1 A/D Self-Diagnosis Data Register

S12AD1 A/D Data Register 0

ADCER

ADSTRGR

ADEXICR

ADANSB0

ADANSB1

ADDBLDR

ADTSDR

ADOCDR

ADRD

S12ADFa

ADDR0

S12AD1 A/D Data Register 1

ADDR1

S12AD1 A/D Data Register 2

ADDR2

S12AD1 A/D Data Register 3

ADDR3

S12AD1 A/D Data Register 4

ADDR4

S12AD1 A/D Data Register 5

ADDR5

S12AD1 A/D Data Register 6

ADDR6

S12AD1 A/D Data Register 7

ADDR7

S12AD1 A/D Data Register 8

ADDR8

S12AD1 A/D Data Register 9

ADDR9

S12AD1 A/D Data Register 10

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

ADDR20

S12AD1 A/D Data Register 11

S12AD1 A/D Data Register 12

S12AD1 A/D Data Register 13

S12AD1 A/D Data Register 14

S12AD1 A/D Data Register 15

S12AD1 A/D Data Register 16

S12AD1 A/D Data Register 17

S12AD1 A/D Data Register 18

S12AD1 A/D Data Register 19

S12AD1 A/D Data Register 20

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 112 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (20 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

2 ICLK

0008 9163h

S12AD1 A/D Conversion Time Setting Protection Release

Register

ADSAMPR

S12ADFa

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 916Eh

0008 917Ah

0008 9180h

0008 9184h

0008 9186h

0008 918Ch

S12AD1 A/D Conversion Time Setting Register

S12AD1 A/D Disconnection Detection Control Register

S12AD1 A/D Group Scan Priority Control Register

S12AD1 A/D Data Duplication Register A

ADSAM

S12ADFa

ADDISCR

ADGSPCR

ADDBLDRA

ADDBLDRB

ADWINMON

16

8

16

8

S12AD1 A/D Data Duplication Register B

S12AD1 A/D Comparison Function Window A/B Status

Monitoring Register

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 9190h

0008 9192h

S12AD1 A/D Comparison Function Control Register

ADCMPCR

S12ADFa

S12AD1 A/D Comparison Function Window A Extended Input ADCMPANSE

Select Register

R

8

2, 3 PCLKB

2 ICLK

0008 9193h

0008 9194h

0008 9196h

0008 9198h

0008 919Ah

0008 919Ch

0008 919Eh

0008 91A0h

0008 91A2h

0008 91A4h

0008 91A6h

0008 91A8h

S12AD1 A/D Comparison Function Window A Extended Input ADCMPLER

Comparison Condition Setting Register

S12ADFa

16

8

16

8

S12AD1 A/D Comparison Function Window A Channel Select ADCMPANSR

Register 0

0

S12AD1 A/D Comparison Function Window A Channel Select ADCMPANSR

Register 1

1

S12AD1 A/D Comparison Function Window A Comparison

Condition Setting Register 0

ADCMPLR0

S12AD1 A/D Comparison Function Window A Comparison

Condition Setting Register 1

ADCMPLR1

ADCMPDR0

ADCMPDR1

S12AD1 A/D Comparison Function Window A Lower Level

Setting Register

S12AD1 A/D Comparison Function Window A Upper Level

Setting Register

S12AD1 A/D Comparison Function Window A Channel Status ADCMPSR0

Register 0

S12AD1 A/D Comparison Function Window A Channel Status ADCMPSR1

Register 1

S12AD1 A/D Comparison Function Window A Extended Input ADCMPSER

Channel Status Register

8

S12AD1 A/D Comparison Function Window B Channel Select ADCMPBNS

Register

R

16

8

16

8

S12AD1 A/D Comparison Function Window B Lower Level

Setting Register

ADWINLLB

0008 91AAh S12AD1 A/D Comparison Function Window B Upper Level

Setting Register

ADWINULB

0008 91ACh S12AD1 A/D Comparison Function Window B Channel Status ADCMPBSR

Register

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 91D4h

0008 91D6h

0008 91D8h

0008 91D9h

S12AD1 A/D Channel Select Register C0

ADANSC0

ADANSC1

ADGCEXCR

ADGCTRGR

ADSSTRL

ADSSTRT

ADSSTRO

ADSSTR0

ADSSTR1

ADSSTR2

ADSSTR3

ADSSTR4

ADSSTR5

ADSSTR6

ADSSTR7

ADSSTR8

ADSSTR9

S12ADFa

S12AD1 A/D Channel Select Register C1

S12AD1 A/D Group C Extended Input Control Register

S12AD1 A/D Group C Trigger Select Register

8

0008 91DDh S12AD1 A/D Sampling State Register L

0008 91DEh S12AD1 A/D Sampling State Register T

0008 91DFh S12AD1 A/D Sampling State Register O

8

0008 91E0h

0008 91E1h

0008 91E2h

0008 91E3h

0008 91E4h

0008 91E5h

0008 91E6h

0008 91E7h

0008 91E8h

0008 91E9h

S12AD1 A/D Sampling State Register 0

S12AD1 A/D Sampling State Register 1

S12AD1 A/D Sampling State Register 2

S12AD1 A/D Sampling State Register 3

S12AD1 A/D Sampling State Register 4

S12AD1 A/D Sampling State Register 5

S12AD1 A/D Sampling State Register 6

S12AD1 A/D Sampling State Register 7

S12AD1 A/D Sampling State Register 8

S12AD1 A/D Sampling State Register 9

8

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 113 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (21 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

S12ADFa

QSPI

8

2, 3 PCLKB

4, 5 PCLKB

2 ICLK

0008 91EAh S12AD1 A/D Sampling State Register 10

0008 91EBh S12AD1 A/D Sampling State Register 11

0008 91ECh S12AD1 A/D Sampling State Register 12

0008 91EDh S12AD1 A/D Sampling State Register 13

0008 91EEh S12AD1 A/D Sampling State Register 14

ADSSTR10

ADSSTR11

ADSSTR12

ADSSTR13

ADSSTR14

ADSSTR15

SPCR

2 ICLK

8

2 ICLK

8

2 ICLK

8

2 ICLK

0008 91EFh

0008 9E00h

0008 9E01h

0008 9E02h

0008 9E03h

0008 9E04h

S12AD1 A/D Sampling State Register 15

8

2, 3 ICLK

QSPI

QSPI Control Register

8

QSPI Slave Select Polarity Register

QSPI Pin Control Register

QSPI Status Register

SSLP

QSPI

8

SPPCR

QSPI

8

SPSR

QSPI

32

8, 16,

32

QSPI Data Register

SPDR

QSPI

8

4, 5 PCLKB

2, 3 ICLK

0008 9E08h

0008 9E09h

QSPI

QSPI Sequence Control Register

QSPI Sequence Status Register

QSPI Bit Rate Register

SPSCR

SPSSR

SPBR

QSPI

8

0008 9E0Ah QSPI

0008 9E0Bh QSPI

0008 9E0Ch QSPI

0008 9E0Dh QSPI

0008 9E0Eh QSPI

8

QSPI Data Control Register

SPDCR

SPCKD

SSLND

SPND

8

QSPI Clock Delay Register

8

QSPI Slave Select Negation Delay Register

QSPI Next-Access Delay Register

QSPI Command Register 0

8

16

8

16

8

0008 9E10h

0008 9E12h

0008 9E14h

0008 9E16h

0008 9E18h

QSPI

SPCMD0

SPCMD1

SPCMD2

SPCMD3

SPBFCR

SPBDCR

QSPI Command Register 1

QSPI Command Register 2

QSPI Command Register 3

QSPI Buffer Control Register

QSPI Buffer Data Count Set Register

16

32

16

32

0008 9E1Ah QSPI

0008 9E1Ch QSPI

QSPI Transfer Data Length Multiplier Setting Register SPBMUL0

0

32

8

32

8

4, 5 PCLKB

2, 3 PCLKB

2, 3 ICLK

2 ICLK

0008 9E20h

0008 9E24h

0008 9E28h

0008 A000h

QSPI

SCI0

QSPI Transfer Data Length Multiplier Setting Register SPBMUL1

1

QSPI

QSPI Transfer Data Length Multiplier Setting Register SPBMUL2

2

QSPI Transfer Data Length Multiplier Setting Register SPBMUL3

3

Serial Mode Register

SMR

BRR

SCR

TDR

SSR

RDR

SCIg,

SCIh,

SCIi

8

2, 3 PCLKB

2 ICLK

0008 A000h

0008 A001h

0008 A002h

0008 A003h

0008 A004h

0008 A005h

SMCI0 Serial Mode Register

SCIg,

SCIh,

SCIi

SCI0

Bit Rate Register

SCIg,

SCIh,

SCIi

Serial Control Register

SCIg,

SCIh,

SCIi

SMCI0 Serial Control Register

SCIg,

SCIh,

SCIi

SCI0

Transmit Data Register

Serial Status Register

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

SMCI0 Serial Status Register

SCIg,

SCIh,

SCIi

SCI0

Receive Data Register

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 114 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (22 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A006h

SCI0

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

8

2 ICLK

0008 A006h

0008 A007h

0008 A008h

0008 A009h

SMCI0 Smart Card Mode Register

SCIg,

SCIh,

SCIi

8

SCI0

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

8

0008 A00Ah SCI0

0008 A00Bh SCI0

0008 A00Ch SCI0

0008 A00Dh SCI0

0008 A00Eh SCI0

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

8

I C Status Register

SCIg,

SCIh,

SCIi

8

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

SCIg,

SCIh,

SCIi

8

0008 A00Fh

SCI0

SCIg,

SCIh,

SCIi

16

8

16

8

0008 A00Eh SCI0

SCIg,

SCIh,

SCIi

0008 A010h

0008 A011h

0008 A010h

0008 A012h

0008 A020h

0008 A021h

0008 A022h

0008 A023h

0008 A024h

SCI0

SCI1

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

8

SMCI1 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

8

SCI1

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

8

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SMCI1 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SCI1

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

8

SSR

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 115 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (23 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A024h

SMCI1 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

8

2 ICLK

0008 A025h

0008 A026h

0008 A027h

0008 A028h

0008 A029h

SCI1

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

8

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

8

SMCI1 Smart Card Mode Register

SCIg,

SCIh,

SCIi

8

SCI1

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

8

0008 A02Ah SCI1

0008 A02Bh SCI1

0008 A02Ch SCI1

0008 A02Dh SCI1

0008 A02Eh SCI1

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

8

I C Status Register

SCIg,

SCIh,

SCIi

8

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

SCIg,

SCIh,

SCIi

8

0008 A02Fh

SCI1

SCIg,

SCIh,

SCIi

16

8

16

8

0008 A02Eh SCI1

SCIg,

SCIh,

SCIi

0008 A030h

0008 A031h

0008 A030h

0008 A032h

0008 A040h

0008 A041h

0008 A042h

SCI1

SCI2

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

8

SMCI2 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

8

SCI2

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

8

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SMCI2 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 116 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (24 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A043h

SCI2

Transmit Data Register

TDR

SCIg,

SCIh,

SCIi

8

2 ICLK

0008 A044h

0008 A045h

0008 A046h

0008 A047h

0008 A048h

0008 A049h

SCI2

Serial Status Register

SSR

SCIg,

SCIh,

SCIi

8

SMCI2 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

8

SCI2

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

8

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

8

SMCI2 Smart Card Mode Register

SCIg,

SCIh,

SCIi

8

SCI2

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

8

0008 A04Ah SCI2

0008 A04Bh SCI2

0008 A04Ch SCI2

0008 A04Dh SCI2

0008 A04Eh SCI2

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

8

I C Status Register

SCIg,

SCIh,

SCIi

8

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

SCIg,

SCIh,

SCIi

8

0008 A04Fh

SCI2

SCIg,

SCIh,

SCIi

16

8

16

8

0008 A04Eh SCI2

SCIg,

SCIh,

SCIi

0008 A050h

0008 A051h

0008 A050h

0008 A052h

0008 A060h

0008 A061h

SCI2

SCI3

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

8

SMCI3 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

8

SCI3

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 117 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (25 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A062h

SCI3

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

2 ICLK

0008 A062h

0008 A063h

0008 A064h

0008 A065h

0008 A066h

0008 A067h

0008 A068h

0008 A069h

SMCI3 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SCI3

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

8

SSR

SCIg,

SCIh,

SCIi

8

SMCI3 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

8

SCI3

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

8

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

8

SMCI3 Smart Card Mode Register

SCIg,

SCIh,

SCIi

8

SCI3

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

8

0008 A06Ah SCI3

0008 A06Bh SCI3

0008 A06Ch SCI3

0008 A06Dh SCI3

0008 A06Eh SCI3

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

8

I C Status Register

SCIg,

SCIh,

SCIi

8

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

SCIg,

SCIh,

SCIi

8

0008 A06Fh

SCI3

SCIg,

SCIh,

SCIi

16

8

16

8

0008 A06Eh SCI3

SCIg,

SCIh,

SCIi

0008 A070h

0008 A071h

0008 A070h

0008 A072h

0008 A080h

SCI3

SCI4

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 118 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (26 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2 ICLK

0008 A080h

SMCI4 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

8

2 ICLK

0008 A081h

0008 A082h

0008 A083h

0008 A084h

0008 A085h

0008 A086h

0008 A087h

0008 A088h

0008 A089h

SCI4

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

8

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SMCI4 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SCI4

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

8

SSR

SCIg,

SCIh,

SCIi

8

SMCI4 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

8

SCI4

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

8

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

8

SMCI4 Smart Card Mode Register

SCIg,

SCIh,

SCIi

8

SCI4

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

8

0008 A08Ah SCI4

0008 A08Bh SCI4

0008 A08Ch SCI4

0008 A08Dh SCI4

0008 A08Eh SCI4

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

8

I C Status Register

SCIg,

SCIh,

SCIi

8

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

SCIg,

SCIh,

SCIi

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

SCIg,

SCIh,

SCIi

8

0008 A08Fh

SCI4

SCIg,

SCIh,

SCIi

16

8

16

8

0008 A08Eh SCI4

SCIg,

SCIh,

SCIi

0008 A090h

0008 A091h

0008 A090h

SCI4

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 119 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (27 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

16

8

16

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A092h

SCI4

Modulation Duty Register

MDDR

SCIg,

SCIh,

SCIi

2 ICLK

0008 A0A0h SCI5

Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

0008 A0A0h SMCI5 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

0008 A0A1h SCI5

0008 A0A2h SCI5

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

0008 A0A2h SMCI5 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

0008 A0A3h SCI5

0008 A0A4h SCI5

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

SSR

SCIg,

SCIh,

SCIi

0008 A0A4h SMCI5 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

0008 A0A5h SCI5

0008 A0A6h SCI5

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

0008 A0A6h SMCI5 Smart Card Mode Register

SCIg,

SCIh,

SCIi

0008 A0A7h SCI5

0008 A0A8h SCI5

0008 A0A9h SCI5

0008 A0AAh SCI5

0008 A0ABh SCI5

0008 A0ACh SCI5

0008 A0ADh SCI5

0008 A0AEh SCI5

0008 A0AFh SCI5

0008 A0AEh SCI5

0008 A0B0h SCI5

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

2

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

I C Status Register

SCIg,

SCIh,

SCIi

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

SCIg,

SCIh,

SCIi

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 120 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (28 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

16

8

16

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A0B1h SCI5

0008 A0B0h SCI5

0008 A0B2h SCI5

0008 A0C0h SCI6

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

2 ICLK

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

0008 A0C0h SMCI6 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

0008 A0C1h SCI6

0008 A0C2h SCI6

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

0008 A0C2h SMCI6 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

0008 A0C3h SCI6

0008 A0C4h SCI6

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

SSR

SCIg,

SCIh,

SCIi

0008 A0C4h SMCI6 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

0008 A0C5h SCI6

0008 A0C6h SCI6

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

0008 A0C6h SMCI6 Smart Card Mode Register

SCIg,

SCIh,

SCIi

0008 A0C7h SCI6

0008 A0C8h SCI6

0008 A0C9h SCI6

0008 A0CAh SCI6

0008 A0CBh SCI6

0008 A0CCh SCI6

0008 A0CDh SCI6

0008 A0CEh SCI6

0008 A0CFh SCI6

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

2

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

I C Status Register

SCIg,

SCIh,

SCIi

SPI Mode Register

SPMR

TDRH

TDRL

SCIg,

SCIh,

SCIi

Transmit Data Register H

Transmit Data Register L

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 121 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (29 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

16

8

16

8

16

8

16

8

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A0CEh SCI6

0008 A0D0h SCI6

0008 A0D1h SCI6

0008 A0D0h SCI6

0008 A0D2h SCI6

0008 A0E0h SCI7

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

TDRHL

RDRH

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

2 ICLK

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

0008 A0E0h SMCI7 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

0008 A0E1h SCI7

0008 A0E2h SCI7

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

0008 A0E2h SMCI7 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

0008 A0E3h SCI7

0008 A0E4h SCI7

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

SSR

SCIg,

SCIh,

SCIi

0008 A0E4h SMCI7 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

0008 A0E5h SCI7

0008 A0E6h SCI7

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

0008 A0E6h SMCI7 Smart Card Mode Register

SCIg,

SCIh,

SCIi

0008 A0E7h SCI7

0008 A0E8h SCI7

0008 A0E9h SCI7

0008 A0EAh SCI7

0008 A0EBh SCI7

0008 A0ECh SCI7

0008 A0EDh SCI7

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

2

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

I C Status Register

SCIg,

SCIh,

SCIi

SPI Mode Register

SPMR

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 122 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (30 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A0EEh SCI7

0008 A0EFh SCI7

0008 A0EEh SCI7

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

8

2 ICLK

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

0008 A0F0h

0008 A0F1h

0008 A0F0h

0008 A0F2h

0008 A100h

0008 A101h

0008 A102h

0008 A103h

0008 A104h

0008 A105h

0008 A106h

0008 A107h

0008 A108h

0008 A109h

SCI7

SCI8

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

8

SMCI8 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

8

SCI8

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

8

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SMCI8 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SCI8

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

8

SSR

SCIg,

SCIh,

SCIi

8

SMCI8 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

8

SCI8

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

8

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SCIg,

SCIh,

SCIi

8

SMCI8 Smart Card Mode Register

SCIg,

SCIh,

SCIi

8

SCI8

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 1

SCIg,

SCIh,

SCIi

2

8

0008 A10Ah SCI8

0008 A10Bh SCI8

I C Mode Register 2

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 3

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 123 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (31 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

2

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A10Ch SCI8

0008 A10Dh SCI8

0008 A10Eh SCI8

I C Status Register

SISR

SCIg,

SCIh,

SCIi

8

2 ICLK

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

MDDR

SMR

SCIg,

SCIh,

SCIi

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Serial Mode Register

SCIg,

SCIh,

SCIi

8

0008 A10Fh

SCI8

SCIg,

SCIh,

SCIi

16

8

16

8

0008 A10Eh SCI8

SCIg,

SCIh,

SCIi

0008 A110h

0008 A111h

0008 A110h

0008 A112h

0008 A120h

0008 A121h

0008 A122h

0008 A123h

0008 A124h

0008 A125h

0008 A126h

0008 A127h

0008 A128h

0008 A129h

SCI8

SCI9

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

8

SMCI9 Serial Mode Register

SMR

SCIg,

SCIh,

SCIi

8

SCI9

Bit Rate Register

BRR

SCIg,

SCIh,

SCIi

8

Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SMCI9 Serial Control Register

SCR

SCIg,

SCIh,

SCIi

8

SCI9

Transmit Data Register

Serial Status Register

TDR

SCIg,

SCIh,

SCIi

8

SSR

SCIg,

SCIh,

SCIi

8

SMCI9 Serial Status Register

SSR

SCIg,

SCIh,

SCIi

8

SCI9

Receive Data Register

RDR

SCIg,

SCIh,

SCIi

8

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SCIg,

SCIh,

SCIi

8

SMCI9 Smart Card Mode Register

SCIg,

SCIh,

SCIi

8

SCI9

Serial Extended Mode Register

Noise Filter Setting Register

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

2

8

I C Mode Register 1

SCIg,

SCIh,

SCIi

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 124 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (32 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

2

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 A12Ah SCI9

0008 A12Bh SCI9

0008 A12Ch SCI9

0008 A12Dh SCI9

0008 A12Eh SCI9

I C Mode Register 2

SIMR2

SIMR3

SISR

SCIg,

SCIh,

SCIi

2

8

2 ICLK

I C Mode Register 3

SCIg,

SCIh,

SCIi

2

8

I C Status Register

SCIg,

SCIh,

SCIi

8

SPI Mode Register

SPMR

TDRH

TDRL

SCIg,

SCIh,

SCIi

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

SCIg,

SCIh,

SCIi

8

0008 A12Fh

SCI9

SCIg,

SCIh,

SCIi

16

8

16

8

0008 A12Eh SCI9

TDRHL

RDRH

RDRL

RDRHL

MDDR

SCIg,

SCIh,

SCIi

0008 A130h

0008 A131h

0008 A130h

0008 A132h

SCI9

SCIg,

SCIh,

SCIi

8

SCIg,

SCIh,

SCIi

16

8

16

8

SCIg,

SCIh,

SCIi

SCIg,

SCIh,

SCIi

32

8

32

8

2, 3 PCLKB

2 ICLK

0008 AC00h SDHI

0008 AC08h SDHI

0008 AC10h SDHI

0008 AC14h SDHI

0008 AC18h SDHI

0008 AC20h SDHI

0008 AC28h SDHI

0008 AC30h SDHI

0008 AC38h SDHI

0008 AC3Ch SDHI

0008 AC40h SDHI

0008 AC44h SDHI

0008 AC48h SDHI

0008 AC4Ch SDHI

0008 AC50h SDHI

0008 AC58h SDHI

0008 AC5Ch SDHI

0008 AC60h SDHI

0008 AC68h SDHI

0008 AC6Ch SDHI

0008 AC70h SDHI

0008 ADB0h SDHI

0008 ADC0h SDHI

0008 ADC4h SDHI

0008 ADE0h SDHI

Command Register

SDCMD

SDHI

CAC

Argument Register

SDARG

Data Stop Register

SDSTOP

SDBLKCNT

SDRSP10

SDRSP32

SDRSP54

SDRSP76

SDSTS1

SDSTS2

SDIMSK1

SDIMSK2

SDCLKCR

SDSIZE

Block Count Register

Response Register 10

Response Register 32

Response Register 54

Response Register 76

SD Status Register 1

SD Status Register 2

SD Interrupt Mask Register 1

SD Interrupt Mask Register 2

SDHI Clock Control Register

Transfer Data Size Register

Card Access Option Register

SD Error Status Register 1

SD Error Status Register 2

SD Buffer Register

SDOPT

SDERSTS1

SDERSTS2

SDBUFR

SDIOMD

SDIOSTS

SDIOIMSK

SDDMAEN

SDRST

SDIO Mode Control Register

SDIO Status Register

SDIO Interrupt Mask Register

DMA Transfer Enable Register

SDHI Software Reset Register

Version Register

SDVER

Swap Control Register

CAC Control Register 0

SDSWAP

CACR0

0008 B000h

CAC

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 125 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (33 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

CAC

DOC

ELC

8

2, 3 PCLKB

2 ICLK

0008 B001h

0008 B002h

0008 B003h

0008 B004h

0008 B006h

0008 B008h

CAC

CAC Control Register 1

CACR1

CACR2

CAICR

CASTR

CAULVR

CALLVR

CACNTBR

DOCR

2 ICLK

CAC Control Register 2

8

CAC Interrupt Request Enable Register

CAC Status Register

8

16

8

16

8

CAC Upper-Limit Value Setting Register

CAC Lower-Limit Value Setting Register

CAC Counter Buffer Register

DOC Control Register

0008 B00Ah CAC

0008 B080h

0008 B082h

0008 B084h

0008 B100h

0008 B101h

0008 B104h

0008 B105h

0008 B108h

DOC

ELC

16

8

16

8

DOC Data Input Register

DODIR

DODSR

ELCR

DOC Data Setting Register

Event Link Control Register

8

Event Link Setting Register 0

Event Link Setting Register 3

Event Link Setting Register 4

Event Link Setting Register 7

Event Link Setting Register 10

Event Link Setting Register 11

Event Link Setting Register 12

Event Link Setting Register 13

Event Link Setting Register 15

Event Link Setting Register 16

Event Link Setting Register 18

Event Link Setting Register 19

Event Link Setting Register 20

Event Link Setting Register 21

Event Link Setting Register 22

Event Link Setting Register 23

Event Link Setting Register 24

Event Link Setting Register 25

Event Link Setting Register 26

Event Link Setting Register 27

Event Link Setting Register 28

Event Link Option Setting Register A

Event Link Option Setting Register B

Event Link Option Setting Register C

Event Link Option Setting Register D

Port Group Setting Register 1

Port Group Setting Register 2

Port Group Control Register 1

Port Group Control Register 2

Port Buffer Register 1

ELSR0

ELSR3

ELSR4

ELSR7

ELSR10

ELSR11

ELSR12

ELSR13

ELSR15

ELSR16

ELSR18

ELSR19

ELSR20

ELSR21

ELSR22

ELSR23

ELSR24

ELSR25

ELSR26

ELSR27

ELSR28

ELOPA

ELOPB

ELOPC

ELOPD

PGR1

8

0008 B10Bh ELC

0008 B10Ch ELC

0008 B10Dh ELC

0008 B10Eh ELC

8

0008 B110h

0008 B111h

0008 B113h

0008 B114h

0008 B115h

0008 B116h

0008 B117h

0008 B118h

0008 B119h

0008 B11Ah

0008 B11Bh

0008 B11Ch

0008 B11Dh

0008 B11Fh

0008 B120h

0008 B121h

0008 B122h

0008 B123h

0008 B124h

0008 B125h

0008 B126h

0008 B127h

0008 B128h

0008 B129h

ELC

8

PGR2

8

PGC1

8

PGC2

8

PDBF1

PDBF2

PEL0

8

Port Buffer Register 2

8

Event Link Port Setting Register 0

Event Link Port Setting Register 1

Event Link Port Setting Register 2

Event Link Port Setting Register 3

Event Link Software Event Generation Register

Event Link Setting Register 33

Event Link Setting Register 35

Event Link Setting Register 36

8

0008 B12Ah ELC

0008 B12Bh ELC

0008 B12Ch ELC

0008 B12Dh ELC

PEL1

8

PEL2

8

PEL3

8

ELSEGR

ELSR33

ELSR35

ELSR36

8

0008 B131h

0008 B133h

0008 B134h

ELC

8

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 126 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (34 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

16

8

16

8

16

8

16

8

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

4, 5 PCLKB

2, 3 PCLKB

2 ICLK

0008 B135h

0008 B136h

ELC

Event Link Setting Register 37

ELSR37

ELSR38

ELSR45

ELOPF

ELOPH

SMR

ELC

2 ICLK

Event Link Setting Register 38

Event Link Setting Register 45

Event Link Option Setting Register F

Event Link Option Setting Register H

Serial Mode Register

ELC

0008 B13Dh ELC

ELC

0008 B13Fh

0008 B141h

0008 B300h

0008 B301h

0008 B302h

0008 B303h

0008 B304h

0008 B305h

0008 B306h

0008 B307h

0008 B308h

0008 B309h

ELC

SCI12

SCIh

SMCI12 Serial Mode Register

SMR

SCI12

Bit Rate Register

BRR

Serial Control Register

SCR

SMCI12 Serial Control Register

SCR

SCI12

Transmit Data Register

Serial Status Register

TDR

SSR

SMCI12 Serial Status Register

SSR

SCI12

Receive Data Register

RDR

Smart Card Mode Register

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

SMCI12 Smart Card Mode Register

SCI12

Serial Extended Mode Register

Noise Filter Setting Register

2

I C Mode Register 1

2

0008 B30Ah SCI12

0008 B30Bh SCI12

0008 B30Ch SCI12

0008 B30Dh SCI12

0008 B30Eh SCI12

I C Mode Register 2

2

I C Mode Register 3

2

I C Status Register

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

RDRH

RDRL

RDRHL

MDDR

ESMER

CR0

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Modulation Duty Register

Extended Serial Module Enable Register

Control Register 0

0008 B30Fh

SCI12

0008 B30Eh SCI12

0008 B310h

0008 B311h

0008 B310h

0008 B312h

0008 B320h

0008 B321h

0008 B322h

0008 B323h

0008 B324h

0008 B325h

0008 B326h

0008 B327h

0008 B328h

0008 B329h

SCI12

Control Register 1

CR1

Control Register 2

CR2

Control Register 3

CR3

Port Control Register

PCR

Interrupt Control Register

Status Register

ICR

STR

Status Clear Register

STCR

CF0DR

CF0CR

CF0RR

PCF1DR

SCF1DR

CF1CR

CF1RR

TCR

Control Field 0 Data Register

Control Field 0 Compare Enable Register

Control Field 0 Receive Data Register

Primary Control Field 1 Data Register

Secondary Control Field 1 Data Register

Control Field 1 Compare Enable Register

Control Field 1 Receive Data Register

Timer Control Register

0008 B32Ah SCI12

0008 B32Bh SCI12

0008 B32Ch SCI12

0008 B32Dh SCI12

0008 B32Eh SCI12

0008 B32Fh

0008 B330h

0008 B331h

0008 B332h

0008 B333h

SCI12

Timer Mode Register

TMR

Timer Prescaler Register

Timer Count Register

TPRE

TCNT

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 127 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (35 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

I/O Ports

8

2, 3 PCLKB

2 ICLK

0008 C000h

0008 C001h

0008 C002h

0008 C003h

0008 C004h

0008 C005h

0008 C006h

0008 C007h

0008 C008h

0008 C009h

PORT0 Port Direction Register

PORT1 Port Direction Register

PORT2 Port Direction Register

PORT3 Port Direction Register

PORT4 Port Direction Register

PORT5 Port Direction Register

PORT6 Port Direction Register

PORT7 Port Direction Register

PORT8 Port Direction Register

PORT9 Port Direction Register

PDR

2 ICLK

PDR

0008 C00Ah PORTA Port Direction Register

0008 C00Bh PORTB Port Direction Register

0008 C00Ch PORTC Port Direction Register

0008 C00Dh PORTD Port Direction Register

0008 C00Eh PORTE Port Direction Register

0008 C00Fh PORTF Port Direction Register

PDR

0008 C010h

0008 C012h

0008 C020h

0008 C021h

0008 C022h

0008 C023h

0008 C024h

0008 C025h

0008 C026h

0008 C027h

0008 C028h

0008 C029h

PORTG Port Direction Register

PORTJ Port Direction Register

PORT0 Port Output Data Register

PORT1 Port Output Data Register

PORT2 Port Output Data Register

PORT3 Port Output Data Register

PORT4 Port Output Data Register

PORT5 Port Output Data Register

PORT6 Port Output Data Register

PORT7 Port Output Data Register

PORT8 Port Output Data Register

PORT9 Port Output Data Register

PDR

PODR

PIDR

0008 C02Ah PORTA Port Output Data Register

0008 C02Bh PORTB Port Output Data Register

0008 C02Ch PORTC Port Output Data Register

0008 C02Dh PORTD Port Output Data Register

0008 C02Eh PORTE Port Output Data Register

0008 C02Fh PORTF Port Output Data Register

0008 C030h

0008 C032h

0008 C040h

0008 C041h

0008 C042h

0008 C043h

0008 C044h

0008 C045h

0008 C046h

0008 C047h

0008 C048h

0008 C049h

PORTG Port Output Data Register

PORTJ Port Output Data Register

PORT0 Port Input Register

PORT1 Port Input Register

PORT2 Port Input Register

PORT3 Port Input Register

PORT4 Port Input Register

PORT5 Port Input Register

PORT6 Port Input Register

PORT7 Port Input Register

PORT8 Port Input Register

PORT9 Port Input Register

0008 C04Ah PORTA Port Input Register

0008 C04Bh PORTB Port Input Register

0008 C04Ch PORTC Port Input Register

0008 C04Dh PORTD Port Input Register

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 128 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (36 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

I/O Ports

8

2, 3 PCLKB

2 ICLK

0008 C04Eh PORTE Port Input Register

0008 C04Fh PORTF Port Input Register

PIDR

PMR

2 ICLK

0008 C050h

0008 C052h

0008 C060h

0008 C061h

0008 C062h

0008 C063h

0008 C064h

0008 C065h

0008 C066h

0008 C067h

0008 C068h

0008 C069h

PORTG Port Input Register

PORTJ Port Input Register

PORT0 Port Mode Register

PORT1 Port Mode Register

PORT2 Port Mode Register

PORT3 Port Mode Register

PORT4 Port Mode Register

PORT5 Port Mode Register

PORT6 Port Mode Register

PORT7 Port Mode Register

PORT8 Port Mode Register

PORT9 Port Mode Register

PMR

0008 C06Ah PORTA Port Mode Register

0008 C06Bh PORTB Port Mode Register

0008 C06Ch PORTC Port Mode Register

0008 C06Dh PORTD Port Mode Register

0008 C06Eh PORTE Port Mode Register

0008 C06Fh PORTF Port Mode Register

PMR

0008 C070h

0008 C072h

0008 C080h

0008 C081h

0008 C082h

0008 C083h

0008 C084h

0008 C085h

0008 C086h

0008 C087h

0008 C088h

0008 C089h

PORTG Port Mode Register

PMR

PORTJ Port Mode Register

PMR

PORT0 Open-Drain Control Register 0

PORT0 Open-Drain Control Register 1

PORT1 Open-Drain Control Register 0

PORT1 Open-Drain Control Register 1

PORT2 Open-Drain Control Register 0

PORT2 Open-Drain Control Register 1

PORT3 Open-Drain Control Register 0

PORT3 Open-Drain Control Register 1

PORT4 Open-Drain Control Register 0

PORT4 Open-Drain Control Register 1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

0008 C08Ah PORT5 Open-Drain Control Register 0

0008 C08Bh PORT5 Open-Drain Control Register 1

0008 C08Ch PORT6 Open-Drain Control Register 0

0008 C08Dh PORT6 Open-Drain Control Register 1

0008 C08Eh PORT7 Open-Drain Control Register 0

0008 C08Fh PORT7 Open-Drain Control Register 1

0008 C090h

0008 C091h

0008 C092h

0008 C093h

0008 C094h

0008 C095h

0008 C096h

0008 C097h

0008 C098h

0008 C099h

PORT8 Open-Drain Control Register 0

PORT8 Open-Drain Control Register 1

PORT9 Open-Drain Control Register 0

PORT9 Open-Drain Control Register 1

PORTA Open-Drain Control Register 0

PORTA Open-Drain Control Register 1

PORTB Open-Drain Control Register 0

PORTB Open-Drain Control Register 1

PORTC Open-Drain Control Register 0

PORTC Open-Drain Control Register 1

0008 C09Ah PORTD Open-Drain Control Register 0

0008 C09Bh PORTD Open-Drain Control Register 1

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 129 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (37 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

I/O Ports

MPC

8

2, 3 PCLKB

2 ICLK

0008 C09Ch PORTE Open-Drain Control Register 0

0008 C09Dh PORTE Open-Drain Control Register 1

0008 C09Eh PORTF Open-Drain Control Register 0

0008 C09Fh PORTF Open-Drain Control Register 1

0008 C0A0h PORTG Open-Drain Control Register 0

0008 C0A1h PORTG Open-Drain Control Register 1

0008 C0A4h PORTJ Open-Drain Control Register 0

0008 C0A5h PORTJ Open-Drain Control Register 1

0008 C0C0h PORT0 Pull-Up Resistor Control Register

0008 C0C1h PORT1 Pull-Up Resistor Control Register

0008 C0C2h PORT2 Pull-Up Resistor Control Register

0008 C0C3h PORT3 Pull-Up Resistor Control Register

0008 C0C4h PORT4 Pull-Up Resistor Control Register

0008 C0C5h PORT5 Pull-Up Resistor Control Register

0008 C0C6h PORT6 Pull-Up Resistor Control Register

0008 C0C7h PORT7 Pull-Up Resistor Control Register

0008 C0C8h PORT8 Pull-Up Resistor Control Register

0008 C0C9h PORT9 Pull-Up Resistor Control Register

0008 C0CAh PORTA Pull-Up Resistor Control Register

0008 C0CBh PORTB Pull-Up Resistor Control Register

0008 C0CCh PORTC Pull-Up Resistor Control Register

0008 C0CDh PORTD Pull-Up Resistor Control Register

0008 C0CEh PORTE Pull-Up Resistor Control Register

0008 C0CFh PORTF Pull-Up Resistor Control Register

0008 C0D0h PORTG Pull-Up Resistor Control Register

0008 C0D2h PORTJ Pull-Up Resistor Control Register

0008 C0E0h PORT0 Drive Capacity Control Register

0008 C0E1h PORT1 Drive Capacity Control Register

0008 C0E2h PORT2 Drive Capacity Control Register

0008 C0E5h PORT5 Drive Capacity Control Register

0008 C0E7h PORT7 Drive Capacity Control Register

0008 C0E8h PORT8 Drive Capacity Control Register

0008 C0E9h PORT9 Drive Capacity Control Register

0008 C0EAh PORTA Drive Capacity Control Register

0008 C0EBh PORTB Drive Capacity Control Register

0008 C0ECh PORTC Drive Capacity Control Register

0008 C0EDh PORTD Drive Capacity Control Register

0008 C0EEh PORTE Drive Capacity Control Register

0008 C0F0h PORTG Drive Capacity Control Register

0008 C0F2h PORTJ Drive Capacity Control Register

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

ODR0

ODR1

PCR

2 ICLK

PCR

DSCR

PFCSE

PFCSS0

PFCSS1

PFAOE0

PFAOE1

PFBCR0

PFBCR1

PFBCR2

PFBCR3

PFENET

0008 C100h

0008 C102h

0008 C103h

0008 C104h

0008 C105h

0008 C106h

0008 C107h

0008 C108h

0008 C109h

MPC

CS Output Enable Register

CS Output Pin Select Register 0

CS Output Pin Select Register 1

Address Output Enable Register 0

Address Output Enable Register 1

External Bus Control Register 0

External Bus Control Register 1

External Bus Control Register 2

External Bus Control Register 3

Ethernet Control Register

MPC

0008 C10Eh MPC

MPC

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 130 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (38 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

2, 3 PCLKB

2 ICLK

0008 C11Fh

0008 C128h

0008 C129h

MPC

Write-Protect Register

PWPR

MPC

2 ICLK

PORT0 Drive Capacity Control Register 2

PORT1 Drive Capacity Control Register 2

DSCR2

P00PFS

P01PFS

P02PFS

P03PFS

P05PFS

P07PFS

P10PFS

P11PFS

P12PFS

P13PFS

P14PFS

P15PFS

P16PFS

P17PFS

P20PFS

P21PFS

P22PFS

P23PFS

P24PFS

P25PFS

P26PFS

P27PFS

P30PFS

P31PFS

P32PFS

P33PFS

P34PFS

P40PFS

P41PFS

P42PFS

P43PFS

P44PFS

P45PFS

P46PFS

I/O Ports

MPC

0008 C12Ah PORT2 Drive Capacity Control Register 2

0008 C12Bh PORT3 Drive Capacity Control Register 2

0008 C12Dh PORT5 Drive Capacity Control Register 2

0008 C12Fh PORT7 Drive Capacity Control Register 2

0008 C130h

0008 C131h

0008 C132h

0008 C133h

0008 C134h

0008 C135h

0008 C136h

0008 C138h

PORT8 Drive Capacity Control Register 2

PORT9 Drive Capacity Control Register 2

PORTA Drive Capacity Control Register 2

PORTB Drive Capacity Control Register 2

PORTC Drive Capacity Control Register 2

PORTD Drive Capacity Control Register 2

PORTE Drive Capacity Control Register 2

PORTG Drive Capacity Control Register 2

0008 C13Ah PORTJ Drive Capacity Control Register 2

0008 C140h

0008 C141h

0008 C142h

0008 C143h

0008 C145h

0008 C147h

0008 C148h

0008 C149h

MPC

P00 Pin Function Control Register

P01 Pin Function Control Register

P02 Pin Function Control Register

P03 Pin Function Control Register

P05 Pin Function Control Register

P07 Pin Function Control Register

P10 Pin Function Control Register

P11 Pin Function Control Register

P12 Pin Function Control Register

P13 Pin Function Control Register

P14 Pin Function Control Register

P15 Pin Function Control Register

P16 Pin Function Control Register

P17 Pin Function Control Register

P20 Pin Function Control Register

P21 Pin Function Control Register

P22 Pin Function Control Register

P23 Pin Function Control Register

P24 Pin Function Control Register

P25 Pin Function Control Register

P26 Pin Function Control Register

P27 Pin Function Control Register

P30 Pin Function Control Register

P31 Pin Function Control Register

P32 Pin Function Control Register

P33 Pin Function Control Register

P34 Pin Function Control Register

P40 Pin Function Control Register

P41 Pin Function Control Register

P42 Pin Function Control Register

P43 Pin Function Control Register

P44 Pin Function Control Register

P45 Pin Function Control Register

P46 Pin Function Control Register

MPC

0008 C14Ah MPC

0008 C14Bh MPC

0008 C14Ch MPC

0008 C14Dh MPC

0008 C14Eh MPC

0008 C14Fh MPC

MPC

0008 C150h

0008 C151h

0008 C152h

0008 C153h

0008 C154h

0008 C155h

0008 C156h

0008 C157h

0008 C158h

0008 C159h

MPC

0008 C15Ah MPC

0008 C15Bh MPC

0008 C15Ch MPC

MPC

0008 C160h

0008 C161h

0008 C162h

0008 C163h

0008 C164h

0008 C165h

0008 C166h

MPC

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 131 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (39 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

MPC

8

2, 3 PCLKB

2 ICLK

0008 C167h

0008 C168h

0008 C169h

MPC

P47 Pin Function Control Register

P47PFS

P50PFS

P51PFS

P52PFS

P54PFS

P55PFS

P56PFS

P57PFS

P66PFS

P67PFS

P71PFS

P72PFS

P73PFS

P74PFS

P75PFS

P76PFS

P77PFS

P80PFS

P81PFS

P82PFS

P83PFS

P84PFS

P85PFS

P86PFS

P87PFS

P90PFS

P91PFS

P92PFS

P93PFS

PA0PFS

PA1PFS

PA2PFS

PA3PFS

PA4PFS

PA5PFS

PA6PFS

PA7PFS

PB0PFS

PB1PFS

PB2PFS

PB3PFS

PB4PFS

PB5PFS

PB6PFS

PB7PFS

PC0PFS

PC1PFS

PC2PFS

PC3PFS

PC4PFS

2 ICLK

P50 Pin Function Control Register

P51 Pin Function Control Register

P52 Pin Function Control Register

P54 Pin Function Control Register

P55 Pin Function Control Register

P56 Pin Function Control Register

P57 Pin Function Control Register

P66 Pin Function Control Register

P67 Pin Function Control Register

P71 Pin Function Control Register

P72 Pin Function Control Register

P73 Pin Function Control Register

P74 Pin Function Control Register

P75 Pin Function Control Register

P76 Pin Function Control Register

P77 Pin Function Control Register

P80 Pin Function Control Register

P81 Pin Function Control Register

P82 Pin Function Control Register

P83 Pin Function Control Register

P84 Pin Function Control Register

P85 Pin Function Control Register

P86 Pin Function Control Register

P87 Pin Function Control Register

P90 Pin Function Control Register

P91 Pin Function Control Register

P92 Pin Function Control Register

P93 Pin Function Control Register

PA0 Pin Function Control Register

PA1 Pin Function Control Register

PA2 Pin Function Control Register

PA3 Pin Function Control Register

PA4 Pin Function Control Register

PA5 Pin Function Control Register

PA6 Pin Function Control Register

PA7 Pin Function Control Register

PB0 Pin Function Control Register

PB1 Pin Function Control Register

PB2 Pin Function Control Register

PB3 Pin Function Control Register

PB4 Pin Function Control Register

PB5 Pin Function Control Register

PB6 Pin Function Control Register

PB7 Pin Function Control Register

PC0 Pin Function Control Register

PC1 Pin Function Control Register

PC2 Pin Function Control Register

PC3 Pin Function Control Register

PC4 Pin Function Control Register

0008 C16Ah MPC

0008 C16Ch MPC

0008 C16Dh MPC

0008 C16Eh MPC

0008 C16Fh MPC

0008 C176h

0008 C177h

0008 C179h

MPC

0008 C17Ah MPC

0008 C17Bh MPC

0008 C17Ch MPC

0008 C17Dh MPC

0008 C17Eh MPC

0008 C17Fh MPC

0008 C180h

0008 C181h

0008 C182h

0008 C183h

0008 C184h

0008 C185h

0008 C186h

0008 C187h

0008 C188h

0008 C189h

MPC

0008 C18Ah MPC

0008 C18Bh MPC

0008 C190h

0008 C191h

0008 C192h

0008 C193h

0008 C194h

0008 C195h

0008 C196h

0008 C197h

0008 C198h

0008 C199h

MPC

0008 C19Ah MPC

0008 C19Bh MPC

0008 C19Ch MPC

0008 C19Dh MPC

0008 C19Eh MPC

0008 C19Fh MPC

0008 C1A0h MPC

0008 C1A1h MPC

0008 C1A2h MPC

0008 C1A3h MPC

0008 C1A4h MPC

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 132 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (40 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

MPC

8

2, 3 PCLKB

4, 5 PCLKB

2 ICLK

0008 C1A5h MPC

0008 C1A6h MPC

0008 C1A7h MPC

0008 C1A8h MPC

0008 C1A9h MPC

0008 C1AAh MPC

0008 C1ABh MPC

0008 C1ACh MPC

0008 C1ADh MPC

0008 C1AEh MPC

0008 C1AFh MPC

0008 C1B0h MPC

0008 C1B1h MPC

0008 C1B2h MPC

0008 C1B3h MPC

0008 C1B4h MPC

0008 C1B5h MPC

0008 C1B6h MPC

0008 C1B7h MPC

0008 C1B8h MPC

0008 C1B9h MPC

0008 C1BAh MPC

0008 C1BDh MPC

0008 C1D0h MPC

0008 C1D1h MPC

0008 C1D2h MPC

0008 C1D3h MPC

0008 C1D5h MPC

PC5 Pin Function Control Register

PC6 Pin Function Control Register

PC7 Pin Function Control Register

PD0 Pin Function Control Register

PD1 Pin Function Control Register

PD2 Pin Function Control Register

PD3 Pin Function Control Register

PD4 Pin Function Control Register

PD5 Pin Function Control Register

PD6 Pin Function Control Register

PD7 Pin Function Control Register

PE0 Pin Function Control Register

PE1 Pin Function Control Register

PE2 Pin Function Control Register

PE3 Pin Function Control Register

PE4 Pin Function Control Register

PE5 Pin Function Control Register

PE6 Pin Function Control Register

PE7 Pin Function Control Register

PF0 Pin Function Control Register

PF1 Pin Function Control Register

PF2 Pin Function Control Register

PF5 Pin Function Control Register

PJ0 Pin Function Control Register

PJ1 Pin Function Control Register

PJ2 Pin Function Control Register

PJ3 Pin Function Control Register

PJ5 Pin Function Control Register

PC5PFS

PC6PFS

PC7PFS

PD0PFS

PD1PFS

PD2PFS

PD3PFS

PD4PFS

PD5PFS

PD6PFS

PD7PFS

PE0PFS

PE1PFS

PE2PFS

PE3PFS

PE4PFS

PE5PFS

PE6PFS

PE7PFS

PF0PFS

PF1PFS

PF2PFS

PF5PFS

PJ0PFS

PJ1PFS

PJ2PFS

PJ3PFS

PJ5PFS

DPSBYCR

2 ICLK

2, 3 ICLK

0008 C280h

0008 C282h

0008 C283h

0008 C284h

0008 C285h

0008 C286h

0008 C287h

0008 C288h

SYSTE Deep Standby Control Register

M

Low

Power

Consumpt

ion

8

4, 5 PCLKB

2, 3 ICLK

SYSTE Deep Standby Interrupt Enable Register 0

M

DPSIER0

DPSIER1

DPSIER2

DPSIER3

DPSIFR0

DPSIFR1

DPSIFR2

Low

Power

Consumpt

ion

SYSTE Deep Standby Interrupt Enable Register 1

M

Low

Power

Consumpt

ion

SYSTE Deep Standby Interrupt Enable Register 2

M

Low

Power

Consumpt

ion

SYSTE Deep Standby Interrupt Enable Register 3

M

Low

Power

Consumpt

ion

SYSTE Deep Standby Interrupt Flag Register 0

M

Low

Power

Consumpt

ion

SYSTE Deep Standby Interrupt Flag Register 1

M

Low

Power

Consumpt

ion

SYSTE Deep Standby Interrupt Flag Register 2

M

Low

Power

Consumpt

ion

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 133 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (41 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

4, 5 PCLKB

2, 3 ICLK

0008 C289h

SYSTE Deep Standby Interrupt Flag Register 3

M

DPSIFR3

Low

Power

Consumpt

ion

2, 3 ICLK

0008 C28Ah SYSTE Deep Standby Interrupt Edge Register 0

M

DPSIEGR0

DPSIEGR1

DPSIEGR2

DPSIEGR3

Low

Power

Consumpt

ion

0008 C28Bh SYSTE Deep Standby Interrupt Edge Register 1

M

Low

Power

Consumpt

ion

0008 C28Ch SYSTE Deep Standby Interrupt Edge Register 2

M

Low

Power

Consumpt

ion

0008 C28Dh SYSTE Deep Standby Interrupt Edge Register 3

M

Low

Power

Consumpt

ion

8

4, 5 PCLKB

2, 3 ICLK

0008 C290h

0008 C291h

0008 C293h

SYSTE Reset Status Register 0

M

RSTSR0

RSTSR1

MOFCR

Resets

SYSTE Reset Status Register 1

M

Resets

SYSTE Main Clock Oscillator Forced Oscillation Control

Clock

M

Register

Generatio

n Circuit

8

4, 5 PCLKB

2, 3 ICLK

0008 C294h

SYSTE High-Speed On-Chip Oscillator Power Supply Control HOCOPCR

Register

Clock

Generatio

n Circuit

M

8

2 ICLK

0008 C296h

0008 C297h

FLASH Flash P/E Protect Register

FWEPROR

LVCMPCR

Flash

LVDA

4, 5 PCLKB

2, 3 ICLK

SYSTE Voltage Monitoring Circuit Control Register

M

8

0008 C298h

SYSTE Voltage Detection Level Select Register

M

LVDLVLR

LVD1CR0

LVD2CR0

LVDA

0008 C29Ah SYSTE Voltage Monitoring 1 Circuit Control Register 0

M

0008 C29Bh SYSTE Voltage Monitoring 2 Circuit Control Register 0

M

0008 C2A0h SYSTE Deep Standby Backup Register 0 to Deep Standby

to

0008 C2BFh

DPSBKR0 to

DPSBKR31

Low

M

Backup Register 31

Power

Consumpt

ion

8

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 C400h

0008 C402h

0008 C404h

0008 C406h

0008 C408h

RTC

64-Hz Counter

R64CNT

RSECCNT

BCNT0

RTCd

Second Counter

Binary Counter 0

Minute Counter

RMINCNT

BCNT1

Binary Counter 1

Hour Counter

RHRCNT

BCNT2

Binary Counter 2

Day-of-Week Counter

Binary Counter 3

RWKCNT

BCNT3

0008 C40Ah RTC

0008 C40Ch RTC

0008 C40Eh RTC

Date Counter

RDAYCNT

RMONCNT

RYRCNT

RSECAR

BCNT0AR

RMINAR

BCNT1AR

RHRAR

Month Counter

Year Counter

0008 C410h

0008 C412h

0008 C414h

0008 C416h

RTC

Second Alarm Register

Binary Counter 0 Alarm Register

Minute Alarm Register

Binary Counter 1 Alarm Register

Hour Alarm Register

Binary Counter 2 Alarm Register

Day-of-Week Alarm Register

BCNT2AR

RWKAR

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 134 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (42 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

RTCd

POE3a

8

2, 3 PCLKB

2 ICLK

0008 C416h

0008 C418h

RTC

Binary Counter 3 Alarm Register

BCNT3AR

RDAYAR

BCNT0AER

RMONAR

BCNT1AER

RYRAR

2 ICLK

Date Alarm Register

8

Binary Counter 0 Alarm Enable Register

Month Alarm Register

8

0008 C41Ah RTC

0008 C41Ch RTC

0008 C41Eh RTC

8

Binary Counter 1 Alarm Enable Register

Year Alarm Register

16

8

16

8

Binary Counter 2 Alarm Enable Register

Year Alarm Enable Register

Binary Counter 3 Alarm Enable Register

RTC Control Register 1

BCNT2AER

RYRAREN

BCNT3AER

RCR1

8

0008 C422h

0008 C424h

0008 C426h

0008 C428h

RTC

8

RTC Control Register 2

RCR2

8

RTC Control Register 3

RCR3

8

RTC Control Register 4

RCR4

16

8

16

8

0008 C42Ah RTC

0008 C42Ch RTC

0008 C42Eh RTC

Frequency Register H

RFRH

Frequency Register L

RFRL

Time Error Adjustment Register

Time Capture Control Register 0

Time Capture Control Register 1

Time Capture Control Register 2

Second Capture Register 0

BCNT0 Capture Register 0

Minute Capture Register 0

BCNT1 Capture Register 0

Hour Capture Register 0

RADJ

8

0008 C440h

0008 C442h

0008 C444h

0008 C452h

0008 C454h

0008 C456h

RTC

RTCCR0

RTCCR1

RTCCR2

RSECCP0

BCNT0CP0

RMINCP0

BCNT1CP0

RHRCP0

BCNT2CP0

RDAYCP0

BCNT3CP0

RMONCP0

RSECCP1

BCNT0CP1

RMINCP1

BCNT1CP1

RHRCP1

BCNT2CP1

RDAYCP1

BCNT3CP1

RMONCP1

RSECCP2

BCNT0CP2

RMINCP2

BCNT1CP2

RHRCP2

BCNT2CP2

RDAYCP2

BCNT3CP2

RMONCP2

ICSR1

8

BCNT2 Capture Register 0

Date Capture Register 0

8

0008 C45Ah RTC

0008 C45Ch RTC

8

BCNT3 Capture Register 0

Month Capture Register 0

Second Capture Register 1

BCNT0 Capture Register 1

Minute Capture Register 1

BCNT1 Capture Register 1

Hour Capture Register 1

8

0008 C462h

0008 C464h

0008 C466h

RTC

8

BCNT2 Capture Register 1

Date Capture Register 1

8

0008 C46Ah RTC

0008 C46Ch RTC

8

BCNT3 Capture Register 1

Month Capture Register 1

Second Capture Register 2

BCNT0 Capture Register 2

Minute Capture Register 2

BCNT1 Capture Register 2

Hour Capture Register 2

8

0008 C472h

0008 C474h

0008 C476h

RTC

8

BCNT2 Capture Register 2

Date Capture Register 2

8

0008 C47Ah RTC

0008 C47Ch RTC

0008 C4C0h POE3

0008 C4C2h POE3

0008 C4C4h POE3

0008 C4C6h POE3

8

BCNT3 Capture Register 2

Month Capture Register 2

Input Level Control/Status Register 1

Output Level Control/Status Register 1

Input Level Control/Status Register 2

Output Level Control/Status Register 2

8

16

OCSR1

ICSR2

OCSR2

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 135 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (43 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

POE3a

TEMPS

R12DA

CAN

16

8

16

8

2, 3 PCLKB

2 ICLK

0008 C4C8h POE3

0008 C4CAh POE3

0008 C4CBh POE3

0008 C4CCh POE3

0008 C4D0h POE3

0008 C4D2h POE3

0008 C4D6h POE3

0008 C4D8h POE3

0008 C4DAh POE3

0008 C4DCh POE3

0008 C4E4h POE3

0008 C4E5h POE3

0008 C4E6h POE3

0008 C4E7h POE3

0008 C4E8h POE3

0008 C4EAh POE3

Input Level Control/Status Register 3

Software Port Output Enable Register

Port Output Enable Control Register 1

Port Output Enable Control Register 2

Port Output Enable Control Register 4

Port Output Enable Control Register 5

Input Level Control/Status Register 4

Input Level Control/Status Register 5

Active Level Setting Register 1

Input Level Control/Status Register 6

MTU0 Pin Select Register 1

ICSR3

2 ICLK

SPOER

8

POECR1

POECR2

POECR4

POECR5

ICSR4

16

8

16

8

ICSR5

ALR1

ICSR6

M0SELR1

M0SELR2

M3SELR

M4SELR1

M4SELR2

M6SELR

TSCR

8

MTU0 Pin Select Register 2

8

MTU3 Pin Select Register

8

MTU4 Pin Select Register 1

8

MTU4 Pin Select Register 2

8

MTU6 Pin Select Register

8

0008 C500h

TEMPS Temperature Sensor Control Register

8

0008 C5C0h DA

D/A A/D Synchronous Unit Select Register

Mailbox Register 0 to Mailbox Register 31

DAADUSR

MB0 to MB31

128

8, 16,

0009 0200h to CAN0

0009 03FFh

2

32*

32

8, 16,

32

2, 3 PCLKB

2 ICLK

0009 0400h to CAN0

0009 041Fh

Mask Register 0 to Mask Register 7

MKR0 to

MKR7

CAN

32

8

8, 16,

32

2, 3 PCLKB

2 ICLK

0009 0420h

0009 0424h

0009 0428h

0009 042Ch

CAN0

FIFO Received ID Compare Register 0

FIFO Received ID Compare Register 1

Mask Invalid Register

FIDCR0

FIDCR1

MKIVLR

MIER

CAN

8, 16,

32

8, 16,

32

8, 16,

32

Mailbox Interrupt Enable Register

8

0009 0820h to CAN0

0009 083Fh

Message Control Register 0 to Message Control

Register 31

MCTL0 to

MCTL31

16

32

8, 16

2, 3 PCLKB

2 ICLK

0009 0840h

0009 0842h

0009 0844h

CAN0

Control Register

CTLR

STR

CAN

Status Register

8, 16,

32

Bit Configuration Register

BCR

8

2, 3 PCLKB

2 ICLK

0009 0848h

0009 0849h

0009 084Ah

0009 084Bh

0009 084Ch

0009 084Dh

0009 084Eh

0009 084Fh

0009 0850h

0009 0851h

0009 0852h

0009 0853h

0009 0854h

0009 0856h

0009 0858h

CAN0

Receive FIFO Control Register

Receive FIFO Pointer Control Register

Transmit FIFO Control Register

Transmit FIFO Pointer Control Register

Error Interrupt Enable Register

Error Interrupt Factor Judge Register

Receive Error Count Register

Transmit Error Count Register

Error Code Store Register

RFCR

RFPCR

TFCR

TFPCR

EIER

CAN

8

EIFR

8

RECR

TECR

ECSR

CSSR

MSSR

MSMR

TSR

8

Channel Search Support Register

Mailbox Search Status Register

Mailbox Search Mode Register

Time Stamp Register

8

16

8

16

8

Acceptance Filter Support Register

Test Control Register

AFSR

TCR

128

8, 16,

32*

0009 1200h to CAN1

0009 13FFh

Mailbox Register 0 to Mailbox Register 31

MB0 to MB31

2

32

8, 16,

32

2, 3 PCLKB

2 ICLK

0009 1400h to CAN1

0009 141Fh

Mask Register 0 to Mask Register 7

MKR0 to

MKR7

CAN

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 136 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (44 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

32

8

8, 16,

32

2, 3 PCLKB

2 ICLK

0009 1420h

CAN1

FIFO Received ID Compare Register 0

FIDCR0

FIDCR1

MKIVLR

MIER

CAN

8, 16,

32

2 ICLK

0009 1424h

0009 1428h

0009 142Ch

FIFO Received ID Compare Register 1

Mask Invalid Register

CAN

8, 16,

32

8, 16,

32

Mailbox Interrupt Enable Register

8

0009 1820h to CAN1

0009 183Fh

Message Control Register 0 to Message Control

Register 31

MCTL0 to

MCTL31

16

32

8, 16

2, 3 PCLKB

2 ICLK

0009 1840h

0009 1842h

0009 1844h

CAN1

Control Register

CTLR

STR

CAN

Status Register

8, 16,

32

Bit Configuration Register

BCR

8

2, 3 PCLKB

10, 11 PCLKB

7, 8 PCLKB

2 ICLK

0009 1848h

0009 1849h

0009 184Ah

0009 184Bh

0009 184Ch

0009 184Dh

0009 184Eh

0009 184Fh

0009 1850h

0009 1851h

0009 1852h

0009 1853h

0009 1854h

0009 1856h

0009 1858h

0009 4200h

0009 4204h

0009 4208h

0009 4210h

0009 4214h

0009 4218h

0009 421Ch

0009 4220h

0009 4224h

0009 4280h

0009 4284h

0009 4288h

0009 4290h

0009 4294h

0009 4298h

0009 429Ch

0009 42A0h

0009 42A4h

0009 5000h

0009 5004h

0009 5005h

0009 5006h

0009 5007h

0009 5008h

CAN1

Receive FIFO Control Register

Receive FIFO Pointer Control Register

Transmit FIFO Control Register

Transmit FIFO Pointer Control Register

Error Interrupt Enable Register

Error Interrupt Factor Judge Register

Receive Error Count Register

Transmit Error Count Register

Error Code Store Register

RFCR

CAN

RFPCR

CAN

8

2 ICLK

TFCR

CAN

8

2 ICLK

TFPCR

CAN

8

2 ICLK

EIER

CAN

8

2 ICLK

EIFR

CAN

8

2 ICLK

RECR

CAN

8

2 ICLK

TECR

CAN

8

2 ICLK

ECSR

CAN

8

2 ICLK

Channel Search Support Register

Mailbox Search Status Register

Mailbox Search Mode Register

Time Stamp Register

CSSR

CAN

8

2 ICLK

MSSR

CAN

8

2 ICLK

MSMR

CAN

16

8

16

8

2 ICLK

TSR

CAN

2 ICLK

Acceptance Filter Support Register

Test Control Register

AFSR

CAN

2 ICLK

TCR

CAN

16

32

16

32

8

16

32

16

32

8

2 ICLK

CMTW0 Timer Start Register

CMWSTR

CMWCR

CMWIOR

CMWCNT

CMWCOR

CMWICR0

CMWICR1

CMWOCR0

CMWOCR1

CMWSTR

CMWCR

CMWIOR

CMWCNT

CMWCOR

CMWICR0

CMWICR1

CMWOCR0

CMWOCR1

FN1ACCR

INTENCR1

INTSR1

CMTW

SDSI

2 ICLK

CMTW0 Timer Control Register

CMTW0 Timer I/O Control Register

CMTW0 Timer Counter

2 ICLK

CMTW0 Compare Match Constant Register

CMTW0 Input Capture Register 0

CMTW0 Input Capture Register 1

CMTW0 Output Compare Register 0

CMTW0 Output Compare Register 1

CMTW1 Timer Start Register

2 ICLK

CMTW1 Timer Control Register

CMTW1 Timer I/O Control Register

CMTW1 Timer Counter

2 ICLK

CMTW1 Compare Match Constant Register

CMTW1 Input Capture Register 0

CMTW1 Input Capture Register 1

CMTW1 Output Compare Register 0

CMTW1 Output Compare Register 1

2 ICLK

2 to 6 ICLK

2 to 5 ICLK

SDSI

FN1 Access Control Register

Interrupt Enable Control Register 1

Interrupt Status Register 1

SDSI

8

SDSI

8

SD Command Control Register

SD Command Access Address 0 Register

SD Command Access Address 1 Register

SDCMDCR

SDCADD0R

SDCADD1R

SDSI

8

SDSI

8

SDSI

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 137 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (45 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

SDSI

8

7, 8 PCLKB

8, 9 PCLKB

10, 11 PCLKB

2, 3 PCLKB

2 to 5 ICLK

0009 5009h

0009 500Ah

0009 500Bh

0009 500Ch

0009 500Eh

0009 5010h

0009 5100h

0009 5104h

0009 5108h

0009 510Ch

0009 5110h

SDSI

SD Command Access Address 2 Register

SDCADD2R

SDSICR1

DMACR1

BLKCNT

8

2 to 5 ICLK

2 to 6 ICLK

2 ICLK

SDSI Control Register 1

DMA Control Register 1

Block Counter

8

16

32

16

32

Byte Counter

BYTCNT

DMA Transfer Address Register

SDSI Control Register 2

SDSI Control Register 3

Interrupt Enable Control Register 2

Interrupt Status Register 2

DMA Control Register 2

CIS Data Register 0 to 26

DMATRADDR

SDSICR2

SDSICR3

INTENCR2

INTSR2

2 ICLK

DMACR2

2 ICLK

0009 5200h to SDSI

0009 526Bh

CISDATAR0

to 26

32

2, 3 PCLKB

10, 11 PCLKB

2 ICLK

0009 5270h

0009 5274h

0009 5278h

0009 527Ch

0009 5280h

SDSI

FBR Setting Register 1

FBR Setting Register 2

FBR Setting Register 3

FBR Setting Register 4

FBR Setting Register 5

FN1 Data Register 10 to 163

FBR1

FBR2

FBR3

FBR4

FBR5

SDSI

32

2 ICLK

32

2 ICLK

32

2 ICLK

8, 32

2 to 6 ICLK

0009 5800h to SDSI

0009 58FFh

FN1DATAR10

to 163

32

8, 32

10, 11 PCLKB

2 to 6 ICLK

0009 5900h to SDSI

0009 59FFh

FN1 Data Register 20 to 263

FN1 Data Register 30 to 363

FN1DATAR20

to 263

SDSI

0009 5A00h

to

SDSI

FN1DATAR30

to 363

0009 5AFFh

8

7, 8 PCLKB

2 to 5 ICLK

0009 5B00h

0009 5B01h

SDSI

FN1 Interrupt Vector Register

FN1 Interrupt Clear Register

FN1 Data Register 50 to 5255

FN1INTVECR

FN1INTCLRR

SDSI

32

8, 32

0009 5C00h

to

FN1DATAR50

to 5255

0009 5FFFh

16

3, 4 PCLKB

2 ICLK

000A 0000h

000A 0004h

USB0

System Configuration Control Register

System Configuration Status Register 0

SYSCFG

SYSSTS0

USBb

9 PCLKB

or more

Rounded up to the

nearest integer

greater than 1 + 9 ×

(frequency ratio of

1

ICLK/PCLKB)*

16

9 PCLKB

or more

Rounded up to the

nearest integer

000A 0008h

USB0

Device State Control Register 0

DVSTCTR0

USBb

greater than 1 + 9 ×

(frequency ratio of

1

ICLK/PCLKB)*

16

8, 16

16

3, 4 PCLKB

2 ICLK

000A 0014h

000A 0018h

USB0

CFIFO Port Register

CFIFO

USBb

D0FIFO Port Register

D0FIFO

000A 001Ch USB0

D1FIFO Port Register

D1FIFO

000A 0020h

000A 0022h

000A 0028h

USB0

CFIFO Port Select Register

CFIFO Port Control Register

D0FIFO Port Select Register

D0FIFO Port Control Register

D1FIFO Port Select Register

D1FIFO Port Control Register

Interrupt Enable Register 0

CFIFOSEL

CFIFOCTR

D0FIFOSEL

D0FIFOCTR

D1FIFOSEL

D1FIFOCTR

INTENB0

16

000A 002Ah USB0

000A 002Ch USB0

000A 002Eh USB0

16

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

of ICLK/PCLKB)*

000A 0030h

000A 0032h

000A 0036h

000A 0038h

USB0

1

16

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

of ICLK/PCLKB)*

Interrupt Enable Register 1

INTENB1

USBb

1

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

of ICLK/PCLKB)*

BRDY Interrupt Enable Register

NRDY Interrupt Enable Register

BRDYENB

NRDYENB

1

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

of ICLK/PCLKB)*

1

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 138 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (46 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

16

9 PCLKB

or more

Frequency with 1 +

USBb

000A 003Ah USB0

BEMP Interrupt Enable Register

SOF Output Configuration Register

Interrupt Status Register 0

Interrupt Status Register 1

BRDY Interrupt Status Register

NRDY Interrupt Status Register

BEMP Interrupt Status Register

Frame Number Register

BEMPENB

SOFCFG

INTSTS0

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 003Ch USB0

USBb

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 0040h

000A 0042h

000A 0046h

000A 0048h

USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

INTSTS1

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

BRDYSTS

NRDYSTS

BEMPSTS

FRMNUM

DVCHGR

USBADDR

USBREQ

USBVAL

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 004Ah USB0

000A 004Ch USB0

000A 004Eh USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

Device State Change Register

USB Address Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 0050h

000A 0054h

000A 0056h

000A 0058h

USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

USB Request Type Register

USB Request Value Register

USB Request Index Register

USB Request Length Register

DCP Configuration Register

DCP Maximum Packet Size Register

DCP Control Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

USBINDX

USBLENG

DCPCFG

DCPMAXP

DCPCTR

PIPESEL

PIPECFG

PIPEMAXP

PIPEPERI

PIPE1CTR

PIPE2CTR

PIPE3CTR

PIPE4CTR

PIPE5CTR

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 005Ah USB0

000A 005Ch USB0

000A 005Eh USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 0060h

000A 0064h

000A 0068h

USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

Pipe Window Select Register

Pipe Configuration Register

Pipe Maximum Packet Size Register

Pipe Cycle Control Register

PIPE1 Control Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 006Ch USB0

000A 006Eh USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 0070h

000A 0072h

000A 0074h

000A 0076h

000A 0078h

USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

PIPE2 Control Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

PIPE3 Control Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

PIPE4 Control Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

PIPE5 Control Register

1

of ICLK/PCLKB)*

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 139 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (47 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

16

32

16

32

9 PCLKB

or more

Frequency with 1 +

USBb

000A 007Ah USB0

000A 007Ch USB0

000A 007Eh USB0

PIPE6 Control Register

PIPE6CTR

PIPE7CTR

PIPE8CTR

PIPE9CTR

PIPE1TRE

PIPE1TRN

PIPE2TRE

PIPE2TRN

PIPE3TRE

PIPE3TRN

PIPE4TRE

PIPE4TRN

PIPE5TRE

PIPE5TRN

DEVADD0

DEVADD1

DEVADD2

DEVADD3

DEVADD4

DEVADD5

PHYSLEW

DPUSR0R

DPUSR1R

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

PIPE7 Control Register

USBb

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

PIPE8 Control Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 0080h

000A 0090h

000A 0092h

000A 0094h

000A 0096h

000A 0098h

USB0

PIPE9 Control Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

PIPE1 Transaction Counter Enable Register

PIPE1 Transaction Counter Register

PIPE2 Transaction Counter Enable Register

PIPE2 Transaction Counter Register

PIPE3 Transaction Counter Enable Register

PIPE3 Transaction Counter Register

PIPE4 Transaction Counter Enable Register

PIPE4 Transaction Counter Register

PIPE5 Transaction Counter Enable Register

PIPE5 Transaction Counter Register

Device Address 0 Configuration Register

Device Address 1 Configuration Register

Device Address 2 Configuration Register

Device Address 3 Configuration Register

Device Address 4 Configuration Register

Device Address 5 Configuration Register

PHY Cross Point Adjustment Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 009Ah USB0

000A 009Ch USB0

000A 009Eh USB0

000A 00A0h USB0

000A 00A2h USB0

000A 00D0h USB0

000A 00D2h USB0

000A 00D4h USB0

000A 00D6h USB0

000A 00D8h USB0

000A 00DAh USB0

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

000A 00F0h

000A 0400h

000A 0404h

USB0

USB

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

Deep Standby USB Transceiver Control/Pin

Monitoring Register

1

of ICLK/PCLKB)*

9 PCLKB

or more

Frequency with 1 +

9 × (frequency ratio

Deep Standby USB Suspend/Resume Interrupt

Register

1

of ICLK/PCLKB)*

32

2, 3 PCLKB

2 ICLK

000A 0500h

000A 0504h

000A 0508h

PDC

PDC Control Register 0

PDC Control Register 1

PDC Status Register

PCCR0

PCCR1

PCSR

PCMONR

PCDR

VCR

PDC

000A 050Ch PDC

PDC Pin Monitor Register

PDC Receive Data Register

Vertical Capture Register

Horizontal Capture Register

000A 0510h

000A 0514h

000A 0518h

PDC

HCR

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 140 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (48 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

32

4, 5 PCLKA

13, 14 PCLKA

1 to 3 ICLK

000C 0000h

EDMAC EDMAC Mode Register

0

EDMR

EDTRR

EDRRR

TDLAR

RDLAR

EESR

EDMACa

1 to 3 ICLK

1 to 7 ICLK

000C 0008h

000C 0010h

000C 0018h

000C 0020h

000C 0028h

000C 0030h

000C 0038h

000C 0040h

000C 0048h

000C 0050h

000C 0058h

000C 0064h

000C 0068h

EDMAC EDMAC Transmit Request Register

0

EDMACa

ETHERC

EDMAC EDMAC Receive Request Register

0

EDMAC Transmit Descriptor List Start Address Register

0

EDMAC Receive Descriptor List Start Address Register

0

EDMAC ETHERC/EDMAC Status Register

0

EDMAC ETHERC/EDMAC Status Interrupt Enable Register

0

EESIPR

TRSCER

RMFCR

TFTR

EDMAC ETHERC/EDMAC Transmit/Receive Status Copy

0

Enable Register

EDMAC Missed-Frame Counter Register

0

EDMAC Transmit FIFO Threshold Register

0

EDMAC FIFO Depth Register

0

FDR

EDMAC Receive Method Control Register

0

RMCR

TFUCR

RFOCR

IOSR

EDMAC Transmit FIFO Underflow Counter

0

EDMAC Receive FIFO Overflow Counter

0

000C 006Ch EDMAC Independent Output Signal Setting Register

0

000C 0070h

EDMAC Flow Control Start FIFO Threshold Setting Register

0

FCFTR

RPADIR

TRIMD

RBWAR

RDFAR

TBRAR

TDFAR

ECMR

RFLR

000C 0078h

EDMAC Receive Data Padding Insert Register

0

000C 007Ch EDMAC Transmit Interrupt Setting Register

0

000C 00C8h EDMAC Receive Buffer Write Address Register

0

000C 00CCh EDMAC Receive Descriptor Fetch Address Register

0

000C 00D4h EDMAC Transmit Buffer Read Address Register

0

000C 00D8h EDMAC Transmit Descriptor Fetch Address Register

0

000C 0100h

000C 0108h

000C 0110h

000C 0118h

000C 0120h

000C 0128h

000C 0140h

000C 0150h

000C 0154h

ETHER ETHERC Mode Register

C0

ETHER Receive Frame Maximum Length Register

C0

ETHER ETHERC Status Register

C0

ECSR

ETHER ETHERC Interrupt Enable Register

C0

ECSIPR

PIR

ETHER PHY Interface Register

C0

ETHER PHY Status Register

C0

PSR

ETHER Random Number Generation Counter Limit Setting

RDMLR

IPGR

C0

Register

ETHER Interpacket Gap Register

C0

ETHER Automatic PAUSE Frame Register

C0

APR

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 141 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (49 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

32

13, 14 PCLKA

1 to 7 ICLK

000C 0158h

ETHER Manual PAUSE Frame Register

C0

MPR

ETHERC

1 to 7 ICLK

000C 0160h

000C 0164h

000C 0168h

ETHER Received PAUSE Frame Counter

C0

RFCF

ETHERC

ETHER PAUSE Frame Retransmit Count Setting Register

C0

TPAUSER

TPAUSECR

BCFRR

MAHR

ETHER PAUSE Frame Retransmit Counter

C0

000C 016Ch ETHER Broadcast Frame Receive Count Setting Register

C0

000C 01C0h ETHER MAC Address Upper Bit Register

C0

000C 01C8h ETHER MAC Address Lower Bit Register

C0

MALR

000C 01D0h ETHER Transmit Retry Over Counter Register

C0

TROCR

CDCR

000C 01D4h ETHER Late Collision Detect Counter Register

C0

000C 01D8h ETHER Lost Carrier Counter Register

C0

LCCR

000C 01DCh ETHER Carrier Not Detect Counter Register

C0

CNDCR

CEFCR

FRECR

TSFRCR

TLFRCR

RFCR

000C 01E4h ETHER CRC Error Frame Receive Counter Register

C0

000C 01E8h ETHER Frame Receive Error Counter Register

C0

000C 01ECh ETHER Too-Short Frame Receive Counter Register

C0

000C 01F0h ETHER Too-Long Frame Receive Counter Register

C0

000C 01F4h ETHER Received Alignment Error Frame Counter Register

C0

000C 01F8h ETHER Multicast Address Frame Receive Counter Register

C0

MAFCR

8

4, 5 PCLKA

1, 2 ICLK

000C 1200h

000C 1201h

000C 1202h

000C 1203h

000C 1204h

000C 1205h

000C 1206h

000C 1207h

000C 1208h

000C 1209h

MTU3

MTU4

MTU3

MTU4

MTU3

MTU4

MTU3

MTU4

Timer Control Register

TCR

MTU3a

Timer Control Register

TCR

8

Timer Mode Register 1

TMDR1

TIORH

TIORL

TIORH

TIORL

TIER

8

Timer Mode Register 1

8

Timer I/O Control Register H

Timer I/O Control Register L

Timer I/O Control Register H

Timer I/O Control Register L

Timer Interrupt Enable Register

Timer Output Master Enable Register A

Timer Gate Control Register A

Timer Output Control Register 1A

Timer Output Control Register 2A

Timer Counter

8

TIER

8

000C 120Ah MTU

000C 120Dh MTU

000C 120Eh MTU

000C 120Fh MTU

TOERA

TGCRA

TOCR1A

TOCR2A

TCNT

8

16

000C 1210h

000C 1212h

000C 1214h

000C 1216h

000C 1218h

MTU3

MTU4

MTU

Timer Counter

TCNT

Timer Cycle Data Register A

Timer Dead Time Data Register A

Timer General Register A

Timer General Register B

Timer General Register A

Timer General Register B

Timer Subcounter A

TCDRA

TDDRA

TGRA

TGRB

TGRA

TGRB

TCNTSA

MTU

MTU3

000C 121Ah MTU3

000C 121Ch MTU4

000C 121Eh MTU4

000C 1220h

MTU

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 142 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (50 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

MTU3a

16

8

16

8

4, 5 PCLKA

1, 2 ICLK

000C 1222h

000C 1224h

000C 1226h

000C 1228h

MTU

Timer Cycle Buffer Register A

TCBRA

TGRC

1, 2 ICLK

MTU3

MTU4

Timer General Register C

Timer General Register D

TGRD

Timer General Register C

TGRC

000C 122Ah MTU4

000C 122Ch MTU3

000C 122Dh MTU4

Timer General Register D

TGRD

Timer Status Register

TSR

8

Timer Status Register

TSR

8

000C 1230h

000C 1231h

000C 1232h

000C 1234h

000C 1236h

000C 1238h

000C 1239h

MTU

MTU3

MTU4

Timer Interrupt Skipping Set Register 1A

Timer Interrupt Skipping Counter 1A

Timer Buffer Transfer Set Register A

Timer Dead Time Enable Register A

Timer Output Level Buffer Register A

Timer Buffer Operation Transfer Mode Register

Timer Interrupt Skipping Mode Register A

Timer Interrupt Skipping Set Register 2A

Timer Interrupt Skipping Counter 2A

Timer A/D Converter Start Request Control Register

TITCR1A

TITCNT1A

TBTERA

TDERA

TOLBRA

TBTM

8

TBTM

8

000C 123Ah MTU

000C 123Bh MTU

000C 123Ch MTU

TITMRA

TITCR2A

TITCNT2A

TADCR

8

16

000C 1240h

000C 1244h

MTU4

Timer A/D Converter Start Request Cycle Set Register TADCORA

A

16

4, 5 PCLKA

1, 2 ICLK

000C 1246h

000C 1248h

MTU4

Timer A/D Converter Start Request Cycle Set Register TADCORB

B

MTU3a

Timer A/D Converter Start Request Cycle Set Buffer

Register A

TADCOBRA

000C 124Ah MTU4

Timer A/D Converter Start Request Cycle Set Buffer

Register B

TADCOBRB

8

4, 5 PCLKA

1, 2 ICLK

000C 124Ch MTU3

000C 124Dh MTU4

Timer Control Register 2

TCR2

MTU3a

Timer Control Register 2

TCR2

8

000C 1260h

000C 1270h

000C 1272h

000C 1274h

000C 1276h

000C 1280h

000C 1281h

000C 1282h

000C 1284h

000C 1290h

000C 1291h

000C 1292h

000C 1293h

000C 1294h

000C 1298h

000C 1299h

000C 1300h

000C 1301h

000C 1302h

000C 1303h

000C 1304h

000C 1306h

000C 1308h

MTU

Timer Waveform Control Register A

Timer Mode Register 2A

TWCRA

TMDR2A

TGRE

8

MTU

16

8

16

8

MTU3

MTU4

MTU

Timer General Register E

TGRE

Timer General Register F

TGRF

Timer Start Register A

TSTRA

TSYRA

TCSYSTR

TRWERA

NFCR0

NFCR1

NFCR2

NFCR3

NFCR4

NFCR8

NFCRC

TCR

8

MTU

Timer Synchronous Register A

Timer Counter Synchronous Start Register

Timer Read/Write Enable Register A

Noise Filter Control Register 0

Noise Filter Control Register 1

Noise Filter Control Register 2

Noise Filter Control Register 3

Noise Filter Control Register 4

Noise Filter Control Register 8

Noise Filter Control Register C

Timer Control Register

8

MTU

8

MTU

8

MTU0

MTU1

MTU2

MTU3

MTU4

MTU8

MTU0

8

Timer Mode Register 1

TMDR1

TIORH

TIORL

TIER

8

Timer I/O Control Register H

Timer I/O Control Register L

Timer Interrupt Enable Register

Timer Counter

8

16

TCNT

Timer General Register A

TGRA

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 143 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (51 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

MTU3a

16

8

16

8

4, 5 PCLKA

1, 2 ICLK

000C 130Ah MTU0

000C 130Ch MTU0

000C 130Eh MTU0

Timer General Register B

Timer General Register C

Timer General Register D

Timer General Register E

Timer General Register F

Timer Interrupt Enable Register 2

Timer Buffer Operation Transfer Mode Register

Timer Control Register 2

Timer Control Register

TGRB

TGRC

TGRD

TGRE

TGRF

TIER2

TBTM

TCR2

TCR

1, 2 ICLK

000C 1320h

000C 1322h

000C 1324h

000C 1326h

000C 1328h

000C 1380h

000C 1381h

000C 1382h

000C 1384h

000C 1385h

000C 1386h

000C 1388h

MTU0

MTU1

8

Timer Mode Register 1

TMDR1

TIOR

8

Timer I/O Control Register

Timer Interrupt Enable Register

Timer Status Register

8

TIER

8

TSR

16

8

16

8

Timer Counter

TCNT

TGRA

TGRB

TICCR

TMDR3

TCR2

TCNTLW

TGRALW

TGRBLW

TCR

Timer General Register A

Timer General Register B

Timer Input Capture Control Register

Timer Mode Register 3

000C 138Ah MTU1

000C 1390h

000C 1391h

000C 1394h

MTU1

8

Timer Control Register 2

Timer Longword Counter

Timer Longword General Register

Timer Control Register

32

8

32

8

000C 13A0h MTU1

000C 13A4h MTU1

000C 13A8h MTU1

000C 1400h

000C 1401h

000C 1402h

000C 1404h

000C 1405h

000C 1406h

000C 1408h

MTU2

8

Timer Mode Register 1

TMDR1

TIOR

8

Timer I/O Control Register

Timer Interrupt Enable Register

Timer Status Register

8

TIER

8

TSR

16

8

16

8

Timer Counter

TCNT

TGRA

TGRB

TCR2

TCR

Timer General Register A

Timer General Register B

Timer Control Register 2

Timer Control Register

000C 140Ah MTU2

000C 140Ch MTU2

8

000C 1600h

000C 1601h

000C 1602h

000C 1603h

000C 1604h

000C 1606h

000C 1608h

MTU8

8

Timer Mode Register 1

TMDR1

TIORH

TIORL

TIER

8

Timer I/O Control Register H

Timer I/O Control Register L

Timer Interrupt Enable Register

Timer Control Register 2

Timer Counter

8

TCR2

TCNT

TGRA

TGRB

TGRC

TGRD

TCR

32

8

32

8

000C 160Ch MTU8

Timer General Register A

Timer General Register B

Timer General Register C

Timer General Register D

Timer Control Register

000C 1610h

000C 1614h

000C 1618h

MTU8

000C 1A00h MTU6

000C 1A01h MTU7

000C 1A02h MTU6

000C 1A03h MTU7

000C 1A04h MTU6

000C 1A05h MTU6

000C 1A06h MTU7

000C 1A07h MTU7

8

Timer Control Register

TCR

8

Timer Mode Register 1

TMDR1

TIORH

TIORL

TIORH

TIORL

8

Timer Mode Register 1

8

Timer I/O Control Register H

Timer I/O Control Register L

Timer I/O Control Register H

Timer I/O Control Register L

8

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 144 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (52 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

MTU3a

8

4, 5 PCLKA

1, 2 ICLK

000C 1A08h MTU6

000C 1A09h MTU7

000C 1A0Ah MTU

000C 1A0Eh MTU

000C 1A0Fh MTU

000C 1A10h MTU6

000C 1A12h MTU7

000C 1A14h MTU

000C 1A16h MTU

000C 1A18h MTU6

000C 1A1Ah MTU6

000C 1A1Ch MTU7

000C 1A1Eh MTU7

000C 1A20h MTU

000C 1A22h MTU

000C 1A24h MTU6

000C 1A26h MTU6

000C 1A28h MTU7

000C 1A2Ah MTU7

000C 1A2Ch MTU6

000C 1A2Dh MTU7

000C 1A30h MTU

000C 1A31h MTU

000C 1A32h MTU

000C 1A34h MTU

000C 1A36h MTU

000C 1A38h MTU6

000C 1A39h MTU7

000C 1A3Ah MTU

000C 1A3Bh MTU

000C 1A3Ch MTU

000C 1A40h MTU7

000C 1A44h MTU7

Timer Interrupt Enable Register

Timer Output Master Enable Register B

Timer Output Control Register 1B

Timer Output Control Register 2B

Timer Counter

TIER

1, 2 ICLK

TIER

8

TOERB

TOCR1B

TOCR2B

TCNT

8

16

8

16

8

Timer Counter

TCNT

Timer Cycle Data Register B

TCDRB

TDDRB

TGRA

Timer Dead Time Data Register B

Timer General Register A

Timer General Register B

TGRB

Timer General Register A

TGRA

Timer General Register B

TGRB

Timer Subcounter B

TCNTSB

TCBRB

TGRC

Timer Cycle Buffer Register B

Timer General Register C

Timer General Register D

TGRD

Timer General Register C

TGRC

Timer General Register D

TGRD

Timer Status Register

TSR

8

Timer Status Register

TSR

8

Timer Interrupt Skipping Set Register 1B

Timer Interrupt Skipping Counter 1B

Timer Buffer Transfer Set Register B

Timer Dead Time Enable Register B

Timer Output Level Buffer Register B

Timer Buffer Operation Transfer Mode Register

Timer Interrupt Skipping Mode Register B

Timer Interrupt Skipping Set Register 2B

Timer Interrupt Skipping Counter 2B

Timer A/D Converter Start Request Control Register

TITCR1B

TITCNT1B

TBTERB

TDERB

TOLBRB

TBTM

8

TBTM

8

TITMRB

TITCR2B

TITCNT2B

TADCR

8

16

Timer A/D Converter Start Request Cycle Set Register TADCORA

A

16

4, 5 PCLKA

1, 2 ICLK

000C 1A46h MTU7

000C 1A48h MTU7

000C 1A4Ah MTU7

Timer A/D Converter Start Request Cycle Set Register TADCORB

B

MTU3a

Timer A/D Converter Start Request Cycle Set Buffer

Register A

TADCOBRA

Timer A/D Converter Start Request Cycle Set Buffer

Register B

TADCOBRB

8

4, 5 PCLKA

1, 2 ICLK

000C 1A4Ch MTU6

000C 1A4Dh MTU7

000C 1A50h MTU6

000C 1A60h MTU

000C 1A70h MTU

000C 1A72h MTU6

000C 1A74h MTU7

000C 1A76h MTU7

000C 1A80h MTU

000C 1A81h MTU

000C 1A84h MTU

Timer Control Register 2

TCR2

MTU3a

Timer Control Register 2

TCR2

8

Timer Synchronous Clear Register

Timer Waveform Control Register B

Timer Mode Register 2B

TSYCR

TWCRB

TMDR2B

TGRE

8

16

8

16

8

Timer General Register E

TGRE

Timer General Register F

TGRF

Timer Start Register B

TSTRB

TSYRB

TRWERB

8

Timer Synchronous Register B

Timer Read/Write Enable Register B

8

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 145 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (53 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

MTU3a

8

4, 5 PCLKA

1, 2 ICLK

000C 1A93h MTU6

000C 1A94h MTU7

000C 1A95h MTU5

000C 1C80h MTU5

000C 1C82h MTU5

000C 1C84h MTU5

000C 1C85h MTU5

000C 1C86h MTU5

000C 1C90h MTU5

000C 1C92h MTU5

000C 1C94h MTU5

000C 1C95h MTU5

000C 1C96h MTU5

000C 1CA0h MTU5

000C 1CA2h MTU5

000C 1CA4h MTU5

000C 1CA5h MTU5

000C 1CA6h MTU5

000C 1CB2h MTU5

000C 1CB4h MTU5

000C 1CB6h MTU5

Noise Filter Control Register 6

Noise Filter Control Register 7

Noise Filter Control Register 5

Timer Counter U

NFCR6

NFCR7

NFCR5

TCNTU

TGRU

TCRU

1, 2 ICLK

8

16

8

16

8

Timer General Register U

Timer Control Register U

Timer Control Register 2

Timer I/O Control Register U

Timer Counter V

8

TCR2U

TIORU

TCNTV

TGRV

8

16

8

16

8

Timer General Register V

Timer Control Register V

Timer Control Register 2

Timer I/O Control Register V

Timer Counter W

TCRV

8

TCR2V

TIORV

TCNTW

TGRW

TCRW

TCR2W

TIORW

TIER

8

16

8

16

8

Timer General Register W

Timer Control Register W

Timer Control Register 2

Timer I/O Control Register W

Timer Interrupt Enable Register

Timer Start Register

8

TSTR

8

Timer Compare Match Clear Register

TCNTCMPCL

R

32

8

32

8

1, 2 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

1 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

000C 5800h

000D 0040h

000D 0041h

000D 0042h

000D 0043h

000D 0044h

000D 0045h

000D 0046h

000D 0047h

000D 0048h

000D 0049h

BSC

Extended Bus Master Priority Control Register

Serial Mode Register

EBMAPCR

SMR

BSC

SCIi

SCI10

8

SMCI10 Serial Mode Register

SMR

8

SCI10

Bit Rate Register

BRR

8

Serial Control Register

SCR

8

SMCI10 Serial Control Register

SCR

8

SCI10

Transmit Data Register

Serial Status Register

TDR

8

SSR

8

SMCI10 Serial Status Register

SSR

8

SCI10

Serial Status Register

Receive Data Register

Smart Card Mode Register

SSRFIFO

RDR

8

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

8

SMCI10 Smart Card Mode Register

8

SCI10

Serial Extended Mode Register

Noise Filter Setting Register

8

2

8

I C Mode Register 1

2

8

000D 004Ah SCI10

000D 004Bh SCI10

000D 004Ch SCI10

000D 004Dh SCI10

000D 004Eh SCI10

000D 004Fh SCI10

000D 004Eh SCI10

000D 004Fh SCI10

000D 004Eh SCI10

I C Mode Register 2

2

8

I C Mode Register 3

2

8

I C Status Register

8

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

FTDR.H

FTDR.L

FTDR

RDRH

RDRL

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Transmit FIFO Data Register

Receive Data Register H

Receive Data Register L

8

16

8

16

8

16

8

16

8

000D 0050h

000D 0051h

SCI10

8

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 146 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (54 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

SCIi

16

8

16

8

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

1 to 3 ICLK

000D 0050h

000D 0051h

000D 0050h

000D 0052h

000D 0053h

000D 0054h

000D 0055h

000D 0054h

000D 0056h

000D 0057h

000D 0056h

000D 0058h

000D 0059h

000D 0058h

SCI10

Receive Data Register HL

RDRHL

FRDR.H

FRDR.L

FRDR

MDDR

DCCR

FCR.H

FCR.L

FCR

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

Receive FIFO Data Register

Modulation Duty Register

Data Comparison Control Register

FIFO Control Register

8

16

8

16

8

FIFO Control Register

16

8

16

8

FIFO Control Register

FIFO Data Count Register

Line Status Register

FDR.H

FDR.L

FDR

8

16

8

16

8

LSR.H

LSR.L

LSR

8

Line Status Register

16

8

16

8

Line Status Register

000D 005Ah SCI10

000D 005Bh SCI10

000D 005Ah SCI10

000D 005Ch SCI10

Comparison Data Register

Serial Port Register

CDR.H

CDR.L

CDR

8

16

8

16

8

SPTR

SMR

8

000D 0060h

000D 0061h

000D 0062h

000D 0063h

000D 0064h

000D 0065h

000D 0066h

000D 0067h

000D 0068h

000D 0069h

SCI11

Serial Mode Register

8

SMCI11 Serial Mode Register

SMR

8

SCI11

Bit Rate Register

BRR

8

Serial Control Register

SCR

8

SMCI11 Serial Control Register

SCR

8

SCI11

Transmit Data Register

Serial Status Register

TDR

8

SSR

8

SMCI11 Serial Status Register

SSR

8

SCI11

Serial Status Register

Receive Data Register

Smart Card Mode Register

SSRFIFO

RDR

8

SCMR

SEMR

SNFR

SIMR1

SIMR2

SIMR3

SISR

8

SMCI11 Smart Card Mode Register

8

SCI11

Serial Extended Mode Register

Noise Filter Setting Register

8

2

8

I C Mode Register 1

2

8

000D 006Ah SCI11

000D 006Bh SCI11

000D 006Ch SCI11

000D 006Dh SCI11

000D 006Eh SCI11

000D 006Fh SCI11

000D 006Eh SCI11

000D 006Fh SCI11

000D 006Eh SCI11

I C Mode Register 2

2

8

I C Mode Register 3

2

8

I C Status Register

8

SPI Mode Register

SPMR

TDRH

TDRL

TDRHL

FTDR.H

FTDR.L

FTDR

RDRH

RDRL

RDRHL

FRDR.H

FRDR.L

FRDR

8

Transmit Data Register H

Transmit Data Register L

Transmit Data Register HL

Transmit FIFO Data Register

Receive Data Register H

Receive Data Register L

Receive Data Register HL

Receive FIFO Data Register

8

16

8

16

8

16

8

16

8

000D 0070h

000D 0071h

000D 0070h

000D 0071h

000D 0070h

SCI11

8

16

8

16

8

16

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 147 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (55 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

Address

ICLK < PCLK

8

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

5, 6 PCLKA

3, 4 PCLKA

1, 2 ICLK

000D 0072h

000D 0073h

000D 0074h

000D 0075h

000D 0074h

000D 0076h

000D 0077h

000D 0076h

000D 0078h

000D 0079h

000D 0078h

SCI11

Modulation Duty Register

MDDR

DCCR

FCR.H

FCR.L

FCR

SCIi

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

1 to 3 ICLK

1, 2 ICLK

Data Comparison Control Register

FIFO Control Register

FIFO Data Count Register

Line Status Register

SCIi

8

SCIi

8

SCIi

16

8

16

8

SCIi

FDR.H

FDR.L

FDR

SCIi

8

SCIi

16

8

16

8

SCIi

LSR.H

LSR.L

LSR

SCIi

8

Line Status Register

SCIi

16

8

16

8

Line Status Register

SCIi

000D 007Ah SCI11

000D 007Bh SCI11

000D 007Ah SCI11

000D 007Ch SCI11

Comparison Data Register

Serial Port Register

CDR.H

CDR.L

CDR

SCIi

8

SCIi

16

8

16

8

SCIi

SPTR

SPCR

SSLP

SPPCR

SPSR

SPDR

SCIi

8

000D 0100h

000D 0101h

000D 0102h

000D 0103h

000D 0104h

RSPI0 RSPI Control Register

RSPIc

8

RSPI0 RSPI Slave Select Polarity Register

RSPI0 RSPI Pin Control Register

RSPI0 RSPI Status Register

8

32

8, 16,

32

RSPI0 RSPI Data Register

8

3, 4 PCLKA

1, 2 ICLK

000D 0108h

000D 0109h

RSPI0 RSPI Sequence Control Register

RSPI0 RSPI Sequence Status Register

SPSCR

SPSSR

SPBR

RSPIc

8

000D 010Ah RSPI0 RSPI Bit Rate Register

8

000D 010Bh RSPI0 RSPI Data Control Register

000D 010Ch RSPI0 RSPI Clock Delay Register

000D 010Dh RSPI0 RSPI Slave Select Negation Delay Register

000D 010Eh RSPI0 RSPI Next-Access Delay Register

000D 010Fh RSPI0 RSPI Control Register 2

SPDCR

SPCKD

SSLND

SPND

8

SPCR2

SPCMD0

SPCMD1

SPCMD2

SPCMD3

SPCMD4

SPCMD5

SPCMD6

SPCMD7

SPDCR2

SPCR

16

8

16

8

000D 0110h

000D 0112h

000D 0114h

000D 0116h

000D 0118h

000D 011Ah

RSPI0 RSPI Command Register 0

RSPI0 RSPI Command Register 1

RSPI0 RSPI Command Register 2

RSPI0 RSPI Command Register 3

RSPI0 RSPI Command Register 4

RSPI0 RSPI Command Register 5

000D 011Ch RSPI0 RSPI Command Register 6

000D 011Eh

000D 0120h

000D 0140h

000D 0141h

000D 0142h

000D 0143h

000D 0144h

RSPI0 RSPI Command Register 7

RSPI0 RSPI Data Control Register 2

RSPI1 RSPI Control Register

8

RSPI1 RSPI Slave Select Polarity Register

RSPI1 RSPI Pin Control Register

RSPI1 RSPI Status Register

SSLP

8

SPPCR

SPSR

8

32

8, 16,

32

RSPI1 RSPI Data Register

SPDR

8

3, 4 PCLKA

1, 2 ICLK

000D 0148h

000D 0149h

RSPI1 RSPI Sequence Control Register

RSPI1 RSPI Sequence Status Register

SPSCR

SPSSR

SPBR

RSPIc

000D 014Ah RSPI1 RSPI Bit Rate Register

000D 014Bh RSPI1 RSPI Data Control Register

000D 014Ch RSPI1 RSPI Clock Delay Register

000D 014Dh RSPI1 RSPI Slave Select Negation Delay Register

000D 014Eh RSPI1 RSPI Next-Access Delay Register

SPDCR

SPCKD

SSLND

SPND

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 148 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (56 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

RSPIc

8

16

8

16

8

3, 4 PCLKA

1, 2 ICLK

000D 014Fh RSPI1 RSPI Control Register 2

SPCR2

SPCMD0

SPCMD1

SPCMD2

SPCMD3

SPCMD4

SPCMD5

SPCMD6

SPCMD7

SPDCR2

SPCR

1, 2 ICLK

000D 0150h

000D 0152h

000D 0154h

000D 0156h

000D 0158h

RSPI1 RSPI Command Register 0

RSPI1 RSPI Command Register 1

RSPI1 RSPI Command Register 2

RSPI1 RSPI Command Register 3

RSPI1 RSPI Command Register 4

000D 015Ah RSPI1 RSPI Command Register 5

000D 015Ch RSPI1 RSPI Command Register 6

000D 015Eh RSPI1 RSPI Command Register 7

000D 0160h

000D 0300h

000D 0301h

000D 0302h

000D 0303h

000D 0304h

RSPI1 RSPI Data Control Register 2

RSPI2 RSPI Control Register

8

RSPI2 RSPI Slave Select Polarity Register

RSPI2 RSPI Pin Control Register

RSPI2 RSPI Status Register

SSLP

8

SPPCR

SPSR

8

32

8, 16,

32

RSPI2 RSPI Data Register

SPDR

8

3, 4 PCLKA

5, 6 PCLKA*

1, 2 ICLK

000D 0308h

000D 0309h

RSPI2 RSPI Sequence Control Register

RSPI2 RSPI Sequence Status Register

SPSCR

SPSSR

SPBR

RSPIc

GLCDC

8

000D 030Ah RSPI2 RSPI Bit Rate Register

8

000D 030Bh RSPI2 RSPI Data Control Register

000D 030Ch RSPI2 RSPI Clock Delay Register

000D 030Dh RSPI2 RSPI Slave Select Negation Delay Register

000D 030Eh RSPI2 RSPI Next-Access Delay Register

000D 030Fh RSPI2 RSPI Control Register 2

SPDCR

SPCKD

SSLND

8

SPND

8

SPCR2

16

8

16

8

000D 0310h

000D 0312h

000D 0314h

000D 0316h

000D 0318h

RSPI2 RSPI Command Register 0

RSPI2 RSPI Command Register 1

RSPI2 RSPI Command Register 2

RSPI2 RSPI Command Register 3

RSPI2 RSPI Command Register 4

SPCMD0

SPCMD1

SPCMD2

SPCMD3

SPCMD4

SPCMD5

SPCMD6

SPCMD7

SPDCR2

000D 031Ah RSPI2 RSPI Command Register 5

000D 031Ch RSPI2 RSPI Command Register 6

000D 031Eh RSPI2 RSPI Command Register 7

000D 0320h

RSPI2 RSPI Data Control Register 2

3

32

1, 2 ICLK*

000E 0000h

to

000E 03FCh

GLCDC Graphic 1 Color Look-up Table 0[0 to 255]

GR1CLUT0[0

to 255]

3

32

5, 6 PCLKA*

2, 3 PCLKA

000E 0400h

to

000E 07FCh

GLCDC Graphic 1 Color Look-up Table 1[0 to 255]

GLCDC Graphic 2 Color Look-up Table 0[0 to 255]

GR1CLUT1[0

to 255]

GLCDC

000E 0800h

to

000E 0BFCh

GR2CLUT0[0

to 255]

000E 0C00h GLCDC Graphic 2 Color Look-up Table 1[0 to 255]

to

000E 0FFCh

GR2CLUT1[0

to 255]

1, 2 ICLK

000E 1000h

GLCDC Background Generating Block Operation Control

Register

BGEN

32

2, 3 PCLKA

1, 2 ICLK

000E 1004h

000E 1008h

GLCDC Free-Running Period Register

GLCDC Synchronization Position Register

BGPERI

GLCDC

BGSYNC

BGVSIZE

BGHSIZE

BGCOLOR

000E 100Ch GLCDC Vertical Size Register

000E 1010h

000E 1014h

000E 1018h

000E 1100h

GLCDC Horizontal Size Register

GLCDC Background Color Register

GLCDC Background Generating Block Status Monitor Register BGMON

GLCDC Graphic 1 Register Update Control Register GR1VEN

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 149 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (57 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

GLCDC

32

2, 3 PCLKA

1, 2 ICLK

000E 1104h

000E 110Ch

000E 1110h

000E 1118h

000E 111Ch

000E 1120h

000E 1124h

000E 1128h

000E 112Ch

000E 1130h

000E 1134h

000E 1138h

000E 113Ch

000E 1140h

000E 114Ch

000E 1150h

000E 1154h

000E 1200h

000E 1204h

GLCDC Graphic 1 Frame Buffer Read Control Register

GLCDC Graphic 1 Frame Buffer Control Register 2

GLCDC Graphic 1 Frame Buffer Control Register 3

GLCDC Graphic 1 Frame Buffer Control Register 5

GLCDC Graphic 1 Frame Buffer Control Register 6

GLCDC Graphic 1 Alpha Blending Control Register 1

GLCDC Graphic 1 Alpha Blending Control Register 2

GLCDC Graphic 1 Alpha Blending Control Register 3

GLCDC Graphic 1 Alpha Blending Control Register 4

GLCDC Graphic 1 Alpha Blending Control Register 5

GLCDC Graphic 1 Alpha Blending Control Register 6

GLCDC Graphic 1 Alpha Blending Control Register 7

GLCDC Graphic 1 Alpha Blending Control Register 8

GLCDC Graphic 1 Alpha Blending Control Register 9

GLCDC Graphic 1 Background Color Control Register

GLCDC Graphic 1 CLUT/Interrupt Control Register

GLCDC Graphic 1 Status Monitor Register

GR1FLMRD

GR1FLM2

GR1FLM3

GR1FLM5

GR1FLM6

GR1AB1

1, 2 ICLK

GR1AB2

GR1AB3

GR1AB4

GR1AB5

GR1AB6

GR1AB7

GR1AB8

GR1AB9

GR1BASE

GR1CLUTINT

GR1MON

GR2VEN

GR2FLMRD

GR2FLM2

GR2FLM3

GR2FLM5

GR2FLM6

GR2AB1

GLCDC Graphic 2 Register Update Control Register

GLCDC Graphic 2 Frame Buffer Read Control Register

000E 120Ch GLCDC Graphic 2 Frame Buffer Control Register 2

000E 1210h

000E 1218h

GLCDC Graphic 2 Frame Buffer Control Register 3

GLCDC Graphic 2 Frame Buffer Control Register 5

000E 121Ch GLCDC Graphic 2 Frame Buffer Control Register 6

000E 1220h

000E 1224h

000E 1228h

GLCDC Graphic 2 Alpha Blending Control Register 1

GLCDC Graphic 2 Alpha Blending Control Register 2

GLCDC Graphic 2 Alpha Blending Control Register 3

GR2AB2

GR2AB3

000E 122Ch GLCDC Graphic 2 Alpha Blending Control Register 4

GR2AB4

000E 1230h

000E 1234h

000E 1238h

GLCDC Graphic 2 Alpha Blending Control Register 5

GLCDC Graphic 2 Alpha Blending Control Register 6

GLCDC Graphic 2 Alpha Blending Control Register 7

GR2AB5

GR2AB6

GR2AB7

000E 123Ch GLCDC Graphic 2 Alpha Blending Control Register 8

000E 1240h GLCDC Graphic 2 Alpha Blending Control Register 9

000E 124Ch GLCDC Graphic 2 Background Color Control Register

GR2AB8

GR2AB9

GR2BASE

GR2CLUTINT

GR2MON

000E 1250h

000E 1254h

000E 1300h

GLCDC Graphic 2 CLUT/Interrupt Control Register

GLCDC Graphic 2 Status Monitor Register

GLCDC Gamma Correction G Block Register Update Control GAMGVEN

Register

32

2, 3 PCLKA

1, 2 ICLK

000E 1304h

000E 1308h

GLCDC Gamma Correction Block Function Switch Register

GLCDC Gamma Correction G Table Setting Register 1

GAMSW

GLCDC

GAMGLUT1

GAMGLUT2

GAMGLUT3

GAMGLUT4

GAMGLUT5

GAMGLUT6

GAMGLUT7

GAMGLUT8

GAMGAREA1

GAMGAREA2

GAMGAREA3

GAMGAREA4

000E 130Ch GLCDC Gamma Correction G Table Setting Register 2

000E 1310h

000E 1314h

000E 1318h

GLCDC Gamma Correction G Table Setting Register 3

GLCDC Gamma Correction G Table Setting Register 4

GLCDC Gamma Correction G Table Setting Register 5

000E 131Ch GLCDC Gamma Correction G Table Setting Register 6

000E 1320h

000E 1324h

000E 1328h

GLCDC Gamma Correction G Table Setting Register 7

GLCDC Gamma Correction G Table Setting Register 8

GLCDC Gamma Correction G Area Setting Register 1

000E 132Ch GLCDC Gamma Correction G Area Setting Register 2

000E 1330h

000E 1334h

GLCDC Gamma Correction G Area Setting Register 3

GLCDC Gamma Correction G Area Setting Register 4

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 150 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (58 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

GLCDC

32

2, 3 PCLKA

1, 2 ICLK

000E 1338h

000E 1340h

GLCDC Gamma Correction G Area Setting Register 5

GAMGAREA5

1, 2 ICLK

GLCDC Gamma Correction B Block Register Update Control GAMBVEN

Register

32

2, 3 PCLKA

1, 2 ICLK

000E 1348h

GLCDC Gamma Correction B Table Setting Register 1

GAMBLUT1

GAMBLUT2

GAMBLUT3

GAMBLUT4

GAMBLUT5

GAMBLUT6

GAMBLUT7

GAMBLUT8

GAMBAREA1

GAMBAREA2

GAMBAREA3

GAMBAREA4

GAMBAREA5

GLCDC

000E 134Ch GLCDC Gamma Correction B Table Setting Register 2

000E 1350h

000E 1354h

000E 1358h

GLCDC Gamma Correction B Table Setting Register 3

GLCDC Gamma Correction B Table Setting Register 4

GLCDC Gamma Correction B Table Setting Register 5

000E 135Ch GLCDC Gamma Correction B Table Setting Register 6

000E 1360h

000E 1364h

000E 1368h

GLCDC Gamma Correction B Table Setting Register 7

GLCDC Gamma Correction B Table Setting Register 8

GLCDC Gamma Correction B Area Setting Register 1

000E 136Ch GLCDC Gamma Correction B Area Setting Register 2

000E 1370h

000E 1374h

000E 1378h

000E 1380h

GLCDC Gamma Correction B Area Setting Register 3

GLCDC Gamma Correction B Area Setting Register 4

GLCDC Gamma Correction B Area Setting Register 5

GLCDC Gamma Correction R Block Register Update Control GAMRVEN

Register

32

2, 3 PCLKA

1, 2 ICLK

000E 1388h

GLCDC Gamma Correction R Table Setting Register 1

GAMRLUT1

GAMRLUT2

GAMRLUT3

GAMRLUT4

GAMRLUT5

GAMRLUT6

GAMRLUT7

GAMRLUT8

GAMRAREA1

GAMRAREA2

GAMRAREA3

GAMRAREA4

GAMRAREA5

OUTVEN

GLCDC

000E 138Ch GLCDC Gamma Correction R Table Setting Register 2

000E 1390h

000E 1394h

000E 1398h

GLCDC Gamma Correction R Table Setting Register 3

GLCDC Gamma Correction R Table Setting Register 4

GLCDC Gamma Correction R Table Setting Register 5

000E 139Ch GLCDC Gamma Correction R Table Setting Register 6

000E 13A0h GLCDC Gamma Correction R Table Setting Register 7

000E 13A4h GLCDC Gamma Correction R Table Setting Register 8

000E 13A8h GLCDC Gamma Correction R Area Setting Register 1

000E 13ACh GLCDC Gamma Correction R Area Setting Register 2

000E 13B0h GLCDC Gamma Correction R Area Setting Register 3

000E 13B4h GLCDC Gamma Correction R Area Setting Register 4

000E 13B8h GLCDC Gamma Correction R Area Setting Register 5

000E 13C0h GLCDC Output Control Block Register Update Control

Register

32

2, 3 PCLKA

1, 2 ICLK

000E 13C4h GLCDC Output Interface Register

000E 13C8h GLCDC Brightness Adjustment Register 1

000E 13CCh GLCDC Brightness Adjustment Register 2

000E 13D0h GLCDC Contrast Adjustment Register

000E 13D4h GLCDC Panel Dither Control Register

000E 13E4h GLCDC Output Phase Control Register

OUTSET

GLCDC

BRIGHT1

BRIGHT2

CONTRAST

PANELDTHA

CLKPHASE

TCONTIM

000E 1404h

000E 1408h

GLCDC Reference Timing Setting Register

GLCDC Vertical Timing Setting Register A1

TCONSTVA1

TCONSTVA2

TCONSTVB1

TCONSTVB2

TCONSTHA1

TCONSTHA2

TCONSTHB1

TCONSTHB2

TCONDE

000E 140Ch GLCDC Vertical Timing Setting Register A2

000E 1410h

000E 1414h

000E 1418h

GLCDC Vertical Timing Setting Register B1

GLCDC Vertical Timing Setting Register B2

GLCDC Horizontal Timing Setting Register A1

000E 141Ch GLCDC Horizontal Timing Setting Register A2

000E 1420h

000E 1424h

000E 1428h

000E 1440h

000E 1444h

GLCDC Horizontal Timing Setting Register B1

GLCDC Horizontal Timing Setting Register B2

GLCDC Data Enable Polarity Setting Register

GLCDC Status Detection Control Register

GLCDC Interrupt Request Enable Control Register

DTCTEN

INTEN

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 151 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (59 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

GLCDC

DRW2D

32

2, 3 PCLKA

1, 2 ICLK

000E 1448h

GLCDC Detected Status Clear Register

STCLR

1, 2 ICLK

000E 144Ch GLCDC Detected Status Monitor Register

STMON

000E 1450h

000E 3000h

000E 3004h

000E 3010h

000E 3014h

000E 3018h

GLCDC Panel Clock Control Register

DRW2D Geometry Control Register

DRW2D Status Register

PANELCLK

CONTROL

STATUS

CONTROL2

HWVER

L1START

L2START

L3START

L4START

L5START

L6START

L1XADD

L2XADD

L3XADD

L4XADD

L5XADD

L6XADD

L1YADD

L2YADD

L3YADD

L4YADD

L5YADD

L6YADD

L1BAND

L2BAND

COLOR1

COLOR2

PATTERN

SIZE

DRW2D Surface Control Register

DRW2D Hardware Version Register

DRW2D Limiter 1 Start Value Register

DRW2D Limiter 2 Start Value Register

DRW2D Limiter 3 Start Value Register

000E 301Ch DRW2D Limiter 4 Start Value Register

000E 3020h

000E 3024h

000E 3028h

DRW2D Limiter 5 Start Value Register

DRW2D Limiter 6 Start Value Register

DRW2D Limiter 1 X-Axis Increment Register

000E 302Ch DRW2D Limiter 2 X-Axis Increment Register

000E 3030h

000E 3034h

000E 3038h

DRW2D Limiter 3 X-Axis Increment Register

DRW2D Limiter 4 X-Axis Increment Register

DRW2D Limiter 5 X-Axis Increment Register

000E 303Ch DRW2D Limiter 6 X-Axis Increment Register

000E 3040h

000E 3044h

000E 3048h

DRW2D Limiter 1 Y-Axis Increment Register

DRW2D Limiter 2 Y-Axis Increment Register

DRW2D Limiter 3 Y-Axis Increment Register

000E 304Ch DRW2D Limiter 4 Y-Axis Increment Register

000E 3050h

000E 3054h

000E 3058h

DRW2D Limiter 5 Y-Axis Increment Register

DRW2D Limiter 6 Y-Axis Increment Register

DRW2D Limiter 1 Band Width Parameter Register

000E 305Ch DRW2D Limiter 2 Band Width Parameter Register

000E 3064h

000E 3068h

000E 3074h

000E 3078h

DRW2D Base Color Register

DRW2D Secondary Color Register

DRW2D Pattern Register

DRW2D Bounding Box Dimension Register

000E 307Ch DRW2D Frame Buffer Pitch Register

PITCH

000E 3080h

000E 3090h

000E 3094h

000E 3098h

DRW2D Frame Buffer Base Address Register

DRW2D U Limiter Start Value Register

ORIGIN

LUST

DRW2D U Limiter X-Axis Increment Register

DRW2D U Limiter Y-Axis Increment Register

LUXADD

LUYADD

LVSTI

000E 309Ch DRW2D V Limiter Start Value Integer Part Register

000E 30A0h DRW2D V Limiter Start Value Fractional Part Register

000E 30A4h DRW2D V Limiter X-Axis Increment Integer Part Register

000E 30A8h DRW2D V Limiter Y-Axis Increment Integer Part Register

000E 30ACh DRW2D V Limiter Increment Fractional Parts Register

000E 30B4h DRW2D Texels Per Texture Line Register

000E 30B8h DRW2D Texture Mask Register

LVSTF

LVXADDI

LVYADDI

LVYXADDF

TEXPITCH

TEXMSK

TEXORG

IRQCTL

000E 30BCh DRW2D Texture Base Address Register

000E 30C0h DRW2D Interrupt Control Register

000E 30C4h DRW2D Cache Control Register

CACHECTL

DLISTST

PERFCNT1

PERFCNT2

PERFTRG

000E 30C8h DRW2D Display List Start Address Register

000E 30CCh DRW2D Performance Counter 1

000E 30D0h DRW2D Performance Counter 2

000E 30D4h DRW2D Performance Counters Control Register

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 152 of 246

RX65N Group, RX651 Group

4. I/O Registers

Table 4.1

List of I/O Registers (Address Order) (60 / 60)

Number of Access Cycles

ICLK ≥ PCLK

Module

Symbol Register Name

Register

Symbol

Number Access

of Bits Size

ICLK < PCLK

Function

DRW2D

Flash

32

8

32

8

2, 3 PCLKA

1, 2 ICLK

000E 30DCh DRW2D CLUT Start Address Register

000E 30E0h DRW2D CLUT Data Register

000E 30E4h DRW2D CLUT Offset Register

000E 30E8h DRW2D Chroma Key Register

TEXCLADDR

TEXCLDATA

TEXCLOFST

COLKEY

1, 2 ICLK

2 FCLK

007F C040h FLASH Data Flash Memory Access Frequency Setting

Register

EEPFCLK

32

1 to 3 ICLK

FE7F 5D00h OFSM Endian Select Register

MDE

Option-

Setting

Memory

FE7F 5D04h OFSM Option Function Select Register 0

FE7F 5D08h OFSM Option Function Select Register 1

FE7F 5D10h OFSM TM Identification Data Register

FE7F 5D20h OFSM Bank Select Register

OFS0

Option-

Setting

Memory

OFS1

Option-

Setting

Memory

TMINF

BANKSEL

SPCC

TMEF

Option-

Setting

Memory

Option-

Setting

Memory

FE7F 5D40h OFSM Serial Programmer Command Control Register

FE7F 5D48h OFSM TM Enable Flag Register

Option-

Setting

Memory

Option-

Setting

Memory

FE7F 5D50h OFSM OCD/Serial Programmer ID Setting Register

FE7F 5D64h OFSM Flash Access Window Setting Register

FE7F 5D70h OFSM ROM Code Protection Register

OSIS

Option-

Setting

Memory

FAW

Option-

Setting

Memory

ROMCODE

Option-

Setting

Memory

32

1 to 3 ICLK

FE7F 7D7Ch TEMPS Temperature Sensor Calibration Data Register

FE7F 7D90h FLASH Unique ID Register 0

TSCDR

UIDR0

UIDR1

UIDR2

UIDR3

TEMPS

Flash

FE7F 7D94h FLASH Unique ID Register 1

FE7F 7D98h FLASH Unique ID Register 2

FE7F 7D9Ch FLASH Unique ID Register 3

Note 1. When the register is accessed while the USB is operating, a delay may be generated in accessing.

Note 2. The address must end with 0h, 4h, 8h, or Ch when access is made in 32-bit units. The address must end with 0h, 2h, 4h, 6h, 8h,

Ah, Ch, or Eh when access is made in 16-bit units.

Note 3. When the register is accessed while the GLCDC is operating, a delay may be generated in accessing.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 153 of 246

RX65N Group, RX651 Group

5. Electrical Characteristics

5.

Electrical Characteristics

5.1

Absolute Maximum Ratings

Table 5.1

Absolute Maximum Rating

Conditions: VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V

Item

Symbol

Value

Unit

Power supply voltage

_BATTpower supply voltage

VCC, VCC_USB

–0.3 to +4.0

V

V_BATT

Input voltage (except for ports for 5 V tolerant*¹)

Input voltage (ports for 5 V tolerant*¹)

Reference power supply voltage

Analog power supply voltage

V_in

–0.3 to VCC + 0.3 (up to 4.0)

–0.3 to VCC + 4.0 (up to 5.8)

–0.3 to AVCC0 + 0.3 (up to 4.0)

–0.3 to +4.0

V

V_in

V

VREFH0

V

AVCC0, AVCC1*²

V

Analog input voltage

V_AN

T_j

–0.3 to AVCC + 0.3 (up to 4.0)

–40 to +105

V

Junction temperature

D version

G version

°C

T_j

–40 to +125

Storage temperature

T_stg

–55 to +125

Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.

Note 1. Ports 07, 11 to 17, 20, 21, 30 to 33, 67, and C0 to C3 are 5 V tolerant.

Note 2. Connect the AVCC0, AVCC1, and VCC_USB pins to VCC, and the AVSS0, AVSS1, and VSS_USB pins to VSS.

When the A/D converter unit 0 is not to be used, connect the VREFH0 pin to VCC and the VREFL0 pin to VSS, respectively.

Do not leave these pins open. Insert capacitors of high frequency characteristics between the AVCC0 and AVSS0 pins, or

AVCC1 and AVSS1 pins. Place capacitors of about 0.1 μF as close as possible to every power supply pin and use the shortest

and heaviest possible traces.

Table 5.2

Recommended Operating Conditions

Item

Symbol

Min.

2.7

—

Typ.

—

Max.

Unit

V

Power supply voltage*¹

VCC

VSS

3.6

0

—

V

_BATTpower supply voltage

V_BATT

2.0

—

3.6

V

USB power supply voltage

VCC_USB

VSS_USB

AVCC0

AVSS0

AVCC1

AVSS1

VREFH0

VREFL0

V_in

VCC

0

—

V

—

V

Analog power supply voltage*^1,

*

—

VCC

0

—

V

2

—

V

—

VCC

0

V

—

V

2.7

—

AVCC0

—

V

0

V

Input voltage (except for 5 V tolerant ports,

except for ports 03, 05 and 40 to 47)*³

–0.3

—

VCC + 0.3

V

Input voltage (ports 03, 05 and 40 to 47)

V_in

–0.3

—

AVCC + 0.3

V

Input voltage (5V tolerant ports 11 to 17, ports 20 and

21, ports 30 to 33, port 67, and ports C0 to C3)*⁴

VCC + 3.6 (up to 5.5)

Input voltage (5V tolerant port 07)

Operating temperature (D version)

Operating temperature (G version)

V_in

T_opr

–0.3

–40

—

AVCC + 3.6 (up to 5.5)

V

85

°C

105

Note 1. Comply with the following potential condition: VCC = AVCC0 = AVCC1 = VCC_USB

Note 2. For details, see section 53.6.11, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.

Note 3. Ports 07, 11 to 17, 20, 21, 30 to 33, 67, and C0 to C3 are 5 V tolerant.

Note 4. For P32, P31, and P30, input as follows when the V_BATTpower supply is selected.

V_inMin. = –0.3, Max. = V_BATT+ 0.3 (V_BATT= 2.0 to 3.6 V)

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5. Electrical Characteristics

5.2

DC Characteristics

Table 5.3

DC Characteristics (1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

V

Schmitt trigger

input voltage

IRQ input pin*¹

MTU input pin*¹

POE3 input pin*¹

TPU input pin*¹

TMR input pin*¹

CMTW input pin*¹

SCI input pin*¹

V_IH

V_IL

VCC × 0.8

—

VCC × 0.2

—

ΔV_T

VCC × 0.06

CAN input pin*¹

CAC input pin*¹

ADTRG# input pin*¹

QSPI input pin*¹

RES#, NMI, TCK

RIIC input pin

(except for SMBus)

V_IH

V_IL

VCC × 0.7

—

VCC × 0.3

ΔV_T

V_IH

V_IL

VCC × 0.05

VCC × 0.8

—

Ports for 5 V tolerant*²

—

VCC × 0.2

—

Other input pins excluding ports

for 5 V tolerant*³

V_IH

V_IL

VCC × 0.8

—

VCC × 0.2

—

Input high voltage MD pin, EMLE

(except for Schmitt

V_IH

VCC × 0.9

VCC × 0.8

V

EXTAL, RSPI input pin,

—

trigger input pin)

EXDMAC input pin, WAIT#,

SDHI input pin, MMC input pin,

PDC input pin, SDSI input pin

ETHERC input pin

D0 to D31

2.3

VCC × 0.7

2.1

—

RIIC (SMBus)

MD pin, EMLE

—

Input low voltage

(except for Schmitt

trigger input pin)

V_IL

—

VCC × 0.1

VCC × 0.2

V

EXTAL, RSPI input pin,

—

ETHERC input pin,

EXDMAC input pin, WAIT#,

SDHI input pin, MMC input pin,

PDC input pin, SDSI input pin

D0 to D31

—

VCC × 0.3

0.8

RIIC (SMBus)

Note 1. This does not include the pins, which are multiplexed as ports for 5 V tolerant.

Note 2. Ports 07, 11 to 17, 20, 21, 30 to 33, 67, and C0 to C3 are 5 V tolerant.

Note 3. For P32, P31, and P30, input as follows when the V_BATTpower supply is selected.

V_IHMin. = V_BATT× 0.8, V_ILMax. = V_BATT× 0.2 (V_BATT= 2.0 to 3.6 V)

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5. Electrical Characteristics

Table 5.4

DC Characteristics (2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

V_OH

Min.

VCC – 0.5

—

Typ.

—

Max.

—

Unit

V

Test Conditions

I_OH= –1 mA

Output high voltage

Output low voltage

All output pins

V_OL

—

0.5

V

I_OL= 1.0 mA

(except for RIIC pins and

ETHERC output pin)

RIIC output pin

—

0.4

0.6

0.4

I

_OL= 3.0 mA

_OL= 6.0 mA

I

RIIC output pin

(only P12 and P13 in channel 0)

V_OL

V

I_OL= 15.0 mA

(ICFER.FMPE = 1)

—

0.4

—

I_OL= 20.0 mA

(ICFER.FMPE = 1)

ETHERC output pin

V_OL

| I_in

—

0.4

1.0

I_OL= 1.0 mA

Input leakage current RES#, MD pin, EMLE*¹,

BSCANP*¹, NMI

|

μA V_in= 0 V

V_in= VCC

Three-state leakage Other than ports for 5 V tolerant

current (off state)

| I_TSI

|

—

1.0

5.0

–10

300

8

μA V_in= 0 V

V_in= VCC

Ports for 5 V tolerant

V_in= 0 V

V_in= 5.5 V

Input pull-up resistor Other than P35

current

I_p

–300

10

μA VCC = 2.7 to 3.6 V

V_in= 0 V

Input pull-down

resistor current

EMLE, BSCANP

μA V_in= VCC

Input capacitance

All input pins

C_in

—

pF Vbias = 0 V

Vamp = 20 mV

f = 1 MHz

(except for ports 03, 05, 12, 13,

16, 17, 20, 21, EMLE, BSCANP,

USB0_DP, and USB0_DM)

T_a= 25°C

Ports 03, 05, 12, 13, 16, 17, 20,

21, EMLE, BSCANP, USB0_DP,

and USB0_DM

—

16

Note 1. The input leakage current value at the EMLE and BSCANP pins are only when V_in= 0 V.

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RX65N Group, RX651 Group

5. Electrical Characteristics

Table 5.5

DC Characteristics (3) (Products with 1 Mbyte of code flash memory or less)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

D version

G version

Item

Full operation*²

Symbol

Unit

Test Conditions

Typ. Max. Typ. Max.

3

Supply

current*¹

I_CC

*

—

40

—

45

—

mA ICLK = 120 MHz,

PCLKA = 120 MHz,

PCLKB = 60 MHz,

PCLKC = 60 MHz,

PCLKD = 60 MHz,

FCLK = 60 MHz,

Normal

operation

Peripheral module clocks are supplied

*

22

4

Peripheral module clocks are stopped

12

15

16

—

24

12

15

16

—

28

4,

5

*

Core

Mark

Peripheral module clocks are stopped

BCLK = 120 MHz,

BCLK pin = 60 MHz

4,

5

*

Sleep mode: Peripheral module clocks are

supplied*⁴

All module clock stop mode (reference value)

8

15

—

8

19

—

Low-speed operating mode 1: Peripheral module

clocks are stopped*⁴

1.1

All clocks 1 MHz

Low-speed operating mode 2: Peripheral module

clocks are stopped*⁴

1.1

—

1.1

—

All clocks 32.768

kHz

Software standby mode

1.6

6.4

61

1.6

9.8

85

Power is supplied to the standby RAM and USB

resume detecting unit (USB0 only)

15.5

μA

Power is not

supplied to the

standby RAM and reset circuit is disabled*⁶

USB resume

detecting unit

(USB0 only)

Low power consumption

function of the power-on

11.5

4.9

38

29

11.5

4.9

48

39

Low power consumption

function of the power-on

reset circuit is enabled*⁷

When a low C_Lcrystal is in

use

1

—

1

—

Increase current

by operating RTC

When a standard C_Lcrystal

is in use

2

When the RTC is

When a low C_Lcrystal is in

0.9

1.6

1.7

3.3

0.9

1.6

1.7

3.3

V_BATT= 2.0 V,

VCC = 0 V

operating while VCC is use

not supplied (Only the

RTC and sub-clock

V_BATT= 3.3 V,

VCC = 0 V

oscillator operate with

the battery backup

function)

When a standard C_Lcrystal

is in use

V_BATT= 2.0 V,

VCC = 0 V

V

_BATT= 3.3 V,

VCC = 0 V

I_RUSH

—

70

—

70

mA

μC

Inrush current on

release from deep

software standby mode

Inrush current*⁸

Total inrush current*⁸

E_RUSH

1.0

Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.

Note 2. Peripheral module clocks are supplied.

Note 3.

I_CCdepends on the f (ICLK) as follows (when ICLK/PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 2 : 1 : 2 : 1 and

EXTAL = 12 MHz).

 D version

I_CCmax = 0.31 × f + 6.5 (full operation in high-speed operating mode)

I_CCtyp = 0.16 × f + 2.8 (normal operation in high-speed operating mode)

I_CCtyp = 0.1 × f + 1.0 (ICLK 1 MHz max) (low-speed operating mode 1)

I_CCmax = 0.15 × f + 6.5 (sleep mode)

 G version

I_CCmax = 0.33 × f + 9 (full operation in high-speed operating mode)

I_CCtyp = 0.16 × f + 2.8 (normal operation in high-speed operating mode)

I_CCtyp = 0.1 × f + 1.0 (ICLK 1 MHz max) (low-speed operating mode 1)

I_CCmax = 0.21 × f + 9 (sleep mode)

Note 4. Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control

registers A to D.

Note 5. When the peripheral module clock is stopped, the settings of the clock frequency are as follows:

ICLK = 120 MHz and PCLKA = PCLKB = PCLKC = PCLKD = FCLK = BCLK = BCLK pin = 3.75 MHz (divided by 64).

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5. Electrical Characteristics

Note 6. When the low power consumption function is disabled, the DEEPCUT[1:0] bits are set to 01b.

Note 7. When the low power consumption function is enabled, the DEEPCUT[1:0] bits are set to 11b.

Note 8. Reference value

Table 5.6

DC Characteristics (3) (Products for products with at least 1.5 Mbytes of code flash

memory)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

D version

G version

Item

Full operation*²

Symbol

Unit

Test Conditions

Typ. Max. Typ. Max.

3

Supply

current*¹

I_CC

*

—

26

13

60

—

26

13

73

—

mA ICLK = 120 MHz,

PCLKA = 120 MHz,

PCLKB = 60 MHz,

PCLKC = 60 MHz,

PCLKD = 60 MHz,

FCLK = 60 MHz,

Normal

Peripheral module clocks are supplied*⁴

operation

Peripheral module clocks are stopped

4,

5

*

Core

Mark

Peripheral module clocks are stopped

17

20

—

17

20

—

4,

5

*

BCLK = 120 MHz,

BCLK pin = 60 MHz

Sleep mode: Peripheral module clocks are supplied

38

52

4

*

All module clock stop mode (reference value)

Increased by BGO Reading from the code flash

9

6

26

—

9

6

39

—

operation

*

memory while the data flash

memory is being programmed

8

Reading from the code flash

memory while the code flash

memory is being programmed

7

—

7

—

Increased by Trusted Secure IP operation

—

12

—

12

—

Low-speed operating mode 1: Peripheral module clocks

are stopped*⁴

1.6

All clocks 1 MHz

Low-speed operating mode 2: Peripheral module clocks

are stopped*⁴

1.6

—

1.6

—

All clocks 32.768

kHz

Software standby mode

1.6

13

70

1.6 22.4

Power is supplied to the standby RAM and USB

resume detecting unit (USB0 only)

15.5

98

μA

Power is not

supplied to the

standby RAM and circuit is disabled*⁶

USB resume

detecting unit

(USB0 only)

Low power consumption

function of the power-on reset

11.5

4.9

42

32

11.5

54

Low power consumption

function of the power-on reset

circuit is enabled*⁷

4.9

47

When a low C_Lcrystal is in

use

1

—

1

—

Increase current

by operating RTC

When a standard C_Lcrystal is

in use

2

—

When the RTC is

When a low C_Lcrystal is in

0.9

1.6

1.7

3.3

0.9

1.6

1.7

3.3

—

V_BATT= 2.0 V,

VCC = 0 V

operating while VCC is use

not supplied (Only the

RTC and sub-clock

—

V_BATT= 3.3 V,

VCC = 0 V

oscillator operate with

the battery backup

function)

When a standard C_Lcrystal is

in use

—

V_BATT= 2.0 V,

VCC = 0 V

—

V_BATT= 3.3 V,

VCC = 0 V

I_RUSH

—

130

1.0

—

130 mA

Inrush current on

release from deep

software standby mode

Inrush current*⁹

Total inrush current*⁹

E_RUSH

1.0

μC

Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.

Note 2. Peripheral module clocks are supplied.

Note 3.

I_CCdepends on the f (ICLK) as follows (when ICLK/PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 2 : 1 : 2 : 1 and

EXTAL = 12 MHz).

 D version

I_CCmax = 0.38 × f + 14 (full operation in high-speed operating mode)

I_CCtyp = 0.18 × f + 4 (normal operation in high-speed operating mode)

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5. Electrical Characteristics

I_CCtyp = 0.1 × f + 1.5 (ICLK 1 MHz max) (low-speed operating mode 1)

_CCmax = 0.2 × f + 14 (sleep mode)

I

 G version

I_CCmax = 0.44 × f + 20 (full operation in high-speed operating mode)

I_CCtyp = 0.18 × f + 4 (normal operation in high-speed operating mode)

I_CCtyp = 0.1 × f + 1.5 (ICLK 1 MHz max) (low-speed operating mode 1)

I_CCmax = 0.27 × f + 20 (sleep mode)

Note 4. Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control

registers A to D.

Note 5. When the peripheral module clock is stopped, the settings of the clock frequency are as follows:

ICLK = 120 MHz and PCLKA = PCLKB = PCLKC = PCLKD = FCLK = BCLK = BCLK pin = 3.75 MHz (divided by 64).

Note 6. When the low power consumption function is disabled, the DEEPCUT[1:0] bits are set to 01b.

Note 7. When the low power consumption function is enabled, the DEEPCUT[1:0] bits are set to 11b.

Note 8. These are the increases during programming of the code flash memory after the code flash memory (limitations apply to the

combinations of address ranges of the program area and the readable area) or the data flash memory has been programmed or

erased.

Note 9. Reference value

Table 5.7

DC Characteristics (4)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

D version

G version

Item

Symbol

AI_CC

Unit

Test Conditions

Min. Typ. Max. Min. Typ. Max.

Analog

power

supply

current*¹

During 12-bit A/D conversion (unit 0)

—

0.8

1.7

1

—

0.8

1.7

1

mA IAVCC0_AD

During 12-bit A/D conversion (unit 0)

with channel dedicated sample-and-

hold circuits (3 channels)

2.5

mA IAVCC0_AD + SH

During 12-bit A/D conversion (unit 1)

—

0.6

0.7

1

—

0.6

0.7

1

mA IAVCC1_AD

During 12-bit A/D conversion (unit 1)

+ temperature sensor

1.1

mA IAVCC1_AD +

TEMP

During D/A

conversion

(per unit)

Unbuffered output

Buffered output

—

0.25

0.75

0.4

1.1

—

0.25

0.75

0.4

1.1

mA IAVCC1_DA

mA

Waiting for A/D, D/A, and

temperature sensor conversion

(all units)

—

0.9

1.4

—

0.9

1.4

mA IAVCC0 +

IAVCC1

A/D, D/A, and temperature sensor

are in standby mode (all units)

—

1.4

6.7

—

1.4

9.0

μA IAVCC0 +

IAVCC1

Reference During 12-bit A/D conversion (unit 0) AI_REFH

—

38

60

—

38

60

μA IVREFH0

power

Waiting for 12-bit A/D conversion

0.07

0.5

0.07

0.6

supply

(unit 0)

current

12-bit A/D converter in module stop

—

0.07

0.4

—

0.07

0.5

μA IVREFH0

status (unit 0)

USB

operating

current

Low speed

Full speed

USB0

I_CCUSBLS

I_CCUSBFS

—

3.7

4.2

6.5

10

—

3.7

4.2

6.5

10

mA VCC_USB

RAM retension voltage

VCC rising gradient

VCC falling gradient*²

V_RAM

SrVCC

SfVCC

2.7

8.4

—

2.7

—

V

20000 8.4

8.4

20000 μs/V

μs/V

—

Note 1. The reference power supply current is included in the power supply current value for 12-bit A/D converter (unit 1) and D/A

converter.

Note 2. This applies when V_BATTis used.

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RX65N Group, RX651 Group

5. Electrical Characteristics

Table 5.8

Permissible Output Currents

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

I_OL

Min.

—

Typ.

—

Max.

2.0

Unit

mA

Permissible output low current

(average value per pin)

All output pins*¹

All output pins*²

All output pins*³

Normal drive

High drive

I_OL

—

3.8

High-speed interface

high-drive

I_OL

—

7.5

Permissible output low current

(max. value per pin)

All output pins*¹

All output pins*²

All output pins*³

Normal drive

High drive

I_OL

—

4.0

7.6

15

mA

High-speed interface

high-drive

Permissible output low current (total)

Total of all output pins

All output pins*¹

All output pins*²

All output pins*³

ΣI_OL

I_OH

—

80

mA

Permissible output high current

(average value per pin)

Normal drive

High drive

–2.0

–3.8

–7.5

High-speed interface

high-drive

Permissible output high current

(max. value per pin)

All output pins*¹

All output pins*²

All output pins*³

Normal drive

High drive

I_OH

—

–4.0

–7.6

–15

mA

High-speed interface

high-drive

Permissible output high current (total) Total of all output pins

ΣI_OH

—

–80

mA

Caution: To protect the LSI’s reliability, the output current values should not exceed the values in this table.

Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable.

Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to

which high driving ability is fixed.

Note 3. This is the value when high-speed interface high-driving ability is set with a pin for which high-speed interface high-driving ability

is selectable.

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RX65N Group, RX651 Group

5. Electrical Characteristics

Table 5.9

Thermal Resistance Value (Reference)

Item

Thermal resistance

Package

Symbol

Max.

48.0

50.9

52.5

53.7

36.3

35.4

34.6

34.1

35.3

1.0

Unit

°C/W JESD51-2 and

JESD51-7 compliant

Test Conditions

176-pin LFQFP (PLQP0176KB-A)

144-pin LFQFP (PLQP0144KA-B)

100-pin LFQFP (PLQP0100KB-B)

64-pin LFQFP (PLQP0064KB-C)

177-pin TFLGA (PTLG0177KA-A)

176-pin LFBGA (PLBG0176GA-A)

145-pin TFLGA (PTLG0145KA-A)

100-pin TFLGA (PTLG0100JA-A)

64-pin TFBGA (PTBG0064KB-A)

176-pin LFQFP (PLQP0176KB-A)

144-pin LFQFP (PLQP0144KA-B)

100-pin LFQFP (PLQP0100KB-B)

64-pin LFQFP (PLQP0064KB-C)

177-pin TFLGA (PTLG0177KA-A)

176-pin LFBGA (PLBG0176GA-A)

145-pin TFLGA (PTLG0145KA-A)

100-pin TFLGA (PTLG0100JA-A)

64-pin TFBGA (PTBG0064KB-A)

_ja

JESD51-2 and

JESD51-9 compliant

_jt

°C/W JESD51-2 and

JESD51-7 compliant

1.5

0.3

JESD51-2 and

JESD51-9 compliant

0.3

0.4

0.5

Note:

The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of

the board. For details, refer to the JEDEC standards.

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RX65N Group, RX651 Group

5. Electrical Characteristics

5.3

AC Characteristics

Table 5.10 Operating Frequency (High-Speed Operating Mode)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f

Min.

—

Typ.

—

Max.

120

60

Unit

Operating

frequency

System clock (ICLK)

MHz

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)

Peripheral module clock (PCLKD)

Flash-IF clock (FCLK)

—

60

—

60

—*¹

—

60

External bus clock (BCLK) Package of 144 pins or more

100-pin package

120

60

—

BCLK pin output

Package of 144 pins or more

100-pin package

—

60

—

30

SDRAM clock (SDCLK)

SDCLK pin output

Package of 144 pins or more

—

60

—

60

Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the flash memory contents.

Table 5.11 Operating Frequency (Low-Speed Operating Mode 1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f

Min.

—

Typ.

—

Max.

1

Unit

Operating

frequency

System clock (ICLK)

MHz

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)*¹

Peripheral module clock (PCLKD)*¹

Flash-IF clock (FCLK)

1

External bus clock (BCLK) Package of 144 pins or more

100-pin package

1

BCLK pin output

Package of 144 pins or more

100-pin package

1

SDRAM clock (SDCLK)

SDCLK pin output

Package of 144 pins or more

1

Note 1. When the 12-bit A/D converter is used, the frequency must be set to at least 1 MHz.

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5. Electrical Characteristics

Table 5.12 Operating Frequency (Low-Speed Operating Mode 2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f

Min.

32

—

32

—

Typ.

—

Max.

264

Unit

kHz

Operating

frequency

System clock (ICLK)

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)*¹

Peripheral module clock (PCLKD)*¹

Flash-IF clock (FCLK)

External bus clock (BCLK) Package of 144 pins or more

100-pin package

BCLK pin output

Package of 144 pins or more

100-pin package

SDRAM clock (SDCLK)

SDCLK pin output

Package of 144 pins or more

Note 1. The 12-bit A/D converter cannot be used.

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5. Electrical Characteristics

5.3.1

Reset Timing

Table 5.13 Reset Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

Figure 5.1

Figure 5.2

RES# pulse

width

Power-on

t_RESWP

t_RESWD

t_RESWS

1

—

ms

Deep software standby mode

0.6

0.3

Software standby mode, low-speed operating

mode 2

Programming or erasure of the code flash

memory, or programming, erasure or blank

checking of the data flash memory

t_RESWF

200

—

μs

Other than above

t_RESW

t_RESWT

t_RESW2

200

54

—

55

μs

Waiting time after release from the RES# pin reset

t_Lcyc

Figure 5.1

Internal reset time

100

108

(independent watchdog timer reset, watchdog timer reset,

software reset)

VCC

RES#

t_RESWP

Internal reset signal

(Low is valid)

t_RESWT

Figure 5.1

Reset Input Timing at Power-On

t_RESWD, t_RESWS, t_RESWF, t_RESW

RES#

Internal reset signal

(Low is valid)

t_RESWT

Figure 5.2

Reset Input Timing

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5. Electrical Characteristics

5.3.2

Clock Timing

Table 5.14 BCLK Pin Output, SDCLK Pin Output Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

t_Bcyc

Min.

Typ.

Max.

Unit

BCLK pin output cycle time

Package of 144 pins or more

100-pin package

16.6

33.2

3.3

—

5

ns

Figure 5.3

BCLK pin output high pulse width

BCLK pin output low pulse width

BCLK pin output rising time

t_CH

t_CL

t_Cr

BCLK pin output falling time

t_Cf

—

5

SDCLK pin output cycle time

SDCLK pin output high pulse width

SDCLK pin output low pulse width

SDCLK pin output rising time

SDCLK pin output falling time

Package of 144 pins or more

t_Bcyc

t_CH

t_CL

t_Cr

16.6

3.3

—

5

t_Cf

—

5

t_Bcyc, t_SDcyc

t_CH

t_Cf

BCLK pin output, SDCLK pin output

t_Cr

t_CL

Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, C = 30 pF

Figure 5.3

BCLK Pin and SDCLK Pin Output Timing

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5. Electrical Characteristics

Table 5.15 EXTAL Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

EXTAL external clock input cycle time

EXTAL external clock input frequency

EXTAL external clock input high pulse width

EXTAL external clock input low pulse width

EXTAL external clock rising time

t_EXcyc

f_EXMAIN

t_EXH

41.66

—

24

—

5

ns

MHz

ns

Figure 5.4

15.83

—

t_EXL

ns

t_EXr

ns

EXTAL external clock falling time

t_EXf

—

5

ns

t_EXcyc

t_EXH

t_EXL

EXTAL external clock input

VCC × 0.5

t_EXr

t_EXf

Figure 5.4

EXTAL External Clock Input Timing

Table 5.16 Main Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Main clock oscillation frequency

f_MAIN

8

—

24

MHz

ms

Main clock oscillator stabilization time (crystal)

Main clock oscillation stabilization wait time (crystal)

t_MAINOSC

t_MAINOSCWT

—

—*¹

—*²

Figure 5.5

ms

Note 1. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation

provided by the manufacturer for the oscillation stabilization time.

Note 2. The number of cycles selected by the value of the MOSCWTCR.MSTS[7:0] bits determines the main clock oscillation

stabilization wait time in accord with the formula below.

t_MAINOSCWT= [(MSTS[7:0] bits × 32) + 10] / f_LOCO

MOSCCR.MOSTP

t_MAINOSC

Main clock oscillator output

t_MAINOSCWT

OSCOVFSR.MOOVF

Main clock

Figure 5.5

Main Clock Oscillation Start Timing

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5. Electrical Characteristics

Table 5.17 LOCO and IWDT-Dedicated Low-Speed Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

Figure 5.6

Figure 5.7

LOCO clock cycle time

t_Lcyc

f_LOCO

t_LOCOWT

t_ILcyc

f_ILOCO

t_ILOCOWT

4.63

216

—

4.16

240

—

3.78

264

44

μs

kHz

μs

LOCO clock oscillation frequency

LOCO clock oscillation stabilization wait time

IWDT-dedicated low-speed clock cycle time

IWDT-dedicated low-speed clock oscillation frequency

9.26

108

—

8.33

120

142

7.57

132

190

μs

kHz

μs

IWDT-dedicated low-speed clock oscillation stabilization wait

time

LOCOCR.LCSTP

On-chip oscillator output

t_LOCOWT

LOCO clock

Figure 5.6

LOCO Clock Oscillation Start Timing

ILOCOCR.ILCSTP

IWDT-dedicated on-chip

oscillator output

t_ILOCOWT

OSCOVFSR.ILCOVF

IWDT-dedicated

low-speed clock

Figure 5.7

IWDT-dedicated Low-Speed Clock Oscillation Start Timing

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5. Electrical Characteristics

Table 5.18 HOCO Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f_HOCO

Min.

15.61

17.56

19.52

15.52

17.46

19.4

—

Typ.

16

Max.

16.39

18.44

20.48

16.48

18.54

20.6

Unit

Test Conditions

HOCO clock oscillation frequency

MHz

μs

–20°C ≤ T_a≤ 105°C

18

20

16

–40°C ≤ T_a< –20°C

18

20

HOCO clock oscillation stabilization wait time

HOCO clock power supply stabilization time

t_HOCOWT

t_HOCOP

105

—

149

Figure 5.8

Figure 5.9

—

150

μs

HOCOCR.HCSTP

High-speed on-chip

oscillator output

t_HOCOWT

OSCOVFSR.HCOVF

HOCO clock

Figure 5.8

HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the

HOCOCR.HCSTP Bit)

HOCOPCR.HOCOPCNT

HOCOCR.HCSTP

t_HOCOP

Internal power supply for

high-speed on-chip oscillator

Figure 5.9

High-Speed On-Chip Oscillator Power Supply Control Timing

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5. Electrical Characteristics

Table 5.19 PLL Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

PLL clock oscillation frequency

f_PLL

120

—

240

320

MHz

μs

PLL clock oscillation stabilization wait time

t_PLLWT

259

Figure 5.10

PLLCR2.PLLEN

PLL circuit output

t_PLLWT

OSCOVFSR.PLOVF

PLL clock

Figure 5.10

PLL Clock Oscillation Start Timing

Table 5.20 Sub-Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

V

= 2.0 to 3.6 V, T = T

BATT

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

—

Unit

Sub-clock oscillation frequency

f_SUB

—

32.768

—

kHz

s

1

Sub-clock oscillation stabilization time

Sub-clock oscillation stabilization wait time

t_SUBOSC

t_SUBOSCWT

*

Figure 5.11

2

—

*

s

Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation

provided by the manufacturer for the oscillation stabilization time.

Note 2. The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization

wait time in accord with the formula below.

t_SUBOSCWT= [(SSTS[7:0] bits × 16384) + 10] / f_LOCO

SOSCCR.SOSTP

t_SUBOSC

Sub-clock oscillator output

t_SUBOSCWT

OSCOVFSR.SOOVF

Sub-clock

Figure 5.11

Sub-Clock Oscillation Start Timing

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5. Electrical Characteristics

5.3.3

Timing of Recovery from Low Power Consumption Modes

Table 5.21 Timing of Recovery from Low Power Consumption Modes (1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Max.

Test

Unit

Item

Symbol Min. Typ.

Conditions

2

3

t_SBYOSCWT

{(MSTS[7:0] bit × 32) 100 + 7 / f_ICLK

+ 76} / 0.216 2n / f_MAIN

*

t_SBYSEQ*

Recovery time Crystal

from software resonator

standby mode connected to

Main clock

oscillator

operating

t_SBYMC

—

+

μs Figure 5.12

1

*

main clock

oscillator

Main clock

oscillator and

PLL circuit

operating

t_SBYPC

{(MSTS[7:0] bit × 32) 100 + 7 / f_ICLK

+ 138} / 0.216

2n / f_PLL

External clock Main clock

input to main oscillator

clock oscillator operating

t_SBYEX

352

639

100 + 7 / f_ICLK

2n / f_EXMAIN

+

Main clock

oscillator and

PLL circuit

operating

t_SBYPE

100 + 7 / f_ICLK

2n / f_PLL

Sub-clock oscillator operating

t_SBYSC

{(SSTS[7:0] bit ×

16384) + 13} / 0.216

+ 10 / f_FCLK

100 + 4 / f_ICLK

2n / f_SUE

+

High-speed

on-chip

High-speed

on-chip

t_SBYHO

454

100 + 7 / f_ICLK

2n / f_HOCO

oscillator

operating

oscillator

operating

High-speed

on-chip

t_SBYPH

741

100 + 7 / f_ICLK

2n / f_PLL

+

oscillator

operatingand

PLL circuit

operating

Low-speed on-chip oscillator

operating*⁴

t_SBYLO

338

100 + 7 / f_ICLK

2n / f_LOCO

+

Note 1. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization

waiting time (t_SBYOSCWT) and the time required for operations by the software standby release sequencer (t_SBYSEQ).

Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization

waiting time t_SBYOSCWTis selected.

Note 3. For n, the greatest value is selected from among the internal clock division settings.

Note 4. This condition applies when f_ICLK:f_FCLK= 1:1, 2:1, or 4:1.

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5. Electrical Characteristics

Oscillator

(System clock)

t_SBYOSCWT

t_SBYSEQ

Oscillator

(Other than the system clock)

ICLK

IRQ

Software standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of the system clock oscillator is slower

Oscillator

(System clock)

t_SBYSEQ

t_SBYOSCWT

Oscillator

(Other than the system clock)

t_SBYOSCWT

ICLK

IRQ

Software standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of an oscillator other than the system clock is slower

Figure 5.12

Software Standby Mode Recovery Timing

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5. Electrical Characteristics

Table 5.22 Timing of Recovery from Low Power Consumption Modes (2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Recovery time from deep software standby mode

t_DSBY

—

0.9

24

ms

Figure 5.13

Wait time after recovery from deep software standby mode

t_DSBYWT

23

t_Lcyc

Oscillator

IRQ

Deep software standby reset

(Low is valid)

Internal reset

(Low is valid)

Deep software standby mode

t_DSBY

t_DSBYWT

Reset exception handling start

Figure 5.13

Deep Software Standby Mode Recovery Timing

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5. Electrical Characteristics

5.3.4

Control Signal Timing

Table 5.23 Control Signal Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

t_NMIW

Min.*¹

200

Typ.

—

Max.

—

Unit

ns

Test Conditions*¹

NMI pulse width

t_PBcyc× 2 ≤ 200 ns, Figure 5.14

t_PBcyc× 2 > 200 ns, Figure 5.14

t_PBcyc× 2 ≤ 200 ns, Figure 5.15

t_PBcyc× 2 > 200 ns, Figure 5.15

t_PBcyc× 2

200

—

ns

IRQ pulse width

t_IRQW

—

ns

t_PBcyc× 2

—

ns

Note 1. t_PBcyc: PCLKB cycle

NMI

t_NMIW

Figure 5.14

NMI Interrupt Input Timing

IRQ

t_IRQW

Figure 5.15

IRQ Interrupt Input Timing

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5. Electrical Characteristics

5.3.5

Bus Timing

Table 5.24 Bus Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Item

Symbol

t_AD

Min.

—

12.5

0

Max.

12.5

—

Unit

ns

Test Conditions

Address delay time

Figure 5.16 to

Figure 5.21

Byte control delay time

CS# delay time

t_BCD

t_CSD

ALE delay time

t_ALED

t_RSD

RD# delay time

Read data setup time

t_RDS

Read data hold time

t_RDH

—

WR# delay time

t_WRD

t_WDD

t_WDH

t_WTS

—

0

12.5

—

Write data delay time

Write data hold time

WAIT# setup time

12.5

0

—

Figure 5.22

Figure 5.23

WAIT# hold time

t_WTH

t_AD2

—

Address delay time 2 (SDRAM)

CS# delay time 2 (SDRAM)

DQM delay time (SDRAM)

CKE delay time (SDRAM)

Read data setup time 2 (SDRAM)

Read data hold time 2 (SDRAM)

Write data delay time 2 (SDRAM)

Write data hold time 2 (SDRAM)

WE# delay time (SDRAM)

RAS# delay time (SDRAM)

CAS# delay time (SDRAM)

1

12.5

—

t_CSD2

t_DQMD

t_CKED

t_RDS2

t_RDH2

t_WDD2

t_WDH2

t_WED

t_RASD

t_CASD

1

10

0

—

1

12.5

—

1

12.5

1

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5. Electrical Characteristics

Data cycle

T_end

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_n1

T_n2

T_W5

BCLK

t_AD

Address bus

t_RDSt_RDH

t_AD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_RSD

Data read

(RD#)

t_CSD

Chip select

(CS1#)

Figure 5.16

Address/Data Multiplexed Bus Read Access Timing

Data cycle

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_end

T_n1

T_n2

t_WDH

t_WRD

T_n3

T_W5

BCLK

t_AD

Address bus

t_AD

t_WDD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_WRD

Data write

(WRm#)

t_CSD

Chip select

(CS1#)

Figure 5.17

Address/Data Multiplexed Bus Write Access Timing

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5. Electrical Characteristics

CSRWAIT:2

RDON:1

CSON:0

CSROFF:2

T_W1

T_W2

T_end

T_n1

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

1-write strobe mode

A23 to A1

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_RSD

RD# (Read)

t_RDS

t_RDH

D31 to D0 (Read)

Figure 5.18

External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)

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5. Electrical Characteristics

CSWWAIT:2

WRON:1

WDON:1 ^*1

CSWOFF:2

WDOFF:1 ^*1

T_n1

CSON:0

T_W1

T_W2

T_end

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

1-write strobe mode

A23 to A1

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_WRD

WR1# to WR0#, WR# (Write)

t_WDD

t_WDH

D31 to D0 (Write)

Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.

Figure 5.19

External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)

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5. Electrical Characteristics

CSRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSROFF:2

CSON:0

T_W1

T_W2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_n1

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

A23 to A1

1-write strobe mode

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_RSD

RD# (Read)

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

D31 to D0 (Read)

Figure 5.20

External Bus Timing/Page Read Cycle (Bus Clock Synchronized)

CSPWWAIT:2

CSWWAIT:2

WRON:1

WDON:1 ^*1

CSON:0

CSPWWAIT:2

CSWOFF:2

WRON:1

WDOFF:1 ^*1

T_dw1

WDOFF:1 ^*1

T_n1

WDOFF:1 ^*1

T_dw1

WDON:1 ^*1

T_pw1

WDON:1 ^*1

T_pw1

T_W2

T_end

T_pw2

T_W1

T_end

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

A23 to A1

1-write strobe mode

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_WRD

WR1# to WR0#, WR# (Write)

D31 to D0 (Write)

t_WDD

t_WDH

Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.

Figure 5.21

External Bus Timing/Page Write Cycle (Bus Clock Synchronized)

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5. Electrical Characteristics

CSRWAIT:3

CSWWAIT:3

T_W1

T_W2

T_W3

(T_end

)

T_end

T_n1

T_n2

BCLK

A23 to A0

CS7# to CS0#

RD# (Read)

WR# (Write)

External wait

t_WTSt_WTHt_WTSt_WTH

WAIT#

Figure 5.22

External Bus Timing/External Wait Control

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5. Electrical Characteristics

SDRAM command

SDCLK pin

ACT

RD

PRA

t_AD2

Row

address

A18 to A0

AP*¹

Column address

t_AD2

PRA

command

t_CSD2

t_CSD2t_CSD2

SDCS#

RAS#

CAS#

t_RASD

t_CASD

t_WED

WE#

CKE

(High)

t_DQMD

DQMn

t_RDS2t_RDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 5.23

SDRAM Space Single Read Bus Timing

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5. Electrical Characteristics

SDRAM command

SDCLK pin

ACT

WR

PRA

t_AD2

Row

address

A18 to A0

AP*¹

Column address

t_AD2

PRA

command

t_CSD2

SDCS#

RAS#

CAS#

t_RASD

t_CASD

t_WED

WE#

CKE

(High)

t_DQMD

DQMn

t_WDD2

t_WDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 5.24

SDRAM Space Single Write Bus Timing

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5. Electrical Characteristics

ACT

RD RD RD RD PRA

SDCLK pin

t_AD2

t_AD2t_AD2

t_AD2t_AD2t_AD2t_AD2

t_AD2

Row

address

C0

(column address)

C1

C2

C3

A18 to A0

AP*¹

t_AD2t_AD2

t_AD2

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2

SDCS#

t_RASDt_RASD

t_RASD

RAS#

CAS#

WE#

t_CASD

t_WED

(High)

CKE

t_DQMD

DQMn

t_RDS2t_RDH2

t_RDS2

t_RDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 5.25

SDRAM Space Multiple Read Bus Timing

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5. Electrical Characteristics

ACT

WR WR WR PRA

WR

SDCLK pin

t_AD2t_AD2t_AD2

t_AD2t_AD2

C0

Row

address

C1

C2

C3

A18 to A0

AP*¹

(column address)

t_AD2

t_AD2t_AD2

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2t_CSD2

SDCS#

t_RASDt_RASD

t_RASDt_RASDt_RASD

RAS#

CAS#

t_CASD

t_WED

WE#

CKE

(High)

t_DQMD

DQMn

t_WDD2t_WDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command

(Precharge-sel) for SDRAM.

Figure 5.26

SDRAM Space Multiple Write Bus Timing

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5. Electrical Characteristics

ACT

RD

PRA

ACT

RD

PRA

SDRAM command

SDCLK pin

t

AD2

Row

address

C0

(column address 0)

C1

C2

C3

R1

C4

C5

C6

C7

A18 to A0

t

AD2

t

AD2

AP*¹

PRA

command

PRA

command

t

CSD2

SDCS#

RAS#

CAS#

WE#

t

t t

RASD RASD

RASD RASD RASD RASD

t

CASD

WED

t

WED

(High)

CKE

t

DQMD

DQMn

t

t t

RDS2 RDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 5.27

SDRAM Space Multiple Read Line Stride Bus Timing

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5. Electrical Characteristics

MRS

SDRAM command

SDCLK pin

A18 to A0

AP*¹

t

AD2

t

CSD2

SDCS#

RAS#

t

RASD

CASD

RASD

CASD

t

CAS#

t

WED

WE#

CKE

(High)

DQMn

(Hi-Z)

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 5.28

SDRAM Space Mode Register Set Bus Timing

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5. Electrical Characteristics

SDRAM command

SDCLK pin

Ts (RFA)

(RFS)

(RFX)

(RFA)

t

AD2

A18 to A0

AP*¹

t

CSD2 CSD2

CSD2

RASD

CSD2

RASD

CSD2

SDCS#

RAS#

CAS#

WE#

t

t t

RASD RASD RASD

RASD RASD

t

t t

CASD CASD CASD

CASD

(High)

t

CKED

CKE

t

DQMD

DQMn

(Hi-Z)

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 5.29

SDRAM Space Self-Refresh Bus Timing

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5. Electrical Characteristics

5.3.6

EXDMAC Timing

Table 5.25 EXDMAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.

Max.

Unit

EXDMAC

EDREQ setup time

EDREQ hold time

EDACK delay time

t_EDRQS

t_EDRQH

t_EDACD

13

2

—

13

ns

Figure 5.30

—

Figure 5.31,

Figure 5.32

BCLK pin

t_EDRQSt_EDRQH

EDREQ0,

EDREQ1

Figure 5.30

EDREQ0 and EDREQ1 Input Timing

BCLK pin

t_EDACD

EDACK0,

EDACK1

Figure 5.31

EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)

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5. Electrical Characteristics

BCLK pin

t_EDACD

EDACK0,

EDACK1

Figure 5.32

EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)

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5. Electrical Characteristics

5.3.7

Timing of On-Chip Peripheral Modules

Table 5.26 I/O Port Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_PRW

Min.

1.5

Max.

—

Conditions

I/O ports

Input data pulse width

t_PBcyc

Figure 5.33

Note 1. t_PBcyc: PCLKB cycle

PCLKB

Port

t_PRW

Figure 5.33

I/O Port Input Timing

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5. Electrical Characteristics

Table 5.27 TPU Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_TICW

Min.

1.5

Max.

—

Conditions

TPU

Input capture input pulse

width

Single-edge

setting

t_PBcyc

Figure 5.34

Both-edge

setting

2.5

1.5

2.5

—

Timer clock pulse width

Single-edge

setting

t_TCKWH,

t_TCKWL

t_PBcyc

Figure 5.35

Both-edge

setting

Phase counting

mode

Note 1. t_PBcyc: PCLKB cycle

PCLKB

Input capture

input

t_TICW

Figure 5.34

TPU Input Capture Input Timing

PCLKB

TCLKA to

TCLKD

t_TCKWL

t_TCKWH

Figure 5.35

TPU Clock Input Timing

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5. Electrical Characteristics

Table 5.28 TMR Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

Min.

1.5

Max.

—

Conditions

TMR

Timer clock pulse width

Single-edge

setting

t_TMCWH,

t_TMCWL

t_PBcyc

Figure 5.36

Both-edge

setting

2.5

—

Note 1. t_PBcyc: PCLKB cycle

PCLKB

TMCI0 to TMCI3

t_TMCWL

t_TMCWH

Figure 5.36

TMR Clock Input Timing

Table 5.29 CMTW Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.

1.5

Max.

—

Unit*¹

t_PBcyc

CMTW

Input capture input pulse

width

Single-edge

setting

t_CMTWTICW

Figure 5.37

Both-edge

setting

2.5

—

Note 1. t_PBcyc: PCLKB cycle

PCLKB

Input capture

input

t_CMTWICW

Figure 5.37

CMTW Input Capture Input Timing

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5. Electrical Characteristics

Table 5.30 MTU3 Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_MTICW

Min.

1.5

Max.

—

Conditions

MTU3

Input capture input pulse

width

Single-edge

setting

t_PAcyc

Figure 5.38

Both-edge

setting

2.5

1.5

2.5

—

Timer clock pulse width

Single-edge

setting

t_MTCKWH,

t_MTCKWL

t_PAcyc

Figure 5.39

Both-edge

setting

Phase counting

mode

Note 1. t_PAcyc: PCLKA cycle

PCLKA

Input capture

input

t_MTICW

Figure 5.38

MTU3 Input Capture Input Timing

PCLKA

MTCLKA to

MTCLKD

t_MTCKWL

t_MTCKWH

Figure 5.39

MTU3 Clock Input Timing

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5. Electrical Characteristics

Table 5.31 POE3 Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_POEW

Min.

1.5

Max.

—

Conditions

POE

POE# input pulse width

t_PBcyc

Figure 5.40

Note 1. t_PBcyc: PCLKB cycle

PCLKB

POEn# input

t_POEW

Figure 5.40

POE# Input Timing

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5. Electrical Characteristics

Table 5.32 A/D Converter Trigger Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_TRGW

Min.

1.5

Max.

—

Conditions

A/D

converter

A/D converter trigger input pulse width

t_PBcyc

Figure 5.41

Note 1. t_PBcyc: PCLKB cycle

PCLKB

ADTRG0#,

ADTRG1#

t_TRGW

Figure 5.41

A/D Converter Trigger Input Timing

Table 5.33 CAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

2

Item*^1,

*

Symbol

t_CACREF

Min.*^1,

*

Max.

—

Unit

ns

CAC

CACREF input pulse width

t

_PBcyc≤ t_cac

_PBcyc> t_cac

4.5 t_cac

+

3 t_PBcyc

5 t_cac

6.5 t_PBcyc

t

+

—

Note 1. t_PBcyc: PCLKB cycle

Note 2. _cac: CAC count clock source cycle

t

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5. Electrical Characteristics

Table 5.34 SCIg, SCIh, and SCIi Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit^*1

Item

SCIg, SCIh Input clock cycle

Symbol

t_Scyc

Min.

Max.

Conditions

Asynchronous

4

6

—

t_PBcycFigure 5.42

Clock

synchronous

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t_SCKW

t_SCKr

t_SCKf

t_Scyc

0.4

—

8

0.6

5

t_Scyc

ns

5

ns

Asynchronous^*2

—

t_PBcyc

Clock

4

synchronous

Output clock pulse width

Output clock rise time

Output clock fall time

Transmit data delay time

t_SCKW

t_SCKr

t_SCKf

t_TXD

0.4

—

0.6

5

t_Scyc

ns

5

ns

Clock

synchronous

28

ns

Figure 5.43

Receive data setup time

Receive data hold time

Input clock cycle

Clock

synchronous

t_RXS

t_RXH

t_Scyc

15

5

—

Clock

synchronous

SCIi

Asynchronous

4

—

t_PAcycFigure 5.42

Clock

12

synchronous

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t_SCKW

t_SCKr

t_SCKf

t_Scyc

0.4

—

8

0.6

5

t_Scyc

ns

5

ns

Asynchronous^*2

—

t_PAcyc

Clock

8

synchronous

Output clock pulse width

Output clock rise time

Output clock fall time

Transmit data delay time

t_SCKW

t_SCKr

t_SCKf

t_TXD

0.4

—

20

0.6

5

t_Scyc

ns

5

ns

Master

Slave

15

28

—

ns

Figure 5.43

Receive data setup time

Receive data hold time

Clock

synchronous

t_RXS

t_RXH

Clock

5

—

synchronous

Note 1. t_PBcyc: PCLKB cycle; t_PAcyc: PCLKA cycle

Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1

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5. Electrical Characteristics

t_SCKW

t_SCKr

t_SCKf

SCKn

(n = 0 to 12)

SCK Clock Input Timing

SCKn

t_Scyc

Figure 5.42

t_TXD

TxDn

t_RXSt_RXH

RxDn

n = 0 to 12

Figure 5.43

SCI Input/Output Timing: Clock Synchronous Mode

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5. Electrical Characteristics

Table 5.35 RSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Item

Symbol

t_SPcyc

Min.*¹

Max.*¹

Unit*¹

Conditions*²

RSPI RSPCK clock cycle

Master

Slave

2

4

4096

—

t_PAcycFigure 5.44

RSPCK clock high pulse

width

Master

t_SPCKWH

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2 – 3

ns

Slave

Master

Slave

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2

—

RSPCK clock low pulse

width

t_SPCKWL

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2 – 3

ns

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2

RSPCK clock rise/fall time Output

Input

t_SPCKr,

t_SPCKf

—

6

5

ns

μs

1

Data input setup time

Master

Slave

t_SU

—

ns

Figure 5.45 to

Figure 5.50

8.3

0

Data input hold time

Master PCLKA divi-

sion ratio set to

1/2

t_HF

ns

PCLKA divi-

sion ratio set to

a value other

than 1/2

t_H

t_PAcyc

—

Slave

8.3

—

8

SSL setup time

Master

Slave

t_LEAD

t_LAG

t_OD

1

t_SPcyc

t_PAcyc

t_SPcyc

t_PAcyc

ns

6

—

8

SSL hold time

Master

Slave

1

6

—

6.3

28

—

Data output delay time

Data output hold time

Master

Slave

—

Master

Slave

t_OH

0

ns

0

Successive transmission

delay time

Master

t_TD

t_SPcyc+ 2 × t_PAcyc

8 × t_SPcyc

+ 2 × t_PAcyc

Slave

Output

Input

6 × t_PAcyc

—

5

MOSI and MISO

rise/fall time

t

_Dr,t_Df

—

ns

μs

ns

μs

ns

1

SSL

rise/fall time

Output

Input

t_SSLr,

5

tSSLf

1

Slave access time

t_SA

2 × t_PAcyc

+ 28

Figure 5.49,

Figure 5.50

Slave output release time

t_REL

—

2 × t_PAcyc

+ 28

ns

Note 1. t_PAcyc: PCLKA cycle

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All RSPI AC timings are measured in combination with the pins in the same group.

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5. Electrical Characteristics

Table 5.36 Simple SPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_SPcyc

Min.

Max.

Conditions

Simple

SPI

SCK clock cycle output (master)

SCK clock cycle input (slave)

SCK clock high pulse width

SCK clock low pulse width

SCK clock rise/fall time

Data input setup time

Data input hold time

4

8

65536

0.6

20

t_PAcyc

Figure 5.44

t_SPCKWH

t_SPCKWL

t_SPCKr,t_SPCKf

t_SU

0.4

—

t_SPcyc

ns

33.3

1

—

ns

Figure 5.45 to

Figure 5.50

t_H

—

ns

SS input setup time

t_LEAD

—

t_SPcyc

ns

SS input hold time

t_LAG

1

—

Data output delay time

Data output hold time

Data rise/fall time

t_OD

—

33.3

—

t_OH

–10

—

ns

t

_Dr,t_Df

t_SSLr,t_SSLf

t_SA

16.6

5

ns

SS input rise/fall time

Slave access time

—

ns

—

t_PBcyc

Figure 5.49,

Figure 5.50

Slave output release time

t_REL

—

5

Note 1. t_PAcyc: PCLKA cycle, t_PBcyc: PCLKB cycle

t_SPCKr

t_SPCKf

t_SPCKWH

Simple SPI

RSPI

RSPCKA

master select

output

V_OH

V_OL

V_OH

SCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

SCKn

slave select input

RSPCKA

slave select input

V_IL

t_SPCKWL

V_IL

(n = 0 to 12)

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Figure 5.44

RSPI Clock Timing and Simple SPI Clock Timing

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5. Electrical Characteristics

Simple SPI

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

SCKn

CKPOL = 0

output

RSPCKA

CPOL = 1

output

SCKn

CKPOL = 1

output

t_SU

t_H

MISOA

input

SMISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIA

output

SMOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 12)

Figure 5.45

RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other

Than 1/2) and Simple SPI Timing (Master, CKPH = 1)

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

RSPCKA

CPOL = 1

output

t_SU

t_HF

MISOA

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIA

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Figure 5.46

RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to 1/2)

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5. Electrical Characteristics

Simple SPI

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

SCKn

CKPOL = 1

output

RSPCKA

CPOL = 1

output

SCKn

CKPOL = 0

output

t_SU

t_H

MISOA

input

SMISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIA

output

SMOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 12)

Figure 5.47

RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to a Value Other

Than 1/2) and Simple SPI Timing (Master, CKPH = 0)

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

RSPCKA

CPOL = 1

output

t_SU

t_HF

t_H

MISOA

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIA

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Figure 5.48

RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2)

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5. Electrical Characteristics

Simple SPI

RSPI

t_TD

SSLA0

input

SSn#

input

t_LEAD

t_LAG

RSPCKA

CPOL = 0

input

SCKn

CKPOL = 0

input

RSPCKA

CPOL = 1

input

SCKn

CKPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOA

output

SMISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIA

input

SMOSIn

input

MSB IN

DATA

(n = 0 to 12)

Figure 5.49

RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)

Simple SPI

RSPI

t_TD

SSLA0

input

SSn#

input

t_LEAD

t_LAG

RSPCKA

CPOL = 0

input

SCKn

CKPOL = 1

input

RSPCKA

CPOL = 1

input

SCKn

CKPOL = 0

input

t_SA

t_OH

t_OD

t_REL

LSB OUT

(Last data)

MISOA

output

SMISOn

output

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIA

input

SMOSIn

input

MSB IN

DATA

LSB IN

(n = 0 to 12)

Figure 5.50

RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)

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5. Electrical Characteristics

Table 5.37 QSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

3

High-drive output is selected by the driving ability control register.*

Test

Unit*¹

Item

Symbol

Min.

Max.

Conditions*²

QSPI

QSPCLK clock cycle

Data input setup time

Data input hold time

SS setup time

t_QScyc

t_Su

2

6.5

5

4080

—

t_PBcyc

ns

Figure 5.51

Figure 5.52,

Figure 5.53

t_IH

—

ns

t_LEAD

t_LAG

t_OD

1.5

1

8.5

8

t_QScyc

ns

SS hold time

Data output delay time

Data output hold time

Successive transmission delay time

—

–5

1

10.0

—

t_OH

ns

t_TD

8

t_QScyc

Note 1. t_PBcyc: PCLKB cycle

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All QSPI AC timings are measured in combination with the pins in the same group.

Note 3. In the G-version products, the AC characteristics are measured by setting the drive capacity control register 2 corresponding the

QSPCLK pin as a high-speed interface high-drive output.

QSPCLK

output

t_QScyc

Figure 5.51

QSPI Clock Timing

t_TD

QSSL

output

t_LEAD

t_LAG

QSPCLK

CPOL = 0

output

QSPCLK

CPOL = 1

output

t_SU

t_IH

QMI,

QIO0 to QIO3

input

MSB IN

DATA

LSB IN

t_OH

t_OD

QMO,

QIO0 to QIO3

output

MSB OUT

DATA

LSB OUT

IDLE

Figure 5.52

Transmit/Receive Timing (CPHA = 0)

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5. Electrical Characteristics

t_TD

QSSL

output

t_LEAD

t_LAG

QSPCLK

CPOL = 0

output

QSPCLK

CPOL = 1

output

t_SUt_IH

MSB IN

QMI,

QIO0 to QIO3

input

DATA

LSB IN

t_OH

t_OD

QMO,

QIO0 to QIO3

output

MSB OUT

DATA

LSB OUT

IDLE

Figure 5.53

Transmit/Receive Timing (CPHA = 1)

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5. Electrical Characteristics

Table 5.38 RIIC Timing (1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

High-drive output is selected by the driving ability control register.

Test

Conditions

2

Item

Symbol

Min.*^1,

*

Max.

Unit

RIIC

(Standard-mode,

SMBus)

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6(12) × t_IICcyc+ 1300

—

ns Figure 5.54

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

SCL, SDA input spike pulse removal time

SDA input bus free time

3(6) × t_IICcyc+ 300

—

ns

pF

ns

3(6) × t_IICcyc+ 300

—

ICFER.FMPE = 0

—

1000

t_Sf

—

300

t_SP

0

3(6) × t_IICcyc+ 300

t_IICcyc+ 300

1000

1(4) × t_IICcyc

t_BUF

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

—

Start condition input hold time

Restart condition input setup time

Stop condition input setup time

Data input setup time

—

1000

—

t_IICcyc+ 50

0

—

Data input hold time

—

SCL, SDA capacitive load

SCL input cycle time

—

400

—

RIIC

(Fast-mode)

ICFER.FMPE = 0

t_SCL

t_SCLH

t_SCLL

t_Sr

6(12) × t_IICcyc+ 600

3(6) × t_IICcyc+ 300

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

—

20 × (External pull-up

voltage/5.5V)

300

SCL, SDA input fall time

t_Sf

20 × (External pull-up

voltage/5.5V)

300

ns

SCL, SDA input spike pulse removal time

SDA input bus free time

t_SP

0

1(4) × t_IICcyc

ns

pF

t_BUF

3(6) × t_IICcyc+ 300

—

Start condition input hold time

Restart condition input setup time

Stop condition input setup time

Data input setup time

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

t_IICcyc+ 300

300

—

300

—

t_IICcyc+ 50

—

Data input hold time

0

—

SCL, SDA capacitive load

—

400

Note:

t_IICcyc: RIIC internal reference clock (IIC) cycle

Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by

the setting ICFER.NFE = 1.

Note 2. Cb is the total capacitance of the bus lines.

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5. Electrical Characteristics

Table 5.39 RIIC Timing (2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

High-drive output is selected by the driving ability control register.

Test

Conditions

2

Item

Symbol

Min.*^1,

*

Max.

Unit

RIIC

(Fast-mode+)

ICFER.FMPE = 1

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6(12) × t_IICcyc+ 240

—

ns

pF

ns

pF

ns

pF

Figure 5.54

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

SCL, SDA input spike pulse removal time

SDA input bus free time

Start condition input hold time

Restart condition input setup time

Stop condition input setup time

Data input setup time

3(6) × t_IICcyc+ 120

—

3(6) × t_IICcyc+ 120

—

120

t_Sf

—

120

t_SP

0

1(4) × t_IICcyc

t_BUF

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

3(6) × t_IICcyc+ 120

—

t_IICcyc+ 120

120

—

120

—

t_IICcyc+ 20

—

Data input hold time

0

—

0

—

SCL, SDA capacitive load

SDA input rise time

550

1000

300

4 × t_PBcyc

—

Simple IIC

(Standard-mode)

t_Sr

SDA input fall time

t_Sf

SDA input spike pulse removal time

Data input setup time

t_SP

t_SDAS

t_SDAH

C_b

250

0

Data input hold time

—

SCL, SDA capacitive load

SCL, SDA input rise time

SCL, SDA input fall time

SCL, SDA input spike pulse removal time

Data input setup time

—

0

400

300

4 × t_PBcyc

—

Simple IIC

(Fast-mode)

t_Sr

t_Sf

t_SP

t_SDAS

t_SDAH

C_b

100

0

Data input hold time

—

SCL, SDA capacitive load

—

400

Note:

t_IICcyc: RIIC internal reference clock (IIC) cycle, t_PBcyc: PCLKB cycle

Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by

the setting ICFER.NFE = 1.

Note 2. Cb is the total capacitance of the bus lines.

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5. Electrical Characteristics

V_IH

V_IL

SDA0 to SDA2

t_BUF

t_SCLH

t_STAS

t_STOS

t_STAH

t_SP

SCL0 to SCL2

P*¹

S*¹

Sr*¹

t_SCLL

t_Sr

t_Sf

t_SDAS

t_SCL

t_SDAH

Test conditions

Note 1. S, P, and Sr indicate the following conditions.

S: Start condition

V_IH= VCC × 0.7, V_IL= VCC × 0.3

V_OL= 0.6 V, I_OL= 6 mA (ICFER.FMPE = 0)

V_OL= 0.4 V, I_OL= 15 mA (ICFER.FMPE = 1)

P: Stop condition

Sr: Restart condition

Figure 5.54

RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output

Timing

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RX65N Group, RX651 Group

5. Electrical Characteristics

Table 5.40 MMC Host Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Item

MMCIF MMC_CLK clock cycle

Symbol

Min.*¹

Max.

Unit

Conditions*²

t_MMCPP

t_MMCWH

t_MMCWL

t_MMCLH

2 × t_PBcyc

6.5

—

3

ns Figure 5.55

MMC_CLK clock high level width

MMC_CLK clock low level width

MMC_CLK clock rising time

MMC_CLK clock falling time

ns

6.5

—

t_MMCHL

—

3

MMC_CMD, MMC_D7 to MMC_D0 output data delay

(data transfer mode)

t_MMCODLY

–6.6

6.6

MMC_CMD, MMC_D7 to MMC_D0 input data setup

MMC_CMD, MMC_D7 to MMC_D0 input data hold

t_MMCISU

t_MMCIH

8

—

ns

2.5

Note 1. t_PBcyc: PCLKB cycle

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All MMC AC timings are measured in combination with the pins in the same group.

t_MMCPP

t_MMCWL

t_MMCWH

MMC_CLK

t_MMCHL

t_MMCLH

t_MMCISUt_MMCIH

MMC_CMD,

MMC_D7 to MMC_D0 input

MMC_CMD,

MMC_D7 to MMC_D0 output

t_MMCODLY(max)

t_MMCODLY(min)

Figure 5.55

MMC Interface

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RX65N Group, RX651 Group

5. Electrical Characteristics

Table 5.41 ETHERC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit

Item

Symbol

Min.

Max.

Conditions

ETHERC

(RMII)

REF50CK cycle time

T_ck

—

20

—

35

0.5

2.5

3

—

ns

MHz

%

Figure 5.56 to

Figure 5.58

REF50CK frequency Typ. 50 MHz

REF50CK duty

50 + 100 ppm

—

65

3.5

15.0

—

REF50CK rise/fall time

T_ckr/ckf

T_co

ns

RMII0_xxxx*¹output delay time

RMII0_xxxx*²setup time

RMII0_xxxx*²hold time

T_su

T_hd

1

—

RMII0_xxxx*^1,*²rise/fall time

ET0_WOL output delay time

ET0_TX_CLK cycle time

ET0_TX_EN output delay time

ET0_ETXD0 to ET0_ETXD3 output delay time

ET0_CRS setup time

T_r/T_f

t_WOLd

t_Tcyc

t_TENd

t_MTDd

t_CRSs

t_CRSh

t_COLs

t_COLh

t_TRcyc

t_RDVs

t_RDVh

t_MRDs

t_MRDh

t_RERs

t_RERh

t_WOLd

0.5

1

5

23.5

—

Figure 5.60

—

ETHERC

(MII)

40

1

20

—

Figure 5.61

1

10

40

10

1

ET0_CRS hold time

—

ET0_COL setup time

—

Figure 5.62

ET0_COL hold time

—

ET0_RX_CLK cycle time

ET0_RX_DV setup time

—

Figure 5.63

ET0_RX_DV hold time

—

ET0_ERXD0 to ET0_ERXD3 setup time

ET0_ERXD0 to ET0_ERXD3 hold time

ET0_RX_ER setup time

—

Figure 5.64

Figure 5.65

ET0_RX_ER hold time

—

ET0_WOL output delay time

23.5

Note 1. RMII0_TXD_EN, RMII0_TXD1, RMII0_TXD0

Note 2. RMII0_CRS_DV, RMII0_RXD1, RMII0_RXD0, RMII0_RX_ER

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5. Electrical Characteristics

Tck

90%

Tckr

REF50CK 50%

Tckf

Tco

10%

Tsu

Thd

Tr

Tf

70%

Change

in signal

level

Change

in signal

level

RMII0_xxxx^*150%

Change in

signal level

Signal

30%

Note 1. RMII0_TXD_EN, RMII0_TXD1, RMII0_TXD0, RMII0_CRS_DV, RMII0_RXD1, RMII0_RXD0, RMII0_RX_ER

Figure 5.56

Timing with the REF50CK and RMII Signals

T_CK

REF50CK

T_CO

RMII0_TXD_EN

T_CO

RMII0_TXD1,

RMII0_TXD0

Preamble

SFD

DATA

CRC

Figure 5.57

RMII Transmission Timing

REF50CK

Tsu

Thd

RMII0_CRS_DV

Thd

Tsu

RMII0_RXD1,

RMII0_RXD0

Preamble

DATA

CRC

SFD

RMII0_RX_ER

L

Figure 5.58

RMII Reception Timing (Normal Operation)

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5. Electrical Characteristics

REF50CK

RMII0_CRS_DV

RMII0_RXD1,

RMII0_RXD0

Preamble

SFD

DATA

xxxx

Thd

Tsu

RMII0_RX_ER

Figure 5.59

RMII Reception Timing (Error Occurrence)

REF50CK

t_WOLd

ET0_WOL

Figure 5.60

WOL Output Timing (RMII)

ET0_TX_CLK

t_TENd

ET0_TX_EN

t_MTDd

ET0_ETXD[3:0]

ET0_TX_ER

Preamble

SFD

DATA

CRC

t_CRSs

t_CRSh

ET0_CRS

ET0_COL

Figure 5.61

MII Transmission Timing (Normal Operation)

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5. Electrical Characteristics

ET0_TX_CLK

ET0_TX_EN

ET0_ETXD[3:0]

ET0_TX_ER

ET0_CRS

Preamble

JAM

t_COLs

t_COLh

ET0_COL

Figure 5.62

MII Transmission Timing (Conflict Occurrence)

ET0_RX_CLK

t_RDVs

t_RDVh

ET0_RX_DV

t_MRDh

t_MRDs

ET0_ERXD[3:0]

ET0_RX_ER

Preamble

SFD

DATA

CRC

Figure 5.63

MII Reception Timing (Normal Operation)

ET0_RX_CLK

ET0_RX_DV

ET0_ERXD[3:0]

Preamble

SFD

DATA

xxxx

t_RERh

t_RERs

ET0_RX_ER

Figure 5.64

MII Reception Timing (Error Occurrence)

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5. Electrical Characteristics

ET0_RX_CLK

ET0_WOL

t_WOLd

Figure 5.65

WOL Output Timing (MII)

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5. Electrical Characteristics

Table 5.42 PDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF

,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.*¹

Max.

Unit

PDC PIXCLK input cycle time

PIXCLK input high pulse width

PIXCLK input low pulse width

PIXCLK rising time

t_PIXcyc

t_PIXH

37

—

5

ns

Figure 5.66

10

t_PIXL

t_PIXr

—

PIXCLK falling time

t_PIXf

—

5

PCKO output cycle time

PCKO output high pulse width

PCKO output low pulse width

PCKO rising time

t_PCKcyc

t_PCKH

t_PCKL

t_PCKr

2 × t_PBcyc

—

5

Figure 5.67

Figure 5.68

(t_PCKcyc– t_PCKr– t_PCKf)/2 – 3

—

10

5

PCKO falling time

t_PCKf

5

VSYNC/HSYNC input setup time

VSYNC/HSYNC input hold time

PIXD input setup time

t_SYNCS

t_SYNCH

t_PIXDS

t_PIXDH

—

10

5

PIXD input hold time

Note 1. t_PBcyc: PCLKB cycle

t_PIXcyc

t_PIXH

t_PIXf

PIXCLK input

t_PIXr

t_PIXL

Figure 5.66

PDC Input Clock Timing

t_PCKcyc

t_PCKH

t_PCKf

PCKO pin output

t_PCKr

t_PCKL

Figure 5.67

PDC Output Clock Timing

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5. Electrical Characteristics

PIXCLK

VSYNC

t_SYNCS

t_SYNCH

t_SYNCS

t_SYNCH

HSYNC

t_PIXDS

t_PIXDH

PIXD7 to PIXD0

Figure 5.68

PDC AC Timing

Table 5.43 GLCDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

t_Ecyc

t_WL

Min.

—

Typ.

—

Max.

30*¹

0.55

30*¹

0.6

Unit

MHz

t_Ecyc

Test Conditions

Figure 5.69

LCD_EXTCLK Input clock frequency

LCD_EXTCLK Input clock Low pulse width

LCD_EXTCLK Input clock High pulse width

LCD_CLK Output clock frequency

LCD_CLK Output clock Low pulse width

LCD_CLK Output clock High pulse width

LCD data output Delay timing

0.45

—

t_WH

—

t_Lcyc

t_LOL

t_LOH

t_DD

—

MHz

t_Lcyc

ns

Figure 5.70

Figure 5.71

0.4

—

0.4

—

0.6

–3.5*²

—

4*²

Note 1. Parallel RGB888,666,565: Max. 27 MHz

Serial RGB888: Max. 30 MHz (4x speed)

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All GLCDC AC timings are measured in combination with the pins in the same

group.

If we use group “-A” and “-B” combination, “LCD data output Delay timing (t_DD)” is Min = –5.0 ns, Max = 5.5 ns.

t_Dcyc,t_Ecyc

t_WH

t_WL

V_IHV_IH

1/2 Vcc

V_ILV_IL

LCD_EXTCLK

Figure 5.69

LCD_EXTCLK Clock Input Timing

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5. Electrical Characteristics

t_Lcyc

t_LOL

t_LOH

LCD_CLK

t_LOF

t_LOR

Figure 5.70

LCD_CLK Clock Output Timing

LCD_CLK

t_DD

Output on

falling edge

LCD_DATA23 to

LCD_DATA0,

LCD_TCON3 to

LCD_TCON0

t_DD

Output on

rising edge

Figure 5.71

LCD Output Data Timing

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5. Electrical Characteristics

Table 5.44 SDHI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.*

,

OH

OL

1

Item

Symbol

t_PP(SD)

Min.

20

Max.

—

3

Unit

ns

Test Conditions*²

Figure 5.72

SDHI

SDHI_CLK pin output cycle time

SDHI_CLK pin output high pulse width

SDHI_CLK pin output low pulse width

SDHI_CLK pin output rise time

SDHI_CLK pin output fall time

t_WH(SD)0.4 × t_PP(SD)

t_WL(SD)

t_TLH(SD)

t_THL(SD)

t_ODLY(SD)

0.4 × t_PP(SD)

—

3

Output data delay time (data transfer mode) for

SDHI_CMD and SDHI_D0 to SDHI_D3 pins

–6.5

4

Input data setup time for SDHI_CMD and SDHI_D0 to

SDHI_D3 pins

t_ISU(SD)

t_IH(SD)

6

2

—

ns

Input data hold time for SDHI_CMD and SDHI_D0 to

SDHI_D3 pins

Note 1. In the G-version products, the AC characteristics are measured by setting the drive capacity control register 2 corresponding the

SDHI_CLK-C pin as a high-speed interface high-drive output.

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All SDHI AC timings are measured in combination with the pins in the same group.

t_PP(SD)

t_WL(SD)

t_WH(SD)

V_IH

50% V_CC

SDHI_CLK output

V_IL

t_THL(SD)

t_TLH(SD)

t_ISU(SD)t_IH(SD)

SDHI_CMD, SDHI_D3 to SDHI_D0 input

SDHI_CMD, SDHI_D3 to SDHI_D0 output

t_ODLY(SD)

Figure 5.72

SD Host Interface Input/Output Signal Timing

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RX65N Group, RX651 Group

5. Electrical Characteristics

Table 5.45 SDSI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF

,

OH

OL

High-drive output is selected by the driving ability control register.

1

Item

Symbol

t_PP(SDSI)

t_WH(SDSI)

Min.

20

Max.

—

Unit

ns

Test Conditions

Figure 5.73

*

SDSI

SDSI_CLK pin input cycle time

SDSI_CLK pin input high pulse width

0.4 ×

—

ns

t_PP(SDSI)

SDSI_CLK pin input low pulse width

t_WL(SDSI)

0.4 ×

—

ns

t_PP(SDSI)

SDSI_CLK pin input rise time

SDSI_CLK pin input fall time

t_TLH(SDSI)

t_THL(SDSI)

—

5

3

ns

Input data setup time for SDSI_CMD and SDSI_D0 to t_ISU(SDSI)

SDSI_D3 pins

—

Input data hold time for SDSI_CMD and SDSI_D0 to

SDSI_D3 pins

t_IH(SDSI)

2

0

—

14

ns

Output data delay time for SDSI_CMD and SDSI_D0 t_ODLY(SDSI)

to SDSI_D3 pins (default speed mode)

Figure 5.74

Figure 5.75

Output data delay time for SDSI_CMD and SDSI_D0

to SDSI_D3 pins (high speed mode)

2.5

Note 1. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All SDSI AC timings are measured in combination with the pins in the same group.

t_PP(SDSI)

t_WL(SDSI)

t_WH(SDSI)

V_IH

50% V_CC

SDSI_CLK input

V_IL

t_THL(SDSI)

t_TLH(SDSI)

t_ISU(SDSI)t_IH(SDSI)

SDSI_CMD, SDSI_D3 to SDSI_D0 input

Figure 5.73

SD Slave Interface Input Signal Timing

V_IH

SDSI_CLK input

V_IL

t_ODLY(SDSI)

SDSI_CMD, SDSI_D3 to SDSI_D0 output

Figure 5.74

SD Slave Interface Output Signal Timing (Default Speed Mode)

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5. Electrical Characteristics

50% V_CC

SDSI_CLK input

t_ODLY(SDSI)

SDSI_CMD, SDSI_D3 to SDSI_D0 output

Figure 5.75

SD Slave Interface Output Signal Timing (High Speed Mode)

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5. Electrical Characteristics

5.4

USB Characteristics

Table 5.46 On-Chip USB Low Speed (Host Only) Characteristics (DP and DM Pin Characteristics)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

UCLK = 48 MHz,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

V_IH

Min.

Typ.

—

Max.

—

Unit

V

Test Conditions

| DP – DM |

Input

characteristics

Input high level voltage

Input low level voltage

Differential input sensitivity

Differential common mode range

Output high level voltage

Output low level voltage

Cross-over voltage

Rise time

2.0

—

V_IL

0.8

V

V_DI

0.2

0.8

2.8

0.0

1.3

75

—

V

V_CM

V_OH

V_OL

V_CRS

t_LR

2.5

V

Output

characteristics

3.6

V

I_OH= –200 μA

I_OL= 2 mA

0.3

V

2.0

V

Figure 5.76

300

125

24.80

ns

%

kΩ

Fall time

t_LF

75

Rise/fall time ratio

t_LR/ t_LF

80

t_LR/ t_LF

Pull-down

DP/DM pull-down resistance

R_pd

14.25

characteristics (when the host controller function is

selected)

90%

V_CRS

DP, DM

10%

t_LR

10%

t_LF

Figure 5.76

DP and DM Output Timing (Low Speed)

Observation

point

dp

27

200 pF to

600 pF

3.6 V

1.5 k

dm

27

200 pF to

600 pF

Figure 5.77

Test Circuit (Low Speed)

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5. Electrical Characteristics

Table 5.47 On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

UCLK = 48 MHz,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

V_IH

Min.

Typ.

—

Max.

—

Unit

V

Test Conditions

| DP – DM |

Input

characteristics

Input high level voltage

Input low level voltage

Differential input sensitivity

Differential common mode range

Output high level voltage

Output low level voltage

Cross-over voltage

Rise time

2.0

—

V_IL

0.8

V

V_DI

0.2

0.8

2.8

0.0

1.3

4

—

V

V_CM

V_OH

V_OL

V_CRS

t_FR

2.5

V

Output

characteristics

3.6

V

I_OH= –200 μA

I_OL= 2 mA

0.3

V

2.0

V

Figure 5.78

20

ns

%

Ω

Fall time

t_FF

4

20

Rise/fall time ratio

t

_FR/ t_FF

Z_DRV

R_pu

90

111.11

44

t_FR/ t_FF

Rs = 27 Ω included

Idle state

Output resistance

28

Pull-up and

pull-down

DP pull-up resistance

(when the function controller

characteristics function is selected)

0.900

1.425

1.575

3.090

kΩ

At transmission and reception

DP/DM pull-down resistance

R_pd

14.25

—

24.80

kΩ

(when the host controller function

is selected)

90%

V_CRS

DP, DM

10%

t_FR

t_FF

Figure 5.78

DP and DM Output Timing (Full-Speed)

Observation

point

dp

27

50 pF

dm

Figure 5.79

Test Circuit (Full-Speed)

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5. Electrical Characteristics

5.5

A/D Conversion Characteristics

Table 5.48 12-Bit A/D (Unit 0) Conversion Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKC = 1 MHz to 60 MHz, T = T

,

a

opr

Source impedance = 1.0 kΩ

Item

Min.

8

Typ.

—

Max.

12

Unit

Bit

Test Conditions

Resolution

Analog input capacitance

—

30

pF

Channel-dedicated Conversion time*¹

1.06

—

μs

 Sampling of channel-

dedicated sample-and-

hold circuits in 24 states

 Sampling in 15 states

sample-and-hold

circuits in use

(Operation at PCLKC = 60 MHz)

(0.4 + 0.25)

2

*

(AN000 to AN002)

Offset error

—

±1.5

±3.5

LSB

AN000 to AN002 = 0.25 V

Full-scale error

AN000 to AN002 = VREFH0

– 0.25 V

Quantization error

—

±0.5

±3.0

±1.0

±1.5

—

LSB

μs

Absolute accuracy

±5.5

±2.0

±3.0

20

DNL differential nonlinearity error

INL integral nonlinearity error

Holding characteristics of sample-and-

hold circuits

Dynamic range

0.25

—

VREFH0

– 0.25

V

Channel-dedicated Conversion time*¹

0.48

(0.267)*²

—

μs

Sampling in 16 states

sample-and-hold

circuits not in use

(AN000 to AN007)

(Operation at PCLKC = 60 MHz)

Offset error

—

±1.0

±0.5

±2.5

±0.5

±1.0

±2.5

—

LSB

Full-scale error

Quantization error

Absolute accuracy

±4.5

±1.5

±2.5

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds

during A/D conversion, values may not fall within the above ranges.

Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states

is indicated.

Note 2. The value in parentheses indicates the sampling time.

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5. Electrical Characteristics

Table 5.49 12-Bit A/D (Unit 1) Conversion Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKD = 1 MHz to 60 MHz, T = T

,

a

opr

Source impedance = 1.0 kΩ

Item

Min.

8

Typ.

—

Max.

12

Unit

Bit

Test Conditions

Resolution

Conversion time*¹

(Operation at PCLKD = 60 MHz)

0.88

(0.633)*²

—

μs

Sampling in 38 states

(ADSAM.SAM = 1)

Conversion time*¹

(Operation at PCLKD = 30 MHz)

1

—

μs

Sampling in 15 states

(ADSAM.SAM = 1)

(0.500)*²

Analog input capacitance

Offset error

—

30

pF

±2.0

±0.5

±4.0

±1.5

±3.5

—

LSB

Full-scale error

Quantization error

Absolute accuracy

±6.0

±4.0

DNL differential nonlinearity error

(Operation at PCLKD = 60 MHz)

DNL differential nonlinearity error

(Operation at PCLKD = 30 MHz)

—

±1.5

±2.0

±2.5

±4.0

±3.5

LSB

INL integral nonlinearity error

(Operation at PCLKD = 60 MHz)

INL integral nonlinearity error

(Operation at PCLKD = 30 MHz)

Note:

The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds

during A/D conversion, values may not fall within the above ranges.

Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states

is indicated.

Note 2. The value in parentheses indicates the sampling time.

Table 5.50 A/D Internal Reference Voltage Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKD = 60 MHz, T = T

a

opr

Test

Conditions

Item

Min.

1.13

Typ.

1.18

Max.

1.23

Unit

V

A/D internal reference voltage

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5. Electrical Characteristics

5.6

D/A Conversion Characteristics

Table 5.51 D/A Conversion Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

—

Min.

12

Typ.

12

Max.

12

Unit

Test Conditions

Resolution

Unbuffered output Absolute accuracy

Bit

—

±6.0

LSB

2-MΩ resistive load

10-bit conversion

Differential nonlinearity error

DNL

R_O

t_S

—

5

±1.0

8.6

—

±2.0

—

LSB

kΩ

μs

2-MΩ resistive load

Output resistance

Setting time

3

20-pF capacitive load

Buffered output

Load resistance

Load capacitance

Output voltage

R_L

—

kΩ

pF

V

C_L

—

0.2

—

50

V_O

—

AVCC1 –

0.2

Differential nonlinearity error

Integral nonlinearity error

Setting time

DNL

INL

t_S

—

±1.0

±2.0

—

±2.0

±4.0

4

LSB

μs

5.7

Temperature Sensor Characteristics

Table 5.52 Temperature Sensor Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Relative accuracy

Temperature slope

Min.

—

Typ.

±1

Max.

—

Unit

°C

Test Conditions

—

4

—

mV/°C

V

Output voltage (at 25°C)

Temperature sensor start time

Sampling time*¹

—

1.21

—

30

—

μs

4.15

—

μs

Note 1. Set the S12AD1.ADSSTRT register such that the sampling time of the 12-bit A/D converter satisfies this specification.

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5. Electrical Characteristics

5.8

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Table 5.53 Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

V_POR

Min.

2.5

Typ.

2.6

Max.

2.7

Unit

V

Voltage detection

level

Power-on

reset (POR)

Low power consumption

function disabled*¹

Figure 5.80

Low power consumption

function enabled*²

1.8

2.25

2.7

Voltage detection circuit (LVD0)

Voltage detection circuit (LVD1)

Voltage detection circuit (LVD2)

V_{det0_1}

V_{det0_2}

V_{det0_3}

V_{det1_1}

V_{det1_2}

V_{det1_3}

V_{det2_1}

V_{det2_2}

V_{det2_3}

t_POR

2.84

2.77

2.70

2.89

2.82

2.75

2.89

2.82

2.75

—

2.94

2.87

2.80

2.99

2.92

2.85

2.99

2.92

2.85

4.6

3.04

2.97

2.90

3.09

3.02

2.95

3.09

3.02

2.95

—

Figure 5.81

Figure 5.82

Figure 5.83

Internal reset time Power-on reset time

LVD0 reset time

ms

Figure 5.80

Figure 5.81

Figure 5.82

Figure 5.83

t_LVD0

—

0.70

0.57

—

LVD1 reset time

t_LVD1

—

LVD2 reset time

t_LVD2

—

Minimum VCC down time

t_VOFF

200

—

μs

Figure 5.80,

Figure 5.81

Response delay time

t_det

—

200

Figure 5.80 to

Figure 5.83

LVD operation stabilization time (after LVD is enabled)

Hysteresis width (LVD1 and LVD2)

T_d(E-A)

V _LVH

—

10

—

μs

Figure 5.82,

Figure 5.83

70

mV

Note:

The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det1,

and V_det2for the POR/ LVD.

Note 1. The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b.

Note 2. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.

t_VOFF

V_POR

VCC

Internal reset signal

(Low is valid)

t_det

t_POR

t_det

t_dett_POR

Figure 5.80

Power-on Reset Timing

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Jun 20, 2019

Page 224 of 246

RX65N Group, RX651 Group

5. Electrical Characteristics

t_VOFF

VCC

V_det0

Internal reset signal

(Low is valid)

t_det

t_LVD0

Figure 5.81

Voltage Detection Circuit Timing (V

)

det0

t_VOFF

V_LVH

VCC

V_det1

LVD1E

T_d(E-A)

LVD1

Comparator output

LVD1CMPE

LVD1MON

Internal reset signal

(Low is valid)

When LVD1RN = L

t_det

t_LVD1

t_det

When LVD1RN = H

t_LVD1

Figure 5.82

Voltage Detection Circuit Timing (V

)

det1

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 225 of 246

RX65N Group, RX651 Group

5. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det2

LVD2E

T_d(E-A)

LVD2

Comparator output

LVD2CMPE

LVD2MON

Internal reset signal

(Low is valid)

When LVD2RN = L

t_det

t_LVD2

When LVD2RN = H

t_LVD2

Figure 5.83

Voltage Detection Circuit Timing (V

)

det2

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 226 of 246

RX65N Group, RX651 Group

5. Electrical Characteristics

5.9

Oscillation Stop Detection Timing

Table 5.54 Oscillation Stop Detection Circuit Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

t_dr

Min.

—

Typ.

—

Max.

Unit

ms

Detection time

1

Figure 5.84

Main clock or

PLL clock

t_dr

OSTDSR.OSTDF

LOCO clock

ICLK

Figure 5.84

Oscillation Stop Detection Timing

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Jun 20, 2019

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RX65N Group, RX651 Group

5. Electrical Characteristics

5.10 Battery Backup Function Characteristics

Table 5.55 Battery Backup Function Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

V

= 2.0 to 3.6 V, T = T

BATT

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

V

Voltage level for switching to battery backup

V_DETBATT

V_BATTSW

2.50

2.70

2.60

—

2.70

—

Figure 5.85

Lower-limit V_BATTvoltage for power supply switching due to

VCC voltage drop

VCC-off period for starting power supply switching

t_VOFFBATT

200

—

μs

Note:

The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the

voltage level for switching to battery backup (V_DETBATT).

t_VOFFBATT

VCC voltage

guaranteed range

V_DETBATT

VCC

V_BATTSW

VBATT voltage

VBATT

Switching prohibited

guaranteed range

VBATT

Switching prohibited

Backup power

area

VBATT supply

VCC supply

Note.

The VBATT voltage when the supplied power source switches from Vcc to V_BATTshould not be lower than V_BATTSW

,

the lower-limit VBATT voltage for switching between power supplies due to a drop in the VCC voltage.

Figure 5.85

Battery Backup Function Characteristics

R01DS0276EJ0230 Rev.2.30

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RX65N Group, RX651 Group

5. Electrical Characteristics

5.11 Flash Memory Characteristics

Table 5.56 Code Flash Memory Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Temperature range for programming/erasure: T = T

a

opr

FCLK = 4 MHz

FCLK = 15 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Unit

Item

Symbol

Min.

—

Typ.

0.75

49

Max.

Min.

Typ.

0.38

25

Max.

Min.

Typ.

0.34

22

Max.

Programming time 128 bytes

_PEC≤ 100 times

t_P128

t_P8K

13.2

176

704

15.8

212

848

216

864

260

1040

—

6.6

88

—

6

ms

N

8 Kbytes

—

80

32 Kbytes

t_P32K

t_P128

t_P8K

—

194

0.91

60

—

97

352

8

—

88

320

7.2

96

ms

Programming time 128 bytes

_PEC> 100 times

—

0.46

30

—

0.41

27

ms

N

8 Kbytes

32 Kbytes

8 Kbytes

32 Kbytes

8 Kbytes

32 Kbytes

—

106

424

132

528

158

632

—

ms

t_P32K

t_E8K

t_E32K

t_E8K

t_E32K

N_PEC

—

234

78

—

117

48

—

106

43

384

120

480

144

576

—

ms

Erasure time

_PEC≤ 100 times

—

ms

N

—

283

94

—

173

58

—

157

52

ms

Erasure time

—

ms

N_PEC> 100 times

—

341

—

208

—

189

—

ms

Reprogramming/erasure cycle*¹

10000

Times

2

*

Suspend delay time during

programming

t_SPD

—

264

216

—

132

—

120

μs

First suspend delay time during

erasing

t_SESD1

(in suspend priority mode)

Second suspend delay time

during erasure

(in suspend priority mode)

t_SESD2

—

1.7

—

1.7

—

1.7

ms

Suspend delay time during

erasure

t_SEED

(in erasure priority mode)

Forced stop command

Data hold time*³

t_FD

—

32

—

22

—

20

—

μs

t_DRP

10

Year

Note 1. Definition of reprogram/erase cycle:

The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 1000),

erasing can be performed n times for each block. For instance, when 128-byte programming is performed 64 times for different

addresses in 8-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasing is not enabled (overwriting is prohibited).

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming (guaranteed range is from 1 to the

value of the minimum value).

Note 3. This shows the characteristics when reprogramming is performed within the specified range, including the minimum value.

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RX65N Group, RX651 Group

5. Electrical Characteristics

Table 5.57 Data Flash Memory Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Temperature range for programming/erasure: T = T

a

opr

FCLK = 4 MHz

FCLK = 15 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Unit

Item

Symbol

Min.

—

Typ.

0.36

3.1

4.7

8.9

—

Max.

Min.

Typ.

0.18

1.9

2.9

5.4

—

Max.

Min.

Typ.

0.16

1.7

2.6

4.9

—

Max.

1.7

10

Programming time 4 bytes

t_DP4

t_DP64

3.8

18

—

1.9

11

—

ms

Erasure time

64 bytes

128 bytes

256 bytes

4 bytes

—

t_DP128

t_DP256

t_DBC4

t_DBC64

t_DBC2K

—

27

—

16

—

15

ms

—

50

—

31

—

28

ms

Blank check time

—

84

—

33

—

30

μs

64 bytes

2 Kbytes

—

280

6160

—

110

2420

—

100

2200

—

μs

—

μs

Reprogramming/erasure cycle*¹

N_DPEC100000

—

100000

—

100000

—

Times

2

*

Suspend delay time during

programming

t_DSPD

—

264

—

132

—

120

μs

First suspend

delay time during

erasure

(in suspend prior-

ity mode)

64 bytes

128 bytes

256 bytes

—

216

—

132

—

120

μs

Second suspend

delay time during

erasure

(in suspend prior-

ity mode)

64 bytes

128 bytes

256 bytes

—

300

390

570

—

300

390

570

—

300

390

570

μs

Suspend delay

time during erasing

(in suspend prior-

ity mode)

64 bytes

128 bytes

256 bytes

—

10

—

300

390

570

32

—

10

—

300

390

570

22

—

10

—

300

390

570

20

μs

—

μs

Forced stop command

Data hold time*³

t_FD

μs

t_DDRP

—

Year

Note 1. Definition of reprogram/erase cycle:

The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),

erasing can be performed n times for each block. For instance, when 4-byte programming is performed 512 times for different

addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasing is not enabled (overwriting is prohibited).

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming (guaranteed range is from 1 to the

value of the minimum value).

Note 3. This shows the characteristics when reprogramming is performed within the specified range, including the minimum value.

R01DS0276EJ0230 Rev.2.30

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RX65N Group, RX651 Group

5. Electrical Characteristics

• Suspension during programming

FCU command

Program

Ready

Suspend

t_SPD

FSTATR.FRDY

Not Ready

Ready

Programming pulse

Programming

• Suspension during erasure in suspend priority mode

FCU command

Erase

Suspend

Not Ready

Erasing

Resume

t_SESD1

t_SESD2

FSTATR.FRDY

Erasure pulse

Ready

Not Ready

Erasing

• Suspension during erasure in erasure priority mode

FCU command

FSTATR.FRDY

Erasure pulse

Erase

Suspend

Not Ready

Erasing

t_SEED

Ready

Figure 5.86

Flash Memory Programming/Erasure Suspension Timing

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Jun 20, 2019

Page 231 of 246

RX65N Group, RX651 Group

5. Electrical Characteristics

5.12 Boundary Scan

Table 5.58 Boundary Scan Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TRST# pulse width

TMS setup time

t_TCKcyc

t_TCKH

t_TCKL

t_TCKr

100

45

—

5

ns

Figure 5.87

t_TCKf

—

5

t_TRSTW

t_TMSS

t_TMSH

t_TDIS

20

—

40

t_TCKcycFigure 5.88

ns

Figure 5.89

TMS hold time

TDI setup time

TDI hold time

t_TDIH

TDO data delay time

t_TDOD

t_TCKcyc

t_TCKH

t_TCKf

TCK

t_TCKL

t_TCKr

Figure 5.87

TCK

Boundary Scan TCK Timing

RES#

TRST#

t_TRSTW

Figure 5.88

Boundary Scan TRST# Timing

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RX65N Group, RX651 Group

5. Electrical Characteristics

TCK

TMS

t_TMSS

t_TMSH

t_TDIS

t_TDIH

TDI

t_TDOD

TDO

Figure 5.89

Boundary Scan Input/Output Timing

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 233 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas

Electronics Corporation website.

JEITA Package Code

P-TFLGA177-8x8-0.50

RENESAS Code

PTLG0177KA-A

Previous Code

177F0E-A

MASS[Typ.]

0.2g

φ b

1

S

AB

S

φ × M

φ b

D

φ × M

AB

e

w

S A

Z

D

A

R

P

N

M

L

K

J

B

H

G

F

E

D

C

B

A

Dimension in Millimeters

Reference

Symbol

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

y

S

x4

Min

Nom Max

8.0

v

D

E

v

Index mark

S

(Laser mark)

8.0

0.15

w

A

e

0.20

1.05

0.5

b

0.21 0.25 0.29

b

1

0.29 0.34 0.39

x

0.08

y

Z

D

E

0.5

Z

0.5

Figure A 177-Pin TFLGA (PTLG0177KA-A)

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Jun 20, 2019

Page 234 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

Figure B 176-Pin LFBGA (PLBG0176GA-A)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 235 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

JEITA Package Code

P-LFQFP176-24x24-0.50

RENESAS Code

PLQP0176KB-A 176P6Q-A/FP-176E/FP-176EV

Previous Code

MASS[Typ.]

1.8g

H_D

*1

D

132

89

133

88

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

b_p

b₁

Dimension in Millimeters

Reference

Terminal cross section

Symbol

Min Nom Max

D

E

A₂

23.9 24.0 24.1

1.4

H_D

H_E

A

25.8 26.0 26.2

1.7

176

45

A₁

b_p

b₁

c

c₁

θ

e

0.05 0.1 0.15

0.15 0.20 0.25

0.18

1

44

Index mark

F

Z_D

S

0.09 0.145 0.20

0.125

L

0°

8°

L₁

*3

0.5

y

S

b_p

e

x

M

x

y

0.08

0.10

Detail F

Z_D

Z_E

1.25

0.35 0.5 0.65

1.0

L

L₁

Figure C 176-Pin LFQFP (PLQP0176KB-A)

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Jun 20, 2019

Page 236 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

JEITA Package Code

P-TFLGA145-7x7-0.50

RENESAS Code

PTLG0145KA-A

Previous Code

145F0G

MASS[Typ.]

0.1g

φb₁

φ

M

S AB

φb

φ

M

S AB

D

w

S A

Z_D

e

A

N

M

L

K

J

H

G

F

B

E

D

C

B

A

Dimension in Millimeters

Reference

Symbol

1

2

3

4

5

6

7

8

9

10 11 12 13

y

S

x4

Min

Nom Max

7.0

v

Index mark

D

E

S

(Laser mark)

7.0

v

0.15

w

A

0.20

1.05

e

0.5

b

0.21 0.25 0.29

b₁

x

0.29 0.34 0.39

0.08

y

Z_D

Z_E

0.5

Figure D 145-Pin TFLGA (PTLG0145KA-A)

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Jun 20, 2019

Page 237 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

Figure E 144-Pin LFQFP (PLQP0144KA-B)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 238 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

JEITA Package Code

P-TFLGA100-7x7-0.65

RENESAS Code

PTLG0100JA-A

Previous Code

100F0G

MASS[Typ.]

0.1g

φ b₁

φ× M

S

AB

φ b

D

φ× M

S

AB

w

S A

Z_D

e

A

K

J

H

G

F

B

E

D

C

B

A

Dimension in Millimeters

Reference

Symbol

Min Nom Max

7.0

1

2

3

4

5

6

7

8

9

10

y

S

×4

D

E

v

Index mark

S

(Laser mark)

0.15

w

A

e

0.20

1.05

0.65

0.31 0.35 0.39

b

b₁0.385 0.435 0.485

x

0.08

0.10

y

Z_D

Z_E

0.575

Figure F 100-Pin TFLGA (PTLG0100JA-A)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 239 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

Figure G 100-Pin LFQFP (PLQP0100KB-B)

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Jun 20, 2019

Page 240 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

Figure H 64-Pin TFBGA (PTBG0064KB-A)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 241 of 246

RX65N Group, RX651 Group

Appendix 1. Package Dimensions

Figure I 64-Pin LFQFP (PLQP0064KB-C)

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 242 of 246

REVISION HISTORY

RX65N Group, RX651 Group

REVISION HISTORY

RX65N Group, RX651 Group Datasheet

Classifications

- Items with Technical Update document number: Changes according to the corresponding issued Technical Update

- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued

Description

Rev.

Date

Classification

Page

—

Summary

1.00 Aug 24, 2016

2.10 Oct 02, 2017

First edition, issued

—

Products with at least 1.5 Mbytes of code flash memory added

The conventional products indicated as “products with 1 Mbyte of code

flash memory or less”

1. Overview

6, 9

8

Table 1.1 Outline of Specifications (5/9), Note added

TN-RX*-A164B/E

TN-RX*-A165A/E

Table 1.1 Outline of Specifications (8/9)

Description of the 12-bit D/A converter (R12DA) changed

4. I/O Registers

131

Table 4.1 List of I/O Registers (Address Order) (46 / 61), changed

TN-RX*-A176A/E

5. Electrical Characteristics

147

150

Table 5.1 Absolute Maximum Rating, changed

Table 5.5 DC Characteristics (3) (Products with 1 Mbyte of code flash

memory or less), changed

TN-RX*-A164B/E

152

Table 5.7 DC Characteristics (4), changed

TN-RX*-A164B/E

TN-RX*-A176A/E

153

162

Table 5.9 Heat Resistance Value (Reference), added

Table 5.21 Timing of Recovery from Low Power Consumption Modes (1), TN-RX*-A176A/E

changed

189

212

218

219

—

Table 5.35 RSPI Timing, changed

Table 5.49 D/A Conversion Characteristics, changed

Table 5.54 Code Flash Memory Characteristics, changed

Table 5.55 Data Flash Memory Characteristics, changed

TN-RX*-A165A/E

2.30 Jun 20, 2019

64-pin Package Products added

Terms unified:

pull-up MOS → pull-up resistors

pull-down MOS → pull-down resistors

1. Overview

14 to 22

30

Table 1.3 List of Products, changed

Table 1.4 Pin Functions (6/8), changed

TN-RX*-A204A/E

TN-RX*-A0211A/E

47 to 49

Table 1.5 List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA), TN-RX*-A182A/E

changed

52

Table 1.6 List of Pin and Pin Functions (176-Pin LFQFP), changed

4. I/O Registers

136 to 138 Table 4.1 List of I/O Registers (Address Order), changed

5. Electrical Characteristics

TN-RX*-A0211A/E

157

Table 5.5 DC Characteristics (3) (Products with 1 Mbyte of code flash

memory or less), changed

158, 159

Table 5.6 DC Characteristics (3) (Products for products with at least 1.5

Mbytes of code flash memory), changed

159

161

164

206

Table 5.7 DC Characteristics (4), changed

Table 5.9 Thermal Resistance Value (Reference), changed

Table 5.13 Reset Timing, Unit changed

TN-RX*-A182A/E

TN-RX*-A202A/E

Figure 5.54 RIIC Bus Interface Input/Output Timing and Simple IIC Bus

Interface Input/Output Timing, changed

216

Table 5.44 SDHI Timing, added

TN-RX*-A196A/E

Figure 5.72 SD Host Interface Input/Output Signal Timing, added

217, 218

Table 5.45 SDSI Timing, added

Figure 5.73 SD Slave Interface Input Signal Timing to

Figure 5.75 SD Slave Interface Output Signal Timing (High Speed Mode),

added

221

Table 5.48 12-Bit A/D (Unit 0) Conversion Characteristics, changed

TN-RX*-A182A/E

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Jun 20, 2019

Page 243 of 246

RX65N Group, RX651 Group

REVISION HISTORY

Description

Summary

Rev.

Date

Classification

Page

230

2.30 Jun 20, 2019

Table 5.57 Data Flash Memory Characteristics, changed (64-bytes and 2-

Kbytes blank check time added)

All trademarks and registered trademarks are the property of their respective owners.

R01DS0276EJ0230 Rev.2.30

Jun 20, 2019

Page 244 of 246

General Precautions in the Handling of Microprocessing Unit and Microcontroller

Unit Products

The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the

products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps

must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be

adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.

Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and

measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor

devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.

2. Processing at power-on

The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of

register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset

pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins

in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the

level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O

pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal

elements. Follow the guideline for input signal during power-off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are

generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of

the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal

become possible.

5. Clock signals

After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program

execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator

during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal

produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V_IL

(Max.) and V_IH(Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the

input level is fixed, and also in the transition period when the input level passes through the area between V_IL(Max.) and V_IH(Min.).

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these

addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.

The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms

of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,

operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-

evaluation test for the given product.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

equipment; industrial robots; etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause

serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all

liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	R5F565N7FGFP
厂家：	RENESAS TECHNOLOGY CORP
描述：	Max. operating frequency: 120 MHz Capable of 240 DMIPS in operation at 120 MHz
文件：	总246页 (文件大小：2832K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F565N7FGFP [RENESAS]

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