R5F566TAEGFF [RENESAS]
160-MHz, 32-bit RX MCU, on-chip FPU, 928 CoreMark, Supportive of 5V power supply,;
| 型号： | R5F566TAEGFF |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 160-MHz, 32-bit RX MCU, on-chip FPU, 928 CoreMark, Supportive of 5V power supply, |
| 文件： | 总201页 (文件大小：2178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
Datasheet
R01DS0315EJ0110
Rev.1.10
RX66T Group
Renesas MCUs
Feb 08, 2019
160-MHz, 32-bit RX MCU, on-chip FPU, 928 CoreMark, Supportive of 5V power supply,
up to 1-MB flash memory, up to 128-KB SRAM, 32-KB data flash memory, 16-KB SRAM with ECC, Simultaneous sampling with
3 units of 12-bit A/D converter (up to 7 channels), Single-end/pseudo differential input supportive amplifier (6 channels),
Analog comparator (6 channels), 160 MHz PWM (4 channels for 3-phase complementary, 2 channels for 5-phase
complementary, 10 channels for single-phase complementary), 4-channel high-resolution PWM with resolution of 195 ps at the
minimum, Host/function or OTG controller with full-speed USB 2.0 transfer, CAN, Encryption functions (optional)
Features
PLQP0144KA-B 20 × 20 mm, 0.5 mm pitch
■ 32-bit RXv3 CPU core
PLQP0112JA-B 20 × 20 mm, 0.65 mm pitch
PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch
PLQP0080JA-A 14 × 14 mm, 0.65 mm pitch
PLQP0080KB-B 12 × 12 mm, 0.5 mm pitch
PLQP0064KB-B 10 × 10 mm, 0.5 mm pitch
Maximum operating frequency: 160 MHz
Capable of 928 CoreMark in operation at 160 MHz
JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
Operation from a single 2.7- to 5.5-V supply
Four low-power modes
■ Various communications interfaces
Host/function or OTG controller (1 channel) with full-speed USB
2.0 (USBb) transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(1 channel)
SCIj and SCIh with multiple functionalities (up to 6 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
■ On-chip code flash memory
Supports versions with 1 Mbytes/512 Kbytes/256 Kbytes
No wait cycles at up to 120 MHz or when the ROM cache is hit
User code is programmable by on-board or off-board programming.
■ On-chip data flash memory
32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
SCIi with 16-byte transmission and reception FIFOs (1 channel)
I2C bus interface (RIICa) for transfer at up to 400 kbps (fast mode),
capable of SMBus operation (1 channel)
■ On-chip SRAM, no wait states
128K/64 Kbytes of SRAM (no wait states)
16 Kbytes of RAM with ECC (with wait)
RSPId (1 channel) for transfer at up to 30 Mbps
■ Data transfer
DMACa: 8 channels
DTCa: 1 channel
■ Up to 31 extended-function timers
32-bit GPTW (10 channels): operation at 160 MHz, input capture,
output compare, PWM waveforms: 10 output channels in single-
phase complementary PWM mode/3 output channels in 3-phase
complementary PWM mode/2 output channels in 5-phase
complementary PWM mode, phase-counting mode, linkage with
comparator (counting operation, PWM negate control)
16-bit MTU3d (9 channels): operation at 160 MHz, input capture,
output compare, PWM waveforms: 2 output channels in 3-phase
complementary PWM mode, phase-counting mode
8-bit TMR (8 channels)
■ ELC
Module operation can be initiated by event signals without using
interrupts
Linked operation between modules is possible when the CPU is in
sleep mode
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVDA) with voltage settings
16-bit CMT (4 channels)
■ Clock functions
Frequency of resonator for main clock oscillator: 8 to 24 MHz (this
can be used as the PLL reference clock)
High-speed on-chip oscillator: 16 MHz/18 MHz/20 MHz (this can
be used as the PLL reference clock)
Low-speed on-chip oscillator: 240 kHz
■ High-resolution PWM waveform generation circuit
(HRPWM): 4 channels
Controlling the timing of rising or falling of the PWM output
waveform for 32-bit GPTW is realized with minimum of 195 ps
resolution (in operation at 160 MHz)
■ 12-bit A/D converter (S12ADH):
total of 30 channels for three units
Up to three 12-bit units of sample-and-hold circuit included
Unit 0 (8 channels for 3 sample-and-hold circuits),
Unit 1 (8 channels for 3 sample-and-hold circuits),
Unit 2 (14 channels)
■ Independent watchdog timer
120-kHz IWDT-dedicated on-chip oscillator clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stoppage detection, functions for self-diagnosis and
detection of disconnection for the A/D converter, clock frequency
accuracy measurement circuit, independent watchdog timer, RAM
test-assisting function by DOC, and CRCA, etc.
Programmable gain amplifier with pseudo differential amplification
(3 channels × 2)
Register write protection function can protect values in important
registers against overwriting.
■ Analog Comparator (CMPC): 6 channels
■ 12-bit D/A converter: 2 channels
Usable as a reference voltage for the analog comparator
■ External bus
Bus clock at 40 MHz (max)
Four CS areas
■ Temperature sensor for measuring temperature
within the chip
8- or 16-bit bus space is selectable per area
■ Encryption functions (Trusted Secure IP Lite)
128- or 256-bit key length of AES for ECB, CBC, GCM, others
True random number generator
Unauthorized access to the encryption engine is disabled and
imposture and falsification of information are prevented
Safe management of keys
■ Up to 110 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Recommended operating temp. range (Topr)
–40C to +85C
–40C to +105C
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RX66T Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2,
Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1/9)
Classification Module/Function
Description
CPU
CPU
Maximum operating frequency: 160 MHz
32-bit RX CPU (RXv3)
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
111 instructions
Standard provided instructions: 111
Basic instructions: 77
Single precision floating point instructions: 11
DSP instructions: 23
Addressing modes: 11
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 → 64 bits
On-chip divider: 32/32 → 32 bits
Barrel shifter: 32 bits
FPU
Single-precision (32-bit) floating-point number
Data types and floating-point exceptions in conformance with the IEEE754 standard
Memory
Code flash memory
Capacity: 1 Mbyte, 512 Kbytes, 256 Kbytes
ROM cache: Operation of an 8-Kbyte instruction fetching cache can be enabled or
disabled (this is disabled by default).
While ROM cache operation is enabled:
- when the cache is hit, one-cycle access up to 160 MHz
- when the cache is missed:
one to two cycles if ICLK ≤ 120 MHz (bus wait: 0 cycles),
two to three cycles if ICLK > 120 MHz (bus wait: 1 cycle).
While ROM cache operation is disabled:
one cycle if ICLK ≤ 120 MHz (bus wait: 0 cycles),
two cycles if ICLK > 120 MHz (bus wait: 1 cycle).
On-board programming: Five types
Off-board programming (parallel programmer mode) (This is not available for 80/64-pin
products)
The trusted memory (TM) function protects against the reading of programs from blocks
8 and 9.
Data flash memory
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
Unique ID
RAM
12-byte unique ID for the device
Capacity: 128 Kbytes, 64 Kbytes
160 MHz No-wait access
SED (single error detection)
RAM with ECC
Capacity: 16 Kbytes
00FF C000h to 00FF FFFFh (16 Kbytes)
SEC-DED (single error correction/double error detection)
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RX66T Group
1. Overview
Table 1.1
Outline of Specifications (2/9)
Classification Module/Function
Description
Operating modes
Operating modes by the mode-setting pins at the time of release from the reset state
Single-chip mode
Boot mode (SCI interface)
Boot mode (USB interface)
Boot mode (FINE interface)
User boot mode
Selection of operating mode by register setting
Single-chip mode, user boot mode, On-chip ROM disabled extended mode,
On-chip ROM enabled extended mode
Endian selectable
Clock
Clock generation circuit Main clock oscillator, low-speed/high-speed on-chip oscillator, PLL frequency
synthesizer, and IWDT-dedicated on-chip oscillator
The peripheral module clocks can be set to frequencies above that of the system clock.
Main-clock oscillation stoppage detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and
external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK): Up
to 160 MHz
Peripheral modules of MTU3 (Internal peripheral bus), GPTW (Internal peripheral bus),
HRPWM (Internal peripheral bus), RSPI, and SCI11 run in synchronization with PCLKA,
which operates at up to 120 MHz.
Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz
MTU3 (counter reference clocks), GPTW (counter reference clocks), and HRPWM
(reference clocks) are synchronized with PCLKC: Up to 160 MHz
ADCLK in the S12AD runs in synchronization with PCLKD: Up to 60 MHz
Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 40 MHz
Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a
reference clock of the PLL circuit
Reset
Nine types of reset
RES# pin reset: Generated when the RES# pin is driven low.
Power-on reset: Generated when the RES# pin is driven high and VCC rises.
Voltage-monitoring 0 reset: Generated when VCC falls.
Voltage-monitoring 1 reset: Generated when VCC falls.
Voltage-monitoring 2 reset: Generated when VCC falls.
Deep software standby reset: Generated in response to an interrupt to trigger release
from deep software standby.
Independent watchdog timer reset: Generated when the independent watchdog timer
underflows, or a refresh error occurs.
Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh error
occurs.
Software reset: Generated by register setting.
Power-on reset
If the RES# pin is at the high level when power is supplied, an internal reset is generated.
After VCC has exceeded the voltage detection level and the specified period has elapsed,
the reset is cancelled.
Voltage detection circuit (LVDA)
Monitors the voltage being input to the VCC pin and generates an internal reset or internal
interrupt.
Voltage detection circuit 0
Capable of generating an internal reset
The option-setting memory can be used to select enabling or disabling of the reset.
Voltage detection level: Selectable from two different levels
Voltage detection circuits 1 and 2
Voltage detection level: Selectable from five different levels
Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)
Capable of generating an internal reset
Two types of timing are selectable for release from reset
An internal interrupt can be requested.
Detection of voltage rising above and falling below thresholds is selectable.
Maskable or non-maskable interrupt is selectable
Voltage detection monitoring
Event linking
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RX66T Group
1. Overview
Table 1.1
Outline of Specifications (3/9)
Classification Module/Function
Description
Low power
Low power consumption Module stop function
consumption
facilities
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Interrupt
Interrupt controller
(ICUC)
Interrupt vectors: 256
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: 2 sources
Non-maskable interrupts: 7 sources
Sixteen levels specifiable for the order of priority
Method of interrupt source selection:
The interrupt vectors consist of 256 vectors (208 sources are fixed. The remaining 135
vectors are selected from among the other 48 sources.)
External bus extension
The external address space can be divided into four areas (CS0 to CS3), each with
independent control of access settings.
Capacity of each area: 2 Mbytes (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8- or 16-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA
DMA controller
8 channels
(DMACAa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Request sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Data transfer controller
(DTCa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Request sources: External interrupts and interrupt requests from peripheral functions
I/O ports
Programmable I/O ports I/O ports for the 144-pin LFQFP
I/O pins: 110
Input pin: 9
Pull-up resistors: 110
Open-drain outputs: 110
5-V tolerance: 4
Large current output: 15
I/O ports for the 112-pin LQFP
I/O pins: 84
Input pin: 9
Pull-up resistors: 84
Open-drain outputs: 84
5-V tolerance: 2
Large current output: 15
I/O ports for the 100-pin LFQFP (with PGA pseudo-differential input, and with USB)
I/O pins: 69
Input pin: 9
Pull-up resistors: 69
Open-drain outputs: 69
5-V tolerance: 3
Large current output: 15
I/O ports for the 100-pin LFQFP (with PGA pseudo-differential input, and without USB)
I/O pins: 72
Input pin: 9
Pull-up resistors: 72
Open-drain outputs: 72
5-V tolerance: 2 (products with 64 Kbytes of RAM), 3 (products with 128 Kbytes of RAM)
Large current output: 15
I/O ports for the 100-pin LFQFP (without PGA pseudo-differential input, and without
USB)
I/O pins: 73
Input pin: 7
Pull-up resistors: 73
Open-drain outputs: 73
5-V tolerance: 2 (products with 64 Kbytes of RAM), 3 (products with 128 Kbytes of RAM)
Large current output: 15
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RX66T Group
1. Overview
Table 1.1
Outline of Specifications (4/9)
Classification Module/Function
Description
I/O ports
Programmable I/O ports I/O ports for the 80-pin LFQFP, 80-pin LQFP
I/O pins: 52
Input pin: 9
Pull-up resistors: 52
Open-drain outputs: 52
5-V tolerance: 2
Large current output: 14
I/O ports for the 64-pin LFQFP
I/O pins: 39
Input pin: 7
Pull-up resistors: 39
Open-drain outputs: 39
5-V tolerance: 2
Large current output: 14
Event link controller (ELC)
Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
188 internal event signals can be freely combined for interlinked operation with
connected functions.
Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
Timers
8-bit timers (TMR)
(8 bits × 2 channels) × 4 units
Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/
32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Event linking by the ELC
Compare match timer
(CMT)
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
Event linking by the ELC
Watchdog timer (WDTA) 14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,
PCLKB/512, PCLKB/2048, PCLKB/8192)
Independent watchdog
timer (IWDTa)
14 bits × 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated
clock/128, dedicated clock/256
Window function: The positions where the window starts and ends are specifiable (the
window defines the timing with which refreshing is enabled and disabled).
Event linking by the ELC
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1. Overview
Table 1.1
Outline of Specifications (5/9)
Classification Module/Function
Description
Timers Multifunction timer pulse 9 channels (16 bits × 9 channels)
unit 3 (MTU3d)
Maximum of 28 pulse-input/output and 3 pulse-input possible
Select from among 14 counter-input clock signals for each channel (PCLKC/1, PCLKC/2,
PCLKC/4, PCLKC/8, PCLKC/16, PCLKC/32, PCLKC/64, PCLKC/256, PCLKC/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)
11 of the signals are available for channels 1, 3, 4, 12 are available for channel 2, and 10
are available for channel 5.
43 output compare/input capture registers
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffered operation
Support for cascade-connected operation
45 interrupt sources
Automatic transfer of register data
Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
Counter functionality for dead-time compensation
Generation of triggers for A/D converter conversion
The timing of the generation of requests to start A/D conversion can be monitored by an
external pin.
A/D converter start triggers can be skipped
Digital filter function for signals on the input capture and external counter clock pins
Event linking by the ELC
Internal peripheral bus clock: PCLKA
Counter reference clock: PCLKC
Frequency ratio: PCLKA to PCLKC = 1: N (N = 1 or 2)
Port output enable 3
(POE3B)
Control of the high-impedance state of the MTU3/GPTW’s waveform output pins, and
control of switching to the general I/O port pin
9 pins for input from signal sources: POE0, POE4, POE8, POE9, POE10, POE11,
POE12, POE13, POE14
Initiation by detection of short-circuited outputs (detection of PWM outputs that have
become an active level simultaneously)
Initiation by comparator detection/oscillation stop detection/software
Additional programming of output control target pins is enabled
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RX66T Group
1. Overview
Table 1.1
Outline of Specifications (6/9)
Classification Module/Function
Description
Timers
General PWM timer
(GPTW)
32 bits × 10 channels
Counting up or down (sawtooth-wave), counting up and down (triangle-wave) selectable
for all channels
Clock sources independently selectable for each channel
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Generation of dead times in PWM operation
Capable of synchronous start, stop, or clearing of counter for any channel
Capable of a start, stop, clearing, or up-/down-counting of the counter supporting
maximum of 8 ELC events
Capable of a start, stop, clearing, or up-/down-counting of the counter supporting input
level comparison
Capable of a start, stop, clearing, or up-/down-counting of the counter supporting
maximum of 4 external triggers
Output pin disabling function by a dead time error or a short circuit detection among
output pins
Capable of generating conversion start triggers for the A/D converters as well as
monitoring external pins for a start timing of conversion.
Capable of outputting events, such as compare-match from A to F and overflow/
underflow, to ELC
Capable of using noise filter of input capture
Internal peripheral bus clock: PCLKA
Counter reference clock: PCLKC
Frequency ratio: PCLKA to PCLKC = 1: N (N = 1 or 2)
High resolution PWM
(HRPWM)
Capable of generating the PWM waveform that is generated by GPTW0 through GPTW3
with resolution of minimum of 195 ps.
Port output enable for
GPTW (POEG)
Controlling the output disable for GPTW waveform output
Initiation by input level detection of GTETRG pins
Initiation by output disable request from GPTW
Initiation by detection of comparator interrupt request
Initiation by detection of oscillation stop or by software
Communication USB 2.0 FS host/
Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS
function
function module (USBb) One port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)
Self-power mode and bus power are selectable
OTG (On the Go) operation is possible (low-speed is not supported)
Incorporates 2 Kbytes of RAM as a transfer buffer
External pull-up and pull-down resistors are not required
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1. Overview
Table 1.1
Outline of Specifications (7/9)
Classification Module/Function
Description
Communication Serial communications
7 channels
function
interfaces (SCIj, SCIi,
SCIh)
SCIj: SCI1, SCI5, SCI6, SCI8, SCI9
SCIi: SCI11
SCIh: SCI12
SCIj, SCIi, SCIh
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
7, 8, 9-bit transfer mode
Bit rate modulation
Double-speed mode
Data match detection (SCI12 is not supported)
Event linking by the ELC (supported by SCI5 only)
SCIi Only
Capable of serial sending and receiving with 16-byte FIFO-buffered structure both at
transmission and reception sections
SCIh Only
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
I2C bus interface (RIICa) 1 channel
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 400 kbps
Event linking by the ELC
CAN module (CAN)
1 channel
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes per channel
Serial peripheral
interface (RSPIc)
1 channel
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each
frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
RSPCK can be stopped with the receive buffer full for master reception.
Event linking by the ELC
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1. Overview
Table 1.1
Outline of Specifications (8/9)
Classification Module/Function
Description
12-bit A/D converter (S12ADH)
12 bits (8 channels × 2 units, 14 channels × 1 unit)
12-bit resolution
Minimum conversion time
0.9 μs per channel (when ADCLK operates at 60 MHz)
Operating mode
Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)
Group A priority control (only for 3 group scan mode)
Sample-and-hold function
channel-dedicated sample-and-hold function (unit 0 × 3 channels, unit 1 × 3 channels)
included
Sampling variable
Sampling time can be set up for each channel.
Conversion function in order of arbitrarily selected channels (Serial conversion of the
same channel cannot be allowed)
Double trigger mode (A/D conversion data duplicated)
Three ways to start A/D conversion
Software trigger, synchronous trigger (MTU, TMR, ELC), external trigger
Prioritization in group scanning can be controlled among group A, B, and C.
Digital comparison
Method: Comparison to detect voltages above or below thresholds and window
comparison
Measurement: Comparison of two results of conversion or comparison of a value in the
comparison register and a result of conversion
Self-diagnostic function
Detection of analog input disconnection
Event linking by the ELC
Input signal amplification function by the programmable gain amplifier
(unit 0 × 3 channels, unit 1 × 3 channels)
Capable of supporting single end/pseudo-differential input
12-bit D/A converter (R12DAb)
Comparator C (CMPC)
Temperature sensor
2 channels
12-bit resolution
Output voltage: 0 V to AVCC2
Capable of providing as a reference voltage for comparator
Event linking by the ELC
6 channels
Function to compare the reference voltage and the analog input voltage
Reference voltage is selectable from 4 inputs
Analog input voltage is selectable from 4 inputs
Digital filtering
1 channel
Relative precision: ±1.0°C
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter (unit 2).
Safety
Memory protection unit
(MPU)
Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to
FFFF FFFFh.
Minimum protection unit: 16 bytes
Reading from, writing to, and enabling the execution access can be specified for each
area.
An access exception occurs when the detected access is not in the permitted area.
Trusted Memory (TM)
Function
Protects against the reading of programs from blocks 8 and 9 of the code flash memory
Instruction fetching by the CPU is the only form of access to these areas when the TM
function is enabled.
Register write protection Protects important registers from being overwritten for in case a program runs out of
function control.
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1. Overview
Table 1.1
Outline of Specifications (9/9)
Classification Module/Function
Description
Safety
CRC calculator (CRCA) Generation of CRC codes for 8-/32-bit data
8-bit data
Selectable from the following three polynomials
X8 + X2 + X + 1, X16 + X15 + X2 + 1, X16 + X12 + X5 + 1
32-bit data
Selectable from the following two polynomials
X
X
32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1,
32+X28+X27+X26+X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
Main clock oscillation
stop detection function
Main clock oscillation stop detection: Available
Clock frequency
accuracy measurement
circuit (CAC)
Monitors the clock output from the main clock oscillator, low- and high-speed on-chip
oscillators, the PLL frequency synthesizer, IWDT-dedicated on-chip oscillator, and
PCLKB.
Data operation circuit
(DOC)
The function to compare, add, or subtract 16-bit data
Encryption
functions
Trusted Secure IP
(TSIP-Lite)
Access management circuit
Encryption engine
128- or 256-bit key sizes of AES
Block cipher mode of operation: GCM, ECB, CBC, CMAC, XTS, CTR, GCTR
Hash function
True random number generator
Prevention from illicit copying of a key
Operating frequency
Power supply voltage
Up to 160 MHz
VCC = 2.7 to 5.5V
AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V (VCC ≤ AVCC0 = AVCC1 = AVCC2)
With USB in use: VCC_USB = 3.0 to 3.6V (VCC ≥ VCC_USB)
With USB not in use: VCC_USB = VCC
VSS = AVSS0 = AVSS1 = AVSS2 = VSS_USB = 0V
Operating temperature
Package
D-version: –40 to +85°C
G-version: –40 to +105°C
144-pin LFQFP 0.5 mm pitch
112-pin LQFP 0.65 mm pitch
100-pin LFQFP 0.5 mm pitch
80-pin LFQFP 0.5 mm pitch
80-pin LQFP 0.65 mm pitch
64-pin LFQFP 0.5 mm pitch
Debugging interfaces
JTAG and One-line FINE interfaces
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 10 of 201
RX66T Group
1. Overview
Table 1.2
Comparison of Functions for Different Packages (1/2)
RX66T Group
RAM 64 Kbytes
RAM 128 Kbytes
Without
PGA
Without
PGA
pseudo-
differenti
al input
With PGA pseudo-differential
input
pseudo- With PGA pseudo-differential input
differenti
al input
With USB
144 Pins 100 Pins 100 Pins 100 Pins 112 Pins 100 Pins 80 Pins 64 Pins 100 Pins
Maximum 1 Mbyte Maximum 512 Kbytes
16 bits
Without USB
Module/Functions
Code flash memory capacity
External External bus width
—
—
—
16 bits
bus
Address Space
2 Mbytes × 4 areas
2 Mbytes × 3 areas
—
2 Mbytes
× 3 areas
External NMI
Available
interrupts
IRQ
16 channels
13
11
16
channels channels channels
DMA
DMA controller
Available
Available
Data transfer controller
Timers
Multifunction timer pulse
unit 3
9 channels (Ch. 0 to 7, Ch. 9)
General PWM timer
High resolution PWM
Port output enable 3
10 channels
4 channels
Available
Port Output Enable for
GPTW
Available
8-bit timer
2 channels × 4 units
2 channels × 2 units
Available
Compare match timer
Independent watchdog
timer
Commun USB 2.0 FS host/
1 channel
—
5 channels (SCI1, 5, 6, 8, 9)
1 channel (SCI11)
ication
function module
functions
Serial communications
interfaces (SCIj)
Serial communications
interfaces (SCIi)
Serial communications
interfaces (SCIh)
1 channel (SCI12)
I2C bus interfaces
1 channel
1 channel
Serial peripheral
interface
CAN module
1 channel
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 11 of 201
RX66T Group
1. Overview
Table 1.2
Comparison of Functions for Different Packages (2/2)
RX66T Group
RAM 64 Kbytes
RAM 128 Kbytes
Without
PGA
Without
PGA
pseudo-
differenti
al input
With PGA pseudo-differential
input
pseudo- With PGA pseudo-differential input
differenti
al input
With USB
Without USB
Module/Functions
144 Pins 100 Pins 100 Pins 100 Pins 112 Pins 100 Pins 80 Pins 64 Pins 100 Pins
12-bit A/D Converter
AN000 to
007*1
(unit 0: 8
channels)
AN000 to 003,
007*1 (unit 0: 5
channels)
AN000 to AN000 to 003, 007*1 AN000 to AN000 to AN000 to
003 (unit (unit 0: 5 channels)
0: 4
003,
007*1
002,
007*1
003 (unit
0: 4
channels)
(unit 0: 5 (unit 0: 4 channels)
channels) channels)
AN100 to
107*1
(unit 1: 8
channels)
AN100 to 103,
107*1 (unit 1: 5
channels)
AN100 to AN100 to 103, 107*1 AN100 to AN100 to AN100 to
103 (unit (unit 1: 5 channels)
1: 4
103,
107*1
102,
107*1
103 (unit
1: 4
channels)
(unit 1: 5 (unit 1: 4 channels)
channels) channels)
AN200 to AN200 to 203, 206 AN200 to AN200 to 203, 206 to AN200 to AN200 to AN200 to
211, 216, to 211, 216, 217 211, 216, 211, 216, 217 (unit 2: 203, 208, 202, 210, 211, 216,
217 (unit (unit 2: 12 channels) 217 (unit 12 channels) 210, 211, 211, 216, 217 (unit
216, 217 217 2: 14
2: 14
2: 14
channels)
channels)
(unit 2: 9 (unit 2: 7 channels)
channels) channels)
3 channels
simultaneous sampling
function
3 channels × 2 units (unit 0, 1)
6 channels
Programmable gain
amplifier
Comparator C
6 channels
2 channels
1 channel
Available
Available
D/A converter
Temperature sensor
CRC calculator
Clock frequency accuracy
measurement circuit
Trusted Secure IP (TSIP-Lite)
Event link controller
Packages
Available/Not available
Available
144-pin 100-pin 100-pin
100-pin
LFQFP
112-pin
LQFP
100-pin
LFQFP
80-pin
LFQFP,
LQFP
64-pin
LFQFP
100-pin
LFQFP
LFQFP
LFQFP
LFQFP
Note 1. AN007 and AN107 cannot be used when PGA pseudo-differential input is enabled.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 12 of 201
RX66T Group
1. Overview
1.2
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.
Table 1.3
List of Products (1/3)
Code
Flash
Data
Flash
PGA
pseudo-
Operati
ng
RAM
Part No.
(for Orders)
Memory Capacit Memory differential
temper
ature
Group Part No.
Package
Capacity
y
Capacity input
TSIP-Lite
USB
Note
RX66T R5F566TKCD R5F566TKCD PLQP0144KA- 1 Mbyte 128
FB FB#30 Kbytes
32 Kbytes Available
Not
available
Available
-40 to
85°C
B
R5F566TKGD R5F566TKGD PLQP0144KA- 1 Mbyte 128
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
Available
Available
Available
Available
-40 to
85°C
FB
FB#30
B
Kbytes
R5F566TFCD R5F566TFCD PLQP0144KA- 512
128
Not
available
-40 to
85°C
FB FB#30 Kbytes
B
Kbytes
R5F566TFGD R5F566TFGD PLQP0144KA- 512
FB FB#30 Kbytes
128
Kbytes
Available
-40 to
85°C
B
R5F566TEAD R5F566TEAD PLQP0112JA- 512
FH FH#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
85°C
B
R5F566TEED R5F566TEED PLQP0112JA- 512
FH FH#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
B
R5F566TAAD R5F566TAAD PLQP0112JA- 256
FH FH#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
85°C
B
R5F566TAED R5F566TAED PLQP0112JA- 256
FH FH#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
B
R5F566TKAD R5F566TKAD PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
Not
available
Not
available
-40 to
85°C
B
R5F566TKBD R5F566TKBD PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
85°C
B
R5F566TKCD R5F566TKCD PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Available
Not
available
Available
-40 to
85°C
B
R5F566TKED R5F566TKED PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Available
Available
Available
Available
Not
available
-40 to
85°C
B
R5F566TKFD R5F566TKFD PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Not
available
Not
available
-40 to
85°C
B
R5F566TKGD R5F566TKGD PLQP0100KB- 1 Mbyte 128
32 Kbytes Available
Available
-40 to
85°C
FP
FP#30
B
Kbytes
R5F566TFADF R5F566TFADF PLQP0100KB- 512
128
Kbytes
32 Kbytes Available
Not
available
Not
available
-40 to
85°C
P
P#30 Kbytes
B
R5F566TFBD R5F566TFBD PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
85°C
B
R5F566TFCD R5F566TFCD PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Available
Not
available
Available
-40 to
85°C
B
R5F566TFED R5F566TFED PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Available
Available
Available
Available
Not
available
-40 to
85°C
B
R5F566TFFDF R5F566TFFDF PLQP0100KB- 512
P#30 Kbytes
128
Kbytes
32 Kbytes Not
available
Not
available
-40 to
85°C
P
B
R5F566TFGD R5F566TFGD PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Available
Available
-40 to
85°C
B
R5F566TEAD R5F566TEAD PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Not
available
Not
available
-40 to
85°C
B
R5F566TEBD R5F566TEBD PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
85°C
B
R5F566TEED R5F566TEED PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Available
Available
Not
available
-40 to
85°C
B
R5F566TEFD R5F566TEFD PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Not
available
Not
available
-40 to
85°C
B
R5F566TAAD R5F566TAAD PLQP0100KB- 256
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Not
available
Not
available
-40 to
85°C
B
R5F566TABD R5F566TABD PLQP0100KB- 256
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
85°C
B
R5F566TAED R5F566TAED PLQP0100KB- 256
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Available
Not
available
-40 to
85°C
B
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 13 of 201
RX66T Group
1. Overview
Table 1.3
List of Products (2/3)
Code
Flash
Data
Flash
PGA
pseudo-
Operati
ng
RAM
Part No.
(for Orders)
Memory Capacit Memory differential
temper
ature
Group Part No.
Package
Capacity
y
Capacity input
TSIP-Lite
USB
Note
RX66T R5F566TAFDF R5F566TAFDF PLQP0100KB- 256
P#30 Kbytes
64
Kbytes
32 Kbytes Not
Available
Not
available
-40 to
85°C
P
B
available
R5F566TEAD R5F566TEAD PLQP0080JA- 512
FF FF#30 Kbytes
64
Kbytes
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
Not
available
Not
available
-40 to
85°C
A
R5F566TEED R5F566TEED PLQP0080JA- 512
FF FF#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
A
R5F566TAAD R5F566TAAD PLQP0080JA- 256
FF FF#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
85°C
A
R5F566TAED R5F566TAED PLQP0080JA- 256
FF FF#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
A
R5F566TEAD R5F566TEAD PLQP0080KB- 512
FN FN#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
85°C
B
R5F566TEED R5F566TEED PLQP0080KB- 512
FN FN#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
B
R5F566TAAD R5F566TAAD PLQP0080KB- 256
FN FN#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
85°C
B
R5F566TAED R5F566TAED PLQP0080KB- 256
FN FN#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
B
R5F566TEAD R5F566TEAD PLQP0064KB- 512
FM FM#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
85°C
C
R5F566TEED R5F566TEED PLQP0064KB- 512
FM FM#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
C
R5F566TAAD R5F566TAAD PLQP0064KB- 256
FM FM#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
85°C
C
R5F566TAED R5F566TAED PLQP0064KB- 256
FM FM#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
85°C
C
R5F566TKCG R5F566TKCG PLQP0144KA- 1 Mbyte 128
FB FB#30 Kbytes
Not
available
Available
Available
Available
Available
-40 to
105°C
B
R5F566TKGG R5F566TKGG PLQP0144KA- 1 Mbyte 128
Available
-40 to
105°C
FB
FB#30
B
Kbytes
R5F566TFCG R5F566TFCG PLQP0144KA- 512
128
Kbytes
Not
available
-40 to
105°C
FB FB#30 Kbytes
B
R5F566TFGG R5F566TFGG PLQP0144KA- 512
FB FB#30 Kbytes
128
Kbytes
Available
-40 to
105°C
B
R5F566TEAG R5F566TEAG PLQP0112JA- 512
FH FH#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
105°C
B
R5F566TEEG R5F566TEEG PLQP0112JA- 512
FH FH#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
B
R5F566TAAG R5F566TAAG PLQP0112JA- 256
FH FH#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
105°C
B
R5F566TAEG R5F566TAEG PLQP0112JA- 256
FH FH#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
B
R5F566TKAG R5F566TKAG PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
Not
available
Not
available
-40 to
105°C
B
R5F566TKBG R5F566TKBG PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
105°C
B
R5F566TKCG R5F566TKCG PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Available
Not
available
Available
-40 to
105°C
B
R5F566TKEG R5F566TKEG PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Available
Available
Available
Available
Not
available
-40 to
105°C
B
R5F566TKFG R5F566TKFG PLQP0100KB- 1 Mbyte 128
FP FP#30 Kbytes
32 Kbytes Not
available
Not
available
-40 to
105°C
B
R5F566TKGG R5F566TKGG PLQP0100KB- 1 Mbyte 128
32 Kbytes Available
Available
-40 to
105°C
FP
FP#30
B
Kbytes
R5F566TFAG R5F566TFAG PLQP0100KB- 512
128
Kbytes
32 Kbytes Available
Not
available
Not
available
-40 to
105°C
FP FP#30 Kbytes
B
R5F566TFBG R5F566TFBG PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
105°C
B
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 14 of 201
RX66T Group
1. Overview
Table 1.3
List of Products (3/3)
Code
Flash
Data
Flash
PGA
pseudo-
Operati
ng
RAM
Part No.
(for Orders)
Memory Capacit Memory differential
temper
ature
Group Part No.
Package
Capacity
y
Capacity input
TSIP-Lite
USB
Note
RX66T R5F566TFCG R5F566TFCG PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Available
Not
available
Available
-40 to
105°C
B
R5F566TFEG R5F566TFEG PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Available
Available
Available
Available
Not
available
-40 to
105°C
B
R5F566TFFG R5F566TFFG PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Not
available
Not
available
-40 to
105°C
B
R5F566TFGG R5F566TFGG PLQP0100KB- 512
FP FP#30 Kbytes
128
Kbytes
32 Kbytes Available
Available
-40 to
105°C
B
R5F566TEAG R5F566TEAG PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Not
available
Not
available
-40 to
105°C
B
R5F566TEBG R5F566TEBG PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
105°C
B
R5F566TEEG R5F566TEEG PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Available
Not
available
-40 to
105°C
B
R5F566TEFG R5F566TEFG PLQP0100KB- 512
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Not
available
Available
Not
available
-40 to
105°C
B
R5F566TAAG R5F566TAAG PLQP0100KB- 256
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Not
available
Not
available
-40 to
105°C
B
R5F566TABG R5F566TABG PLQP0100KB- 256
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Not
available
Not
available
Not
available
-40 to
105°C
B
R5F566TAEG R5F566TAEG PLQP0100KB- 256
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Available
Available
Available
Not
available
-40 to
105°C
B
R5F566TAFG R5F566TAFG PLQP0100KB- 256
FP FP#30 Kbytes
64
Kbytes
32 Kbytes Not
available
Not
available
-40 to
105°C
B
R5F566TEAG R5F566TEAG PLQP0080JA- 512
FF FF#30 Kbytes
64
Kbytes
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
32 Kbytes Available
Not
available
Not
available
-40 to
105°C
A
R5F566TEEG R5F566TEEG PLQP0080JA- 512
FF FF#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
A
R5F566TAAG R5F566TAAG PLQP0080JA- 256
FF FF#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
105°C
A
R5F566TAEG R5F566TAEG PLQP0080JA- 256
FF FF#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
A
R5F566TEAG R5F566TEAG PLQP0080KB- 512
FN FN#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
105°C
B
R5F566TEEG R5F566TEEG PLQP0080KB- 512
FN FN#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
B
R5F566TAAG R5F566TAAG PLQP0080KB- 256
FN FN#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
105°C
B
R5F566TAEG R5F566TAEG PLQP0080KB- 256
FN FN#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
B
R5F566TEAG R5F566TEAG PLQP0064KB- 512
FM
FM#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
105°C
C
R5F566TEEG R5F566TEEG PLQP0064KB- 512
FM FM#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
C
R5F566TAAG R5F566TAAG PLQP0064KB- 256
FM FM#30 Kbytes
64
Kbytes
Not
available
Not
available
-40 to
105°C
C
R5F566TAEG R5F566TAEG PLQP0064KB- 256
FM FM#30 Kbytes
64
Kbytes
Available
Not
available
-40 to
105°C
C
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 15 of 201
RX66T Group
1. Overview
R
5
F
5 6 6 T
E
A
D
F B
Package type, number of pins, and pin pitch
FB: LFQFP/144/0.50
FH: LQFP/112/0.65
FP: LFQFP/100/0.50
FF: LQFP/80/0.65
FN: LFQFP/80/0.50
FM: LFQFP/64/0.50
D: Operating peripheral temperature: –40 to +85°C
G: Operating peripheral temperature: –40 to +105°C
A: With PGA pseudo-differential input, without TSIP-Lite,
without USB
B: Without PGA pseudo-differential input, without TSIP-Lite,
without USB
C: With PGA pseudo-differential input, without TSIP-Lite,
with USB
E: With PGA pseudo-differential input, with TSIP-Lite,
without USB
F: Without PGA pseudo-differential input, with TSIP-Lite,
without USB
G: With PGA pseudo-differential input, with TSIP-Lite,
with USB
Code flash memory, RAM, and data flash memory capacity
K: 1 Mbyte/128 Kbytes/32 Kbytes
F: 512 Kbytes/128 Kbytes/32 Kbytes
E: 512 Kbytes/64 Kbytes/32 Kbytes
A: 256 Kbytes/64 Kbytes/32 Kbytes
Group name
6T: RX66T Group
Series name
RX600 Series
Type of memory
F: Flash memory version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part Number
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Feb 08, 2019
Page 16 of 201
RX66T Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows a block diagram.
E2 Data flash memory
Trusted Secure IP*1
ELC
SCIi × 1 channel
RSPIc × 1 channel
MTU3d × 9 channels
GPTW × 10 channels
HRPWM
WDTA
IWDTa
CAC
DOC
CRCA
SCIj × 5 channels
SCIh × 1 channel
USBb × 1 port
CAN × 1 channel
RIICa × 1 channel
POE3B
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Port K
POEG
RAM with
ECC
TMR × 8 channels
CMT × 4 channels
12-bit A/D converter × 30 channels
RAM
ROM
ICUC
DTCa
Programmable gain amplifier
× 6 channels
Sample and hold circuit
× 6 channels
DMACAa ×
8 channels
ROM
Cache
Temperature sensor
Comparator C × 6 channels
12-bit DAC × 2 channels
RX CPU
MPU
Clock
generation
circuit
BSC
ICUC:
Interrupt controller
Data transfer controller
Watchdog timer
Independent watchdog timer
CRC (cyclic redundancy check) calculator
RIICa:
MTU3d:
GPTW:
POE3B:
CMT:
I2C bus interface
DTCa:
WDTA:
IWDTa:
CRCA:
Multi-function timer pulse unit 3
General-purpose PWM timer W
Port output enable 3
Compare match timer
SCIj, SCIh, SCIi: Serial communications interface
RSPIc: Serial peripheral interface
Trusted Secure IP:Encryption engine
TMR:
DOC:
CAC:
CAN:
8-bit timer
Data operation circuit
Clock frequency accuracy measurement circuit
CAN module
*1
POEG:
HRPWM:
ELC:
Port output enable for GPTW
High resolution PWM
Event link controller
USBb:
USB2.0 FS host/function module
Note 1. Optional
Figure 1.2
Block Diagram
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Feb 08, 2019
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RX66T Group
1. Overview
1.4
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/6)
Pin Name
Classifications
I/O
Description
Digital power supply
VCC
—
Power supply pin. Connect this pin to the system power supply.
Connect the pin to VSS via a 0.1-μF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VCL
—
—
Connect this pin to VSS via a 0.47-μF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VSS
Ground pin. Connect it to the system power supply (0 V).
Clock
XTAL
EXTAL
BCLK
CACREF
MD
Output Pins for a crystal resonator. An external clock signal can be
input through the EXTAL pin.
Input
Output Outputs the external bus clock for external devices.
CAC
Input
Input
Input pin for the clock frequency accuracy measurement circuit.
Operating mode control
Pins for setting the operating mode. The signal levels on these
pins must not be changed during operation.
UB
Input
Input
Enable pin for boot mode (USB interface) and user boot mode
UPSEL
Selects the power supply method in boot mode (USB interface).
The low level selects self-power mode and the high level selects
bus power mode.
System control
RES#
EMLE
Input
Input
Reset pin. This MCU enters the reset state when this signal
goes low.
Input pin for the on-chip emulator enable signal. When the on-
chip emulator is used, this pin should be driven high. When not
used, it should be driven low.
On-chip emulator
FINED
TRST#
TMS
I/O
FINE interface pin.
Input
Input
Input
Input
Output
Pins for the on-chip emulator. When the EMLE pin is driven
high, these pins are dedicated for the on-chip emulator.
TDI
TCK
TDO
TRCLK
Output This pin outputs the clock for synchronization with the trace
data.
TRSYNC
Output This pin indicates that output from the TRDATA0 to TRDATA3
pins is valid.
TRSYNC1
Output This pin indicates that output from the TRDATA4 to TRDATA7
pins is valid.
TRDATA0, TRDATA1,
TRDATA2, TRDATA3,
TRDATA4, TRDATA5,
TRDATA6, TRDATA7
Output These pins output the trace information.
Address bus
Data bus
A0 to A20
D0 to D15
A0/D0 to A15/D15
RD#
Output Output pins for the address
I/O
I/O
Input and output pins for the bidirectional data bus
Address/data multiplexed bus
Multiplexed bus
Bus control
Output Strobe signal which indicates that reading from the external bus
interface space is in progress
WR#
Output Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode
WR0#, WR1#
Output Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8) is valid in writing to the external bus
interface space, in byte strobe mode
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Feb 08, 2019
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RX66T Group
1. Overview
Table 1.4
Pin Functions (2/6)
Classifications
Pin Name
I/O
Description
Bus control
BC0#, BC1#
Output Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8) is valid in access to the external bus
interface space, in 1-write strobe mode
ALE
Output Address latch signal when address/data multiplexed bus is
selected
WAIT#
Input
Input pin for wait request signals in access to the external space
CS0# to CS3#
NMI
Output Select signals for CS areas
Interrupt
Input
Input
Input
Non-maskable interrupt request pin
Maskable interrupt request pins
IRQ0 to IRQ15
IRQ0-DS to IRQ15-DS
Maskable interrupt request pins or pins which can also be used
as triggers for release from deep software standby
Multi-function timer pulse MTIOC0A, MTIOC0B,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins
unit 3
MTIOC0C, MTIOC0D
MTIOC0A#, MTIOC0B#,
MTIOC0C#, MTIOC0D#
The TGRA0 to TGRD0 input capture inverted input/output
compare inverted output/PWM inverted output pins.
MTIOC1A, MTIOC1B
MTIOC1A#, MTIOC1B#
MTIOC2A, MTIOC2B
MTIOC2A#, MTIOC2B#
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins.
The TGRA1 and TGRB1 input capture inverted input/output
compare inverted output/PWM inverted output pins.
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins.
The TGRA2 and TGRB2 input capture inverted input/output
compare inverted output/PWM inverted output pins.
MTIOC3A, MTIOC3B,
MTIOC3C, MTIOC3D
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins.
MTIOC3A#, MTIOC3B#,
MTIOC3C#, MTIOC3D#
The TGRA3 to TGRD3 input capture inverted input/output
compare inverted output/PWM inverted output pins.
MTIOC4A, MTIOC4B,
MTIOC4C, MTIOC4D
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins
MTIOC4A#, MTIOC4B#,
MTIOC4C#, MTIOC4D#
The TGRA4 to TGRD4 input capture inverted input/output
compare inverted output/PWM inverted output pins.
MTIC5U, MTIC5V, MTIC5W
The TGRU5, TGRV5, and TGRW5 input capture input/external
pulse input pins
MTIC5U#, MTIC5V#,
MTIC5W#
The TGRU5, TGRV5, and TGRW5 input capture inverted input/
external pulse inverted input pins.
MTIOC6A, MTIOC6B,
MTIOC6C, MTIOC6D
The TGRA6 to TGRD6 input capture input/output compare
output/PWM output pins
MTIOC6A#, MTIOC6B#,
MTIOC6C#, MTIOC6D#
The TGRA6 to TGRD6 input capture inverted input/output
compare inverted output/PWM inverted output pins.
MTIOC7A, MTIOC7B,
MTIOC7C, MTIOC7D
The TGRA7 to TGRD7 input capture input/output compare
output/PWM output pins
MTIOC7A#, MTIOC7B#,
MTIOC7C#, MTIOC7D#
The TGRA7 to TGRD7 input capture inverted input/output
compare inverted output/PWM inverted output pins.
MTIOC9A, MTIOC9B,
MTIOC9C, MTIOC9D
The TGRA9 to TGRD9 input capture input/output compare
output/PWM output pins
MTIOC9A#, MTIOC9B#,
MTIOC9C#, MTIOC9D#
The TGRA9 to TGRD9 input capture inverted input/output
compare inverted output/PWM inverted output pins.
MTCLKA, MTCLKB, MTCLKC, Input
MTCLKD
Input pins for the external clock.
MTCLKA#, MTCLKB#,
MTCLKC#, MTCLKD#
Input
Inverted input pins for the external clock.
ADSM0, ADSM1
Output A/D conversion start request frame synchronization signal
output pins.
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Feb 08, 2019
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RX66T Group
1. Overview
Table 1.4
Pin Functions (3/6)
Pin Name
Classifications
I/O
Description
General PWM timer
GTETRGA, GTETRGB,
GTETRGC, GTETRGD
Input
External trigger input pin
GTIOC0A to GTIOC9A,
GTIOC0B to GTIOC9B
I/O
I/O
Input capture input/output compare output/PWM output pins
GTIOC0A# to GTIOC9A#,
GTIOC0B# to GTIOC9B#
Input capture inverted input/output compare inverted output/
PWM inverted output pins
GTADSM0, GTADSM1
TMO0 to TMO7
Output A/D conversion start request monitoring output pins
Output Compare match output pins.
8-bit timer
TMCI0 to TMCI7
TMRI0 to TMRI7
Input
Input
Input
Input pins for the external clock to be input to the counter.
Counter reset input pins.
Port output enable 3
POE0#, POE4#, POE8#,
POE9#, POE10#, POE11#,
POE12#, POE13#, POE14#
Input pins for request signals to switch the MTU3 and GPTW
pins between the high impedance state
Serial communications
interface (SCIj)
Asynchronous mode/clock synchronous mode
SCK1, SCK5, SCK6, SCK8,
SCK9
I/O
Input/output pins for the clock
RXD1, RXD5, RXD6, RXD8,
RXD9
Input
Input pins for received data
TXD1, TXD5, TXD6, TXD8,
TXD9
Output Output pins for transmitted data
Input Input pins for controlling the start of transmission and reception.
CTS1#, CTS5#, CTS6#,
CTS8#, CTS9#
RTS1#, RTS5#, RTS6#,
RTS8#, RTS9#
Output Output pins for controlling the start of transmission and
reception.
Simple I2C mode
SSCL1, SSCL5, SSCL6,
SSCL8, SSCL9
I/O
I/O
Input/output pins for the I2C clock.
Input/output pins for the I2C data.
SSDA1, SSDA5, SSDA6,
SSDA8, SSDA9
Simple SPI mode
SCK1, SCK5, SCK6, SCK8,
SCK9
I/O
Input/output pins for the clock
SMISO1, SMISO5, SMISO6,
SMISO8, SMISO9
I/O
Input/output pins for slave transmit data.
Input/output pins for master transmit data.
Chip-select input pins.
SMOSI1, SMOSI5, SMOSI6,
SMOSI8, SMOSI9
I/O
SS1#, SS5#, SS6#, SS8#,
SS9#
Input
Serial communications
interface (SCIh)
Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock
Input pin for received data
RXD12
Input
TXD12
Output Output pin for transmitted data
Input Input pin for controlling the start of transmission and reception
Output Output pin for controlling the start of transmission and reception
CTS12#
RTS12#
Simple I2C mode
SSCL12
I/O
I/O
Input/output pin for the I2C clock
Input/output pin for the I2C data
SSDA12
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Feb 08, 2019
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RX66T Group
1. Overview
Table 1.4
Pin Functions (4/6)
Pin Name
Classifications
I/O
Description
Serial communications
interface (SCIh)
Simple SPI mode
SCK12
I/O
Input/output pin for the clock
SMISO12
I/O
Input/output pin for slave transmission of data
Input/output pin for master transmission of data
Chip-select input pin
SMOSI12
I/O
SS12#
Input
Extended serial mode
RXDX12
Input
Input pin for received data
TXDX12
Output Output pin for transmitted data
I/O Input/output pin for received or transmitted data
SIOX12
Serial communications
interface (SCIi)
Asynchronous mode/clock synchronous mode
SCK11
I/O
Input/output pin for the clock
Input pin for received data
RXD11
Input
TXD11
Output Output pin for transmitted data
Input Input pin for controlling the start of transmission and reception
Output Output pin for controlling the start of transmission and reception
CTS11#
RTS11#
Simple I2C mode
SSCL11
I/O
I/O
Input/output pin for the I2C clock
Input/output pin for the I2C data
SSDA11
Simple SPI mode
SCK11
I/O
Input/output pin for the clock
SMISO11
SMOSI11
SS11#
I/O
Input/output pin for slave transmission of data
Input/output pin for master transmission of data
Chip-select input pin
I/O
Input
I/O
I2C bus interface
SCL
Input/output pin for I2C bus interface clocks. Bus can be directly
driven by the N-channel open drain output.
SDA
I/O
Input/output pin for I2C bus interface data. Bus can be directly
driven by the N-channel open drain output.
USB 2.0 host/function
module
VCC_USB
Input
Input
I/O
Power supply pins
VSS_USB
Ground pins
USB0_DP
Input or output USB transceiver D+ data
Input or output USB transceiver D- data.
USB0_DM
I/O
USB0_EXICEN
USB0_ID
Output Connect to the OTG power IC.
Input Connect to the OTG power IC.
Output USB VBUS power enable pins
USB0_VBUSEN
USB0_OVRCURA,
USB0_OVRCURB
Input
USB overcurrent pins
USB0_VBUS
CRX
Input
Input
USB cable connection/disconnection detection input pins
Input pins
CAN module
CTX
Output Output pins
Serial peripheral interface RSPCKA
I/O
I/O
I/O
I/O
Input/output pin for the RSPI clock.
MOSIA
MISOA
SSLA0
Input/output pin for transmitting data from the RSPI master.
Input/output pin for transmitting data from the RSPI slave.
Input/output pin to select the slave for the RSPI.
SSLA1 to SSLA3
Output Output pins to select the slave for the RSPI.
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Feb 08, 2019
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RX66T Group
1. Overview
Table 1.4
Pin Functions (5/6)
Pin Name
Classifications
I/O
Description
12-bit A/D converter
AN000 to AN002,
AN100 to AN102
Input
Input pins for the analog signals to be processed by the A/D
converter. (Positive side input at PGA pseudo-differential input.)
AN003 to AN007,
AN103 to AN107,
AN200 to AN211,
AN216 to AN217
Input
Input pins for the analog signals to be processed by the A/D
converter.
ADST0, ADST1, ADST2
Output Output pins for A/D conversion status.
ADTRG0#, ADTRG1#,
ADTRG2#
Input
Input pins for the external trigger signals that start the A/D
conversion.
PGAVSS0, PGAVSS1
Input
A common reference ground pin for PGA pseudo-differential
input in the unit
12-bit D/A converter
Comparator C
DA0, DA1
Output Output pins for the analog signals to be processed by the D/A
converter
COMP0 to COMP5
CVREFC0, CVREFC1
CMPCnm
Output Comparator detection result output pins.
Input
Input
—
Analog reference voltage supply pins for comparator C.
Analog input pin for CMPCnm (n = 0 to 5, m = 0 to 3)
Analog power supply
AVCC0
Analog voltage supply pin for 12-bit A/D converter unit 0.
Connect the AVCC0 pin to AVCC1 or AVCC2 when 12-bit A/D
converter unit 0 is not used.
AVSS0
AVCC1
—
—
Analog ground pin for 12-bit A/D converter unit 0. Connect the
AVSS0 pin to AVSS1 or AVSS2 when 12-bit A/D converter unit
0 is not used.
Analog voltage supply pin for 12-bit A/D converter unit 1.
Connect this pin to AVCC0 when not using the 12-bit A/D
converter 1 but using the 12-bit A/D converter 0.
Connect this pin to AVCC2 when not using the 12-bit A/D
converter 0 and the 12-bit A/D converter 1.
AVSS1
AVCC2
—
—
Analog ground pin for 12-bit A/D converter unit 1.
Connect this pin to AVSS0 when not using the 12-bit A/D
converter 1 but using the 12-bit A/D converter 0.
Connect this pin to AVSS2 when not using the 12-bit A/D
converter 0 and the 12-bit A/D converter 1.
Analog voltage supply pin for the 12-bit A/D converter unit 2,
reference voltage supply pin for the 12-bit D/A converter, analog
voltage supply pin for the comparator C, and analog voltage
supply pin for the temperature sensor.
Connect this pin to either of AVCC0 or AVCC1 when not using
the 12-bit A/D converter unit 2, 12-bit D/A converter, comparator
C, and temperature sensor.
AVSS2
—
Analog ground pin for the 12-bit A/D converter unit 2, reference
ground pin for the D/A converter, analog ground pin for the
comparator C, and analog ground pin for the temperature
sensor.
Connect this pin to either of AVSS0 or AVSS1 when not using
the 12-bit A/D converter unit 2, 12-bit D/A converter, comparator
C, and temperature sensor.
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Feb 08, 2019
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RX66T Group
1. Overview
Table 1.4
Pin Functions (6/6)
Classifications
Pin Name
P00, P01
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
I/O ports
2-bit input/output pins.
8-bit input/output pins.
8-bit input/output pins.
8-bit input/output pins.
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P55
P60 to P65
P70 to P76
P80 to P82
P90 to P96
PA0 to PA7
PB0 to PB7
PC0 to PC6
PD0 to PD7
PE0 to PE6
PF0 to PF3
PG0 to PG2
PH0 to PH7
PK0 to PK2
8-bit input/output pins (P40 to P42, P44 to P46: input).
6-bit input/output pins.
6-bit input/output pins.
7-bit input/output pins.
3-bit input/output pins.
7-bit input/output pins.
8-bit input/output pins.
8-bit input/output pins.
7-bit input/output pins.
8-bit input/output pins.
7-bit input/output pins (PE2: input).
4-bit input/output pins.
3-bit input/output pins.
8-bit input/output pins (PH0, PH4: input).
3-bit input/output pins.
Note:
Note:
When not using any of the A/D converter, D/A converter, comparator C and temperature sensor, connect the AVCC0, AVCC1
and AVCC2 pins to VCC, and connect the AVSS0, AVSS1 and AVSS2 pins to VSS, respectively.
When the pin functions have “-DS” appended to their names, they can also be used as triggers for release from deep software
standby.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 23 of 201
RX66T Group
1. Overview
1.5
Pin Assignments
Figure 1.3 to Figure 1.9 show the pin assignments. Table 1.5 to Table 1.11 show the lists of pins and pin functions.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
P61
P60
P55
P54
P53
P52
P51
P50
PH7
PH6
PH5
P47
P46
P45
P44
P90
P91
P92
P93
P94
P95
VSS
P96
VCC
PC5
PC6
P34
P35
PA0
PA1
RX66T Group
LFQFP-144
(Top view)
PH4/PGAVSS1
PH3
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PH2
PH1
P43
P42
P41
P40
PH0/PGAVSS0
PB3
PC0
AVCC1
AVCC0
AVSS0
AVSS1
P82
PC1
PC2
VSS
PB4
VCC
PB5
P81
P80
P11
P10
P17
P16
P15
PB6
PB7
VCC_USB
VSS_USB
Figure 1.3
Pin Assignment (144-pin LFQFP) with PGA pseudo-differential input and with USB pin
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RX66T Group
1. Overview
P61
56
P90
P91
P92
P93
P94
P95
VSS
P96
VCC
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PC0
PC1
PC2
VSS
PB4
VCC
PB5
PB6
PB7
85
86
P60
P55
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
87
P54
88
P53
89
P52
90
P47
91
P46
92
P45
93
P44
94
PH4/PGAVSS1
P43
95
RX66T Group
LQFP-112
96
P42
97
P41
98
(Top view)
P40
99
PH0/PGAVSS0
AVCC1
AVCC0
AVSS0
AVSS1
P82
100
101
102
103
104
105
106
107
108
109
110
111
112
P81
P80
P11
P10
P17
P16
P15
Figure 1.4
Pin Assignment (112-pin LQFP) with PGA pseudo-differential input and without USB pin
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RX66T Group
1. Overview
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P61
P90
P91
P92
P93
P94
P95
VSS
P96
VCC
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
P60
P55
P54
P53
P52
P47
P46
P45
P44
PH4/PGAVSS1
P43
RX66T Group
LFQFP-100
(Top view)
P42
P41
P40
PH0/PGAVSS0
AVCC1
AVCC0
AVSS0
AVSS1
P82
VSS/VSS_USB
PB4
P81
VCC
P80
PB5
P11
PB6
P10
VCC_USB
Figure 1.5
Pin Assignment (100-pin LFQFP) with PGA pseudo-differential input and with USB pin
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RX66T Group
1. Overview
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P61
P60
P55
P54
P53
P52
P47
P46
P45
P44
P90
P91
P92
P93
P94
P95
VSS
P96
VCC
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
VSS
PB4
VCC
PB5
PB6
PB7
PH4/PGAVSS1
P43
RX66T Group
LFQFP-100
(Top view)
P42
P41
P40
PH0/PGAVSS0
AVCC1
AVCC0
AVSS0
AVSS1
P82
P81
P80
P11
P10
Figure 1.6
Pin Assignment (100-pin LFQFP) with PGA pseudo-differential input and without USB pin
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 27 of 201
RX66T Group
1. Overview
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P61
P90
P60
P55
P91
P92
P93
P94
P95
VSS
P96
VCC
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
VSS
PB4
VCC
PB5
PB6
PB7
P54
P53
P52
P51
P50
P47
P46
P45
P44
RX66T Group
LFQFP-100
(Top view)
P43
P42
P41
P40
AVCC1
AVCC0
AVSS0
AVSS1
P82
P81
P80
P11
P10
Figure 1.7
Pin Assignment (100-pin LFQFP) without PGA pseudo-differential input and without USB pin
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 28 of 201
RX66T Group
1. Overview
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P90
P91
P92
P93
P94
P95
VSS
P96
VCC
PA3
PA5
PB0
PB1
PB2
PB3
VSS
PB4
VCC
PB5
PB6
P55
P54
P53
P52
P47
P46
P45
P44
RX66T Group
LQFP-80
PH4/PGAVSS1
P43
P42
LFQFP-80
(Top view)
P41
P40
PH0/PGAVSS0
AVCC1
AVCC0
AVSS0
AVSS1
P11
P10
Figure 1.8
Pin Assignment (80-pin LQFP and LFQFP) with PGA pseudo-differential input and without USB
pin
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 29 of 201
RX66T Group
1. Overview
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P54
P53
P90
P91
P92
P93
P94
P95
VSS
P96
VCC
PB0
PB1
PB2
PB3
PB4
PB5
PB6
P52
P46
P45
P44
PH4/PGAVSS1
P42
RX66T Group
LFQFP-64
P41
P40
(Top view)
PH0/PGAVSS0
AVCC1
AVCC0
AVSS0
AVSS1
P11
Figure 1.9
Pin Assignment (64-pin LFQFP) with PGA pseudo-differential input and without USB pin
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 30 of 201
RX66T Group
1. Overview
Table 1.5
List of Pin and Pin Functions (144-pin with PGA pseudo-differential input and with USB pin) (1/7)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
144-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
1
2
3
P14
MTIOC4B/
MTIOC4B#/
GTIOC2A/GTIOC9A/
GTIOC2A#/
GTIOC9A#
IRQ11
P13
P12
MTIOC4A/
MTIOC4A#/
GTIOC1A/GTIOC8A/
GTIOC1A#/
GTIOC8A#
IRQ10
IRQ9
MTIOC3B/
MTIOC3B#/
GTIOC0A/GTIOC7A/
GTIOC0A#/
GTIOC7A#
4
5
PE6
PE5
RD#
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/POE10#
IRQ3
IRQ0
BCLK
MTIOC9D/
MTIOC9D#/
GTIOC3A/
GTETRGB/
GTIOC3A#/
GTETRGD
SCK9/CTS9#/
RTS9#/SS9#
ADST0
6
7
8
9
VCC
EMLE
VSS
UB
P00
P01
A11
A10
MTIOC9A/
MTIOC9A#/CACREF SSCL9/RXD12/
SMISO12/SSCL12/
RXD9/SMISO9/
IRQ2
IRQ4
ADST1/
COMP0
RXDX12
10
11
12
VCL
MD/FINED
MTIOC9C/
MTIOC9C#/
GTETRGA/
TXD9/SMOSI9/
SSDA9/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
ADST2/
COMP1
GTETRGB/
GTETRGC/
GTETRGD/POE12#
13
14
PE4
PE3
A9
A8
MTCLKC/MTCLKC#/ SCK9
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/POE10#
IRQ1
MTCLKD/MTCLKD#/ CTS9#/RTS9#/
IRQ2-DS
GTETRGA/
SS9#
GTETRGB/
GTETRGC/
GTETRGD/POE11#
15
16
17
18
19
20
21
RES#
XTAL
VSS
P37
P36
EXTAL
VCC
UPSEL
PE2
PE1
POE10#
NMI
WR0#/WR# MTIOC9D/
MTIOC9D#/TMO5
CTS5#/RTS5#/
SS5#/CTS12#/
RTS12#/SS12#/
SSLA3
IRQ15
22
PE0
WR1#/
BC1#/
WAIT#
MTIOC9B/
MTIOC9B#/TMCI1/
TMCI5
RXD5/SMISO5/
SSCL5/SSLA2/
CRX0
USB0_OVR IRQ7
CURB
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 31 of 201
RX66T Group
1. Overview
Table 1.5
List of Pin and Pin Functions (144-pin with PGA pseudo-differential input and with USB pin) (2/7)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
144-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
23
24
TRST#
TMS
PD7
MTIOC9A/
MTIOC9A#/
GTIOC0A/GTIOC3A/ CTX0
GTIOC0A#/
GTIOC3A#/TMRI1/
TMRI5
TXD5/SMOSI5/
SSDA5/SSLA1/
IRQ8
PD6
MTIOC9C/
MTIOC9C#/
CTS1#/RTS1#/
SS1#/CTS11#/
IRQ5
ADST0
GTIOC0B/GTIOC3B/ RTS11#/SS11#/
GTIOC0B#/
SSLA0
GTIOC3B#/TMO1
25
26
TDI
PD5
PD4
GTIOC1A/
RXD1/SMISO1/
SSCL1/RXD11/
SMISO11/SSCL11
IRQ6
IRQ2
GTETRGA/
GTIOC1A#/TMRI0/
TMRI6
TCK
GTIOC1B/
SCK1/SCK11
GTETRGB/
GTIOC1B#/TMCI0/
TMCI6
27
28
TDO
PD3
PD2
GTIOC2A/
GTETRGC/
GTIOC2A#/TMO0
TXD1/SMOSI1/
SSDA1/TXD11/
SMOSI11/SSDA11
TRCLK
A7
GTIOC2B/GTIOC0A/ SCK5/SCK8/
USB0_VBUS
GTIOC2B#/
GTIOC0A#/TMCI1/
TMO4
MOSIA
29
30
31
TRDATA3
TRDATA2
TRDATA7
PD1
PD0
PF3
A6
GTIOC3A/GTIOC0B/ RXD8/SMISO8/
GTIOC3A#/
SSCL8/MISOA
GTIOC0B#/TMO2
A5
GTIOC3B/GTIOC1A/ TXD8/SMOSI8/
GTIOC3B#/
SSDA8/RSPCKA
GTIOC1A#/TMO6
A19/CS3#
GTETRGA/TMO7
CTS11#/RTS11#/
SS11#/CRX0
IRQ14
COMP0
32
33
TRDATA6
TRDATA5
PF2
PF1
A18/CS2#
A17/CS1#
GTETRGB/TMO3
GTETRGC/TMO5
SCK11/CTX0
IRQ5
COMP1
COMP2
RXD11/SMISO11/
SSCL11
IRQ13
34
TRDATA4
PF0
A0/BC0#
GTETRGD/TMO1
TXD11/SMOSI11/
SSDA11
IRQ12
COMP3
35
36
37
38
39
USB0_DM
USB0_DP
VSS_USB
VCC_USB
TRDATA1
PB7
PB6
A4
A3
GTIOC1B/
GTIOC1B#
SCK5/SCK11/
SCK12
USB0_OVR
CURB
40
TRDATA0
GTIOC2A/
GTIOC2A#
RXD5/SMISO5/
SSCL5/RXD11/
SMISO11/SSCL11/
RXD12/SMISO12/
SSCL12/RXDX12/
CRX0
USB0_OVR IRQ2
CURA
41
TRSYNC
PB5
PB4
A2
A1
GTIOC2B/
GTIOC2B#
TXD5/SMOSI5/
SSDA5/TXD11/
SMOSI11/SSDA11/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/CTX0
USB0_VBUS
EN
42
43
VCC
TRSYNC1
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/POE8#
CTS5#/RTS5#/
SS5#/SCK11/
CTS11#/RTS11#/
SS11#
USB0_OVR IRQ3-DS
CURB
44
VSS
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 32 of 201
RX66T Group
1. Overview
Table 1.5
List of Pin and Pin Functions (144-pin with PGA pseudo-differential input and with USB pin) (3/7)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
144-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
45
PC2
CS1#
MTIOC0D/
MTIOC0D#/
GTADSM0
SCK8
USB0_ID/
USB0_OVR
CURA
IRQ15
ADSM0/
COMP5
46
PC1
A16
MTIOC0C/
MTIOC0C#/
GTADSM1
TXD8/SMOSI8/
SSDA8
USB0_EXIC IRQ13
EN/
USB0_VBUS
EN
ADSM1/
COMP4
47
48
49
PC0
PB3
PB2
CS0#
A7
MTIOC0B/
MTIOC0B#
RXD8/SMISO8/
SSCL8
USB0_VBUS IRQ12
COMP3
MTIOC0A/
MTIOC0A#/CACREF
SCK6/RSPCKA
IRQ9
A6
MTIOC0B/
MTIOC0B#/
TXD6/SMOSI6/
SSDA6/SDA
ADSM0
GTADSM0/TMRI0
50
51
PB1
PB0
A5
MTIOC0C/
MTIOC0C#/
GTADSM1/TMCI0
RXD6/SMISO6/
SSCL6/SCL
IRQ4
IRQ8
ADSM1
A0/BC0#/A4 MTIOC0D/
MTIOC0D#/TMO0
TXD6/SMOSI6/
SSDA6/CTS11#/
RTS11#/SS11#/
MOSIA
ADTRG2#
52
53
PA7
PA6
A15
A14
MTCLKA/MTCLKC/ RXD11/SMISO11/
ADSM0
ADSM1
MTCLKA#/
MTCLKC#/
GTADSM0/TMO2
SSCL11/RXD12/
SMISO12/SSCL12/
RXDX12/CRX0
MTCLKB/MTCLKD/ TXD11/SMOSI11/
IRQ7
IRQ1
MTCLKB#/
MTCLKD#/
GTADSM1/TMO6
SSDA11/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
CTX0
54
PA5
A3
MTIOC1A/
MTIOC1A#/TMCI3
RXD6/SMISO6/
SSCL6/RXD8/
SMISO8/SSCL8/
MISOA
ADTRG1#
ADTRG0#
55
56
57
PA4
PA3
PA2
A2
MTIOC1B/
MTIOC1B#/TMCI7
SCK6/TXD8/
SMOSI8/SSDA8/
RSPCKA
A1
MTIOC2A/
MTIOC2A#/
GTADSM0/TMRI7
TXD9/SMOSI9/
SSDA9/SCK8/
SSLA0
A0/BC0#
MTIOC2B/
MTIOC2B#/
CTS6#/RTS6#/
SS6#/RXD9/
GTADSM1/TMO7
SMISO9/SSCL9/
SCK11/SSLA1
58
59
60
61
PA1
PA0
P35
P34
MTIOC6A/
MTIOC6A#/TMO4
TXD9/SMOSI9/
SSDA9/RXD11/
SMISO11/SSCL11/ CURA
SSLA2/CRX0
USB0_ID/
USB0_OVR
IRQ14-DS
ADTRG0#
MTIOC6C/
MTIOC6C#/TMO2
SCK9/TXD11/
SMOSI11/SSDA11/ EN/
SSLA3/CTX0
USB0_EXIC
USB0_VBUS
EN
A13
A12
MTIOC2A/MTIOC9A/ CTS8#/RTS8#/
MTIOC2A#/
MTIOC9A#/
GTADSM0/TMO0
IRQ6
SS8#/TXD1/
SMOSI1/SSDA1
MTIOC2B/MTIOC9B/ CTS9#/RTS9#/
MTIOC2B#/
USB0_OVR IRQ3
CURB
SS9#/RXD1/
MTIOC9B#/
SMISO1/SSCL1
GTADSM1/
GTETRGB/TMO4
62
PC6
MTIOC1A/MTIOC9C/ RXD11/SMISO11/
IRQ11-DS
MTIOC1A#/
MTIOC9C#
SSCL11/CRX0
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 33 of 201
RX66T Group
1. Overview
Table 1.5
List of Pin and Pin Functions (144-pin with PGA pseudo-differential input and with USB pin) (4/7)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
144-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
POE, POEG, CAC) CAN)
I/O Port
Bus
(USB)
(IRQ, NMI)
Analog
Others
63
PC5
MTIOC1B/MTIOC9D/ TXD11/SMOSI11/
IRQ10-DS
MTIOC1B#/
MTIOC9D#
SSDA11/CTX0
64
65
VCC
VSS
P96
CS0#/
WAIT#
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/POE4#
CTS8#/RTS8#/
SS8#
IRQ4-DS
66
67
P95
P94
P93
P92
P91
P90
P76
P75
P74
P73
P72
MTIOC6B/
MTIOC6B#/
GTIOC4A/GTIOC7A/
GTIOC4A#/
GTIOC7A#
68
69
70
71
72
73
74
75
76
77
MTIOC7A/
MTIOC7A#/
GTIOC5A/GTIOC8A/
GTIOC5A#/
GTIOC8A#
MTIOC7B/
MTIOC7B#/
GTIOC6A/GTIOC9A/
GTIOC6A#/
GTIOC9A#
MTIOC6D/
MTIOC6D#/
GTIOC4B/GTIOC7B/
GTIOC4B#/
GTIOC7B#
MTIOC7C/
MTIOC7C#/
GTIOC5B/GTIOC8B/
GTIOC5B#/
GTIOC8B#
MTIOC7D/
MTIOC7D#/
GTIOC6B/GTIOC9B/
GTIOC6B#/
GTIOC9B#
D0 [A0/D0] MTIOC4D/
MTIOC4D#/
GTIOC2B/GTIOC6B/
GTIOC2B#/
GTIOC6B#
D1 [A1/D1] MTIOC4C/
MTIOC4C#/
GTIOC1B/GTIOC5B/
GTIOC1B#/
GTIOC5B#
D2 [A2/D2] MTIOC3D/
MTIOC3D#/
GTIOC0B/GTIOC4B/
GTIOC0B#/
GTIOC4B#
D3 [A3/D3] MTIOC4B/
MTIOC4B#/
GTIOC2A/GTIOC6A/
GTIOC2A#/
GTIOC6A#
D4 [A4/D4] MTIOC4A/
MTIOC4A#/
GTIOC1A/GTIOC5A/
GTIOC1A#/
GTIOC5A#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 34 of 201
RX66T Group
1. Overview
Table 1.5
List of Pin and Pin Functions (144-pin with PGA pseudo-differential input and with USB pin) (5/7)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
144-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
78
P71
D5 [A5/D5] MTIOC3B/
MTIOC3B#/
GTIOC0A/GTIOC4A/
GTIOC0A#/
GTIOC4A#
79
80
P70
D6 [A6/D6] GTETRGA/
GTETRGB/
CTS9#/RTS9#/
SS9#
IRQ5-DS
IRQ2
GTETRGC/
GTETRGD/POE0#
PG2
D11 [A11/
D11]
GTETRGA/
GTIOC0B/
GTIOC0B#
SCK9
COMP0
81
82
83
84
PG1
PG0
PK2
PK1
D12 [A12/
D12]
GTIOC0A/
GTIOC0A#
TXD9/SMOSI9/
SSDA9
IRQ1
COMP1
COMP2
COMP3
COMP4
D13 [A13/
D13]
GTIOC1B/
GTIOC1B#
RXD9/SMISO9/
SSCL9
IRQ0
D14 [A14/
D14]
GTIOC1A/
GTIOC1A#/POE12# SS9#/SCK5
CTS9#/RTS9#/
IRQ9-DS
IRQ8-DS
D15 [A15/
D15]
GTIOC2B/ CTS8#/RTS8#/
GTIOC2B#/POE13# SS8#/TXD5/
SMOSI5/SSDA5
85
86
PK0
P33
CS1#
GTIOC2A/
GTIOC2A#/POE14# SSCL5
RXD5/SMISO5/
IRQ15-DS
IRQ13-DS
COMP5
D7 [A7/D7] MTIOC3A/MTCLKA/ SSLA3
MTIOC3A#/
MTCLKA#/GTIOC3B/
GTIOC3B#/TMO0
87
P32
P31
D8 [A8/D8] MTIOC3C/MTCLKB/ SSLA2
MTIOC3C#/
IRQ12-DS
MTCLKB#/GTIOC3A/
GTIOC3A#/TMO6
88
89
VCC
VSS
D9 [A9/D9] MTIOC0A/MTCLKC/ SSLA1
MTIOC0A#/
IRQ6
MTCLKC#/TMRI6
90
91
P30
P27
D10 [A10/
D10]
MTIOC0B/MTCLKD/ SCK8/CTS8#/
IRQ7
COMP3
MTIOC0B#/
RTS8#/SS8#/
SSLA0
MTCLKD#/TMCI6
92
CS3#
MTIOC1A/MTIOC0C/
MTIOC1A#/
IRQ15
MTIOC0C#/POE9#
93
94
95
P26
P25
P24
CS2#
CS3#
MTIOC9A/
MTIOC9A#
CTS1#/RTS1#/
SS1#
IRQ11
IRQ10
IRQ4
ADST0
ADST1
COMP0
MTIOC9C/
MTIOC9C#
SCK1
D11 [A11/
D11]
MTIC5U/MTIC5U#/
TMCI2/TMO6
CTS8#/RTS8#/
SS8#/SCK8/
RSPCKA
96
97
98
P23
P22
PC4
D12 [A12/
D12]
MTIC5V/MTIC5V#/
TMO2/CACREF
TXD8/SMOSI8/
SSDA8/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
MOSIA/CTX0
IRQ11
IRQ10
COMP1
D13 [A13/
D13]
MTIC5W/MTCLKD/
MTIC5W#/
MTCLKD#/
MTIOC9B/TMRI2/
TMO4
RXD8/SMISO8/
SSCL8/RXD12/
SMISO12/SSCL12/
RXDX12/MISOA/
CRX0
ADTRG2#/
COMP2
A20
MTIOC9B/
MTIOC9B#
TXD1/SMOSI1/
SSDA1/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
ADST2/
COMP5
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 35 of 201
RX66T Group
1. Overview
Table 1.5
List of Pin and Pin Functions (144-pin with PGA pseudo-differential input and with USB pin) (6/7)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
144-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
99
PC3
MTIOC9D/
MTIOC9D#
RXD1/SMISO1/
SSCL1/RXD12/
SMISO12/SSCL12/
RXDX12
IRQ14
COMP4
100
P21
D14 [A14/
D14]
MTIOC9A/MTCLKA/ TXD8/SMOSI8/
IRQ6-DS
AN217
AN216
ADTRG1#/
COMP5
MTIOC9A#/
MTCLKA#/TMCI4
SSDA8/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
MOSIA
101
102
103
P20
P65
P64
D15 [A15/
D15]
MTIOC9C/MTCLKB/ CTS8#/RTS8#/
IRQ7-DS
IRQ9
ADTRG0#/
COMP4
MTIOC9C#/
MTCLKB#/TMRI4
SS8#/SCK8/
RSPCKA
A12
A13
AN211/
CMPC53/
DA1
IRQ8
AN210/
CMPC33/
DA0
104
105
106
107
AVCC2
AVCC2
AVSS2
P63
P62
P61
P60
P55
P54
P53
P52
P51
P50
PH7
A14/A12
A15/A13
A16/A14
A17/A15
A18/A16
A19/A17
A20/A18
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
AN209/
CMPC23
108
109
110
111
112
113
114
115
116
117
AN208/
CMPC43
AN207/
CMPC13
AN206/
CMPC03
AN203/
CMPC32
AN202/
CMPC22
AN201/
CMPC12
AN200/
CMPC02
AN205/
CMPC52
AN204/
CMPC42
AN106/
CVREFC1
118
119
120
121
PH6
PH5
P47
P46
AN105
AN104
AN103
AN102/
CMPC50/
CMPC51
122
123
P45
P44
AN101/
CMPC40/
CMPC41
AN100/
CMPC30/
CMPC31
124
125
126
PH4
PH3
PH2
AN107/
PGAVSS1
AN006/
CVREFC0
AN005
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 36 of 201
RX66T Group
1. Overview
Table 1.5
List of Pin and Pin Functions (144-pin with PGA pseudo-differential input and with USB pin) (7/7)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
144-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
PH1
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
AN004
AN003
Others
127
128
129
P43
P42
AN002/
CMPC20/
CMPC21
130
131
132
P41
P40
PH0
AN001/
CMPC10/
CMPC11
AN000/
CMPC00/
CMPC01
AN007/
PGAVSS0
133
134
135
136
137
AVCC1
AVCC0
AVSS0
AVSS1
P82
P81
ALE/WAIT# MTIC5U/MTIC5U#/
TMO4
SCK6/SCK12
IRQ3
COMP5
COMP4
138
139
140
CS2#
CS1#
RD#
MTIC5V/MTIC5V#/
TMCI4
TXD6/SMOSI6/
SSDA6/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
P80
P11
MTIC5W/MTIC5W#/ RXD6/SMISO6/
TMRI4
IRQ5
COMP3
SSCL6/RXD12/
SMISO12/SSCL12/
RXDX12
MTIOC3A/MTCLKC/
MTIOC3A#/
IRQ1-DS
MTCLKC#/
MTIOC9D/GTIOC3B/
GTETRGA/
GTIOC3B#/
GTETRGC/TMO3/
POE9#
141
P10
MTIOC9B/MTCLKD/ CTS6#/RTS6#/
IRQ0-DS
MTIOC9B#/
MTCLKD#/
SS6#
GTETRGB/
GTETRGD/TMRI3/
POE12#
142
143
144
P17
P16
P15
MTIOC4D/
MTIOC4D#/
GTIOC2B/GTIOC9B/
GTIOC2B#/
GTIOC9B#
IRQ14
IRQ13
IRQ12
MTIOC4C/
MTIOC4C#/
GTIOC1B/GTIOC8B/
GTIOC1B#/
GTIOC8B#
MTIOC3D/
MTIOC3D#/
GTIOC0B/GTIOC7B/
GTIOC0B#/
GTIOC7B#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 37 of 201
RX66T Group
1. Overview
Table 1.6
List of Pin and Pin Functions (112-pin with PGA pseudo-differential input and without USB pin)
(1/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
112-pin
LQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
1
2
3
4
P14
MTIOC4B/MTIOC4B#/
GTIOC2A/GTIOC9A/
GTIOC2A#/GTIOC9A#
IRQ11
P13
P12
PE5
MTIOC4A/MTIOC4A#/
GTIOC1A/GTIOC8A/
GTIOC1A#/GTIOC8A#
IRQ10
IRQ9
MTIOC3B/MTIOC3B#/
GTIOC0A/GTIOC7A/
GTIOC0A#/GTIOC7A#
BCLK
A11
MTIOC9D/MTIOC9D#/ SCK9/CTS9#/RTS9#/
GTIOC3A/GTETRGB/ SS9#
GTIOC3A#/GTETRGD
IRQ0
ADST0
5
6
7
EMLE
VSS
UB
P00
MTIOC9A/MTIOC9A#/ RXD9/SMISO9/SSCL9/ IRQ2
CACREF
ADST1/
COMP0
RXD12/SMISO12/
SSCL12/RXDX12
8
VCL
9
MD/FINED
10
P01
PE4
PE3
A10
A9
MTIOC9C/MTIOC9C#/ TXD9/SMOSI9/SSDA9/ IRQ4
GTETRGA/GTETRGB/ TXD12/SMOSI12/
GTETRGC/GTETRGD/ SSDA12/TXDX12/
ADST2/
COMP1
POE12#
SIOX12
11
12
MTCLKC/MTCLKC#/
GTETRGA/GTETRGB/
GTETRGC/GTETRGD/
POE10#
SCK9
IRQ1
A8
MTCLKD/MTCLKD#/
GTETRGA/GTETRGB/
GTETRGC/GTETRGD/
POE11#
CTS9#/RTS9#/SS9#
IRQ2-DS
13
14
15
16
17
18
19
RES#
XTAL
VSS
P37
P36
EXTAL
VCC
PE2
PE1
POE10#
NMI
WR0#/WR#
MTIOC9D/MTIOC9D#/ CTS5#/RTS5#/SS5#/
IRQ15
TMO5
CTS12#/RTS12#/
SS12#/SSLA3
20
21
PE0
PD7
WR1#/BC1#/
WAIT#
MTIOC9B/MTIOC9B#/ RXD5/SMISO5/SSCL5/ IRQ7
TMCI1/TMCI5 SSLA2/CRX0
TRST#
TMS
MTIOC9A/MTIOC9A#/ TXD5/SMOSI5/SSDA5/ IRQ8
GTIOC0A/GTIOC3A/
GTIOC0A#/GTIOC3A#/
TMRI1/TMRI5
SSLA1/CTX0
22
PD6
MTIOC9C/MTIOC9C#/ CTS1#/RTS1#/SS1#/
GTIOC0B/GTIOC3B/ CTS11#/RTS11#/
IRQ5
ADST0
GTIOC0B#/GTIOC3B#/ SS11#/SSLA0
TMO1
23
24
25
TDI
PD5
PD4
PD3
GTIOC1A/GTETRGA/ RXD1/SMISO1/SSCL1/ IRQ6
GTIOC1A#/TMRI0/
TMRI6
RXD11/SMISO11/
SSCL11
TCK
TDO
GTIOC1B/GTETRGB/ SCK1/SCK11
GTIOC1B#/TMCI0/
IRQ2
TMCI6
GTIOC2A/GTETRGC/ TXD1/SMOSI1/SSDA1/
GTIOC2A#/TMO0
TXD11/SMOSI11/
SSDA11
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 38 of 201
RX66T Group
1. Overview
Table 1.6
List of Pin and Pin Functions (112-pin with PGA pseudo-differential input and without USB pin)
(2/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
112-pin
LQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
26
27
28
TRCLK
PD2
A7
GTIOC2B/GTIOC0A/
GTIOC2B#/GTIOC0A#/
TMCI1/TMO4
SCK5/SCK8/MOSIA
TRDATA3
TRDATA2
PD1
PD0
A6
A5
GTIOC3A/GTIOC0B/
GTIOC3A#/GTIOC0B#/ MISOA
TMO2
RXD8/SMISO8/SSCL8/
GTIOC3B/GTIOC1A/
GTIOC3B#/GTIOC1A#/ RSPCKA
TMO6
TXD8/SMOSI8/SSDA8/
29
30
TRDATA1
TRDATA0
PB7
PB6
A4
A3
GTIOC1B/GTIOC1B#
GTIOC2A/GTIOC2A#
SCK5/SCK11/SCK12
RXD5/SMISO5/SSCL5/ IRQ2
RXD11/SMISO11/
SSCL11/RXD12/
SMISO12/SSCL12/
RXDX12/CRX0
31
TRSYNC
PB5
PB4
A2
A1
GTIOC2B/GTIOC2B#
TXD5/SMOSI5/SSDA5/
TXD11/SMOSI11/
SSDA11/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/CTX0
32
33
VCC
VSS
GTETRGA/GTETRGB/ CTS5#/RTS5#/SS5#/
GTETRGC/GTETRGD/ SCK11/CTS11#/
POE8#
IRQ3-DS
IRQ15
RTS11#/SS11#
34
35
PC2
PC1
CS1#
A16
MTIOC0D/MTIOC0D#/ SCK8
GTADSM0
ADSM0/
COMP5
36
MTIOC0C/MTIOC0C#/ TXD8/SMOSI8/SSDA8 IRQ13
GTADSM1
ADSM1/
COMP4
37
38
PC0
PB3
CS0#
MTIOC0B/MTIOC0B# RXD8/SMISO8/SSCL8 IRQ12
COMP3
MTIOC0A/MTIOC0A#/ SCK6/RSPCKA
CACREF
IRQ9
39
40
41
PB2
PB1
PB0
MTIOC0B/MTIOC0B#/ TXD6/SMOSI6/SSDA6/
ADSM0
GTADSM0/TMRI0
SDA
MTIOC0C/MTIOC0C#/ RXD6/SMISO6/SSCL6/ IRQ4
GTADSM1/TMCI0 SCL
ADSM1
A0/BC0#
MTIOC0D/MTIOC0D#/ TXD6/SMOSI6/SSDA6/ IRQ8
ADTRG2#
TMO0
CTS11#/RTS11#/
SS11#/MOSIA
42
PA5
MTIOC1A/MTIOC1A#/ RXD6/SMISO6/SSCL6/ IRQ1
ADTRG1#
ADTRG0#
TMCI3
RXD8/SMISO8/SSCL8/
MISOA
43
44
45
PA4
PA3
PA2
MTIOC1B/MTIOC1B#/ SCK6/TXD8/SMOSI8/
TMCI7 SSDA8/RSPCKA
MTIOC2A/MTIOC2A#/ TXD9/SMOSI9/SSDA9/
GTADSM0/TMRI7 SCK8/SSLA0
A0/BC0#
MTIOC2B/MTIOC2B#/ CTS6#/RTS6#/SS6#/
GTADSM1/TMO7
RXD9/SMISO9/SSCL9/
SSLA1
46
47
PA1
PA0
MTIOC6A/MTIOC6A#/ TXD9/SMOSI9/SSDA9/ IRQ14-DS
ADTRG0#
TMO4
RXD11/SMISO11/
SSCL11/SSLA2/CRX0
MTIOC6C/MTIOC6C#/ SCK9/TXD11/SMOSI11/
TMO2 SSDA11/SSLA3/CTX0
48
49
VCC
VSS
P96
CS0#/WAIT#
GTETRGA/GTETRGB/ CTS8#/RTS8#/SS8#
GTETRGC/GTETRGD/
POE4#
IRQ4-DS
50
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 39 of 201
RX66T Group
1. Overview
Table 1.6
List of Pin and Pin Functions (112-pin with PGA pseudo-differential input and without USB pin)
(3/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
112-pin
LQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P95
MTIOC6B/MTIOC6B#/
GTIOC4A/GTIOC7A/
GTIOC4A#/GTIOC7A#
P94
P93
P92
P91
P90
P76
P75
P74
P73
P72
P71
P70
PG2
MTIOC7A/MTIOC7A#/
GTIOC5A/GTIOC8A/
GTIOC5A#/GTIOC8A#
MTIOC7B/MTIOC7B#/
GTIOC6A/GTIOC9A/
GTIOC6A#/GTIOC9A#
MTIOC6D/MTIOC6D#/
GTIOC4B/GTIOC7B/
GTIOC4B#/GTIOC7B#
MTIOC7C/MTIOC7C#/
GTIOC5B/GTIOC8B/
GTIOC5B#/GTIOC8B#
MTIOC7D/MTIOC7D#/
GTIOC6B/GTIOC9B/
GTIOC6B#/GTIOC9B#
D0 [A0/D0]
D1 [A1/D1]
D2 [A2/D2]
D3 [A3/D3]
D4 [A4/D4]
D5 [A5/D5]
D6 [A6/D6]
MTIOC4D/MTIOC4D#/
GTIOC2B/GTIOC6B/
GTIOC2B#/GTIOC6B#
MTIOC4C/MTIOC4C#/
GTIOC1B/GTIOC5B/
GTIOC1B#/GTIOC5B#
MTIOC3D/MTIOC3D#/
GTIOC0B/GTIOC4B/
GTIOC0B#/GTIOC4B#
MTIOC4B/MTIOC4B#/
GTIOC2A/GTIOC6A/
GTIOC2A#/GTIOC6A#
MTIOC4A/MTIOC4A#/
GTIOC1A/GTIOC5A/
GTIOC1A#/GTIOC5A#
MTIOC3B/MTIOC3B#/
GTIOC0A/GTIOC4A/
GTIOC0A#/GTIOC4A#
GTETRGA/GTETRGB/ CTS9#/RTS9#/SS9#
GTETRGC/GTETRGD/
POE0#
IRQ5-DS
IRQ2
D11 [A11/D11] GTETRGA/GTIOC0B/ SCK9
GTIOC0B#
COMP0
65
66
67
PG1
PG0
P33
D12 [A12/D12] GTIOC0A/GTIOC0A#
D13 [A13/D13] GTIOC1B/GTIOC1B#
TXD9/SMOSI9/SSDA9 IRQ1
RXD9/SMISO9/SSCL9 IRQ0
COMP1
COMP2
D7 [A7/D7]
MTIOC3A/MTCLKA/
MTIOC3A#/MTCLKA#/
GTIOC3B/GTIOC3B#/
TMO0
SSLA3
IRQ13-DS
68
P32
P31
D8 [A8/D8]
MTIOC3C/MTCLKB/
MTIOC3C#/MTCLKB#/
GTIOC3A/GTIOC3A#/
TMO6
SSLA2
IRQ12-DS
69
70
VCC
VSS
D9 [A9/D9]
MTIOC0A/MTCLKC/
MTIOC0A#/MTCLKC#/
TMRI6
SSLA1
IRQ6
71
72
P30
P27
D10 [A10/D10] MTIOC0B/MTCLKD/
SCK8/CTS8#/RTS8#/
IRQ7
COMP3
MTIOC0B#/MTCLKD#/ SS8#/SSLA0
TMCI6
73
MTIOC1A/MTIOC0C/
MTIOC1A#/
IRQ15
MTIOC0C#/POE9#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 40 of 201
RX66T Group
1. Overview
Table 1.6
List of Pin and Pin Functions (112-pin with PGA pseudo-differential input and without USB pin)
(4/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
112-pin
LQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
74
P24
D11 [A11/D11] MTIC5U/MTIC5U#/
TMCI2/TMO6
CTS8#/RTS8#/SS8#/
SCK8/RSPCKA
IRQ4
COMP0
75
P23
P22
P21
D12 [A12/D12] MTIC5V/MTIC5V#/
TMO2/CACREF
TXD8/SMOSI8/SSDA8/ IRQ11
TXD12/SMOSI12/
SSDA12/TXDX12/
COMP1
SIOX12/MOSIA/CTX0
76
77
D13 [A13/D13] MTIC5W/
MTCLKD/MTIC5W#/
RXD8/SMISO8/SSCL8/ IRQ10
RXD12/SMISO12/
ADTRG2#/
COMP2
MTCLKD#/MTIOC9B/ SSCL12/RXDX12/
TMRI2/TMO4
MISOA/CRX0
D14 [A14/D14] MTIOC9A/MTCLKA/
TXD8/SMOSI8/SSDA8/ IRQ6-DS
AN217
AN216
ADTRG1#/
COMP5
MTIOC9A#/MTCLKA#/ TXD12/SMOSI12/
TMCI4
SSDA12/TXDX12/
SIOX12/MOSIA
78
79
80
P20
P65
P64
D15 [A15/D15] MTIOC9C/MTCLKB/
CTS8#/RTS8#/SS8#/
IRQ7-DS
IRQ9
ADTRG0#/
COMP4
MTIOC9C#/MTCLKB#/ SCK8/RSPCKA
TMRI4
A12
A13
AN211/
CMPC53/
DA1
IRQ8
AN210/
CMPC33/
DA0
81
82
83
AVCC2
AVSS2
P63
P62
P61
P60
P55
P54
P53
P52
A14
A15
A16
A17
A18
A19
A20
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
AN209/
CMPC23
84
85
86
87
88
89
90
AN208/
CMPC43
AN207/
CMPC13
AN206/
CMPC03
AN203/
CMPC32
AN202/
CMPC22
AN201/
CMPC12
AN200/
CMPC02
91
92
P47
P46
AN103
AN102/
CMPC50/
CMPC51
93
94
95
P45
P44
PH4
AN101/
CMPC40/
CMPC41
AN100/
CMPC30/
CMPC31
AN107/
PGAVSS1
96
97
P43
P42
AN003
AN002/
CMPC20/
CMPC21
98
P41
AN001/
CMPC10/
CMPC11
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 41 of 201
RX66T Group
1. Overview
Table 1.6
List of Pin and Pin Functions (112-pin with PGA pseudo-differential input and without USB pin)
(5/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
112-pin
LQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
99
P40
AN000/
CMPC00/
CMPC01
100
PH0
AN007/
PGAVSS0
101
102
103
104
105
AVCC1
AVCC0
AVSS0
AVSS1
P82
P81
ALE/WAIT#
CS2#
MTIC5U/MTIC5U#/
TMO4
SCK6/SCK12
IRQ3
COMP5
COMP4
106
MTIC5V/MTIC5V#/
TMCI4
TXD6/SMOSI6/SSDA6/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
107
108
P80
P11
CS1#
RD#
MTIC5W/MTIC5W#/
TMRI4
RXD6/SMISO6/SSCL6/ IRQ5
RXD12/SMISO12/
SSCL12/RXDX12
COMP3
MTIOC3A/MTCLKC/
MTIOC3A#/MTCLKC#/
MTIOC9D/GTIOC3B/
GTETRGA/GTIOC3B#/
GTETRGC/TMO3/
POE9#
IRQ1-DS
109
P10
MTIOC9B/MTCLKD/
MTIOC9B#/MTCLKD#/
GTETRGB/GTETRGD/
TMRI3/POE12#
CTS6#/RTS6#/SS6#
IRQ0-DS
110
111
112
P17
P16
P15
MTIOC4D/MTIOC4D#/
GTIOC2B/GTIOC9B/
GTIOC2B#/GTIOC9B#
IRQ14
IRQ13
IRQ12
MTIOC4C/MTIOC4C#/
GTIOC1B/GTIOC8B/
GTIOC1B#/GTIOC8B#
MTIOC3D/MTIOC3D#/
GTIOC0B/GTIOC7B/
GTIOC0B#/GTIOC7B#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 42 of 201
RX66T Group
1. Overview
Table 1.7
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and with USB pin) (1/5)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
100-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
1
PE5
BCLK
MTIOC9D/
MTIOC9D#/
GTIOC3A/
GTETRGB/
GTIOC3A#/
GTETRGD
SCK9/CTS9#/
RTS9#/SS9#
IRQ0
ADST0
2
3
4
EMLE
VSS
UB
P00
P01
A11
A10
MTIOC9A/
MTIOC9A#/CACREF SSCL9/RXD12/
SMISO12/SSCL12/
RXD9/SMISO9/
IRQ2
IRQ4
ADST1/
COMP0
RXDX12
5
6
7
VCL
MD/FINED
MTIOC9C/
MTIOC9C#/
GTETRGA/
TXD9/SMOSI9/
SSDA9/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
ADST2/
COMP1
GTETRGB/
GTETRGC/
GTETRGD/POE12#
8
9
PE4
PE3
A9
A8
MTCLKC/MTCLKC#/ SCK9
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/POE10#
IRQ1
MTCLKD/MTCLKD#/ CTS9#/RTS9#/
IRQ2-DS
GTETRGA/
SS9#
GTETRGB/
GTETRGC/
GTETRGD/POE11#
10
11
12
13
14
15
16
RES#
XTAL
VSS
P37
P36
EXTAL
VCC
UPSEL
PE2
PE1
POE10#
NMI
WR0#/WR# MTIOC9D/
MTIOC9D#/TMO5
CTS5#/RTS5#/
SS5#/CTS12#/
RTS12#/SS12#/
SSLA3
IRQ15
17
18
PE0
PD7
WR1#/
BC1#/
WAIT#
MTIOC9B/
MTIOC9B#/TMCI1/
TMCI5
RXD5/SMISO5/
SSCL5/SSLA2/
CRX0
USB0_OVR IRQ7
CURB
TRST#
TMS
MTIOC9A/
MTIOC9A#/
GTIOC0A/GTIOC3A/ CTX0
GTIOC0A#/
GTIOC3A#/TMRI1/
TMRI5
TXD5/SMOSI5/
SSDA5/SSLA1/
IRQ8
19
PD6
MTIOC9C/
MTIOC9C#/
CTS1#/RTS1#/
SS1#/CTS11#/
IRQ5
ADST0
GTIOC0B/GTIOC3B/ RTS11#/SS11#/
GTIOC0B#/
SSLA0
GTIOC3B#/TMO1
20
21
TDI
PD5
PD4
GTIOC1A/
RXD1/SMISO1/
SSCL1/RXD11/
SMISO11/SSCL11
IRQ6
IRQ2
GTETRGA/
GTIOC1A#/TMRI0/
TMRI6
TCK
GTIOC1B/
SCK1/SCK11
GTETRGB/
GTIOC1B#/TMCI0/
TMCI6
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 43 of 201
RX66T Group
1. Overview
Table 1.7
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and with USB pin) (2/5)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
100-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
22
TDO
PD3
GTIOC2A/
GTETRGC/
GTIOC2A#/TMO0
TXD1/SMOSI1/
SSDA1/TXD11/
SMOSI11/SSDA11
23
TRCLK
PD2
A7
GTIOC2B/GTIOC0A/ SCK5/SCK8/
USB0_VBUS
GTIOC2B#/
GTIOC0A#/TMCI1/
TMO4
MOSIA
24
25
26
27
USB0_DM
USB0_DP
VCC_USB
TRDATA0
PB6
PB5
A3
A2
GTIOC2A/
GTIOC2A#
RXD5/SMISO5/
SSCL5/RXD11/
SMISO11/SSCL11/
RXD12/SMISO12/
SSCL12/RXDX12/
CRX0
USB0_OVR IRQ2
CURA
28
TRSYNC
GTIOC2B/
GTIOC2B#
TXD5/SMOSI5/
SSDA5/TXD11/
SMOSI11/SSDA11/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/CTX0
USB0_VBUS
EN
29
30
VCC
PB4
A1
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/POE8#
CTS5#/RTS5#/
SS5#/SCK11/
CTS11#/RTS11#/
SS11#
USB0_OVR IRQ3-DS
CURB
31
32
VSS/VSS_USB
PB3
PB2
A7
A6
MTIOC0A/
MTIOC0A#/CACREF
SCK6/RSPCKA
IRQ9
33
34
35
MTIOC0B/
MTIOC0B#/
GTADSM0/TMRI0
TXD6/SMOSI6/
SSDA6/SDA
ADSM0
PB1
PB0
A5
MTIOC0C/
MTIOC0C#/
GTADSM1/TMCI0
RXD6/SMISO6/
SSCL6/SCL
IRQ4
IRQ8
ADSM1
A0/BC0#/A4 MTIOC0D/
MTIOC0D#/TMO0
TXD6/SMOSI6/
SSDA6/CTS11#/
RTS11#/SS11#/
MOSIA
ADTRG2#
36
PA5
A3
MTIOC1A/
MTIOC1A#/TMCI3
RXD6/SMISO6/
SSCL6/RXD8/
SMISO8/SSCL8/
MISOA
IRQ1
ADTRG1#
ADTRG0#
37
38
39
PA4
PA3
PA2
A2
MTIOC1B/
MTIOC1B#/TMCI7
SCK6/TXD8/
SMOSI8/SSDA8/
RSPCKA
A1
MTIOC2A/
MTIOC2A#/
GTADSM0/TMRI7
TXD9/SMOSI9/
SSDA9/SCK8/
SSLA0
A0/BC0#
MTIOC2B/
MTIOC2B#/
CTS6#/RTS6#/
SS6#/RXD9/
GTADSM1/TMO7
SMISO9/SSCL9/
SCK11/SSLA1
40
41
42
PA1
PA0
MTIOC6A/
MTIOC6A#/TMO4
TXD9/SMOSI9/
SSDA9/RXD11/
SMISO11/SSCL11/ CURA
SSLA2/CRX0
USB0_ID/
USB0_OVR
IRQ14-DS
ADTRG0#
MTIOC6C/
MTIOC6C#/TMO2
SCK9/TXD11/
SMOSI11/SSDA11/ EN/
SSLA3/CTX0
USB0_EXIC
USB0_VBUS
EN
VCC
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 44 of 201
RX66T Group
1. Overview
Table 1.7
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and with USB pin) (3/5)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
100-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
43
P96
CS0#/
WAIT#
GTETRGA/
GTETRGB/
CTS8#/RTS8#/
SS8#
IRQ4-DS
GTETRGC/
GTETRGD/POE4#
44
45
VSS
P95
P94
P93
P92
P91
P90
P76
P75
P74
P73
P72
P71
P70
MTIOC6B/
MTIOC6B#/
GTIOC4A/GTIOC7A/
GTIOC4A#/
GTIOC7A#
46
47
48
49
50
51
52
53
54
55
56
57
MTIOC7A/
MTIOC7A#/
GTIOC5A/GTIOC8A/
GTIOC5A#/
GTIOC8A#
MTIOC7B/
MTIOC7B#/
GTIOC6A/GTIOC9A/
GTIOC6A#/
GTIOC9A#
MTIOC6D/
MTIOC6D#/
GTIOC4B/GTIOC7B/
GTIOC4B#/
GTIOC7B#
MTIOC7C/
MTIOC7C#/
GTIOC5B/GTIOC8B/
GTIOC5B#/
GTIOC8B#
MTIOC7D/
MTIOC7D#/
GTIOC6B/GTIOC9B/
GTIOC6B#/
GTIOC9B#
D0 [A0/D0] MTIOC4D/
MTIOC4D#/
GTIOC2B/GTIOC6B/
GTIOC2B#/
GTIOC6B#
D1 [A1/D1] MTIOC4C/
MTIOC4C#/
GTIOC1B/GTIOC5B/
GTIOC1B#/
GTIOC5B#
D2 [A2/D2] MTIOC3D/
MTIOC3D#/
GTIOC0B/GTIOC4B/
GTIOC0B#/
GTIOC4B#
D3 [A3/D3] MTIOC4B/
MTIOC4B#/
GTIOC2A/GTIOC6A/
GTIOC2A#/
GTIOC6A#
D4 [A4/D4] MTIOC4A/
MTIOC4A#/
GTIOC1A/GTIOC5A/
GTIOC1A#/
GTIOC5A#
D5 [A5/D5] MTIOC3B/
MTIOC3B#/
GTIOC0A/GTIOC4A/
GTIOC0A#/
GTIOC4A#
D6 [A6/D6] GTETRGA/
GTETRGB/
CTS9#/RTS9#/
SS9#
IRQ5-DS
GTETRGC/
GTETRGD/POE0#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 45 of 201
RX66T Group
1. Overview
Table 1.7
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and with USB pin) (4/5)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
100-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
POE, POEG, CAC) CAN)
I/O Port
Bus
(USB)
(IRQ, NMI)
Analog
Others
58
59
P33
D7 [A7/D7] MTIOC3A/MTCLKA/ SSLA3
MTIOC3A#/
IRQ13-DS
MTCLKA#/GTIOC3B/
GTIOC3B#/TMO0
P32
P31
D8 [A8/D8] MTIOC3C/MTCLKB/ SSLA2
MTIOC3C#/
IRQ12-DS
MTCLKB#/GTIOC3A/
GTIOC3A#/TMO6
60
61
VCC
VSS
D9 [A9/D9] MTIOC0A/MTCLKC/ SSLA1
MTIOC0A#/
IRQ6
MTCLKC#/TMRI6
62
63
P30
P27
P24
P23
D10 [A10/
D10]
MTIOC0B/MTCLKD/ SCK8/CTS8#/
IRQ7
COMP3
MTIOC0B#/
RTS8#/SS8#/
SSLA0
MTCLKD#/TMCI6
64
65
66
CS3#
MTIOC1A/MTIOC0C/
MTIOC1A#/
IRQ15
IRQ4
MTIOC0C#/POE9#
D11 [A11/
D11]
MTIC5U/MTIC5U#/
TMCI2/TMO6
CTS8#/RTS8#/
SS8#/SCK8/
RSPCKA
COMP0
COMP1
D12 [A12/
D12]
MTIC5V/MTIC5V#/
TMO2/CACREF
TXD8/SMOSI8/
SSDA8/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
MOSIA/CTX0
IRQ11
67
68
P22
P21
D13 [A13/
D13]
MTIC5W/MTCLKD/
MTIC5W#/
MTCLKD#/
MTIOC9B/TMRI2/
TMO4
RXD8/SMISO8/
SSCL8/RXD12/
SMISO12/SSCL12/
RXDX12/MISOA/
CRX0
IRQ10
ADTRG2#/
COMP2
D14 [A14/
D14]
MTIOC9A/MTCLKA/ TXD8/SMOSI8/
MTIOC9A#/
MTCLKA#/TMCI4
IRQ6-DS
AN217
AN216
ADTRG1#/
COMP5
SSDA8/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
MOSIA
69
70
71
P20
P65
P64
D15 [A15/
D15]
MTIOC9C/MTCLKB/ CTS8#/RTS8#/
MTIOC9C#/
MTCLKB#/TMRI4
IRQ7-DS
IRQ9
ADTRG0#/
COMP4
SS8#/SCK8/
RSPCKA
A12
A13
AN211/
CMPC53/
DA1
IRQ8
AN210/
CMPC33/
DA0
72
73
74
AVCC2
AVSS2
P63
P62
P61
P60
P55
P54
P53
A14/A12
A15/A13
A16/A14
A17/A15
A18/A16
A19/A17
A20/A18
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
AN209/
CMPC23
75
76
77
78
79
80
AN208/
CMPC43
AN207/
CMPC13
AN206/
CMPC03
AN203/
CMPC32
AN202/
CMPC22
AN201/
CMPC12
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 46 of 201
RX66T Group
1. Overview
Table 1.7
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and with USB pin) (5/5)
Pin
Communica
Number
Timer
Communications tions
Interrupt
Power Supply
100-Pin
LFQFP
Clock System
Control
(MTU, GPTW, TMR, (SCI, RSPI, RIIC,
I/O Port
Bus
POE, POEG, CAC)
CAN)
(USB)
(IRQ, NMI)
Analog
Others
81
P52
IRQ0
AN200/
CMPC02
82
83
P47
P46
AN103
AN102/
CMPC50/
CMPC51
84
85
86
P45
P44
PH4
AN101/
CMPC40/
CMPC41
AN100/
CMPC30/
CMPC31
AN107/
PGAVSS1
87
88
P43
P42
AN003
AN002/
CMPC20/
CMPC21
89
90
91
P41
P40
PH0
AN001/
CMPC10/
CMPC11
AN000/
CMPC00/
CMPC01
AN007/
PGAVSS0
92
93
94
95
96
AVCC1
AVCC0
AVSS0
AVSS1
P82
P81
ALE/WAIT# MTIC5U/MTIC5U#/
TMO4
SCK6/SCK12
IRQ3
COMP5
COMP4
97
98
99
CS2#
CS1#
RD#
MTIC5V/MTIC5V#/
TMCI4
TXD6/SMOSI6/
SSDA6/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
P80
P11
MTIC5W/MTIC5W#/ RXD6/SMISO6/
TMRI4
IRQ5
COMP3
SSCL6/RXD12/
SMISO12/SSCL12/
RXDX12
MTIOC3A/MTCLKC/
MTIOC3A#/
IRQ1-DS
MTCLKC#/
MTIOC9D/GTIOC3B/
GTETRGA/
GTIOC3B#/
GTETRGC/TMO3/
POE9#
100
P10
MTIOC9B/MTCLKD/ CTS6#/RTS6#/
IRQ0-DS
MTIOC9B#/
MTCLKD#/
SS6#
GTETRGB/
GTETRGD/TMRI3/
POE12#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 47 of 201
RX66T Group
1. Overview
Table 1.8
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and without USB pin)
(1/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
1
PE5
BCLK
MTIOC9D/MTIOC9D#/ SCK9/CTS9#/RTS9#/
GTIOC3A/GTETRGB/ SS9#
GTIOC3A#/GTETRGD
IRQ0
ADST0
2
3
4
EMLE
VSS
UB
P00
A11
MTIOC9A/MTIOC9A#/ RXD9/SMISO9/SSCL9/ IRQ2
ADST1/
COMP0
CACREF
RXD12/SMISO12/
SSCL12/RXDX12
5
6
7
VCL
MD/FINED
P01
PE4
PE3
A10
A9
MTIOC9C/MTIOC9C#/ TXD9/SMOSI9/SSDA9/ IRQ4
GTETRGA/GTETRGB/ TXD12/SMOSI12/
GTETRGC/GTETRGD/ SSDA12/TXDX12/
ADST2/
COMP1
POE12#
SIOX12
8
9
MTCLKC/MTCLKC#/
GTETRGA/GTETRGB/
GTETRGC/GTETRGD/
POE10#
SCK9
IRQ1
A8
MTCLKD/MTCLKD#/
GTETRGA/GTETRGB/
GTETRGC/GTETRGD/
POE11#
CTS9#/RTS9#/SS9#
IRQ2-DS
10
11
12
13
14
15
16
RES#
XTAL
VSS
P37
P36
EXTAL
VCC
PE2
PE1
POE10#
NMI
WR0#/WR#
MTIOC9D/MTIOC9D#/ CTS5#/RTS5#/SS5#/
IRQ15
TMO5
CTS12#/RTS12#/
SS12#/SSLA3
17
18
PE0
PD7
WR1#/BC1#/
WAIT#
MTIOC9B/MTIOC9B#/ RXD5/SMISO5/SSCL5/ IRQ7
TMCI1/TMCI5 SSLA2/CRX0
TRST#
TMS
MTIOC9A/MTIOC9A#/ TXD5/SMOSI5/SSDA5/ IRQ8
GTIOC0A/GTIOC3A/
GTIOC0A#/GTIOC3A#/
TMRI1/TMRI5
SSLA1/CTX0
19
PD6
MTIOC9C/MTIOC9C#/ CTS1#/RTS1#/SS1#/
GTIOC0B/GTIOC3B/ CTS11#/RTS11#/
IRQ5
ADST0
GTIOC0B#/GTIOC3B#/ SS11#/SSLA0
TMO1
20
21
22
23
24
25
26
TDI
PD5
PD4
PD3
PD2
PD1
PD0
PB7
GTIOC1A/GTETRGA/ RXD1/SMISO1/SSCL1/ IRQ6
GTIOC1A#/TMRI0/
TMRI6
RXD11/SMISO11/
SSCL11
TCK
GTIOC1B/GTETRGB/ SCK1/SCK11
GTIOC1B#/TMCI0/
IRQ2
TMCI6
TDO
GTIOC2A/GTETRGC/ TXD1/SMOSI1/SSDA1/
GTIOC2A#/TMO0
TXD11/SMOSI11/
SSDA11
TRCLK
TRDATA3
TRDATA2
TRDATA1
A7
A6
A5
A4
GTIOC2B/GTIOC0A/
GTIOC2B#/GTIOC0A#/
TMCI1/TMO4
SCK5/SCK8/MOSIA
GTIOC3A/GTIOC0B/
RXD8/SMISO8/SSCL8/
GTIOC3A#/GTIOC0B#/ MISOA
TMO2
GTIOC3B/GTIOC1A/
GTIOC3B#/GTIOC1A#/ RSPCKA
TMO6
TXD8/SMOSI8/SSDA8/
GTIOC1B/GTIOC1B#
SCK5/SCK11/SCK12
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 48 of 201
RX66T Group
1. Overview
Table 1.8
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and without USB pin)
(2/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
27
28
TRDATA0
PB6
A3
GTIOC2A/GTIOC2A#
RXD5/SMISO5/SSCL5/ IRQ2
RXD11/SMISO11/
SSCL11/RXD12/
SMISO12/SSCL12/
RXDX12/CRX0
TRSYNC
PB5
PB4
A2
A1
GTIOC2B/GTIOC2B#
TXD5/SMOSI5/SSDA5/
TXD11/SMOSI11/
SSDA11/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/CTX0
29
30
VCC
VSS
GTETRGA/GTETRGB/ CTS5#/RTS5#/SS5#/
GTETRGC/GTETRGD/ SCK11/CTS11#/
POE8#
IRQ3-DS
IRQ9
RTS11#/SS11#
31
32
1
PB3
PB2
PB1
PB0
A7*
A6*
A5*
MTIOC0A/MTIOC0A#/ SCK6/RSPCKA
CACREF
1
1
33
34
35
MTIOC0B/MTIOC0B#/ TXD6/SMOSI6/SSDA6/
GTADSM0/TMRI0
ADSM0
SDA
MTIOC0C/MTIOC0C#/ RXD6/SMISO6/SSCL6/ IRQ4
GTADSM1/TMCI0 SCL
ADSM1
1
A0/A4* /BC0# MTIOC0D/MTIOC0D#/ TXD6/SMOSI6/SSDA6/ IRQ8
ADTRG2#
TMO0
CTS11#/RTS11#/
SS11#/MOSIA
1
36
PA5
A3*
MTIOC1A/MTIOC1A#/ RXD6/SMISO6/SSCL6/ IRQ1
ADTRG1#
ADTRG0#
TMCI3
RXD8/SMISO8/SSCL8/
MISOA
1
1
37
38
39
PA4
PA3
PA2
A2*
A1*
MTIOC1B/MTIOC1B#/ SCK6/TXD8/SMOSI8/
TMCI7 SSDA8/RSPCKA
MTIOC2A/MTIOC2A#/ TXD9/SMOSI9/SSDA9/
GTADSM0/TMRI7 SCK8/SSLA0
A0/BC0#
MTIOC2B/MTIOC2B#/ CTS6#/RTS6#/SS6#/
GTADSM1/TMO7
RXD9/SMISO9/SSCL9/
SCK11* /SSLA1
1
40
41
PA1
PA0
MTIOC6A/MTIOC6A#/ TXD9/SMOSI9/SSDA9/ IRQ14-DS
ADTRG0#
TMO4
RXD11/SMISO11/
SSCL11/SSLA2/CRX0
MTIOC6C/MTIOC6C#/ SCK9/TXD11/SMOSI11/
TMO2 SSDA11/SSLA3/CTX0
42
43
VCC
VSS
P96
CS0#/WAIT#
GTETRGA/GTETRGB/ CTS8#/RTS8#/SS8#
GTETRGC/GTETRGD/
POE4#
IRQ4-DS
44
45
P95
P94
P93
P92
P91
P90
MTIOC6B/MTIOC6B#/
GTIOC4A/GTIOC7A/
GTIOC4A#/GTIOC7A#
46
47
48
49
50
MTIOC7A/MTIOC7A#/
GTIOC5A/GTIOC8A/
GTIOC5A#/GTIOC8A#
MTIOC7B/MTIOC7B#/
GTIOC6A/GTIOC9A/
GTIOC6A#/GTIOC9A#
MTIOC6D/MTIOC6D#/
GTIOC4B/GTIOC7B/
GTIOC4B#/GTIOC7B#
MTIOC7C/MTIOC7C#/
GTIOC5B/GTIOC8B/
GTIOC5B#/GTIOC8B#
MTIOC7D/MTIOC7D#/
GTIOC6B/GTIOC9B/
GTIOC6B#/GTIOC9B#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 49 of 201
RX66T Group
1. Overview
Table 1.8
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and without USB pin)
(3/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
51
52
53
54
55
56
57
58
P76
D0 [A0/D0]
MTIOC4D/MTIOC4D#/
GTIOC2B/GTIOC6B/
GTIOC2B#/GTIOC6B#
P75
P74
P73
P72
P71
P70
P33
D1 [A1/D1]
D2 [A2/D2]
D3 [A3/D3]
D4 [A4/D4]
D5 [A5/D5]
D6 [A6/D6]
D7 [A7/D7]
MTIOC4C/MTIOC4C#/
GTIOC1B/GTIOC5B/
GTIOC1B#/GTIOC5B#
MTIOC3D/MTIOC3D#/
GTIOC0B/GTIOC4B/
GTIOC0B#/GTIOC4B#
MTIOC4B/MTIOC4B#/
GTIOC2A/GTIOC6A/
GTIOC2A#/GTIOC6A#
MTIOC4A/MTIOC4A#/
GTIOC1A/GTIOC5A/
GTIOC1A#/GTIOC5A#
MTIOC3B/MTIOC3B#/
GTIOC0A/GTIOC4A/
GTIOC0A#/GTIOC4A#
GTETRGA/GTETRGB/ CTS9#/RTS9#/SS9#
GTETRGC/GTETRGD/
POE0#
IRQ5-DS
MTIOC3A/MTCLKA/
MTIOC3A#/MTCLKA#/
GTIOC3B/GTIOC3B#/
TMO0
SSLA3
IRQ13-DS
59
P32
P31
D8 [A8/D8]
D9 [A9/D9]
MTIOC3C/MTCLKB/
MTIOC3C#/MTCLKB#/
GTIOC3A/GTIOC3A#/
TMO6
SSLA2
IRQ12-DS
60
61
VCC
VSS
MTIOC0A/MTCLKC/
MTIOC0A#/MTCLKC#/
TMRI6
SSLA1
IRQ6
62
63
P30
P27
D10 [A10/D10] MTIOC0B/MTCLKD/
SCK8/CTS8#/RTS8#/
IRQ7
IRQ15
IRQ4
COMP3
MTIOC0B#/MTCLKD#/ SS8#/SSLA0
TMCI6
1
64
CS3*
MTIOC1A/MTIOC0C/
MTIOC1A#/
MTIOC0C#/POE9#
65
66
P24
P23
D11 [A11/D11] MTIC5U/MTIC5U#/
TMCI2/TMO6
CTS8#/RTS8#/SS8#/
SCK8/RSPCKA
COMP0
COMP1
D12 [A12/D12] MTIC5V/MTIC5V#/
TMO2/CACREF
TXD8/SMOSI8/SSDA8/ IRQ11
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/MOSIA/CTX0
67
68
P22
P21
D13 [A13/D13] MTIC5W/MTCLKD/
RXD8/SMISO8/SSCL8/ IRQ10
ADTRG2#/
COMP2
MTIC5W#/MTCLKD#/ RXD12/SMISO12/
MTIOC9B/TMRI2/
TMO4
SSCL12/RXDX12/
MISOA/CRX0
D14 [A14/D14] MTIOC9A/MTCLKA/
TMCI4
TXD8/SMOSI8/SSDA8/ IRQ6-DS
AN217
AN216
ADTRG1#/
COMP5
MTIOC9A#/MTCLKA#/ TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/MOSIA
69
70
71
P20
P65
P64
D15 [A15/D15] MTIOC9C/MTCLKB/
CTS8#/RTS8#/SS8#/
IRQ7-DS
IRQ9
ADTRG0#/
COMP4
MTIOC9C#/MTCLKB#/ SCK8/RSPCKA
TMRI4
A12
A13
AN211/
CMPC53/
DA1
IRQ8
AN210/
CMPC33/
DA0
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 50 of 201
RX66T Group
1. Overview
Table 1.8
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and without USB pin)
(4/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
72
73
74
AVCC2
AVSS2
1
P63
P62
P61
P60
P55
P54
P53
P52
A12* /A14
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
AN209/
CMPC23
1
75
76
77
78
79
80
81
A13* /A15
AN208/
CMPC43
1
A14* /A16
AN207/
CMPC13
1
A15* /A17
AN206/
CMPC03
1
A16* /A18
AN203/
CMPC32
1
A17* /A19
AN202/
CMPC22
1
A18* /A20
AN201/
CMPC12
AN200/
CMPC02
82
83
P47
P46
AN103
AN102/
CMPC50/
CMPC51
84
85
86
P45
P44
PH4
AN101/
CMPC40/
CMPC41
AN100/
CMPC30/
CMPC31
AN107/
PGAVSS1
87
88
P43
P42
AN003
AN002/
CMPC20/
CMPC21
89
90
91
P41
P40
PH0
AN001/
CMPC10/
CMPC11
AN000/
CMPC00/
CMPC01
AN007/
PGAVSS0
92
93
94
95
96
AVCC1
AVCC0
AVSS0
AVSS1
P82
P81
ALE/WAIT#
CS2#
MTIC5U/MTIC5U#/
TMO4
SCK6/SCK12
IRQ3
COMP5
COMP4
97
MTIC5V/MTIC5V#/
TMCI4
TXD6/SMOSI6/SSDA6/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
98
P80
CS1#
MTIC5W/MTIC5W#/
TMRI4
RXD6/SMISO6/SSCL6/ IRQ5
RXD12/SMISO12/
COMP3
SSCL12/RXDX12
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 51 of 201
RX66T Group
1. Overview
Table 1.8
List of Pin and Pin Functions (100-pin with PGA pseudo-differential input and without USB pin)
(5/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
99
P11
RD#
MTIOC3A/MTCLKC/
MTIOC3A#/MTCLKC#/
MTIOC9D/GTIOC3B/
GTETRGA/GTIOC3B#/
GTETRGC/TMO3/
POE9#
IRQ1-DS
100
P10
MTIOC9B/MTCLKD/
MTIOC9B#/MTCLKD#/
GTETRGB/GTETRGD/
TMRI3/POE12#
CTS6#/RTS6#/SS6#
IRQ0-DS
Note 1. These pins are only enabled for products with 128 Kbytes of RAM.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 52 of 201
RX66T Group
1. Overview
Table 1.9
List of Pin and Pin Functions (100-pin without PGA pseudo-differential input and without USB pin)
(1/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
1
PE5
BCLK
MTIOC9D/MTIOC9D#/ SCK9/CTS9#/RTS9#/
GTIOC3A/GTETRGB/ SS9#
GTIOC3A#/GTETRGD
IRQ0
ADST0
2
3
4
EMLE
VSS
UB
P00
A11
MTIOC9A/MTIOC9A#/ RXD9/SMISO9/SSCL9/ IRQ2
ADST1/
COMP0
CACREF
RXD12/SMISO12/
SSCL12/RXDX12
5
6
7
VCL
MD/FINED
P01
PE4
PE3
A10
A9
MTIOC9C/MTIOC9C#/ TXD9/SMOSI9/SSDA9/ IRQ4
GTETRGA/GTETRGB/ TXD12/SMOSI12/
GTETRGC/GTETRGD/ SSDA12/TXDX12/
ADST2/
COMP1
POE12#
SIOX12
8
9
MTCLKC/MTCLKC#/
GTETRGA/GTETRGB/
GTETRGC/GTETRGD/
POE10#
SCK9
IRQ1
A8
MTCLKD/MTCLKD#/
GTETRGA/GTETRGB/
GTETRGC/GTETRGD/
POE11#
CTS9#/RTS9#/SS9#
IRQ2-DS
10
11
12
13
14
15
16
RES#
XTAL
VSS
P37
P36
EXTAL
VCC
PE2
PE1
POE10#
NMI
WR0#/WR#
MTIOC9D/MTIOC9D#/ CTS5#/RTS5#/SS5#/
IRQ15
TMO5
CTS12#/RTS12#/
SS12#/SSLA3
17
18
PE0
PD7
WR1#/BC1#/
WAIT#
MTIOC9B/MTIOC9B#/ RXD5/SMISO5/SSCL5/ IRQ7
TMCI1/TMCI5 SSLA2/CRX0
TRST#
TMS
MTIOC9A/MTIOC9A#/ TXD5/SMOSI5/SSDA5/ IRQ8
GTIOC0A/GTIOC3A/
GTIOC0A#/GTIOC3A#/
TMRI1/TMRI5
SSLA1/CTX0
19
PD6
MTIOC9C/MTIOC9C#/ CTS1#/RTS1#/SS1#/
GTIOC0B/GTIOC3B/ CTS11#/RTS11#/
IRQ5
ADST0
GTIOC0B#/GTIOC3B#/ SS11#/SSLA0
TMO1
20
21
22
23
24
25
26
TDI
PD5
PD4
PD3
PD2
PD1
PD0
PB7
GTIOC1A/GTETRGA/ RXD1/SMISO1/SSCL1/ IRQ6
GTIOC1A#/TMRI0/
TMRI6
RXD11/SMISO11/
SSCL11
TCK
GTIOC1B/GTETRGB/ SCK1/SCK11
GTIOC1B#/TMCI0/
IRQ2
TMCI6
TDO
GTIOC2A/GTETRGC/ TXD1/SMOSI1/SSDA1/
GTIOC2A#/TMO0
TXD11/SMOSI11/
SSDA11
TRCLK
TRDATA3
TRDATA2
TRDATA1
A7
A6
A5
A4
GTIOC2B/GTIOC0A/
GTIOC2B#/GTIOC0A#/
TMCI1/TMO4
SCK5/SCK8/MOSIA
GTIOC3A/GTIOC0B/
RXD8/SMISO8/SSCL8/
GTIOC3A#/GTIOC0B#/ MISOA
TMO2
GTIOC3B/GTIOC1A/
GTIOC3B#/GTIOC1A#/ RSPCKA
TMO6
TXD8/SMOSI8/SSDA8/
GTIOC1B/GTIOC1B#
SCK5/SCK11/SCK12
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 53 of 201
RX66T Group
1. Overview
Table 1.9
List of Pin and Pin Functions (100-pin without PGA pseudo-differential input and without USB pin)
(2/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
27
28
TRDATA0
PB6
A3
GTIOC2A/GTIOC2A#
RXD5/SMISO5/SSCL5/ IRQ2
RXD11/SMISO11/
SSCL11/RXD12/
SMISO12/SSCL12/
RXDX12/CRX0
TRSYNC
PB5
PB4
A2
A1
GTIOC2B/GTIOC2B#
TXD5/SMOSI5/SSDA5/
TXD11/SMOSI11/
SSDA11/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/CTX0
29
30
VCC
VSS
GTETRGA/GTETRGB/ CTS5#/RTS5#/SS5#/
GTETRGC/GTETRGD/ SCK11/CTS11#/
POE8#
IRQ3-DS
IRQ9
RTS11#/SS11#
31
32
1
PB3
PB2
PB1
PB0
A7*
A6*
A5*
MTIOC0A/MTIOC0A#/ SCK6/RSPCKA
CACREF
1
1
33
34
35
MTIOC0B/MTIOC0B#/ TXD6/SMOSI6/SSDA6/
GTADSM0/TMRI0
ADSM0
SDA
MTIOC0C/MTIOC0C#/ RXD6/SMISO6/SSCL6/ IRQ4
GTADSM1/TMCI0 SCL
ADSM1
1
A0/A4* /BC0# MTIOC0D/MTIOC0D#/ TXD6/SMOSI6/SSDA6/ IRQ8
ADTRG2#
TMO0
CTS11#/RTS11#/
SS11#/MOSIA
1
36
PA5
A3*
MTIOC1A/MTIOC1A#/ RXD6/SMISO6/SSCL6/ IRQ1
ADTRG1#
ADTRG0#
TMCI3
RXD8/SMISO8/SSCL8/
MISOA
1
1
37
38
39
PA4
PA3
PA2
A2*
A1*
MTIOC1B/MTIOC1B#/ SCK6/TXD8/SMOSI8/
TMCI7 SSDA8/RSPCKA
MTIOC2A/MTIOC2A#/ TXD9/SMOSI9/SSDA9/
GTADSM0/TMRI7 SCK8/SSLA0
A0/BC0#
MTIOC2B/MTIOC2B#/ CTS6#/RTS6#/SS6#/
GTADSM1/TMO7
RXD9/SMISO9/SSCL9/
SCK11* /SSLA1
1
40
41
PA1
PA0
MTIOC6A/MTIOC6A#/ TXD9/SMOSI9/SSDA9/ IRQ14-DS
ADTRG0#
TMO4
RXD11/SMISO11/
SSCL11/SSLA2/CRX0
MTIOC6C/MTIOC6C#/ SCK9/TXD11/SMOSI11/
TMO2 SSDA11/SSLA3/CTX0
42
43
VCC
VSS
P96
CS0#/WAIT#
GTETRGA/GTETRGB/ CTS8#/RTS8#/SS8#
GTETRGC/GTETRGD/
POE4#
IRQ4-DS
44
45
P95
P94
P93
P92
P91
P90
MTIOC6B/MTIOC6B#/
GTIOC4A/GTIOC7A/
GTIOC4A#/GTIOC7A#
46
47
48
49
50
MTIOC7A/MTIOC7A#/
GTIOC5A/GTIOC8A/
GTIOC5A#/GTIOC8A#
MTIOC7B/MTIOC7B#/
GTIOC6A/GTIOC9A/
GTIOC6A#/GTIOC9A#
MTIOC6D/MTIOC6D#/
GTIOC4B/GTIOC7B/
GTIOC4B#/GTIOC7B#
MTIOC7C/MTIOC7C#/
GTIOC5B/GTIOC8B/
GTIOC5B#/GTIOC8B#
MTIOC7D/MTIOC7D#/
GTIOC6B/GTIOC9B/
GTIOC6B#/GTIOC9B#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 54 of 201
RX66T Group
1. Overview
Table 1.9
List of Pin and Pin Functions (100-pin without PGA pseudo-differential input and without USB pin)
(3/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
51
52
53
54
55
56
57
58
P76
D0 [A0/D0]
MTIOC4D/MTIOC4D#/
GTIOC2B/GTIOC6B/
GTIOC2B#/GTIOC6B#
P75
P74
P73
P72
P71
P70
P33
D1 [A1/D1]
D2 [A2/D2]
D3 [A3/D3]
D4 [A4/D4]
D5 [A5/D5]
D6 [A6/D6]
D7 [A7/D7]
MTIOC4C/MTIOC4C#/
GTIOC1B/GTIOC5B/
GTIOC1B#/GTIOC5B#
MTIOC3D/MTIOC3D#/
GTIOC0B/GTIOC4B/
GTIOC0B#/GTIOC4B#
MTIOC4B/MTIOC4B#/
GTIOC2A/GTIOC6A/
GTIOC2A#/GTIOC6A#
MTIOC4A/MTIOC4A#/
GTIOC1A/GTIOC5A/
GTIOC1A#/GTIOC5A#
MTIOC3B/MTIOC3B#/
GTIOC0A/GTIOC4A/
GTIOC0A#/GTIOC4A#
GTETRGA/GTETRGB/ CTS9#/RTS9#/SS9#
GTETRGC/GTETRGD/
POE0#
IRQ5-DS
MTIOC3A/MTCLKA/
MTIOC3A#/MTCLKA#/
GTIOC3B/GTIOC3B#/
TMO0
SSLA3
IRQ13-DS
59
P32
D8 [A8/D8]
D9 [A9/D9]
MTIOC3C/MTCLKB/
MTIOC3C#/MTCLKB#/
GTIOC3A/GTIOC3A#/
TMO6
SSLA2
IRQ12-DS
60
61
VCC
VSS
P31
P30
MTIOC0A/MTCLKC/
MTIOC0A#/MTCLKC#/
TMRI6
SSLA1
IRQ6
62
63
D10 [A10/D10] MTIOC0B/MTCLKD/
SCK8/CTS8#/RTS8#/
IRQ7
IRQ4
COMP3
MTIOC0B#/MTCLKD#/ SS8#/SSLA0
TMCI6
64
65
P24
P23
D11 [A11/D11] MTIC5U/MTIC5U#/
TMCI2/TMO6
CTS8#/RTS8#/SS8#/
SCK8/RSPCKA
COMP0
COMP1
D12 [A12/D12] MTIC5V/MTIC5V#/
TMO2/CACREF
TXD8/SMOSI8/SSDA8/ IRQ11
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/MOSIA/CTX0
66
67
P22
P21
D13 [A13/D13] MTIC5W/MTCLKD/
RXD8/SMISO8/SSCL8/ IRQ10
ADTRG2#/
COMP2
MTIC5W#/MTCLKD#/ RXD12/SMISO12/
MTIOC9B/TMRI2/
TMO4
SSCL12/RXDX12/
MISOA/CRX0
D14 [A14/D14] MTIOC9A/MTCLKA/
TMCI4
TXD8/SMOSI8/SSDA8/ IRQ6-DS
AN217
AN216
ADTRG1#/
COMP5
MTIOC9A#/MTCLKA#/ TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/MOSIA
68
69
70
P20
P65
P64
D15 [A15/D15] MTIOC9C/MTCLKB/
CTS8#/RTS8#/SS8#/
IRQ7-DS
IRQ9
ADTRG0#/
COMP4
MTIOC9C#/MTCLKB#/ SCK8/RSPCKA
TMRI4
A12
A13
AN211/
CMPC53/
DA1
IRQ8
AN210/
CMPC33/
DA0
71
72
AVCC2
AVCC2
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 55 of 201
RX66T Group
1. Overview
Table 1.9
List of Pin and Pin Functions (100-pin without PGA pseudo-differential input and without USB pin)
(4/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
Analog
Others
73
74
AVSS2
1
P63
P62
P61
P60
P55
P54
P53
P52
P51
P50
A12* /A14
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
AN209/
CMPC23
1
75
76
77
78
79
80
81
82
83
A13* /A15
AN208/
CMPC43
1
A14* /A16
AN207/
CMPC13
1
A15* /A17
AN206/
CMPC03
1
A16* /A18
AN203/
CMPC32
1
A17* /A19
AN202/
CMPC22
1
A18* /A20
AN201/
CMPC12
AN200/
CMPC02
AN205/
CMPC52
AN204/
CMPC42
84
85
P47
P46
AN103
AN102/
CMPC50/
CMPC51
86
87
P45
P44
AN101/
CMPC40/
CMPC41
AN100/
CMPC30/
CMPC31
88
89
P43
P42
AN003
AN002/
CMPC20/
CMPC21
90
91
P41
P40
AN001/
CMPC10/
CMPC11
AN000/
CMPC00/
CMPC01
92
93
94
95
96
AVCC1
AVCC0
AVSS0
AVSS1
P82
P81
ALE/WAIT#
CS2#
MTIC5U/MTIC5U#/
TMO4
SCK6/SCK12
IRQ3
COMP5
COMP4
97
MTIC5V/MTIC5V#/
TMCI4
TXD6/SMOSI6/SSDA6/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
98
99
P80
P11
CS1#
RD#
MTIC5W/MTIC5W#/
TMRI4
RXD6/SMISO6/SSCL6/ IRQ5
RXD12/SMISO12/
SSCL12/RXDX12
COMP3
MTIOC3A/MTCLKC/
MTIOC3A#/MTCLKC#/
MTIOC9D/GTIOC3B/
GTETRGA/GTIOC3B#/
GTETRGC/TMO3/
POE9#
IRQ1-DS
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 56 of 201
RX66T Group
1. Overview
Table 1.9
List of Pin and Pin Functions (100-pin without PGA pseudo-differential input and without USB pin)
(5/5)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
100-Pin
LFQFP
(MTU, GPTW, TMR,
POE, POEG, CAC)
I/O Port
Bus
(SCI, RSPI, RIIC, CAN) (IRQ, NMI)
CTS6#/RTS6#/SS6# IRQ0-DS
Analog
Others
100
P10
MTIOC9B/MTCLKD/
MTIOC9B#/MTCLKD#/
GTETRGB/GTETRGD/
TMRI3/POE12#
Note 1. These pins are only enabled for products with 128 Kbytes of RAM.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 57 of 201
RX66T Group
1. Overview
Table 1.10
List of Pin and Pin Functions (80-pin with PGA pseudo-differential input and without USB pin) (1/5)
Pin
Number
Timer
Communications
Interrupt
80-Pin
LQFP
80-Pin
LFQFP
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
1
2
3
EMLE
VSS
UB
P00
MTIOC9A/
MTIOC9A#/
CACREF
RXD9/SMISO9/SSCL9/
RXD12/SMISO12/
SSCL12/RXDX12
IRQ2
IRQ4
ADST1/
COMP0
4
5
6
VCL
MD/FINED
P01
PE4
PE3
MTIOC9C/
MTIOC9C#/
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE12#
TXD9/SMOSI9/SSDA9/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
ADST2/
COMP1
7
8
MTCLKC/
MTCLKC#/
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE10#
SCK9
IRQ1
MTCLKD/
MTCLKD#/
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE11#
CTS9#/RTS9#/SS9#
IRQ2-DS
9
RES#
XTAL
VSS
10
11
12
13
14
15
P37
P36
EXTAL
VCC
PE2
PD7
POE10#
NMI
TRST#
MTIOC9A/
MTIOC9A#/
GTIOC0A/
TXD5/SMOSI5/SSDA5/
SSLA1/CTX0
IRQ8
GTIOC3A/
GTIOC0A#/
GTIOC3A#/
TMRI1/TMRI5
16
TMS
PD6
MTIOC9C/
MTIOC9C#/
GTIOC0B/
GTIOC3B/
GTIOC0B#/
GTIOC3B#/
TMO1
CTS1#/RTS1#/SS1#/
CTS11#/RTS11#/SS11#/
SSLA0
IRQ5
ADST0
17
18
19
TDI
PD5
PD4
PD3
GTIOC1A/
RXD1/SMISO1/SSCL1/
RXD11/SMISO11/SSCL11
IRQ6
IRQ2
GTETRGA/
GTIOC1A#/
TMRI0/TMRI6
TCK
TDO
GTIOC1B/
SCK1/SCK11
GTETRGB/
GTIOC1B#/
TMCI0/TMCI6
GTIOC2A/
GTETRGC/
GTIOC2A#/
TMO0
TXD1/SMOSI1/SSDA1/
TXD11/SMOSI11/SSDA11
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 58 of 201
RX66T Group
1. Overview
Table 1.10
List of Pin and Pin Functions (80-pin with PGA pseudo-differential input and without USB pin) (2/5)
Pin
Number
Timer
Communications
Interrupt
80-Pin
LQFP
80-Pin
LFQFP
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
20
21
22
PD2
GTIOC2B/
GTIOC0A/
GTIOC2B#/
GTIOC0A#/
TMCI1/TMO4
SCK5/SCK8/MOSIA
PB6
PB5
GTIOC2A/
GTIOC2A#
RXD5/SMISO5/SSCL5/
RXD11/SMISO11/
SSCL11/RXD12/
SMISO12/SSCL12/
RXDX12/CRX0
IRQ2
GTIOC2B/
GTIOC2B#
TXD5/SMOSI5/SSDA5/
TXD11/SMOSI11/
SSDA11/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/CTX0
23
24
VCC
VSS
PB4
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE8#
CTS5#/RTS5#/SS5#/
SCK11/CTS11#/RTS11#/
SS11#
IRQ3-DS
25
26
PB3
PB2
MTIOC0A/
MTIOC0A#/
CACREF
SCK6/RSPCKA
IRQ9
27
28
MTIOC0B/
MTIOC0B#/
GTADSM0/
TMRI0
TXD6/SMOSI6/SSDA6/
SDA
ADSM0
ADSM1
PB1
MTIOC0C/
MTIOC0C#/
GTADSM1/
TMCI0
RXD6/SMISO6/SSCL6/
SCL
IRQ4
29
30
31
PB0
PA5
PA3
MTIOC0D/
MTIOC0D#/
TMO0
TXD6/SMOSI6/SSDA6/
CTS11#/RTS11#/SS11#/
MOSIA
IRQ8
IRQ1
ADTRG2#
ADTRG1#
MTIOC1A/
MTIOC1A#/
TMCI3
RXD6/SMISO6/SSCL6/
RXD8/SMISO8/SSCL8/
MISOA
MTIOC2A/
MTIOC2A#/
GTADSM0/
TMRI7
TXD9/SMOSI9/SSDA9/
SCK8/SSLA0
32
33
VCC
VSS
P96
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE4#
CTS8#/RTS8#/SS8#
IRQ4-DS
34
35
P95
P94
MTIOC6B/
MTIOC6B#/
GTIOC4A/
GTIOC7A/
GTIOC4A#/
GTIOC7A#
36
MTIOC7A/
MTIOC7A#/
GTIOC5A/
GTIOC8A/
GTIOC5A#/
GTIOC8A#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 59 of 201
RX66T Group
1. Overview
Table 1.10
List of Pin and Pin Functions (80-pin with PGA pseudo-differential input and without USB pin) (3/5)
Pin
Number
Timer
Communications
Interrupt
80-Pin
LQFP
80-Pin
LFQFP
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
37
38
39
40
41
42
43
44
45
46
P93
MTIOC7B/
MTIOC7B#/
GTIOC6A/
GTIOC9A/
GTIOC6A#/
GTIOC9A#
P92
P91
P90
P76
P75
P74
P73
P72
P71
P70
MTIOC6D/
MTIOC6D#/
GTIOC4B/
GTIOC7B/
GTIOC4B#/
GTIOC7B#
MTIOC7C/
MTIOC7C#/
GTIOC5B/
GTIOC8B/
GTIOC5B#/
GTIOC8B#
MTIOC7D/
MTIOC7D#/
GTIOC6B/
GTIOC9B/
GTIOC6B#/
GTIOC9B#
MTIOC4D/
MTIOC4D#/
GTIOC2B/
GTIOC6B/
GTIOC2B#/
GTIOC6B#
MTIOC4C/
MTIOC4C#/
GTIOC1B/
GTIOC5B/
GTIOC1B#/
GTIOC5B#
MTIOC3D/
MTIOC3D#/
GTIOC0B/
GTIOC4B/
GTIOC0B#/
GTIOC4B#
MTIOC4B/
MTIOC4B#/
GTIOC2A/
GTIOC6A/
GTIOC2A#/
GTIOC6A#
MTIOC4A/
MTIOC4A#/
GTIOC1A/
GTIOC5A/
GTIOC1A#/
GTIOC5A#
MTIOC3B/
MTIOC3B#/
GTIOC0A/
GTIOC4A/
GTIOC0A#/
GTIOC4A#
47
48
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE0#
CTS9#/RTS9#/SS9#
IRQ5-DS
VCC
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 60 of 201
RX66T Group
1. Overview
Table 1.10
List of Pin and Pin Functions (80-pin with PGA pseudo-differential input and without USB pin) (4/5)
Pin
Number
Timer
Communications
Interrupt
80-Pin
LQFP
80-Pin
LFQFP
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
49
P31
MTIOC0A/
MTCLKC/
MTIOC0A#/
MTCLKC#/
TMRI6
SSLA1
IRQ6
50
51
VSS
P30
P27
P22
MTIOC0B/
MTCLKD/
MTIOC0B#/
MTCLKD#/
TMCI6
SCK8/CTS8#/RTS8#/
SS8#/SSLA0
IRQ7
COMP3
52
53
MTIOC1A/
MTIOC0C/
MTIOC1A#/
MTIOC0C#/
POE9#
IRQ15
IRQ10
MTIC5W/
MTCLKD/
MTIC5W#/
MTCLKD#/
MTIOC9B/
TMRI2/TMO4
RXD8/SMISO8/SSCL8/
RXD12/SMISO12/
SSCL12/RXDX12/
MISOA/CRX0
ADTRG2#/
COMP2
54
55
P21
P20
MTIOC9A/
MTCLKA/
MTIOC9A#/
MTCLKA#/
TMCI4
TXD8/SMOSI8/SSDA8/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/MOSIA
IRQ6-DS
IRQ7-DS
AN217
AN216
ADTRG1#/
COMP5
MTIOC9C/
MTCLKB/
MTIOC9C#/
MTCLKB#/
TMRI4
CTS8#/RTS8#/SS8#/
SCK8/RSPCKA
ADTRG0#/
COMP4
56
57
P65
P64
IRQ9
IRQ8
AN211/CMPC53/
DA1
AN210/CMPC33/
DA0
58
59
60
61
62
63
64
65
66
AVCC2
AVSS2
P62
P55
P54
P53
P52
P47
P46
IRQ6
IRQ3
IRQ2
IRQ1
IRQ0
AN208/CMPC43
AN203/CMPC32
AN202/CMPC22
AN201/CMPC12
AN200/CMPC02
AN103
AN102/CMPC50/
CMPC51
67
68
P45
P44
AN101/CMPC40/
CMPC41
AN100/CMPC30/
CMPC31
69
70
71
PH4
P43
P42
AN107/PGAVSS1
AN003
AN002/CMPC20/
CMPC21
72
73
74
P41
P40
PH0
AN001/CMPC10/
CMPC11
AN000/CMPC00/
CMPC01
AN007/PGAVSS0
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 61 of 201
RX66T Group
1. Overview
Table 1.10
List of Pin and Pin Functions (80-pin with PGA pseudo-differential input and without USB pin) (5/5)
Pin
Number
Timer
Communications
Interrupt
80-Pin
LQFP
80-Pin
LFQFP
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
75
76
77
78
79
AVCC1
AVCC0
AVSS0
AVSS1
P11
MTIOC3A/
MTCLKC/
IRQ1-DS
MTIOC3A#/
MTCLKC#/
MTIOC9D/
GTIOC3B/
GTETRGA/
GTIOC3B#/
GTETRGC/
TMO3/POE9#
80
P10
MTIOC9B/
CTS6#/RTS6#/SS6#
IRQ0-DS
MTCLKD/
MTIOC9B#/
MTCLKD#/
GTETRGB/
GTETRGD/
TMRI3/POE12#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 62 of 201
RX66T Group
1. Overview
Table 1.11
List of Pin and Pin Functions (64-pin with PGA pseudo-differential input and without USB pin) (1/4)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
64-Pin
LFQFP
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
1
2
EMLE
UB
P00
MTIOC9A/
MTIOC9A#/
CACREF
RXD9/SMISO9/SSCL9/
RXD12/SMISO12/
SSCL12/RXDX12
IRQ2
ADST1/
COMP0
3
4
5
VCL
MD/FINED
P01
MTIOC9C/
MTIOC9C#/
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE12#
TXD9/SMOSI9/SSDA9/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
IRQ4
ADST2/
COMP1
6
RES#
XTAL
VSS
7
P37
P36
8
9
EXTAL
VCC
10
11
12
PE2
PD7
POE10#
NMI
TRST#
MTIOC9A/
MTIOC9A#/
GTIOC0A/
TXD5/SMOSI5/SSDA5/
SSLA1/CTX0
IRQ8
GTIOC3A/
GTIOC0A#/
GTIOC3A#/
TMRI1/TMRI5
13
TMS
PD6
MTIOC9C/
MTIOC9C#/
GTIOC0B/
GTIOC3B/
GTIOC0B#/
GTIOC3B#/
TMO1
CTS1#/RTS1#/SS1#/
CTS11#/RTS11#/SS11#/
SSLA0
IRQ5
ADST0
14
15
16
17
TDI
PD5
PD4
PD3
PB6
GTIOC1A/
RXD1/SMISO1/SSCL1/
RXD11/SMISO11/SSCL11
IRQ6
IRQ2
GTETRGA/
GTIOC1A#/
TMRI0/TMRI6
TCK
TDO
GTIOC1B/
SCK1/SCK11
GTETRGB/
GTIOC1B#/
TMCI0/TMCI6
GTIOC2A/
GTETRGC/
GTIOC2A#/
TMO0
TXD1/SMOSI1/SSDA1/
TXD11/SMOSI11/SSDA11
GTIOC2A/
GTIOC2A#
RXD5/SMISO5/SSCL5/
RXD11/SMISO11/
SSCL11/RXD12/
IRQ2
SMISO12/SSCL12/
RXDX12/CRX0
18
19
20
PB5
PB4
PB3
GTIOC2B/
GTIOC2B#
TXD5/SMOSI5/SSDA5/
TXD11/SMOSI11/
SSDA11/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/CTX0
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE8#
CTS5#/RTS5#/SS5#/
SCK11/CTS11#/RTS11#/
SS11#
IRQ3-DS
IRQ9
MTIOC0A/
MTIOC0A#/
CACREF
SCK6/RSPCKA
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 63 of 201
RX66T Group
1. Overview
Table 1.11
List of Pin and Pin Functions (64-pin with PGA pseudo-differential input and without USB pin) (2/4)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
64-Pin
LFQFP
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
21
22
23
PB2
MTIOC0B/
MTIOC0B#/
GTADSM0/
TMRI0
TXD6/SMOSI6/SSDA6/
SDA
ADSM0
PB1
PB0
MTIOC0C/
MTIOC0C#/
GTADSM1/
TMCI0
RXD6/SMISO6/SSCL6/
SCL
IRQ4
IRQ8
ADSM1
MTIOC0D/
MTIOC0D#/
TMO0
TXD6/SMOSI6/SSDA6/
CTS11#/RTS11#/SS11#/
MOSIA
ADTRG2#
24
25
VCC
VSS
P96
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE4#
CTS8#/RTS8#/SS8#
IRQ4-DS
26
27
P95
P94
P93
P92
P91
P90
P76
P75
MTIOC6B/
MTIOC6B#/
GTIOC4A/
GTIOC7A/
GTIOC4A#/
GTIOC7A#
28
29
30
31
32
33
34
MTIOC7A/
MTIOC7A#/
GTIOC5A/
GTIOC8A/
GTIOC5A#/
GTIOC8A#
MTIOC7B/
MTIOC7B#/
GTIOC6A/
GTIOC9A/
GTIOC6A#/
GTIOC9A#
MTIOC6D/
MTIOC6D#/
GTIOC4B/
GTIOC7B/
GTIOC4B#/
GTIOC7B#
MTIOC7C/
MTIOC7C#/
GTIOC5B/
GTIOC8B/
GTIOC5B#/
GTIOC8B#
MTIOC7D/
MTIOC7D#/
GTIOC6B/
GTIOC9B/
GTIOC6B#/
GTIOC9B#
MTIOC4D/
MTIOC4D#/
GTIOC2B/
GTIOC6B/
GTIOC2B#/
GTIOC6B#
MTIOC4C/
MTIOC4C#/
GTIOC1B/
GTIOC5B/
GTIOC1B#/
GTIOC5B#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 64 of 201
RX66T Group
1. Overview
Table 1.11
List of Pin and Pin Functions (64-pin with PGA pseudo-differential input and without USB pin) (3/4)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
64-Pin
LFQFP
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
35
36
37
38
39
P74
MTIOC3D/
MTIOC3D#/
GTIOC0B/
GTIOC4B/
GTIOC0B#/
GTIOC4B#
P73
P72
P71
P70
MTIOC4B/
MTIOC4B#/
GTIOC2A/
GTIOC6A/
GTIOC2A#/
GTIOC6A#
MTIOC4A/
MTIOC4A#/
GTIOC1A/
GTIOC5A/
GTIOC1A#/
GTIOC5A#
MTIOC3B/
MTIOC3B#/
GTIOC0A/
GTIOC4A/
GTIOC0A#/
GTIOC4A#
GTETRGA/
GTETRGB/
GTETRGC/
GTETRGD/
POE0#
CTS9#/RTS9#/SS9#
IRQ5-DS
40
41
42
VCC
VSS
P22
MTIC5W/
MTCLKD/
MTIC5W#/
MTCLKD#/
MTIOC9B/
TMRI2/TMO4
RXD8/SMISO8/SSCL8/
RXD12/SMISO12/
SSCL12/RXDX12/
MISOA/CRX0
IRQ10
ADTRG2#/
COMP2
43
44
P21
P20
MTIOC9A/
MTCLKA/
MTIOC9A#/
MTCLKA#/
TMCI4
TXD8/SMOSI8/SSDA8/
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/MOSIA
IRQ6-DS
IRQ7-DS
AN217
AN216
ADTRG1#/
COMP5
MTIOC9C/
MTCLKB/
MTIOC9C#/
MTCLKB#/
TMRI4
CTS8#/RTS8#/SS8#/
SCK8/RSPCKA
ADTRG0#/
COMP4
45
46
P65
P64
IRQ9
IRQ8
AN211/CMPC53/
DA1
AN210/CMPC33/
DA0
47
48
49
50
51
52
AVCC2
AVSS2
P54
P53
P52
P46
IRQ2
IRQ1
IRQ0
AN202/CMPC22
AN201/CMPC12
AN200/CMPC02
AN102/CMPC50/
CMPC51
53
54
55
P45
P44
PH4
AN101/CMPC40/
CMPC41
AN100/CMPC30/
CMPC31
AN107/PGAVSS1
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 65 of 201
RX66T Group
1. Overview
Table 1.11
List of Pin and Pin Functions (64-pin with PGA pseudo-differential input and without USB pin) (4/4)
Pin
Number
Timer
Communications
Interrupt
Power Supply
Clock System
Control
(MTU, GPTW,
TMR, POE,
POEG, CAC)
64-Pin
LFQFP
I/O Port
(SCI, RSPI, RIIC, CAN)
(IRQ, NMI)
Analog
Others
56
57
58
P42
AN002/CMPC20/
CMPC21
P41
P40
PH0
AN001/CMPC10/
CMPC11
AN000/CMPC00/
CMPC01
59
60
61
62
63
64
AN007/PGAVSS0
AVCC1
AVCC0
AVSS0
AVSS1
P11
MTIOC3A/
MTCLKC/
IRQ1-DS
MTIOC3A#/
MTCLKC#/
MTIOC9D/
GTIOC3B/
GTETRGA/
GTIOC3B#/
GTETRGC/
TMO3/POE9#
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 66 of 201
RX66T Group
2. CPU
2.
CPU
Figure 2.1 shows register set of the CPU.
Control register
b31
General-purpose register
b31
b0
b0
R0 (SP)*1
ISP (Interrupt stack pointer)
USP (User stack pointer)
R1
R2
INTB (Interrupt table register)
R3
R4
PC (Program counter)
R5
PSW (Processor status word)
BPC (Backup PC)
R6
R7
R8
BPSW (Backup PSW)
R9
R10
R11
R12
R13
R14
R15
FINTV (Fast interrupt vector register)
FPSW (Single precision floating-point status word)
EXTB (Exception table register)
DSP instruction register
b71
b0
ACC0 (Accumulator 0)
ACC1 (Accumulator 1)
Note 1. The stack pointer (SP) is switchable between the interrupt stack pointer (ISP) and user stack pointer
(USP) by changing the value of the U bit in the PSW.
Figure 2.1
Register Set of the CPU
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RX66T Group
2. CPU
2.1
General-Purpose Registers (R0 to R15)
This CPU has sixteen 32-bit general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address
registers.
R0, a general-purpose register, also functions as the stack pointer (SP).
The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the
stack pointer select bit (U) in the processor status word (PSW).
2.2
Control Registers
(1) Interrupt Stack Pointer (ISP) / User Stack Pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
(2) Exception Table Register (EXTB)
The exception table register (EXTB) specifies the address where the exception vector table starts.
(3) Interrupt Table Register (INTB)
The interrupt table register (INTB) specifies the address where the interrupt vector table starts.
(4) Program Counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(5) Processor Status Word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(6) Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(7) Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(8) Fast Interrupt Vector Register (FINTV)
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
(9) Single-Precision Floating-Point Status Word (FPSW)
The single-precision floating-point status word (FPSW) indicates the results of single-precision floating-point
operations.
When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified
by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the
occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has
been set to 1, this value is retained until it is set to 0 by software (j = X, U, Z, O, or V).
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RX66T Group
2. CPU
2.3
Accumulator
The accumulator (ACC0 or ACC1) is a 72-bit register used for DSP instructions. The accumulator is handled as a 96-bit
register for reading and writing. At this time, when bits 95 to 72 of the accumulator are read, the value where the value of
bit 71 is sign extended is read. Writing to bits 95 to 72 of the accumulator is ignored. ACC0 is also used for the multiply
and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in
ACC0 is modified by execution of the instruction.
Use the MVTACGU, MVTACHI, and MVTACLO instructions for writing to the accumulator. The MVTACGU,
MVTACHI, and MVTACLO instructions write data to bits 95 to 64, the higher-order 32 bits (bits 63 to 32), and the
lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions for reading data from the accumulator. The
MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions read data from the guard bits (bits 95 to 64), higher-
order 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 16), and the lower-order 32 bits (bits 31 to 0), respectively.
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RX66T Group
3. Address Space
3.
Address Space
3.1
Address Space
This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh.
Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the
operating mode and states of control bits.
Single-chip mode*1
On-chip ROM enabled
extended mode
On-chip ROM disabled
extended mode
0000 0000h
0002 0000h
0000 0000h
0002 0000h
0000 0000h
0002 0000h
RAM*2
RAM*2
RAM*2
Reserved area*3
Reserved area*3
Reserved area*3
0008 0000h
000A 4000h
000A 6000h
0008 0000h
000A 4000h
000A 6000h
0008 0000h
000A 4000h
000A 6000h
Peripheral I/O register
Reserved area*3
Peripheral I/O register
Reserved area*3
Peripheral I/O register
Reserved area*3
Peripheral I/O register
Peripheral I/O register
Peripheral I/O register
0010 0000h
0010 0000h
0010 0000h
ROM (data flash memory)*2
ROM (data flash memory)*2
Reserved area*3
ROM (option-setting memory)
Reserved area*3
ROM (option-setting memory)
0010 8000h
0012 0040h
0012 0080h
0010 8000h
0012 0040h
0012 0080h
Reserved area*3
Reserved area*3
Reserved area*3
007E 0000h
0080 0000h
007E 0000h
0080 0000h
Peripheral I/O register
Peripheral I/O register
Reserved area*3
ECCRAM
Reserved area*3
ECCRAM
00FF C000h
0100 0000h
00FF C000h
0100 0000h
00FF C000h
0100 0000h
ECCRAM
Reserved area*3
Reserved area*3
0500 0000h
0800 0000h
0500 0000h
0800 0000h
External address space
(CS area)
External address space
(CS area)
Reserved area*3
Reserved area*3
Reserved area*3
FF00 0000h
FF7F 8000h
FF80 0000h
FF7F 8000h
FF80 0000h
ROM (user boot)
Reserved area*3
ROM (user boot)
Reserved area*3
External address space
(CS area)
FFF0 0000h
FFFF FFFFh
FFF0 0000h
FFFF FFFFh
ROM (code flash memory)*2
ROM (code flash memory)*2
FFFF FFFFh
Note 1. The memory map in boot mode and user boot mode is the same as that in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
Code Flash Memory
Data Flash Memory
Capacity Address
FFF0 0000h to FFFF FFFFh 32 Kbytes 0010 0000h to 0010 7FFFh
RAM
Capacity
Address
Capacity
Address
1 Mbyte
128 Kbytes 0000 0000h to 0001 FFFFh
512 Kbytes FFF8 0000h to FFFF FFFFh
256 Kbytes FFFC 0000h to FFFF FFFFh
64 Kbytes
0000 0000h to 0000 FFFFh
Note 3. Reserved areas should not be accessed.
Figure 3.1
Memory Map in Each Operating Mode
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RX66T Group
3. Address Space
3.2
External Address Space
The external address space is divided into four CS areas (CS0 to CS3), each corresponding to the CSn# signal output
from a CSn# (n = 0 to 3) pin.
Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS3) in on-chip ROM disabled
extended mode.
On-chip ROM disabled
extended mode
0000 0000h
On-chip RAM
0002 0000h
Reserved area*1
0008 0000h
000A 4000h
000A 6000h
Peripheral I/O register
Reserved area*1
Peripheral I/O register
0010 0000h
Reserved area*1
0500 0000h
Reserved area*1
CS3 (2 Mbytes)
Reserved area*1
CS2 (2 Mbytes)
Reserved area*1
CS1 (2 Mbytes)
00FF C000h
0100 0000h
ECCRAM
05DF FFFFh
05E0 0000h
Reserved area*1
05FF FFFFh
0600 0000h
0500 0000h
0800 0000h
06DF FFFFh
06E0 0000h
External address space
(CS area)
06FF FFFFh
0700 0000h
07DF FFFFh
07E0 0000h
Reserved area*1
07FF FFFFh
FF00 0000h
Reserved area*1
CS0 (2 Mbytes)
FF00 0000h
FFFF FFFFh
FFDF 0000h
FFE0 0000h
External address space
(CS area)*2
FFFF FFFFh
Note 1. Reserved areas should not be accessed.
Note 2. The CS0 area is disabled in on-chip ROM enabled extended mode. In this mode, the memory map for the
addresses above 0800 0000h is as shown in Figure 3.1.
Figure 3.2
Correspondence between External Address Spaces and CS Areas
(In On-Chip ROM Disabled Extended Mode)
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RX66T Group
4. I/O Registers
4.
I/O Registers
This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on
writing to registers are also given at the end.
(1) I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
The number of access cycles indicates the number of cycles based on the specified reference clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2) Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) set to 0.
A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
(a) Write to an I/O register.
(b) Read the value from the I/O register to a general register.
(c) Execute the operation using the value read.
(d) Execute the subsequent instruction.
[Instruction examples]
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
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RX66T Group
4. I/O Registers
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3) Number of Access Cycles to I/O Registers
For the number of I/O register access cycles, refer to Table 4.1, List of I/O Registers (Address Order).
1
The number of access cycles to I/O registers is obtained by following equation.*
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral busses 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except
for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK, BCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access states shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided
clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of
access cycles shown in Table 4.1.
Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction fetching
to the external memory or bus access from the different bus master (DMAC or DTC).
(4) Notes on Sleep Mode and Mode Transitions
During sleep mode or mode transitions, do not write to the registers related to system control (indicated by 'SYSTEM' in
the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).
(5) Restrictions in Relation to RMPA and String-Manipulation Instructions
The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited, and
operation is not guaranteed if this restriction is not observed.
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RX66T Group
4. I/O Registers
4.1
I/O Register Addresses (Address Order)
Table 4.1
List of I/O Registers (Address Order) (1 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 0000h
SYSTE Mode Monitor Register
M
MDMONR
16
16
16
16
16
16
16
16
16
16
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Operating
Modes
0008 0002h
0008 0006h
0008 0008h
0008 000Ch
SYSTE Mode Status Register
M
MDSR
Operating
Modes
SYSTE System Control Register 0
M
SYSCR0
SYSCR1
SBYCR
Operating
Modes
SYSTE System Control Register 1
M
Operating
Modes
SYSTE Standby Control Register
M
Low
Power
Consumpt
ion
0008 0010h
0008 0014h
0008 0018h
0008 001Ch
SYSTE Module Stop Control Register A
M
MSTPCRA
MSTPCRB
MSTPCRC
MSTPCRD
32
32
32
32
32
32
32
32
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Low
Power
Consumpt
ion
SYSTE Module Stop Control Register B
M
Low
Power
Consumpt
ion
SYSTE Module Stop Control Register C
M
Low
Power
Consumpt
ion
SYSTE Module Stop Control Register D
M
Low
Power
Consumpt
ion
0008 0020h
0008 0024h
0008 0026h
0008 0028h
0008 002Ah
0008 0030h
0008 0032h
0008 0034h
0008 0035h
0008 0036h
0008 0037h
0008 003Ch
SYSTE System Clock Control Register
M
SCKCR
32
16
16
16
8
32
16
16
16
8
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Clock
Generatio
n Circuit
SYSTE System Clock Control Register 2
M
SCKCR2
SCKCR3
PLLCR
Clock
Generatio
n Circuit
SYSTE System Clock Control Register 3
M
Clock
Generatio
n Circuit
SYSTE PLL Control Register
M
Clock
Generatio
n Circuit
SYSTE PLL Control Register 2
M
PLLCR2
Clock
Generatio
n Circuit
SYSTE External Bus Clock Control Register
M
BCKCR
8
8
Clock
Generatio
n Circuit
SYSTE Main Clock Oscillator Control Register
M
MOSCCR
LOCOCR
ILOCOCR
HOCOCR
HOCOCR2
OSCOVFSR
8
8
Clock
Generatio
n Circuit
SYSTE Low-Speed On-Chip Oscillator Control Register
M
8
8
Clock
Generatio
n Circuit
SYSTE IWDT-Dedicated On-Chip Oscillator Control Register
M
8
8
Clock
Generatio
n Circuit
SYSTE High-Speed On-Chip Oscillator Control Register
M
8
8
Clock
Generatio
n Circuit
SYSTE High-Speed On-Chip Oscillator Control Register 2
M
8
8
Clock
Generatio
n Circuit
SYSTE Oscillation Stabilization Flag Register
M
8
8
Clock
Generatio
n Circuit
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RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (2 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 0040h
SYSTE Oscillation Stop Detection Control Register
M
OSTDCR
OSTDSR
RSTCKCR
8
8
8
8
8
8
3 ICLK
3 ICLK
3 ICLK
Clock
Generatio
n Circuit
0008 0041h
0008 00A1h
SYSTE Oscillation Stop Detection Status Register
M
Clock
Generatio
n Circuit
SYSTE Sleep Mode Return Clock Source Switching Register
M
Low
Power
Consumpt
ion
0008 00A2h
SYSTE Main Clock Oscillator Wait Control Register
M
MOSCWTCR
8
8
3 ICLK
Clock
Generatio
n Circuit
0008 00C0h
0008 00C2h
0008 00E0h
0008 00E1h
0008 00E2h
0008 00E3h
0008 03FEh
SYSTE Reset Status Register 2
M
RSTSR2
SWRR
8
16
8
8
16
8
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Resets
Resets
LVDA
LVDA
LVDA
LVDA
SYSTE Software Reset Register
M
SYSTE Voltage Monitoring 1 Circuit Control Register 1
M
LVD1CR1
LVD1SR
LVD2CR1
LVD2SR
PRCR
SYSTE Voltage Monitoring 1 Circuit Status Register
M
8
8
SYSTE Voltage Monitoring 2 Circuit Control Register 1
M
8
8
SYSTE Voltage Monitoring 2 Circuit Status Register
M
8
8
SYSTE Protect Register
M
16
16
Register
Write
Protection
Function
0008 1000h
0008 1004h
0008 101Ch
FLASH ROM Cache Enable Register
FLASH ROM Cache Invalidate Register
ROMCE
16
16
8
16
16
8
2 ICLK
2 ICLK
2 ICLK
Flash
ROMCIV
MEMWAIT
Flash
SYSTE Memory Wait Cycle Setting Register
M
Clock
Generatio
n Circuit
0008 1040h
0008 1044h
0008 1048h
0008 104Ch
FLASH Non-Cacheable Area 0 Address Register
FLASH Non-Cacheable Area 0 Setting Register
FLASH Non-Cacheable Area 1 Address Register
FLASH Non-Cacheable Area 1 Setting Register
NCRG0
NCRC0
NCRG1
NCRC1
32
32
32
32
32
32
32
32
2 ICLK
2 ICLK
2 ICLK
2 ICLK
Flash
Flash
Flash
Flash
0008 1200h
0008 1201h
0008 1204h
0008 1208h
0008 12C0h
RAM
RAM
RAM
RAM
RAM
RAM Operating Mode Control Register
RAM Error Status Register
RAMMODE
RAMSTS
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
RAM
RAM
RAM
RAM
RAM
RAM Protection Register
RAMPRCR
RAMECAD
8
8
RAM Error Address Capture Register
ECCRAM Operating Mode Control Register
32
8
32
8
ECCRAMMOD
E
0008 12C1h
0008 12C2h
0008 12C3h
0008 12C4h
0008 12C8h
0008 12CCh
0008 12D0h
RAM
RAM
RAM
RAM
RAM
RAM
RAM
ECCRAM 2-Bit Error Status Register
ECCRAM2ST
S
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
RAM
RAM
RAM
RAM
RAM
RAM
RAM
ECCRAM 1-Bit Error Information Update Enable Register ECCRAM1ST
SEN
ECCRAM 1-Bit Error Status Register
ECCRAM1ST
S
8
8
ECCRAM Protection Register
ECCRAMPRC
R
8
8
ECCRAM 2-Bit Error Address Capture Register
ECCRAM 1-Bit Error Address Capture Register
ECCRAM Protection Register 2
ECCRAM2EC
AD
32
32
8
32
32
8
ECCRAM1EC
AD
ECCRAMPRC
R2
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RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (3 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 12D4h
RAM
ECCRAM Test Control Register
ECCRAMETS
T
8
8
2 ICLK
RAM
0008 1300h
0008 1304h
0008 1308h
0008 130Ah
0008 1310h
0008 2000h
0008 2004h
0008 2008h
0008 200Ch
0008 2010h
0008 2013h
0008 2014h
0008 2018h
0008 201Ch
0008 201Dh
0008 201Eh
0008 201Fh
0008 2040h
0008 2044h
0008 2048h
0008 204Ch
0008 2050h
0008 2053h
0008 2054h
0008 205Ch
0008 205Dh
0008 205Eh
0008 205Fh
0008 2080h
0008 2084h
0008 2088h
0008 208Ch
0008 2090h
0008 2093h
0008 2094h
0008 209Ch
0008 209Dh
0008 209Eh
0008 209Fh
0008 20C0h
0008 20C4h
0008 20C8h
0008 20CCh
0008 20D0h
0008 20D3h
0008 20D4h
0008 20DCh
0008 20DDh
BSC
BSC
BSC
BSC
BSC
Bus Error Status Clear Register
Bus Error Monitoring Enable Register
Bus Error Status Register 1
BERCLR
BEREN
BERSR1
BERSR2
BUSPRI
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
Buses
Buses
8
8
Buses
Bus Error Status Register 2
16
16
32
32
32
16
16
8
16
16
32
32
32
16
16
8
Buses
Bus Priority Control Register
Buses
DMAC0 DMA Source Address Register
DMAC0 DMA Destination Address Register
DMAC0 DMA Transfer Count Register
DMAC0 DMA Block Transfer Count Register
DMAC0 DMA Transfer Mode Register
DMAC0 DMA Interrupt Setting Register
DMAC0 DMA Address Mode Register
DMAC0 DMA Offset Register
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMAMD
DMOFR
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
16
32
8
16
32
8
DMAC0 DMA Transfer Enable Register
DMAC0 DMA Software Start Register
DMAC0 DMA Status Register
8
8
8
8
DMAC0 DMA Request Source Flag Control Register
DMAC1 DMA Source Address Register
DMAC1 DMA Destination Address Register
DMAC1 DMA Transfer Count Register
DMAC1 DMA Block Transfer Count Register
DMAC1 DMA Transfer Mode Register
DMAC1 DMA Interrupt Setting Register
DMAC1 DMA Address Mode Register
DMAC1 DMA Transfer Enable Register
DMAC1 DMA Software Start Register
DMAC1 DMA Status Register
8
8
32
32
32
16
16
8
32
32
32
16
16
8
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
16
8
16
8
8
8
8
8
DMAC1 DMA Request Source Flag Control Register
DMAC2 DMA Source Address Register
DMAC2 DMA Destination Address Register
DMAC2 DMA Transfer Count Register
DMAC2 DMA Block Transfer Count Register
DMAC2 DMA Transfer Mode Register
DMAC2 DMA Interrupt Setting Register
DMAC2 DMA Address Mode Register
DMAC2 DMA Transfer Enable Register
DMAC2 DMA Software Start Register
DMAC2 DMA Status Register
8
8
32
32
32
16
16
8
32
32
32
16
16
8
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
16
8
16
8
8
8
8
8
DMAC2 DMA Request Source Flag Control Register
DMAC3 DMA Source Address Register
DMAC3 DMA Destination Address Register
DMAC3 DMA Transfer Count Register
DMAC3 DMA Block Transfer Count Register
DMAC3 DMA Transfer Mode Register
DMAC3 DMA Interrupt Setting Register
DMAC3 DMA Address Mode Register
DMAC3 DMA Transfer Enable Register
DMAC3 DMA Software Start Register
8
8
32
32
32
16
16
8
32
32
32
16
16
8
DMAMD
DMCNT
DMREQ
16
8
16
8
8
8
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 76 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (4 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 20DEh
0008 20DFh
0008 2100h
0008 2104h
0008 2108h
0008 210Ch
0008 2110h
0008 2113h
0008 2114h
0008 211Ch
0008 211Dh
0008 211Eh
0008 211Fh
0008 2140h
0008 2144h
0008 2148h
0008 214Ch
0008 2150h
0008 2153h
0008 2154h
0008 215Ch
0008 215Dh
0008 215Eh
0008 215Fh
0008 2180h
0008 2184h
0008 2188h
0008 218Ch
0008 2190h
0008 2193h
0008 2194h
0008 219Ch
0008 219Dh
0008 219Eh
0008 219Fh
0008 21C0h
0008 21C4h
0008 21C8h
0008 21CCh
0008 21D0h
0008 21D3h
0008 21D4h
0008 21DCh
0008 21DDh
0008 21DEh
0008 21DFh
0008 2200h
0008 2204h
0008 2400h
0008 2404h
DMAC3 DMA Status Register
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DMACAa
DTCa
DMAC3 DMA Request Source Flag Control Register
DMAC4 DMA Source Address Register
DMAC4 DMA Destination Address Register
DMAC4 DMA Transfer Count Register
DMAC4 DMA Block Transfer Count Register
DMAC4 DMA Transfer Mode Register
DMAC4 DMA Interrupt Setting Register
DMAC4 DMA Address Mode Register
DMAC4 DMA Transfer Enable Register
DMAC4 DMA Software Start Register
DMAC4 DMA Status Register
32
32
32
16
16
8
32
32
32
16
16
8
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
16
8
16
8
8
8
8
8
DMAC4 DMA Request Source Flag Control Register
DMAC5 DMA Source Address Register
DMAC5 DMA Destination Address Register
DMAC5 DMA Transfer Count Register
DMAC5 DMA Block Transfer Count Register
DMAC5 DMA Transfer Mode Register
DMAC5 DMA Interrupt Setting Register
DMAC5 DMA Address Mode Register
DMAC5 DMA Transfer Enable Register
DMAC5 DMA Software Start Register
DMAC5 DMA Status Register
8
8
32
32
32
16
16
8
32
32
32
16
16
8
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
16
8
16
8
8
8
8
8
DMAC5 DMA Request Source Flag Control Register
DMAC6 DMA Source Address Register
DMAC6 DMA Destination Address Register
DMAC6 DMA Transfer Count Register
DMAC6 DMA Block Transfer Count Register
DMAC6 DMA Transfer Mode Register
DMAC6 DMA Interrupt Setting Register
DMAC6 DMA Address Mode Register
DMAC6 DMA Transfer Enable Register
DMAC6 DMA Software Start Register
DMAC6 DMA Status Register
8
8
32
32
32
16
16
8
32
32
32
16
16
8
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
16
8
16
8
8
8
8
8
DMAC6 DMA Request Source Flag Control Register
DMAC7 DMA Source Address Register
DMAC7 DMA Destination Address Register
DMAC7 DMA Transfer Count Register
DMAC7 DMA Block Transfer Count Register
DMAC7 DMA Transfer Mode Register
DMAC7 DMA Interrupt Setting Register
DMAC7 DMA Address Mode Register
DMAC7 DMA Transfer Enable Register
DMAC7 DMA Software Start Register
DMAC7 DMA Status Register
8
8
32
32
32
16
16
8
32
32
32
16
16
8
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMAST
DMIST
16
8
16
8
8
8
8
8
DMAC7 DMA Request Source Flag Control Register
8
8
DMAC
DMAC
DTC
DMAC Module Start Register
DMAC74 Interrupt Status Monitor Register
DTC Control Register
8
8
8
8
DTCCR
DTCVBR
8
8
DTC
DTC Vector Base Register
32
32
DTCa
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 77 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (5 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 2408h
0008 240Ch
0008 240Eh
0008 3002h
0008 3004h
0008 3008h
0008 3012h
0008 3014h
0008 3018h
0008 3022h
0008 3024h
0008 3028h
0008 3032h
0008 3034h
0008 3038h
0008 3802h
0008 380Ah
0008 3812h
0008 381Ah
0008 3822h
0008 382Ah
0008 3832h
0008 383Ah
0008 3880h
0008 6400h
0008 6404h
0008 6408h
0008 640Ch
0008 6410h
0008 6414h
0008 6418h
0008 641Ch
0008 6420h
0008 6424h
0008 6428h
0008 642Ch
0008 6430h
0008 6434h
0008 6438h
0008 643Ch
0008 6500h
0008 6504h
0008 6508h
0008 650Ch
0008 6514h
0008 6520h
0008 6524h
0008 6526h
0008 6528h
0008 652Ch
DTC
DTC
DTC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
DTC Address Mode Register
DTCADMOD
DTCST
8
8
2 ICLK
2 ICLK
DTCa
DTCa
DTCa
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
Buses
MPU
DTC Module Start Register
8
8
DTC Status Register
DTCSTS
CS0MOD
CS0WCR1
CS0WCR2
CS1MOD
CS1WCR1
CS1WCR2
CS2MOD
CS2WCR1
CS2WCR2
CS3MOD
CS3WCR1
CS3WCR2
CS0CR
16
16
32
32
16
32
32
16
32
32
16
32
32
16
16
16
16
16
16
16
16
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
32
32
16
16
32
32
16
32
32
16
32
32
16
32
32
16
16
16
16
16
16
16
16
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
32
32
2 ICLK
CS0 Mode Register
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1 ICLK
CS0 Wait Control Register 1
CS0 Wait Control Register 2
CS1 Mode Register
CS1 Wait Control Register 1
CS1 Wait Control Register 2
CS2 Mode Register
CS2 Wait Control Register 1
CS2 Wait Control Register 2
CS3 Mode Register
CS3 Wait Control Register 1
CS3 Wait Control Register 2
CS0 Control Register
CS0 Recovery Cycle Register
CS1 Control Register
CS0REC
CS1CR
CS1 Recovery Cycle Register
CS2 Control Register
CS1REC
CS2CR
CS2 Recovery Cycle Register
CS3 Control Register
CS2REC
CS3CR
CS3 Recovery Cycle Register
CS Recovery Cycle Insertion Enable Register
Region-0 Start Page Number Register
Region-0 End Page Number Register
Region-1 Start Page Number Register
Region-1 End Page Number Register
Region-2 Start Page Number Register
Region-2 End Page Number Register
Region-3 Start Page Number Register
Region-3 End Page Number Register
Region-4 Start Page Number Register
Region-4 End Page Number Register
Region-5 Start Page Number Register
Region-5 End Page Number Register
Region-6 Start Page Number Register
Region-6 End Page Number Register
Region-7 Start Page Number Register
Region-7 End Page Number Register
Memory-Protection Enable Register
Background Access Control Register
Memory-Protection Error Status-Clearing Register
Memory-Protection Error Status Register
Data Memory-Protection Error Address Register
Region Search Address Register
Region Search Operation Register
Region Invalidation Operation Register
Instruction-Hit Region Register
Data-Hit Region Register
CS3REC
CSRECEN
RSPAGE0
REPAGE0
RSPAGE1
REPAGE1
RSPAGE2
REPAGE2
RSPAGE3
REPAGE3
RSPAGE4
REPAGE4
RSPAGE5
REPAGE5
RSPAGE6
REPAGE6
RSPAGE7
REPAGE7
MPEN
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
MPBAC
1 ICLK
MPU
MPECLR
MPESTS
MPDEA
1 ICLK
MPU
1 ICLK
MPU
1 ICLK
MPU
MPSA
1 ICLK
MPU
MPOPS
1 ICLK
MPU
MPOPI
1 ICLK
MPU
MHITI
1 ICLK
MPU
MHITD
1 ICLK
MPU
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 78 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (6 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 7010h to ICU
0008 70FFh
Interrupt Request Register 016 to Interrupt Request
Register 255
IR016 to IR255
8
8
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
ICUC
ICUC
ICUC
0008 711Ah to ICU
0008 71FFh
DTC Transfer Request Enable Register 026 to DTC
Transfer Request Enable Register 255
DTCER026 to
DTCER255
0008 7202h to ICU
0008 721Fh
Interrupt Request Enable Register 02 to Interrupt
Request Enable Register 1F
IER02 to
IER1F
0008 72E0h
0008 72E1h
0008 72F0h
ICU
ICU
ICU
Software Interrupt Generation Register
Software Interrupt 2 Generation Register
Fast Interrupt Set Register
SWINTR
SWINT2R
FIR
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
ICUC
ICUC
ICUC
ICUC
16
8
16
8
0008 7300h to ICU
0008 73FFh
Interrupt Source Priority Register 000 to Interrupt Source IPR000 to
Priority Register 255
IPR255
0008 7400h
0008 7404h
0008 7408h
0008 740Ch
0008 7410h
0008 7414h
0008 7418h
0008 741Ch
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
DMAC Trigger Select Register 0
DMAC Trigger Select Register 1
DMAC Trigger Select Register 2
DMAC Trigger Select Register 3
DMAC Trigger Select Register 4
DMAC Trigger Select Register 5
DMAC Trigger Select Register 6
DMAC Trigger Select Register 7
IRQ Control Register 0 to IRQ Control Register 15
DMRSR0
DMRSR1
DMRSR2
DMRSR3
DMRSR4
DMRSR5
DMRSR6
DMRSR7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
0008 7500h to ICU
0008 750Fh
IRQCR0 to
IRQCR15
0008 7520h
0008 7521h
0008 7528h
0008 752Ah
0008 7580h
0008 7581h
0008 7582h
0008 7583h
0008 7590h
0008 7594h
0008 7600h
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
IRQ Pin Digital Filter Enable Register 0
IRQ Pin Digital Filter Enable Register 1
IRQ Pin Digital Filter Setting Register 0
IRQ Pin Digital Filter Setting Register 1
Non-Maskable Interrupt Status Register
Non-Maskable Interrupt Enable Register
Non-Maskable Interrupt Status Clear Register
NMI Pin Interrupt Control Register
IRQFLTE0
IRQFLTE1
IRQFLTC0
IRQFLTC1
NMISR
8
8
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
16
16
8
16
16
8
NMIER
8
8
NMICLR
NMICR
8
8
8
8
NMI Pin Digital Filter Enable Register
NMI Pin Digital Filter Setting Register
Group BE0 Interrupt Request Register
NMIFLTE
NMIFLTC
GRPBE0
8
8
8
8
32
32
2 ICLK to
1 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
0008 7630h
0008 7634h
0008 7640h
0008 7670h
0008 7674h
0008 7680h
0008 7830h
0008 7870h
0008 7900h
0008 7901h
0008 7902h
0008 7903h
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
Group BL0 Interrupt Request Register
GRPBL0
GRPBL1
GENBE0
GENBL0
GENBL1
GCRBE0
GRPAL0
GENAL0
PIAR0
32
32
32
32
32
32
32
32
8
32
32
32
32
32
32
32
32
8
2 ICLK to
1 PCLKB
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
Group BL1 Interrupt Request Register
2 ICLK to
1 PCLKB
Group BE0 Interrupt Request Enable Register
Group BL0 Interrupt Request Enable Register
Group BL1 Interrupt Request Enable Register
Group BE0 Interrupt Clear Register
2 ICLK to
1 PCLKB
2 ICLK to
1 PCLKB
2 ICLK to
1 PCLKB
2 ICLK to
1 PCLKB
Group AL0 Interrupt Request Register
2 ICLK to
1 PCLKA
Group AL0 Interrupt Request Enable Register
Software Configurable Interrupt A Request Register 0
Software Configurable Interrupt A Request Register 1
Software Configurable Interrupt A Request Register 2
Software Configurable Interrupt A Request Register 3
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
PIAR1
8
8
2 ICLK to
1 PCLKA
PIAR2
8
8
2 ICLK to
1 PCLKA
PIAR3
8
8
2 ICLK to
1 PCLKA
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 79 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (7 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 7904h
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
Software Configurable Interrupt A Request Register 4
Software Configurable Interrupt A Request Register 5
Software Configurable Interrupt A Request Register 6
Software Configurable Interrupt A Request Register 7
Software Configurable Interrupt A Request Register 8
Software Configurable Interrupt A Request Register 9
Software Configurable Interrupt A Request Register A
Software Configurable Interrupt A Request Register B
Software Configurable Interrupt A Request Register C
Software Configurable Interrupt A Request Register D
Software Configurable Interrupt A Request Register E
Software Configurable Interrupt A Request Register F
Software Configurable Interrupt A Request Register 10
Software Configurable Interrupt A Request Register 11
Software Configurable Interrupt A Request Register 12
PIAR4
PIAR5
PIAR6
PIAR7
PIAR8
PIAR9
PIARA
PIARB
PIARC
PIARD
PIARE
PIARF
PIAR10
PIAR11
PIAR12
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2 ICLK to
1 PCLKA
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
0008 7905h
0008 7906h
0008 7907h
0008 7908h
0008 7909h
0008 790Ah
0008 790Bh
0008 790Ch
0008 790Dh
0008 790Eh
0008 790Fh
0008 7910h
0008 7911h
0008 7912h
0008 79D0h
0008 79D1h
0008 79D2h
0008 79D3h
0008 79D4h
0008 79D5h
0008 79D6h
0008 79D7h
0008 79D8h
0008 79D9h
0008 79DAh
0008 79DBh
0008 79DCh
0008 79DDh
0008 79DEh
0008 79DFh
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR208
208
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR209
209
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR210
210
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR211
211
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR212
212
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR213
213
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR214
214
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR215
215
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR216
216
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR217
217
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR218
218
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR219
219
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR220
220
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR221
221
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR222
222
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR223
223
2 ICLK to
1 PCLKA
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 80 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (8 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 79E0h
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
ICU
Software Configurable Interrupt A Source Select Register SLIAR224
224
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2 ICLK to
1 PCLKA
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
ICUC
0008 79E1h
0008 79E2h
0008 79E3h
0008 79E4h
0008 79E5h
0008 79E6h
0008 79E7h
0008 79E8h
0008 79E9h
0008 79EAh
0008 79EBh
0008 79ECh
0008 79EDh
0008 79EEh
0008 79EFh
0008 79F0h
0008 79F1h
0008 79F2h
0008 79F3h
0008 79F4h
0008 79F5h
0008 79F6h
0008 79F7h
0008 79F8h
0008 79F9h
0008 79FAh
0008 79FBh
0008 79FCh
0008 79FDh
0008 79FEh
Software Configurable Interrupt A Source Select Register SLIAR225
225
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR226
226
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR227
227
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR228
228
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR229
229
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR230
230
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR231
231
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR232
232
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR233
233
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR234
234
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR235
235
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR236
236
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR237
237
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR238
238
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR239
239
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR240
240
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR241
241
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR242
242
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR243
243
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR244
244
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR245
245
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR246
246
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR247
247
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR248
248
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR249
249
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR250
250
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR251
251
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR252
252
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR253
253
2 ICLK to
1 PCLKA
Software Configurable Interrupt A Source Select Register SLIAR254
254
2 ICLK to
1 PCLKA
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 81 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (9 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 79FFh
ICU
Software Configurable Interrupt A Source Select Register SLIAR255
255
8
8
2 ICLK to
1 PCLKA
2 ICLK
ICUC
0008 7A00h
ICU
Software Configurable Interrupt Source Select Register
Write Protect Register
SLIPRCR
8
8
2 ICLK to
1 PCLKA/B
2 ICLK
ICUC
0008 8000h
0008 8002h
0008 8004h
0008 8006h
0008 8008h
0008 800Ah
0008 800Ch
0008 8010h
0008 8012h
0008 8014h
0008 8016h
0008 8018h
0008 801Ah
0008 801Ch
0008 8020h
0008 8022h
0008 8024h
0008 8026h
0008 8030h
0008 8032h
0008 8034h
0008 8036h
0008 8038h
0008 8040h
0008 8042h
0008 8044h
0008 8045h
0008 8046h
0008 8049h
0008 8200h
0008 8201h
0008 8202h
0008 8203h
0008 8204h
0008 8204h
0008 8205h
0008 8206h
0008 8206h
0008 8207h
0008 8208h
0008 8208h
0008 8209h
0008 820Ah
0008 820Ah
0008 820Bh
0008 820Ch
0008 820Dh
CMT
CMT0
CMT0
CMT0
CMT1
CMT1
CMT1
CMT
CMT2
CMT2
CMT2
CMT3
CMT3
CMT3
WDT
WDT
WDT
WDT
IWDT
IWDT
IWDT
IWDT
IWDT
DA
Compare Match Timer Start Register 0
Compare Match Timer Control Register
Compare Match Counter
CMSTR0
CMCR
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
CMT
CMT
CMCNT
CMCOR
CMCR
CMT
Compare Match Constant Register
Compare Match Timer Control Register
Compare Match Counter
CMT
CMT
CMCNT
CMCOR
CMSTR1
CMCR
CMT
Compare Match Constant Register
Compare Match Timer Start Register 1
Compare Match Timer Control Register
Compare Match Counter
CMT
CMT
CMT
CMCNT
CMCOR
CMCR
CMT
Compare Match Constant Register
Compare Match Timer Control Register
Compare Match Counter
CMT
CMT
CMCNT
CMCOR
WDTRR
WDTCR
WDTSR
WDTRCR
IWDTRR
IWDTCR
IWDTSR
IWDTRCR
IWDTCSTPR
DADR0
DADR1
DACR
CMT
Compare Match Constant Register
WDT Refresh Register
CMT
WDTA
WDTA
WDTA
WDTA
IWDTa
IWDTa
IWDTa
IWDTa
IWDTa
R12DAb
R12DAb
R12DAb
R12DAb
R12DAb
R12DAb
TMR
WDT Control Register
16
16
8
16
16
8
WDT Status Register
WDT Reset Control Register
IWDT Refresh Register
8
8
IWDT Control Register
16
16
8
16
16
8
IWDT Status Register
IWDT Reset Control Register
IWDT Count Stop Control Register
D/A Data Register 0
8
8
16
16
8
16
16
8
DA
D/A Data Register 1
DA
D/A Control Register
DA
Data Register Format Select Register
D/A A/D Synchronous Start Control Register
D/A Destination Select Register
Timer Control Register
DADPR
DAADSCR
DADSELR
TCR
8
8
DA
8
8
DA
8
8
TMR0
TMR1
TMR0
TMR1
TMR0
8
8
Timer Control Register
TCR
8
8
TMR
Timer Control/Status Register
Timer Control/Status Register
Time Constant Register A
TCSR
8
8
TMR
TCSR
8
8
TMR
TCORA
TCORA
TCORA
TCORB
TCORB
TCORB
TCNT
8
8
TMR
TMR01 Time Constant Register A
16
8
16
8
TMR
TMR1
TMR0
Time Constant Register A
Time Constant Register B
TMR
8
8
TMR
TMR01 Time Constant Register B
16
8
16
8
TMR
TMR1
TMR0
Time Constant Register B
Timer Counter
TMR
8
8
TMR
TMR01 Timer Counter
TCNT
16
8
16
8
TMR
TMR1
TMR0
Timer Counter
TCNT
TMR
Timer Counter Control Register
TCCR
8
8
TMR
TMR01 Timer Counter Control Register
TCCR
16
8
16
8
TMR
TMR1
TMR0
TMR1
Timer Counter Control Register
Timer Counter Start Register
Timer Counter Start Register
TCCR
TMR
TCSTR
TCSTR
8
8
TMR
8
8
TMR
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 82 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (10 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 8210h
0008 8211h
0008 8212h
0008 8213h
0008 8214h
0008 8214h
0008 8215h
0008 8216h
0008 8216h
0008 8217h
0008 8218h
0008 8218h
0008 8219h
0008 821Ah
0008 821Ah
0008 821Bh
0008 821Ch
0008 821Dh
0008 8220h
0008 8221h
0008 8222h
0008 8223h
0008 8224h
0008 8224h
0008 8225h
0008 8226h
0008 8226h
0008 8227h
0008 8228h
0008 8228h
0008 8229h
0008 822Ah
0008 822Ah
0008 822Bh
0008 8230h
0008 8231h
0008 8232h
0008 8233h
0008 8234h
0008 8234h
0008 8235h
0008 8236h
0008 8236h
0008 8237h
0008 8238h
0008 8238h
0008 8239h
0008 823Ah
0008 823Ah
0008 823Bh
TMR2
TMR3
TMR2
TMR3
TMR2
Timer Control Register
TCR
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
TMR
Timer Control Register
TCR
Timer Control/Status Register
Timer Control/Status Register
Time Constant Register A
TCSR
TCSR
TCORA
TCORA
TCORA
TCORB
TCORB
TCORB
TCNT
8
8
8
8
8
8
TMR23 Time Constant Register A
16
8
16
8
TMR3
TMR2
Time Constant Register A
Time Constant Register B
8
8
TMR23 Time Constant Register B
16
8
16
8
TMR3
TMR2
Time Constant Register B
Timer Counter
8
8
TMR23 Timer Counter
TCNT
16
8
16
8
TMR3
TMR2
Timer Counter
TCNT
Timer Counter Control Register
TCCR
TCCR
TCCR
TCSTR
TCSTR
TCR
8
8
TMR23 Timer Counter Control Register
16
8
16
8
TMR3
TMR2
TMR3
TMR4
TMR5
TMR4
TMR5
TMR4
Timer Counter Control Register
Timer Counter Start Register
Timer Counter Start Register
Timer Control Register
8
8
8
8
8
8
Timer Control Register
TCR
8
8
Timer Control/Status Register
Timer Control/Status Register
Time Constant Register A
TCSR
TCSR
TCORA
TCORA
TCORA
TCORB
TCORB
TCORB
TCNT
8
8
8
8
8
8
TMR45 Time Constant Register A
16
8
16
8
TMR5
TMR4
Time Constant Register A
Time Constant Register B
8
8
TMR45 Time Constant Register B
16
8
16
8
TMR5
TMR4
Time Constant Register B
Timer Counter
8
8
TMR45 Timer Counter
TCNT
16
8
16
8
TMR5
TMR4
Timer Counter
TCNT
Timer Counter Control Register
TCCR
TCCR
TCCR
TCR
8
8
TMR45 Timer Counter Control Register
16
8
16
8
TMR5
TMR6
TMR7
TMR6
TMR7
TMR6
Timer Counter Control Register
Timer Control Register
8
8
Timer Control Register
TCR
8
8
Timer Control/Status Register
Timer Control/Status Register
Time Constant Register A
TCSR
TCSR
TCORA
TCORA
TCORA
TCORB
TCORB
TCORB
TCNT
8
8
8
8
8
8
TMR67 Time Constant Register A
16
8
16
8
TMR7
TMR6
Time Constant Register A
Time Constant Register B
8
8
TMR67 Time Constant Register B
16
8
16
8
TMR7
TMR6
Time Constant Register B
Timer Counter
8
8
TMR67 Timer Counter
TCNT
16
8
16
8
TMR7
TMR6
Timer Counter
TCNT
Timer Counter Control Register
TCCR
TCCR
TCCR
8
8
TMR67 Timer Counter Control Register
TMR7 Timer Counter Control Register
16
8
16
8
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 83 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (11 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
CRCCR
CRCDIR
CRCDOR
ICCR1
ICCR2
ICMR1
ICMR2
ICMR3
ICFER
ICSER
ICIER
ICLK ≥ PCLK ICLK < PCLK Function
0008 8280h
0008 8284h
0008 8288h
0008 8300h
0008 8301h
0008 8302h
0008 8303h
0008 8304h
0008 8305h
0008 8306h
0008 8307h
0008 8308h
0008 8309h
0008 830Ah
0008 830Bh
0008 830Ch
0008 830Dh
0008 830Eh
0008 830Fh
0008 8310h
0008 8311h
0008 8312h
0008 8313h
0008 9000h
0008 9004h
0008 9008h
CRC
CRC Control Register
8
32
32
8
8
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
CRCA
CRCA
CRCA
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
RIICa
S12ADH
S12ADH
S12ADH
CRC
CRC Data Input Register
CRC Data Output Register
8, 32
CRC
8, 16, 32 2, 3 PCLKB
2
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
RIIC0
I C-bus Control Register 1
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2
I C-bus Control Register 2
8
2
I C-bus Mode Register 1
8
8
2
I C-bus Mode Register 2
8
8
2
I C-bus Mode Register 3
8
8
2
I C-bus Function Enable Register
8
8
2
I C-bus Status Enable Register
8
8
2
I C-bus Interrupt Enable Register
8
8
2
I C-bus Status Register 1
ICSR1
8
8
2
I C-bus Status Register 2
ICSR2
8
8
Slave Address Register L0
Slave Address Register U0
Slave Address Register L1
Slave Address Register U1
Slave Address Register L2
Slave Address Register U2
SARL0
SARU0
SARL1
SARU1
SARL2
SARU2
ICBRL
8
8
8
8
8
8
8
8
8
8
8
8
2
I C-bus Bit Rate Low-Level Register
8
8
2
I C-bus Bit Rate High-Level Register
ICBRH
ICDRT
ICDRR
ADCSR
ADANSA0
8
8
2
I C-bus Transmit Data Register
8
8
2
I C-bus Receive Data Register
8
8
S12AD A/D Control Register
16
16
16
16
16
16
S12AD A/D Channel Select Register A0
S12AD A/D-Converted Value Addition/Average Function Channel ADADS0
Select Register 0
0008 900Ch
S12AD A/D-Converted Value Addition/Average Count Select
Register
ADADC
8
8
2, 3 PCLKB
2 ICLK
S12ADH
0008 900Eh
0008 9010h
0008 9014h
0008 9018h
0008 901Eh
0008 9020h
0008 9022h
0008 9024h
0008 9026h
0008 9028h
0008 902Ah
0008 902Ch
0008 902Eh
0008 9066h
0008 907Ah
0008 907Ch
0008 907Dh
0008 9080h
0008 9084h
0008 9086h
0008 908Ch
S12AD A/D Control Extended Register
S12AD A/D Conversion Start Trigger Select Register
S12AD A/D Channel Select Register B0
S12AD A/D Data Duplication Register
S12AD A/D Self-Diagnosis Data Register
S12AD A/D Data Register 0
ADCER
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
ADSTRGR
ADANSB0
ADDBLDR
ADRD
ADDR0
S12AD A/D Data Register 1
ADDR1
S12AD A/D Data Register 2
ADDR2
S12AD A/D Data Register 3
ADDR3
S12AD A/D Data Register 4
ADDR4
S12AD A/D Data Register 5
ADDR5
S12AD A/D Data Register 6
ADDR6
S12AD A/D Data Register 7
ADDR7
S12AD A/D Sample-and-Hold Circuit Control Register
S12AD A/D Disconnection Detection Control Register
S12AD A/D Sample-and-Hold Operating Mode Select Register
S12AD A/D Event Link Control Register
S12AD A/D Group Scan Priority Control Register
S12AD A/D Data Duplication Register A
S12AD A/D Data Duplication Register B
ADSHCR
ADDISCR
ADSHMSR
ADELCCR
ADGSPCR
ADDBLDRA
ADDBLDRB
8
8
8
8
16
16
16
8
16
16
16
8
S12AD A/D Comparison Function Window A/B Status Monitoring ADWINMON
Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 84 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (12 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 9090h
0008 9094h
S12AD A/D Compare Control Register
ADCMPCR
16
16
16
16
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
S12ADH
S12ADH
S12AD A/D Comparison Function Window A Channel Select
Register 0
ADCMPANSR
0
0008 9098h
0008 909Ch
0008 909Eh
0008 90A0h
0008 90A6h
0008 90A8h
0008 90AAh
0008 90ACh
S12AD A/D Comparison Function Window A Comparison
Condition Setting Register 0
ADCMPLR0
16
16
16
16
8
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12AD A/D Comparison Function Window A Lower Level Setting ADCMPDR0
Register
S12AD A/D Comparison Function Window A Upper Level Setting ADCMPDR1
Register
S12AD A/D Comparison Function Window A Channel Status
Register 0
ADCMPSR0
S12AD A/D Comparison Function Window B Channel Select
Register
ADCMPBNSR
S12AD A/D Comparison Function Window B Lower Level Setting ADWINLLB
Register
16
16
8
16
16
8
S12AD A/D Comparison Function Window B Upper Level Setting ADWINULB
Register
S12AD A/D Comparison Function Window B Channel Status
Register
ADCMPBSR
0008 90D4h
0008 90D9h
0008 90E0h
0008 90E1h
0008 90E2h
0008 90E3h
0008 90E4h
0008 90E5h
0008 90E6h
0008 90E7h
0008 91A0h
0008 91A2h
S12AD A/D Channel Select Register C0
S12AD A/D Group C Trigger Select Register
S12AD A/D Sampling State Register 0
S12AD A/D Sampling State Register 1
S12AD A/D Sampling State Register 2
S12AD A/D Sampling State Register 3
S12AD A/D Sampling State Register 4
S12AD A/D Sampling State Register 5
S12AD A/D Sampling State Register 6
S12AD A/D Sampling State Register 7
S12AD A/D Programmable Gain Amplifier Control Register
ADANSC0
ADGCTRGR
ADSSTR0
ADSSTR1
ADSSTR2
ADSSTR3
ADSSTR4
ADSSTR5
ADSSTR6
ADSSTR7
ADPGACR
16
8
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
S12AD A/D Programmable Gain Amplifier Gain Setting Register ADPGAGS0
0
0008 91B0h
S12AD A/D Programmable Gain Amplifier Differential Input
Control Register
ADPGADCR0
16
16
2, 3 PCLKB
2 ICLK
S12ADH
0008 91C0h
0008 91C1h
0008 91C2h
0008 91C3h
0008 91C4h
0008 91C5h
0008 91C6h
0008 91C7h
0008 9200h
0008 9204h
0008 9208h
S12AD A/D Channel Conversion Order Setting Register 0
S12AD A/D Channel Conversion Order Setting Register 1
S12AD A/D Channel Conversion Order Setting Register 2
S12AD A/D Channel Conversion Order Setting Register 3
S12AD A/D Channel Conversion Order Setting Register 4
S12AD A/D Channel Conversion Order Setting Register 5
S12AD A/D Channel Conversion Order Setting Register 6
S12AD A/D Channel Conversion Order Setting Register 7
S12AD1 A/D Control Register
ADSCS0
ADSCS1
ADSCS2
ADSCS3
ADSCS4
ADSCS5
ADSCS6
ADSCS7
ADCSR
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
S12AD1 A/D Channel Select Register A0
ADANSA0
S12AD1 A/D-Converted Value Addition/Average Function Channel ADADS0
Select Register 0
0008 920Ch
S12AD1 A/D-Converted Value Addition/Average Count Select
Register
ADADC
8
8
2, 3 PCLKB
2 ICLK
S12ADH
0008 920Eh
0008 9210h
0008 9214h
0008 9218h
0008 921Eh
0008 9220h
0008 9222h
S12AD1 A/D Control Extended Register
S12AD1 A/D Conversion Start Trigger Select Register
S12AD1 A/D Channel Select Register B0
S12AD1 A/D Data Duplication Register
S12AD1 A/D Self-Diagnosis Data Register
S12AD1 A/D Data Register 0
ADCER
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
ADSTRGR
ADANSB0
ADDBLDR
ADRD
ADDR0
S12AD1 A/D Data Register 1
ADDR1
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 85 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (13 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 9224h
0008 9226h
0008 9228h
0008 922Ah
0008 922Ch
0008 922Eh
0008 9266h
0008 927Ah
0008 927Ch
0008 927Dh
0008 9280h
0008 9284h
0008 9286h
0008 928Ch
S12AD1 A/D Data Register 2
ADDR2
16
16
16
16
16
16
16
8
16
16
16
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12AD1 A/D Data Register 3
ADDR3
S12AD1 A/D Data Register 4
ADDR4
S12AD1 A/D Data Register 5
ADDR5
S12AD1 A/D Data Register 6
ADDR6
S12AD1 A/D Data Register 7
ADDR7
S12AD1 A/D Sample-and-Hold Circuit Control Register
S12AD1 A/D Disconnection Detection Control Register
S12AD1 A/D Sample-and-Hold Operating Mode Select Register
S12AD1 A/D Event Link Control Register
S12AD1 A/D Group Scan Priority Control Register
S12AD1 A/D Data Duplication Register A
S12AD1 A/D Data Duplication Register B
ADSHCR
ADDISCR
ADSHMSR
ADELCCR
ADGSPCR
ADDBLDRA
ADDBLDRB
8
8
8
8
16
16
16
8
16
16
16
8
S12AD1 A/D Comparison Function Window A/B Status Monitoring ADWINMON
Register
0008 9290h
0008 9294h
S12AD1 A/D Comparison Function Control Register
ADCMPCR
16
16
16
16
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
S12ADH
S12ADH
S12AD1 A/D Comparison Function Window A Channel Select
Register 0
ADCMPANSR
0
0008 9298h
0008 929Ch
0008 929Eh
0008 92A0h
0008 92A6h
0008 92A8h
0008 92AAh
0008 92ACh
S12AD1 A/D Comparison Function Window A Comparison
Condition Setting Register 0
ADCMPLR0
16
16
16
16
8
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12AD1 A/D Comparison Function Window A Lower Level Setting ADCMPDR0
Register
S12AD1 A/D Comparison Function Window A Upper Level Setting ADCMPDR1
Register
S12AD1 A/D Comparison Function Window A Channel Status
Register 0
ADCMPSR0
S12AD1 A/D Comparison Function Window B Channel Select
Register
ADCMPBNSR
S12AD1 A/D Comparison Function Window B Lower Level Setting ADWINLLB
Register
16
16
8
16
16
8
S12AD1 A/D Comparison Function Window B Upper Level Setting ADWINULB
Register
S12AD1 A/D Comparison Function Window B Channel Status
Register
ADCMPBSR
0008 92D4h
0008 92D9h
0008 92E0h
0008 92E1h
0008 92E2h
0008 92E3h
0008 92E4h
0008 92E5h
0008 92E6h
0008 92E7h
0008 93A0h
0008 93A2h
S12AD1 A/D Channel Select Register C0
S12AD1 A/D Group C Trigger Select Register
S12AD1 A/D Sampling State Register 0
S12AD1 A/D Sampling State Register 1
S12AD1 A/D Sampling State Register 2
S12AD1 A/D Sampling State Register 3
S12AD1 A/D Sampling State Register 4
S12AD1 A/D Sampling State Register 5
S12AD1 A/D Sampling State Register 6
S12AD1 A/D Sampling State Register 7
S12AD1 A/D Programmable Gain Amplifier Control Register
ADANSC0
ADGCTRGR
ADSSTR0
ADSSTR1
ADSSTR2
ADSSTR3
ADSSTR4
ADSSTR5
ADSSTR6
ADSSTR7
ADPGACR
16
8
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
S12AD1 A/D Programmable Gain Amplifier Gain Setting Register ADPGAGS0
0
0008 93B0h
S12AD1 A/D Programmable Gain Amplifier Differential Input
Control Register
ADPGADCR0
16
16
2, 3 PCLKB
2 ICLK
S12ADH
0008 93C0h
0008 93C1h
0008 93C2h
0008 93C3h
0008 93C4h
0008 93C5h
S12AD1 A/D Channel Conversion Order Setting Register 0
S12AD1 A/D Channel Conversion Order Setting Register 1
S12AD1 A/D Channel Conversion Order Setting Register 2
S12AD1 A/D Channel Conversion Order Setting Register 3
S12AD1 A/D Channel Conversion Order Setting Register 4
S12AD1 A/D Channel Conversion Order Setting Register 5
ADSCS0
ADSCS1
ADSCS2
ADSCS3
ADSCS4
ADSCS5
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 86 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (14 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 93C6h
0008 93C7h
0008 9400h
0008 9404h
0008 9406h
0008 9408h
S12AD1 A/D Channel Conversion Order Setting Register 6
S12AD1 A/D Channel Conversion Order Setting Register 7
S12AD2 A/D Control Register
ADSCS6
ADSCS7
ADCSR
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
8
8
16
16
16
16
16
16
16
16
S12AD2 A/D Channel Select Register A0
S12AD2 A/D Channel Select Register A1
ADANSA0
ADANSA1
S12AD2 A/D-Converted Value Addition/Average Function Channel ADADS0
Select Register 0
0008 940Ah
0008 940Ch
S12AD2 A/D-Converted Value Addition/Average Function Channel ADADS1
Select Register 1
16
8
16
8
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
S12ADH
S12ADH
S12AD2 A/D-Converted Value Addition/Average Count Select
Register
ADADC
0008 940Eh
0008 9410h
0008 9412h
0008 9414h
0008 9416h
0008 9418h
0008 941Ah
0008 941Ch
0008 941Eh
0008 9420h
0008 9422h
0008 9424h
0008 9426h
0008 9428h
0008 942Ah
0008 942Ch
0008 942Eh
0008 9430h
0008 9432h
0008 9434h
0008 9436h
0008 9440h
0008 9442h
0008 947Ah
0008 947Dh
0008 9480h
0008 9484h
0008 9486h
0008 948Ch
S12AD2 A/D Control Extended Register
S12AD2 A/D Conversion Start Trigger Select Register
S12AD2 A/D Conversion Extended Input Control Register
S12AD2 A/D Channel Select Register B0
S12AD2 A/D Channel Select Register B1
S12AD2 A/D Data Duplication Register
S12AD2 A/D Temperature Sensor Data Register
S12AD2 A/D Internal Reference Voltage Data Register
S12AD2 A/D Self-Diagnosis Data Register
S12AD2 A/D Data Register 0
ADCER
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
ADSTRGR
ADEXICR
ADANSB0
ADANSB1
ADDBLDR
ADTSDR
ADOCDR
ADRD
ADDR0
S12AD2 A/D Data Register 1
ADDR1
S12AD2 A/D Data Register 2
ADDR2
S12AD2 A/D Data Register 3
ADDR3
S12AD2 A/D Data Register 4
ADDR4
S12AD2 A/D Data Register 5
ADDR5
S12AD2 A/D Data Register 6
ADDR6
S12AD2 A/D Data Register 7
ADDR7
S12AD2 A/D Data Register 8
ADDR8
S12AD2 A/D Data Register 9
ADDR9
S12AD2 A/D Data Register 10
ADDR10
ADDR11
ADDR16
ADDR17
ADDISCR
ADELCCR
ADGSPCR
ADDBLDRA
ADDBLDRB
S12AD2 A/D Data Register 11
S12AD2 A/D Data Register 16
S12AD2 A/D Data Register 17
S12AD2 A/D Disconnection Detection Control Register
S12AD2 A/D Event Link Control Register
S12AD2 A/D Group Scan Priority Control Register
S12AD2 A/D Data Duplication Register A
S12AD2 A/D Data Duplication Register B
8
8
16
16
16
8
16
16
16
8
S12AD2 A/D Comparison Function Window A/B Status Monitoring ADWINMON
Register
0008 9490h
0008 9492h
S12AD2 A/D Comparison Function Control Register
ADCMPCR
16
8
16
8
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
S12ADH
S12ADH
S12AD2 A/D Comparison Function Window A Extended Input
Select Register
ADCMPANSE
R
0008 9493h
0008 9494h
0008 9496h
0008 9498h
0008 949Ah
S12AD2 A/D Comparison Function Window A Extended Input
Comparison Condition Setting Register
ADCMPLER
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12AD2 A/D Comparison Function Window A Channel Select
Register 0
ADCMPANSR
0
16
16
16
16
16
16
16
16
S12AD2 A/D Comparison Function Window A Channel Select
Register 1
ADCMPANSR
1
S12AD2 A/D Comparison Function Window A Comparison
Condition Setting Register 0
ADCMPLR0
S12AD2 A/D Comparison Function Window A Comparison
Condition Setting Register 1
ADCMPLR1
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 87 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (15 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 949Ch
S12AD2 A/D Comparison Function Window A Lower Level Setting ADCMPDR0
Register
16
16
16
16
8
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
0008 949Eh
0008 94A0h
0008 94A2h
0008 94A4h
0008 94A6h
0008 94A8h
0008 94AAh
0008 94ACh
S12AD2 A/D Comparison Function Window A Upper Level Setting ADCMPDR1
Register
S12AD2 A/D Comparison Function Window A Channel Status
Register 0
ADCMPSR0
ADCMPSR1
ADCMPSER
ADCMPBNSR
S12AD2 A/D Comparison Function Window A Channel Status
Register 1
S12AD2 A/D Comparison Function Window A Extended Input
Channel Status Register
S12AD2 A/D Comparison Function Window B Channel Select
Register
8
8
S12AD2 A/D Comparison Function Window B Lower Level Setting ADWINLLB
Register
16
16
8
16
16
8
S12AD2 A/D Comparison Function Window B Upper Level Setting ADWINULB
Register
S12AD2 A/D Comparison Function Window B Channel Status
Register
ADCMPBSR
0008 94D4h
0008 94D6h
0008 94D8h
0008 94D9h
0008 94DDh
0008 94DEh
0008 94DFh
0008 94E0h
0008 94E1h
0008 94E2h
0008 94E3h
0008 94E4h
0008 94E5h
0008 94E6h
0008 94E7h
0008 94E8h
0008 94E9h
0008 94EAh
0008 94EBh
0008 95C0h
0008 95C1h
0008 95C2h
0008 95C3h
0008 95C4h
0008 95C5h
0008 95C6h
0008 95C7h
0008 95C8h
0008 95C9h
0008 95CAh
0008 95CBh
0008 95D0h
0008 95D1h
0008 95E2h
S12AD2 A/D Channel Select Register C0
ADANSC0
ADANSC1
ADGCEXCR
ADGCTRGR
ADSSTRL
ADSSTRT
ADSSTRO
ADSSTR0
ADSSTR1
ADSSTR2
ADSSTR3
ADSSTR4
ADSSTR5
ADSSTR6
ADSSTR7
ADSSTR8
ADSSTR9
ADSSTR10
ADSSTR11
ADSCS0
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12ADH
S12AD2 A/D Channel Select Register C1
S12AD2 A/D Group C Extended Input Control Register
S12AD2 A/D Group C Trigger Select Register
S12AD2 A/D Sampling State Register L
S12AD2 A/D Sampling State Register T
S12AD2 A/D Sampling State Register O
S12AD2 A/D Sampling State Register 0
S12AD2 A/D Sampling State Register 1
S12AD2 A/D Sampling State Register 2
S12AD2 A/D Sampling State Register 3
S12AD2 A/D Sampling State Register 4
S12AD2 A/D Sampling State Register 5
S12AD2 A/D Sampling State Register 6
S12AD2 A/D Sampling State Register 7
S12AD2 A/D Sampling State Register 8
S12AD2 A/D Sampling State Register 9
S12AD2 A/D Sampling State Register 10
S12AD2 A/D Sampling State Register 11
S12AD2 A/D Channel Conversion Order Setting Register 0
S12AD2 A/D Channel Conversion Order Setting Register 1
S12AD2 A/D Channel Conversion Order Setting Register 2
S12AD2 A/D Channel Conversion Order Setting Register 3
S12AD2 A/D Channel Conversion Order Setting Register 4
S12AD2 A/D Channel Conversion Order Setting Register 5
S12AD2 A/D Channel Conversion Order Setting Register 6
S12AD2 A/D Channel Conversion Order Setting Register 7
S12AD2 A/D Channel Conversion Order Setting Register 8
S12AD2 A/D Channel Conversion Order Setting Register 9
S12AD2 A/D Channel Conversion Order Setting Register 10
S12AD2 A/D Channel Conversion Order Setting Register 11
S12AD2 A/D Channel Conversion Order Setting Register 12
S12AD2 A/D Channel Conversion Order Setting Register 13
ADSCS1
ADSCS2
ADSCS3
ADSCS4
ADSCS5
ADSCS6
ADSCS7
ADSCS8
ADSCS9
ADSCS10
ADSCS11
ADSCS12
ADSCS13
S12AD2 A/D Internal Reference Voltage Monitoring Circuit Enable ADVMONCR
Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 88 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (16 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 95E4h
S12AD2 A/D Internal Reference Voltage Monitoring Circuit Output ADVMONO
Enable Register
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
S12ADH
0008 A020h
0008 A020h
0008 A021h
0008 A022h
0008 A022h
0008 A023h
0008 A024h
0008 A024h
0008 A025h
0008 A026h
0008 A027h
0008 A028h
0008 A029h
0008 A02Ah
0008 A02Bh
0008 A02Ch
0008 A02Dh
0008 A02Eh
0008 A02Fh
0008 A02Eh
0008 A030h
0008 A031h
0008 A030h
0008 A032h
0008 A033h
0008 A03Ah
0008 A03Bh
0008 A03Ah
0008 A03Ch
0008 A0A0h
SCI1
SMCI1
SCI1
SCI1
SMCI1
SCI1
SCI1
SMCI1
SCI1
SMCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI1
SCI5
Serial Mode Register
SMR
8
8
SCIj,SCIi,
SCIh
Serial Mode Register
SMR
8
8
SCIj,SCIi,
SCIh
Bit Rate Register
BRR
8
8
SCIj,SCIi,
SCIh
Serial Control Register
Serial Control Register
Transmit Data Register
Serial Status Register
Serial Status Register
Receive Data Register
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
SCR
8
8
SCIj, SCIi,
SCIh
SCR
8
8
SCIj,SCIi,
SCIh
TDR
8
8
SCIj, SCIi,
SCIh
SSR
8
8
SCIj, SCIi,
SCIh
SSR
8
8
SCIj, SCIi,
SCIh
RDR
8
8
SCIj,SCIi,
SCIh
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 1
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 2
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 3
8
8
SCIj,SCIi,
SCIh
2
I C Status Register
8
8
SCIj,SCIi,
SCIh
SPI Mode Register
SPMR
TDRH
TDRL
TDRHL
RDRH
RDRL
RDRHL
MDDR
DCCR
CDR.H
CDR.L
CDR
8
8
SCIj,SCIi,
SCIh
Transmit Data Register H
Transmit Data Register L
Transmit Data Register HL
Receive Data Register H
Receive Data Register L
Receive Data Register HL
Modulation Duty Register
Data Comparison Control Register
Comparison Data Register H
Comparison Data Register L
Comparison Data Register
Serial Port Register
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
8
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
16
8
8, 16
8
SCIj,SCIi,
SCIh
SPTR
SMR
SCIj,SCIi,
SCIh
Serial Mode Register
8
8
SCIj,SCIi,
SCIh
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 89 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (17 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 A0A0h
SMCI5
SCI5
SCI5
SMCI5
SCI5
SCI5
SMCI5
SCI5
SMCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI5
SCI6
SMCI6
SCI6
Serial Mode Register
SMR
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj,SCIi,
SCIh
0008 A0A1h
0008 A0A2h
0008 A0A2h
0008 A0A3h
0008 A0A4h
0008 A0A4h
0008 A0A5h
0008 A0A6h
0008 A0A7h
0008 A0A8h
0008 A0A9h
0008 A0AAh
0008 A0ABh
0008 A0ACh
0008 A0ADh
0008 A0AEh
0008 A0AFh
0008 A0AEh
0008 A0B0h
0008 A0B1h
0008 A0B0h
0008 A0B2h
0008 A0B3h
0008 A0BAh
0008 A0BBh
0008 A0BAh
0008 A0BCh
0008 A0C0h
0008 A0C0h
0008 A0C1h
Bit Rate Register
BRR
8
8
SCIj,SCIi,
SCIh
Serial Control Register
Serial Control Register
Transmit Data Register
Serial Status Register
Serial Status Register
Receive Data Register
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
SCR
8
8
SCIj, SCIi,
SCIh
SCR
8
8
SCIj,SCIi,
SCIh
TDR
8
8
SCIj,SCIi,
SCIh
SSR
8
8
SCIj, SCIi,
SCIh
SSR
8
8
SCIj,SCIi,
SCIh
RDR
8
8
SCIj,SCIi,
SCIh
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 1
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 2
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 3
8
8
SCIj,SCIi,
SCIh
2
I C Status Register
8
8
SCIj,SCIi,
SCIh
SPI Mode Register
SPMR
TDRH
TDRL
TDRHL
RDRH
RDRL
RDRHL
MDDR
DCCR
CDR.H
CDR.L
CDR
8
8
SCIj,SCIi,
SCIh
Transmit Data Register H
Transmit Data Register L
Transmit Data Register HL
Receive Data Register H
Receive Data Register L
Receive Data Register HL
Modulation Duty Register
Data Comparison Control Register
Comparison Data Register H
Comparison Data Register L
Comparison Data Register
Serial Port Register
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
SPTR
SMR
8
8
8
8
SCIj,SCIi,
SCIh
Serial Mode Register
8
SCIj,SCIi,
SCIh
Serial Mode Register
SMR
8
SCIj,SCIi,
SCIh
Bit Rate Register
BRR
8
SCIj,SCIi,
SCIh
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 90 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (18 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 A0C2h
SCI6
SMCI6
SCI6
SCI6
SMCI6
SCI6
SMCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI6
SCI8
SMCI8
SCI8
SCI8
SMCI8
Serial Control Register
SCR
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj, SCIi,
SCIh
0008 A0C2h
0008 A0C3h
0008 A0C4h
0008 A0C4h
0008 A0C5h
0008 A0C6h
0008 A0C7h
0008 A0C8h
0008 A0C9h
0008 A0CAh
0008 A0CBh
0008 A0CCh
0008 A0CDh
0008 A0CEh
0008 A0CFh
0008 A0CEh
0008 A0D0h
0008 A0D1h
0008 A0D0h
0008 A0D2h
0008 A0D3h
0008 A0DAh
0008 A0DBh
0008 A0DAh
0008 A0DCh
0008 A100h
0008 A100h
0008 A101h
0008 A102h
0008 A102h
Serial Control Register
Transmit Data Register
Serial Status Register
SCR
8
8
SCIj,SCIi,
SCIh
TDR
8
8
SCIj,SCIi,
SCIh
SSR
8
8
SCIj, SCIi,
SCIh
Serial Status Register
SSR
8
8
SCIj, SCIi,
SCIh
Receive Data Register
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
RDR
8
8
SCIj,SCIi,
SCIh
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 1
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 2
8
8
SCIj,SCIi,
SCIh
2
I C Mode Register 3
8
8
SCIj,SCIi,
SCIh
2
I C Status Register
8
8
SCIj,SCIi,
SCIh
SPI Mode Register
SPMR
TDRH
TDRL
TDRHL
RDRH
RDRL
RDRHL
MDDR
DCCR
CDR.H
CDR.L
CDR
8
8
SCIj,SCIi,
SCIh
Transmit Data Register H
Transmit Data Register L
Transmit Data Register HL
Receive Data Register H
Receive Data Register L
Receive Data Register HL
Modulation Duty Register
Data Comparison Control Register
Comparison Data Register H
Comparison Data Register L
Comparison Data Register
Serial Port Register
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
SPTR
SMR
8
8
8
8
8
8
SCIj,SCIi,
SCIh
Serial Mode Register
8
SCIj,SCIi,
SCIh
Serial Mode Register
SMR
8
SCIj,SCIi,
SCIh
Bit Rate Register
BRR
8
SCIj,SCIi,
SCIh
Serial Control Register
Serial Control Register
SCR
8
SCIj, SCIi,
SCIh
SCR
8
SCIj,SCIi,
SCIh
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 91 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (19 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 A103h
SCI8
SCI8
SMCI8
SCI8
SMCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI8
SCI9
SMCI9
SCI9
SCI9
SMCI9
SCI9
SCI9
Transmit Data Register
TDR
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj,SCIi,
SCIh
0008 A104h
0008 A104h
0008 A105h
0008 A106h
0008 A107h
0008 A108h
0008 A109h
0008 A10Ah
0008 A10Bh
0008 A10Ch
0008 A10Dh
0008 A10Eh
0008 A10Fh
0008 A10Eh
0008 A110h
0008 A111h
0008 A110h
0008 A112h
0008 A113h
0008 A11Ah
0008 A11Bh
0008 A11Ah
0008 A11Ch
0008 A120h
0008 A120h
0008 A121h
0008 A122h
0008 A122h
0008 A123h
0008 A124h
Serial Status Register
SSR
8
8
SCIj, SCIi,
SCIh
Serial Status Register
SSR
8
8
SCIj,SCIi,
SCIh
Receive Data Register
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
I2C Mode Register 1
RDR
8
8
SCIj,SCIi,
SCIh
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
I2C Mode Register 2
8
8
SCIj,SCIi,
SCIh
I2C Mode Register 3
8
8
SCIj,SCIi,
SCIh
I2C Status Register
8
8
SCIj,SCIi,
SCIh
SPI Mode Register
SPMR
TDRH
TDRL
TDRHL
RDRH
RDRL
RDRHL
MDDR
DCCR
CDR.H
CDR.L
CDR
8
8
SCIj,SCIi,
SCIh
Transmit Data Register H
Transmit Data Register L
Transmit Data Register HL
Receive Data Register H
Receive Data Register L
Receive Data Register HL
Modulation Duty Register
Data Comparison Control Register
Comparison Data Register H
Comparison Data Register L
Comparison Data Register
Serial Port Register
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
8
SCIj,SCIi,
SCIh
SPTR
SMR
SCIj,SCIi,
SCIh
Serial Mode Register
8
8
SCIj,SCIi,
SCIh
Serial Mode Register
SMR
8
8
SCIj,SCIi,
SCIh
Bit Rate Register
BRR
8
8
SCIj,SCIi,
SCIh
Serial Control Register
Serial Control Register
Transmit Data Register
Serial Status Register
SCR
8
8
SCIj, SCIi,
SCIh
SCR
8
8
SCIj,SCIi,
SCIh
TDR
8
8
SCIj,SCIi,
SCIh
SSR
8
8
SCIj, SCIi,
SCIh
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 92 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (20 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 A124h
SMCI9
SCI9
SMCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
SCI9
Serial Status Register
SSR
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj,SCIi,
SCIh
0008 A125h
0008 A126h
0008 A127h
0008 A128h
0008 A129h
0008 A12Ah
0008 A12Bh
0008 A12Ch
0008 A12Dh
0008 A12Eh
0008 A12Fh
0008 A12Eh
0008 A130h
0008 A131h
0008 A130h
0008 A132h
0008 A133h
0008 A13Ah
0008 A13Bh
0008 A13Ah
0008 A13Ch
Receive Data Register
RDR
8
8
SCIj,SCIi,
SCIh
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
I2C Mode Register 1
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
I2C Mode Register 2
8
8
SCIj,SCIi,
SCIh
I2C Mode Register 3
8
8
SCIj,SCIi,
SCIh
I2C Status Register
8
8
SCIj,SCIi,
SCIh
SPI Mode Register
SPMR
TDRH
TDRL
TDRHL
RDRH
RDRL
RDRHL
MDDR
DCCR
CDR.H
CDR.L
CDR
8
8
SCIj,SCIi,
SCIh
Transmit Data Register H
Transmit Data Register L
Transmit Data Register HL
Receive Data Register H
Receive Data Register L
Receive Data Register HL
Modulation Duty Register
Data Comparison Control Register
Comparison Data Register H
Comparison Data Register L
Comparison Data Register
Serial Port Register
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
8
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
8
SCIj,SCIi,
SCIh
SPTR
SCIj,SCIi,
SCIh
0008 B000h
0008 B001h
0008 B002h
0008 B003h
0008 B004h
0008 B006h
0008 B008h
0008 B00Ah
0008 B080h
0008 B082h
0008 B084h
0008 B100h
0008 B101h
0008 B104h
0008 B105h
CAC
CAC
CAC
CAC
CAC
CAC
CAC
CAC
DOC
DOC
DOC
ELC
ELC
ELC
ELC
CAC Control Register 0
CACR0
CACR1
CACR2
CAICR
CASTR
CAULVR
CALLVR
CACNTBR
DOCR
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
CAC
CAC
CAC
CAC
CAC
CAC
CAC
CAC
DOC
DOC
DOC
ELC
ELC
ELC
ELC
CAC Control Register 1
CAC Control Register 2
8
8
CAC Interrupt Request Enable Register
CAC Status Register
8
8
8
8
CAC Upper-Limit Value Setting Register
CAC Lower-Limit Value Setting Register
CAC Counter Buffer Register
DOC Control Register
16
16
16
8
16
16
16
8
DOC Data Input Register
DODIR
DODSR
ELCR
16
16
8
16
16
8
DOC Data Setting Register
Event Link Control Register
Event Link Setting Register 0
Event Link Setting Register 3
Event Link Setting Register 4
ELSR0
ELSR3
ELSR4
8
8
8
8
8
8
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 93 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (21 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 B108h
0008 B10Bh
0008 B10Ch
0008 B10Dh
0008 B10Eh
0008 B110h
0008 B111h
0008 B113h
0008 B114h
0008 B115h
0008 B116h
0008 B117h
0008 B118h
0008 B119h
0008 B11Ah
0008 B11Bh
0008 B11Ch
0008 B11Dh
0008 B11Fh
0008 B120h
0008 B121h
0008 B122h
0008 B123h
0008 B124h
0008 B125h
0008 B126h
0008 B127h
0008 B128h
0008 B129h
0008 B12Ah
0008 B12Bh
0008 B12Ch
0008 B12Dh
0008 B12Eh
0008 B12Fh
0008 B13Dh
0008 B13Eh
0008 B144h
0008 B145h
0008 B146h
0008 B147h
0008 B148h
0008 B149h
0008 B14Ah
0008 B14Bh
0008 B14Ch
0008 B14Dh
0008 B14Eh
0008 B14Fh
0008 B150h
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
Event Link Setting Register 7
ELSR7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
Event Link Setting Register 10
Event Link Setting Register 11
Event Link Setting Register 12
Event Link Setting Register 13
Event Link Setting Register 15
Event Link Setting Register 16
Event Link Setting Register 18
Event Link Setting Register 19
Event Link Setting Register 20
Event Link Setting Register 21
Event Link Setting Register 22
Event Link Setting Register 23
Event Link Setting Register 24
Event Link Setting Register 25
Event Link Setting Register 26
Event Link Setting Register 27
Event Link Setting Register 28
Event Link Option Setting Register A
Event Link Option Setting Register B
Event Link Option Setting Register C
Event Link Option Setting Register D
Port Group Setting Register 1
Port Group Setting Register 2
Port Group Control Register 1
Port Group Control Register 2
Port Buffer Register 1
ELSR10
ELSR11
ELSR12
ELSR13
ELSR15
ELSR16
ELSR18
ELSR19
ELSR20
ELSR21
ELSR22
ELSR23
ELSR24
ELSR25
ELSR26
ELSR27
ELSR28
ELOPA
ELOPB
ELOPC
ELOPD
PGR1
PGR2
PGC1
PGC2
PDBF1
PDBF2
PEL0
Port Buffer Register 2
Event Link Port Setting Register 0
Event Link Port Setting Register 1
Event Link Port Setting Register 2
Event Link Port Setting Register 3
Event Link Software Event Generation Register
Event Link Setting Register 30
Event Link Setting Register 31
Event Link Setting Register 45
Event Link Option Setting Register E
Event Link Setting Register 46
Event Link Setting Register 47
Event Link Setting Register 48
Event Link Setting Register 49
Event Link Setting Register 50
Event Link Setting Register 51
Event Link Setting Register 52
Event Link Setting Register 53
Event Link Setting Register 54
Event Link Setting Register 55
Event Link Setting Register 56
Event Link Setting Register 57
Event Link Setting Register 58
PEL1
PEL2
PEL3
ELSEGR
ELSR30
ELSR31
ELSR45
ELOPE
ELSR46
ELSR47
ELSR48
ELSR49
ELSR50
ELSR51
ELSR52
ELSR53
ELSR54
ELSR55
ELSR56
ELSR57
ELSR58
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 94 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (22 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 B300h
SCI12 Serial Mode Register
SMR
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
8
8
16
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 to 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj,SCIi,
SCIh
0008 B300h
0008 B301h
0008 B302h
0008 B302h
0008 B303h
0008 B304h
0008 B304h
0008 B305h
0008 B306h
0008 B307h
0008 B308h
0008 B309h
0008 B30Ah
0008 B30Bh
0008 B30Ch
0008 B30Dh
0008 B30Eh
0008 B30Fh
0008 B30Eh
0008 B310h
0008 B311h
0008 B310h
0008 B312h
0008 B320h
0008 B321h
0008 B322h
0008 B323h
0008 B324h
0008 B325h
0008 B326h
SMCI12 Serial Mode Register
SMR
8
SCIj,SCIi,
SCIh
SCI12
SCI12
Bit Rate Register
BRR
8
SCIj,SCIi,
SCIh
Serial Control Register
SCR
8
SCIj,SCIi,
SCIh
SMCI12 Serial Control Register
SCR
8
SCIj,SCIi,
SCIh
SCI12
SCI12
Transmit Data Register
Serial Status Register
TDR
8
SCIj, SCIi,
SCIh
SSR
8
SCIj,SCIi,
SCIh
SMCI12 Serial Status Register
SSR
8
SCIj,SCIi,
SCIh
SCI12
Receive Data Register
RDR
8
SCIj,SCIi,
SCIh
SMCI12 Smart Card Mode Register
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
SPMR
TDRH
TDRL
TDRHL
RDRH
RDRL
RDRHL
MDDR
ESMER
CR0
8
SCIj,SCIi,
SCIh
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
Serial Extended Mode Register
Noise Filter Setting Register
8
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
2
I C Mode Register 1
8
SCIj,SCIi,
SCIh
2
I C Mode Register 2
8
SCIj,SCIi,
SCIh
2
I C Mode Register 3
8
SCIj,SCIi,
SCIh
2
I C Status Register
8
SCIj,SCIi,
SCIh
SPI Mode Register
8
SCIj,SCIi,
SCIh
Transmit Data Register H
Transmit Data Register L
Transmit Data Register HL
Receive Data Register H
Receive Data Register L
Receive Data Register HL
Modulation Duty Register
Extended Serial Module Enable Register
Control Register 0
8
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8, 16
8
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8, 16
8
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
Control Register 1
CR1
8
SCIj,SCIi,
SCIh
Control Register 2
CR2
8
SCIj,SCIi,
SCIh
Control Register 3
CR3
8
SCIj,SCIi,
SCIh
Port Control Register
PCR
8
SCIj, SCIi,
SCIh
Interrupt Control Register
ICR
8
SCIj,SCIi,
SCIh
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 95 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (23 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 B327h
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
Status Register
STR
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj,SCIi,
SCIh
0008 B328h
0008 B329h
0008 B32Ah
0008 B32Bh
0008 B32Ch
0008 B32Dh
0008 B32Eh
0008 B32Fh
0008 B330h
0008 B331h
0008 B332h
0008 B333h
Status Clear Register
STCR
SCIj, SCIi,
SCIh
Control Field 0 Data Register
Control Field 0 Compare Enable Register
Control Field 0 Receive Data Register
Primary Control Field 1 Data Register
Secondary Control Field 1 Data Register
Control Field 1 Compare Enable Register
Control Field 1 Receive Data Register
Timer Control Register
CF0DR
CF0CR
CF0RR
PCF1DR
SCF1DR
CF1CR
CF1RR
TCR
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
Timer Mode Register
TMR
SCIj,SCIi,
SCIh
Timer Prescaler Register
TPRE
SCIj,SCIi,
SCIh
Timer Count Register
TCNT
SCIj,SCIi,
SCIh
0008 C000h
0008 C001h
0008 C002h
0008 C003h
0008 C004h
0008 C005h
0008 C006h
0008 C007h
0008 C008h
0008 C009h
0008 C00Ah
0008 C00Bh
0008 C00Ch
0008 C00Dh
0008 C00Eh
0008 C00Fh
0008 C010h
0008 C011h
0008 C013h
0008 C020h
0008 C021h
0008 C022h
0008 C023h
0008 C024h
0008 C025h
0008 C026h
0008 C027h
0008 C028h
0008 C029h
PORT0 Port Direction Register
PORT1 Port Direction Register
PORT2 Port Direction Register
PORT3 Port Direction Register
PORT4 Port Direction Register
PORT5 Port Direction Register
PORT6 Port Direction Register
PORT7 Port Direction Register
PORT8 Port Direction Register
PORT9 Port Direction Register
PORTA Port Direction Register
PORTB Port Direction Register
PORTC Port Direction Register
PORTD Port Direction Register
PORTE Port Direction Register
PORTF Port Direction Register
PORTG Port Direction Register
PORTH Port Direction Register
PORTK Port Direction Register
PORT0 Port Output Data Register
PORT1 Port Output Data Register
PORT2 Port Output Data Register
PORT3 Port Output Data Register
PORT4 Port Output Data Register
PORT5 Port Output Data Register
PORT6 Port Output Data Register
PORT7 Port Output Data Register
PORT8 Port Output Data Register
PORT9 Port Output Data Register
PDR
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 96 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (24 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PIDR
PMR
ICLK ≥ PCLK ICLK < PCLK Function
0008 C02Ah
0008 C02Bh
0008 C02Ch
0008 C02Dh
0008 C02Eh
0008 C02Fh
0008 C030h
0008 C031h
0008 C033h
0008 C040h
0008 C041h
0008 C042h
0008 C043h
0008 C044h
0008 C045h
0008 C046h
0008 C047h
0008 C048h
0008 C049h
0008 C04Ah
0008 C04Bh
0008 C04Ch
0008 C04Dh
0008 C04Eh
0008 C04Fh
0008 C050h
0008 C051h
0008 C053h
0008 C060h
0008 C061h
0008 C062h
0008 C063h
0008 C064h
0008 C065h
0008 C066h
0008 C067h
0008 C068h
0008 C069h
0008 C06Ah
0008 C06Bh
0008 C06Ch
0008 C06Dh
0008 C06Eh
0008 C06Fh
0008 C070h
0008 C071h
0008 C073h
0008 C080h
0008 C082h
0008 C083h
PORTA Port Output Data Register
PORTB Port Output Data Register
PORTC Port Output Data Register
PORTD Port Output Data Register
PORTE Port Output Data Register
PORTF Port Output Data Register
PORTG Port Output Data Register
PORTH Port Output Data Register
PORTK Port Output Data Register
PORT0 Port Input Register
PORT1 Port Input Register
PORT2 Port Input Register
PORT3 Port Input Register
PORT4 Port Input Register
PORT5 Port Input Register
PORT6 Port Input Register
PORT7 Port Input Register
PORT8 Port Input Register
PORT9 Port Input Register
PORTA Port Input Register
PORTB Port Input Register
PORTC Port Input Register
PORTD Port Input Register
PORTE Port Input Register
PORTF Port Input Register
PORTG Port Input Register
PORTH Port Input Register
PORTK Port Input Register
PORT0 Port Mode Register
PORT1 Port Mode Register
PORT2 Port Mode Register
PORT3 Port Mode Register
PORT4 Port Mode Register
PORT5 Port Mode Register
PORT6 Port Mode Register
PORT7 Port Mode Register
PORT8 Port Mode Register
PORT9 Port Mode Register
PORTA Port Mode Register
PORTB Port Mode Register
PORTC Port Mode Register
PORTD Port Mode Register
PORTE Port Mode Register
PORTF Port Mode Register
PORTG Port Mode Register
PORTH Port Mode Register
PORTK Port Mode Register
PORT0 Open-Drain Control Register 0
PORT1 Open-Drain Control Register 0
PORT1 Open-Drain Control Register 1
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
PMR
ODR0
ODR0
ODR1
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 97 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (25 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR1
ODR0
ODR0
ODR0
ODR1
ODR0
PCR
ICLK ≥ PCLK ICLK < PCLK Function
0008 C084h
0008 C085h
0008 C086h
0008 C087h
0008 C088h
0008 C089h
0008 C08Ah
0008 C08Bh
0008 C08Ch
0008 C08Dh
0008 C08Eh
0008 C08Fh
0008 C090h
0008 C092h
0008 C093h
0008 C094h
0008 C095h
0008 C096h
0008 C097h
0008 C098h
0008 C099h
0008 C09Ah
0008 C09Bh
0008 C09Ch
0008 C09Dh
0008 C09Eh
0008 C0A0h
0008 C0A2h
0008 C0A3h
0008 C0A6h
0008 C0C0h
0008 C0C1h
0008 C0C2h
0008 C0C3h
0008 C0C4h
0008 C0C5h
0008 C0C6h
0008 C0C7h
0008 C0C8h
0008 C0C9h
0008 C0CAh
0008 C0CBh
0008 C0CCh
0008 C0CDh
0008 C0CEh
0008 C0CFh
0008 C0D0h
0008 C0D1h
0008 C0D3h
0008 C0E0h
PORT2 Open-Drain Control Register 0
PORT2 Open-Drain Control Register 1
PORT3 Open-Drain Control Register 0
PORT3 Open-Drain Control Register 1
PORT4 Open-Drain Control Register 0
PORT4 Open-Drain Control Register 1
PORT5 Open-Drain Control Register 0
PORT5 Open-Drain Control Register 1
PORT6 Open-Drain Control Register 0
PORT6 Open-Drain Control Register 1
PORT7 Open-Drain Control Register 0
PORT7 Open-Drain Control Register 1
PORT8 Open-Drain Control Register 0
PORT9 Open-Drain Control Register 0
PORT9 Open-Drain Control Register 1
PORTA Open-Drain Control Register 0
PORTA Open-Drain Control Register 1
PORTB Open-Drain Control Register 0
PORTB Open-Drain Control Register 1
PORTC Open-Drain Control Register 0
PORTC Open-Drain Control Register 1
PORTD Open-Drain Control Register 0
PORTD Open-Drain Control Register 1
PORTE Open-Drain Control Register 0
PORTE Open-Drain Control Register 1
PORTF Open-Drain Control Register 0
PORTG Open-Drain Control Register 0
PORTH Open-Drain Control Register 0
PORTH Open-Drain Control Register 1
PORTK Open-Drain Control Register 0
PORT0 Pull-Up Resistor Control Register
PORT1 Pull-Up Resistor Control Register
PORT2 Pull-Up Resistor Control Register
PORT3 Pull-Up Resistor Control Register
PORT4 Pull-Up Resistor Control Register
PORT5 Pull-Up Resistor Control Register
PORT6 Pull-Up Resistor Control Register
PORT7 Pull-Up Resistor Control Register
PORT8 Pull-Up Resistor Control Register
PORT9 Pull-Up Resistor Control Register
PORTA Pull-Up Resistor Control Register
PORTB Pull-Up Resistor Control Register
PORTC Pull-Up Resistor Control Register
PORTD Pull-Up Resistor Control Register
PORTE Pull-Up Resistor Control Register
PORTF Pull-Up Resistor Control Register
PORTG Pull-Up Resistor Control Register
PORTH Pull-Up Resistor Control Register
PORTK Pull-Up Resistor Control Register
PORT0 Drive Capacity Control Register
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
DSCR
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 98 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (26 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 C0E1h
0008 C0E2h
0008 C0E3h
0008 C0E7h
0008 C0E8h
0008 C0E9h
0008 C0EAh
0008 C0EBh
0008 C0ECh
0008 C0EDh
0008 C0EEh
0008 C0EFh
0008 C0F0h
0008 C0F3h
0008 C100h
0008 C102h
0008 C104h
0008 C105h
0008 C106h
0008 C107h
0008 C108h
0008 C109h
0008 C10Ah
0008 C11Fh
0008 C12Fh
0008 C130h
0008 C131h
0008 C133h
0008 C135h
0008 C140h
0008 C141h
0008 C148h
0008 C149h
0008 C14Ah
0008 C14Bh
0008 C14Ch
0008 C14Dh
0008 C14Eh
0008 C14Fh
0008 C150h
0008 C151h
0008 C152h
0008 C153h
0008 C154h
0008 C155h
0008 C156h
0008 C157h
0008 C158h
0008 C159h
0008 C15Ah
PORT1 Drive Capacity Control Register
PORT2 Drive Capacity Control Register
PORT3 Drive Capacity Control Register
PORT7 Drive Capacity Control Register
PORT8 Drive Capacity Control Register
PORT9 Drive Capacity Control Register
PORTA Drive Capacity Control Register
PORTB Drive Capacity Control Register
PORTC Drive Capacity Control Register
PORTD Drive Capacity Control Register
PORTE Drive Capacity Control Register
PORTF Drive Capacity Control Register
PORTG Drive Capacity Control Register
PORTK Drive Capacity Control Register
DSCR
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
MPC
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
DSCR
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
CS Output Enable Register
PFCSE
PFCSS0
PFAOE0
PFAOE1
PFBCR0
PFBCR1
PFBCR2
PFBCR3
PFBCR4
PWPR
CS Output Pin Select Register 0
Address Output Enable Register 0
Address Output Enable Register 1
External Bus Control Register 0
External Bus Control Register 1
External Bus Control Register 2
External Bus Control Register 3
External Bus Control Register 4
Write-Protect Register
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
PORT7 Drive Capacity Control Register 2
PORT8 Drive Capacity Control Register 2
PORT9 Drive Capacity Control Register 2
PORTB Drive Capacity Control Register 2
PORTD Drive Capacity Control Register 2
DSCR2
DSCR2
DSCR2
DSCR2
DSCR2
P00PFS
P01PFS
P10PFS
P11PFS
P12PFS
P13PFS
P14PFS
P15PFS
P16PFS
P17PFS
P20PFS
P21PFS
P22PFS
P23PFS
P24PFS
P25PFS
P26PFS
P27PFS
P30PFS
P31PFS
P32PFS
I/O Ports
I/O Ports
I/O Ports
I/O Ports
I/O Ports
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
P00 Pin Function Control Register
P01 Pin Function Control Register
P10 Pin Function Control Register
P11 Pin Function Control Register
P12 Pin Function Control Register
P13 Pin Function Control Register
P14 Pin Function Control Register
P15 Pin Function Control Register
P16 Pin Function Control Register
P17 Pin Function Control Register
P20 Pin Function Control Register
P21 Pin Function Control Register
P22 Pin Function Control Register
P23 Pin Function Control Register
P24 Pin Function Control Register
P25 Pin Function Control Register
P26 Pin Function Control Register
P27 Pin Function Control Register
P30 Pin Function Control Register
P31 Pin Function Control Register
P32 Pin Function Control Register
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 99 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (27 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
P33PFS
P34PFS
P35PFS
P40PFS
P41PFS
P42PFS
P43PFS
P44PFS
P45PFS
P46PFS
P47PFS
P50PFS
P51PFS
P52PFS
P53PFS
P54PFS
P55PFS
P60PFS
P61PFS
P62PFS
P63PFS
P64PFS
P65PFS
P70PFS
P71PFS
P72PFS
P73PFS
P74PFS
P75PFS
P76PFS
P80PFS
P81PFS
P82PFS
P90PFS
P91PFS
P92PFS
P93PFS
P94PFS
P95PFS
P96PFS
PA0PFS
PA1PFS
PA2PFS
PA3PFS
PA4PFS
PA5PFS
PA6PFS
PA7PFS
PB0PFS
PB1PFS
ICLK ≥ PCLK ICLK < PCLK Function
0008 C15Bh
0008 C15Ch
0008 C15Dh
0008 C160h
0008 C161h
0008 C162h
0008 C163h
0008 C164h
0008 C165h
0008 C166h
0008 C167h
0008 C168h
0008 C169h
0008 C16Ah
0008 C16Bh
0008 C16Ch
0008 C16Dh
0008 C170h
0008 C171h
0008 C172h
0008 C173h
0008 C174h
0008 C175h
0008 C178h
0008 C179h
0008 C17Ah
0008 C17Bh
0008 C17Ch
0008 C17Dh
0008 C17Eh
0008 C180h
0008 C181h
0008 C182h
0008 C188h
0008 C189h
0008 C18Ah
0008 C18Bh
0008 C18Ch
0008 C18Dh
0008 C18Eh
0008 C190h
0008 C191h
0008 C192h
0008 C193h
0008 C194h
0008 C195h
0008 C196h
0008 C197h
0008 C198h
0008 C199h
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
P33 Pin Function Control Register
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
P34 Pin Function Control Register
P35 Pin Function Control Register
P40 Pin Function Control Register
P41 Pin Function Control Register
P42 Pin Function Control Register
P43 Pin Function Control Register
P44 Pin Function Control Register
P45 Pin Function Control Register
P46 Pin Function Control Register
P47 Pin Function Control Register
P50 Pin Function Control Register
P51 Pin Function Control Register
P52 Pin Function Control Register
P53 Pin Function Control Register
P54 Pin Function Control Register
P55 Pin Function Control Register
P60 Pin Function Control Register
P61 Pin Function Control Register
P62 Pin Function Control Register
P61 Pin Function Control Register
P61 Pin Function Control Register
P61 Pin Function Control Register
P70 Pin Function Control Register
P71 Pin Function Control Register
P72 Pin Function Control Register
P73 Pin Function Control Register
P74 Pin Function Control Register
P75 Pin Function Control Register
P76 Pin Function Control Register
P80 Pin Function Control Register
P81 Pin Function Control Register
P82 Pin Function Control Register
P90 Pin Function Control Register
P91 Pin Function Control Register
P92 Pin Function Control Register
P93 Pin Function Control Register
P94 Pin Function Control Register
P95 Pin Function Control Register
P96 Pin Function Control Register
PA0 Pin Function Control Register
PA1 Pin Function Control Register
PA2 Pin Function Control Register
PA3 Pin Function Control Register
PA4 Pin Function Control Register
PA5 Pin Function Control Register
PA6 Pin Function Control Register
PA7 Pin Function Control Register
PB0 Pin Function Control Register
PB1 Pin Function Control Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 100 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (28 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
PB2PFS
PB3PFS
PB4PFS
PB5PFS
PB6PFS
PB7PFS
PC0PFS
PC1PFS
PC2PFS
PC3PFS
PC4PFS
PC5PFS
PC6PFS
PD0PFS
PD1PFS
PD2PFS
PD3PFS
PD4PFS
PD5PFS
PD6PFS
PD7PFS
PE0PFS
PE1PFS
PE2PFS
PE3PFS
PE4PFS
PE5PFS
PE6PFS
PF0PFS
PF1PFS
PF2PFS
PF3PFS
PG0PFS
PG1PFS
PG2PFS
PH0PFS
PH1PFS
PH2PFS
PH3PFS
PH4PFS
PH5PFS
PH6PFS
PH7PFS
PK0PFS
PK1PFS
PK2PFS
DPSBYCR
ICLK ≥ PCLK ICLK < PCLK Function
0008 C19Ah
0008 C19Bh
0008 C19Ch
0008 C19Dh
0008 C19Eh
0008 C19Fh
0008 C1A0h
0008 C1A1h
0008 C1A2h
0008 C1A3h
0008 C1A4h
0008 C1A5h
0008 C1A6h
0008 C1A8h
0008 C1A9h
0008 C1AAh
0008 C1ABh
0008 C1ACh
0008 C1ADh
0008 C1AEh
0008 C1AFh
0008 C1B0h
0008 C1B1h
0008 C1B2h
0008 C1B3h
0008 C1B4h
0008 C1B5h
0008 C1B6h
0008 C1B8h
0008 C1B9h
0008 C1BAh
0008 C1BBh
0008 C1C0h
0008 C1C1h
0008 C1C2h
0008 C1C8h
0008 C1C9h
0008 C1CAh
0008 C1CBh
0008 C1CCh
0008 C1CDh
0008 C1CEh
0008 C1CFh
0008 C1D8h
0008 C1D9h
0008 C1DAh
0008 C280h
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
PB2 Pin Function Control Register
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
4, 5 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2, 3 ICLK
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
PB3 Pin Function Control Register
PB4 Pin Function Control Register
PB5 Pin Function Control Register
PB6 Pin Function Control Register
PB7 Pin Function Control Register
PC0 Pin Function Control Register
PC1 Pin Function Control Register
PC2 Pin Function Control Register
PC3 Pin Function Control Register
PC4 Pin Function Control Register
PC5 Pin Function Control Register
PC6 Pin Function Control Register
PD0 Pin Function Control Register
PD1 Pin Function Control Register
PD2 Pin Function Control Register
PD3 Pin Function Control Register
PD4 Pin Function Control Register
PD5 Pin Function Control Register
PD6 Pin Function Control Register
PD7 Pin Function Control Register
PE0 Pin Function Control Register
PE1 Pin Function Control Register
PE2 Pin Function Control Register
PE3 Pin Function Control Register
PE4 Pin Function Control Register
PE5 Pin Function Control Register
PE6 Pin Function Control Register
PF0 Pin Function Control Register
PF1 Pin Function Control Register
PF2 Pin Function Control Register
PF3 Pin Function Control Register
PG0 Pin Function Control Register
PG1 Pin Function Control Register
PG2 Pin Function Control Register
PH0 Pin Function Control Register
PH1 Pin Function Control Register
PH2 Pin Function Control Register
PH3 Pin Function Control Register
PH4 Pin Function Control Register
PH5 Pin Function Control Register
PH6 Pin Function Control Register
PH7 Pin Function Control Register
PK0 Pin Function Control Register
PK1 Pin Function Control Register
PK2 Pin Function Control Register
SYSTE Deep Standby Control Register
M
Low
Power
Consumpt
ion
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 101 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (29 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0008 C282h
SYSTE Deep Standby Interrupt Enable Register 0
M
DPSIER0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
Low
Power
Consumpt
ion
0008 C283h
0008 C284h
0008 C286h
0008 C287h
0008 C288h
0008 C28Ah
0008 C28Bh
0008 C28Ch
SYSTE Deep Standby Interrupt Enable Register 1
M
DPSIER1
DPSIER2
DPSIFR0
DPSIFR1
DPSIFR2
DPSIEGR0
DPSIEGR1
DPSIEGR2
Low
Power
Consumpt
ion
SYSTE Deep Standby Interrupt Enable Register 2
M
Low
Power
Consumpt
ion
SYSTE Deep Standby Interrupt Flag Register 0
M
Low
Power
Consumpt
ion
SYSTE Deep Standby Interrupt Flag Register 1
M
Low
Power
Consumpt
ion
SYSTE Deep Standby Interrupt Flag Register 2
M
Low
Power
Consumpt
ion
SYSTE Deep Standby Interrupt Edge Register 0
M
Low
Power
Consumpt
ion
SYSTE Deep Standby Interrupt Edge Register 1
M
Low
Power
Consumpt
ion
SYSTE Deep Standby Interrupt Edge Register 2
M
Low
Power
Consumpt
ion
0008 C290h
0008 C291h
0008 C293h
SYSTE Reset Status Register 0
M
RSTSR0
RSTSR1
MOFCR
8
8
8
8
8
8
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
Resets
SYSTE Reset Status Register 1
M
Resets
SYSTE Main Clock Oscillator Function Control Register
M
Clock
Generatio
n Circuit
0008 C294h
0008 C295h
SYSTE High-Speed On-Chip Oscillator Power Supply Control
HOCOPCR
VOLSR
8
8
8
8
4, 5 PCLKB
4, 5 PCLKB
2, 3 ICLK
2, 3 ICLK
Clock
Generatio
n Circuit
M
Register
SYSTE Voltage Level Setting Register
M
Operating
Modes
0008 C296h
0008 C297h
FLASH Flash P/E Protect Register
FWEPROR
LVCMPCR
8
8
8
8
4, 5 PCLKB
4, 5 PCLKB
2, 3 ICLK
2, 3 ICLK
Flash
LVDA
SYSTE Voltage Monitoring Circuit Control Register
M
0008 C298h
0008 C29Ah
0008 C29Bh
SYSTE Voltage Detection Level Select Register
M
LVDLVLR
LVD1CR0
LVD2CR0
8
8
8
8
8
8
8
8
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
4, 5 PCLKB
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
LVDA
LVDA
LVDA
SYSTE Voltage Monitoring 1 Circuit Control Register 0
M
SYSTE Voltage Monitoring 2 Circuit Control Register 0
M
0008 C2A0h to SYSTE Deep Standby Backup Register 0 to Deep Standby
0008 C2BFh
DPSBKR0 to
DPSBKR31
Low
M
Backup Register 31
Power
Consumpt
ion
0009 0200h to CAN0
0009 03FFh
Mailbox Register 0 to Mailbox Register 31
Mask Register 0 to Mask Register 7
MB0 to MB31
128
32
8, 16,
32*
2, 3 PCLKB
2 ICLK
2 ICLK
CAN
2
0009 0400h to CAN0
0009 041Fh
MKR0 to
MKR7
8, 16, 32 2, 3 PCLKB
CAN
0009 0420h
0009 0424h
0009 0428h
CAN0
CAN0
CAN0
FIFO Received ID Compare Register 0
FIFO Received ID Compare Register 1
Mask Invalid Register
FIDCR0
FIDCR1
MKIVLR
32
32
32
8, 16, 32 2, 3 PCLKB
8, 16, 32 2, 3 PCLKB
8, 16, 32 2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
CAN
CAN
CAN
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 102 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (30 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0009 042Ch
CAN0 Mailbox Interrupt Enable Register
MIER
32
8
8, 16, 32 2, 3 PCLKB
2 ICLK
2 ICLK
CAN
CAN
0009 0820h to CAN0
0009 083Fh
Message Control Register 0 to Message Control Register MCTL0 to
31
8
2, 3 PCLKB
MCTL31
CTLR
STR
0009 0840h
0009 0842h
0009 0844h
0009 0848h
0009 0849h
0009 084Ah
0009 084Bh
0009 084Ch
0009 084Dh
0009 084Eh
0009 084Fh
0009 0850h
0009 0851h
0009 0852h
0009 0853h
0009 0854h
0009 0856h
0009 0858h
0009 E000h
0009 E040h
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
POEG
POEG
Control Register
16
16
32
8
8, 16
8, 16
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
POEG
POEG
Status Register
Bit Configuration Register
Receive FIFO Control Register
Receive FIFO Pointer Control Register
Transmit FIFO Control Register
Transmit FIFO Pointer Control Register
Error Interrupt Enable Register
Error Interrupt Factor Judge Register
Receive Error Count Register
Transmit Error Count Register
Error Code Store Register
Channel Search Support Register
Mailbox Search Status Register
Mailbox Search Mode Register
Time Stamp Register
BCR
8, 16, 32 2, 3 PCLKB
RFCR
RFPCR
TFCR
TFPCR
EIER
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
8
8
8
8
8
8
8
EIFR
8
8
RECR
TECR
ECSR
CSSR
MSSR
MSMR
TSR
8
8
8
8
8
8
8
8
8
8
8
8
16
16
8
16
16
8
Acceptance Filter Support Register
Test Control Register
AFSR
TCR
POEG Group A Setting Register
POEGGA
32
16
32
16
GPTW Output Negate Control Group A writing Protection GTONCWPA
Register
0009 E044h
POEG
GPTW Output Negate Control Group A Controlling
Register
GTONCCRA
16
16
2, 3 PCLKB
2 ICLK
POEG
0009 E100h
0009 E140h
POEG
POEG
POEG Group B Setting Register
POEGGB
32
16
32
16
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
POEG
POEG
GPTW Output Negate Control Group B writing Protection GTONCWPB
Register
0009 E144h
POEG
GPTW Output Negate Control Group B Controlling
Register
GTONCCRB
16
16
2, 3 PCLKB
2 ICLK
POEG
0009 E200h
0009 E240h
POEG
POEG
POEG Group C Setting Register
POEGGC
32
16
32
16
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
POEG
POEG
GPTW Output Negate Control Group C writing Protection GTONCWPC
Register
0009 E244h
POEG
GPTW Output Negate Control Group C Controlling
Register
GTONCCRC
16
16
2, 3 PCLKB
2 ICLK
POEG
0009 E300h
0009 E340h
POEG
POEG
POEG Group D Setting Register
POEGGD
32
16
32
16
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
POEG
POEG
GPTW Output Negate Control Group D writing Protection GTONCWPD
Register
0009 E344h
POEG
GPTW Output Negate Control Group D Controlling
Register
GTONCCRD
16
16
2, 3 PCLKB
2 ICLK
POEG
0009 E400h
0009 E402h
0009 E404h
0009 E406h
0009 E408h
0009 E40Bh
0009 E40Ch
0009 E40Eh
0009 E410h
0009 E412h
0009 E414h
0009 E416h
0009 E418h
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
Input Level Control/Status Register 1
Output Level Control/Status Register 1
Input Level Control/Status Register 2
Output Level Control/Status Register 2
Input Level Control/Status Register 3
Port Output Enable Control Register 1
Port Output Enable Control Register 2
Port Output Enable Control Register 3
Port Output Enable Control Register 4
Port Output Enable Control Register 5
Port Output Enable Control Register 6
Input Level Control/Status Register 4
Input Level Control/Status Register 5
ICSR1
16
16
16
16
16
8
16
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
OCSR1
ICSR2
OCSR2
ICSR3
POECR1
POECR2
POECR3
POECR4
POECR5
POECR6
ICSR4
16
16
16
16
16
16
16
16
16
16
16
16
16
16
ICSR5
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 103 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (31 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0009 E41Ah
0009 E41Ch
0009 E41Eh
0009 E420h
0009 E422h
0009 E424h
0009 E426h
0009 E428h
0009 E42Ah
0009 E42Ch
0009 E42Eh
0009 E430h
0009 E432h
0009 E434h
0009 E436h
0009 E438h
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
Active Level Setting Register 1
ALR1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
Input Level Control/Status Register 6
Active Level Setting Register 2
ICSR6
ALR2
Input Level Control/Status Register 7
Port Output Enable Control Register 7
Port Output Enable Control Register 8
ICSR7
POECR7
POECR8
Port Output Enable Comparator Detection Flag Register POECMPFR
Port Output Enable Comparator Request Select Register POECMPSEL
Output Level Control/Status Register 3
Active Level Setting Register 3
OCSR3
ALR3
Software Port Output Enable Register
Port Mode Mask Control Register 0
Port Mode Mask Control Register 1
Port Mode Mask Control Register 2
Port Mode Mask Control Register 3
SPOER
PMMCR0
PMMCR1
PMMCR2
PMMCR3
POECMPEX0
Port Output Enable Comparator Request Extended
Select Register 0
0009 E439h
0009 E43Ah
0009 E43Bh
0009 E43Ch
0009 E43Dh
POE
POE
POE
POE
POE
Port Output Enable Comparator Request Extended
Select Register 1
POECMPEX1
POECMPEX2
POECMPEX3
POECMPEX4
POECMPEX5
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
POE3B
POE3B
POE3B
POE3B
POE3B
Port Output Enable Comparator Request Extended
Select Register 2
Port Output Enable Comparator Request Extended
Select Register 3
Port Output Enable Comparator Request Extended
Select Register 4
Port Output Enable Comparator Request Extended
Select Register 5
0009 E440h
0009 E442h
0009 E444h
0009 E446h
0009 E448h
0009 E44Ah
0009 E44Ch
0009 E44Eh
0009 E450h
0009 E452h
0009 E454h
0009 E456h
0009 E458h
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
Input Level Control/Status Register 8
Input Level Control/Status Register 9
Input Level Control/Status Register 10
Output Level Control/Status Register 4
Output Level Control/Status Register 5
Active Level Setting Register 4
ICSR8
16
16
16
16
16
16
16
16
16
16
16
16
8
16
16
16
16
16
16
16
16
16
16
16
16
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
ICSR9
ICSR10
OCSR4
OCSR5
ALR4
Active Level Setting Register 5
ALR5
Port Output Enable Control Register 4B
Port Output Enable Control Register 6B
Port Output Enable Control Register 9
Port Output Enable Control Register 10
Port Output Enable Control Register 11
POECR4B
POECR6B
POECR9
POECR10
POECR11
POECMPEX6
Port Output Enable Comparator Request Extended
Select Register 6
0009 E459h
0009 E45Ah
POE
POE
Port Output Enable Comparator Request Extended
Select Register 7
POECMPEX7
POECMPEX8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
POE3B
POE3B
Port Output Enable Comparator Request Extended
Select Register 8
0009 E460h
0009 E461h
0009 E462h
0009 E463h
0009 E464h
0009 E465h
0009 E466h
0009 E467h
0009 E468h
POE
POE
POE
POE
POE
POE
POE
POE
POE
MTU0 Pin Select Register 1
MTU0 Pin Select Register 2
MTU3 Pin Select Register
MTU4 Pin Select Register 1
MTU4 Pin Select Register 2
MTU6 Pin Select Register
MTU7 Pin Select Register 1
MTU7 Pin Select Register 2
MTU9 Pin Select Register 1
M0SELR1
M0SELR2
M3SELR
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
M4SELR1
M4SELR2
M6SELR
M7SELR1
M7SELR2
M9SELR1
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 104 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (32 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
0009 E469h
0009 E46Ah
0009 E46Bh
0009 E46Ch
0009 E46Dh
0009 E46Eh
0009 E46Fh
0009 E470h
0009 E471h
0009 E472h
0009 E473h
000A 0000h
000A 0004h
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
POE
USB0
USB0
MTU9 Pin Select Register 2
M9SELR2
G0SELR
G1SELR
G2SELR
G3SELR
G4SELR
G5SELR
G6SELR
G7SELR
G8SELR
G9SELR
SYSCFG
SYSSTS0
8
8
8
8
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
2, 3 PCLKB
3, 4 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
POE3B
USBb
GPTW0 Pin Select Register
GPTW1 Pin Select Register
GPTW2 Pin Select Register
GPTW3 Pin Select Register
GPTW4 Pin Select Register
GPTW5 Pin Select Register
GPTW6 Pin Select Register
GPTW7 Pin Select Register
GPTW8 Pin Select Register
GPTW9 Pin Select Register
System Configuration Control Register
System Configuration Status Register 0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
9 PCLKB
or more
Rounded up to USBb
the nearest
integer greater
than 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
000A 0008h
USB0
Device State Control Register 0
DVSTCTR0
16
16
9 PCLKB
or more
Rounded up to USBb
the nearest
integer greater
than 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
000A 0014h
000A 0018h
000A 001Ch
000A 0020h
000A 0022h
000A 0028h
000A 002Ah
000A 002Ch
000A 002Eh
000A 0030h
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
CFIFO Port Register
CFIFO
16
16
16
16
16
16
16
16
16
16
8, 16
8, 16
8, 16
16
3, 4 PCLKB
3, 4 PCLKB
3, 4 PCLKB
3, 4 PCLKB
3, 4 PCLKB
3, 4 PCLKB
3, 4 PCLKB
3, 4 PCLKB
3, 4 PCLKB
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
D0FIFO Port Register
D0FIFO
D1FIFO Port Register
D1FIFO
CFIFO Port Select Register
CFIFO Port Control Register
D0FIFO Port Select Register
D0FIFO Port Control Register
D1FIFO Port Select Register
D1FIFO Port Control Register
Interrupt Enable Register 0
CFIFOSEL
CFIFOCTR
D0FIFOSEL
D0FIFOCTR
D1FIFOSEL
D1FIFOCTR
INTENB0
16
16
16
16
16
16
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
000A 0032h
000A 0036h
000A 0038h
000A 003Ah
000A 003Ch
USB0
USB0
USB0
USB0
USB0
Interrupt Enable Register 1
INTENB1
BRDYENB
NRDYENB
BEMPENB
SOFCFG
16
16
16
16
16
16
16
16
16
16
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
USBb
USBb
USBb
USBb
USBb
ratio of ICLK/
1
PCLKB)*
BRDY Interrupt Enable Register
NRDY Interrupt Enable Register
BEMP Interrupt Enable Register
SOF Output Configuration Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 105 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (33 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000A 0040h
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
Interrupt Status Register 0
INTSTS0
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
ratio of ICLK/
1
PCLKB)*
000A 0042h
000A 0046h
000A 0048h
000A 004Ah
000A 004Ch
000A 0054h
000A 0056h
000A 0058h
000A 005Ah
000A 005Ch
000A 005Eh
000A 0060h
000A 0064h
000A 0068h
Interrupt Status Register 1
BRDY Interrupt Status Register
NRDY Interrupt Status Register
BEMP Interrupt Status Register
Frame Number Register
INTSTS1
BRDYSTS
NRDYSTS
BEMPSTS
FRMNUM
USBREQ
USBVAL
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
USB Request Type Register
USB Request Value Register
USB Request Index Register
USB Request Length Register
DCP Configuration Register
DCP Maximum Packet Size Register
DCP Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
USBINDX
USBLENG
DCPCFG
DCPMAXP
DCPCTR
PIPESEL
PIPECFG
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
Pipe Window Select Register
Pipe Configuration Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 106 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (34 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000A 006Ch
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
Pipe Maximum Packet Size Register
PIPEMAXP
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
ratio of ICLK/
1
PCLKB)*
000A 006Eh
000A 0070h
000A 0072h
000A 0074h
000A 0076h
000A 0078h
000A 007Ah
000A 007Ch
000A 007Eh
000A 0080h
000A 0090h
000A 0092h
000A 0094h
000A 0096h
Pipe Cycle Control Register
PIPE1 Control Register
PIPEPERI
PIPE1CTR
PIPE2CTR
PIPE3CTR
PIPE4CTR
PIPE5CTR
PIPE6CTR
PIPE7CTR
PIPE8CTR
PIPE9CTR
PIPE1TRE
PIPE1TRN
PIPE2TRE
PIPE2TRN
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE2 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE3 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE4 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE5 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE6 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE7 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE8 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
PIPE9 Control Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
Pipe1 Transaction Counter Enable Register
Pipe1 Transaction Counter Register
Pipe2 Transaction Counter Enable Register
Pipe2 Transaction Counter Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 107 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (35 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000A 0098h
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
Pipe3 Transaction Counter Enable Register
PIPE3TRE
16
16
16
16
16
16
16
16
16
16
16
16
32
16
16
16
16
16
16
16
16
16
16
16
16
32
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
USBb
ratio of ICLK/
1
PCLKB)*
000A 009Ah
000A 009Ch
000A 009Eh
000A 00A0h
000A 00A2h
000A 00D0h
000A 00D2h
000A 00D4h
000A 00D6h
000A 00D8h
000A 00DAh
000A 00F0h
Pipe3 Transaction Counter Register
PIPE3TRN
PIPE4TRE
PIPE4TRN
PIPE5TRE
PIPE5TRN
DEVADD0
DEVADD1
DEVADD2
DEVADD3
DEVADD4
DEVADD5
PHYSLEW
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
Pipe4 Transaction Counter Enable Register
Pipe4 Transaction Counter Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
Pipe5 Transaction Counter Enable Register
Pipe5 Transaction Counter Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
Device Address 0 Configuration Register
Device Address 1 Configuration Register
Device Address 2 Configuration Register
Device Address 3 Configuration Register
Device Address 4 Configuration Register
Device Address 5 Configuration Register
PHY Cross Point Adjustment Register
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
9 PCLKB
or more
Frequency
with 1 + 9 ×
(frequency
ratio of ICLK/
1
PCLKB)*
000A 0C80h
000A 0C84h
000A 0C88h
000A 0C8Ch
000A 0C90h
000A 0CA0h
000A 0CA4h
CMPC0 Comparator Control Register
CMPCTL
CMPSEL0
CMPSEL1
CMPMON
CMPIOC
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC0 Comparator Input Select Register
CMPC0 Comparator Reference Voltage Select Register
CMPC0 Comparator Output Monitor Register
CMPC0 Comparator External Output Enable Register
CMPC1 Comparator Control Register
CMPCTL
CMPSEL0
CMPC1 Comparator Input Select Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 108 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (36 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
CMPSEL1
CMPMON
CMPIOC
CMPCTL
CMPSEL0
CMPSEL1
CMPMON
CMPIOC
CMPCTL
CMPSEL0
CMPSEL1
CMPMON
CMPIOC
CMPCTL
CMPSEL0
CMPSEL1
CMPMON
CMPIOC
CMPCTL
CMPSEL0
CMPSEL1
CMPMON
CMPIOC
TCR
ICLK ≥ PCLK ICLK < PCLK Function
000A 0CA8h
000A 0CACh
000A 0CB0h
000A 0CC0h
000A 0CC4h
000A 0CC8h
000A 0CCCh
000A 0CD0h
000A 0CE0h
000A 0CE4h
000A 0CE8h
000A 0CECh
000A 0CF0h
000A 0D00h
000A 0D04h
000A 0D08h
000A 0D0Ch
000A 0D10h
000A 0D20h
000A 0D24h
000A 0D28h
000A 0D2Ch
000A 0D30h
000C 1200h
000C 1201h
000C 1202h
000C 1203h
000C 1204h
000C 1205h
000C 1206h
000C 1207h
000C 1208h
000C 1209h
000C 120Ah
000C 120Dh
000C 120Eh
000C 120Fh
000C 1210h
000C 1212h
000C 1214h
000C 1216h
000C 1218h
000C 121Ah
000C 121Ch
000C 121Eh
000C 1220h
000C 1222h
000C 1224h
000C 1226h
000C 1228h
CMPC1 Comparator Reference Voltage Select Register
CMPC1 Comparator Output Monitor Register
CMPC1 Comparator External Output Enable Register
CMPC2 Comparator Control Register
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 PCLKB
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
1, 2 ICLK
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
CMPC
8
8
CMPC2 Comparator Input Select Register
CMPC2 Comparator Reference Voltage Select Register
CMPC2 Comparator Output Monitor Register
CMPC2 Comparator External Output Enable Register
CMPC3 Comparator Control Register
8
8
8
8
8
CMPC3 Comparator Input Select Register
CMPC3 Comparator Reference Voltage Select Register
CMPC3 Comparator Output Monitor Register
CMPC3 Comparator External Output Enable Register
CMPC4 Comparator Control Register
8
8
8
8
8
CMPC4 Comparator Input Select Register
CMPC4 Comparator Reference Voltage Select Register
CMPC4 Comparator Output Monitor Register
CMPC4 Comparator External Output Enable Register
CMPC5 Comparator Control Register
8
8
8
8
8
CMPC5 Comparator Input Select Register
CMPC5 Comparator Reference Voltage Select Register
CMPC5 Comparator Output Monitor Register
CMPC5 Comparator External Output Enable Register
8
8
8
8
MTU3
MTU4
MTU3
MTU4
MTU3
MTU3
MTU4
MTU4
MTU3
MTU4
MTU
Timer Control Register
8
8, 16, 32 4 to 7 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
Timer Control Register
TCR
8
8
8, 16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
Timer Mode Register 1
TMDR1
TMDR1
TIORH
8
Timer Mode Register 1
8
Timer I/O Control Register H
Timer I/O Control Register L
Timer I/O Control Register H
Timer I/O Control Register L
Timer Interrupt Enable Register
Timer Interrupt Enable Register
Timer Output Master Enable Register A
Timer Gate Control Register A
Timer Output Control Register 1A
Timer Output Control Register 2A
Timer Counter
8
8, 16, 32 4 to 7 PCLKA
TIORL
8
8
8, 16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
TIORH
8
TIORL
8
TIER
8
8, 16
8
TIER
8
TOERA
TGCRA
TOCR1A
TOCR2A
TCNT
8
8
MTU
8
8
MTU
8
8, 16
8
MTU
8
MTU3
MTU4
MTU
16
16
16
16
16
16
16
16
16
16
16
16
16
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
Timer Counter
TCNT
Timer Cycle Data Register A
Timer Dead Time Data Register A
Timer General Register A
Timer General Register B
Timer General Register A
Timer General Register B
Timer Subcounter A
TCDRA
TDDRA
TGRA
MTU
MTU3
MTU3
MTU4
MTU4
MTU
TGRB
TGRA
TGRB
TCNTSA
TCBRA
TGRC
MTU
Timer Cycle Buffer Register A
Timer General Register C
Timer General Register D
Timer General Register C
MTU3
MTU3
MTU4
TGRD
TGRC
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 109 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (37 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 122Ah
000C 122Ch
000C 122Dh
000C 1230h
000C 1231h
000C 1232h
000C 1234h
000C 1236h
000C 1238h
000C 1239h
000C 123Ah
000C 123Bh
000C 123Ch
000C 1240h
000C 1244h
000C 1246h
000C 1248h
MTU4
MTU3
MTU4
MTU
Timer General Register D
TGRD
16
8
16
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
Timer Status Register
TSR
8, 16
Timer Status Register
TSR
8
8
Timer Interrupt Skipping Set Register 1A
Timer Interrupt Skipping Counter 1A
Timer Buffer Transfer Set Register A
Timer Dead Time Enable Register A
Timer Output Level Buffer Register A
Timer Buffer Operation Transfer Mode Register
Timer Buffer Operation Transfer Mode Register
Timer Interrupt Skipping Mode Register A
Timer Interrupt Skipping Set Register 2A
Timer Interrupt Skipping Counter 2A
Timer A/D Converter Start Request Control Register
TITCR1A
TITCNT1A
TBTERA
TDERA
TOLBRA
TBTM
8
8, 16
MTU
8
8
8
MTU
8
MTU
8
8
MTU
8
8
MTU3
MTU4
MTU
8
8, 16
8
TBTM
8
TITMRA
TITCR2A
TITCNT2A
TADCR
8
8
MTU
8
8
MTU
8
8
MTU4
MTU4
MTU4
MTU4
16
16
16
16
16
Timer A/D Converter Start Request Cycle Set Register A TADCORA
Timer A/D Converter Start Request Cycle Set Register B TADCORB
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
Timer A/D Converter Start Request Cycle Set Buffer
Register A
TADCOBRA
000C 124Ah
MTU4
Timer A/D Converter Start Request Cycle Set Buffer
Register B
TADCOBRB
16
16
4 to 7 PCLKA
2 to 4 ICLK MTU3d
000C 124Ch
000C 124Dh
000C 1260h
000C 1270h
000C 1272h
000C 1274h
000C 1276h
000C 1280h
000C 1281h
000C 1282h
000C 1284h
000C 1290h
000C 1291h
000C 1292h
000C 1293h
000C 1294h
000C 1296h
000C 1299h
000C 1300h
000C 1301h
000C 1302h
000C 1303h
000C 1304h
000C 1306h
000C 1308h
000C 130Ah
000C 130Ch
000C 130Eh
000C 1320h
000C 1322h
000C 1324h
MTU3
MTU4
MTU
Timer Control Register 2
TCR2
8
8
8
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
Timer Control Register 2
TCR2
Timer Waveform Control Register A
Timer Mode Register 2A
TWCRA
TMDR2A
TGRE
8
8
MTU
8
8
MTU3
MTU4
MTU4
MTU
Timer General Register E
Timer General Register E
Timer General Register F
Timer Start Register A
16
16
16
8
16
16
16
8, 16
8
TGRE
TGRF
TSTRA
TSYRA
TCSYSTR
TRWERA
NFCR0
NFCR1
NFCR2
NFCR3
NFCR4
NFCR9
NFCRC
TCR
MTU
Timer Synchronous Register A
Timer Counter Synchronous Start Register
Timer Read/Write Enable Register A
Noise Filter Control Register 0
Noise Filter Control Register 1
Noise Filter Control Register 2
Noise Filter Control Register 3
Noise Filter Control Register 4
Noise Filter Control Register 9
Noise Filter Control Register C
Timer Control Register
8
MTU
8
8
MTU
8
8
MTU0
MTU1
MTU2
MTU3
MTU4
MTU9
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
MTU0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8, 16, 32 4 to 7 PCLKA
Timer Mode Register 1
TMDR1
TIORH
TIORL
TIER
8
8
8, 16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
Timer I/O Control Register H
Timer I/O Control Register L
Timer Interrupt Enable Register
Timer Counter
8
8
8
8, 16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
TCNT
16
16
16
16
16
16
16
8
Timer General Register A
Timer General Register B
Timer General Register C
Timer General Register D
Timer General Register E
Timer General Register F
Timer Interrupt Enable Register 2
TGRA
TGRB
TGRC
TGRD
TGRE
TGRF
16
4 to 7 PCLKA
4 to 7 PCLKA
TIER2
8, 16
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 110 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (38 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
TBTM
TCR2
TCR
ICLK ≥ PCLK ICLK < PCLK Function
000C 1326h
000C 1328h
000C 1380h
000C 1381h
000C 1382h
000C 1384h
000C 1385h
000C 1386h
000C 1388h
000C 138Ah
000C 1390h
000C 1391h
000C 1394h
000C 13A0h
000C 13A4h
000C 13A8h
000C 1400h
000C 1401h
000C 1402h
000C 1404h
000C 1405h
000C 1406h
000C 1408h
000C 140Ah
000C 140Ch
000C 1580h
000C 1581h
000C 1582h
000C 1583h
000C 1584h
000C 1586h
000C 1588h
000C 158Ah
000C 158Ch
000C 158Eh
000C 15A0h
000C 15A2h
000C 15A4h
000C 15A6h
000C 15A8h
000C 1A00h
000C 1A01h
000C 1A02h
000C 1A03h
000C 1A04h
000C 1A05h
000C 1A06h
000C 1A07h
000C 1A08h
000C 1A09h
MTU0
MTU0
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU1
MTU2
MTU2
MTU2
MTU2
MTU2
MTU2
MTU2
MTU2
MTU2
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU9
MTU6
MTU7
MTU6
MTU7
MTU6
MTU6
MTU7
MTU7
MTU6
MTU7
Timer Buffer Operation Transfer Mode Register
8
8
8
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
Timer Control Register 2
Timer Control Register
8
8, 16
8
Timer Mode Register 1
TMDR1
TIOR
8
Timer I/O Control Register
Timer Interrupt Enable Register
Timer Status Register
8
8
TIER
8
8, 16, 32 4 to 7 PCLKA
TSR
8
8
4 to 7 PCLKA
4 to 7 PCLKA
Timer Counter
TCNT
TGRA
TGRB
TICCR
TMDR3
TCR2
TCNTLW
TGRALW
TGRBLW
TCR
16
16
16
8
16
Timer General Register A
Timer General Register B
Timer Input Capture Control Register
Timer Mode Register 3
16, 32 4 to 7 PCLKA
16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
8
8
Timer Control Register 2
Timer Longword Counter
Timer Longword General Register
Timer Longword General Register
Timer Control Register
8
8
32
32
32
8
32
32
32
8, 16
8
Timer Mode Register 1
TMDR1
TIOR
8
Timer I/O Control Register
Timer Interrupt Enable Register
Timer Status Register
8
8
TIER
8
8, 16, 32 4 to 7 PCLKA
TSR
8
8
4 to 7 PCLKA
4 to 7 PCLKA
Timer Counter
TCNT
TGRA
TGRB
TCR2
TCR
16
16
16
8
16
Timer General Register A
Timer General Register B
Timer Control Register 2
Timer Control Register
16, 32 4 to 7 PCLKA
16
8
4 to 7 PCLKA
4 to 7 PCLKA
8
8, 16, 32 4 to 7 PCLKA
Timer Mode Register 1
TMDR1
TIORH
TIORL
TIER
8
8
8, 16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
Timer I/O Control Register H
Timer I/O Control Register L
Timer Interrupt Enable Register
Timer Counter
8
8
8
8, 16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
TCNT
TGRA
TGRB
TGRC
TGRD
TGRE
TGRF
TIER2
TBTM
TCR2
TCR
16
16
16
16
16
16
16
8
Timer General Register A
Timer General Register B
Timer General Register C
Timer General Register D
Timer General Register E
Timer General Register F
Timer Interrupt Enable Register 2
Timer Buffer Operation Transfer Mode Register
Timer Control Register 2
Timer Control Register
16
8, 16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
8
8
8
8
8, 16, 32 4 to 7 PCLKA
Timer Control Register
TCR
8
8
8, 16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
Timer Mode Register 1
TMDR1
TMDR1
TIORH
TIORL
TIORH
TIORL
TIER
8
Timer Mode Register 1
8
Timer I/O Control Register H
Timer I/O Control Register L
Timer I/O Control Register H
Timer I/O Control Register L
Timer Interrupt Enable Register
Timer Interrupt Enable Register
8
8, 16, 32 4 to 7 PCLKA
8
8
8, 16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
8
8
8
8, 16
8
TIER
8
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 111 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (39 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
TOERB
TGCRB
TOCR1B
TOCR2B
TCNT
ICLK ≥ PCLK ICLK < PCLK Function
000C 1A0Ah
000C 1A0Dh
000C 1A0Eh
000C 1A0Fh
000C 1A10h
000C 1A12h
000C 1A14h
000C 1A16h
000C 1A18h
000C 1A1Ah
000C 1A1Ch
000C 1A1Eh
000C 1A20h
000C 1A22h
000C 1A24h
000C 1A26h
000C 1A28h
000C 1A2Ah
000C 1A2Ch
000C 1A2Dh
000C 1A30h
000C 1A31h
000C 1A32h
000C 1A34h
000C 1A36h
000C 1A38h
000C 1A39h
000C 1A3Ah
000C 1A3Bh
000C 1A3Ch
000C 1A40h
000C 1A44h
000C 1A46h
000C 1A48h
MTU
Timer Output Master Enable Register B
8
8
8
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
MTU
Timer Gate Control Register B
Timer Output Control Register 1B
Timer Output Control Register 2B
Timer Counter
MTU
8
8, 16
8
MTU
8
MTU6
MTU7
MTU
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
Timer Counter
TCNT
Timer Cycle Data Register B
Timer Dead Time Data Register B
Timer General Register A
TCDRB
TDDRB
TGRA
MTU
MTU6
MTU6
MTU7
MTU7
MTU
Timer General Register B
TGRB
Timer General Register A
TGRA
Timer General Register B
TGRB
Timer Subcounter B
TCNTSB
TCBRB
TGRC
MTU
Timer Cycle Buffer Register B
Timer General Register C
MTU6
MTU6
MTU7
MTU7
MTU6
MTU7
MTU
Timer General Register D
TGRD
Timer General Register C
TGRC
Timer General Register D
TGRD
16
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
Timer Status Register
TSR
8, 16
Timer Status Register
TSR
8
8
Timer Interrupt Skipping Set Register 1B
Timer Interrupt Skipping Counter 1B
Timer Buffer Transfer Set Register B
Timer Dead Time Enable Register B
Timer Output Level Buffer Register B
Timer Buffer Operation Transfer Mode Register
Timer Buffer Operation Transfer Mode Register
Timer Interrupt Skipping Mode Register B
Timer Interrupt Skipping Set Register 2B
Timer Interrupt Skipping Counter 2B
Timer A/D Converter Start Request Control Register
TITCR1B
TITCNT1B
TBTERB
TDERB
TOLBRB
TBTM
8
8, 16
MTU
8
8
8
MTU
8
MTU
8
8
MTU
8
8
MTU6
MTU7
MTU
8
8, 16
8
TBTM
8
TITMRB
TITCR2B
TITCNT2B
TADCR
8
8
MTU
8
8
MTU
8
8
MTU7
MTU7
MTU7
MTU7
16
16
16
16
16
Timer A/D Converter Start Request Cycle Set Register A TADCORA
Timer A/D Converter Start Request Cycle Set Register B TADCORB
16, 32 4 to 7 PCLKA
16 4 to 7 PCLKA
16, 32 4 to 7 PCLKA
Timer A/D Converter Start Request Cycle Set Buffer
Register A
TADCOBRA
000C 1A4Ah
MTU7
Timer A/D Converter Start Request Cycle Set Buffer
Register B
TADCOBRB
16
16
4 to 7 PCLKA
2 to 4 ICLK MTU3d
000C 1A4Ch
000C 1A4Dh
000C 1A50h
000C 1A60h
000C 1A70h
000C 1A72h
000C 1A74h
000C 1A76h
000C 1A80h
000C 1A81h
000C 1A84h
000C 1A93h
000C 1A94h
000C 1A95h
MTU6
MTU7
MTU6
MTU
Timer Control Register 2
TCR2
8
8
8
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
Timer Control Register 2
TCR2
Timer Synchronous Clear Register
Timer Waveform Control Register B
Timer Mode Register 2B
TSYCR
TWCRB
TMDR2B
TGRE
8
8
8
8
MTU
8
8
MTU6
MTU7
MTU7
MTU
Timer General Register E
16
16
16
8
16
16
16
8, 16
8
Timer General Register E
TGRE
Timer General Register F
TGRF
Timer Start Register B
TSTRB
TSYRB
TRWERB
NFCR6
NFCR7
NFCR5
MTU
Timer Synchronous Register B
Timer Read/Write Enable Register B
Noise Filter Control Register 6
Noise Filter Control Register 7
Noise Filter Control Register 5
8
MTU
8
8
MTU6
MTU7
MTU5
8
8
8
8
8
8
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 112 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (40 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
TCNTU
TGRU
TCRU
ICLK ≥ PCLK ICLK < PCLK Function
000C 1C80h
000C 1C82h
000C 1C84h
000C 1C85h
000C 1C86h
000C 1C90h
000C 1C92h
000C 1C94h
000C 1C95h
000C 1C96h
000C 1CA0h
000C 1CA2h
000C 1CA4h
000C 1CA5h
000C 1CA6h
000C 1CB2h
000C 1CB4h
000C 1CB6h
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
MTU5
Timer Counter U
16
16
8
16, 32 4 to 7 PCLKA
2 to 4 ICLK MTU3d
Timer General Register U
Timer Control Register U
Timer Control Register 2U
Timer I/O Control Register U
Timer Counter V
16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
TCR2U
TIORU
TCNTV
TGRV
8
8
8
8
16
16
8
16, 32 4 to 7 PCLKA
Timer General Register V
Timer Control Register V
Timer Control Register 2V
Timer I/O Control Register V
Timer Counter W
16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
TCRV
TCR2V
TIORV
TCNTW
TGRW
TCRW
TCR2W
TIORW
TIER
8
8
8
8
16
16
8
16, 32 4 to 7 PCLKA
Timer General Register W
Timer Control Register W
Timer Control Register 2W
Timer I/O Control Register W
Timer Interrupt Enable Register
Timer Start Register
16
8
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
4 to 7 PCLKA
8
8
8
8
8
8
TSTR
8
8
Timer Compare Match Clear Register
TCNTCMPCL
R
8
8
000C 1D30h
000C 1D32h
000C 2000h
000C 2004h
000C 2008h
000C 200Ch
000C 2010h
000C 2014h
000C 2018h
000C 201Ch
000C 2020h
000C 2024h
MTU
MTU
A/D Conversion Start Request Select Register 0
A/D Conversion Start Request Select Register 1
TADSTRGR0
TADSTRGR1
GTWP
8
8
4 to 7 PCLKA
4 to 7 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2 to 4 ICLK MTU3d
2 to 4 ICLK MTU3d
8
8
GPTW0 General PWM Timer Write-Protection Register
GPTW0 General PWM Timer Software Start Register
GPTW0 General PWM Timer Software Stop Register
GPTW0 General PWM Timer Software Clear Register
GPTW0 General PWM Timer Start Source Select Register
GPTW0 General PWM Timer Stop Source Select Register
GPTW0 General PWM Timer Clear Source Select Register
GPTW0 General PWM Timer Count-Up Source Select Register
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW0 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW0 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2028h
GPTW0 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 202Ch
000C 2030h
GPTW0 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW0 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2034h
000C 2038h
000C 203Ch
000C 2040h
000C 2044h
GPTW0 General PWM Timer I/O Control Register
GPTW0 General PWM Timer Interrupt Output Setting Register
GPTW0 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW0 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW0 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2048h
000C 204Ch
000C 2050h
000C 2054h
000C 2058h
000C 205Ch
000C 2060h
000C 2064h
000C 2068h
GPTW0 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW0 General PWM Timer Compare Capture Register A
GPTW0 General PWM Timer Compare Capture Register B
GPTW0 General PWM Timer Compare Capture Register C
GPTW0 General PWM Timer Compare Capture Register E
GPTW0 General PWM Timer Compare Capture Register D
GPTW0 General PWM Timer Compare Capture Register F
GPTW0 General PWM Timer Period Setting Register
GPTW0 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 113 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (41 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 206Ch
GPTW0 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 2070h
000C 2074h
000C 2078h
GPTW0 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW0 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW0 A/D Converter Start Request Timing Double-Buffer
Register A
000C 207Ch
000C 2080h
000C 2084h
GPTW0 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW0 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW0 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2088h
000C 208Ch
000C 2090h
000C 2094h
000C 2098h
000C 209Ch
GPTW0 General PWM Timer Dead Time Control Register
GPTW0 General PWM Timer Dead Time Value Register U
GPTW0 General PWM Timer Dead Time Value Register D
GPTW0 General PWM Timer Dead Time Buffer Register U
GPTW0 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW0 General PWM Timer Output Protection Function Status
Register
000C 20A0h
000C 20A4h
000C 20A8h
000C 20ACh
000C 20B0h
000C 20B4h
000C 20D0h
000C 20D4h
GPTW0 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW0 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW0 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW0 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW0 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW0 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW0 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW0 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2100h
000C 2104h
000C 2108h
000C 210Ch
000C 2110h
000C 2114h
000C 2118h
000C 211Ch
000C 2120h
000C 2124h
GPTW1 General PWM Timer Write-Protection Register
GPTW1 General PWM Timer Software Start Register
GPTW1 General PWM Timer Software Stop Register
GPTW1 General PWM Timer Software Clear Register
GPTW1 General PWM Timer Start Source Select Register
GPTW1 General PWM Timer Stop Source Select Register
GPTW1 General PWM Timer Clear Source Select Register
GPTW1 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW1 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW1 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2128h
GPTW1 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 212Ch
000C 2130h
GPTW1 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW1 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2134h
000C 2138h
000C 213Ch
000C 2140h
000C 2144h
GPTW1 General PWM Timer I/O Control Register
GPTW1 General PWM Timer Interrupt Output Setting Register
GPTW1 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW1 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW1 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2148h
000C 214Ch
GPTW1 General PWM Timer Counter
GTCNT
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW1 General PWM Timer Compare Capture Register A
GTCCRA
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 114 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (42 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
ICLK ≥ PCLK ICLK < PCLK Function
000C 2150h
000C 2154h
000C 2158h
000C 215Ch
000C 2160h
000C 2164h
000C 2168h
000C 216Ch
GPTW1 General PWM Timer Compare Capture Register B
GPTW1 General PWM Timer Compare Capture Register C
GPTW1 General PWM Timer Compare Capture Register E
GPTW1 General PWM Timer Compare Capture Register D
GPTW1 General PWM Timer Compare Capture Register F
GPTW1 General PWM Timer Period Setting Register
GPTW1 General PWM Timer Period Setting Buffer Register
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTPBR
GPTW1 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2170h
000C 2174h
000C 2178h
GPTW1 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW1 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW1 A/D Converter Start Request Timing Double-Buffer
Register A
000C 217Ch
000C 2180h
000C 2184h
GPTW1 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW1 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW1 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2188h
000C 218Ch
000C 2190h
000C 2194h
000C 2198h
000C 219Ch
GPTW1 General PWM Timer Dead Time Control Register
GPTW1 General PWM Timer Dead Time Value Register U
GPTW1 General PWM Timer Dead Time Value Register D
GPTW1 General PWM Timer Dead Time Buffer Register U
GPTW1 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW1 General PWM Timer Output Protection Function Status
Register
000C 21A0h
000C 21A4h
000C 21A8h
000C 21ACh
000C 21B0h
000C 21B4h
000C 21D0h
000C 21D4h
GPTW1 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW1 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW1 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW1 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW1 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW1 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW1 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW1 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2200h
000C 2204h
000C 2208h
000C 220Ch
000C 2210h
000C 2214h
000C 2218h
000C 221Ch
000C 2220h
000C 2224h
GPTW2 General PWM Timer Write-Protection Register
GPTW2 General PWM Timer Software Start Register
GPTW2 General PWM Timer Software Stop Register
GPTW2 General PWM Timer Software Clear Register
GPTW2 General PWM Timer Start Source Select Register
GPTW2 General PWM Timer Stop Source Select Register
GPTW2 General PWM Timer Clear Source Select Register
GPTW2 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW2 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW2 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2228h
GPTW2 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 222Ch
000C 2230h
GPTW2 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW2 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 115 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (43 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
GTIOR
GTINTAD
GTST
ICLK ≥ PCLK ICLK < PCLK Function
000C 2234h
000C 2238h
000C 223Ch
000C 2240h
000C 2244h
GPTW2 General PWM Timer I/O Control Register
GPTW2 General PWM Timer Interrupt Output Setting Register
GPTW2 General PWM Timer Status Register
GPTW2 General PWM Timer Buffer Enable Register
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GTBER
GTITC
GPTW2 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2248h
000C 224Ch
000C 2250h
000C 2254h
000C 2258h
000C 225Ch
000C 2260h
000C 2264h
000C 2268h
000C 226Ch
GPTW2 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW2 General PWM Timer Compare Capture Register A
GPTW2 General PWM Timer Compare Capture Register B
GPTW2 General PWM Timer Compare Capture Register C
GPTW2 General PWM Timer Compare Capture Register E
GPTW2 General PWM Timer Compare Capture Register D
GPTW2 General PWM Timer Compare Capture Register F
GPTW2 General PWM Timer Period Setting Register
GPTW2 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
GPTW2 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2270h
000C 2274h
000C 2278h
GPTW2 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW2 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW2 A/D Converter Start Request Timing Double-Buffer
Register A
000C 227Ch
000C 2280h
000C 2284h
GPTW2 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW2 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW2 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2288h
000C 228Ch
000C 2290h
000C 2294h
000C 2298h
000C 229Ch
GPTW2 General PWM Timer Dead Time Control Register
GPTW2 General PWM Timer Dead Time Value Register U
GPTW2 General PWM Timer Dead Time Value Register D
GPTW2 General PWM Timer Dead Time Buffer Register U
GPTW2 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW2 General PWM Timer Output Protection Function Status
Register
000C 22A0h
000C 22A4h
000C 22A8h
000C 22ACh
000C 22B0h
000C 22B4h
000C 22D0h
000C 22D4h
GPTW2 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW2 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW2 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW2 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW2 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW2 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW2 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW2 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2300h
000C 2304h
000C 2308h
000C 230Ch
000C 2310h
000C 2314h
000C 2318h
GPTW3 General PWM Timer Write-Protection Register
GPTW3 General PWM Timer Software Start Register
GPTW3 General PWM Timer Software Stop Register
GPTW3 General PWM Timer Software Clear Register
GPTW3 General PWM Timer Start Source Select Register
GPTW3 General PWM Timer Stop Source Select Register
GPTW3 General PWM Timer Clear Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 116 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (44 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 231Ch
000C 2320h
000C 2324h
GPTW3 General PWM Timer Count-Up Source Select Register
GTUPSR
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW3 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW3 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2328h
GPTW3 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 232Ch
000C 2330h
GPTW3 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW3 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2334h
000C 2338h
000C 233Ch
000C 2340h
000C 2344h
GPTW3 General PWM Timer I/O Control Register
GPTW3 General PWM Timer Interrupt Output Setting Register
GPTW3 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW3 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW3 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2348h
000C 234Ch
000C 2350h
000C 2354h
000C 2358h
000C 235Ch
000C 2360h
000C 2364h
000C 2368h
000C 236Ch
GPTW3 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW3 General PWM Timer Compare Capture Register A
GPTW3 General PWM Timer Compare Capture Register B
GPTW3 General PWM Timer Compare Capture Register C
GPTW3 General PWM Timer Compare Capture Register E
GPTW3 General PWM Timer Compare Capture Register D
GPTW3 General PWM Timer Compare Capture Register F
GPTW3 General PWM Timer Period Setting Register
GPTW3 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
GPTW3 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2370h
000C 2374h
000C 2378h
GPTW3 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW3 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW3 A/D Converter Start Request Timing Double-Buffer
Register A
000C 237Ch
000C 2380h
000C 2384h
GPTW3 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW3 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW3 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2388h
000C 238Ch
000C 2390h
000C 2394h
000C 2398h
000C 239Ch
GPTW3 General PWM Timer Dead Time Control Register
GPTW3 General PWM Timer Dead Time Value Register U
GPTW3 General PWM Timer Dead Time Value Register D
GPTW3 General PWM Timer Dead Time Buffer Register U
GPTW3 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW3 General PWM Timer Output Protection Function Status
Register
000C 23A0h
000C 23A4h
000C 23A8h
000C 23ACh
000C 23B0h
000C 23B4h
000C 23D0h
000C 23D4h
GPTW3 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW3 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW3 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW3 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW3 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW3 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW3 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW3 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 117 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (45 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 2400h
000C 2404h
000C 2408h
000C 240Ch
000C 2410h
000C 2414h
000C 2418h
000C 241Ch
000C 2420h
000C 2424h
GPTW4 General PWM Timer Write-Protection Register
GPTW4 General PWM Timer Software Start Register
GPTW4 General PWM Timer Software Stop Register
GPTW4 General PWM Timer Software Clear Register
GPTW4 General PWM Timer Start Source Select Register
GPTW4 General PWM Timer Stop Source Select Register
GPTW4 General PWM Timer Clear Source Select Register
GPTW4 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW4 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW4 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2428h
GPTW4 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 242Ch
000C 2430h
GPTW4 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW4 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2434h
000C 2438h
000C 243Ch
000C 2440h
000C 2444h
GPTW4 General PWM Timer I/O Control Register
GPTW4 General PWM Timer Interrupt Output Setting Register
GPTW4 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW4 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW4 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2448h
000C 244Ch
000C 2450h
000C 2454h
000C 2458h
000C 245Ch
000C 2460h
000C 2464h
000C 2468h
000C 246Ch
GPTW4 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW4 General PWM Timer Compare Capture Register A
GPTW4 General PWM Timer Compare Capture Register B
GPTW4 General PWM Timer Compare Capture Register C
GPTW4 General PWM Timer Compare Capture Register E
GPTW4 General PWM Timer Compare Capture Register D
GPTW4 General PWM Timer Compare Capture Register F
GPTW4 General PWM Timer Period Setting Register
GPTW4 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
GPTW4 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2470h
000C 2474h
000C 2478h
GPTW4 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW4 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW4 A/D Converter Start Request Timing Double-Buffer
Register A
000C 247Ch
000C 2480h
000C 2484h
GPTW4 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW4 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW4 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2488h
000C 248Ch
000C 2490h
000C 2494h
000C 2498h
000C 249Ch
GPTW4 General PWM Timer Dead Time Control Register
GPTW4 General PWM Timer Dead Time Value Register U
GPTW4 General PWM Timer Dead Time Value Register D
GPTW4 General PWM Timer Dead Time Buffer Register U
GPTW4 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW4 General PWM Timer Output Protection Function Status
Register
000C 24A0h
000C 24A4h
000C 24A8h
GPTW4 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW4 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW4 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 118 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (46 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 24ACh
GPTW4 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
000C 24B0h
000C 24B4h
000C 24D0h
000C 24D4h
GPTW4 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW4 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW4 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW4 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2500h
000C 2504h
000C 2508h
000C 250Ch
000C 2510h
000C 2514h
000C 2518h
000C 251Ch
000C 2520h
000C 2524h
GPTW5 General PWM Timer Write-Protection Register
GPTW5 General PWM Timer Software Start Register
GPTW5 General PWM Timer Software Stop Register
GPTW5 General PWM Timer Software Clear Register
GPTW5 General PWM Timer Start Source Select Register
GPTW5 General PWM Timer Stop Source Select Register
GPTW5 General PWM Timer Clear Source Select Register
GPTW5 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW5 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW5 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2528h
GPTW5 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 252Ch
000C 2530h
GPTW5 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW5 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2534h
000C 2538h
000C 253Ch
000C 2540h
000C 2544h
GPTW5 General PWM Timer I/O Control Register
GPTW5 General PWM Timer Interrupt Output Setting Register
GPTW5 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW5 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW5 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2548h
000C 254Ch
000C 2550h
000C 2554h
000C 2558h
000C 255Ch
000C 2560h
000C 2564h
000C 2568h
000C 256Ch
GPTW5 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW5 General PWM Timer Compare Capture Register A
GPTW5 General PWM Timer Compare Capture Register B
GPTW5 General PWM Timer Compare Capture Register C
GPTW5 General PWM Timer Compare Capture Register E
GPTW5 General PWM Timer Compare Capture Register D
GPTW5 General PWM Timer Compare Capture Register F
GPTW5 General PWM Timer Period Setting Register
GPTW5 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
GPTW5 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2570h
000C 2574h
000C 2578h
GPTW5 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW5 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW5 A/D Converter Start Request Timing Double-Buffer
Register A
000C 257Ch
000C 2580h
000C 2584h
GPTW5 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW5 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW5 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2588h
000C 258Ch
000C 2590h
000C 2594h
GPTW5 General PWM Timer Dead Time Control Register
GPTW5 General PWM Timer Dead Time Value Register U
GPTW5 General PWM Timer Dead Time Value Register D
GPTW5 General PWM Timer Dead Time Buffer Register U
GTDTCR
GTDVU
GTDVD
GTDBU
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 119 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (47 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
GTDBD
GTSOS
ICLK ≥ PCLK ICLK < PCLK Function
000C 2598h
000C 259Ch
GPTW5 General PWM Timer Dead Time Buffer Register D
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW5 General PWM Timer Output Protection Function Status
Register
000C 25A0h
000C 25A4h
000C 25A8h
000C 25ACh
000C 25B0h
000C 25B4h
000C 25D0h
000C 25D4h
GPTW5 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW5 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW5 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW5 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW5 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW5 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW5 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW5 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2600h
000C 2604h
000C 2608h
000C 260Ch
000C 2610h
000C 2614h
000C 2618h
000C 261Ch
000C 2620h
000C 2624h
GPTW6 General PWM Timer Write-Protection Register
GPTW6 General PWM Timer Software Start Register
GPTW6 General PWM Timer Software Stop Register
GPTW6 General PWM Timer Software Clear Register
GPTW6 General PWM Timer Start Source Select Register
GPTW6 General PWM Timer Stop Source Select Register
GPTW6 General PWM Timer Clear Source Select Register
GPTW6 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW6 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW6 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2628h
GPTW6 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 262Ch
000C 2630h
GPTW6 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW6 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2634h
000C 2638h
000C 263Ch
000C 2640h
000C 2644h
GPTW6 General PWM Timer I/O Control Register
GPTW6 General PWM Timer Interrupt Output Setting Register
GPTW6 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW6 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW6 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2648h
000C 264Ch
000C 2650h
000C 2654h
000C 2658h
000C 265Ch
000C 2660h
000C 2664h
000C 2668h
000C 266Ch
GPTW6 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW6 General PWM Timer Compare Capture Register A
GPTW6 General PWM Timer Compare Capture Register B
GPTW6 General PWM Timer Compare Capture Register C
GPTW6 General PWM Timer Compare Capture Register E
GPTW6 General PWM Timer Compare Capture Register D
GPTW6 General PWM Timer Compare Capture Register F
GPTW6 General PWM Timer Period Setting Register
GPTW6 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
GPTW6 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2670h
000C 2674h
000C 2678h
GPTW6 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW6 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW6 A/D Converter Start Request Timing Double-Buffer
Register A
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 120 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (48 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 267Ch
000C 2680h
000C 2684h
GPTW6 A/D Converter Start Request Timing Register B
GPTW6 A/D Converter Start Request Timing Buffer Register B
GTADTRB
GTADTBRB
GTADTDBRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW6 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2688h
000C 268Ch
000C 2690h
000C 2694h
000C 2698h
000C 269Ch
GPTW6 General PWM Timer Dead Time Control Register
GPTW6 General PWM Timer Dead Time Value Register U
GPTW6 General PWM Timer Dead Time Value Register D
GPTW6 General PWM Timer Dead Time Buffer Register U
GPTW6 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW6 General PWM Timer Output Protection Function Status
Register
000C 26A0h
000C 26A4h
000C 26A8h
000C 26ACh
000C 26B0h
000C 26B4h
000C 26D0h
000C 26D4h
GPTW6 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW6 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW6 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW6 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW6 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW6 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW6 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW6 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2700h
000C 2704h
000C 2708h
000C 270Ch
000C 2710h
000C 2714h
000C 2718h
000C 271Ch
000C 2720h
000C 2724h
GPTW7 General PWM Timer Write-Protection Register
GPTW7 General PWM Timer Software Start Register
GPTW7 General PWM Timer Software Stop Register
GPTW7 General PWM Timer Software Clear Register
GPTW7 General PWM Timer Start Source Select Register
GPTW7 General PWM Timer Stop Source Select Register
GPTW7 General PWM Timer Clear Source Select Register
GPTW7 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW7 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW7 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2728h
GPTW7 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 272Ch
000C 2730h
GPTW7 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW7 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2734h
000C 2738h
000C 273Ch
000C 2740h
000C 2744h
GPTW7 General PWM Timer I/O Control Register
GPTW7 General PWM Timer Interrupt Output Setting Register
GPTW7 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW7 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW7 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2748h
000C 274Ch
000C 2750h
000C 2754h
000C 2758h
000C 275Ch
000C 2760h
GPTW7 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW7 General PWM Timer Compare Capture Register A
GPTW7 General PWM Timer Compare Capture Register B
GPTW7 General PWM Timer Compare Capture Register C
GPTW7 General PWM Timer Compare Capture Register E
GPTW7 General PWM Timer Compare Capture Register D
GPTW7 General PWM Timer Compare Capture Register F
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 121 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (49 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 2764h
000C 2768h
000C 276Ch
GPTW7 General PWM Timer Period Setting Register
GPTW7 General PWM Timer Period Setting Buffer Register
GTPR
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GTPBR
GTPDBR
GPTW7 General PWM Timer Period Setting Double-Buffer
Register
000C 2770h
000C 2774h
000C 2778h
GPTW7 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW7 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW7 A/D Converter Start Request Timing Double-Buffer
Register A
000C 277Ch
000C 2780h
000C 2784h
GPTW7 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW7 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW7 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2788h
000C 278Ch
000C 2790h
000C 2794h
000C 2798h
000C 279Ch
GPTW7 General PWM Timer Dead Time Control Register
GPTW7 General PWM Timer Dead Time Value Register U
GPTW7 General PWM Timer Dead Time Value Register D
GPTW7 General PWM Timer Dead Time Buffer Register U
GPTW7 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW7 General PWM Timer Output Protection Function Status
Register
000C 27A0h
000C 27A4h
000C 27A8h
000C 27ACh
000C 27B0h
000C 27B4h
000C 27D0h
000C 27D4h
GPTW7 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW7 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW7 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW7 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW7 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW7 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW7 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW7 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2800h
000C 2804h
000C 2808h
000C 280Ch
000C 2810h
000C 2814h
000C 2818h
000C 281Ch
000C 2820h
000C 2824h
GPTW8 General PWM Timer Write-Protection Register
GPTW8 General PWM Timer Software Start Register
GPTW8 General PWM Timer Software Stop Register
GPTW8 General PWM Timer Software Clear Register
GPTW8 General PWM Timer Start Source Select Register
GPTW8 General PWM Timer Stop Source Select Register
GPTW8 General PWM Timer Clear Source Select Register
GPTW8 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW8 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW8 General PWM Timer Input Capture Source Select
Register A
GTICASR
000C 2828h
GPTW8 General PWM Timer Input Capture Source Select
Register B
GTICBSR
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 282Ch
000C 2830h
GPTW8 General PWM Timer Control Register
GTCR
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW8 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
000C 2834h
000C 2838h
000C 283Ch
000C 2840h
000C 2844h
GPTW8 General PWM Timer I/O Control Register
GPTW8 General PWM Timer Interrupt Output Setting Register
GPTW8 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW8 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW8 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 122 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (50 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 2848h
000C 284Ch
000C 2850h
000C 2854h
000C 2858h
000C 285Ch
000C 2860h
000C 2864h
000C 2868h
000C 286Ch
GPTW8 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW8 General PWM Timer Compare Capture Register A
GPTW8 General PWM Timer Compare Capture Register B
GPTW8 General PWM Timer Compare Capture Register C
GPTW8 General PWM Timer Compare Capture Register E
GPTW8 General PWM Timer Compare Capture Register D
GPTW8 General PWM Timer Compare Capture Register F
GPTW8 General PWM Timer Period Setting Register
GPTW8 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
GPTW8 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2870h
000C 2874h
000C 2878h
GPTW8 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW8 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW8 A/D Converter Start Request Timing Double-Buffer
Register A
000C 287Ch
000C 2880h
000C 2884h
GPTW8 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW8 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW8 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2888h
000C 288Ch
000C 2890h
000C 2894h
000C 2898h
000C 289Ch
GPTW8 General PWM Timer Dead Time Control Register
GPTW8 General PWM Timer Dead Time Value Register U
GPTW8 General PWM Timer Dead Time Value Register D
GPTW8 General PWM Timer Dead Time Buffer Register U
GPTW8 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW8 General PWM Timer Output Protection Function Status
Register
000C 28A0h
000C 28A4h
000C 28A8h
000C 28ACh
000C 28B0h
000C 28B4h
000C 28D0h
000C 28D4h
GPTW8 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW8 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW8 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW8 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW8 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW8 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW8 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW8 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2900h
000C 2904h
000C 2908h
000C 290Ch
000C 2910h
000C 2914h
000C 2918h
000C 291Ch
000C 2920h
000C 2924h
GPTW9 General PWM Timer Write-Protection Register
GPTW9 General PWM Timer Software Start Register
GPTW9 General PWM Timer Software Stop Register
GPTW9 General PWM Timer Software Clear Register
GPTW9 General PWM Timer Start Source Select Register
GPTW9 General PWM Timer Stop Source Select Register
GPTW9 General PWM Timer Clear Source Select Register
GPTW9 General PWM Timer Count-Up Source Select Register
GTWP
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GTSTR
GTSTP
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GPTW9 General PWM Timer Count-Down Source Select Register GTDNSR
GPTW9 General PWM Timer Input Capture Source Select
Register A
GTICASR
GTICBSR
GTCR
000C 2928h
000C 292Ch
GPTW9 General PWM Timer Input Capture Source Select
Register B
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW9 General PWM Timer Control Register
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 123 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (51 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 2930h
GPTW9 General PWM Timer Count Direction and Duty Setting
Register
GTUDDTYC
32
32
4, 5 PCLKA
2, 3 ICLK
GPTW
000C 2934h
000C 2938h
000C 293Ch
000C 2940h
000C 2944h
GPTW9 General PWM Timer I/O Control Register
GPTW9 General PWM Timer Interrupt Output Setting Register
GPTW9 General PWM Timer Status Register
GTIOR
GTINTAD
GTST
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW9 General PWM Timer Buffer Enable Register
GTBER
GTITC
GPTW9 General PWM Timer Interrupt and A/D Converter Start
Request Skipping Setting Register
000C 2948h
000C 294Ch
000C 2950h
000C 2954h
000C 2958h
000C 295Ch
000C 2960h
000C 2964h
000C 2968h
000C 296Ch
GPTW9 General PWM Timer Counter
GTCNT
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW9 General PWM Timer Compare Capture Register A
GPTW9 General PWM Timer Compare Capture Register B
GPTW9 General PWM Timer Compare Capture Register C
GPTW9 General PWM Timer Compare Capture Register E
GPTW9 General PWM Timer Compare Capture Register D
GPTW9 General PWM Timer Compare Capture Register F
GPTW9 General PWM Timer Period Setting Register
GPTW9 General PWM Timer Period Setting Buffer Register
GTCCRA
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
GTPBR
GPTW9 General PWM Timer Period Setting Double-Buffer
Register
GTPDBR
000C 2970h
000C 2974h
000C 2978h
GPTW9 A/D Converter Start Request Timing Register A
GTADTRA
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW9 A/D Converter Start Request Timing Buffer Register A
GTADTBRA
GTADTDBRA
GPTW9 A/D Converter Start Request Timing Double-Buffer
Register A
000C 297Ch
000C 2980h
000C 2984h
GPTW9 A/D Converter Start Request Timing Register B
GTADTRB
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW9 A/D Converter Start Request Timing Buffer Register B
GTADTBRB
GTADTDBRB
GPTW9 A/D Converter Start Request Timing Double-Buffer
Register B
000C 2988h
000C 298Ch
000C 2990h
000C 2994h
000C 2998h
000C 299Ch
GPTW9 General PWM Timer Dead Time Control Register
GPTW9 General PWM Timer Dead Time Value Register U
GPTW9 General PWM Timer Dead Time Value Register D
GPTW9 General PWM Timer Dead Time Buffer Register U
GPTW9 General PWM Timer Dead Time Buffer Register D
GTDTCR
GTDVU
GTDVD
GTDBU
GTDBD
GTSOS
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW9 General PWM Timer Output Protection Function Status
Register
000C 29A0h
000C 29A4h
000C 29A8h
000C 29ACh
000C 29B0h
000C 29B4h
000C 29D0h
000C 29D4h
GPTW9 General PWM Timer Output Protection Function
Temporary Release Register
GTSOTR
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW
GPTW9 General PWM Timer A/D Converter Start Request Signal GTADSMR
Monitoring Register
GPTW9 General PWM Timer Extended Interrupt Skipping Counter GTEITC
Control Register
GPTW9 General PWM Timer Extended Interrupt Skipping Setting GTEITLI1
Register 1
GPTW9 General PWM Timer Extended Interrupt Skipping Setting GTEITLI2
Register 2
GPTW9 General PWM Timer Extended Buffer Transfer Skipping GTEITLB
Setting Register
GPTW9 General PWM Timer Operation Enable Bit Simultaneous GTSECSR
Control Channel Select Register
GPTW9 General PWM Timer Operation Enable Bit Simultaneous GTSECR
Control Register
000C 2A00h
000C 2A02h
000C 2A18h
000C 2A1Ah
000C 2A1Ch
000C 2A1Eh
HRPWM HRPWM Operation Control Register
HROCR
16
16
16
16
16
16
16
16
16
16
16
16
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM HRPWM Operation Control Register 2
HROCR2
HRPWM GTIOC0A Pin Rising Edge Adjustment Register
HRPWM GTIOC0B Pin Rising Edge Adjustment Register
HRPWM GTIOC1A Pin Rising Edge Adjustment Register
HRPWM GTIOC1B Pin Rising Edge Adjustment Register
HRREAR0A
HRREAR0B
HRREAR1A
HRREAR1B
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 124 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (52 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000C 2A20h
000C 2A22h
000C 2A24h
000C 2A26h
000C 2A28h
000C 2A2Ah
000C 2A2Ch
000C 2A2Eh
000C 2A30h
000C 2A32h
000C 2A34h
000C 2A36h
000D 0000h
HRPWM GTIOC2A Pin Rising Edge Adjustment Register
HRPWM GTIOC2B Pin Rising Edge Adjustment Register
HRPWM GTIOC3A Pin Rising Edge Adjustment Register
HRPWM GTIOC3B Pin Rising Edge Adjustment Register
HRPWM GTIOC0A Pin Falling Edge Adjustment Register
HRPWM GTIOC0B Pin Falling Edge Adjustment Register
HRPWM GTIOC1A Pin Falling Edge Adjustment Register
HRPWM GTIOC1B Pin Falling Edge Adjustment Register
HRPWM GTIOC2A Pin Falling Edge Adjustment Register
HRPWM GTIOC2B Pin Falling Edge Adjustment Register
HRPWM GTIOC3A Pin Falling Edge Adjustment Register
HRPWM GTIOC3B Pin Falling Edge Adjustment Register
HRREAR2A
HRREAR2B
HRREAR3A
HRREAR3B
HRFEAR0A
HRFEAR0B
HRFEAR1A
HRFEAR1B
HRFEAR2A
HRFEAR2B
HRFEAR3A
HRFEAR3B
SMR
16
16
16
16
16
16
16
16
16
16
16
16
8
16
16
16
16
16
16
16
16
16
16
16
16
8
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
4, 5 PCLKA
2, 3 PCLKA
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2 ICLK
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
HRPWM
SCI11
Serial Mode Register
SCIj,SCIi,
SCIh
000D 0000h
000D 0001h
000D 0002h
000D 0002h
000D 0003h
000D 0004h
000D 0004h
000D 0004h
000D 0005h
000D 0006h
000D 0007h
000D 0008h
000D 0009h
000D 000Ah
000D 000Bh
000D 000Ch
000D 000Dh
000D 000Eh
000D 000Fh
000D 000Eh
000D 000Eh
000D 000Fh
000D 000Eh
SMCI11 Serial Mode Register
SMR
8
8
8
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj, SCIi,
SCIh
SCI11
SCI11
Bit Rate Register
BRR
8
SCIj,SCIi,
SCIh
Serial Control Register
SCR
8
8
SCIj,SCIi,
SCIh
SMCI11 Serial Control Register
SCR
8
8
SCIj,SCIi,
SCIh
SCI11
SCI11
Transmit Data Register
Serial Status Register
TDR
8
8
SCIj, SCIi,
SCIh
SSR
8
8
SCIj, SCIi,
SCIh
SMCI11 Serial Status Register
SSR
8
8
SCIj,SCIi,
SCIh
SCI11
SCI11
Serial Status Register
Receive Data Register
SSRFIFO
RDR
8
8
SCIj,SCIi,
SCIh
8
8
SCIj, SCIi,
SCIh
SMCI11 Smart Card Mode Register
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
8
8
SCIj,SCIi,
SCIh
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
Serial Extended Mode Register
Noise Filter Setting Register
I2C Mode Register 1
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj, SCIi,
SCIh
I2C Mode Register 2
8
8
SCIj, SCIi,
SCIh
I2C Mode Register 3
8
8
SCIj, SCIi,
SCIh
I2C Status Register
8
8
SCIj,SCIi,
SCIh
SPI Mode Register
SPMR
TDRH
TDRL
TDRHL
FTDR.H
FTDR.L
FTDR
8
8
8
SCIj,SCIi,
SCIh
Transmit Data Register H
Transmit Data Register L
Transmit Data Register HL
Transmit FIFO Data Register H
Transmit FIFO Data Register L
Transmit FIFO Data Register
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
8
SCIj,SCIi,
SCIh
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8, 16
SCIj,SCIi,
SCIh
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 125 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (53 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Symbol
Number Access
of Bits Size
Related
Address
ICLK ≥ PCLK ICLK < PCLK Function
000D 0010h
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
SCI11
Receive Data Register H
RDRH
8
8
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 to 5 PCLKA
2, 3 PCLKA
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
SCIj,SCIi,
SCIh
000D 0011h
000D 0010h
000D 0010h
000D 0011h
000D 0010h
000D 0012h
000D 0013h
000D 0014h
000D 0015h
000D 0014h
000D 0016h
000D 0017h
000D 0016h
000D 0018h
000D 0019h
000D 0018h
000D 001Ah
000D 001Bh
000D 001Ah
000D 001Ch
Receive Data Register L
Receive Data Register
RDRL
RDRHL
FRDR.H
FRDR.L
FRDR
MDDR
DCCR
FCR.H
FCR.L
FCR
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
Receive FIFO Data Register H
Receive FIFO Data Register L
Receive FIFO Data Register HL
Modulation Duty Register
Data Comparison Control Register
FIFO Control Register H
FIFO Control Register L
FIFO Control Register
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
SCIj,SCIi,
SCIh
FIFO Data Count Register H
FIFO Data Count Register L
FIFO Data Count Register
Line Status Register H
FDR.H
FDR.L
FDR
8
SCIj,SCIi,
SCIh
8
8
8, 16
8
SCIj,SCIi,
SCIh
16
8
SCIj,SCIi,
SCIh
LSR.H
LSR.L
LSR
SCIj,SCIi,
SCIh
Line Status Register L
8
8
SCIj,SCIi,
SCIh
Line Status Register
16
8
8, 16
8
SCIj,SCIi,
SCIh
Comparison Data Register H
Comparison Data Register L
Comparison Data Register
Serial Port Register
CDR.H
CDR.L
CDR
SCIj,SCIi,
SCIh
8
8
SCIj,SCIi,
SCIh
16
8
8, 16
8
SCIj,SCIi,
SCIh
SPTR
SCIj, SCIi,
SCIh
000D 0100h
000D 0101h
000D 0102h
000D 0103h
000D 0104h
000D 0108h
000D 0109h
000D 010Ah
000D 010Bh
000D 010Ch
000D 010Dh
000D 010Eh
000D 010Fh
000D 0110h
000D 0112h
000D 0114h
000D 0116h
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
RSPI Control Register
SPCR
8
8
8
8
8
8
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPI Slave Select Polarity Register
RSPI Pin Control Register
RSPI Status Register
SSLP
SPPCR
SPSR
8
8
RSPI Data Register
SPDR
32
8
8, 16, 32 2, 3 PCLKA
RSPI Sequence Control Register
RSPI Sequence Status Register
RSPI Bit Rate Register
SPSCR
SPSSR
SPBR
8
8
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
8
8
8
RSPI Data Control Register
RSPI Clock Delay Register
RSPI Slave Select Negation Delay Register
RSPI Next-Access Delay Register
RSPI Control Register 2
SPDCR
SPCKD
SSLND
SPND
8
8
8
8
8
8
8
8
SPCR2
SPCMD0
SPCMD1
SPCMD2
SPCMD3
8
8
RSPI Command Register 0
RSPI Command Register 1
RSPI Command Register 2
RSPI Command Register 3
16
16
16
16
16
16
16
16
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 126 of 201
RX66T Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (54 / 54)
Number of Access Cycles
Module
Symbol Register Name
Register
Number Access
of Bits Size
Related
Address
Symbol
SPCMD4
SPCMD5
SPCMD6
SPCMD7
SPDCR2
SPCC
ICLK ≥ PCLK ICLK < PCLK Function
000D 0118h
000D 011Ah
000D 011Ch
000D 011Eh
000D 0120h
0012 0040h
RSPI0
RSPI0
RSPI0
RSPI0
RSPI0
OFSM
RSPI Command Register 4
16
16
16
16
8
16
16
16
16
8
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2, 3 PCLKA
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
RSPIc
RSPIc
RSPIc
RSPIc
RSPIc
RSPI Command Register 5
RSPI Command Register 6
RSPI Command Register 7
RSPI Data Control Register 2
Serial Programmer Command Control Register
32
32
8 FCLK
Option-
Setting
Memory
0012 0048h
0012 0050h
0012 0060h
0012 0064h
0012 0068h
0012 006Ch
0012 007Ch
OFSM
OFSM
OFSM
OFSM
OFSM
OFSM
OFSM
TM Enable Flag Register
TMEF
OSIS
32
128
32
32
32
32
32
32
32
32
8 FCLK
8 FCLK
8 FCLK
8 FCLK
8 FCLK
8 FCLK
8 FCLK
Option-
Setting
Memory
OCD/Serial Programmer ID Setting Register
TM Identification Data Register
Endian Select Register
Option-
Setting
Memory
TMINF
MDE
Option-
Setting
Memory
32
Option-
Setting
Memory
Option Function Select Register 0
Option Function Select Register 1
ROM Code Protection Register
OFS0
32
Option-
Setting
Memory
OFS1
32
Option-
Setting
Memory
ROMCODE
32
Option-
Setting
Memory
007F B174h
007F B17Ch
007F B1E4h
007F B1E8h
007F E010h
007F E014h
007F E018h
007F E030h
007F E034h
007F E080h
007F E084h
007F E088h
007F E08Ch
007F E090h
007F E0A0h
007F E0C0h
007F E0D0h
007F E0D4h
007F E0D8h
007F E0E0h
007F E0E4h
FLASH Unique ID Register 0
UIDR0
32
32
32
32
8
32
32
32
32
8
3 to 5 FCLK
3 to 5 FCLK
3 to 5 FCLK
3 to 5 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
2 to 4 FCLK
3, 4 ICLK
3, 4 ICLK
3, 4 ICLK
3, 4 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
2, 3 ICLK
Flash
TEMPS
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Flash
TEMPS Temperature Sensor Calibration Data Register
FLASH Unique ID Register 1
TSCDR
UIDR1
FLASH Unique ID Register 2
UIDR2
FLASH Flash Access Status Register
FASTAT
FAEINT
FLASH Flash Access Error Interrupt Enable Register
FLASH Flash Ready Interrupt Enable Register
FLASH FACI Command Processing Start Address Register
FLASH FACI Command Processing End Address Register
FLASH Flash Status Register
8
8
FRDYIE
FSADDR
FEADDR
FSTATR
FENTRYR
FPROTR
FSUINITR
FLKSTAT
FCMDR
FPESTAT
FBCCNT
FBCSTAT
FPSADDR
FCPSR
8
8
32
32
32
16
16
16
8
32
32
32
16
16
16
8
FLASH Flash P/E Mode Entry Register
FLASH Flash Protection Register
FLASH Flash Sequencer Set-Up Initialization Register
FLASH Lock Bit Status Register
FLASH FACI Command Register
16
16
8
16
16
8
FLASH Flash P/E Status Register
FLASH Data Flash Blank Check Control Register
FLASH Data Flash Blank Check Status Register
FLASH Data Flash Programming Start Address Register
FLASH Flash Sequencer Processing Switching Register
8
8
32
16
16
32
16
16
FLASH Flash Sequencer Processing Clock Frequency
Notification Register
FPCKAR
Note 1. When the register is accessed while the USB is operating, a delay may be generated in accessing.
Note 2. The address must end with 0h, 4h, 8h, or Ch when access is made in 32-bit units. The address must end with 0h, 2h, 4h, 6h, 8h,
Ah, Ch, or Eh when access is made in 16-bit units.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 127 of 201
RX66T Group
5. Electrical Characteristics
5.
Electrical Characteristics
5.1
Absolute Maximum Ratings
Table 5.1
Absolute Maximum Rating
Conditions: VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0V
Item
Power supply voltage*1
Symbol
VCC
Value
Unit
V
–0.3 to +6.5
–0.3 to +6.5
–0.3 to +6.5
USB power supply voltage*1
Analog power supply voltage*1
VCC_USB
AVCC0, AVCC1,
AVCC2
Input voltage
PB1, PB2, PC0*2, and PD2*2
Vin
–0.3 to +6.5
P40 to P42, P44 to
P46, PH0, and PH4
With negative input
enabled*3
–1.0 to AVCC1 + 0.3 (up to 6.5)
With negative input
disabled
–0.3 to AVCC1 + 0.3 (up to 6.5)
P43, P47, PH1 to PH3, and PH5 to PH7
P50 to P55, and P60 to P65
USB0_DP, USB0_DM
–0.3 to AVCC1 + 0.3 (up to 6.5)
–0.3 to AVCC2 + 0.3 (up to 6.5)
–0.3 to VCC_USB + 0.3 (up to 6.5)
–0.3 to VCC + 0.3 (up to 6.5)
–40 to +105
Other than above
Junction temperature
D version
G version
Tj
°C
–40 to +125
Storage temperature
Tstg
–55 to +125
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note 1. Insert capacitors with good frequency characteristics between each power supply pin and the ground. Specifically, place
capacitors with a value around 0.1 μF as close as possible to every power supply pin, and use the shortest and thickest possible
traces.
Note 2. This is only available for products with 128 Kbytes of RAM.
Note 3. When VOLSR.PGAVLS = 0 and ADPGADCR0.PxDEN = 1 (x = 000, 001, 002, 100, 101, 102).
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 128 of 201
RX66T Group
5. Electrical Characteristics
5.2
Recommended operating conditions
Table 5.2
Recommended operating conditions (1)
Item
Symbol
VCC*1
Min.
2.7
—
Typ.
—
Max.
5.5
—
Unit
V
Power supply voltage
VSS
0
USB power supply voltage*2
When USB in use
VCC_USB*1
VSS_USB
VCC_USB
VSS_USB
3.0
—
—
3.6
—
0
When USB not in
use
—
VCC
VSS
—
—
—
—
Analog power supply voltage*3
AVCC0, AVCC1,
AVCC2*1
3.0
5.5
AVSS0, AVSS1,
AVSS2
—
0
—
Input voltage
PB1, PB2, PC0*4, and PD2*4
Vin
–0.3
–1.0
—
—
5.8
P40 to P42, and
P44 to P46
With negative input
enabled*5
AVCC1 + 0.3
With negative input
disabled
–0.3
–0.5
–0.3
—
—
—
PH0, PH4
With negative input
enabled*5
AVCC1 + 0.3
With negative input
disabled
P43, P47, PH1 to PH3, and PH5 to PH7
P50 to P55, and P60 to P65
USB0_DP, USB0_DM
Other than above
–0.3
–0.3
–0.3
–0.3
–40
—
—
—
—
—
—
AVCC1 + 0.3
AVCC2 + 0.3
VCC_USB + 0.3
VCC + 0.3
85
Operating
D version
Topr
°C
temperature
G version
–40
105
Note 1. Comply with the following voltage condition: VCC_USB ≤ VCC ≤ AVCC0 = AVCC1 = AVCC2
Note 2. When the USB interface is not to be used, connect VCC_USB to VCC and VSS_USB to VSS, and set VOLSR.USBVON=0.
Note 3. When not using any of the12-bit A/D converter (unit 0 to 2), 12-bit D/A converter, comparator C, or temperature sensor, connect
AVCC0, AVCC1, and AVCC2 to VCC, and AVSS0, AVSS1, and AVSS2 to VSS, respectively. For details, refer to section
38.6.10, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.
Note 4. This is only available for products with 128 Kbytes of RAM.
Note 5. When VOLSR.PGAVLS = 0 and ADPGADCR0.PxDEN = 1 (x = 000, 001, 002, 100, 101, 102).
Table 5.3
Recommended operating conditions (2)
Item
Symbol
CVCL
Value
Decoupling capacitance to stabilize the internal voltage
0.47 µF ± 30%*1
Note 1. Use a multilayer ceramic capacitor whose nominal capacitance is 0.47 µF and a capacitance tolerance is ±30% or better.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 129 of 201
RX66T Group
5. Electrical Characteristics
5.3
DC Characteristics
Table 5.4
DC Characteristics (1)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
V
Schmitt trigger
input voltage
CAN input pin
MTU input pin
GPTW input pin
POE input pin
POEG input pin
TMR input pin
SCI input pin
VIH
VIL
0.8 × VCC
—
—
—
—
—
0.2 × VCC
—
ΔVT
0.06 × VCC
ADTRG# input pin
RES#, NMI
IRQ input pin
(except for P52 to P55, and P60
to P65)
VIH
VIL
0.8 × VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.06 × VCC
0.8 × AVCC2
—
0.2 × VCC
ΔVT
VIH
VIL
—
IRQ input pin
(P52 to P55, and P60 to P65)
—
0.2 × AVCC2
ΔVT
VIH
VIL
0.06 × AVCC2
0.7 × VCC
—
—
RIIC input pin
(except for SMBus)
—
0.3 × VCC
ΔVT
VIH
VIL
0.06 × VCC
0.8 × VCC
—
—
Pins for 5 V tolerant
(PB1, PB2, PC0*1, and PD2*1)
—
0.2 × VCC
Analog input pins
(P40 to P47, and PH0 to PH7)
VIH
VIL
0.8 × AVCC1
—
—
0.2 × AVCC1
Analog input pins
(P50 to P55, and P60 to P65)
VIH
VIL
0.8 × AVCC2
—
—
0.2 × AVCC2
Other input pins
(pins other than those above)
VIH
VIL
0.8 × VCC
—
—
0.2 × VCC
—
High-level input
voltage (except for
Schmitt trigger
input pin)
MD pin, EMLE
VIH
0.9 × VCC
0.8 × VCC
0.7 × VCC
2.1
V
V
EXTAL, WAIT#, RSPI input pin
D0 to D15
—
—
RIIC (SMBus)
—
Low-level input
voltage (except for
Schmitt trigger
input pin)
MD pin, EMLE
VIL
—
0.1 × VCC
0.2 × VCC
0.3 × VCC
0.8
EXTAL, WAIT#, RSPI input pin
D0 to D15
—
—
RIIC (SMBus)
—
Note 1. This is only available for products with 128 Kbytes of RAM.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 130 of 201
RX66T Group
5. Electrical Characteristics
Table 5.5
DC Characteristics (2)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Symbol
VOH
Min.
Typ.
—
Max.
—
Unit
V
Test Conditions
IOH = –1.0 mA
High-level output
voltage
P43, P47, PH1 to PH3, and
PH5 to PH7
AVCC1 – 0.5
P50 to P55, and P60 to P65
AVCC2 – 0.5
VCC – 1.0
—
—
—
—
IOH = –1.0 mA
P90 to P95, P71 to P76, P81,
PB5, and PD3
IOH = –5.0 mA
(when the large
current output is set)
Other than above
VCC – 0.5
—
—
—
—
I
OH = –1.0 mA
Low-level output
voltage
P43, P47, PH1 to PH3, and
PH5 to PH7
VOL
0.5
IOL = 1.0 mA
P50 to P55, and P60 to P65
—
—
—
—
0.5
1.0
I
OL = 1.0 mA
OL = 15 mA
P90 to P95, P71 to P76, P81,
PB5, and PD3
I
(when the large
current output is set)
RIIC pins
—
—
—
—
—
—
—
—
0.4
0.6
0.5
1.0
IOL = 3.0 mA
IOL = 6.0 mA
Other than above
IOL = 1.0 mA
Input leakage current RES#, MD pin, PE2, and
EMLE*1
| Iin
|
μA Vin = 0 V
Vin = VCC
P40 to P42, and P44 to P46
—
—
—
—
1.0
1.0
Vin = 0 V
Vin = AVCC1
PH0 and PH4
Vin = 0 V
Vin = AVCC1
VOLSR.PGAVLS = 1
Three-state leakage RIIC pins
| ITSI
|
—
—
—
—
—
5.0
1.0
Vin = 0 V
Vin = VCC
current (off state)
Other than above
Input pull-up resistors P43, P47, PH1 to PH3,
Ip
–300
–10
AVCC1 = AVCC2 =
3.0 to 5.5 V
current
PH5 to PH7, P50 to P55, and
P60 to P65
Vin = 0 V
Pins other than those above and
PE2
–300
10
—
—
–10
300
VCC = 2.7 to 5.5 V
Vin = 0 V
Input pull-down
resistors current
EMLE
Vin = VCC = AVCC
Input capacitance
RIIC pins, PH0, and PH4
USB0_DP, and USB0_DM pins
Other than above
Cin
—
—
—
—
—
—
16
16
8
pF Vbias = 0 V
Vamp = 20 mV
f = 1 MHz
Ta = 25°C
—
Output voltage of the VCL pin
VCL
1.25
—
V
Note 1. The input leakage current value at the EMLE pin is only when Vin = 0 V.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 131 of 201
RX66T Group
5. Electrical Characteristics
Table 5.6
DC Characteristics (3) (Products with 64 Kbytes of RAM, D version)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
D version
Typ. Max.
Item
Symbol
Unit
Test Conditions
Min.
—
3
Supply
current*1
Full operation*2
ICC
*
—
21
12
75
—
—
mA ICLK = 160 MHz
PCLKA = 80 MHz
PCLKB = 40 MHz
PCLKC = 160 MHz
PCLKD = 40 MHz
FCLK = 40 MHz
Normal
operation
Peripheral module clocks are supplied*4
—
Peripheral module clocks are stopped
—
4,
5
*
*
CoreMark Peripheral module clocks are stopped
—
—
21
18
—
4,
5
*
*
BCLK = 40 MHz
BCLK pin = 40 MHz
Sleep mode: Peripheral module clocks are
supplied*4
37
All module clock stop mode (reference value)
Increase current by BGO operation*6
Increase current by operating Trusted Secure IP
Software standby mode
—
—
—
—
—
9.4
13
23
—
3.9
0.9
14
5.0
7.0
20
VOLSR.PGAVLS = 1
Deep software standby mode
μA VOLSR.PGAVLS = 1
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
Note 2. Peripheral module clocks are supplied. This does not include operations as BGO (background operations).
Note 3. ICC depends on f (ICLK) as follows.
(when ICLK : PCLKA : PCLKB : PCLKC : PCLKD : BCLK : BCLK pin = 4 : 2 : 1 : 4 : 1 : 1 : 1 and EXTAL = 16 MHz)
• D version product
ICC Max. = 0.375 × f + 15 (full operation in high-speed operating mode)
ICC Typ. = 0.099 × f + 5 (normal operation in high-speed operating mode)
ICC Max. = 0.135 × f + 15 (sleep mode)
Note 4. This does not include operations as BGO (background operations). Whether the peripheral module clocks are supplied or
stopped is controlled only by the bit settings in the module stop control registers A to D.
Note 5. When peripheral module clocks are stopped, each clock frequency is set for division by 64, and the frequencies of FCLK, BCLK,
PCLKA, PCLKB, PCLKC, PCLKD, and the BCLK pin are the same.
Note 6. This is an increase caused by program/erase operation to the code flash memory or data flash memory during executing the
user program.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 132 of 201
RX66T Group
5. Electrical Characteristics
Table 5.7
DC Characteristics (3) (Products with 64 Kbytes of RAM, G version)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
G version
Typ. Max.
Item
Symbol
Unit
Test Conditions
Min.
—
3
Supply
current*1
Full operation*2
ICC
*
—
21
12
82
—
—
mA ICLK = 160 MHz
PCLKA = 80 MHz
PCLKB = 40 MHz
PCLKC = 160 MHz
PCLKD = 40 MHz
FCLK = 40 MHz
Normal
operation
Peripheral module clocks are supplied*4
—
Peripheral module clocks are stopped
—
4,
5
*
*
CoreMark Peripheral module clocks are stopped
—
—
21
18
—
4,
5
*
*
BCLK = 40 MHz
BCLK pin = 40 MHz
Sleep mode: Peripheral module clocks are
supplied*4
42
All module clock stop mode (reference value)
Increase current by BGO operation*6
Increase current by operating Trusted Secure IP
Software standby mode
—
—
—
—
—
9.4
13
28
—
3.9
0.9
14
5.0
11.2
26
VOLSR.PGAVLS = 1
Deep software standby mode
μA VOLSR.PGAVLS = 1
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
Note 2. Peripheral module clocks are supplied. This does not include operations as BGO (background operations).
Note 3. ICC depends on f (ICLK) as follows.
(when ICLK : PCLKA : PCLKB : PCLKC : PCLKD : BCLK : BCLK pin = 4 : 2 : 1 : 4 : 1 : 1 : 1 and EXTAL = 16 MHz)
• G version product
ICC Max. = 0.394 × f + 19 (full operation in high-speed operating mode)
ICC Typ. = 0.099 × f + 5 (normal operation in high-speed operating mode)
ICC Max. = 0.144 × f + 19 (sleep mode)
Note 4. This does not include operations as BGO (background operations). Whether the peripheral module clocks are supplied or
stopped is controlled only by the bit settings in the module stop control registers A to D.
Note 5. When peripheral module clocks are stopped, each clock frequency is set for division by 64, and the frequencies of FCLK, BCLK,
PCLKA, PCLKB, PCLKC, PCLKD, and the BCLK pin are the same.
Note 6. This is an increase caused by program/erase operation to the code flash memory or data flash memory during executing the
user program.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 133 of 201
RX66T Group
5. Electrical Characteristics
Table 5.8
DC Characteristics (3) (Products with 128 Kbytes of RAM, D version)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
D version
Typ. Max.
Item
Symbol
Unit
Test Conditions
Min.
—
3
Supply
current*1
Full operation*2
ICC
*
—
23
14
96
—
—
mA ICLK = 160 MHz
PCLKA = 80 MHz
PCLKB = 40 MHz
PCLKC = 160 MHz
PCLKD = 40 MHz
FCLK = 40 MHz
Normal
operation
Peripheral module clocks are supplied*4
—
Peripheral module clocks are stopped
—
4,
5
*
*
CoreMark Peripheral module clocks are stopped
—
—
23
20
—
4,
5
*
*
BCLK = 40 MHz
BCLK pin = 40 MHz
Sleep mode: Peripheral module clocks are
supplied*4
45
All module clock stop mode (reference value)
Increase current by BGO operation*6
Increase current by operating Trusted Secure IP
Software standby mode
—
—
—
—
—
9.8
14
33
—
3.9
0.9
15
5.3
13.9
21
VOLSR.PGAVLS = 1
Deep software standby mode
μA VOLSR.PGAVLS = 1
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
Note 2. Peripheral module clocks are supplied. This does not include operations as BGO (background operations).
Note 3. ICC depends on f (ICLK) as follows.
(when ICLK : PCLKA : PCLKB : PCLKC : PCLKD : BCLK : BCLK pin = 4 : 2 : 1 : 4 : 1 : 1 : 1 and EXTAL = 16 MHz)
• D version product
ICC Max. = 0.469 × f + 21 (full operation in high-speed operating mode)
ICC Typ. = 0.112 × f + 5 (normal operation in high-speed operating mode)
ICC Max. = 0.15 × f + 21 (sleep mode)
Note 4. This does not include operations as BGO (background operations). Whether the peripheral module clocks are supplied or
stopped is controlled only by the bit settings in the module stop control registers A to D.
Note 5. When peripheral module clocks are stopped, each clock frequency is set for division by 64, and the frequencies of FCLK, BCLK,
PCLKA, PCLKB, PCLKC, PCLKD, and the BCLK pin are the same.
Note 6. This is an increase caused by program/erase operation to the code flash memory or data flash memory during executing the
user program.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 134 of 201
RX66T Group
5. Electrical Characteristics
Table 5.9
DC Characteristics (3) (Products with 128 Kbytes of RAM, G version)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
G version
Typ. Max.
Item
Symbol
Unit
Test Conditions
Min.
—
3
Supply
current*1
Full operation*2
ICC
*
—
23
14
109
—
mA ICLK = 160 MHz
PCLKA = 80 MHz
PCLKB = 40 MHz
PCLKC = 160 MHz
PCLKD = 40 MHz
FCLK = 40 MHz
Normal
operation
Peripheral module clocks are supplied*4
—
Peripheral module clocks are stopped
—
—
4,
5
*
*
CoreMark Peripheral module clocks are stopped
—
—
23
20
—
4,
5
*
*
BCLK = 40 MHz
BCLK pin = 40 MHz
Sleep mode: Peripheral module clocks are
supplied*4
57
All module clock stop mode (reference value)
Increase current by BGO operation*6
Increase current by operating Trusted Secure IP
Software standby mode
—
—
—
—
—
9.8
14
45
—
3.9
0.9
15
5.3
22.1
28
VOLSR.PGAVLS = 1
Deep software standby mode
μA VOLSR.PGAVLS = 1
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
Note 2. Peripheral module clocks are supplied. This does not include operations as BGO (background operations).
Note 3. ICC depends on f (ICLK) as follows.
(when ICLK : PCLKA : PCLKB : PCLKC : PCLKD : BCLK : BCLK pin = 4 : 2 : 1 : 4 : 1 : 1 : 1 and EXTAL = 16 MHz)
• G version product
ICC Max. = 0.50 × f + 29 (full operation in high-speed operating mode)
ICC Typ. = 0.112 × f + 5 (normal operation in high-speed operating mode)
ICC Max. = 0.175 × f + 29 (sleep mode)
Note 4. This does not include operations as BGO (background operations). Whether the peripheral module clocks are supplied or
stopped is controlled only by the bit settings in the module stop control registers A to D.
Note 5. When peripheral module clocks are stopped, each clock frequency is set for division by 64, and the frequencies of FCLK, BCLK,
PCLKA, PCLKB, PCLKC, PCLKD, and the BCLK pin are the same.
Note 6. This is an increase caused by program/erase operation to the code flash memory or data flash memory during executing the
user program.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 135 of 201
RX66T Group
5. Electrical Characteristics
Table 5.10 DC Characteristics (4)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Symbol
AICC
Min. Typ. Max. Unit
Test Conditions
Analog
power
supply
current
Unit 0
Unit 1
Unit 2
During 12-bit A/D conversion
—
—
—
—
—
—
—
—
2.9
1.9
2.0
1.0
2.9
1.9
2.0
1.0
5.1
2.9
4.0
1.5
5.1
2.9
4.0
1.5
mA IAVCC0_AD + SH +
PGA
(Channel-dedicated sample-and-hold
circuits: operation for all channels;
PGA: enabled for all channels)
During 12-bit A/D conversion
IAVCC0_AD + SH
IAVCC0_AD + PGA
IAVCC0_AD
(Channel-dedicated sample-and-hold
circuits: operation for all channels;
PGA: disabled for all channels)
During 12-bit A/D conversion
(Channel-dedicated sample-and-hold
circuits: stopping of all channels;
PGA: enabled for all channels)
During 12-bit A/D conversion
(Channel-dedicated sample-and-hold
circuits: stopping of all channels;
PGA: disabled for all channels)
During 12-bit A/D conversion
IAVCC1_AD + SH +
PGA
(Channel-dedicated sample-and-hold
circuits: operation for all channels;
PGA: enabled for all channels)
During 12-bit A/D conversion
IAVCC1_AD + SH
IAVCC1_AD + PGA
IAVCC1_AD
(Channel-dedicated sample-and-hold
circuits: operation for all channels;
PGA: disabled for all channels)
During 12-bit A/D conversion
(Channel-dedicated sample-and-hold
circuits: stopping of all channels;
PGA: enabled for all channels)
During 12-bit A/D conversion
(Channel-dedicated sample-and-hold
circuits: stopping of all channels;
PGA: disabled for all channels)
During 12-bit A/D conversion with the
temperature sensor operating
—
—
0.9
0.9
1.5
1.5
IAVCC2_AD +
TEMP
During 12-bit A/D conversion with the
temperature sensor stopped
IAVCC2_AD
Comparator (6 channels)
—
—
—
0.5
0.6
0.1
0.6
0.8
0.4
IAVCC2_CMP
IAVCC2_DA
During 12-bit D/A conversion (2 channels)
Waiting for 12-bit A/D, 12-bit D/A, Comparator C, and
temperature sensor conversion (all units)
IAVCC0_AD +
IAVCC1_AD +
IAVCC2_AD +
IAVCC2_DA
12-bit A/D, 12-bit D/A, Comparator C, and temperature
sensor are in module stop status (all units)
—
0.2
14.8
µA IAVCC0_AD +
IAVCC1_AD +
IAVCC2_AD +
IAVCC2_DA
USB
operating
current
Low speed
Full speed
ICCUSBLS
ICCUSBFS
VRAM
—
—
3.6
4.1
—
6.5
10
—
mA VCC_USB = 3.0 to
3.6 V
VCC_USB = 3.0 to
3.6 V
RAM retention voltage
2.7
V
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 136 of 201
RX66T Group
5. Electrical Characteristics
Table 5.11 DC Characteristics (5)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Symbol
SrVCC
Min.
0.02
0.02
Typ.
—
Max.
8
Unit
Test Conditions
VCC ramp rate at power-on
At normal startup
ms/V
Voltage monitoring 0
—
20
reset enabled at
2
startup*1,
*
VCC ramp rate at power fluctuation
Note 1. When OFS1.LVDAS = 0.
dt/dVCC
1.0
—
—
When VCC change
exceeds VCC ±10%
Note 2. Settings of the OFS1 register are not read in boot mode or user boot mode, so turn on the power supply voltage with a ramp rate
at normal startup.
max = 8 ms/V
min = 0.02 ms/V
max = 20 ms/V
Figure 5.1
VCC Ramp Rate at Power-On
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 137 of 201
RX66T Group
5. Electrical Characteristics
Table 5.12 Permissible Output Currents
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Symbol
IOL
Min.
—
Typ.
—
Max.
2.0
2.0
15.0
3
Unit
mA
Permissible low-level output
All output pins (except for Normal drive*1
current (average value per pin) RIIC pins, P43, P47, PH1
to PH3, PH5 to PH7, P50
High drive*2
—
—
Large current output*3
Standard mode
Fast mode
—
—
to P55, and P60 to P65)
RIIC pins
—
—
—
—
6
P43, P47, PH1 to PH3, PH5 to PH7, P50 to P55,
and P60 to P65
—
—
2.0
Permissible low-level output
current (max. value per pin)
All output pins (except for Normal drive*1
—
—
—
—
—
—
—
—
—
—
—
—
4.0
4.0
15.0
3
RIIC pins, P43, P47, PH1
to PH3, PH5 to PH7, P50
Large current output*3
to P55, and P60 to P65)
High drive*2
RIIC pins
Standard mode
Fast mode
6
P43, P47, PH1 to PH3, PH5 to PH7, P50 to P55,
and P60 to P65
4.0
Permissible low-level output
current (total)
Total of all output pins
ΣIOL
IOH
—
—
110
Permissible high-level output
current (average value per pin) P43, P47, PH1 to PH3,
PH5 to PH7, P50 to P55,
All output pins (except for Normal drive*1
—
—
—
—
—
—
—
—
–2.0
–2.0
–5.0
–2.0
High drive*2
Large current output*3
and P60 to P65)
P43, P47, PH1 to PH3, PH5 to PH7, P50 to P55,
and P60 to P65
Permissible high-level output
current (max. value per pin)
All output pins (except for Normal drive*1
—
—
—
—
—
—
—
—
–4.0
–4.0
–5.0
–4.0
P43, P47, PH1 to PH3,
PH5 to PH7, P50 to P55,
Large current output*3
and P60 to P65)
High drive*2
P43, P47, PH1 to PH3, PH5 to PH7, P50 to P55,
and P60 to P65
Permissible high-level output
current (total)
Total of all output pins
ΣIOH
—
—
–35
Caution: To protect the LSI’s reliability, the output current values should not exceed the values in this table.
Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable.
Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to
which high driving ability is fixed.
Note 3. This is the value when large current output is set with a pin for which large current output ability is selectable.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 138 of 201
RX66T Group
5. Electrical Characteristics
Table 5.13 Thermal Resistance Value (Reference)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Thermal resistance
Package
Symbol
Min.
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
32.4
33.8
35.0
36.3
35.7
37.9
0.6
Unit
°C/W JESD51-2 and
JESD51-7 compliant
Test Conditions
144-pin LFQFP (PLQP0144KA-B)
112-pin LQFP (PLQP0112JA-B)
100-pin LFQFP (PLQP0100KB-B)
80-pin LFQFP (PLQP0080KB-B)
80-pin LQFP (PLQP0080JA-A)
64-pin LFQFP (PLQP0064KB-C)
144-pin LFQFP (PLQP0144KA-B)
112-pin LQFP (PLQP0112JA-B)
100-pin LFQFP (PLQP0100KB-B)
80-pin LFQFP (PLQP0080KB-B)
80-pin LQFP (PLQP0080JA-A)
64-pin LFQFP (PLQP0064KB-C)
ja
jt
0.6
0.8
0.8
0.8
0.8
Note:
The values are reference values when the 4-layer printed circuit board is used. Thermal resistance depends on the number of
layers and size of the board. For details, refer to the JEDEC standards.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 139 of 201
RX66T Group
5. Electrical Characteristics
5.4
AC Characteristics
Table 5.14 Operating Frequency
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Symbol
f
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
Max.*3
160
120
60
Unit
Test Conditions
System clock (ICLK)
MHz
Peripheral module clock (PCLKA)
Peripheral module clock (PCLKB)
Peripheral module clock (PCLKC)
Peripheral module clock (PCLKD)
—
—
—
160
60
8*1
8*1
4*2
—
AVCC0 = AVCC1 = AVCC2 ≥ 4.5 V
AVCC0 = AVCC1 = AVCC2 < 4.5 V
40
Flash-IF clock (FCLK)
External bus clock (BCLK)
BCLK pin output
60
60
—
40
VCC ≥ 4.5 V,
High-drive output is selected in the
driving ability control register.
—
—
—
32
—
USB clock (UCLK)
48
Note 1. This restriction is only applied when a 12-bit A/D converter is to be used.
Note 2. This restriction is only applied when flash memory is to be programmed or erased.
Note 3. The maximum frequencies of each clock based on the frequency of ICLK are listed below.
ICLK = 160 MHz, PCLKA = 80 MHz, PCLKB = 40 MHz, PCLKC = 160 MHz, PCLKD = 40 MHz, FCLK = 40 MHz, BCLK =
40 MHz, BCLK pin output = 40 MHz
ICLK = 120 MHz, PCLKA = 120 MHz, PCLKB = 60 MHz, PCLKC = 120 MHz, PCLKD = 60 MHz, FCLK = 60 MHz,
BCLK = 60 MHz, BCLK pin output = 30 MHz
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 140 of 201
RX66T Group
5. Electrical Characteristics
5.4.1
Reset Timing
Table 5.15 Reset Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
ms
RES# pulse
width
Power-on
tRESWP
tRESWD
tRESWS
tRESWF
2.0
0.6
0.3
200
—
—
—
—
—
—
—
—
Figure 5.2
Figure 5.3
Deep software standby mode
Software standby mode
Programming or erasure of the code flash
memory, or programming, erasure or blank
checking of the data flash memory
μs
Other than above
tRESW
tRESWT
tRESW2
200
62
—
—
—
—
63
Waiting time after release from the RES# pin reset
tLcyc
Figure 5.2
Internal reset time
108
116
(independent watchdog timer reset, watchdog timer reset,
software reset)
VCC
RES#
tRESWP
Internal reset signal
(Low is valid)
tRESWT
Figure 5.2
Reset Input Timing at Power-On
tRESWD, tRESWS, tRESWF, tRESW
RES#
Internal reset signal
(Low is valid)
tRESWT
Figure 5.3
Reset Input Timing
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RX66T Group
5. Electrical Characteristics
5.4.2
Clock Timing
Table 5.16 BCLK Pin Output Clock Timing (1)
Conditions: 4.5 V ≤ VCC ≤ 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
ns
BCLK pin output cycle time
tBcyc
tCH
tCL
tCr
25
7.5
7.5
—
—
—
—
—
—
—
—
—
5
Figure 5.4
BCLK pin output high pulse width
BCLK pin output low pulse width
BCLK pin output rising time
BCLK pin output falling time
tCf
—
5
Table 5.17 BCLK Pin Output Clock Timing (2)
Conditions: 2.7 V ≤ VCC < 4.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
ns
BCLK pin output cycle time
tBcyc
tCH
tCL
tCr
31.25
10.625
10.625
—
—
—
—
—
—
—
—
—
5
Figure 5.4
BCLK pin output high pulse width
BCLK pin output low pulse width
BCLK pin output rising time
BCLK pin output falling time
tCf
—
5
tBcyc
tCH
tCf
BCLK pin output
tCr
tCL
Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF
High-drive output is selected by the driving ability control register.
Figure 5.4
BCLK Pin Output Timing
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RX66T Group
5. Electrical Characteristics
Table 5.18 EXTAL Clock Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
EXTAL external clock input cycle time
EXTAL external clock input frequency
EXTAL external clock input high pulse width
EXTAL external clock input low pulse width
EXTAL external clock rising time
tEXcyc
fEXMAIN
tEXH
41.66
—
—
—
—
—
—
—
—
24
—
—
5
ns
MHz
ns
Figure 5.5
15.83
15.83
—
tEXL
tEXr
EXTAL external clock falling time
tEXf
—
5
tEXcyc
tEXH
tEXL
EXTAL external clock input
0.5 × VCC
tEXr
tEXf
Figure 5.5
EXTAL External Clock Input Timing
Table 5.19 Main Clock Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Main clock oscillation frequency
fMAIN
8
—
—
—
24
MHz
ms
Main clock oscillator stabilization time (crystal)
Main clock oscillation stabilization wait time (crystal)
tMAINOSC
tMAINOSCWT
—
—
—*1
—*2
Figure 5.6
Note 1. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles selected by the value of the MOSCWTCR.MSTS[7:0] bits determines the main clock oscillation
stabilization wait time in accord with the formula below.
tMAINOSCWT = [(MSTS[7:0] bits × 32) + 7] / fLOCO
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
tMAINOSCWT
OSCOVFSR.MOOVF
Main clock
Figure 5.6
Main Clock Oscillation Start Timing
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RX66T Group
5. Electrical Characteristics
Table 5.20 LOCO and IWDT-Dedicated Low-Speed Clock Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
LOCO clock cycle time
tLcyc
fLOCO
tLOCOWT
tILcyc
fILOCO
tILOCOWT
3.78
216
—
4.16
240
—
4.63
264
44
μs
kHz
μs
LOCO clock oscillation frequency
LOCO clock oscillation stabilization time
IWDT-dedicated low-speed clock cycle time
IWDT-dedicated low-speed clock oscillation frequency
Figure 5.7
Figure 5.8
7.57
108
—
8.33
120
142
9.26
132
190
kHz
μs
IWDT-dedicated low-speed clock oscillation stabilization wait
time
LOCOCR.LCSTP
On-chip oscillator output
tLOCOWT
LOCO clock
Figure 5.7
LOCO Clock Oscillation Start Timing
ILOCOCR.ILCSTP
IWDT-dedicated on-chip
oscillator output
tILOCOWT
OSCOVFSR.ILCOVF
IWDT-dedicated
low-speed clock
Figure 5.8
IWDT-dedicated Low-Speed Clock Oscillation Start Timing
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RX66T Group
5. Electrical Characteristics
Table 5.21 HOCO Clock Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Symbol
fHOCO
Min.
15.61
17.56
19.52
15.52
17.46
19.40
—
Typ.
16
Max.
16.39
18.44
20.48
16.48
18.54
20.60
149
Unit
Test Conditions
HOCO clock oscillation frequency
MHz
–20°C ≤ Ta ≤ 105°C
18
20
16
–40°C ≤ Ta < –20°C
18
20
HOCO clock oscillation stabilization wait time
HOCO clock power supply stabilization time
tHOCOWT
tHOCOP
105
—
μs
Figure 5.9
—
150
Figure 5.10
HOCOCR.HCSTP
High-speed on-chip
oscillator output
tHOCOWT
OSCOVFSR.HCOVF
HOCO clock
Figure 5.9
HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the
HOCOCR.HCSTP Bit)
HOCOPCR.HOCOPCNT
HOCOCR.HCSTP
tHOCOP
Internal power supply for
high-speed on-chip oscillator
Figure 5.10
High-Speed On-Chip Oscillator Power Supply Control Timing
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Feb 08, 2019
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RX66T Group
5. Electrical Characteristics
Table 5.22 PLL Clock Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
PLL clock oscillation frequency
fPLL
120
—
—
240
320
MHz
μs
PLL clock oscillation stabilization wait time
tPLLWT
259
Figure 5.11
PLLCR2.PLLEN
PLL circuit output
tPLLWT
OSCOVFSR.PLOVF
PLL clock
Figure 5.11
PLL Clock Oscillation Start Timing
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RX66T Group
5. Electrical Characteristics
5.4.3
Timing of Recovery from Low Power Consumption Modes
Table 5.23 Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Max.
Test
Conditions
Item
Recovery time Crystal
Symbol Min. Typ.
tSBYMC
Unit
2
3
tSBYOSCWT
*
tSBYSEQ*
Main clock
oscillator
operating
—
—
{(MSTS[7:0] bits ×
32) + 76} / 0.216
100 + 7 / fICLK
2n / fMAIN
+
+
μs Figure 5.12
after
resonator
cancellation of connected to
software
standby
mode*1
main clock
oscillator
Main clock
oscillator and
PLL circuit
operating
tSBYPC
{(MSTS[7:0] bits ×
32) + 138} / 0.216
100 + 7 / fICLK
2n / fPLL
External clock Main clock
input to main oscillator
clock oscillator operating
tSBYEX
352
639
100 + 7 / fICLK
2n / fEXMAIN
+
+
Main clock
oscillator and
PLL circuit
operating
tSBYPE
100 + 7 / fICLK
2n / fPLL
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating
tSBYHO
454
741
100 + 7 / fICLK
2n / fHOCO
+
+
High-speed
on-chip
tSBYPH
100 + 7 / fICLK
2n / fPLL
oscillator
operatingand
PLL circuit
operating
Low-speed on-chip oscillator
operating*4
tSBYLO
338
100 + 7 / fICLK
2n / fLOCO
+
Note 1. The time for return after release from software standby is determined by the value obtained by adding the oscillation stabilization
waiting time (tSBYOSCWT) and the time required for operations by the software standby release sequencer (tSBYSEQ).
Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization
waiting time tSBYOSCWT is selected.
Note 3. For n, the greatest value is selected from among the internal clock division settings.
Note 4. This condition applies when fICLK : fFCLK = 1 : 1, 2 : 1, or 4 : 1.
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RX66T Group
5. Electrical Characteristics
Oscillator
(System clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(Other than the system clock)
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower
Oscillator
(System clock)
tSBYSEQ
tSBYOSCWT
Oscillator
(Other than the system clock)
tSBYOSCWT
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower
Figure 5.12
Software Standby Mode Cancellation Timing
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Page 148 of 201
RX66T Group
5. Electrical Characteristics
Table 5.24 Timing of Recovery from Low Power Consumption Modes (2)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Test
Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Recovery time after cancellation of deep software standby mode
Wait time after cancellation of deep software standby mode
tDSBY
—
—
—
0.9
32
ms
Figure 5.13
tDSBYWT
31
tLcyc
Oscillator
IRQ
Deep software standby reset
(Low is valid)
Internal reset
(Low is valid)
Deep software standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 5.13
Deep Software Standby Mode Cancellation Timing
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RX66T Group
5. Electrical Characteristics
5.4.4
Control Signal Timing
Table 5.25 Control Signal Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
T = T
a
opr
Item
Symbol
tNMIW
Min.*1
200
Typ.
—
Max.
—
Unit
ns
Test Conditions*1
NMI pulse width
2 × tPBcyc ≤ 200 ns, Figure 5.14
2 × tPBcyc > 200 ns, Figure 5.14
2 × tPBcyc ≤ 200 ns, Figure 5.15
2 × tPBcyc > 200 ns, Figure 5.15
2 × tPBcyc
200
—
—
IRQ pulse width
tIRQW
—
—
2 × tPBcyc
—
—
Note 1. tPBcyc: PCLKB cycle
NMI
tNMIW
tNMIW
Figure 5.14
NMI Interrupt Input Timing
IRQn
tIRQW
tIRQW
Figure 5.15
IRQ Interrupt Input Timing
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RX66T Group
5. Electrical Characteristics
5.4.5
Bus Timing
Table 5.26 Bus Timing (1)
Conditions: 4.5 V ≤ VCC ≤ 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Item
Symbol
tAD
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
12.5
12.5
12.5
12.5
12.5
—
Unit
ns
Test Conditions
Address delay time
Figure 5.16 to
Figure 5.21
Byte control delay time
CS# delay time
tBCD
tCSD
tALED
tRSD
tRDS
tRDH
tWRD
tWDD
tWDH
tWTS
tWTH
—
—
ALE delay time
—
RD# delay time
—
Read data setup time
Read data hold time
WR# delay time
12.5
0
—
—
12.5
12.5
—
Write data delay time
Write data hold time
WAIT# setup time
WAIT# hold time
—
0
12.5
0
—
Figure 5.22
—
Table 5.27 Bus Timing (2)
Conditions: 2.7 V ≤ VCC < 4.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Item
Symbol
tAD
Min.
—
—
—
—
—
25
0
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
25
25
25
25
25
—
Unit
ns
Test Conditions
Address delay time
Figure 5.16 to
Figure 5.21
Byte control delay time
CS# delay time
tBCD
tCSD
tALED
tRSD
tRDS
tRDH
tWRD
tWDD
tWDH
tWTS
tWTH
ALE delay time
RD# delay time
Read data setup time
Read data hold time
WR# delay time
—
—
—
0
25
25
—
Write data delay time
Write data hold time
WAIT# setup time
WAIT# hold time
25
0
—
Figure 5.22
—
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RX66T Group
5. Electrical Characteristics
Data cycle
Tend
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
Tn1
Tn2
TW5
BCLK
tAD
Address bus
tRDS tRDH
tAD
tAD
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tRSD
tRSD
Data read
(RD#)
tCSD
tCSD
Chip select
(CS1#)
Figure 5.16
Address/Data Multiplexed Bus Read Access Timing
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
Tend
Tn1
Tn2
tWDH
tWRD
Tn3
TW5
BCLK
tAD
Address bus
tAD
tWDD
tAD
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tWRD
Data write
(WRm#)
tCSD
tCSD
Chip select
(CS1#)
Figure 5.17
Address/Data Multiplexed Bus Write Access Timing
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RX66T Group
5. Electrical Characteristics
CSRWAIT:2
RDON:1
CSON:0
CSROFF:2
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
A20 to A0
A20 to A1
1-write strobe mode
tAD
tAD
tBCD
tBCD
BC1#, BC0#
Common to both byte strobe mode
and 1-write strobe mode
tCSD
tCSD
CS3# to CS0#
tRSD
tRSD
RD# (Read)
tRDS
tRDH
D15 to D0 (Read)
Figure 5.18
External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)
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RX66T Group
5. Electrical Characteristics
CSWWAIT:2
WRON:1
WDON:1 *1
CSWOFF:2
WDOFF:1 *1
Tn1
CSON:0
TW1
TW2
Tend
Tn2
BCLK
Byte strobe mode
tAD
tAD
A20 to A0
A20 to A1
1-write strobe mode
tAD
tAD
tBCD
tBCD
BC1#, BC0#
Common to both byte strobe mode
and 1-write strobe mode
tCSD
tCSD
CS3# to CS0#
tWRD
tWRD
WR1#, WR0#, WR# (Write)
tWDD
tWDH
D15 to D0 (Write)
Note 1. Specify WDON and WDOFF as at least one cycle of BCLK.
Figure 5.19
External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)
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RX66T Group
5. Electrical Characteristics
CSRWAIT:2
RDON:1
CSON:0
CSPRWAIT:2
RDON:1
CSPRWAIT:2
RDON:1
CSPRWAIT:2
RDON:1
CSROFF:2
TW1
TW2
Tend
Tpw1
Tpw2
Tend
Tpw1
Tpw2
Tend
Tpw1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tAD
A20 to A0
A20 to A1
1-write strobe mode
tAD
tAD
tAD
tAD
tAD
tBCD
tBCD
BC1#, BC0#
Common to both byte strobe mode
and 1-write strobe mode
tCSD
tCSD
CS3# to CS0#
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
RD# (Read)
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
D15 to D0 (Read)
Figure 5.20
External Bus Timing/Page Read Cycle (Bus Clock Synchronized)
CSPWWAIT:2
CSPWWAIT:2
CSWOFF:2
CSWWAIT:2
WRON:1
WDON:1 *1
CSON:0
WRON:1
WRON:1
WDOFF:1 *1
Tdw1
WDOFF:1 *1
Tn1
WDOFF:1 *1
Tdw1
WDON:1 *1
Tpw1
WDON:1 *1
Tpw1
TW2
Tend
Tpw2
Tpw2
TW1
Tend
Tend
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
A20 to A0
A20 to A1
1-write strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
BC1#, BC0#
Common to both byte strobe mode
and 1-write strobe mode
tCSD
tCSD
CS3# to CS0#
tWRD
tWRD
tWRD
tWRD
tWRD
tWRD
WR1#, WR0#, WR# (Write)
D15 to D0 (Write)
tWDD
tWDD
tWDD
tWDH
tWDH
tWDH
Note 1. Specify WDON and WDOFF as at least one cycle of BCLK.
Figure 5.21
External Bus Timing/Page Write Cycle (Bus Clock Synchronized)
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RX66T Group
5. Electrical Characteristics
CSRWAIT:3
CSWWAIT:3
TW1
TW2
TW3
(Tend
)
Tend
Tn1
Tn2
BCLK
A20 to A0
CS3# to CS0#
RD# (Read)
WR# (Write)
External wait
tWTS tWTH tWTS tWTH
WAIT#
Figure 5.22
External Bus Timing/External Wait Control
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RX66T Group
5. Electrical Characteristics
5.4.6
Timing of On-Chip Peripheral Modules
Table 5.28 I/O Port Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Test
Conditions
Item
Symbol
tPRW
Min.
1.5
Max.
—
Unit*1
tPBcyc
I/O ports
Input data pulse width
Figure 5.23
Note 1. tPBcyc: PCLKB cycle
PCLKB
Port
tPRW
Figure 5.23
I/O Port Input Timing
Table 5.29 TMR Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Test
Conditions
Item
Symbol
Min.
1.5
Max.
—
Unit*1
tPBcyc
TMR
Timer clock pulse width
Single-edge
setting
tTMCWH,
tTMCWL
Figure 5.24
Both-edge
setting
2.5
—
Note 1. tPBcyc: PCLKB cycle
PCLKB
TMCI0 to TMCI7
tTMCWL
tTMCWH
Figure 5.24
TMR Clock Input Timing
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Feb 08, 2019
Page 157 of 201
RX66T Group
5. Electrical Characteristics
Table 5.30 MTU Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Test
Conditions
Item
Symbol
tMTICW
Min.
1.5
Max.
—
Unit*1
tPCcyc
MTU
Input capture input pulse
width
Single-edge
setting
Figure 5.25
Both-edge
setting
2.5
1.5
2.5
2.5
—
—
—
—
Timer clock pulse width
Single-edge
setting
tMTCKWH,
tMTCKWL
tPCcyc
Figure 5.26
Both-edge
setting
Phase counting
mode
Note 1. tPCcyc: PCLKC cycle
PCLKC
Input capture
input
tMTICW
Figure 5.25
MTU Input Capture Input Timing
PCLKC
MTCLKA to
MTCLKD,
MTIOC1A
tMTCKWL
tMTCKWH
Figure 5.26
MTU Clock Input Timing
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Feb 08, 2019
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RX66T Group
5. Electrical Characteristics
Table 5.31 POE and POEG Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
1
Item
Symbol
Min. Typ.
Max.
—
Unit*
Test Conditions
Figure 5.27
POE
POEn# input pulse width
(n = 0, 4, and 8 to 14)
t
1.5
—
—
—
t
POEW
PBcyc
µs
Output disable time
Transition of the POEn#
t
5 PCLKB + 0.24
Figure 5.28
POEDI
signal level
When detecting falling edges
(ICSRm.POEnM[3:0] = 0000
(m = 1 to 5, 7 to 9, n = 0, 4, 8 to
14))
Simultaneous conduction
of output pins
t
—
—
—
—
3 PCLKB + 0.2
5 PCLKB + 0.2
µs
µs
Figure 5.29
POEDO
Detection of comparator
outputs
t
Figure 5.30
POEDC
The time is that when the noise
filter for comparator C is not in
use (CMPCTL.CDFS[1:0] = 00)
and excludes the time for
detection by comparator C.
Register setting
t
—
—
1 PCLKB + 0.2
µs
µs
Figure 5.31
Time for access to the register is
not included.
POEDS
Oscillation stop detection
t
—
1.5
—
—
—
—
21
—
Figure 5.32
Figure 5.33
POEDOS
POEG
GTETRGn input pulse width (n = A to D)
Output disable time Input level detection of the
t
t
POEGW
POEGDI
PBcyc
t
3 PCLKB + 0.34
µs
Figure 5.34
GTETRGn pin (via flag)
When the digital noise filter is not
in use (POEGGn.NFEN = 0
(n = A to D))
Detection of the output
stopping signal from
GPTW (deadtime error,
simultaneous high output,
or simultaneous low out-
put)
t
—
—
—
—
—
—
0.5
µs
µs
µs
Figure 5.35
POEGDE
POEGDC
Edge detection signal from
a comparator
t
4 PCLKB + 0.5
Figure 5.36
The time is that when the noise
filter for comparator C is not in
use (CMPCTL.CDFS[1:0] = 00)
and excludes the time for
detection by comparator C.
Register setting
t
1 PCLKB + 0.3
21
Figure 5.37
Time for access to the register is
not included.
POEGDS
Oscillation stop detection
t
t
—
—
—
—
µs
µs
Figure 5.38
Figure 5.39
POEGDOS
Input level detection of the
GTETRGn pin (direct path)
t
2 PCLKB +
1 PCLKC + 0.34
POEGDDI
Level detection signal from
a comparator
—
—
3 PCLKB + 0.3
µs
Figure 5.40
POEGDDC
The time is that when the noise
filter for comparator C is not in
use (CMPCTL.CDFS[1:0] = 00)
and excludes the time for
detection by comparator C.
Note 1. tPBcyc: PCLKB cycle
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Feb 08, 2019
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5. Electrical Characteristics
PCLKB
POEn# input
(n = 0, 4, 8 to 14)
tPOEW
Figure 5.27
POE Input Timing
POEn# input
(n = 0, 4, 8 to 14)
tPOEW
Outputs disabled
MTU PWM output pins
GPTW PWM output pins
tPOEDI
Figure 5.28
Output Disable Time for POE in Response to Transition of the POEn# Signal Level
Simultaneous active-level outputs detected*1
MTU PWM output pins
GPTW PWM output pins
Outputs
disabled
tPOEDO
Note 1. When the active level is set to low.
Figure 5.29
Output Disable Time for POE in Response to the Simultaneous Conduction of Output
Pins
COMPn level detection
signal (n = 0 to 5)
Outputs disabled
MTU PWM output pins
GPTW PWM output pins
tPOEDC
Figure 5.30
Output Disable Time for POE in Response to Detection of the Comparator Outputs
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
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RX66T Group
5. Electrical Characteristics
Corresponding bit in
the SPOER register
Outputs disabled
MTU PWM output pins
GPTW PWM output pins
tPOEDS
Figure 5.31
Output Disable Time for POE in Response to the Register Setting
Main clock
Oscillation stop detection
signal (internal signal)
Outputs disabled
MTU PWM output pins
GPTW PWM output pins
tPOEDOS
Figure 5.32
Output Disable Time for POE in Response to the Oscillation Stop Detection
PCLKB
GTETRGn input
(n = A to D)
tPOEGW
Figure 5.33
POEG Input Timing
GTETRGn input
(n = A to D)
tPOEGW
POEGGn.PIDF flag
(n = A to D)
Outputs disabled
GPTW PWM output pins
tPOEGDI
Figure 5.34
Output Disable Time for POEG via Detection Flag in Response to the Input Level
Detection of the GTETRGn pin
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Feb 08, 2019
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5. Electrical Characteristics
Output stopping signal
from GPTW*1
Outputs disabled
GPTW PWM output pins
tPOEGDE
Note 1. GPTWn.GTST.DTEF (dead time error flag), GPTWn.GTST.OABLF (simultaneous low output flag),
or GPTWn.GTST.OABHF (simultaneous high output flag)
Figure 5.35
Output Disable Time for POEG in Response to Detection of the Output Stopping Signal
from GPTW
COMPn edge detection
signal (n = 0 to 5)
Outputs disabled
GPTW PWM output pins
tPOEGDC
Figure 5.36
Output Disable Time for POEG in Response to Edge Detection Signal from a
Comparator
POEGGn.SSF bit
(n = A to D)
Outputs disabled
GPTW PWM output pins
tPOEGDS
Figure 5.37
Output Disable Time for POEG in Response to the Register Setting
Main clock
Oscillation stop detection
signal (internal signal)
Outputs disabled
GPTW PWM output pins
tPOEGDOS
Figure 5.38
Output Disable Time of POEG in Response to the Oscillation Stop Detection
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Feb 08, 2019
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RX66T Group
5. Electrical Characteristics
GTETRGn input
(n = A to D)
tPOEGW
Outputs disabled
GPTW PWM output pins
tPOEGDDI
Figure 5.39
Output Disable Time for POEG in Direct Response to the Input Level Detection of the
GTETRGn pin
COMPn level detection
signal (n = 0 to 5)
Outputs disabled
GPTW PWM output pins
tPOEGDDC
Figure 5.40
Output Disable Time for POEG in Response to Level Detection Signal from a
Comparator
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Feb 08, 2019
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RX66T Group
5. Electrical Characteristics
Table 5.32 GPTW Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Test
Conditions
2
Item
Symbol
tGTICW
Min.
Max.
Unit*1,
*
GPTW
Input capture input pulse
width
Single-edge setting
Both-edge setting
Single-edge setting
Both-edge setting
1.5
2.5
1.5
2.5
1.5
—
—
—
—
—
tPCcyc
tPBcyc
tPBcyc
Figure 5.41
External trigger input pulse
width
tGTEW
Figure 5.42
Figure 5.43
Timer clock pulse width
tGTCKWH
tGTCKWL
Note 1. tPCcyc: PCLKC cycle
Note 2. tPBcyc: PCLKB cycle
PCLKC
Input capture
input
tGTICW
Figure 5.41
GPTW Input Capture Input Timing
PCLKB
GTETRGn input
(n = A to D)
tGTEW
Figure 5.42
GPTW External Trigger Input Timing
PCLKB
GTETRGn input
(n = A to D)
tGTCKWL
tGTCKWH
Figure 5.43
GPTW Clock Input Timing
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Feb 08, 2019
Page 164 of 201
RX66T Group
5. Electrical Characteristics
Table 5.33 A/D Converter Trigger Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Test
Conditions
Item
Symbol
tTRGW
Min.
1.5
Max.
—
Unit*1
tPBcyc
A/D
converter
A/D converter trigger input pulse width
Figure 5.44
Note 1. tPBcyc: PCLKB cycle
PCLKB
ADTRG0#,
ADTRG1#,
ADTRG2#
tTRGW
Figure 5.44
A/D Converter Trigger Input Timing
Table 5.34 CAC Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Test
Conditions
2
2
Item*1,
*
Symbol
tCACREF
Min.*1,
*
Max.
Unit
ns
CAC
CACREF input pulse width
t
PBcyc ≤ tcac
4.5 tcac + 3 tPBcyc
5 tcac + 6.5 tPBcyc
—
—
tPBcyc > tcac
Note 1. tPBcyc: PCLKB cycle
Note 2. cac: CAC count clock source cycle
t
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Feb 08, 2019
Page 165 of 201
RX66T Group
5. Electrical Characteristics
Table 5.35 SCIj, SCIh, and SCIi Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Item
Symbol
tScyc
Min.
4
Max.
—
—
0.6
5
Unit*1
Test Conditions
SCIj, SCIh Input clock cycle
Asynchronous
tPBcyc Figure 5.45
Clock synchronous
6
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
tSCKW
tSCKr
tSCKf
tScyc
0.4
—
—
8
tScyc
ns
5
ns
Asynchronous*2
—
—
0.6
5
tPBcyc
Clock synchronous
4
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
tSCKW
tSCKr
tSCKf
tTXD
0.4
—
—
—
—
15
20
5
tScyc
ns
5
ns
Clock synchronous
Clock synchronous
28
33
—
—
—
—
—
0.6
5
ns
ns
ns
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Figure 5.46
Figure
5.46
Receive data setup time
tRXS
Figure
5.46
Receive data hold time
Input clock cycle
Clock synchronous
Asynchronous
tRXH
tScyc
SCIi
4
tPAcyc Figure 5.45
Clock synchronous
6
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
tSCKW
tSCKr
tSCKf
tScyc
0.4
—
—
6
tScyc
ns
5
ns
Asynchronous*2
—
—
0.6
5
tPAcyc
Clock synchronous
4
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
tSCKW
tSCKr
tSCKf
tTXD
0.4
—
—
—
—
—
—
15
20
5
tScyc
ns
5
ns
Master
15
28
20
33
—
—
—
ns
VCC ≥ 4.5 V
VCC < 4.5 V
Figure
5.46
Slave
Master
Slave
Receive data setup time
Receive data hold time
Clock synchronous
tRXS
ns
ns
VCC ≥ 4.5 V
VCC < 4.5 V
Figure 5.46
Figure
5.46
Clock synchronous
tRXH
Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle
Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1
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5. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 1, 5, 6, 8, 9, 11, and 12)
tScyc
Figure 5.45
SCK Clock Input Timing
SCKn
tTXD
TxDn
tRXS tRXH
RxDn
n = 1, 5, 6, 8, 9, 11, and 12
Figure 5.46
SCI Input/Output Timing: Clock Synchronous Mode
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RX66T Group
5. Electrical Characteristics
Table 5.36 RSPI Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Item
Symbol
tSPcyc
Min.*1
Max.*1
4096
—
Unit*1
Test Conditions
RSPI RSPCK clock
cycle
Master
Slave
2
4
tPAcyc Figure 5.47
RSPCK clock
high pulse width
Master
tSPCKWH (tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
ns
ns
ns
ns
Slave
Master
Slave
(tSPcyc – tSPCKr
– tSPCKf) / 2
—
—
—
RSPCK clock
low pulse width
tSPCKWL (tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
(tSPcyc – tSPCKr
– tSPCKf) / 2
RSPCK clock
rise/fall time
Output
Input
tSPCKr,
tSPCKf
—
—
6
5
ns
μs
1
Data input setup Master
time
tSU
—
—
—
—
ns
VCC ≥ 4.5 V Figure 5.48 to
Figure 5.53
11
8.3
0
VCC < 4.5 V
Slave
Figure 5.48 to Figure 5.53
Data input hold
time
PCLKA division
ratio set to 1/2
tHF
tH
ns
PCLKA division
ratio set to a value
other than 1/2
tPAcyc
—
Slave
8.3
1
—
8
SSL setup time Master
Slave
tLEAD
tLAG
tOD
tSPcyc
tPAcyc
tSPcyc
tPAcyc
ns
6
—
SSL hold time
Master
Slave
1
8
6
—
Data output
delay time
Master
Slave
—
—
—
—
0
6.3
28
11.3
33
—
VCC ≥ 4.5 V Figure 5.48 to
Figure 5.53
Master
Slave
ns
ns
ns
VCC < 4.5 V
Data output hold Master
tOH
Figure 5.48 to Figure 5.53
time
Slave
0
—
Successive
transmission
delay time
Master
tTD
tSPcyc + 2 ×
tPAcyc
8 × tSPcyc
+ 2 × tPAcyc
Slave
6 × tPAcyc
—
MOSI and MISO Output
tDr, tDf
—
—
—
—
—
—
—
—
5
ns
μs
ns
μs
ns
rise/fall time
Input
1
SSL
rise/fall time
Output
Input
tSSLr,
5
tSSLf
1
Slave access time
tSA
2 × tPAcyc + 28
2 × tPAcyc + 33
2 × tPAcyc + 28
2 × tPAcyc + 33
VCC ≥ 4.5 V Figure 5.52,
Figure 5.53
VCC < 4.5 V
Slave output release time
tREL
ns
VCC ≥ 4.5 V
VCC < 4.5 V
Note 1. tPAcyc: PCLKA cycle
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5. Electrical Characteristics
Table 5.37 Simple SPI Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Test
Item
Symbol
tSPcyc
Min.
Max.
Unit*1
tPAcyc
Conditions
Figure 5.47
Simple
SPI
(SCI11)
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
Data input setup time
Data input hold time
4
8
65536
—
tSPCKWH
tSPCKWL
tSPCKr, tSPCKf
tSU
0.4
0.4
—
0.6
0.6
20
tSPcyc
tSPcyc
ns
33.3
33.3
1
—
ns
Figure 5.48 to
Figure 5.53
tH
—
ns
SS input setup time
tLEAD
—
tSPcyc
tSPcyc
ns
SS input hold time
tLAG
1
—
Data output delay time
Data output hold time
Data rise/fall time
tOD
—
33.3
—
tOH
–10
—
ns
tDr, tDf
16.6
16.6
7
ns
SS input rise/fall time
Slave access time
t
SSLr, tSSLf
tSA
—
ns
—
tPAcyc
tPAcyc
tPBcyc
Figure 5.52,
Figure 5.53
Slave output release time
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
Data input setup time
Data input hold time
tREL
—
7
Simple
SPI
tSPcyc
4
65536
—
Figure 5.47
8
(SCI1,
SCI5,
SCI6,
SCI8,
SCI9,
SCI12)
tSPCKWH
tSPCKWL
0.4
0.4
—
0.6
0.6
20
tSPcyc
tSPcyc
ns
tSPCKr, tSPCKf
tSU
tH
33.3
33.3
1
—
ns
Figure 5.48 to
Figure 5.53
—
ns
SS input setup time
tLEAD
tLAG
tOD
—
tSPcyc
tSPcyc
ns
SS input hold time
1
—
Data output delay time
Data output hold time
Data rise/fall time
—
33.3
—
tOH
–10
—
ns
tDr, tDf
16.6
16.6
7
ns
SS input rise/fall time
Slave access time
t
SSLr, tSSLf
tSA
—
ns
—
tPBcyc
tPBcyc
Figure 5.52,
Figure 5.53
Slave output release time
tREL
—
7
Note 1. tPAcyc: PCLKA cycle, tPBcyc: PCLKB cycle
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RX66T Group
5. Electrical Characteristics
tSPCKr
tSPCKf
tSPCKWH
Simple SPI
RSPI
RSPCKA
master select
output
VOH
VOH
VOL
VOH
VOH
SCKn
master select
output
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKf
tSPCKWH
VIH
VIH
VIL
VIH
VIH
SCKn
slave select input
RSPCKA
slave select input
VIL
tSPCKWL
VIL
(n = 1, 5, 6, 8, 9, 11, 12)
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 5.47
RSPI Clock Timing and Simple SPI Clock Timing
Simple SPI
RSPI
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
SCKn
CKPOL = 0
output
RSPCKA
CPOL = 1
output
SCKn
CKPOL = 1
output
tSU
tH
MISOA
input
SMISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD
MOSIA
output
SMOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
(n = 1, 5, 6, 8, 9, 11, 12)
Figure 5.48
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other
Than 1/2) and Simple SPI Timing (Master, CKPH = 1)
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5. Electrical Characteristics
RSPI
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
tHF
tHF
MISOA
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD
MOSIA
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Figure 5.49
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to 1/2)
Simple SPI
RSPI
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
SCKn
CKPOL = 1
output
RSPCKA
CPOL = 1
output
SCKn
CKPOL = 0
output
tSU
tH
MISOA
input
SMISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIA
output
SMOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
(n = 1, 5, 6, 8, 9, 11, 12)
Figure 5.50
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to a Value Other
Than 1/2) and Simple SPI Timing (Master, CKPH = 0)
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5. Electrical Characteristics
RSPI
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
tHF
tH
MISOA
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIA
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Figure 5.51
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2)
Simple SPI
RSPI
tTD
SSLA0
input
SSn#
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
SCKn
CKPOL = 0
input
RSPCKA
CPOL = 1
input
SCKn
CKPOL = 1
input
tSA
tOH
tOD
tREL
MISOA
output
SMISOn
output
MSB OUT
DATA
LSB OUT
LSB IN
MSB IN
MSB OUT
tSU
tH
tDr, tDf
MOSIA
input
SMOSIn
input
MSB IN
DATA
MSB IN
(n = 1, 5, 6, 8, 9, 11, 12)
Figure 5.52
RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)
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RX66T Group
5. Electrical Characteristics
Simple SPI
RSPI
tTD
SSLA0
input
SSn#
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
SCKn
CKPOL = 1
input
RSPCKA
CPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
tREL
MISOA
output
SMISOn
output
LSB OUT
(Last data)
MSB OUT
tH
DATA
LSB OUT
MSB OUT
tSU
tDr, tDf
MOSIA
input
SMOSIn
input
MSB IN
DATA
LSB IN
MSB IN
(n = 1, 5, 6, 8, 9, 11, 12)
Figure 5.53
RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)
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5. Electrical Characteristics
Table 5.38 RIIC Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Symbol
*
Test
Conditions*3
Item
Min.*1
Max.*1
Unit
2
RIIC
(Standard-mode,
SMBus)
SCL input cycle time
tSCL
tSCLH
tSCLL
tSr
6(12) × tIICcyc + 1300
—
ns Figure 5.54
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
3(6) × tIICcyc + 300
—
3(6) × tIICcyc + 300
—
—
1000
tSf
—
300
tSP
0
3(6) × tIICcyc + 300
tIICcyc + 300
1000
1(4) × tIICcyc
tBUF
tSTAH
tSTAS
tSTOS
tSDAS
tSDAH
Cb
—
—
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
—
1000
—
tIICcyc + 50
0
—
Data input hold time
—
SCL, SDA capacitive load
SCL input cycle time
—
400
—
pF
ns
RIIC
(Fast-mode)
tSCL
tSCLH
tSCLL
tSr
6(12) × tIICcyc + 600
3(6) × tIICcyc + 300
3(6) × tIICcyc + 300
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
—
—
20 × (External pull-up
voltage/5.5V)
300
SCL, SDA input fall time
tSf
20 × (External pull-up
voltage/5.5V)
300
SCL, SDA input spike pulse removal time
SDA input bus free time
tSP
0
1(4) × tIICcyc
tBUF
3(6) × tIICcyc + 300
—
—
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
tSTAH
tSTAS
tSTOS
tSDAS
tSDAH
Cb
tIICcyc + 300
300
—
300
—
tIICcyc + 50
—
Data input hold time
0
—
SCL, SDA capacitive load
—
400
pF
Note:
tIICcyc: RIIC internal reference clock (IICφ) cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
Note 3. When VCC ≥ 4.5V, VOLSR.RICVLS = 0
When VCC < 4.5V, VOLSR.RICVLS = 1
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5. Electrical Characteristics
Table 5.39 Simple IIC Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Item
Symbol*1
tSr
Min.
—
—
0
Max.*2
1000
300
Unit
ns
Test Conditions
Figure 5.54
Simple IIC
(Standard-mode)
SSDA input rise time
SSDA input fall time
tSf
SSCL, SSDA input spike pulse removal time
Data input setup time
tSP
4 × tPcyc
—
tSDAS
tSDAH
Cb
250
0
Data input hold time
—
SSCL, SSDA capacitive load
SSDA input rise time
—
—
—
0
400
pF
ns
Simple IIC
(Fast-mode)
tSr
300
SSDA input fall time
tSf
300
SSCL, SSDA input spike pulse removal time
Data input setup time
tSP
4 × tPcyc
—
tSDAS
tSDAH
Cb
100
0
Data input hold time
—
SSCL, SSDA capacitive load
—
400
pF
Note 1. Cb is the total capacitance of the bus lines.
Note 2.
t
Pcyc: For SCI11, this is the period of PCLKA, and for SCI1, 5, 6, 8, 9, and 12, this is the period of PCLKB.
VIH
SDA0, SSDAn
(n = 1, 5, 6, 8, 9, 11, 12)
VIL
tBUF
tSCLH
tSTAS
tSTOS
tSTAH
tSP
SCL0, SSCLn
(n = 1, 5, 6, 8, 9, 11, 12)
P*1
P*1
S*1
Sr*1
tSCLL
tSr
tSf
tSDAS
tSCL
tSDAH
Test conditions
IH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
VOL = 0.4 V, IOL = 3 mA
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
V
P: Stop condition
Sr: Restart condition
Figure 5.54
RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output
Timing
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5. Electrical Characteristics
Table 5.40 HRPWM Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
opr
a
ICLK = 8 to 160 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 160 MHz, BCLK = 8 to 60 MHz,
Output load conditions: V = 0.5 × VCC, V = 0.5 × VCC, C = 30 pF,
OH
OL
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Item
Min.
80
Typ.
—
Max.
160
—
Unit
MHz
ps
Test Conditions
Input frequency (fIN
Resolution
)
—
195
±2.0
fIN = 160 MHz
DNL*1
—
—
LSB
Note 1. The value is that difference from code to code normalized by the resolution (1 LSB).
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5. Electrical Characteristics
5.5
USB Characteristics
Table 5.41 On-Chip USB Low Speed (Host Only) Characteristics (DP and DM Pin Characteristics)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 3.0 to 3.6 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
a
opr
UCLK = 48 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz
Item
Symbol
VIH
Min.
2.0
—
Max.
—
Unit
V
Test Conditions
Input characteristics
Output characteristics
Input high-level voltage
Input low-level voltage
Differential input sensitivity
Differential common mode range
Output high-level voltage
Output low-level voltage
Cross-over voltage
Rise time
VIL
0.8
V
VDI
0.2
0.8
2.8
0.0
1.3
75
—
V
| DP – DM |
VCM
VOH
VOL
2.5
V
3.6
V
IOH = –200 μA
IOL = 2 mA
0.3
V
VCRS
tLR
2.0
V
Figure 5.55
300
300
125
24.80
ns
ns
%
kΩ
Fall time
tLF
75
Rise/fall time ratio
tLR / tLF
Rpd
80
tLR/ tLF
Pull-down characteristics
DP/DM pull-down resistance
(when the host controller function is
selected)
14.25
90%
90%
VCRS
DP, DM
10%
10%
tLR
tLF
Figure 5.55
DP and DM Output Timing (Low Speed)
Observation
point
dp
22
22
200 pF to
600 pF
3.6 V
1.5 k
dm
200 pF to
600 pF
Figure 5.56
Test Circuit (Low Speed)
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RX66T Group
5. Electrical Characteristics
Table 5.42 On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 3.0 to 3.6 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
a
opr
UCLK = 48 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz
Item
Symbol
VIH
Min.
2.0
—
Max.
—
Unit
V
Test Conditions
Input characteristics
Output characteristics
Input high-level voltage
Input low-level voltage
Differential input sensitivity
Differential common mode range
Output high-level voltage
Output low-level voltage
Cross-over voltage
Rise time
VIL
0.8
V
VDI
0.2
0.8
2.8
0.0
1.3
4
—
V
| DP – DM |
VCM
VOH
VOL
VCRS
tFR
2.5
V
3.6
V
IOH = –200 μA
IOL = 2 mA
0.3
V
2.0
V
Figure 5.57
20
ns
ns
%
Ω
Fall time
tFF
4
20
Rise/fall time ratio
Output resistance
t
FR / tFF
ZDRV
Rpu
90
111.11
44
tFR/ tFF
28
Rs = 22 Ω included
Pull-up and pull-down
characteristics
DP pull-up resistance
(when the function controller function
is selected)
0.900
1.425
1.575
3.090
kΩ Idle state
kΩ
At transmission and
reception
DP/DM pull-down resistance
(when the host controller function is
selected)
Rpd
14.25
24.80
kΩ
90%
90%
VCRS
DP, DM
10%
tFR
10%
tFF
Figure 5.57
DP and DM Output Timing (Full-Speed)
Observation
point
dp
22
22
50 pF
50 pF
dm
Figure 5.58
Test Circuit (Full-Speed)
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5. Electrical Characteristics
5.6
A/D Conversion Characteristics
Table 5.43 12-Bit A/D (Unit 0, 1, 2) Conversion Characteristics (1)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, 4.5 V ≤ AVCC0 = AVCC1 = AVCC2 ≤ 5.5V,
1
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T , PCLKB = PCLKD = 8 to 60 MHz* ,
a
opr
Source impedance = 1.0 kΩ
Item
Min.
12
Typ.
12
Max.
12
Unit
Bit
Test Conditions
Resolution
Analog input capacitance
2
—
—
30
pF
Conversion time*
(Operation at
AN000 to AN002,
AN100 to AN102
Channel-dedicated Constant
1.00
—
—
μs
Sampling time: 24 PCLKD
sample-and-hold
circuits in use
sampling
enabled
PCLKD = 60 MHz)
Constant
sampling
disabled
1.40
—
—
—
—
Sampling time of channel-dedicated
sample-and-hold circuits: 24 PCLKD
Sampling time: 24 PCLKD
Channel-dedicated sample-and- 0.90
hold circuits not in use
Sampling time: 30 PCLKD
AN003 to AN006, AN103 to AN106
AN007, AN107, AN200 to AN211
AN216 to AN217
0.90
0.95
1.05
—
—
—
—
—
Sampling time: 30 PCLKD
Sampling time: 33 PCLKD
Sampling time: 39 PCLKD
—
—
Offset error
Channel-dedicated sample-and-
hold circuits in use
±1.5
±6.0
LSB AN000 to AN002, AN100 to AN102 =
0.2 V
Channel-dedicated sample-and-
hold circuits not in use
—
—
—
—
—
—
—
±1.5
±1.5
±1.5
±0.5
±0.5
±3.0
±2.5
±5.0
±5.5
±4.5
—
Full-scale error
Quantization error
Absolute accuracy
Channel-dedicated sample-and-
hold circuits in use
AN000 to AN002 = AVCC0 – 0.2 V
AN100 to AN102 = AVCC1 – 0.2 V
Channel-dedicated sample-and-
hold circuits not in use
Channel-dedicated sample-and-
hold circuits in use
Channel-dedicated sample-and-
hold circuits not in use
—
AN000 to AN002,
AN100 to AN102
Channel-dedicated sample-and-
hold circuits in use
±6.0
±5.5
Channel-dedicated sample-and-
hold circuits not in use
AN003 to AN007, AN103 to AN107
AN200 to AN211
—
—
—
—
±2.5
±2.5
±2.5
±1.0
±5.5
±5.5
±6.5
±2.5
AN216 to AN217
DNL differential nonlinearity error
Channel-dedicated sample-and-
hold circuits in use
Channel-dedicated sample-and-
hold circuits not in use
—
—
—
±1.0
±1.5
±1.5
±1.5
±4.0
±2.5
20
INL integral nonlinearity error
Channel-dedicated sample-and-
hold circuits in use
Channel-dedicated sample-and-
hold circuits not in use
Holding time of the channel-dedicated sample-and-hold circuit
—
—
—
µs
V
Dynamic range
AN000 to AN002
Channel-dedicated sample-and-
hold circuits in use
0.2
AVCC0
– 0.2
AN100 to AN102
Channel-dedicated sample-and-
hold circuits in use
0.2
—
AVCC1
– 0.2
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. When PCLKD was higher than 40 MHz, capacitors with the following values were placed in parallel with the 0.1-μF capacitors
between AVCC0 and AVSS0, AVCC1 and AVSS1, and AVCC2 and AVSS2 for measurement of the A/D conversion
characteristics.
- Products with 64 Kbytes of RAM: 1000 pF
- Products with 128 Kbytes of RAM: 0.01 μF
Note 2. The conversion time is the sum of the sampling time and the comparison time. The numbers of sampling-clock cycles are
indicated as the test conditions.
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RX66T Group
5. Electrical Characteristics
Table 5.44 12-Bit A/D (Unit 0, 1, 2) Conversion Characteristics (2)
Conditions: VCC = 2.7 to 4.5 V, VCC_USB = 2.7 to 4.5 V, 3.0 V ≤ AVCC0 = AVCC1 = AVCC2 < 4.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T , PCLKB = PCLKD = 8 to 40 MHz,
a
opr
Source impedance = 1.0 kΩ
Item
Min.
12
Typ.
12
Max.
12
Unit
Bit
Test Conditions
Resolution
Analog input capacitance
1
—
—
30
pF
Conversion time*
(Operation at
AN000 to AN002,
AN100 to AN102
Channel-dedicated Constant
1.35
—
—
μs
Sampling time: 18 PCLKD
sample-and-hold
circuits in use
sampling
enabled
PCLKD = 40 MHz)
Constant
sampling
disabled
1.80
—
—
—
—
Sampling time of channel-dedicated
sample-and-hold circuits: 18 PCLKD
Sampling time: 18 PCLKD
Channel-dedicated sample-and- 1.13
hold circuits not in use
Sampling time: 21 PCLKD
AN003 to AN006, AN103 to AN106
AN007, AN107, AN200 to AN211
AN216 to AN217
1.13
1.20
1.28
—
—
—
—
—
Sampling time: 21 PCLKD
Sampling time: 24 PCLKD
Sampling time: 27 PCLKD
—
—
Offset error
Channel-dedicated sample-and-
hold circuits in use
±1.5
±7.5
LSB AN000 to AN002, AN100 to AN102 =
0.2 V
Channel-dedicated sample-and-
hold circuits not in use
—
—
—
—
—
—
—
±1.5
±1.5
±1.5
±0.5
±0.5
±4.0
±2.5
±6.5
±7.5
±6.5
—
Full-scale error
Quantization error
Absolute accuracy
Channel-dedicated sample-and-
hold circuits in use
AN000 to AN002 = AVCC0 – 0.2 V
AN100 to AN102 = AVCC1 – 0.2 V
Channel-dedicated sample-and-
hold circuits not in use
Channel-dedicated sample-and-
hold circuits in use
Channel-dedicated sample-and-
hold circuits not in use
—
AN000 to AN002,
AN100 to AN102
Channel-dedicated sample-and-
hold circuits in use
±8.0
±7.0
Channel-dedicated sample-and-
hold circuits not in use
AN003 to AN007, AN103 to AN107
AN200 to AN211
—
—
—
—
±2.5
±2.5
±2.5
±1.0
±7.0
±7.0
±8.0
±4.5
AN216 to AN217
DNL differential nonlinearity error
Channel-dedicated sample-and-
hold circuits in use
Channel-dedicated sample-and-
hold circuits not in use
—
—
—
±1.0
±2.0
±1.5
±3.5
±5.0
±3.5
20
INL integral nonlinearity error
Channel-dedicated sample-and-
hold circuits in use
Channel-dedicated sample-and-
hold circuits not in use
Channel-dedicated sample-and-hold characteristics of hold circuits
—
—
—
µs
V
Dynamic range
AN000 to AN002
Channel-dedicated sample-and-
hold circuits in use
0.2
AVCC0
– 0.2
AN100 to AN102
Channel-dedicated sample-and-
hold circuits in use
0.2
—
AVCC1
– 0.2
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The numbers of sampling-clock cycles are
indicated as the test conditions.
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RX66T Group
5. Electrical Characteristics
Table 5.45 A/D Internal Reference Voltage Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T , PCLKB = PCLKD = 8 to 60 MHz
a
opr
Item
Min.
1.20
Typ.
1.25
Max.
1.30
Unit
V
Test Conditions
A/D internal reference voltage
Note:
The above specification values apply during normal operations.
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RX66T Group
5. Electrical Characteristics
5.7
Programmable Gain Amplifier Characteristics
Table 5.46 Programmable Gain Amplifier Characteristics (single-ended input)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
a
opr
Item
Input offset voltage
Symbol
VIO
Min.
Typ.
3
Max.
Unit
mV
V
Test Conditions
—
8
Single-ended input voltage range
Output voltage range
VISR
VOR
VOSR (min)/G
0.10 × AVCCn
0.15 × AVCCn
0.20 × AVCCn
2.000
—
—
—
—
—
VOSR (min)/G
0.90 × AVCCn
0.85 × AVCCn
0.80 × AVCCn
20.000
G = 2.000 to 3.636
G = 4.000 to 6.667
G = 8.000 to 20.000
Gain
G
Linear
gain
Gain error
EG
—
—
—
—
—
—
—
—
—
—
—
—
10
—
±0.5
±0.5
±0.5
±0.5
±0.6
±0.6
±0.7
±0.7
±0.7
±0.7
±1.1
±1.3
—
±2.0
±2.0
±2.0
±2.0
±2.0
±2.0
±2.0
±3.0
±3.0
±4.0
±4.0
±4.0
—
%
G = 2.000
G = 2.500
G = 3.077
G = 3.636
G = 4.000
G = 4.444
G = 5.000
G = 6.667
G = 8.000
G = 10.000
G = 13.333
G = 20.000
Slew rate
SR
V/μs
μs
Operation stabilization time
tstart
—
5
n = 0 and 1
Table 5.47 Programmable Gain Amplifier Characteristics (pseudo-differential input)
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
a
opr
Item
Input offset voltage
Symbol
VIO
Min.
—
Typ.
10
Max.
20
Unit
mV
V
Test Conditions*1
Differential input voltage range
VIDR
–0.28 ×
—
0.28 ×
AVCCn / G
AVCCn / G
Output voltage range
Input voltage range (PGAVSS)
Gain error
VOR
VI(PGAVSS)
EG
0.22 × AVCC
—
—
0.78 × AVCC
–0.5
—
0.3
±2.0
±2.0
±3.0
±4.0
—
±0.5
±0.5
±0.8
±1.2
—
%
G = 1.500
—
G = 4.000
G = 7.000
G = 12.333
—
—
Slew rate
SR
10
—
V/μs
μs
Operation stabilization time
tstart
—
5
n = 0 and 1
Note 1. When AVCC0 = AVCC1 = AVCC2 ≥ 4.0 V, VOLSR.PGAVLS = 0
When AVCC0 = AVCC1 = AVCC2 < 4.0 V, VOLSR.PGAVLS = 1
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5. Electrical Characteristics
0.5 × AVCC
R2
AVCC
Analog input
(AN000 to AN002,
AN100 to AN102)
VO
Output voltage (VO)
= G × VID + 0.5 × AVCC
R1
R2
R1
Differential input voltage
VID = VI(AN) – VI(PGAVSS)
0.5 × AVCC
0.5V when
G = 1.5
Reference ground at the
time of PGA pseudo-
differential input
VI(PGAVSS)
0.5V when
G = 1.5
0
(PGAVSS0, PGAVSS1)
Figure 5.59
Input and Output Signal Levels with the PGA’s Pseudo-Differential Setting
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RX66T Group
5. Electrical Characteristics
5.8
Comparator Characteristics
Table 5.48 Comparator Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
a
opr
Item
Input offset voltage
Symbol
VIO
Min.
—
Typ.
8
Max.
40
Unit
mV
V
Test Conditions
Reference input voltage range
Response time
Vref
0
—
AVCC1
CMPSEL1.CVRS[3:0] =
0100b, 1000b
0
—
AVCC2
CMPSEL1.CVRS[3:0] =
0001b, 0010b
ttot(r)
ttot(f)
tcwait
—
—
—
—
—
200
200
—
ns
μs
VOD = 100 mV
CMPCTL.CDFS = 0
Waiting time for stabilization following
switching of the input
300
Operation stabilization time
tcmp
—
—
1
100 mV
100 mV
Reference input
voltage
CMPCn0 to CMPCn3
(analog input voltage)
ttot(r)
ttot(f)
COMPn
(output for monitoring the
results of comparison)
(n = 0 to 5)
Figure 5.60
Comparator Response Time
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RX66T Group
5. Electrical Characteristics
5.9
D/A Conversion Characteristics
Table 5.49 D/A Conversion Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
a
opr
Item
Min.
12
Typ.
12
Max.
12
Unit
Bit
Test Conditions
Resolution
Absolute accuracy
—
—
±6.0
LSB
2-MΩ resistive load, 10-bit
conversion
Differential nonlinearity error (DNL)
Output resistance (Ro)
Conversion time
—
—
—
±1.0
5.7
—
±2.0
—
LSB
kΩ
2-MΩ resistive load
3
μs
20-pF capacitive load
5.10 Temperature Sensor Characteristics
Table 5.50 Temperature Sensor Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
,
a
opr
PCLKB = PCLKD = 8 to 60 MHz
Item
Min.
—
—
—
—
3
Typ.
±1.0
–2.0
0.63
—
Max.
—
Unit
°C
Test Conditions
Relative accuracy
Temperature slope
Output voltage
—
mV/°C
V
—
Ta = 25°C
Temperature sensor start time
Sampling time*1
200
—
μs
—
μs
Note 1. Set the S12AD2.ADSSTRT register such that the sampling time of the 12-bit A/D converter satisfies this specification.
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RX66T Group
5. Electrical Characteristics
5.11 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.51 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
a
opr
Item
Symbol
VPOR
Min.
2.46
4.04
2.71
4.39
4.29
4.14
2.81
2.76
4.39
4.29
4.14
2.81
2.76
—
Typ.
2.58
4.22
2.83
4.57
4.47
4.32
2.93
2.88
4.57
4.47
4.32
2.93
2.88
13.7
0.70
0.57
0.57
—
Max.
2.70
4.40
2.95
4.75
4.65
4.50
3.05
3.00
4.75
4.65
4.50
3.05
3.00
—
Unit
V
Test Conditions
Figure 5.61
Voltage detection level
Power-on reset (POR)
Voltage detection circuit
(LVD0)
Vdet0_1
Vdet0_2
Vdet1_0
Vdet1_1
Vdet1_2
Vdet1_3
Vdet1_4
Vdet2_0
Vdet2_1
Vdet2_2
Vdet2_3
Vdet2_4
tPOR
Figure 5.62
Voltage detection circuit
(LVD1)
Figure 5.63
Voltage detection circuit
(LVD2)
Figure 5.64
Internal reset time
Power-on reset time
LVD0 reset time
LVD1 reset time
LVD2 reset time
ms
Figure 5.61
Figure 5.62
Figure 5.63
Figure 5.64
tLVD0
—
—
tLVD1
—
—
tLVD2
—
—
Minimum VCC down time
Response delay time
tVOFF
200
—
μs
μs
Figure 5.61,
Figure 5.62
tdet
—
—
200
Figure 5.61 to
Figure 5.64
LVD operation stabilization time (after LVD is enabled)
Hysteresis width (LVD1 and LVD2)
Td(E-A)
V LVH
—
—
—
20
—
μs
Figure 5.63,
Figure 5.64
80
mV
Note:
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,
and Vdet2 for the POR/ LVD.
tVOFF
VPOR
VCC
Internal reset signal
(Low is valid)
tdet
tPOR
tdet
tdet tPOR
Figure 5.61
Power-on Reset Timing
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RX66T Group
5. Electrical Characteristics
tVOFF
VCC
Vdet0
Internal reset signal
(Low is valid)
tdet
tdet
tLVD0
Figure 5.62
Voltage Detection Circuit Timing (V
)
det0
tVOFF
VLVH
VCC
Vdet1
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(Low is valid)
When LVD1RN = L
tdet
tLVD1
tdet
When LVD1RN = H
tLVD1
Figure 5.63
Voltage Detection Circuit Timing (V
)
det1
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RX66T Group
5. Electrical Characteristics
tVOFF
VLVH
VCC
Vdet2
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(Low is valid)
When LVD2RN = L
tdet
tdet
tLVD2
When LVD2RN = H
tLVD2
Figure 5.64
Voltage Detection Circuit Timing (V
)
det2
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RX66T Group
5. Electrical Characteristics
5.12 Oscillation Stop Detection Timing
Table 5.52 Oscillation Stop Detection Circuit Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, T = T
a
opr
Item
Symbol
tdr
Min.
—
Typ.
—
Max.
1
Unit
ms
Test Conditions
Figure 5.65
Detection time
Main clock or
PLL clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Figure 5.65
Oscillation Stop Detection Timing
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RX66T Group
5. Electrical Characteristics
5.13 Flash Memory Characteristics
Table 5.53 Code Flash Memory Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
Temperature range for program/erase: T = T
a
opr
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 60 MHz
Item
Symbol
Unit
ms
Min.
—
Typ.
0.9
29
Max.
13.2
176
704
15.8
212
848
216
864
260
1040
—
Min.
—
Typ.
0.4
13
Max.
6
Program time
256 bytes
8 Kbytes
32 Kbytes
256 bytes
8 Kbytes
32 Kbytes
8 Kbytes
32 Kbytes
8 Kbytes
32 Kbytes
tP256
tP8K
(NPEC ≤ 100 cycles)
—
—
80
tP32K
tP256
tP8K
—
116
1.1
35
—
52
320
7.2
96
Program time
—
—
0.5
16
(NPEC > 100 cycles)
—
—
tP32K
tE8K
tE32K
tE8K
—
140
71
—
64
384
120
480
144
576
—
Erase time
—
—
39
(NPEC ≤ 100 cycles)
—
254
85
—
141
47
Erase time
—
—
(NPEC > 100 cycles)
tE32K
NPEC
tSPD
—
304
—
—
169
—
Program/erase cycles*1
Program suspend latency
1000*2
—
1000*2
—
Cycles
μs
—
264
216
—
120
120
Primary erase suspend latency in suspend
priority mode
tSESD1
—
—
—
—
Secondary erase suspend latency in
suspend priority mode
tSESD2
tSEED
—
—
—
—
1.7
1.7
—
—
—
—
1.7
1.7
ms
Erase suspend latency in erase priority
mode
Forced stop command
Data retention*3
tFD
—
—
—
32
—
—
—
—
20
—
μs
tDRP
10
10
Year
Note 1. Definition of program/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 256-byte program is performed 32 times for different addresses in 8-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristic when the program/erase cycle does not exceed the specified value.
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Page 190 of 201
RX66T Group
5. Electrical Characteristics
Table 5.54 Data Flash Memory Characteristics
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
Temperature range for program/erase: T = T
a
opr
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 60 MHz
Item
Symbol
Unit
ms
Min.
—
Typ.
0.36
3.1
—
Max.
3.8
Min.
Typ.
0.16
1.7
—
Max.
1.7
Program time
Erase time
4 bytes
tDP4
tDE64
—
64 bytes
4 bytes
—
18
—
10
Blank check time
tDBC4
—
84
—
30
μs
64 bytes
2 Kbytes
tDBC64
tDBC2K
NDPEC
tDSPD
—
—
280
6160
—
—
—
—
100
2200
—
—
—
—
Program/erase cycles*1
Program suspend latency
100000*2
—
—
—
100000*2
—
—
Cycles
μs
—
—
264
216
—
120
120
Primary erase suspend latency in suspend
priority mode
tDSESD1
—
—
Secondary erase suspend latency in
suspend priority mode
tDSESD2
tDSEED
—
—
—
—
300
300
—
—
—
—
300
300
Erase suspend latency in erase priority
mode
Forced stop command
Data retention*3
tFD
—
—
—
32
—
—
—
—
20
—
tDDRP
10
10
Year
Note 1. Definition of program/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 4-byte program is performed 512 times for different addresses in 2-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristic when the program/erase cycle does not exceed the specified value.
R01DS0315EJ0110 Rev.1.10
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Page 191 of 201
RX66T Group
5. Electrical Characteristics
• Program suspend
FCU command
Program
Ready
Suspend
tSPD
FSTATR.FRDY
Not Ready
Ready
Programming pulse
Programming
• Erase suspend in suspend priority mode
FCU command
Suspend
Erase
Suspend
Not Ready
Erasing
Resume
tSESD1
tSESD2
FSTATR.FRDY
Erasure pulse
Ready
Ready
Not Ready
Erasing
• Erase suspend in erase priority mode
FCU command
Erase
Suspend
Not Ready
Erasing
tSEED
FSTATR.FRDY
Erasure pulse
Ready
Ready
Figure 5.66
Flash Memory Program/Erase Suspend Timing
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Page 192 of 201
RX66T Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas
Electronics Corporation website.
Figure A 144-Pin LFQFP (PLQP0144KA-B)
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 193 of 201
RX66T Group
Appendix 1. Package Dimensions
ꢀꢁꢂꢃꢄꢅꢅꢆ
Figure B 112-Pin LQFP (PLQP0112JA-B)
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 194 of 201
RX66T Group
Appendix 1. Package Dimensions
Figure C 100-Pin LFQFP (PLQP0100KB-B)
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 195 of 201
RX66T Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
PLQP0080JA-A
Previous Code
MASS[Typ.]
0.6g
P-LQFP80-14x14-0.65
FP-80W / FP-80WV
HD
*1
D
41
60
61
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Nom Max
Min
D
E
A2
HD
HE
A
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
Terminal cross section
80
21
1
20
A1
bp
b1
0.05
0.15
0.1
ZD
Index mark
0.27 0.32 0.37
0.30
F
c
c1
0.09
0.20
0.145
0.125
S
θ
e
0°
8°
L
0.65
x
y
0.13
0.10
L1
y
S
*3
Detail F
e
bp
×
M
ZD
ZE
L
0.825
0.825
0.5
0.35
0.65
L1
1.0
Figure D 80-Pin LQFP (PLQP0080JA-A)
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 196 of 201
RX66T Group
Appendix 1. Package Dimensions
Figure E 80-Pin LFQFP (PLQP0080KB-B)
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 197 of 201
RX66T Group
Appendix 1. Package Dimensions
Figure F 64-Pin LFQFP (PLQP0064KB-C)
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 198 of 201
REVISION HISTORY
RX66T Group
REVISION HISTORY
REVISION HISTORY
RX66T Group Datasheet
Classifications
- Items with Technical Update document number: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
Description
Rev.
1.00
Date
Classification
Page
—
Summary
Jul 30, 2018
First edition, issued
1.10 Feb 08, 2019
All
G-version products, added
144-pin products, added
Products with 128 Kbytes of RAM, added
Features
1
1. Overview
23
Features, changed
TN-RX*-A0205A/E
Table 1.4 Pin Functions: Note added
3. Address Space
70
71
Figure 3.1 Memory Map in Each Operating Mode, changed
Figure 3.2 Correspondence between External Address Spaces and CS
Areas (In On-Chip ROM Disabled Extended Mode), changed
5. Electrical Characteristics
129
131
138
150
Table 5.3 Recommended operating conditions (2), added
TN-RX*-A0205A/E
Table 5.5 DC Characteristics (2), changed
Table 5.12 Permissible Output Currents, changed
Figure 5.14 NMI Interrupt Input Timing, Figure 5.15 IRQ Interrupt Input
Timing, changed
159
Table 5.31 POE and POEG Timing, changed
160, 161
Figure 5.28 Output Disable Time for POE in Response to Transition of the
POEn# Signal Level to
Figure 5.32 Output Disable Time for POE in Response to the Oscillation
Stop Detection, changed
161
Figure 5.33 POEG Input Timing, changed
161 to 163 Figure 5.34 Output Disable Time for POEG via Detection Flag in Response TN-RX*-A0205A/E
to the Input Level Detection of the GTETRGn pin to
Figure 5.40 Output Disable Time for POEG in Response to Level Detection
Signal from a Comparator, changed
168
174
175
179
Table 5.36 RSPI Timing, changed
Table 5.38 RIIC Timing, changed
Table 5.39 Simple IIC Timing, changed
Table 5.43 12-Bit A/D (Unit 0, 1, 2) Conversion Characteristics (1),
changed
180
182
Table 5.44 12-Bit A/D (Unit 0, 1, 2) Conversion Characteristics (2),
changed
Table 5.46 Programmable Gain Amplifier Characteristics (single-ended
input), Table 5.47 Programmable Gain Amplifier Characteristics (pseudo-
differential input), changed
All trademarks and registered trademarks are the property of their respective owners.
R01DS0315EJ0110 Rev.1.10
Feb 08, 2019
Page 199 of 201
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
you or third parties arising from such alteration, modification, copying or reverse engineering.
5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
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Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
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Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
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Tel: +65-6213-0200, Fax: +65-6213-0300
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Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
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Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
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Tel: +82-2-558-3737, Fax: +82-2-558-5338
© 2019 Renesas Electronics Corporation. All rights reserved.
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