R5F572MNDGFC_技术文档

Features

Datasheet

RX72M Group

R01DS0332EJ0100

Rev.1.00

Renesas MCUs

May 31, 2019

240-MHz 32-bit RX MCU, on-chip double-precision FPU, 1396 CoreMark,

Arithmetic unit for trigonometric functions, up to 4-MB flash memory (supportive of the dual bank function), 1-MB SRAM,

EtherCAT Slave Controller, various communications interfaces including Ethernet MAC compliant with IEEE 1588, SD host

interface, quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), Serial sound interface, CMOS

camera interface, Graphic-LCD controller, 2D drawing engine

Features

PLQP0176KB-C 24 × 24 mm, 0.5-mm pitch

■ 32-bit RXv3 CPU core

 Maximum operating frequency: 240 MHz

Capable of 1396 CoreMark in operation at 240 MHz

 Double-precision 64-bit IEEE-754 floating point

 A collective register bank save function is available.

PLBG0224GA-A 13 × 13 mm, 0.8-mm pitch

PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch

 Supports the memory protection unit (MPU)

 JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture

■ Various communications interfaces

 Operation from a single 2.7- to 3.6-V supply

 EtherCAT slave controller (two ports)

 RTC is capable of operation from a dedicated power supply.

 Ethernet MAC compliant with IEEE 1588 (2 channels)

 Four low-power modes

 PHY layer (1 channel) for host/function or OTG controller

(1 channel) with full-speed USB 2.0 transfer

 CAN (compliant with ISO11898-1), incorporating 32 mailboxes (3

channels)

■ On-chip code flash memory

 Supports versions with up to 4 Mbytes of ROM

 No wait cycles at up to 120 MHz or when the ROM cache is hit,

one-wait state at above 120 MHz

 User code is programmable by on-board or off-board programming.

 Programming/erasing as background operations (BGOs)

 A dual-bank structure allows exchanging the start-up bank.

 SCIj and SCIh with multiple functionalities (8 channels)

Choose from among asynchronous mode, clock-synchronous mode,

smart-card interface mode, simplified SPI, simplified I²C, and

extended serial mode.

 SCIi with 16-byte transmission and reception FIFOs (5 channels)

 I²C bus interface for transfer at up to 1 Mbps (3 channels)

 Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)

 Parallel data capture unit (PDC) for the CMOS camera interface

 Graphic-LCD controller (GLCDC)

■ On-chip data flash memory

 32 Kbytes, reprogrammable up to 100,000 times

 Programming/erasing as background operations (BGOs)

■ On-chip SRAM

 1 Mbyte of SRAM (no wait states; however, if ICLK is at a

frequency above 120 MHz, access to locations in the 512 Kbytes of

SRAM from 0080 0000h to 0087 FFFFh requires one cycle of

waiting)

 2D drawing engine (DRW2D)

 SD host interface (1 channel) with a 1- or 4-bit SD bus for use with

SD memory or SDIO

 MMCIF with 1-, 4-, or 8-bit transfer bus width

 32 Kbytes of RAM with ECC (single error correction/double error

detection)

 8 Kbytes of standby RAM (backup on deep software standby)

■ External address space

 Buses for full-speed data transfer (max. operating frequency of 80

MHz)

■ Data transfer

 DMACAa: 8 channels

 DTCb: 1 channel

 8 CS areas

 8-, 16-, or 32-bit bus space is selectable per area

 Independent SDRAM area (128 Mbytes)

 EXDMAC: 2 channels

 DMAC for the Ethernet controller: 3 channels

■ Up to 29 extended-function timers

 32-bit GPTW (4 channels)

■ Reset and supply management

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

 16-bit TPUa (6 channels), MTU3a (9 channels)

 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2

channels)

■ Clock functions

 External crystal resonator or internal PLL for operation at 8 to 24

MHz

■ 12-bit A/D converter

 Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)



Self diagnosis, detection of analog input disconnection

 PLL for specific purposes

■ 12-bit D/A converter: 2 channels

 Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20

MHz

■ Temperature sensor for measuring temperature

within the chip

 120-kHz clock for the IWDTa

■ Real-time clock

■ Arithmetic unit for trigonometric functions

 Adjustment functions (30 seconds, leap year, and error)

 Real-time clock counting and binary counting modes are selectable

 Time capture function

■ Delta-Sigma Modulator Interface

 Six external delta-sigma modulators are connectable

(for capturing times in response to event-signal input)

■ Encryption functions (optional)

 AES (key lengths: 128, 192, and 256 bits)

 Trusted Secure IP (TSIP)

■ Independent watchdog timer

 120-kHz clock operation

■ Up to 182 pins for general I/O ports

 5-V tolerance, open drain, input pull-up, switchable driving ability

■ Useful functions for IEC60730 compliance

 Oscillation-stoppage detection, frequency measurement, CRCA,

IWDTa, self-diagnostic function for the A/D converter, etc.

 Register write protection function can protect values in important

registers against overwriting.

■ Operating temp. range

 D-version: –40C to +85C

 G-version: –40C to +105C

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May 31, 2019

Page 1 of 158

RX72M Group

1. Overview

1.

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different

packages.

Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the

modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details,

refer to Table 1.2, Comparison of Functions for Different Packages.

Table 1.1

Outline of Specifications (1/11)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 240 MHz

 32-bit RX CPU (RXv3)

 Minimum instruction execution time: One instruction per state (cycle of the system

clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 113 instructions

Instructions installed as standard: 111

Basic instructions: 77

Single-precision floating-point operation instructions: 11

DSP instructions: 23

Instructions for register bank save function: 2

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32 / 32 → 32 bits

 Barrel shifter: 32 bits

FPU

 Single-precision floating-point numbers (32 bits) and double-precision floating-point

numbers (64 bits)

 Data types and floating-point exceptions in conformance with the IEEE754 standard

Double-precision

floating point

coprocessor

 Double-precision floating-point register set

Double-precision floating-point data registers: 16, each with 64-bit width

Double-precision floating-point control registers: Four, each with 32-bit width

 Double-precision floating-point processing instructions: 21

 Notifying the interrupt controller of double-precision floating-point exceptions

Register bank save

function

 Fast collective saving and restoration of the values of CPU registers

 16 save register banks

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Page 2 of 158

RX72M Group

1. Overview

Table 1.1

Outline of Specifications (2/11)

Classification

Module/Function

Description

Memory

Code flash memory

 Capacity: 2 Mbytes/4 Mbytes

 ROM cache: 8 Kbytes

 120 MHz ≤ No-wait cycle access,

120 MHz > One-wait cycle access

 Instructions hitting the ROM cache or operand = 240 MHz: No-wait access

 On-board programming: Four types

 Off-board programming (parallel programmer mode)

 Instructions are executable only for the program stored in the TM target area by using

the Trusted Memory (TM) function and protection against data reading is realized.

 A dual-bank structure allows programming during reading or exchanging the start-up

areas

Data flash memory

 Capacity: 32 Kbytes

 Programming/erasing: 100,000 times

Unique ID

RAM

 16-byte unique ID for each device

 Capacity: 512 Kbytes

 Up to 240 MHz, no-wait access

Expansion RAM

ECC RAM

 Capacity: 512 Kbytes

 120 MHz ≤ No-wait cycle access,

120 MHz > One-wait cycle access

 Capacity: 32 Kbytes

 If the operating frequency is no greater than 120 MHz, one-wait cycle access,

if greater than 120MHz, two-wait cycle access in the case of reading, and three-wait

cycle access in the case of writing

 SEC-DED (single-bit error correction and double-bit error detection)

Standby RAM

 Capacity: 8 Kbytes

 Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access

Operating modes

 Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (for the SCI interface)

Boot mode (for the USB interface)

Boot mode (for the FINE interface)

 Selection of operating mode by register setting

Single-chip mode

On-chip ROM disabled extended mode

On-chip ROM enabled extended mode

 Endian selectable

Clock

Clock generation circuit  Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL

frequency synthesizer (two circuits), and IWDT-dedicated on-chip oscillator

 The peripheral module clocks can be set to frequencies above that of the system clock.

 Main-clock oscillation stoppage detection

 Separate frequency-division and multiplication settings for the system clock (ICLK),

peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and

external bus clock (BCLK)

The CPU and other bus masters run in synchronization with the system clock (ICLK): Up

to 240 MHz

Peripheral modules of MTU, RSPI, SCIi, ETHERC, EPTPC, PMGI, EDMAC, GPTW,

GLCDC, DRW2D, and ESC run in synchronization with PCLKA, which operates at up to

120 MHz.

Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz

ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz

ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz

Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz

Devices connected to the external bus run in synchronization with the external bus clock

(BCLK): Up to 80 MHz

 The high-speed on-chip oscillator (HOCO) can be obtained through frequency-

multiplication of the PLL or PPLL reference clock

 External clock input frequency: 30 MHz (max)

 Clock output function

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RX72M Group

1. Overview

Table 1.1

Outline of Specifications (3/11)

Classification

Module/Function

Description

Reset

Nine types of reset

 RES# pin reset: Generated when the RES# pin is driven low.

 Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =

AVCC1 rises.

 Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.

 Deep software standby reset: Generated in response to an interrupt to trigger release

from deep software standby.

 Independent watchdog timer reset: Generated when the independent watchdog timer

underflows, or a refresh error occurs.

 Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh

error occurs.

 Software reset: Generated by register setting.

Power-on reset

 If the RES# pin is at the high level when power is supplied, an internal reset is

generated.

After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the

specified period has elapsed, the reset is cancelled.

Voltage detection circuit (LVDA)

Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an

internal reset or interrupt.

 Voltage detection circuit 0

Capable of generating an internal reset

The option-setting memory can be used to select enabling or disabling of the reset.

Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V)

 Voltage detection circuits 1 and 2

Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V)

Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)

Capable of generating an internal reset

 Two types of timing are selectable for release from reset

An internal interrupt can be requested.

 Detection of voltage rising above and falling below thresholds is selectable.

 Maskable or non-maskable interrupt is selectable

Voltage detection monitoring

Event linking

Low power

Low power consumption  Module stop function

consumption

function

 Four low power consumption modes

Sleep mode, all-module clock stop mode, software standby mode, and deep software

standby mode

Battery backup function  When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied

to keep the real-time clock (RTC) operating.

Interrupt

Interrupt controller

(ICUD)

 Number of interrupt vectors: 256

 External interrupts: 16 (pins IRQ0 to IRQ15)

 Software interrupts: 2 sources

 Non-maskable interrupts: 8 sources

 Sixteen levels specifiable for the order of priority

 Method of interrupt source selection:

The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128

vectors are selected from among the other 169 sources.)

External bus extension

 The external address space can be divided into eight areas (CS0 to CS7), each with

independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7)

A chip-select signal (CS0# to CS7#) can be output for each area.

Each area is specifiable as an 8-, 16-, or 32-bit bus space.

The data arrangement in each area is selectable as little or big endian (only for data).

 SDRAM interface connectable

 Bus format: Separate bus, multiplex bus

 Wait control

 Write buffer facility

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RX72M Group

1. Overview

Table 1.1

Outline of Specifications (4/11)

Classification

Module/Function

Description

DMA

DMA controller

(DMACAa)

 8 channels

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Software trigger and interrupt requests from peripheral functions

EXDMA controller

(EXDMACa)

 2 channels

Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster

transfer

 Single-address transfer enabled with the EDACKn signal

 Request sources: Software trigger, external DMA requests (EDREQn), and interrupt

requests from peripheral functions

Data transfer controller

(DTCb)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Request sources: External interrupts and interrupt requests from peripheral functions

 Sequence transfer

I/O ports

Programmable I/O ports  I/O ports for the 224-pin LFBGA

I/O pins: 182

Input pin: 1

Pull-up resistors: 182

Open-drain outputs: 182

5-V tolerance: 19

 I/O ports for the 176-pin LFBGA and 176-pin LFQFP

I/O pins: 136

Input pin: 1

Pull-up resistors: 136

Open-drain outputs: 136

5-V tolerance: 19

Event link controller (ELC)

 Event signals such as interrupt request signals can be interlinked with the operation of

functions such as timer counting, eliminating the need for intervention by the CPU to

control the functions.

 137 internal event signals can be freely combined for interlinked operation with

connected functions.

 Event signals from peripheral modules can be used to change the states of output pins

(of ports B and E).

 Changes in the states of pins (of ports B and E) being used as inputs can be interlinked

with the operation of peripheral modules.

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RX72M Group

1. Overview

Table 1.1

Outline of Specifications (5/11)

Classification

Module/Function

Description

Timers

16-bit timer pulse unit

(TPUa)

 (16 bits × 6 channels) × 1 unit

 Maximum of 16 pulse-input/output possible

 Select from among seven or eight counter-input clock signals for each channel

 Input capture/output compare function

 Output of PWM waveforms in up to 15 phases in PWM mode

 Support for buffered operation, phase-counting mode (two phase encoder input) and

cascade-connected operation (32 bits × 2 channels) depending on the channel.

 PPG output trigger can be generated

 Capable of generating conversion start triggers for the A/D converters

 Digital filtering of signals from the input capture pins

 Event linking by the ELC

Multifunction timer pulse  9 channels (16 bits × 8 channels, 32 bits × 1 channel)

unit (MTU3a)

 Maximum of 28 pulse-input/output and 3 pulse-input possible

 Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/

2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,

MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)

14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8,

12 are available for channel 2, and 10 are available for channel 5.

 Input capture function

 39 output compare/input capture registers

 Counter clear operation (synchronous clearing by compare match/input capture)

 Simultaneous writing to multiple timer counters (TCNT)

 Simultaneous register input/output by synchronous counter operation

 Buffered operation

 Support for cascade-connected operation

 43 interrupt sources

 Automatic transfer of register data

 Pulse output mode

Toggle/PWM/complementary PWM/reset-synchronized PWM

 Complementary PWM output mode

Outputs non-overlapping waveforms for controlling 3-phase inverters

Automatic specification of dead times

PWM duty cycle: Selectable as any value from 0% to 100%

Delay can be applied to requests for A/D conversion.

Non-generation of interrupt requests at peak or trough values of counters can be

selected.

Double buffer configuration

 Reset synchronous PWM mode

Three phases of positive and negative PWM waveforms can be output with desired duty

cycles.

 Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)

 Counter functionality for dead-time compensation

 Generation of triggers for A/D converter conversion

 A/D converter start triggers can be skipped

 Digital filter function for signals on the input capture and external counter clock pins

 PPG output trigger can be generated

 Event linking by the ELC

Port output enable 3

(POE3a)

 Control of the high-impedance state of the MTU waveform output pins

 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#

 Initiation on detection of short-circuited outputs (detection of simultaneous PWM output

to the active level)

 Initiation by oscillation-stoppage detection or software

 Additional programming of output control target pins is enabled

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RX72M Group

1. Overview

Table 1.1

Outline of Specifications (6/11)

Classification

Module/Function

Description

 32 bits × 4 channels (GPTW0 to GPTW3)

 Counting up or down (sawtooth-wave), counting up and down (triangle-wave) selectable

for all channels

Timers

General PWM timer

(GPTW)

 Clock sources independently selectable for each channel

 2 input/output pins per channel

 2 output compare/input capture registers per channel

 For the 2 output compare/input capture registers of each channel, 4 registers are

provided as buffer registers and are capable of operating as comparison registers when

buffering is not in use.

 In output compare operation, buffer switching can be at crests or troughs, enabling the

generation of laterally asymmetrically PWM waveforms.

 Registers for setting up frame intervals on each channel (with capability for generating

interrupts on overflow or underflow)

 Generation of dead times in PWM operation

 Capable of synchronous start, stop, or clearing of counter for any channel

 Capable of a start, stop, clearing, or up-/down-counting of the counter supporting input

level comparison

 Capable of a start, stop, clearing, or up-/down-counting of the counter supporting

maximum of 4 external triggers

 Output pin disabling function by a dead time error or a short circuit detection among

output pins

 Capable of generating conversion start triggers for the A/D converters as well as

monitoring external pins for a start timing of conversion.

 Capable of outputting events, such as compare-match from A to F and overflow/

underflow, to ELC

 Capable of using noise filter of input capture

Port output enable for

GPTW (POEG)

 Controlling the output disable for GPTW waveform output

 Initiation by input level detection of GTETRG pins

 Initiation by output disable request from GPTW

 Initiation by detection of oscillation stop or by software

Programmable pulse

generator (PPG)

 (4 bits × 4 groups) × 2 units

 Pulse output with the MTU or TPU output as a trigger

 Maximum of 32 pulse-output possible

8-bit timers (TMR)

 (8 bits × 2 channels) × 2 units

 Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,

PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Generation of triggers for A/D converter conversion

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

 Event linking by the ELC

Compare match timer

(CMT)

 (16 bits × 2 channels) × 2 units

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

Compare match timer W  (32 bits × 1 channel) × 2 units

(CMTW)  Compare-match, input-capture input, and output-comparison output are available.

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

 Event linking by the ELC

Realtime clock (RTCd)*¹ Clock sources: Main clock, sub-clock

 Selection of the 32-bit binary count in time count/second unit possible

 Clock and calendar functions

 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

 Battery backup operation

 Time-capture facility for three values

 Event linking by the ELC

Watchdog timer (WDTA)  14 bits × 1 channel

 Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,

PCLKB/512, PCLKB/2048, PCLKB/8192)

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RX72M Group

1. Overview

Table 1.1

Outline of Specifications (7/11)

Classification

Module/Function

Description

Timers

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256

 Window function: The positions where the window starts and ends are specifiable (the

window defines the timing with which refreshing is enabled and disabled).

 Event linking by the ELC

Communication Ethernet controller

 2 channels

function

(ETHERC)

 Input and output of Ethernet/IEEE 802.3 frames

 Transfer at 10 or 100 Mbps

 Full- and half-duplex modes

 MII (Media Independent Interface) and RMII (Reduced Media Independent Interface) as

defined in IEEE 802.3u

 Detection of Magic Packets^TM*²or output of a “wake-on-LAN” signal (WOL)

 Compliance with flow control as defined in IEEE 802.3x standards

 Filtering of multicast frames is supported.

 Frame data can be directly transferred between 2 channels by cut-through switching.

PHY management

interface (PMGI)

 2 channels

 This module is compliant with the MII (Media Independent Interface) as defined in the

IEEE 802.3u standard.

 Transmission and reception of management frames through PHY-LSI chips having an

MII or RMII interface is supported.

 Alleviates load on the CPU by shifting it to dedicated hardware

 The timing of management data is adjustable.

 Preambles can be deleted.

PTP module for the

ethernet controller

(EPTPCb)

 In connection with the Ethernet controller (ETHERC), this module is compliant with the

IEEE1588 standard.

 Matching with time stamps can be used to trigger counting by the MTU and GPTW.

DMA controller for

ethernet controller

(EDMACa)

 3 channels (each EDMAC determines the order of priority by a round-robin algorithm)

For ETHERC: 2 channels, for EPTPC: 1 channel

 Alleviation of CPU load by the descriptor control method

 Transmission FIFO: 2 Kbytes; Reception FIFO: 4 Kbytes

EtherCAT slave

controller (ESC)*³

 One channel (two ports)

 The Beckoff EtherCAT Slave Controller IP Core was adopted for this.

USB 2.0 FS host/

 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS

function module (USBb)  One port

 Compliance with the USB 2.0 specification

 Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)

 Both self-power mode and bus-power mode are supported

 OTG (On the Go) operation is possible (low-speed is not supported)

 Incorporates 2 Kbytes of RAM as a transfer buffer

 External pull-up and pull-down resistors are not required

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RX72M Group

1. Overview

Table 1.1

Outline of Specifications (8/11)

Classification

Module/Function

Description

Communication Serial communications

 13 channels (SCIj: 7 channels + SCIi: 5 channels + SCIh: 1 channel)

 SCIj, SCIi, SCIh

function

interfaces

(SCIj, SCIi, SCIh)

Serial communications modes: Asynchronous, clock synchronous, and smart-card

interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Start-bit detection: Level or edge detection is selectable.

Simple I²C

Simple SPI

7- to 9-bit transfer mode

Bit rate modulation

Double-speed mode

Detecting matches of data is supported (other than for SCI12)

 SCIj, SCIh

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Event linking by the ELC (only on channel 5)

 SCIh

Supports the serial communications protocol, which contains the start frame and

information frame

Supports the LIN format

 SCIi

Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the

transmission and reception unit

I²C bus interface (RIICa)  3 channels (only channel 0 can be used in fast-mode plus)

Communication formats

I²C bus format/SMBus format

Supports the multi-master

Max. transfer rate: 1 Mbps (channel 0)

 Event linking by the ELC

CAN module (CAN)

 3 channels

 Compliance with the ISO11898-1 specification (standard frame and extended frame)

 32 mailboxes per channel

Serial peripheral

interface (RSPIc)

 3 channels

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or to 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with

each frame having up to 32 bits)

Transit/receive data can be swapped in byte units

 Buffered structure

Double buffers for both transmission and reception

 RSPCK can be stopped with the receive buffer full for master reception.

 Event linking by the ELC

Quad serial peripheral

interface (QSPI)

 1 channel

 Connectable with serial flash memory equipped with multiple input and output lines (i.e.

for single, dual, or quad operation)

 Programmable bit length and selectable active sense and phase of the clock signal

 Sequential execution of transfer

 LSB or MSB first is selectable

R01DS0332EJ0100 Rev.1.00

May 31, 2019

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RX72M Group

1. Overview

Table 1.1

Outline of Specifications (9/11)

Classification

Module/Function

Description

Extended serial sound interface (SSIE)

 2 channels

 Full-duplex transmission (only for channel 0)

 Various types of serial audio formatting are supported.

 Master and slave operations are supported.

 The bit-clock frequency is selectable from among 13 frequencies (1/1, 1/2, 1/4, 1/6, 1/8,

1/12, 1/16, 1/24, 1/32, 1/48, 1/64, 1/96, or 1/128).

 Data formats with 8, 16, 18, 20, 22, 24, and 32 bits are supported.

 32-stage FIFO buffers for transmission and reception

 Stopping or not stopping the SSILRCK signal on stopping of data transmission is

selectable.

SD host interface (SDHI)

 1 channel

 Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode

(12.5 MB/s)

 One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)

 SD specifications

Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported)

Part E1: SDIO Specification Ver. 3.00

 Error checking: CRC7 for commands and CRC16 for data

 Interrupt requests: Card access interrupt, SDIO access interrupt, card detection

interrupt, interrupt of SD buffer access

 DMA transfer requests: SD_BUF write and SD_BUF read

 Support for card detection and write protection

MMC host interface (MMCIF)

 1 channel

 Transfer speed: Data transfer mode (30 MB/s), backward compatible mode (25 MB/s)

 Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported)

 Interface for Multimedia Cards (MMCs)

 Data buses: Support for 1-, 4-, and 8-bit MMC buses

 Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation

interrupt, interrupt of MMCIF buffer access

 DMA transfer requests: CE_DATA write and CE_DATA read

 Support for card detection, boot operation, high priority interrupt (HPI)

x²+ y²

The arithmetic unit for trigonometric

functions (TFU)

 Sine, cosine, arctangent,

Simultaneous calculation of sine and cosine

Simultaneous calculation of arctangent and

x²+ y²

Delta-sigma modulator interface (DSMIF)

Parallel data capture unit (PDC)

 6 channels

 Up to six external delta-sigma modulators are connectable.

 The sinc filters are selectable as first-, second-, or third-order.

 1 channel

 Acquisition of synchronization through external 8-bit horizontal and vertical

synchronization signals

 Setting of the image size when clipping of the output for a one-frame image is required

Graphic-LCD controller (GLCDC)

2D drawing engine (DRW2D)

 1 channel

 Various data formats and LCD panels are supported

 Superposition of 3 planes (single-color background, graphic 1, graphic 2)

 32- and 16-bpp graphics data and 8-, 4-, and 1-bit CLUT data formats are supported

 1 channel

 Vector drawing (straight lines, triangles, and circles)

 Bit blitting (with support for filling, copying, stretching, and rotation)

 Bus master function for input and output of frame buffer data

32-, 16-, and 8-bit pixel graphics data are supported

 Bus master function for input of texture data

Input of texture data (32, 24, 16, 8, 4, 2, or 1 bit) are supported.

Run length encoding is supported

A CLUT is installed and index data can be converted into color data

 Two rendering modes are supported (register mode and display list mode)

 Performance counting

 Interrupts in response to completion of rendering and processing of the display list

R01DS0332EJ0100 Rev.1.00

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Page 10 of 158

RX72M Group

1. Overview

Table 1.1

Outline of Specifications (10/11)

Classification

Module/Function

Description

12-bit A/D converter (S12ADFa)

 12 bits × 2 units (unit 0: 8 channels; unit 1: 21 channels)

 12-bit resolution (switchable between 8, 10, and 12 bits)

 Conversion time

0.48 μs per channel (for 12-bit conversion)

0.45 μs per channel (for 10-bit conversion)

0.42 μs per channel (for 8-bit conversion)

 Operating mode

Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)

Group priority control (only for 3 group scan mode)

 Sample-and-hold function

Common sample-and-hold circuit included

In addition, channel-dedicated sample-and-hold function (3 channels: in unit 0 only)

included

 Sampling variable

Sampling time can be set up for each channel.

 Digital comparison

Method: Comparison to detect voltages above or below thresholds and window

comparison

Measurement: Comparison of two results of conversion or comparison of a value in the

comparison register and a result of conversion

 Self-diagnostic function

The self-diagnostic function internally generates three analog input voltages

(unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: AVSS1, AVCC1 × 1/2, AVCC1)

 Double trigger mode (A/D conversion data duplicated)

 Detection of analog input disconnection

 Three ways to start A/D conversion

Software trigger, timer (MTU, TMR, TPU) trigger, external trigger

 Event linking by the ELC

12-bit D/A converter (R12DAa)

 2 channels

 12-bit resolution

 Output voltage: 0.2 V to AVCC1 – 0.2 V (buffered output), 0 V to AVCC1 (unbuffered

output)

 Buffered output or unbuffered output can be selected.

 Event linking by the ELC

Temperature sensor

 1 channel

 Relative precision: ± 1°C

 The voltage of the temperature is converted into a digital value by the 12-bit A/D

converter (unit 1).

Safety

Memory protection unit

 Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to

(MPU)

FFFF FFFFh.

 Minimum protection unit: 16 bytes

 Reading from, writing to, and enabling the execution access can be specified for each

area.

 An access exception occurs when the detected access is not in the permitted area.

Trusted Memory (TM)

Function

 Programs in the TM target area in the code flash memory are protected against reading

 Instruction fetching by the CPU is the only form of access to these areas when the TM

function is enabled.

Register write protection  Protects important registers from being overwritten for in case a program runs out of

function control.

CRC calculator (CRCA)  Generation of CRC codes for 8-/32-bit data

8-bit data

Selectable from the following three polynomials

X⁸+ X²+ X + 1, X¹⁶+ X¹⁵+ X²+ 1, X¹⁶+ X¹²+ X⁵+ 1

32-bit data

Selectable from the following two polynomials

X

³²+ X²⁶+ X²³+ X²²+ X¹⁶+ X¹²+ X¹¹+ X¹⁰+ X⁸+ X⁷+ X⁵+ X⁴+ X²+ X + 1,

X³²+ X²⁸+ X²⁷+ X²⁶+ X²⁵+ X²³+ X²²+ X²⁰+ X¹⁹+ X¹⁸+ X¹⁴+ X¹³+ X¹¹+ X¹⁰+ X⁹+

X⁸+ X⁶+ 1

 Generation of CRC codes for use with LSB-first or MSB-first communications is

selectable

Main clock oscillation

stop detection

 Main clock oscillation stop detection: Available

R01DS0332EJ0100 Rev.1.00

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Page 11 of 158

RX72M Group

1. Overview

Table 1.1

Outline of Specifications (11/11)

Classification

Module/Function

Description

Safety

Clock frequency

accuracy measurement

circuit (CAC)

 Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and

high-speed on-chip oscillators, IWDT-dedicated on-chip oscillator, USB clock, Ethernet-

PHY external clock, and PCLKB, and generates interrupts when the setting range is

exceeded.

Data operation circuit

(DOC)

 The function to compare, add, or subtract 16-bit data

Encryption

function

Trusted Secure IP

(TSIP)*⁴

 Security algorithm

Common key encryption: AES (compliant with NIST FIPS PUB 197), TDES, ARC4

Non-common key encryption: RSA

 Other features

TRNG (true-random number generator)

Hash value generation: SHA1, SHA224, SHA256, MD5, GHASH

Prevention of the illicit copying of keys

Operating frequency

Power supply voltage

Up to 240 MHz

VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

V_BATT= 2.0 to 3.6 V

Operating temperature

Package

D-version: –40 to +85°C

G-version: –40 to +105°C

224-pin LFBGA (PLBG0224GA-A)

176-pin LFBGA (PLBG0176GA-A)

176-pin LFQFP (PLQP0176KB-C)

On-chip debugging system

 E1 emulator (JTAG and FINE interfaces)

Note 1. When the realtime clock is not used, initialize the registers in the time clock according to description in section 33.6.7,

Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware.

Note 2. Magic Packet^TMis a registered trademark of Advanced Micro Devices, Inc.

®

Note 3. EtherCAT is a registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.

Note 4. The product part number differs according to whether or not the MCU includes the encryption function.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 12 of 158

RX72M Group

1. Overview

Table 1.2

Comparison of Functions for Different Packages (1/2)

Functions

Package

RX72M

224 Pins

176 Pins

32 bits/16 bits/8 bits

Available

External bus

External bus width

SDRAM area controller

DMA controller

DMA

Ch. 0 to 7

Data transfer controller

EXDMA controller

Available

Ch. 0 and 1

Ch. 0 to 5

Timers

16-bit timer pulse unit

Multi-function timer pulse unit 3

General PWM timer

Ch. 0 to 8

Ch. 0 to 3

Port output enable 3

Available

Port output enable for GPTW

Programmable pulse generator

8-bit timers

Available

Ch. 0 and 1

Ch. 0 to 3

Compare match timer

Compare match timer W

Realtime clock

Ch. 0 to 3

Ch. 0 and 1

Available

Watchdog timer

Available

Independent watchdog timer

Ethernet controller

Available

Communication

function

Ch. 0 and 1

Available

PHY management interface

PTP controller for the ethernet

controller

DMA controller for the ethernet

controller

Ch. 0 and 1 (ETHERC)

Ch. 2 (EPTPC)

EtherCAT slave controller

Ch. 0 and 1

Ch. 0

USB 2.0 FS host/function module

Serial communications interfaces

(SCIj)

Ch. 0 to 6

Serial communications interfaces

(SCIi)

Ch. 7 to 11

Ch. 12

Serial communications interfaces

(SCIh)

I²C bus interfaces

Ch. 0 to 2

Serial peripheral interface

CAN module

Ch. 0 to 2

Quad serial peripheral interface

Expansion serial sound interface

SD host interface

Ch. 0

Ch. 0 and 1

Ch. 0

Multimediacard interface

Parallel data capture unit

Graphic-LCD controller

2D drawing engine

Unit 0

Ch. 0

Available

Graphics

Available

12-bit A/D

converter

AN000 to 007 (8 channels)

AN100 to 120 (21 channels)

Ch. 0 and 1

Available

Unit 1

12-bit D/A converter

Temperature sensor

Arithmetic unit for trigonometric functions

Available

R01DS0332EJ0100 Rev.1.00

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Page 13 of 158

RX72M Group

1. Overview

Table 1.2

Comparison of Functions for Different Packages (2/2)

Functions

Package

RX72M

224 Pins

176 Pins

Available

Delta-sigma modulator interface

CRC calculator

Available

Data operation circuit

Clock frequency accuracy measurement circuit

Trusted Secure IP

Available

Available/Not available

Available

Event link controller

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 14 of 158

RX72M Group

1. Overview

1.2

List of Products

Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.

Table 1.3

List of Products

Code Flash

Memory

Capacity

Data Flash

Memory

Capacity

Operating

Frequency

(Max.)

Operating

temperature

(°C)

RAM

Capacity

Encryption

Module

Group

Part No.

Package

RX72M

(D-version)

R5F572MNDDFC

R5F572MNHDFC

R5F572MDDDFC

R5F572MDHDFC

R5F572MNDDBD

R5F572MNHDBD

R5F572MDDDBD

R5F572MDHDBD

R5F572MNDDBG

R5F572MNHDBG

R5F572MDDDBG

R5F572MDHDBG

R5F572MNDGFC

R5F572MNHGFC

R5F572MDDGFC

R5F572MDHGFC

PLQP0176KB-C

PLBG0224GA-A

PLBG0176GA-A

PLQP0176KB-C

4 Mbytes

2 Mbytes

4 Mbytes

2 Mbytes

4 Mbytes

2 Mbytes

4 Mbytes

2 Mbytes

1 Mbyte

32 Kbytes

240 MHz

Not available

Available

–40 to +85

–40 to +105

Not available

Available

Not available

Available

Not available

Available

Not available

Available

Not available

Available

RX72M

(G-version)

Not available

Available

Not available

Available

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 15 of 158

RX72M Group

1. Overview

R

5

F

5 7

2 M

N

D

B D

Package type, number of pins, and pin pitch

BD: LFBGA/224/0.80

FC: LFQFP/176/0.50

BG: LFBGA/176/0.80

D: Operating peripheral temperature: –40 to +85°C

G: Operating peripheral temperature: –40 to +105°C

D: Encryption module not included

H: Encryption module included

Code flash memory, RAM, and data flash memory capacity

N: 4 Mbytes/1 Mbyte/32 Kbytes

D: 2 Mbytes/1 Mbyte/32 Kbytes

Group name

RX72M Group

Series name

RX700 Series

Type of memory

F : Flash memory version

Renesas MCU

Renesas semiconductor product

Figure 1.1

How to Read the Product Part Number

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 16 of 158

RX72M Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a block diagram.

CAC

ICU

ELC

MTU × 9 channels

POE3

GPTW × 4 channels

POEG

TPU × 6 channels (unit 0)

PPG (unit 0)

PPG (unit 1)

TMR × 2 channels (unit 0)

TMR × 2 channels (unit 1)

CMT × 2 channels (unit 0)

CMT × 2 channels (unit 1)

CMTW × 1 channel (unit 0)

CMTW × 1 channel (unit 1)

RTC

WDT

IWDT

ETHERC × 2 channels

EPTPC

PMGI × 2 channels

ESC

USB × 1 port

SCIh × 1 channel

SCIi × 5 channels

SCIj × 7 channels

RIIC × 3 channels

CAN × 3 channels

SSIE × 2 channels

RSPI × 3 channels

QSPI

DMAC × 8 channels

DTC

EDMAC × 3 channels

GLCDC

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

Port J

Port K

Port L

Port M

Port N

Port Q

RAM

DRW2D

CRC

SDHI

MMCIF

PDC

Expansion

RAM

TFU

Trusted Secure IP^*1

ECCRAM

DSMIF × 3 channels (unit 0)

DSMIF × 3 channels (unit 1)

12-bit A/D converter × 8 channels (unit 0)

12-bit A/D converter × 21 channels (unit 1)

ROM

12-bit D/A converter × 2 channels

Temperature sensor

DOC

ROM Cache

Standby RAM

Data flash

RX CPU

MPU

EXDMAC

Clock

generation

circuit

External bus

BSC

CAC:

ICU:

BSC:

MPU:

DMAC:

Clock frequency accuracy measurement circuit

Interrupt controller

Bus controller

Memory protection unit

DMA controller

EPTPC:

PTP module for the ethernet controller

EDMAC: DMA controller for the ethernet controller

PMGI:

ESC:

USB:

Phy management interface

EtherCAT slave controller

USB2.0 FS host/function module

EXDMAC: EXDMA controller

SCIj, SCIi, SCIh: Serial communications interface

RIIC:

DTC:

ELC:

Data transfer controller

Event link controller

Multi-function timer pulse unit 3

Port output enable 3

General PWM timer

GPTW port output enable

16-bit timer pulse unit

Programmable pulse unit

8-bit timer

I²C-bus interface

CAN:

SSIE:

RSPI:

QSPI:

CRC:

SDHI:

MMCIF:

PDC:

CAN module

MTU:

POE3:

GPTW:

POEG:

TPU:

PPG:

TMR:

CMT:

Serial sound interface enhanced

Serial communications interface

Quad serial peripheral interface

CRC calculator

SD host interface

MultiMediaCard interface

Parallel data capture unit

Compare match timer

Compare match timer W

Realtime clock

GLCDC: Graphic LCD controller

DRW2D: 2D drawing engine

CMTW:

RTC:

TFU:

Arithmetic unit for trigonometric functions

WDT:

IWDT:

Watchdog timer

Independent watchdog timer

Trusted Secure IP: Trusted secure IP^*1

DSMIF:

DOC:

Delta-sigma modulator interface

Data operation circuit

ETHERC: Ethernet controller

Note 1. Optional

Figure 1.2

Block Diagram

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May 31, 2019

Page 17 of 158

RX72M Group

1. Overview

1.4

Pin Functions

Table 1.4 lists the pin functions.

Table 1.4

Pin Functions (1/9)

Pin Name

Classifications

I/O

Description

Digital power supply

VCC

Input

Power supply pin. Connect this pin to the system power supply.

Connect the pin to VSS via a 0.1-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

VCL

Input

Connect this pin to VSS via a 0.22-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

VSS

Input

Ground pin. Connect it to the system power supply (0 V).

Backup power pin

VBATT

XTAL

Clock

Output Input/output pins for a crystal resonator. An external clock signal

can be input through the EXTAL pin.

EXTAL

BCLK

Input

Output Outputs the external bus clock for external devices.

Output Outputs the SDRAM-dedicated clock.

SDCLK

XCOUT

XCIN

Output Input/output pins for the sub-clock oscillator. Connect a crystal

resonator between XCOUT and XCIN.

Input

CLKOUT

Output Clock output pin.

Clock frequency accuracy CACREF

measurement

Input

Reference clock input pin for the clock frequency accuracy

measurement circuit

Operating mode control

MD

Input

Input pin for setting the operating mode. The signal level on this

pin must not be changed during operation.

UB

Input

USB boot mode enable pin

UPSEL

Selects the power supply method in USB boot mode.

The low level selects self-power mode and the high level selects

bus power mode.

System control

RES#

EMLE

Input

Reset signal input pin. This MCU enters the reset state when

this signal goes low.

Input pin for the on-chip emulator enable signal. When the on-

chip emulator is used, this pin should be driven high. When not

used, it should be driven low.

BSCANP

Input

Boundary scan enable pin. Boundary scan is enabled when this

pin goes high. When not used, it should be driven low.

On-chip emulator

FINED

TRST#

TMS

I/O

FINE interface pin

Input

Output

On-chip emulator or boundary scan pins. When the EMLE pin is

driven high, these pins are dedicated for the on-chip emulator.

TDI

TCK

TDO

TRCLK

Output This pin outputs the clock for synchronization with the trace

data.

TRSYNC, TRSYNC1

Output These pins indicate that output from the TRDATA0 to TRDATA7

pins is valid.

TRDATA0 to TRDATA7

A0 to A26

Output These pins output the trace information.

Output Output pins for the address

Address bus

Data bus

D0 to D31

I/O

Input and output pins for the bidirectional data bus

Address/data multiplexed bus

Multiplexed bus

A0/D0 to A15/D15

R01DS0332EJ0100 Rev.1.00

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RX72M Group

1. Overview

Table 1.4

Pin Functions (2/9)

Classifications

Pin Name

I/O

Description

Bus control

RD#

Output Strobe signal which indicates that reading from the external bus

interface space is in progress

WR#

Output Strobe signal which indicates that writing to the external bus

interface space is in progress, in 1-write strobe mode

WR0# to WR3#

Output Strobe signals which indicate that either group of data bus pins

(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in

writing to the external bus interface space, in byte strobe mode

BC0# to BC3#

ALE

Output Strobe signals which indicate that either group of data bus pins

(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in

access to the external bus interface space, in 1-write strobe

mode

Output Address latch signal when address/data multiplexed bus is

selected

WAIT#

Input

Input pin for wait request signals in access to the external space

CS0# to CS7#

CKE

Output Select signals for CS areas

Output SDRAM clock enable signal

Output SDRAM chip select signal

SDRAM interface

SDCS#

RAS#

Output SDRAM row address strobe signal

Output SDRAM column address strove signal

Output SDRAM write enable pin

CAS#

WE#

DQM0 to DQM3

EDREQ0, EDREQ1

EDACK0, EDACK1

NMI

Output SDRAM I/O data mask enable signals

EXDMA controller

Interrupt

Input

External DMA transfer request pins

Output Single address transfer acknowledge signals

Input

Non-maskable interrupt request pin

Maskable interrupt request pins

IRQ0 to IRQ15, IRQ0-DS to

IRQ15-DS

Multi-function timer pulse MTIOC0A, MTIOC0B,

I/O

Input

I/O

The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins

unit 3

MTIOC0C, MTIOC0D

MTIOC1A, MTIOC1B

The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins

MTIOC2A, MTIOC2B

The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins

MTIOC3A, MTIOC3B,

MTIOC3C, MTIOC3D

The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins

MTIOC4A, MTIOC4B,

MTIOC4C, MTIOC4D

The TGRA4 to TGRD4 input capture input/output compare

output/PWM output pins

MTIC5U, MTIC5V, MTIC5W

The TGRU5, TGRV5, and TGRW5 input capture input/dead

time compensation input pins

MTIOC6A, MTIOC6B,

MTIOC6C, MTIOC6D

The TGRA6 to TGRD6 input capture input/output compare

output/PWM output pins

MTIOC7A, MTIOC7B,

MTIOC7C, MTIOC7D

The TGRA7 to TGRD7 input capture input/output compare

output/PWM output pins

MTIOC8A, MTIOC8B,

MTIOC8C, MTIOC8D

The TGRA8 to TGRD8 input capture input/output compare

output/PWM output pins

MTCLKA, MTCLKB, MTCLKC, Input

MTCLKD

Input pins for external clock signals or for phase counting mode

clock signals

Port output enable 3

POE0#, POE4#, POE8#,

POE10#, POE11#

Input

Input pins for request signals to place the MTU in the high

impedance state

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Page 19 of 158

RX72M Group

1. Overview

Table 1.4

Pin Functions (3/9)

Pin Name

Classifications

I/O

Description

General PWM timer W

GTETRGA, GTETRGB,

GTETRGC, GTETRGD

Input

Input pins for the external trigger signals

GTIOC0A to GTIOC3A,

GTIOC0B to GTIOC3B

I/O

Input capture input/output compare output/PWM output pins

GTADSM0, GTADSM1

Output Output pins for monitoring A/D conversion start requests.

16-bit timer pulse unit

TIOCA0, TIOCB0, TIOCC0,

TIOCD0

I/O

Input

The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins

TIOCA1, TIOCB1

The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins

TIOCA2, TIOCB2

The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins

TIOCA3, TIOCB3, TIOCC3,

TIOCD3

The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins

TIOCA4, TIOCB4

The TGRA4 and TGRB4 input capture input/output compare

output/PWM output pins

TIOCA5, TIOCB5

The TGRA5 and TGRB5 input capture input/output compare

output/PWM output pins

TCLKA, TCLKB, TCLKC,

TCLKD

Input pins for external clock signals or for phase counting mode

clock signals

Programmable pulse

generator

PO0 to PO31

Output Output pins for the pulse signals

8-bit timer

TMO0 to TMO3

TMCI0 to TMCI3

TMRI0 to TMRI3

TIC0 to TIC3

Output Compare match output pins

Input

Input pins for external clocks to be input to the counter

Input pins for the counter reset

Compare match timer W

Input pins for CMTW

TOC0 to TOC3

Output Output pins for CMTW

Serial communications

interface (SCIj)

 Asynchronous mode/clock synchronous mode

SCK0 to SCK6

RXD0 to RXD6

TXD0 to TXD6

CTS0# to CTS6#

RTS0# to RTS6#

I/O

Input/output pins for the clock

Input pins for received data

Input

Output Output pins for transmitted data

Input Input pins for controlling the start of transmission and reception

Output Output pins for controlling the start of transmission and

reception

 Simple I²C mode

SSCL0 to SSCL6

SSDA0 to SSDA6

 Simple SPI mode

SCK0 to SCK6

I/O

Input/output pins for the I²C clock

Input/output pins for the I²C data

I/O

Input/output pins for the clock

SMISO0 to SMISO6

SMOSI0 to SMOSI6

SS0# to SS6#

I/O

Input/output pins for slave transmission of data

Input/output pins for master transmission of data

Chip-select input pins

I/O

Input

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 20 of 158

RX72M Group

1. Overview

Table 1.4

Pin Functions (4/9)

Pin Name

Classifications

I/O

Description

Serial communications

interface (SCIh)

 Asynchronous mode/clock synchronous mode

SCK12

I/O

Input/output pin for the clock

Input pin for received data

RXD12

Input

TXD12

Output Output pin for transmitted data

Input Input pin for controlling the start of transmission and reception

Output Output pin for controlling the start of transmission and reception

CTS12#

RTS12#

 Simple I²C mode

SSCL12

I/O

Input/output pin for the I²C clock

Input/output pin for the I²C data

SSDA12

 Simple SPI mode

SCK12

I/O

Input/output pin for the clock

SMISO12

SMOSI12

SS12#

I/O

Input/output pin for slave transmission of data

Input/output pin for master transmission of data

Chip-select input pin

I/O

Input

 Extended serial mode

RXDX12

Input

Input pin for received data

TXDX12

Output Output pin for transmitted data

I/O Input/output pin for received or transmitted data

SIOX12

Serial communications

interface (SCIi)

 Asynchronous mode/clock synchronous mode

SCK7 to SCK11

RXD7 to RXD11

TXD7 to TXD11

CTS7# to CTS11#

RTS7# to RTS11#

I/O

Input/output pins for the clock

Input pins for received data

Input

Output Output pins for transmitted data

Input Input pins for controlling the start of transmission and reception

Output Output pins for controlling the start of transmission and

reception

 Simple I²C mode

SSCL7 to SSCL11

SSDA7 to SSDA11

 Simple SPI mode

SCK7 to SCK11

I/O

Input/output pins for the I²C clock

Input/output pins for the I²C data

I/O

Input/output pins for the clock

SMISO7 to SMISO11

SMOSI7 to SMOSI11

SS7# to SS11#

I/O

Input/output pins for slave transmission of data

Input/output pins for master transmission of data

Chip-select input pins

I/O

Input

I/O

I²C bus interface

SCL0[FM+], SCL1, SCL2,

SCL2-DS

Input/output pins for clocks. Bus can be directly driven by

the N-channel open drain

SDA0[FM+], SDA1, SDA2,

SDA2-DS

I/O

Input/output pins for data. Bus can be directly driven by

the N-channel open drain

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 21 of 158

RX72M Group

1. Overview

Table 1.4

Pin Functions (5/9)

Pin Name

Classifications

I/O

Description

Ethernet controller

REF50CK0, REF50CK1

Input

50-MHz reference clocks. These pins input reference signals for

transmission/reception timings in RMII mode.

RMII0_CRS_DV,

RMII1_CRS_DV

Input

These pins indicate that there are carrier detection signals and

valid receive data on RMIIn_RXD1 and RMIIn_RXD0 in RMII

mode.

RMII0_TXD0, RMII0_TXD1,

RMII1_TXD0, RMII1_TXD1

Output 2-bit transmit data in RMII mode

Input 2-bit receive data in RMII mode

Output Output pins for data transmit enable signals in RMII mode

RMII0_RXD0, RMII0_RXD1,

RMII1_RXD0, RMII1_RXD1

RMII0_TXD_EN,

RMII1_TXD_EN

RMII0_RX_ER,

RMII1_RX_ER

Input

These pins indicate an error has occurred during reception of

data in RMII mode.

ET0_CRS, ET1_CRS

Input

Carrier detection/data reception enable pins

ET0_RX_DV, ET1_RX_DV

These pins indicate that there are valid receive data on

ETn_ERXD3 to ETn_ERXD0.

ET0_EXOUT, ET1_EXOUT

Output General-purpose external output pins

ET0_LINKSTA, ET1_LINKSTA Input

Input link status from the PHY-LSI.

ET0_ETXD0 to ET0_ETXD3,

ET1_ETXD0 to ET1_ETXD3

Output 4 bits of MII transmit data

ET0_ERXD0 to ET0_ERXD3, Input

ET1_ERXD0 to ET1_ERXD3

4 bits of MII receive data

ET0_TX_EN, ET1_TX_EN

ET0_TX_ER, ET1_TX_ER

ET0_RX_ER, ET1_RX_ER

ET0_TX_CLK, ET1_RX_CLK

Output Transmit enable pins. These pins function as signals indicating

that transmit data are ready on ETn_ETXD3 to ETn_ETXD0.

Output Transmit error pins. These pins function as signals notifying the

PHY-LSI of an error during transmission.

Input

Receive error pins. These pins function as signals to recognize

an error during reception.

Input

Transmit clock pins. These pins input reference signals for

output timings from ETn_TX_EN, ETn_ETXD3 to ETn_ETXD0,

and ETn_TX_ER.

ET0_RX_CLK, ET1_RX_CLK Input

Receive clock pins. These pins input reference signals for input

timings to ETn_RX_DV, ETn_ERXD3 to ETn_ERXD0, and

ETn_RX_ER.

ET0_COL, ET1_COL

ET0_WOL, ET1_WOL

ET0_MDC, ET1_MDC

Input

Input collision detection signals.

Output Receive Magic packets.

Output Output reference clock signals for information transfer via

ETn_MDIO.

ET0_MDIO, ET1_MDIO

CLKOUT25M

I/O

Input or output bidirectional signals for exchange of

management information between this MCU and the PHY-LSI.

Output 25-MHz clock output pin for PHY clock input (used in common

by the EtherCAT module)

EPLSOUT0, EPLSOUT1

Output Pulse output signals for time synchronization

PHY management

interface

PMGI0_MDC, PMGI1_MDC

Output Reference clock signals for information transfer by

PMGIn_MDIO

PMGI0_MDIO, PMGI1_MDIO I/O

Bi-directional signals for the exchange of management

information between the PHY LSI chip and this MCU

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 22 of 158

RX72M Group

1. Overview

Table 1.4

Pin Functions (6/9)

Pin Name

Classifications

I/O

Description

EtherCAT slave controller

 MII mode

CAT0_LINKSTA,

CAT1_LINKSTA

Input

PHY link signal input pins

Receive clock input pins

CAT0_RX_CLK,

CAT1_RX_CLK

CAT0_RX_DV, CAT1_RX_DV Input

Receive data enabling signal input pins

Receive data signal input pins

CAT0_ERXD0 to

CAT0_ERXD3,

CAT1_ERXD0 to

CAT1_ERXD3

Input

CAT0_RX_ER, CAT1_RX_ER Input

Receive data error signal input pins

Transmit clock input pins

CAT0_TX_CLK,

CAT1_TX_CLK

Input

CAT0_TX_EN, CAT1_TX_EN Output Transmit enabling signal output pins

CAT0_ETXD0 to

CAT0_ETXD3,

CAT1_ETXD0 to

CAT1_ETXD3

Output Transmit data signal output pins

CAT0_MDC

CAT0_MDIO

CLKOUT25M

Output Management interface clock output pin

I/O

Management data signal input/output pin

Output 25-MHz clock output pin for PHY clock input (used in common

by the EtherC module)

 Exclusively for EtherCAT

CATRESTOUT

CATLEDRUN

Output Output signal for resetting the PHY chip

Output EtherCAT run LED signal output pin

Output EtherCAT IRQ signal output pin

CATIRQ

CATLEDSTER

CATLEDERR

Output EtherCAT dual-color state LED signal output pin

Output EtherCAT error LED signal output pin

Output EtherCAT link/activity LED signal output pins

CATLINKACT0,

CATLINKACT1

CATSYNC0, CATSYNC1

CATLATCH0, CATLATCH1

CATI2CCLK

Output EtherCAT sync signal output pins

Input

EtherCAT latch signal output pins

Output EtherCAT EEPROM I²C clock signal output pin

CATI2CDATA

VCC_USB

I/O

EtherCAT EEPROM I²C data signal input/output pin

Power supply pin

USB 2.0 host/function

module

Input

I/O

VSS_USB

Ground pin

USB0_DP

Input or output USB transceiver D+ data.

Input or output USB transceiver D- data.

USB0_DM

I/O

USB0_EXICEN

USB0_ID

Output Connect to the OTG power IC.

Input Connect to the OTG power IC.

Output USB VBUS power enable pin

USB0_VBUSEN

USB0_OVRCURA/

USB0_OVRCURB

Input

USB overcurrent pins

USB0_VBUS

Input

USB cable connection/disconnection detection input pin

Input pins

CAN module

CRX0, CRX1, CRX2,

CRX1-DS

CTX0, CTX1, CTX2

Output Output pins

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 23 of 158

RX72M Group

1. Overview

Table 1.4

Pin Functions (7/9)

Pin Name

Classifications

I/O

Description

Serial peripheral interface RSPCKA-A/RSPCKA-B/

RSPCKB-A/RSPCKB-B/

I/O

Clock input/output pins

RSPCKC-A/RSPCKC-B

MOSIA-A/MOSIA-B/

MOSIB-A/MOSIB-B/

MOSIC-A/MOSIC-B

I/O

Input or output data output from the master

Input or output data output from the slave

Input or output pins for slave selection

MISOA-A/MISOA-B/

MISOB-A/MISOB-B/

MISOC-A/MISOC-B

SSLA0-A/SSLA0-B/

SSLB0-A/SSLB0-B/

SSLC0-A/SSLC0-B

SSLA1-A/SSLA1-B/

SSLB1-A/SSLB1-B/

SSLC1-A/SSLC1-B,

SSLA2-A/SSLA2-B/

SSLB2-A/SSLB2-B/

SSLC2-A/SSLC2-B,

SSLA3-A/SSLA3-B/

SSLB3-A/SSLB3-B/

SSLC3-A/SSLC3-B

Output Output pins for slave selection

Quad serial peripheral

interface

QSPCLK-A/QSPCLK-B

QSSL-A/QSSL-B

Output QSPI clock output pins

Output QSPI slave output pins

QMO-A/QMO-B,

QIO0-A/QIO0-B

I/O

Master transmit data/data 0

Master input data/data 1

Data 2, data 3

QMI-A/QMI-B,

QIO1-A/QIO1-B

QIO2-A/QIO2-B,

QIO3-A/QIO3-B

Serial sound interface

enhanced

SSIBCK0, SSIBCK1

SSILRCK0, SSILRCK1

SSITXD0

I/O

SSIE serial bit-clock pins

LR clock

Output Serial data output pin

SSIRXD0

Input

I/O

Serial data input pin

SSIDATA1

Serial data input/output pin

AUDIO_CLK

Input

External clock pin for audio

(input for an oversampling clock)

MMC host interface

MMC_CLK-A/MMC_CLK-B

MMC_CMD-A/MMC_CMD-B

Output MMC clock pins

I/O

Command/response pins

MMC_D7-A/MMC_D7-B to

MMC_D0-A/MMC_D0-B

Transmit data/receive data

MMC_CD-A/MMC_CD-B

Input

Card detection pins

MMC_RES#-A/MMC_RES#-B Output MMC reset output pins

SD host interface

SDHI_CLK-A/SDHI_CLK-B/

SDHI_CLK-C

Output SD clock output pins

SDHI_CMD-A/SDHI_CMD-B/

SDHI_CMD-C

I/O

SD command output, response input signal pins

SDHI_D3-A/SDHI_D3-B/

SDHI_D3-C to SDHI_D0-A/

SDHI_D0-B/SDHI_D0-C

SD data bus pins

SDHI_CD

Input

I/O

SD card detection pin

SD write-protect signal

Input/output pins for the clock

Input pins for data

SDHI_WP

Delta-sigma modulator

interface

DSMCLK0 to DSMCLK5

DSMDAT0 to DSMDAT5

Input

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 24 of 158

RX72M Group

1. Overview

Table 1.4

Pin Functions (8/9)

Pin Name

Classifications

I/O

Description

Parallel data capture unit PIXCLK

Input

Image transfer clock pin

Vertical synchronization signal pin

Horizontal synchronization signal pin

8-bit image data pins

VSYNC

HSYNC

PIXD0 to PIXD7

PCKO

Output Output pin for dot clock

Output Panel clock output pins

Output Control signal output pins

Graphic-LCD controller

LCD_CLK-A, LCD_CLK-B

LCD_TCON3-A/

LCD_TCON3-B to

LCD_TCON0-A/

LCD_TCON0-B

LCD_DATA23-A/

LCD_DATA23-B to

LCD_DATA0-A/

LCD_DATA0-B

Output LCD signal output pins

LCD_EXTCLK-A,

LCD_EXTCLK-B

Input

Panel clock source input pins

Realtime clock

RTCOUT

Output Output pin for 1-Hz/64-Hz clock

RTCIC0 to RTCIC2

Input

Time capture event input pins

12-bit A/D converter

AN000 to AN007,

AN100 to AN120

Input pins for the analog signals to be processed by the A/D

converter

ADTRG0#, ADTRG1#

Input

Input pins for the external trigger signals that start the A/D

conversion

ANEX0

Output Extended analog output pin

Input Extended analog input pin

ANEX1

12-bit D/A converter

Analog power supply

DA0, DA1

Output Output pins for the analog signals to be processed by the D/A

converter

AVCC0

AVSS0

Input

Analog voltage supply pin for the 12-bit A/D converter (unit 0).

Connect this pin to a branch from the VCC power supply.

Connect the pin to AVSS0 via a 0.1-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

Analog ground pin for the 12-bit A/D converter (unit 0). Connect

this pin to a branch from the VSS ground power supply.

Connect the pin to AVCC0 via a 0.1-μF multilayer ceramic

capacitor. The capacitor should be placed close to the pin.

VREFH0

VREFL0

AVCC1

Input

Analog reference voltage supply pin for the 12-bit A/D converter

(unit 0). Connect this pin to VCC if the 12-bit A/D converter is

not to be used.

Analog reference ground pin for the 12-bit A/D converter (unit

0). Connect this pin to VSS if the 12-bit A/D converter is not to

be used.

Analog voltage supply and reference voltage supply pin for the

12-bit A/D converter (unit 1) and D/A converter. This pin also

supplies the analog voltage to the temperature sensor. Connect

this pin to a branch from the VCC power supply. Connect the

pin to AVSS1 via a 0.1-μF multilayer ceramic capacitor. The

capacitor should be placed close to the pin.

AVSS1

Input

Analog voltage supply and reference voltage supply pin for the

12-bit A/D converter (unit 1) and D/A converter. This pin also

supplies the analog ground voltage to the temperature sensor.

Connect this pin to a branch from the VSS ground power

supply. Connect the pin to AVCC1 via a 0.1-μF multilayer

ceramic capacitor. The capacitor should be placed close to the

pin.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 25 of 158

RX72M Group

1. Overview

Table 1.4

Pin Functions (9/9)

Pin Name

Classifications

I/O

Description

I/O ports

P00 to P03, P05, P07

6-bit input/output pins

8-bit input/output pins

8-bit input/output pins (P35: input pin)

8-bit input/output pins

6-bit input/output pins

8-bit input/output pins

5-bit input/output pins

8-bit input/output pins

6-bit input/output pins

8-bit input/output pins

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P80 to P87

P90 to P97

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE7

PF0 to PF5

PG0 to PG7

PJ0 to PJ3, PJ5

PH0 to PH7

PK0 to PK7

PL0 to PL7

PM0 to PM7

PN0 to PN5

PQ0 to PQ7

Note:

Note the following regarding pin names. For details, refer to section 1.5, Pin Assignments.

- We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as

groups.

For the RSPI, QSPI, SDHI, MMC, and GLCDC interfaces, the AC portion of the electrical characteristics is measured for each

group.

- When the pin functions have “-DS” appended to their names, they can also be used as triggers for release from deep software

standby.

- RIIC pin functions that have [FM+] appended to their names support fast-mode plus.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 26 of 158

RX72M Group

1. Overview

1.5

Pin Assignments

Figure 1.3 to Figure 1.5 show the pin assignments. Table 1.5 to Table 1.7 are the lists of pins and pin functions.

RX72M Group

PLBG0224GA-A (224-Pin LFBGA)

(Upper Perspective View)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

15

14

13

12

11

10

9

P70

PE7

P66

P67

PG4

PG7

PA4

PA5

PA7

P72

PB4

PB6

PB7

PM3

PM5

15

14

13

12

11

10

9

PE1

P62

PE4

PE2

P63

VCC

PD6

PD4

P95

P94

VCC

P91

P46

P42

P65

PE5

VSS

P64

P60

P97

VCC

PD1

P90

VSS

P44

P05

PG2

VSS

PE3

PE0

PG1

PD5

VSS

P93

P02

P01

P40

P03

P47

PG5

PE6

VCC

PQ4

PQ5

PQ3

PQ1

PQ0

PN0

P07

P43

P00

VSS

PG6

PG3

PA0

PA3

PA2

PA6

VSS

VCC

PL0

P73

PN3

PQ7

PJ3

PB0

P71

PB3

PB5

VSS

PM2

PL3

PK1

P50

P10

PH1

PF0

PH5

PH4

PH6

PB2

VCC

PN4

P77

PL7

P81

P52

VCC

PJ2

VCC

P24

PF1

P27

PC0

PM7

PL6

PL5

PK0

P83

P51

VSS

P84

PJ0

VSS

P25

P23

PC1

PM6

P76

PK2

P80

PC7

VCC

P56

PJ1

P13

P85

P86

PH0

PM4

PC2

PL2

PC4

P82

VSS

P11

P57

P74

P75

PL4

PC3

PC5

PC6

P55

P54

P61

PA1

PB1

PN5

PL1

PD7

PG0

PD3

P96

PM1

VSS

PQ6

PN1

PM0

VCC

PN2

PQ2

RES#

PK3

P53*¹

P15

8

7

PD2

PD0

P92

PK6

7

VSS_US USB0_D

6

EMLE

PK5

PF5 BSCANP PH2

6

B

P

VCC_US USB0_D

5

PJ5

P32

P33

P35

P34

P30

P31

PF3

PF2

5

B

M

MD/

FINED

4

P41

PK4

P14

P12

4

3

VREFL0

PF4

VCC

VSS

P20

P17

P16

P87

3

2

VREFH0 AVCC0 AVCC1

VBATT

2

1

NC

A

AVSS0 AVSS1

P45

D

VCL

E

XCIN XCOUT XTAL

EXTAL

J

PH7

K

PH3

L

P26

M

P22

N

PK7

P

P21

R

1

B

C

F

G

H

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.5, List

of Pin and Pin Functions (224-Pin LFBGA).

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is

enabled.

Figure 1.3

Pin Assignment (224-Pin LFBGA)

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 27 of 158

RX72M Group

1. Overview

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

15

14

13

12

11

10

9

PE2

PE1

PE3

P70

P65

P67

VSS

VCC

PG7

PA6

PB0

P72

PB4

VSS

VCC

PC1

P74

15

14

13

12

11

10

9

PE0

P64

VSS

PG1

PD4

P96

PD1

P92

P91

P47

P41

VSS

PE4

P62

VCC

PG0

PD3

PD2

PD0

P90

P45

P43

PE7

VCC

PE5

P61

PD7

PD5

VSS

P95

P93

P44

P00

P03

P02

PG3

PG2

PE6

PA0

PG4

P66

PA1

PG6

PG5

PA2

PA3

PA4

PA7

VSS

PA5

VCC

P71

PB2

PB1

PB3

PB6

PB5

PB7

P77

P81

PC5

P50

P55

P85

PJ1

PJ2

P86

P24

P26

P73

PC0

PC3

P82

PC7

P51

P54

P84

PJ0

P12

P15

P22

P23

P75

PC2

PC4

PC6

P83

P52

P10

P57

P63

P76

P60

P80

PD6

VCC

VSS

P53*¹

P11

P97

VCC

P94

RX72M Group

PTBG0176GA-A

(176-Pin LFBGA)

8

(Upper Perspective View)

7

VSS

VCC

P46

P56

7

VSS_

USB

USB0_

DP

6

VCC_ USB0_

USB

5

DM

4

P42

VSS BSCANP PF4

MD/

P35

RES#

VSS

PF3

P34

VCC

PF1

PF2

P32

P25

PF0

P30

P14

P13

4

3

VREFL0

AVCC0

P40 VREFH0

PF5

PJ3

P87

P17

P16

P20

3

FINED

2

P07

AVCC1

EMLE

VCL

XCOUT

2

1

AVSS0

A

P05

B

AVSS1

C

P01

D

PJ5

E

VBATT

F

XCIN

G

XTAL

H

EXTAL

J

P33

K

P31

L

P27

M

VCC

N

VSS

P

P21

R

1

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.6, List

of Pin and Pin Functions (176-Pin LFBGA).

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is

enabled.

Figure 1.4

Pin Assignment (176-Pin LFBGA)

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 28 of 158

RX72M Group

1. Overview

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

PE2

PE1

PE0

P64

P63

P62

P61

VSS

P60

VCC

PD7

PG1

PD6

PG0

PD5

PD4

P97

PD3

VSS

P96

VCC

PD2

P95

PD1

P94

PD0

P93

P92

P91

P74

P75

PC2

P76

P77

PC3

PC4

P80

P81

P82

PC5

PC6

PC7

VCC

P83

VSS

P50

P51

P52

RX72M Group

PLQP0176KB-C

(176-pin LFQFP)

(Top view)

P53^*1

P10

P11

P54

P55

P56

P57

P84

P85

PJ0

VSS

P90

VCC

P47

P46

P45

P44

P43

P42

P41

PJ1

PJ2

VSS_USB

USB0_DP

USB0_DM

VCC_USB

P12

P13

P14

P15

P86

P16

P87

P17

P20

VREFL0

P40

VREFH0

AVCC0

P07

Note:

This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.7, List

of Pin and Pin Functions (176-Pin LFQFP).

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is

enabled.

Figure 1.5

Pin Assignment (176-Pin LFQFP)

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 29 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (1/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

A1

A2

A3

A4

A5

NC

VREFH0

VREFL0

P41

IRQ9-DS AN001

AN116

P92

D18/A18 POE4#

D0[A0/D0] POE4#

RXD7/

SMISO7/ RMII1_CR

SSCL7

ET1_CRS/

DSMCLK4

S_DV/

CAT1_RX

_DV

A6

A7

PD0

PD2

GTIOC1B

LCD_EXT IRQ0

CLK-B

AN108

AN110

D2[A2/D2] MTIOC4D/ GTIOC0B MISOC-A/ ET1_EXO QIO2-B/

LCD_DAT IRQ2

TIC2

CRX0

UT

SDHI_D2- A22-B

B/

MMC_D2-B

A8

TRDATA5 P96

D22/A22

ET1_ERX

D2/

CAT1_ER

XD2

A9

PD3

D3[A3/D3] MTIOC8D/ GTIOC0A RSPCKC- ET1_WOL QIO3-B/

LCD_DAT IRQ3

AN111

TOC2/

A

SDHI_D3- A21-B

POE8#

B/

MMC_D3-B

A10

TRDATA6 PG0

D24

ET1_RX_

CLK/

REF50CK

1/

CAT1_RX

_CLK

A11

A12

A13

A14

A15

PD7

P61

P62

PE1

P70

D7[A7/D7] MTIC5U/

POE0#

SSLC3-A ET1_RX_ QMI-B/

ER/ QIO1-B/

RMII1_RX SDHI_D1-

_ER/ B/

LCD_DAT IRQ7

A17-B

AN107

CAT1_RX MMC_D1-B

_ER

SDCS#/

D0[A0/D0]/

CS1#

ET1_ERX

D1/

RMII1_RX

D1/

CAT1_ER

XD1

RAS#/

D1[A1/D1]/

CS2#

ET1_ERX

D0/

RMII1_RX

D0/

CAT1_ER

XD0

D9[A9/D9]/ MTIOC4C/ GTIOC1B TXD12/

D1[A1/D1] MTIOC3B/

PO18

MMC_D5-B LCD_DAT

A15-B

ANEX1

SMOSI12/

SSDA12/

TXDX12/

SIOX12/

SSLB2-B

SDCLK

CATLINKA

CT0

B1

B2

B3

B4

B5

B6

AVSS0

AVCC0

P42

IRQ10-DS AN002

IRQ14-DS AN006

AN115

P46

P91

D17/A17

SCK7

ET1_COL

DSMDAT5

VCC

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 30 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (2/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

B7

P94

D20/A20

ET1_ERX

D0/

RMII1_RX

D0/

CAT1_ER

XD0

B8

TRDATA4 P95

D21/A21

ET1_ERX

D1/

RMII1_RX

D1/

CAT1_ER

XD1

B9

PD4

PD6

D4[A4/D4] MTIOC8B/

POE11#

SSLC0-A ET1_MDI QSSL-B/

LCD_DAT IRQ4

AN112

AN106

O/

SDHI_CMD A20-B

PMGI1_M -B/

DIO

MMC_CMD

-B

B10

D6[A6/D6] MTIC5V/

MTIOC8A/

SSLC2-A ET1_RX_ QMO-B/

CLK/ QIO0-B/

REF50CK SDHI_D0-

1/ B/

LCD_DAT IRQ6

A18-B

POE4#

CAT1_RX MMC_D0-B

_CLK

B11

B12

VCC

P63

CAS#/

D2[A2/D2]/

CS3#

ET1_ETX

D1/

RMII1_TX

D1/

CAT1_ET

XD1

B13

PE2

D10[A10/ MTIOC4A/ GTIOC0B RXD12/

MMC_D6-B LCD_DAT IRQ7-DS AN100

A14-B

D10]/

PO23/TIC3

SMISO12/

SSCL12/

RXDX12/

SSLB3-B

D2[A2/D2]

B14

B15

PE4

PE7

D12[A12/ MTIOC4D/ GTIOC1A SSLB0-B ET0_ERX

LCD_DAT

A12-B

AN102

AN105

D12]/

MTIOC1A/

D2/

D4[A4/D4] PO28

CAT0_ER

XD2

D15[A15/ MTIOC6A/ GTIOC3A MISOB-B

SDHI_WP/ LCD_DAT IRQ7

MMC_RES A9-B

#-B

D15]/

TOC1

D7[A7/D7]

C1

C2

C3

C4

C5

C6

AVSS1

AVCC1

P05

SSILRCK1

TXD7/

IRQ13

DA1

P44

IRQ12-DS AN004

VSS

P90

D16/A16

ET1_RX_

AN114

DSMCLK5

SMOSI7/ DV/

SSDA7 CAT1_RX

_DV

C7

PD1

D1[A1/D1] MTIOC4B/ GTIOC1A MOSIC-A/

POE0# CTX0

LCD_DAT IRQ1

A23-B

AN109

C8

C9

VCC

TRSYNC1 P97

D23/A23

CS0#

ET1_ERX

D3/

CAT1_ER

XD3

C10

P60

ET1_TX_E

N/

RMII1_TX

D_EN/

CAT1_TX_

EN

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 31 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (3/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

C11

P64

PE5

WE#/

D3[A3/D3]/

CS4#

ET1_ETX

D0/

RMII1_TX

D0/

CAT1_ET

XD0

C12

C13

VSS

D13[A13/ MTIOC4C/ GTIOC0A RSPCKB- ET0_RX_

LCD_DAT IRQ5

A11-B

AN103

D13]/

MTIOC2B

B

CLK/

D5[A5/D5]

REF50CK

0/

CAT0_RX

_CLK

C14

C15

P65

P66

CKE/CS5#

DQM0/

CS6#

MTIOC7D GTIOC2B CTX2

D1

D2

D3

D4

D5

P45

P47

P03

P40

P01

IRQ13-DS AN005

IRQ15-DS AN007

SSIDATA1

IRQ11

DA0

IRQ8-DS AN000

TMCI0

TMCI1

RXD6/

SMISO6/ RR

SSCL6/

CATLEDE QIO3-C

IRQ9

AN119

SSIBCK0

D6

D7

P02

P93

SCK6/

SSIBCK1 TER

CATLEDS

IRQ10

AN120

AN117

D19/A19 POE0#

CTS7#/

RTS7#/

SS7#

ET1_LINK

STA/

CAT1_LIN

KSTA

DSMDAT4

D8

D9

VSS

PD5

D5[A5/D5] MTIC5W/

MTIOC8C/

SSLC1-A ET1_MDC/ QSPCLK-B/ LCD_DAT IRQ5

PMGI1_M SDHI_CLK- A19-B

AN113

MTCLKA/

DC

B/

POE10#

MMC_CLK-

B

D10

TRDATA7 PG1

D25

ET1_RX_

ER/

RMII1_RX

_ER/

CAT1_RX

_ER

D11

D12

PE0

PE3

D8[A8/D8]/ MTIOC3D GTIOC2B SCK12/

MMC_D4-B LCD_DAT

A16-B

ANEX0

AN101

D0[A0/D0]

SSLB1-B

D11[A11/ MTIOC4B/ GTIOC2A CTS12#/

ET0_ERX MMC_D7-B LCD_DAT

D11]/

D3[A3/D3] TOC3/

POE8#

PO26/

RTS12#/

SS12#

D3/

CAT0_ER

XD3

A13-B

D13

D14

VSS

TRDATA0 PG2

D26

ET1_TX_

CLK/

CAT1_TX_

CLK

D15

P67

DQM1/

CS7#

MTIOC7C GTIOC1B CRX2

EPLSOUT

1/

IRQ15

CATSYNC

1

E1

E2

VCL

VSS

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 32 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (4/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

E3

P00

TMRI0

TXD6/

CATLATC QIO2-C

IRQ8

AN118

SMOSI6/ H1

SSDA6/

AUDIO_CL

K

E4

E5

E6

P43

P07

PN0

IRQ11-DS AN003

IRQ15

ADTRG0#

ET1_ETX

D2/

CAT1_ET

XD2

E7

PQ0

SCK11

ET1_CRS/

RMII1_CR

S_DV/

CAT1_RX

_DV

E8

PQ1

PQ3

PQ5

SMISO11/ ET1_COL

SSCL11/

RXD11

E9

RTS11#/

CTS11#/

SS11#

ET1_TX_E

R

E10

ET1_ETX

D0/

RMII1_TX

D0/

CAT1_ET

XD0

E11

PQ4

ET1_RX_

CLK/

REF50CK

1/

CAT1_RX

_CLK

E12

E13

VCC

PE6

PG5

D14[A14/ MTIOC6C/ GTIOC3B MOSIB-B

SDHI_CD/ LCD_DAT IRQ6

MMC_CD-B A10-B

AN104

D14]/

TIC1

D6[A6/D6]

E14

E15

TRCLK

D29

ET1_ETX

D2/

CAT1_ET

XD2

TRSYNC PG4

D28

ET1_ETX

D1/

RMII1_TX

D1/

CAT1_ET

XD1

F1

F2

F3

F4

XCIN

VBATT

TRST#

PF4

PK4

GTADSM0 SSLB1

GTADSM1 SSLB2

ET0_ERX

D2/

CAT0_ER

XD2

F5

PK5

PK6

ET0_ERX

D3/

CAT0_ER

XD3

F6

F7

EMLE

GTIOC1A SSLB3

CATLINKA

CT0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 33 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (5/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

F8

PN1

ET1_ETX

D3/

CAT1_ET

XD3

F9

PQ6

ET1_ETX

D1/

RMII1_TX

D1/

CAT1_ET

XD1

F10

F11

VSS

PM1

PA0

TOC3

GTETRGB SMISO10/ ET1_ERX SDHI_CMD

SSCL10/ D1/ -D/QSSL-A

RXD10 RMII1_RX

D1/

CAT1_ER

XD1

F12

F13

DQM2/

MTIOC4A/ GTIOC0B SSLA1-B ET0_TX_E

BC0#/A0 MTIOC6D/

TIOCA0/

LCD_DAT

A8-B

N/

RMII0_TX

D_EN/

CAT0_TX_

EN/

CATLEDR

UN

PO16/

CACREF

TRDATA1 PG3

D27

ET1_ETX

D0/

RMII1_TX

D0/

CAT1_ET

XD0

F14

F15

TRDATA2 PG6

TRDATA3 PG7

D30

D31

ET1_ETX

D3/

CAT1_ET

XD3

ET1_TX_E

R

G1

G2

G3

G4

G5

XCOUT

VSS

VCC

MD/FINED

PJ5

POE8#

CTS2#/

RTS2#/

SS2#/

EPLSOUT QMI-C/

0/

QIO1-C

CATSYNC

0

SSIRXD0

G6

PF5

WAIT#

SSILRCK0 CATLATC

H0

IRQ4

G7

G8

RES#

PQ2

SMOSI11/ ET1_RX_

SSDA11/ DV/

TXD11

CAT1_RX

_DV

G9

PN2

ET1_TX_

CLK/

CAT1_TX_

CLK

G10

G11

VCC

PM0

TIC3

GTETRGA SCK10

ET1_ERX SDHI_CLK-

D0/

RMII1_RX

D0/

D/QSPCLK-

A

CAT1_ER

XD0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 34 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (6/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

G12

PA1

DQM3/A1 MTIOC0B/ GTIOC2A SCK5/

ET0_WOL

LCD_DAT IRQ11

A7-B

MTCLKC/

MTIOC7B/

TIOCB0/

PO17

SSLA2-B

G13

G14

PA2

PA3

A2

A3

MTIOC7A/ GTIOC1A RXD5/

CATLINKA

ET0_MDI

LCD_DAT

A6-B

PO18

SMISO5/ CT1

SSCL5/

SSLA3-B

MTIOC0D/

MTCLKD/

TIOCD0/

TCLKB/

PO19

RXD5/

SMISO5/ O/

SSCL5

LCD_DAT IRQ6-DS

A5-B

CAT0_MDI

O/

PMGI0_M

DIO

G15

PA4

A4

MTIC5U/

MTCLKA/

TIOCA1/

TMRI0/

TXD5/

SMOSI5/ CAT0_MD

SSDA5/ C/

SSLA0-B CATIRQ/

PMGI0_M

ET0_MDC/

LCD_DAT IRQ5-DS

A4-B

PO20

DC

H1

H2

XTAL

P37

P34

MTIOC0A/

TMCI3/

PO12/

SCK6/

SCK0

ET0_LINK

STA/

CAT0_LIN

KSTA

IRQ4

DSMDAT0

DSMCLK0

POE10#

H3

H4

UPSEL

P35

P33

NMI

EDREQ1 MTIOC0D/

TIOCD0/

RXD6/

PCKO

IRQ3-DS

SMISO6/

SSCL6/

RXD0/

TMRI3/

PO11/

POE4#/

POE11#

SMISO0/

SSCL0/

CRX0

H5

P32

MTIOC0C/

TIOCC0/

TMO3/

TXD6/

VSYNC

IRQ2-DS

SMOSI6/

SSDA6/

TXD0/

PO10/

RTCIC2/

RTCOUT/

POE0#/

POE10#

SMOSI0/

SSDA0/

CTX0/

USB0_VB

USEN

H6

H7

BSCANP

PJ3

EDACK1 MTIOC3C

CTS6#/

RTS6#/

SS6#/

CTS0#/

RTS0#/

SS0#/

ET0_EXO QMO-C/

UT/

QIO0-C

CATREST

OUT

SSITXD0

H8

PQ7

PN3

P73

ET1_TX_E

N/

RMII1_TX

D_EN/

CAT1_TX_

EN

H9

ET1_RX_

ER/

RMII1_RX

_ER/

CAT1_RX

_ER

H10

CS3#

PO16

ET0_WOL

LCD_EXT

CLK-A

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 35 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (7/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

H11

PL0

TIC2

GTETRGA SCK9/

ET0_ERX

RSPCKC D0/

RMII0_RX

D0/

CAT0_ER

XD0

H12

H13

H14

VCC

VSS

PA6

PA5

A6

A5

MTIC5V/

MTCLKB/

TIOCA2/

TMCI3/

PO22/

POE10#

GTETRGB CTS5#/

RTS5#/

ET0_EXO

UT/

CATREST

LCD_DAT

A2-B

SS5#/

MOSIA-B OUT

H15

MTIOC6B/ GTIOC0A RSPCKA- ET0_LINK

TIOCB1/

PO21

LCD_DAT

A3-B

B

STA/

CAT0_LIN

KSTA

J1

J2

EXTAL

TDI

P36

PF2

RXD1/

SMISO1/

SSCL1

CATI2CCL

K

J3

J4

TMS

PF3

P31

MTIOC4D/

TMCI2/

PO9/

CTS1#/

RTS1#/

SS1#/

ET1_MDC/

PMGI1_M

DC

IRQ1-DS

IRQ0-DS

RTCIC1

SSLB0-A

J5

P30

MTIOC4B/

TMRI3/

PO8/

RXD1/

SMISO1/ O/

SSCL1/

ET1_MDI

PMGI1_M

RTCIC0/

POE8#

MISOB-A DIO

J6

J7

PH2

P15

GTETRGC SMOSI7/ CATI2CDA

SSDA7/

TXD7/

TA

MISOA

MTIOC0B/ GTETRGA RXD1/

CATLEDR PIXD0

IRQ5

MTCLKB/

TIOCB2/

TCLKB/

TMCI2/

PO13

SMISO1/ UN

SSCL1/

SCK3/

CRX1-DS/

SSILRCK1

1

J8

J9

P53*

BCLK

PK3

GTETRGD RTS8#/

ET0_TX_E

R

CTS8#/

SS8#/

SSLB0

J10

PL1

TOC2

GTETRGB SMISO9/ ET0_ERX

SSCL9/

RXD9/

MOSIC

D1/

RMII0_RX

D1/

CAT0_ER

XD1

J11

J12

PN5

PB1

ET1_MDC/ QSSL-C

PMGI1_M

DC

A9

MTIOC0C/

MTIOC4C/

TIOCB3/

TMCI0/

TXD4/

ET0_ERX

SMOSI4/ D0/

LCD_TCO IRQ4-DS

N3-B

SSDA4/

TXD6/

RMII0_RX

D0/

PO25

SMOSI6/ CAT0_ER

SSDA6 XD0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 36 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (8/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

J13

J14

J15

P71

PB0

PA7

A18/CS1#

ET0_MDI

O/

CAT0_MDI

O/

PMGI0_M

DIO

DSMCLK3

A8

A7

MTIC5W/

TIOCA3/

PO24

RXD4/

ET0_ERX

SMISO4/ D1/

RMII0_RX

D1/

SMISO6/ CAT0_ER

SSCL6 XD1

LCD_DAT IRQ12

A0-B

SSCL4/

RXD6/

TIOCB2/

PO23

MISOA-B ET0_WOL

LCD_DAT

A1-B

K1

K2

K3

K4

K5

CLKOUT2 PH7

5M

GTIOC0B

CLKOUT PH6

GTIOC0A SSLA3

GTADSM0 SSLA1

GTADSM1 SSLA2

TXD1/

CATLATC

H1

PH4

PH5

CATLEDS

TER

CATLATC

H0

TDO

PF0

PH1

CATI2CDA

SMOSI1/ TA

SSDA1

K6

TOC0

GTETRGB SMISO7/ CATI2CCL

SSCL7/

RXD7/

MOSIA

K

K7

K8

P10

P50

ALE

MTIC5W/

TMRI3

IRQ0

WR0#/

WR#

TXD2/

SMOSI2/ RR

SSDA2/

CATLEDE

SSLB1-A

K9

PK1

PL3

TOC1

GTETRGB SMISO8/ ET0_COL

SSCL8/

RXD8/

MOSIB

K10

GTETRGD RTS9#/

CTS9#/

ET0_RX_

CLK/

SS9#/

SSLC0

REF50CK

0/

CAT0_RX

_CLK

K11

PM2

PB5

GTETRGC SMOSI10/ ET1_ERX SDHI_D0-

SSDA10/ D2/ D/QMO-A/

CAT1_ER QIO0-A

TXD10

XD2

K12

K13

VSS

A13

A11

MTIOC2A/

MTIOC1B/

TIOCB4/

TMRI1/

PO29/

POE4#

SCK9/

RTS9#/

SCK11

ET0_ETX

D0/

RMII0_TX

D0/

LCD_CLK-

B

CAT0_ET

XD0

K14

PB3

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/

TMO0/

SCK4/

SCK6

ET0_RX_

ER/

LCD_TCO

N1-B

RMII0_RX

_ER/

CAT0_RX

_ER

PO27/

POE11#

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 37 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (9/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

K15

P72

A19/CS2#

ET0_MDC/

CAT0_MD

C/

LCD_DAT

A23-A

DSMDAT3

PMGI0_M

DC

L1

L2

PH3

P27

GTETRGD RTS7#/

CTS7#/

CATLEDE

RR

SS7#/

SSLA0

CS7#

MTIOC2B/

TMCI3/

PO7

SCK1/

RSPCKB- /CATIRQ

A

ET1_WOL

L3

L4

TCK

VCC

PF1

P24

SCK1

CS4#/

EDREQ1 MTCLKA/

TIOCB4/

MTIOC4A/

SCK3/

USB0_VB

USEN/

SDHI_WP/

PIXCLK

TMRI1/

PO4

SSIBCK1

L5

L6

CLKOUT2 PJ2

5M

TXD8/

LCD_TCO

N2-A

SMOSI8/

SSDA8/

SSLC3-B

L7

L8

VCC

P52

RD#

RXD2/

CATLEDS

SMISO2/ TER

SSCL2/

SSLB3-A

L9

P81

EDACK0 MTIOC3D/ GTIOC0B SMISO10/ ET0_ETX QIO3-A/

PO27 SSCL10/ D0/

RXD10 RMII0_TX MMC_D3-A

LCD_DAT

SDHI_CD/ A13-A

D0/

CAT0_ET

XD0/

CATI2CCL

K

L10

L11

L12

PL7

P77

PN4

GTIOC2B

ET0_MDI

O/

CAT0_MDI

O/

PMGI0_M

DIO

CS7#

PO23

SMOSI11/ ET0_RX_ QSPCLK-A/ LCD_DAT

SSDA11/ ER/

SDHI_CLK- A17-A

TXD11

RMII0_RX A/

_ER/

CAT0_RX

_ER

MMC_CLK-

A

ET1_MDI QSPCLK-C

O/

PMGI1_M

DIO

L13

L14

VCC

PB2

A10

A12

TIOCC3/

TCLKC/

PO26

CTS4#/

RTS4#/

SS4#/

CTS6#/

RTS6#/

SS6#

ET0_RX_

CLK/

REF50CK

0/

CAT0_RX

_CLK

LCD_TCO

N2-B

L15

PB4

TIOCA4/

PO28

CTS9#/

SS9#/

ET0_TX_E

N/

LCD_TCO

N0-B

SS11#/

CTS11#/

RTS11#

RMII0_TX

D_EN/

CAT0_TX_

EN

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 38 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (10/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

M1

P26

CS6#

MTIOC2A/

TMO1/PO6

TXD1/

SMOSI1/ UT/

ET1_EXO

SSDA1/

CTS3#/

RTS3#/

SS3#/

CATLINKA

CT1

MOSIB-A

M2

P23

EDACK0 MTIOC3D/ GTIOC0A TXD3/

SDHI_D1-

C/PIXD7

MTCLKD/

TIOCD3/

PO3

SMOSI3/

SSDA3/

CTS0#/

RTS0#/

SS0#/

CTX1/

SSIBCK0

M3

CLKOUT P25

CS5#/

EDACK1 MTCLKB/

TIOCA4/

MTIOC4C/

RXD3/

SDHI_CD/

HSYNC

ADTRG0#

SMISO3/

SSCL3/

SSIDATA1

PO5

M4

M5

VSS

PJ0

MTIOC6B

MTIOC6D

SCK8/

SSLC1-B 0/

CATSYNC

EPLSOUT

LCD_DAT

A0-A

0

M6

P84

ET1_LINK

STA/

LCD_DAT

A2-A

CAT1_LIN

KSTA

M7

M8

VSS

P51

WR1#/

BC1#/

WAIT#

SCK2/

SSLB2-A

M9

P83

PK0

PL5

EDACK1 MTIOC4C GTIOC0A SCK10/

ET0_CRS/

RMII0_CR

S_DV/

CAT0_RX

_DV

LCD_DAT

A8-A

DSMCLK1

SS10#/

CTS10#

M10

M11

TIC1

GTETRGA SCK8/

ET0_MDC/

RSPCKB CAT0_MD

C/

PMGI0_M

DC

GTADSM1 SSLC2

ET0_ETX

D1/

RMII0_TX

D1/

CAT0_ET

XD1

M12

PL6

GTIOC2A SSLC3

ET0_TX_E

N/

RMII0_TX

D_EN/

CAT0_TX_

EN

M13

M14

PM7

PC0

GTIOC3B

ET0_CRS/ SDHI_WP

RMII0_CR

S_DV/

CAT0_RX

_DV

A16

MTIOC3C/

TCLKC/

PO17

CTS5#/

RTS5#/

SS5#/

ET0_ERX

D3/

CAT0_ER

IRQ14

SSLA1-A XD3

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 39 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (11/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

M15

PB6

A14

MTIOC3D/

TIOCA5/

PO30

RXD9/

SMISO9/ D1/

SSCL9/

ET0_ETX

RMII0_TX

SMISO11/ D1/

SSCL11/

RXD11

CAT0_ET

XD1

N1

P22

EDREQ0 MTIOC3B/ GTIOC1A SCK0/

SDHI_D0-

C/PIXD6

MTCLKC/

TIOCC3/

USB0_OV

RCURB/

AUDIO_CL

K

TMO0/PO2

N2

N3

PH0

P86

TIC0

GTETRGA SCK7/

CATLEDR

RSPCKA UN

MTIOC4D/ GTIOC2B SMISO10/ CATLINKA PIXD1

TIOCA0

SSCL10/ CT0

RXD10

N4

N5

P85

P13

MTIOC6C/

TIOCC0

LCD_DAT

A1-A

WR2#/

BC2#

MTIOC0B/ GTADSM1 TXD2/

LCD_TCO IRQ3

N0-A

ADTRG1#

TIOCA5/

TMO3/

PO13

SMOSI2/

SSDA2/

SDA0[FM+

]

N6

PJ1

MTIOC6A

RXD8/

SMISO8/ 1/

EPLSOUT

LCD_TCO

N3-A

SSCL8/

CATSYNC

SSLC2-B

1

N7

CLKOUT2 P56

5M

EDACK1 MTIOC3C/

TIOCA1

SCK7/

RSPCKC-

B

LCD_DAT

A4-A

DSMDAT1

N8

N9

VCC

UB

PC7

P80

A23/CS0# MTIOC3A/ GTIOC3A TXD8/

ET0_COL MMC_D7-A LCD_DAT IRQ14

A9-A

MTCLKB/

TMO2/

SMOSI8/

SSDA8/

PO31/

TOC0/

CACREF

SMOSI10/

SSDA10/

TXD10/

MISOA-A

N10

EDREQ0 MTIOC3B/

PO26

SCK10/

RTS10#

ET0_TX_E QIO2-A/

LCD_DAT

N/

SDHI_WP/ A14-A

RMII0_TX MMC_D2-A

D_EN/

CAT0_TX_

EN/

CATLATC

H0

N11

N12

PK2

P76

GTETRGC SMOSI8/ ET0_RX_

SSDA8/

TXD8/

MISOB

DV/

CAT0_RX

_DV

CS6#

PO22

SMISO11/ ET0_RX_ QSSL-A/

LCD_DAT

SDHI_CMD A18-A

REF50CK -A/

SSCL11/

RXD11

CLK/

0/

MMC_CMD

CAT0_RX -A

_CLK

N13

N14

PM6

PC1

GTIOC3A

ET0_TX_ SDHI_CD

CLK/

CAT0_TX

_CLK

A17

MTIOC3A/

TCLKD/

PO18

SCK5/

ET0_ERX

LCD_DAT IRQ12

A22-A

SSLA2-A D2/

CAT0_ER

XD2

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 40 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (12/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

N15

PB7

A15

MTIOC3B/

TIOCB5/

PO31

TXD9/

SMOSI9/ RMII0_CR

SSDA9/ S_DV/

ET0_CRS/

SMOSI11/ CAT0_RX

SSDA11/ _DV

TXD11

P1

P2

PK7

P17

GTIOC1B

CATLINKA

CT1

MTIOC3A/ GTIOC0B SCK1/

EPLSOUT SDHI_D3-

0/

SMOSI3/ CATSYNC

IRQ7

IRQ8

ADTRG1#

MTIOC3B/

MTIOC4B/

TIOCB0/

TCLKD/

TMO1/

TXD3/

C/PIXD3

SSDA3/

SDA2-DS/

SSITXD0

0

PO15/

POE8#

P3

P4

P20

P14

MTIOC1A/

TIOCB3/

TMRI0/

PO0

TXD0/

SDHI_CMD

-C/PIXD4

SMOSI0/

SSDA0/

SDA1/

USB0_ID/

SSIRXD0

MTIOC3A/ GTETRGD CTS1#/

LCD_CLK- IRQ4

A

MTCLKA/

TIOCB5/

TCLKA/

TMRI2/

PO15

RTS1#/

SS1#/

CTX1/

USB0_OV

RCURA

P5

P6

P7

VCC_USB

VSS_USB

P57

P11

RXD7/

LCD_DAT

A3-A

SMISO7/

SSCL7/

SSLC0-B

P8

MTIC5V/

TMCI3

SCK2

EPLSOUT

1/

LCD_DAT IRQ1

A7-A

CATSYNC

1

P9

VSS

P10

P82

EDREQ1 MTIOC4A/ GTIOC2A SMOSI10/ ET0_ETX MMC_D4-A LCD_DAT

PO28

SSDA10/ D1/

TXD10 RMII0_TX

A12-A

D1/

CAT0_ET

XD1/

CATI2CDA

TA

P11

PC4

A20/CS3# MTIOC3D/ GTETRGC SCK5/

ET0_TX_ QMI-A/

LCD_DAT

A15-A

MTCLKC/

TMCI1/

PO25/

CTS8#/

SS8#/

SS10#/

CTS10#/

RTS10#/

SSLA0-A

CLK/

CAT0_TX_ SDHI_D1-

CLK/

A/

QIO1-A/

POE0#

CATSYNC MMC_D1-A

0

P12

P13

PL2

PC2

GTETRGC SMOSI9/ ET0_RX_

SSDA9/

TXD9/

MISOC

ER/

RMII0_RX

_ER/

CAT0_RX

_ER

A18

MTIOC4B/ GTIOC2B RXD5/

ET0_RX_ SDHI_D3- LCD_DAT

TCLKA/

PO21

SMISO5/ DV/

A/

A19-A

SSCL5/

CAT0_RX MMC_CD-A

SSLA3-A _DV

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 41 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (13/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

P14

P15

R1

PM4

PM3

P21

GTADSM0

ET0_ETX SDHI_D2-

D2/

D/QIO2-A

CAT0_ET

XD2

GTETRGD RTS10#/

CTS10#/

ET1_ERX SDHI_D1-

D3/ D/QMI-A/

CAT1_ER QIO1-A

XD3

SS10#

MTIOC1B/ GTIOC2A RXD0/

SDHI_CLK-

C/PIXD5

IRQ9

MTIOC4A/

TIOCA3/

TMCI0/

PO1

SMISO0/

SSCL0/

SCL1/

USB0_EXI

CEN/

SSILRCK0

R2

R3

P87

P16

MTIOC4C/ GTIOC1B SMOSI10/ EPLSOUT SDHI_D2-

TIOCA2

SSDA10/ 1/

C/PIXD2

TXD10

CATSYNC

1

MTIOC3C/

MTIOC3D/

TIOCB1/

TCLKC/

TMO2/

TXD1/

IRQ6

ADTRG0#

SMOSI1/

SSDA1/

RXD3/

SMISO3/

SSCL3/

SCL2-DS/

USB0_VB

USEN/

PO14/

RTCOUT

USB0_VB

US/

USB0_OV

RCURB

R4

P12

WR3#/

BC3#

MTIC5U/

TMCI1

GTADSM0 RXD2/

LCD_TCO IRQ2

N1-A

SMISO2/

SSCL2/

SCL0[FM+

]

R5

R6

R7

USB0_DM

USB0_DP

P54

P55

PC6

D1[A1/D1]/ MTIOC4B/

EDACK0/ TMCI1

ALE

CTS2#/

RTS2#/

SS2#/

MOSIC-B/ KSTA

CTX1

ET0_LINK

STA/

CAT0_LIN

LCD_DAT

A6-A

R8

R9

D0[A0/D0]/ MTIOC4D/

EDREQ0/ TMO3

WAIT#

TXD7/

SMOSI7/ UT

SSDA7/

MISOC-B/

CRX1

ET0_EXO

LCD_DAT IRQ10

A5-A

D2[A2/D2]/ MTIOC3C/ GTIOC3B RXD8/

ET0_ETX MMC_D6-A LCD_DAT IRQ13

A22/CS1# MTCLKA/

TMCI2/

SMISO8/ D3/

A10-A

SSCL8/

CAT0_ET

PO30/TIC0

SMISO10/ XD3/

SSCL10/ CATLATC

RXD10/

H1

MOSIA-A

R10

R11

PC5

PC3

D3[A3/D3]/ MTIOC3B/ GTIOC1A SCK8/

ET0_ETX MMC_D5-A LCD_DAT

A21/CS2#/ MTCLKD/

RTS8#/

SCK10/

RSPCKA- XD2

A

D2/

A11-A

WAIT#

TMRI2/

PO29

CAT0_ET

A19

MTIOC4D/ GTIOC1B TXD5/

ET0_TX_E QMO-A/

LCD_DAT

A16-A

TCLKB/

PO24

SMOSI5/

SSDA5

R

QIO0-A/

SDHI_D0-

A/

MMC_D0-A

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 42 of 158

RX72M Group

1. Overview

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (14/14)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

224-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

R12

R13

R14

R15

PL4

P75

P74

PM5

GTADSM0 SSLC1

ET0_ETX

D0/

RMII0_TX

D0/

CAT0_ET

XD0

CS5#

PO20

SCK11/

RTS11#

ET0_ERX SDHI_D2- LCD_DAT

D0/

RMII0_RX MMC_RES

D0/

CAT0_ER

XD0

DSMDAT2

DSMCLK2

A/

A20-A

#-A

A20/CS4# PO19

SS11#/

CTS11#

ET0_ERX

D1/

RMII0_RX

D1/

CAT0_ER

XD1

LCD_DAT

A21-A

GTADSM1

ET0_ETX SDHI_D3-

D3/

D/QIO3-A

CAT0_ET

XD3

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 43 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (1/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

A1

A2

A3

A4

A5

A6

A7

A8

AVSS0

AVCC0

VREFL0

P42

P46

IRQ10-DS AN002

IRQ14-DS AN006

VCC

VSS

P94

D20/A20

D23/A23

ET1_ERX

D0/

RMII1_RX

D0/

CAT1_ER

XD0

A9

VCC

A10

TRSYNC1 P97

ET1_ERX

D3/

CAT1_ER

XD3

A11

A12

A13

A14

A15

PD6

D6[A6/D6] MTIC5V/

MTIOC8A/

SSLC2-A ET1_RX_ QMO-B/

CLK/ QIO0-B/

REF50CK SDHI_D0-

1/ B/

LCD_DAT IRQ6

A18-B

AN106

POE4#

CAT1_RX MMC_D0-B

_CLK

P60

P63

PE1

PE2

CS0#

ET1_TX_E

N/

RMII1_TX

D_EN/

CAT1_TX_

EN

CAS#/

D2[A2/D2]/

CS3#

ET1_ETX

D1/

RMII1_TX

D1/

CAT1_ET

XD1

D9[A9/D9]/ MTIOC4C/ GTIOC1B TXD12/

D1[A1/D1] MTIOC3B/

PO18

MMC_D5-B LCD_DAT

A15-B

ANEX1

SMOSI12/

SSDA12/

TXDX12/

SIOX12/

SSLB2-B

D10[A10/ MTIOC4A/ GTIOC0B RXD12/

MMC_D6-B LCD_DAT IRQ7-DS AN100

A14-B

D10]/

PO23/TIC3

SMISO12/

SSCL12/

RXDX12/

SSLB3-B

D2[A2/D2]

B1

B2

B3

B4

B5

B6

B7

P05

P07

P40

P41

P47

P91

P92

SSILRCK1

IRQ13

IRQ15

DA1

ADTRG0#

IRQ8-DS AN000

IRQ9-DS AN001

IRQ15-DS AN007

AN115

D17/A17

SCK7

ET1_COL

ET1_CRS/

DSMDAT5

DSMCLK4

D18/A18 POE4#

RXD7/

AN116

SMISO7/ RMII1_CR

SSCL7

S_DV/

CAT1_RX

_DV

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 44 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (2/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

B8

PD1

D1[A1/D1] MTIOC4B/ GTIOC1A MOSIC-A/

POE0# CTX0

LCD_DAT IRQ1

A23-B

AN109

B9

TRDATA5 P96

D22/A22

ET1_ERX

D2/

CAT1_ER

XD2

B10

PD4

D4[A4/D4] MTIOC8B/

POE11#

SSLC0-A ET1_MDI QSSL-B/

LCD_DAT IRQ4

AN112

O/

SDHI_CMD A20-B

PMGI1_M -B/

DIO

MMC_CMD

-B

B11

TRDATA7 PG1

D25

ET1_RX_

ER/

RMII1_RX

_ER/

CAT1_RX

_ER

B12

B13

VSS

P64

WE#/

D3[A3/D3]/

CS4#

ET1_ETX

D0/

RMII1_TX

D0/

CAT1_ET

XD0

B14

B15

PE0

PE3

D8[A8/D8]/ MTIOC3D GTIOC2B SCK12/

MMC_D4-B LCD_DAT

A16-B

ANEX0

AN101

D0[A0/D0]

SSLB1-B

D11[A11/ MTIOC4B/ GTIOC2A CTS12#/

ET0_ERX MMC_D7-B LCD_DAT

D11]/

D3[A3/D3] TOC3/

POE8#

PO26/

RTS12#/

SS12#

D3/

CAT0_ER

XD3

A13-B

C1

C2

C3

C4

C5

C6

AVSS1

AVCC1

VREFH0

P43

IRQ11-DS AN003

IRQ13-DS AN005

AN114

P45

P90

D16/A16

TXD7/

ET1_RX_

DSMCLK5

SMOSI7/ DV/

SSDA7 CAT1_RX

_DV

C7

C8

PD0

PD2

D0[A0/D0] POE4#

GTIOC1B

LCD_EXT IRQ0

CLK-B

AN108

AN110

D2[A2/D2] MTIOC4D/ GTIOC0B MISOC-A/ ET1_EXO QIO2-B/

TIC2 CRX0 UT

LCD_DAT IRQ2

SDHI_D2- A22-B

B/

MMC_D2-B

C9

PD3

D3[A3/D3] MTIOC8D/ GTIOC0A RSPCKC- ET1_WOL QIO3-B/

LCD_DAT IRQ3

AN111

TOC2/

A

SDHI_D3- A21-B

POE8#

B/

MMC_D3-B

C10

TRDATA6 PG0

D24

ET1_RX_

CLK/

REF50CK

1/

CAT1_RX

_CLK

C11

C12

VCC

P62

RAS#/

D1[A1/D1]/

CS2#

ET1_ERX

D0/

RMII1_RX

D0/

CAT1_ER

XD0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 45 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (3/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

C13

PE4

D12[A12/ MTIOC4D/ GTIOC1A SSLB0-B ET0_ERX

LCD_DAT

A12-B

AN102

D12]/

MTIOC1A/

D2/

D4[A4/D4] PO28

CAT0_ER

XD2

C14

C15

VSS

P70

P01

SDCLK

TMCI0

CATLINKA

CT0

D1

RXD6/

CATLEDE

IRQ9

AN119

AN120

SMISO6/ RR

SSCL6/

SSIBCK0

D2

P02

TMCI1

TMRI0

SCK6/

SSIBCK1 TER

CATLEDS

IRQ10

D3

D4

P03

P00

SSIDATA1

IRQ11

IRQ8

DA0

TXD6/

CATLATC

AN118

SMOSI6/ H1

SSDA6/

AUDIO_CL

K

D5

D6

P44

P93

IRQ12-DS AN004

AN117

D19/A19 POE0#

D21/A21

CTS7#/

RTS7#/

SS7#

ET1_LINK

STA/

CAT1_LIN

KSTA

DSMDAT4

D7

TRDATA4 P95

ET1_ERX

D1/

RMII1_RX

D1/

CAT1_ER

XD1

D8

D9

VSS

PD5

D5[A5/D5] MTIC5W/

MTIOC8C/

SSLC1-A ET1_MDC/ QSPCLK-B/ LCD_DAT IRQ5

PMGI1_M SDHI_CLK- A19-B

AN113

AN107

MTCLKA/

POE10#

DC

B/

MMC_CLK-

B

D10

D11

D12

PD7

P61

PE5

D7[A7/D7] MTIC5U/

POE0#

SSLC3-A ET1_RX_ QMI-B/

ER/ QIO1-B/

RMII1_RX SDHI_D1-

_ER/ B/

LCD_DAT IRQ7

A17-B

CAT1_RX MMC_D1-B

_ER

SDCS#/

D0[A0/D0]/

CS1#

ET1_ERX

D1/

RMII1_RX

D1/

CAT1_ER

XD1

D13[A13/ MTIOC4C/ GTIOC0A RSPCKB- ET0_RX_

LCD_DAT IRQ5

A11-B

AN103

AN105

D13]/

MTIOC2B

B

CLK/

D5[A5/D5]

REF50CK

0/

CAT0_RX

_CLK

D13

D14

VCC

PE7

D15[A15/ MTIOC6A/ GTIOC3A MISOB-B

SDHI_WP/ LCD_DAT IRQ7

MMC_RES A9-B

#-B

D15]/

TOC1

D7[A7/D7]

D15

E1

P65

PJ5

CKE/CS5#

POE8#

CTS2#/

RTS2#/

SS2#/

EPLSOUT

0/

CATSYNC

0

SSIRXD0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 46 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (4/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

E2

E3

EMLE

VSS

PF5

PE6

WAIT#

SSILRCK0 CATLATC

H0

IRQ4

E4

E12

D14[A14/ MTIOC6C/ GTIOC3B MOSIB-B

D14]/

SDHI_CD/ LCD_DAT IRQ6

MMC_CD-B A10-B

AN104

TIC1

D6[A6/D6]

E13

E14

TRDATA0 PG2

TRDATA1 PG3

D26

ET1_TX_

CLK/

CAT1_TX_

CLK

D27

ET1_ETX

D0/

RMII1_TX

D0/

CAT1_ET

XD0

E15

P67

DQM1/

CS7#

MTIOC7C GTIOC1B CRX2

EPLSOUT

1/

IRQ15

CATSYNC

1

F1

F2

F3

VBATT

VCL

PJ3

EDACK1 MTIOC3C

CTS6#/

RTS6#/

SS6#/

CTS0#/

RTS0#/

SS0#/

ET0_EXO

UT/

CATREST

OUT

SSITXD0

F4

BSCANP

P66

F12

DQM0/

CS6#

MTIOC7D GTIOC2B CTX2

F13

TRSYNC PG4

D28

ET1_ETX

D1/

RMII1_TX

D1/

CAT1_ET

XD1

F14

PA0

DQM2/

BC0#/A0 MTIOC6D/

TIOCA0/

MTIOC4A/ GTIOC0B SSLA1-B ET0_TX_E

LCD_DAT

A8-B

N/

RMII0_TX

D_EN/

CAT0_TX_

EN/

PO16/

CACREF

CATLEDR

UN

F15

G1

VSS

XCIN

G2

XCOUT

MD/FINED

G3

G4

TRST#

TRCLK

PF4

PG5

G12

D29

D30

ET1_ETX

D2/

CAT1_ET

XD2

G13

TRDATA2 PG6

ET1_ETX

D3/

CAT1_ET

XD3

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 47 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (5/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

G14

PA1

DQM3/A1 MTIOC0B/ GTIOC2A SCK5/

ET0_WOL

LCD_DAT IRQ11

A7-B

MTCLKC/

MTIOC7B/

TIOCB0/

PO17

SSLA2-B

G15

H1

VCC

XTAL

VSS

P37

H2

H3

RES#

UPSEL

H4

P35

PA4

NMI

H12

A4

A3

MTIC5U/

MTCLKA/

TIOCA1/

TMRI0/

TXD5/

SMOSI5/ CAT0_MD

SSDA5/ C/

SSLA0-B CATIRQ/

PMGI0_M

ET0_MDC/

LCD_DAT IRQ5-DS

A4-B

PO20

DC

H13

PA3

PA2

MTIOC0D/

MTCLKD/

TIOCD0/

TCLKB/

PO19

RXD5/

SMISO5/ O/

SSCL5 CAT0_MDI

ET0_MDI

LCD_DAT IRQ6-DS

A5-B

O/

PMGI0_M

DIO

H14

H15

A2

MTIOC7A/ GTIOC1A RXD5/

PO18

CATLINKA

SMISO5/ CT1

SSCL5/

SSLA3-B

LCD_DAT

A6-B

TRDATA3 PG7

D31

ET1_TX_E

R

J1

J2

J3

EXTAL

VCC

P36

P34

MTIOC0A/

TMCI3/

SCK6/

SCK0

ET0_LINK

STA/

IRQ4

DSMDAT0

PO12/

POE10#

CAT0_LIN

KSTA

J4

TMS

VSS

PF3

PA5

J12

A5

MTIOC6B/ GTIOC0A RSPCKA- ET0_LINK

LCD_DAT

A3-B

TIOCB1/

PO21

B

STA/

CAT0_LIN

KSTA

J13

J14

PA7

PA6

A7

A6

TIOCB2/

PO23

MISOA-B ET0_WOL

LCD_DAT

A1-B

J15

MTIC5V/

MTCLKB/

TIOCA2/

TMCI3/

GTETRGB CTS5#/

ET0_EXO

UT/

CATREST

LCD_DAT

A2-B

RTS5#/

SS5#/

MOSIA-B OUT

PO22/

POE10#

K1

P33

EDREQ1 MTIOC0D/

TIOCD0/

RXD6/

PCKO

IRQ3-DS

DSMCLK0

SMISO6/

SSCL6/

RXD0/

TMRI3/

PO11/

POE4#/

POE11#

SMISO0/

SSCL0/

CRX0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 48 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (6/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

K2

P32

MTIOC0C/

TIOCC0/

TMO3/

TXD6/

VSYNC

IRQ2-DS

SMOSI6/

SSDA6/

TXD0/

PO10/

RTCIC2/

RTCOUT/

POE0#/

POE10#

SMOSI0/

SSDA0/

CTX0/

USB0_VB

USEN

K3

TDI

PF2

RXD1/

SMISO1/

SSCL1

CATI2CCL

K

K4

TCK

PF1

PB2

SCK1

K12

A10

TIOCC3/

TCLKC/

PO26

CTS4#/

RTS4#/

SS4#/

ET0_RX_

CLK/

LCD_TCO

N2-B

REF50CK

0/

CAT0_RX

_CLK

CTS6#/

RTS6#/

SS6#

K13

P71

A18/CS1#

ET0_MDI

O/

DSMCLK3

CAT0_MDI

O/

PMGI0_M

DIO

K14

K15

VCC

PB0

A8

MTIC5W/

TIOCA3/

PO24

RXD4/

SMISO4/ D1/

SSCL4/

RXD6/

ET0_ERX

LCD_DAT IRQ12

A0-B

RMII0_RX

D1/

SMISO6/ CAT0_ER

SSCL6

XD1

L1

L2

P31

P30

MTIOC4D/

TMCI2/

PO9/

CTS1#/

RTS1#/

SS1#/

ET1_MDC/

PMGI1_M

DC

IRQ1-DS

RTCIC1

SSLB0-A

MTIOC4B/

TMRI3/

PO8/

RXD1/

SMISO1/ O/

SSCL1/

ET1_MDI

IRQ0-DS

PMGI1_M

RTCIC0/

POE8#

MISOB-A DIO

L3

L4

TDO

PF0

TXD1/

SMOSI1/ TA

SSDA1

CATI2CDA

CLKOUT P25

CS5#/

EDACK1 MTCLKB/

TIOCA4/

MTIOC4C/

RXD3/

SDHI_CD/

HSYNC

ADTRG0#

SMISO3/

SSCL3/

SSIDATA1

PO5

L12

L13

PB6

A14

MTIOC3D/

TIOCA5/

PO30

RXD9/

SMISO9/ D1/

SSCL9/

SMISO11/ D1/

SSCL11/

RXD11

ET0_ETX

RMII0_TX

CA

T0_ET

XD1

PB3

PB1

A11

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/

TMO0/

SCK4/

SCK6

ET0_RX_

ER/

RMII0_RX

_ER/

CAT0_RX

_ER

LCD_TCO

N1-B

PO27/

POE11#

L14

A9

MTIOC0C/

MTIOC4C/

TIOCB3/

TMCI0/

TXD4/

SMOSI4/ D0/

SSDA4/

TXD6/

ET0_ERX

LCD_TCO IRQ4-DS

N3-B

RMII0_RX

D0/

PO25

SMOSI6/ CAT0_ER

SSDA6 XD0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 49 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (7/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

L15

P72

A19/CS2#

ET0_MDC/

CAT0_MD

C/

LCD_DAT

A23-A

DSMDAT3

PMGI0_M

DC

M1

M2

P27

P26

CS7#

CS6#

MTIOC2B/

TMCI3/

PO7

SCK1/

RSPCKB- /CATIRQ

A

ET1_WOL

MTIOC2A/

TMO1/PO6

TXD1/

SMOSI1/ UT/

ET1_EXO

SSDA1/

CTS3#/

RTS3#/

SS3#/

CATLINKA

CT1

MOSIB-A

M3

M4

P24

P86

CS4#/

EDREQ1 MTCLKA/

TIOCB4/

MTIOC4A/

SCK3/

USB0_VB

USEN/

SDHI_WP/

PIXCLK

TMRI1/

PO4

SSIBCK1

MTIOC4D/ GTIOC2B SMISO10/ CATLINKA PIXD1

TIOCA0

SSCL10/ CT0

RXD10

M5

M6

CLKOUT2 PJ2

5M

TXD8/

LCD_TCO

N2-A

SMOSI8/

SSDA8/

SSLC3-B

PJ1

MTIOC6A

RXD8/

SMISO8/ 1/

EPLSOUT

LCD_TCO

N3-A

SSCL8/

CATSYNC

SSLC2-B

1

M7

M8

P85

P55

MTIOC6C/

TIOCC0

LCD_DAT

A1-A

D0[A0/D0]/ MTIOC4D/

EDREQ0/ TMO3

WAIT#

TXD7/

SMOSI7/ UT

SSDA7/

ET0_EXO

LCD_DAT IRQ10

A5-A

MISOC-B/

CRX1

M9

P50

PC5

WR0#/

WR#

TXD2/

SMOSI2/ RR

SSDA2/

CATLEDE

SSLB1-A

M10

D3[A3/D3]/ MTIOC3B/ GTIOC1A SCK8/

ET0_ETX MMC_D5-A LCD_DAT

A21/CS2#/ MTCLKD/

RTS8#/

SCK10/

RSPCKA- XD2

A

D2/

CAT0_ET

A11-A

WAIT#

TMRI2/

PO29

M11

P81

EDACK0 MTIOC3D/ GTIOC0B SMISO10/ ET0_ETX QIO3-A/

LCD_DAT

PO27

SSCL10/ D0/

SDHI_CD/ A13-A

RXD10 RMII0_TX MMC_D3-A

D0/

CAT0_ET

XD0/

CATI2CCL

K

M12

M13

P77

PB7

CS7#

A15

PO23

SMOSI11/ ET0_RX_ QSPCLK-A/ LCD_DAT

SSDA11/ ER/

SDHI_CLK- A17-A

TXD11

RMII0_RX A/

_ER/

CAT0_RX

_ER

MMC_CLK-

A

MTIOC3B/

TIOCB5/

PO31

TXD9/

ET0_CRS/

SMOSI9/ RMII0_CR

SSDA9/ S_DV/

SMOSI11/ CAT0_RX

SSDA11/ _DV

TXD11

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 50 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (8/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

M14

PB5

A13

MTIOC2A/

MTIOC1B/

TIOCB4/

TMRI1/

SCK9/

RTS9#/

SCK11

ET0_ETX

D0/

RMII0_TX

D0/

LCD_CLK-

B

PO29/

POE4#

CAT0_ET

XD0

M15

PB4

A12

TIOCA4/

PO28

CTS9#/

SS9#/

ET0_TX_E

N/

LCD_TCO

N0-B

SS11#/

CTS11#/

RTS11#

RMII0_TX

D_EN/

CAT0_TX_

EN

N1

N2

VCC

P23

EDACK0 MTIOC3D/ GTIOC0A TXD3/

SDHI_D1-

C/PIXD7

MTCLKD/

TIOCD3/

PO3

SMOSI3/

SSDA3/

CTS0#/

RTS0#/

SS0#/

CTX1/

SSIBCK0

N3

N4

P22

P15

EDREQ0 MTIOC3B/ GTIOC1A SCK0/

SDHI_D0-

C/PIXD6

MTCLKC/

TIOCC3/

TMO0/PO2

USB0_OV

RCURB/

AUDIO_CL

K

MTIOC0B/ GTETRGA RXD1/

CATLEDR PIXD0

IRQ5

MTCLKB/

TIOCB2/

TCLKB/

TMCI2/

PO13

SMISO1/ UN

SSCL1/

SCK3/

CRX1-DS/

SSILRCK1

N5

P12

WR3#/

BC3#

MTIC5U/

TMCI1

GTADSM0 RXD2/

LCD_TCO IRQ2

N1-A

SMISO2/

SSCL2/

SCL0[FM+

]

N6

N7

N8

PJ0

P84

P54

MTIOC6B

MTIOC6D

SCK8/

SSLC1-B 0/

CATSYNC

EPLSOUT

LCD_DAT

A0-A

0

ET1_LINK

STA/

CAT1_LIN

KSTA

LCD_DAT

A2-A

D1[A1/D1]/ MTIOC4B/

EDACK0/ TMCI1

ALE

CTS2#/

RTS2#/

SS2#/

ET0_LINK

STA/

CAT0_LIN

LCD_DAT

A6-A

MOSIC-B/ KSTA

CTX1

N9

P51

PC7

WR1#/

BC1#/

WAIT#

SCK2/

SSLB2-A

N10

UB

A23/CS0# MTIOC3A/ GTIOC3A TXD8/

ET0_COL MMC_D7-A LCD_DAT IRQ14

A9-A

MTCLKB/

TMO2/

SMOSI8/

SSDA8/

PO31/

TOC0/

CACREF

SMOSI10/

SSDA10/

TXD10/

MISOA-A

N11

P82

EDREQ1 MTIOC4A/ GTIOC2A SMOSI10/ ET0_ETX MMC_D4-A LCD_DAT

PO28 SSDA10/ D1/ A12-A

TXD10 RMII0_TX

D1/

CAT0_ET

XD1/

CATI2CDA

TA

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 51 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (9/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

N12

PC3

A19

MTIOC4D/ GTIOC1B TXD5/

ET0_TX_E QMO-A/

LCD_DAT

A16-A

TCLKB/

PO24

SMOSI5/

SSDA5

R

QIO0-A/

SDHI_D0-

A/

MMC_D0-A

N13

N14

PC0

P73

A16

MTIOC3C/

TCLKC/

PO17

CTS5#/

RTS5#/

SS5#/

ET0_ERX

D3/

CAT0_ER

IRQ14

SSLA1-A XD3

CS3#

PO16

ET0_WOL

LCD_EXT

CLK-A

N15

P1

VSS

P2

P17

MTIOC3A/ GTIOC0B SCK1/

EPLSOUT SDHI_D3-

0/ C/PIXD3

SMOSI3/ CATSYNC

IRQ7

ADTRG1#

MTIOC3B/

MTIOC4B/

TIOCB0/

TCLKD/

TMO1/

TXD3/

SSDA3/

SDA2-DS/

SSITXD0

0

PO15/

POE8#

P3

P4

P87

P14

MTIOC4C/ GTIOC1B SMOSI10/ EPLSOUT SDHI_D2-

TIOCA2 SSDA10/ 1/ C/PIXD2

TXD10 CATSYNC

1

MTIOC3A/ GTETRGD CTS1#/

LCD_CLK- IRQ4

A

MTCLKA/

TIOCB5/

TCLKA/

TMRI2/

PO15

RTS1#/

SS1#/

CTX1/

USB0_OV

RCURA

P5

P6

P7

VCC_USB

VSS_USB

P57

RXD7/

LCD_DAT

A3-A

SMISO7/

SSCL7/

SSLC0-B

P8

P9

P10

P52

ALE

RD#

MTIC5W/

TMRI3

IRQ0

RXD2/

CATLEDS

SMISO2/ TER

SSCL2/

SSLB3-A

P10

P11

P83

PC6

EDACK1 MTIOC4C GTIOC0A SCK10/

ET0_CRS/

RMII0_CR

S_DV/

CAT0_RX

_DV

LCD_DAT

A8-A

DSMCLK1

SS10#/

CTS10#

D2[A2/D2]/ MTIOC3C/ GTIOC3B RXD8/

ET0_ETX MMC_D6-A LCD_DAT IRQ13

A22/CS1# MTCLKA/

TMCI2/

SMISO8/ D3/

A10-A

SSCL8/

CAT0_ET

PO30/TIC0

SMISO10/ XD3/

SSCL10/ CATLATC

RXD10/

H1

MOSIA-A

P12

PC4

A20/CS3# MTIOC3D/ GTETRGC SCK5/

ET0_TX_ QMI-A/

LCD_DAT

A15-A

MTCLKC/

TMCI1/

PO25/

CTS8#/

SS8#/

SS10#/

CTS10#/

RTS10#/

SSLA0-A

CLK/

CAT0_TX_ SDHI_D1-

CLK/ A/

QIO1-A/

POE0#

CATSYNC MMC_D1-A

0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 52 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (10/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

P13

PC2

A18

MTIOC4B/ GTIOC2B RXD5/

ET0_RX_ SDHI_D3- LCD_DAT

TCLKA/

PO21

SMISO5/ DV/

A/

A19-A

SSCL5/

CAT0_RX MMC_CD-A

SSLA3-A _DV

P14

P75

CS5#

PO20

SCK11/

RTS11#

ET0_ERX SDHI_D2- LCD_DAT

D0/ A/ A20-A

RMII0_RX MMC_RES

DSMDAT2

D0/

#-A

CAT0_ER

XD0

P15

R1

VCC

P21

MTIOC1B/ GTIOC2A RXD0/

SDHI_CLK-

C/PIXD5

IRQ9

IRQ8

MTIOC4A/

TIOCA3/

TMCI0/

PO1

SMISO0/

SSCL0/

SCL1/

USB0_EXI

CEN/

SSILRCK0

R2

R3

P20

P16

MTIOC1A/

TIOCB3/

TMRI0/

PO0

TXD0/

SDHI_CMD

-C/PIXD4

SMOSI0/

SSDA0/

SDA1/

USB0_ID/

SSIRXD0

MTIOC3C/

MTIOC3D/

TIOCB1/

TCLKC/

TMO2/

TXD1/

IRQ6

ADTRG0#

SMOSI1/

SSDA1/

RXD3/

SMISO3/

SSCL3/

SCL2-DS/

USB0_VB

USEN/

PO14/

RTCOUT

USB0_VB

US/

USB0_OV

RCURB

R4

P13

WR2#/

BC2#

MTIOC0B/ GTADSM1 TXD2/

LCD_TCO IRQ3

N0-A

ADTRG1#

TIOCA5/

TMO3/

PO13

SMOSI2/

SSDA2/

SDA0[FM+

]

R5

R6

R7

USB0_DM

USB0_DP

CLKOUT2 P56

5M

EDACK1 MTIOC3C/

TIOCA1

SCK7/

RSPCKC-

B

LCD_DAT

A4-A

DSMDAT1

R8

P11

MTIC5V/

TMCI3

SCK2

EPLSOUT

1/

LCD_DAT IRQ1

A7-A

CATSYNC

1

R9

P53*

BCLK

R10

R11

R12

VSS

VCC

P80

EDREQ0 MTIOC3B/

PO26

SCK10/

RTS10#

ET0_TX_E QIO2-A/

LCD_DAT

N/

SDHI_WP/ A14-A

RMII0_TX MMC_D2-A

D_EN/

CAT0_TX_

EN/

CATLATC

H0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 53 of 158

RX72M Group

1. Overview

Table 1.6

List of Pin and Pin Functions (176-Pin LFBGA) (11/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFBGA Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

R13

R14

R15

P76

P74

PC1

CS6#

PO22

SMISO11/ ET0_RX_ QSSL-A/

LCD_DAT

SSCL11/

RXD11

CLK/

REF50CK -A/

SDHI_CMD A18-A

0/

MMC_CMD

CAT0_RX -A

_CLK

A20/CS4# PO19

SS11#/

CTS11#

ET0_ERX

D1/

LCD_DAT

A21-A

DSMCLK2

RMII0_RX

D1/

CAT0_ER

XD1

A17

MTIOC3A/

TCLKD/

PO18

SCK5/

ET0_ERX

LCD_DAT IRQ12

A22-A

SSLA2-A D2/

CAT0_ER

XD2

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 54 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (1/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

1

2

3

4

5

6

AVSS0

AVCC1

AVSS1

P05

SSILRCK1

SSIDATA1

SCK6/

IRQ13

IRQ11

DA1

DA0

P03

P02

P01

TMCI1

TMCI0

CATLEDS

IRQ10

IRQ9

AN120

AN119

SSIBCK1 TER

7

RXD6/

CATLEDE

SMISO6/ RR

SSCL6/

SSIBCK0

8

P00

TMRI0

TXD6/

CATLATC

IRQ8

IRQ4

AN118

SMOSI6/ H1

SSDA6/

AUDIO_CL

K

9

PF5

PJ5

WAIT#

SSILRCK0 CATLATC

H0

10

11

EMLE

VSS

POE8#

CTS2#/

RTS2#/

SS2#/

EPLSOUT

0/

CATSYNC

0

SSIRXD0

12

13

PJ3

EDACK1 MTIOC3C

CTS6#/

RTS6#/

SS6#/

CTS0#/

RTS0#/

SS0#/

ET0_EXO

UT/

CATREST

OUT

SSITXD0

14

15

16

17

18

19

20

21

22

23

24

25

26

27

VCL

VBATT

NC

TRST#

MD/FINED

XCIN

PF4

XCOUT

RES#

XTAL

P37

P36

VSS

EXTAL

VCC

UPSEL

P35

P34

NMI

MTIOC0A/

TMCI3/

SCK6/

SCK0

ET0_LINK

STA/

IRQ4

DSMDAT0

PO12/

POE10#

CAT0_LIN

KSTA

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 55 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (2/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

28

P33

EDREQ1 MTIOC0D/

TIOCD0/

RXD6/

PCKO

IRQ3-DS

DSMCLK0

SMISO6/

SSCL6/

RXD0/

TMRI3/

PO11/

POE4#/

POE11#

SMISO0/

SSCL0/

CRX0

29

P32

MTIOC0C/

TIOCC0/

TMO3/

TXD6/

VSYNC

IRQ2-DS

SMOSI6/

SSDA6/

TXD0/

PO10/

RTCIC2/

RTCOUT/

POE0#/

POE10#

SMOSI0/

SSDA0/

CTX0/

USB0_VB

USEN

30

31

TMS

TDI

PF3

PF2

RXD1/

SMISO1/

SSCL1

CATI2CCL

K

32

33

P31

P30

MTIOC4D/

TMCI2/

PO9/

CTS1#/

RTS1#/

SS1#/

ET1_MDC/

PMGI1_M

DC

IRQ1-DS

IRQ0-DS

RTCIC1

SSLB0-A

MTIOC4B/

TMRI3/

PO8/

RXD1/

SMISO1/ O/

SSCL1/

ET1_MDI

PMGI1_M

RTCIC0/

POE8#

MISOB-A DIO

34

35

TCK

TDO

PF1

PF0

SCK1

TXD1/

CATI2CDA

SMOSI1/ TA

SSDA1

36

37

P27

P26

CS7#

CS6#

MTIOC2B/

TMCI3/

PO7

SCK1/

RSPCKB- /CATIRQ

A

ET1_WOL

MTIOC2A/

TMO1/PO6

TXD1/

SMOSI1/ UT/

ET1_EXO

SSDA1/

CTS3#/

RTS3#/

SS3#/

CATLINKA

CT1

MOSIB-A

38

CLKOUT P25

CS5#/

EDACK1 MTCLKB/

TIOCA4/

MTIOC4C/

RXD3/

SDHI_CD/

HSYNC

ADTRG0#

SMISO3/

SSCL3/

SSIDATA1

PO5

39

40

VCC

P24

CS4#/

EDREQ1 MTCLKA/

TIOCB4/

MTIOC4A/

SCK3/

USB0_VB

USEN/

SDHI_WP/

PIXCLK

TMRI1/

SSIBCK1

PO4

41

42

VSS

P23

EDACK0 MTIOC3D/ GTIOC0A TXD3/

SDHI_D1-

C/PIXD7

MTCLKD/

TIOCD3/

PO3

SMOSI3/

SSDA3/

CTS0#/

RTS0#/

SS0#/

CTX1/

SSIBCK0

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 56 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (3/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

43

P22

EDREQ0 MTIOC3B/ GTIOC1A SCK0/

SDHI_D0-

C/PIXD6

MTCLKC/

TIOCC3/

USB0_OV

RCURB/

AUDIO_CL

K

TMO0/PO2

44

P21

MTIOC1B/ GTIOC2A RXD0/

SDHI_CLK-

C/PIXD5

IRQ9

IRQ8

MTIOC4A/

TIOCA3/

TMCI0/

PO1

SMISO0/

SSCL0/

SCL1/

USB0_EXI

CEN/

SSILRCK0

45

46

P20

P17

MTIOC1A/

TIOCB3/

TMRI0/

PO0

TXD0/

SDHI_CMD

-C/PIXD4

SMOSI0/

SSDA0/

SDA1/

USB0_ID/

SSIRXD0

MTIOC3A/ GTIOC0B SCK1/

EPLSOUT SDHI_D3-

0/ C/PIXD3

SMOSI3/ CATSYNC

SSDA3/

SDA2-DS/

SSITXD0

IRQ7

ADTRG1#

MTIOC3B/

MTIOC4B/

TIOCB0/

TCLKD/

TMO1/

TXD3/

0

PO15/

POE8#

47

48

P87

P16

MTIOC4C/ GTIOC1B SMOSI10/ EPLSOUT SDHI_D2-

TIOCA2

SSDA10/ 1/

C/PIXD2

TXD10

CATSYNC

1

MTIOC3C/

MTIOC3D/

TIOCB1/

TCLKC/

TMO2/

TXD1/

IRQ6

ADTRG0#

SMOSI1/

SSDA1/

RXD3/

SMISO3/

SSCL3/

SCL2-DS/

USB0_VB

USEN/

PO14/

RTCOUT

USB0_VB

US/

USB0_OV

RCURB

49

50

P86

P15

MTIOC4D/ GTIOC2B SMISO10/ CATLINKA PIXD1

TIOCA0

SSCL10/ CT0

RXD10

MTIOC0B/ GTETRGA RXD1/

CATLEDR PIXD0

IRQ5

MTCLKB/

TIOCB2/

TCLKB/

TMCI2/

PO13

SMISO1/ UN

SSCL1/

SCK3/

CRX1-DS/

SSILRCK1

51

P14

MTIOC3A/ GTETRGD CTS1#/

LCD_CLK- IRQ4

A

MTCLKA/

TIOCB5/

TCLKA/

TMRI2/

PO15

RTS1#/

SS1#/

CTX1/

USB0_OV

RCURA

52

53

P13

P12

WR2#/

BC2#

MTIOC0B/ GTADSM1 TXD2/

LCD_TCO IRQ3

N0-A

ADTRG1#

TIOCA5/

TMO3/

PO13

SMOSI2/

SSDA2/

SDA0[FM+

]

WR3#/

BC3#

MTIC5U/

TMCI1

GTADSM0 RXD2/

LCD_TCO IRQ2

N1-A

SMISO2/

SSCL2/

SCL0[FM+

]

54

VCC_USB

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 57 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (4/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

55

56

USB0_DM

USB0_DP

57

58

VSS_USB

CLKOUT2 PJ2

5M

TXD8/

LCD_TCO

N2-A

SMOSI8/

SSDA8/

SSLC3-B

59

60

PJ1

PJ0

MTIOC6A

MTIOC6B

RXD8/

SMISO8/ 1/

SSCL8/

SSLC2-B

EPLSOUT

LCD_TCO

N3-A

CATSYNC

1

SCK8/

SSLC1-B 0/

CATSYNC

EPLSOUT

LCD_DAT

A0-A

0

61

62

P85

P84

MTIOC6C/

TIOCC0

LCD_DAT

A1-A

MTIOC6D

ET1_LINK

STA/

LCD_DAT

A2-A

CAT1_LIN

KSTA

63

P57

RXD7/

LCD_DAT

A3-A

SMISO7/

SSCL7/

SSLC0-B

64

65

CLKOUT2 P56

5M

EDACK1 MTIOC3C/

TIOCA1

SCK7/

RSPCKC-

B

LCD_DAT

A4-A

DSMDAT1

P55

D0[A0/D0]/ MTIOC4D/

EDREQ0/ TMO3

WAIT#

TXD7/

SMOSI7/ UT

SSDA7/

ET0_EXO

LCD_DAT IRQ10

A5-A

MISOC-B/

CRX1

66

P54

D1[A1/D1]/ MTIOC4B/

EDACK0/ TMCI1

ALE

CTS2#/

RTS2#/

SS2#/

ET0_LINK

STA/

CAT0_LIN

LCD_DAT

A6-A

MOSIC-B/ KSTA

CTX1

67

68

P11

P10

MTIC5V/

TMCI3

SCK2

EPLSOUT

1/

CATSYNC

1

LCD_DAT IRQ1

A7-A

ALE

MTIC5W/

TMRI3

IRQ0

1

69

70

P53*

BCLK

RD#

P52

RXD2/

CATLEDS

SMISO2/ TER

SSCL2/

SSLB3-A

71

72

P51

P50

WR1#/

BC1#/

WAIT#

SCK2/

SSLB2-A

WR0#/

WR#

TXD2/

SMOSI2/ RR

SSDA2/

CATLEDE

SSLB1-A

73

74

VSS

P83

EDACK1 MTIOC4C GTIOC0A SCK10/

ET0_CRS/

RMII0_CR

S_DV/

LCD_DAT

A8-A

DSMCLK1

SS10#/

CTS10#

CAT0_RX

_DV

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 58 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (5/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

75

76

VCC

UB

PC7

A23/CS0# MTIOC3A/ GTIOC3A TXD8/

ET0_COL MMC_D7-A LCD_DAT IRQ14

A9-A

MTCLKB/

TMO2/

SMOSI8/

SSDA8/

PO31/

TOC0/

CACREF

SMOSI10/

SSDA10/

TXD10/

MISOA-A

77

PC6

D2[A2/D2]/ MTIOC3C/ GTIOC3B RXD8/

A22/CS1# MTCLKA/

ET0_ETX MMC_D6-A LCD_DAT IRQ13

SMISO8/ D3/

A10-A

TMCI2/

SSCL8/

CAT0_ET

PO30/TIC0

SMISO10/ XD3/

SSCL10/ CATLATC

RXD10/

H1

MOSIA-A

78

79

PC5

P82

D3[A3/D3]/ MTIOC3B/ GTIOC1A SCK8/

ET0_ETX MMC_D5-A LCD_DAT

A21/CS2#/ MTCLKD/

RTS8#/

SCK10/

RSPCKA- XD2

A

D2/

A11-A

WAIT#

TMRI2/

PO29

CAT0_ET

EDREQ1 MTIOC4A/ GTIOC2A SMOSI10/ ET0_ETX MMC_D4-A LCD_DAT

PO28

SSDA10/ D1/

TXD10 RMII0_TX

A12-A

D1/

CAT0_ET

XD1/

CATI2CDA

TA

80

81

82

P81

P80

PC4

EDACK0 MTIOC3D/ GTIOC0B SMISO10/ ET0_ETX QIO3-A/

LCD_DAT

PO27

SSCL10/ D0/

SDHI_CD/ A13-A

RXD10

RMII0_TX MMC_D3-A

D0/

CAT0_ET

XD0/

CATI2CCL

K

EDREQ0 MTIOC3B/

PO26

SCK10/

RTS10#

ET0_TX_E QIO2-A/

LCD_DAT

N/

SDHI_WP/ A14-A

RMII0_TX MMC_D2-A

D_EN/

CAT0_TX_

EN/

CATLATC

H0

A20/CS3# MTIOC3D/ GTETRGC SCK5/

ET0_TX_ QMI-A/

LCD_DAT

A15-A

MTCLKC/

TMCI1/

PO25/

CTS8#/

SS8#/

SS10#/

CTS10#/

RTS10#/

SSLA0-A

CLK/

CAT0_TX_ SDHI_D1-

CLK/ A/

CATSYNC MMC_D1-A

0

QIO1-A/

POE0#

83

84

PC3

P77

A19

MTIOC4D/ GTIOC1B TXD5/

ET0_TX_E QMO-A/

LCD_DAT

A16-A

TCLKB/

PO24

SMOSI5/

SSDA5

R

QIO0-A/

SDHI_D0-

A/

MMC_D0-A

CS7#

PO23

PO22

SMOSI11/ ET0_RX_ QSPCLK-A/ LCD_DAT

SSDA11/ ER/

TXD11

SDHI_CLK- A17-A

RMII0_RX A/

_ER/

CAT0_RX

_ER

MMC_CLK-

A

85

P76

CS6#

SMISO11/ ET0_RX_ QSSL-A/

LCD_DAT

SDHI_CMD A18-A

REF50CK -A/

SSCL11/

RXD11

CLK/

0/

MMC_CMD

CAT0_RX -A

_CLK

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 59 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (6/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

86

PC2

A18

MTIOC4B/ GTIOC2B RXD5/

ET0_RX_ SDHI_D3- LCD_DAT

TCLKA/

PO21

SMISO5/ DV/

A/

A19-A

SSCL5/

CAT0_RX MMC_CD-A

SSLA3-A _DV

87

P75

CS5#

PO20

SCK11/

RTS11#

ET0_ERX SDHI_D2- LCD_DAT

DSMDAT2

D0/

A/

A20-A

RMII0_RX MMC_RES

D0/

#-A

CAT0_ER

XD0

88

89

P74

PC1

PC0

A20/CS4# PO19

SS11#/

CTS11#

ET0_ERX

D1/

RMII0_RX

D1/

CAT0_ER

XD1

LCD_DAT

A21-A

DSMCLK2

A17

A16

MTIOC3A/

TCLKD/

PO18

SCK5/

SSLA2-A D2/

CAT0_ER

ET0_ERX

LCD_DAT IRQ12

A22-A

XD2

90

91

VCC

VSS

MTIOC3C/

TCLKC/

PO17

CTS5#/

RTS5#/

SS5#/

ET0_ERX

D3/

CAT0_ER

IRQ14

SSLA1-A XD3

92

93

P73

PB7

CS3#

A15

PO16

ET0_WOL

LCD_EXT

CLK-A

94

95

96

97

98

MTIOC3B/

TIOCB5/

PO31

TXD9/

SMOSI9/ RMII0_CR

SSDA9/ S_DV/

SMOSI11/ CAT0_RX

SSDA11/ _DV

TXD11

ET0_CRS/

PB6

PB5

PB4

PB3

A14

A13

A12

A11

MTIOC3D/

TIOCA5/

PO30

RXD9/

SMISO9/ D1/

SSCL9/

SMISO11/ D1/

SSCL11/

RXD11

ET0_ETX

RMII0_TX

CAT0_ET

XD1

MTIOC2A/

MTIOC1B/

TIOCB4/

TMRI1/

PO29/

POE4#

SCK9/

RTS9#/

SCK11

ET0_ETX

D0/

RMII0_TX

D0/

CAT0_ET

XD0

LCD_CLK-

B

TIOCA4/

PO28

CTS9#/

SS9#/

SS11#/

CTS11#/

RTS11#

ET0_TX_E

N/

RMII0_TX

D_EN/

CAT0_TX_

EN

LCD_TCO

N0-B

MTIOC0A/

MTIOC4A/

TIOCD3/

TCLKD/

TMO0/

SCK4/

SCK6

ET0_RX_

ER/

RMII0_RX

_ER/

CAT0_RX

_ER

LCD_TCO

N1-B

PO27/

POE11#

99

PB2

A10

TIOCC3/

TCLKC/

PO26

CTS4#/

RTS4#/

SS4#/

CTS6#/

RTS6#/

SS6#

ET0_RX_

CLK/

REF50CK

0/

CAT0_RX

_CLK

LCD_TCO

N2-B

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 60 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (7/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

100

PB1

A9

MTIOC0C/

MTIOC4C/

TIOCB3/

TMCI0/

TXD4/

SMOSI4/ D0/

SSDA4/

TXD6/

ET0_ERX

LCD_TCO IRQ4-DS

N3-B

RMII0_RX

D0/

PO25

SMOSI6/ CAT0_ER

SSDA6

XD0

101

102

P72

P71

A19/CS2#

A18/CS1#

ET0_MDC/

CAT0_MD

C/

PMGI0_M

DC

LCD_DAT

A23-A

DSMDAT3

DSMCLK3

ET0_MDI

O/

CAT0_MDI

O/

PMGI0_M

DIO

103

104

VCC

PB0

A8

MTIC5W/

TIOCA3/

PO24

RXD4/

SMISO4/ D1/

SSCL4/

RXD6/

ET0_ERX

LCD_DAT IRQ12

A0-B

RMII0_RX

D1/

SMISO6/ CAT0_ER

SSCL6 XD1

105

106

VSS

PA7

PA6

A7

A6

TIOCB2/

PO23

MISOA-B ET0_WOL

LCD_DAT

A1-B

107

MTIC5V/

MTCLKB/

TIOCA2/

TMCI3/

GTETRGB CTS5#/

ET0_EXO

UT/

CATREST

LCD_DAT

A2-B

RTS5#/

SS5#/

MOSIA-B OUT

PO22/

POE10#

108

109

PA5

PA4

A5

A4

MTIOC6B/ GTIOC0A RSPCKA- ET0_LINK

LCD_DAT

A3-B

TIOCB1/

PO21

B

STA/

CAT0_LIN

KSTA

MTIC5U/

MTCLKA/

TIOCA1/

TMRI0/

TXD5/

SMOSI5/ CAT0_MD

SSDA5/ C/

SSLA0-B CATIRQ/

PMGI0_M

ET0_MDC/

LCD_DAT IRQ5-DS

A4-B

PO20

DC

110

PA3

A3

MTIOC0D/

MTCLKD/

TIOCD0/

TCLKB/

PO19

RXD5/

SMISO5/ O/

SSCL5 CAT0_MDI

ET0_MDI

LCD_DAT IRQ6-DS

A5-B

O/

PMGI0_M

DIO

111

112

TRDATA3 PG7

PA2

D31

A2

ET1_TX_E

R

MTIOC7A/ GTIOC1A RXD5/

PO18

CATLINKA

SMISO5/ CT1

LCD_DAT

A6-B

SSCL5/

SSLA3-B

113

114

TRDATA2 PG6

D30

ET1_ETX

D3/

CAT1_ET

XD3

PA1

DQM3/A1 MTIOC0B/ GTIOC2A SCK5/

ET0_WOL

LCD_DAT IRQ11

A7-B

MTCLKC/

MTIOC7B/

TIOCB0/

PO17

SSLA2-B

115

VCC

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 61 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (8/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

116

TRCLK

VSS

PG5

D29

ET1_ETX

D2/

CAT1_ET

XD2

117

118

PA0

DQM2/

MTIOC4A/ GTIOC0B SSLA1-B ET0_TX_E

LCD_DAT

A8-B

BC0#/A0 MTIOC6D/

TIOCA0/

N/

RMII0_TX

D_EN/

CAT0_TX_

EN/

PO16/

CACREF

CATLEDR

UN

119

TRSYNC PG4

D28

ET1_ETX

D1/

RMII1_TX

D1/

CAT1_ET

XD1

120

121

P67

DQM1/

CS7#

MTIOC7C GTIOC1B CRX2

EPLSOUT

1/

CATSYNC

1

IRQ15

TRDATA1 PG3

D27

ET1_ETX

D0/

RMII1_TX

D0/

CAT1_ET

XD0

122

123

P66

DQM0/

CS6#

MTIOC7D GTIOC2B CTX2

TRDATA0 PG2

D26

ET1_TX_

CLK/

CAT1_TX_

CLK

124

125

P65

PE7

CKE/CS5#

D15[A15/ MTIOC6A/ GTIOC3A MISOB-B

D15]/

D7[A7/D7]

SDHI_WP/ LCD_DAT IRQ7

MMC_RES A9-B

#-B

AN105

AN104

TOC1

126

PE6

D14[A14/ MTIOC6C/ GTIOC3B MOSIB-B

D14]/

SDHI_CD/ LCD_DAT IRQ6

MMC_CD-B A10-B

TIC1

D6[A6/D6]

127

128

VCC

P70

SDCLK

CATLINKA

CT0

129

130

VSS

PE5

D13[A13/ MTIOC4C/ GTIOC0A RSPCKB- ET0_RX_

LCD_DAT IRQ5

A11-B

AN103

D13]/

MTIOC2B

B

CLK/

D5[A5/D5]

REF50CK

0/

CAT0_RX

_CLK

131

132

PE4

PE3

D12[A12/ MTIOC4D/ GTIOC1A SSLB0-B ET0_ERX

LCD_DAT

A12-B

AN102

AN101

D12]/

MTIOC1A/

D2/

D4[A4/D4] PO28

CAT0_ER

XD2

D11[A11/ MTIOC4B/ GTIOC2A CTS12#/

ET0_ERX MMC_D7-B LCD_DAT

D11]/

D3[A3/D3] TOC3/

POE8#

PO26/

RTS12#/

SS12#

D3/

CAT0_ER

XD3

A13-B

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 62 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (9/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

133

PE2

D10[A10/ MTIOC4A/ GTIOC0B RXD12/

MMC_D6-B LCD_DAT IRQ7-DS AN100

A14-B

D10]/

PO23/TIC3

SMISO12/

SSCL12/

RXDX12/

SSLB3-B

D2[A2/D2]

134

PE1

D9[A9/D9]/ MTIOC4C/ GTIOC1B TXD12/

MMC_D5-B LCD_DAT

A15-B

ANEX1

ANEX0

D1[A1/D1] MTIOC3B/

PO18

SMOSI12/

SSDA12/

TXDX12/

SIOX12/

SSLB2-B

135

136

PE0

P64

D8[A8/D8]/ MTIOC3D GTIOC2B SCK12/

MMC_D4-B LCD_DAT

A16-B

D0[A0/D0]

SSLB1-B

WE#/

D3[A3/D3]/

CS4#

ET1_ETX

D0/

RMII1_TX

D0/

CAT1_ET

XD0

137

138

139

P63

P62

P61

CAS#/

D2[A2/D2]/

CS3#

ET1_ETX

D1/

RMII1_TX

D1/

CAT1_ET

XD1

RAS#/

D1[A1/D1]/

CS2#

ET1_ERX

D0/

RMII1_RX

D0/

CAT1_ER

XD0

SDCS#/

D0[A0/D0]/

CS1#

ET1_ERX

D1/

RMII1_RX

D1/

CAT1_ER

XD1

140

141

VSS

P60

CS0#

ET1_TX_E

N/

RMII1_TX

D_EN/

CAT1_TX_

EN

142

143

VCC

PD7

D7[A7/D7] MTIC5U/

POE0#

SSLC3-A ET1_RX_ QMI-B/

ER/ QIO1-B/

RMII1_RX SDHI_D1-

_ER/ B/

LCD_DAT IRQ7

A17-B

AN107

CAT1_RX MMC_D1-B

_ER

144

145

TRDATA7 PG1

D25

ET1_RX_

ER/

RMII1_RX

_ER/

CAT1_RX

_ER

PD6

D6[A6/D6] MTIC5V/

MTIOC8A/

SSLC2-A ET1_RX_ QMO-B/

LCD_DAT IRQ6

A18-B

AN106

CLK/

REF50CK SDHI_D0-

1/ B/

QIO0-B/

POE4#

CAT1_RX MMC_D0-B

_CLK

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 63 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (10/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

146

TRDATA6 PG0

D24

ET1_RX_

CLK/

REF50CK

1/

CAT1_RX

_CLK

147

148

PD5

PD4

D5[A5/D5] MTIC5W/

MTIOC8C/

SSLC1-A ET1_MDC/ QSPCLK-B/ LCD_DAT IRQ5

PMGI1_M SDHI_CLK- A19-B

AN113

AN112

MTCLKA/

POE10#

DC

B/

MMC_CLK-

B

D4[A4/D4] MTIOC8B/

POE11#

SSLC0-A ET1_MDI QSSL-B/

LCD_DAT IRQ4

O/

SDHI_CMD A20-B

PMGI1_M -B/

DIO

MMC_CMD

-B

149

150

TRSYNC1 P97

D23/A23

ET1_ERX

D3/

CAT1_ER

XD3

PD3

D3[A3/D3] MTIOC8D/ GTIOC0A RSPCKC- ET1_WOL QIO3-B/

LCD_DAT IRQ3

AN111

TOC2/

A

SDHI_D3- A21-B

POE8#

B/

MMC_D3-B

151

152

VSS

TRDATA5 P96

D22/A22

ET1_ERX

D2/

CAT1_ER

XD2

153

154

VCC

PD2

D2[A2/D2] MTIOC4D/ GTIOC0B MISOC-A/ ET1_EXO QIO2-B/

LCD_DAT IRQ2

AN110

TIC2

CRX0

UT

SDHI_D2- A22-B

B/

MMC_D2-B

155

TRDATA4 P95

D21/A21

ET1_ERX

D1/

RMII1_RX

D1/

CAT1_ER

XD1

156

157

PD1

P94

D1[A1/D1] MTIOC4B/ GTIOC1A MOSIC-A/

LCD_DAT IRQ1

A23-B

AN109

POE0#

CTX0

D20/A20

ET1_ERX

D0/

RMII1_RX

D0/

CAT1_ER

XD0

158

159

PD0

P93

D0[A0/D0] POE4#

D19/A19 POE0#

GTIOC1B

LCD_EXT IRQ0

CLK-B

AN108

AN117

CTS7#/

RTS7#/

SS7#

ET1_LINK

STA/

CAT1_LIN

KSTA

DSMDAT4

DSMCLK4

160

P92

D18/A18 POE4#

RXD7/

SMISO7/ RMII1_CR

SSCL7

ET1_CRS/

AN116

AN115

S_DV/

CAT1_RX

_DV

161

162

P91

D17/A17

SCK7

ET1_COL

DSMDAT5

VSS

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 64 of 158

RX72M Group

1. Overview

Table 1.7

List of Pin and Pin Functions (176-Pin LFQFP) (11/11)

Number

Memory I/F

Camera I/F

Timer

Communication

Power

Supply

(MTU,

(SCI,

TPU, TMR,

PPG, RTC,

RSPI,

(QSPI,

Clock

Bus

RIIC, CAN, (ETHERC, SDHI,

USB,

SSIE)

176-Pin System

LFQFP Control

EXDMAC CMTW,

I/O Port SDRAMC POE, CAC) POEG)

(GPTW,

ESC,

MMCIF,

PDC)

A/D

PGMI)

GLCDC

Interrupt D/A

DSMIF

163

P90

D16/A16

TXD7/

ET1_RX_

AN114

DSMCLK5

SMOSI7/ DV/

SSDA7 CAT1_RX

_DV

164

165

166

167

168

169

170

171

172

173

174

175

176

VCC

P47

P46

P45

P44

P43

P42

P41

IRQ15-DS AN007

IRQ14-DS AN006

IRQ13-DS AN005

IRQ12-DS AN004

IRQ11-DS AN003

IRQ10-DS AN002

IRQ9-DS AN001

VREFL0

P40

IRQ8-DS AN000

VREFH0

AVCC0

P07

IRQ15

ADTRG0#

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

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RX72M Group

2. Electrical Characteristics

2.

Electrical Characteristics

2.1

Absolute Maximum Ratings

Table 2.1

Absolute Maximum Rating

Conditions: VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V

Item

Symbol

Value

Unit

Power supply voltage

VCC, VCC_USB

–0.3 to +4.0

V

V_BATTpower supply voltage

V_BATT

Input voltage (except for ports for 5 V tolerant*¹)

Input voltage (ports for 5 V tolerant*¹)

Reference power supply voltage

Analog power supply voltage

V_in

–0.3 to VCC + 0.3 (up to 4.0)

–0.3 to VCC + 4.0 (up to 5.8)

–0.3 to AVCC0 + 0.3 (up to 4.0)

–0.3 to +4.0

V

V_in

V

VREFH0

V

AVCC0, AVCC1*²

V

Analog input voltage

V_AN

T_j

–0.3 to AVCC + 0.3 (up to 4.0)

–40 to +105

V

Junction temperature

D version

G version

°C

T_j

–40 to +125

Storage temperature

T_stg

–55 to +125

Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.

Note 1. Ports 07, 11 to 17, 20, 21, 30 to 33, 67, and C0 to C3 are 5 V tolerant.

Note 2. Connect the AVCC0, AVCC1, and VCC_USB pins to VCC, and the AVSS0, AVSS1, and VSS_USB pins to VSS.

When the A/D converter unit 0 is not to be used, connect the VREFH0 pin to VCC and the VREFL0 pin to VSS, respectively.

Do not leave these pins open. Insert capacitors of high frequency characteristics between the AVCC0 and AVSS0 pins, or

AVCC1 and AVSS1 pins. Place capacitors of about 0.1 μF as close as possible to every power supply pin and use the shortest

and heaviest possible traces.

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RX72M Group

2. Electrical Characteristics

2.2

Recommended Operating Conditions

Table 2.2

Recommended Operating Conditions (1)

Item Symbol

Min.

2.7

—

Typ.

—

Max.

Unit

V

Power supply voltage*¹

VCC

VSS

3.6

0

—

V

_BATTpower supply voltage

V_BATT

2.0

—

3.6

V

USB power supply voltage

VCC_USB

VSS_USB

AVCC0

AVSS0

AVCC1

AVSS1

VREFH0

VREFL0

V_in

VCC

0

—

V

—

V

Analog power supply voltage*^1,

*

—

VCC

0

—

V

2

—

V

—

VCC

0

V

—

V

2.7

—

AVCC0

—

V

0

V

Input voltage (except for 5 V tolerant ports,

except for ports 03, 05 and 40 to 47)*³

–0.3

—

VCC + 0.3

V

Input voltage (ports 03, 05 and 40 to 47)

V_in

–0.3

—

AVCC + 0.3

V

Input voltage (5V tolerant ports 11 to 17, ports 20 and

21, ports 30 to 33, port 67, and ports C0 to C3)*⁴

VCC + 3.6 (up to 5.5)

Input voltage (5V tolerant port 07)

Operating temperature (D version)

Operating temperature (G version)

V_in

T_opr

–0.3

–40

—

AVCC + 3.6 (up to 5.5)

V

85

°C

105

Note 1. Comply with the following potential condition: VCC = AVCC0 = AVCC1 = VCC_USB

Note 2. For details, refer to section 58.6.11, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.

Note 3. Ports 07, 11 to 17, 20, 21, 30 to 33, 67, and C0 to C3 are 5 V tolerant.

Note 4. For P32, P31, and P30, input as follows when the V_BATTpower supply is selected.

V_inMin. = –0.3, Max. = V_BATT+ 0.3 (V_BATT= 2.0 to 3.6 V)

Table 2.3

Recommended Operating Conditions (2)

Item

Symbol

C_VCL

Value

Decoupling capacitance to stabilize the internal voltage

0.22 μF ± 30%*¹

Note 1. Use a multilayer ceramic capacitor whose nominal capacitance is 0.22 μF and a capacitance tolerance is ±30% or better.

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2. Electrical Characteristics

2.3

DC Characteristics

Table 2.4

DC Characteristics (1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

V

Schmitt trigger

input voltage

IRQ input pin*¹,

V_IH

V_IL

VCC × 0.8

—

VCC × 0.2

—

MTU input pin*¹,

POE input pin*¹,

TPU input pin*¹,

TMR input pin*¹,

CMTW input pin*¹,

SCI input pin*¹,

ΔV_T

VCC × 0.06

CAN input pin*¹,

CAC input pin*¹,

ADTRG# input pin*¹,

QSPI input pin*¹,

SSIE input pin*¹,

DSMIF input pin*¹,

GPTW input pin*¹,

POEG input pin*¹,

ESC input pin (except for MII

pin)*¹,

RES#, NMI, TCK

RIIC input pin

(except for SMBus)

V_IH

V_IL

VCC × 0.7

—

VCC × 0.3

ΔV_T

V_IH

V_IL

VCC × 0.05

VCC × 0.8

—

Ports for 5 V tolerant*²

—

VCC × 0.2

Other input pins excluding ports

for 5 V tolerant*³

V_IH

V_IL

VCC × 0.8

—

VCC × 0.2

—

Input high voltage MD pin, EMLE

(except for Schmitt

V_IH

VCC × 0.9

VCC × 0.8

V

EXTAL, RSPI input pin,

—

trigger input pin)

EXDMAC input pin, WAIT#,

SDHI input pin, MMC input pin,

PDC input pin, PMGI input pin

ETHERC input pin,

2.3

—

ESC input pin (MII pin)

D0 to D31

VCC × 0.7

—

RIIC (SMBus)

MD pin, EMLE

2.1

—

Input low voltage

(except for Schmitt

trigger input pin)

V_IL

VCC × 0.1

VCC × 0.2

V

EXTAL, RSPI input pin,

—

ETHERC input pin,

EXDMAC input pin, WAIT#,

SDHI input pin, MMC input pin,

PDC input pin, PMGI input pin,

ESC input pin (MII pin)

D0 to D31

—

VCC × 0.3

0.8

RIIC (SMBus)

Note 1. This does not include the pins, which are multiplexed as ports for 5 V tolerant.

Note 2. Ports 07, 11 to 17, 20, 21, 30 to 33, 67, and C0 to C3 are 5 V tolerant.

Note 3. For P32, P31, and P30, input as follows when the V_BATTpower supply is selected.

V_IHMin. = V_BATT× 0.8, V_ILMax. = V_BATT× 0.2 (V_BATT= 2.0 to 3.6 V)

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2. Electrical Characteristics

Table 2.5

DC Characteristics (2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

V_OH

Min.

VCC – 0.5

—

Typ.

—

Max.

—

Unit

V

Test Conditions

I_OH= –1 mA

Output high voltage

Output low voltage

All output pins

V_OL

—

0.5

V

I_OL= 1.0 mA

(except for RIIC pins and

ETHERC output pin)

RIIC output pin

—

0.4

0.6

0.4

I_OL= 3.0 mA

I_OL= 6.0 mA

RIIC output pin

(only P12 and P13 in channel 0)

V_OL

V

I_OL= 15.0 mA

(ICFER.FMPE = 1)

—

0.4

—

I_OL= 20.0 mA

(ICFER.FMPE = 1)

ETHERC output pin

V_OL

| I_in

—

0.4

1.0

I_OL= 1.0 mA

Input leakage current RES#, MD pin, EMLE*¹,

BSCANP*¹, NMI

|

μA V_in= 0 V

_in= VCC

V

Three-state leakage Other than ports for 5 V tolerant

current (off state)

| I_TSI

|

—

1.0

5.0

–10

300

8

μA V_in= 0 V

_in= VCC

V

Ports for 5 V tolerant

V_in= 0 V

_in= 5.5 V

V

Input pull-up resistor Other than P35

current

I_p

–300

10

μA VCC = 2.7 to 3.6 V

_in= 0 V

V

Input pull-down

resistor current

EMLE, BSCANP

μA V_in= VCC

Input capacitance

All input pins

C_in

—

pF Vbias = 0 V

Vamp = 20 mV

f = 1 MHz

(except for ports 03, 05, 12, 13,

16, 17, 20, 21, EMLE, BSCANP,

USB0_DP, and USB0_DM)

T_a= 25°C

Ports 03, 05, 12, 13, 16, 17, 20,

21, EMLE, BSCANP, USB0_DP,

and USB0_DM

—

16

—

Output voltage of the VCL pin

V_CL

1.18

V

Note 1. The input leakage current value at the EMLE and BSCANP pins are only when V_in= 0 V.

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RX72M Group

2. Electrical Characteristics

Table 2.6

DC Characteristics (3)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

D version

G version

Item

Symbol

Unit

Test Conditions

Typ. Max. Typ. Max.

3

Supply

current

*

Full operation*²

I_CC

*

—

261

—

319

—

mA ICLK = 240 MHz,

PCLKA = 120 MHz,

PCLKB = 60 MHz,

PCLKC = 60 MHz,

PCLKD = 60 MHz,

FCLK = 60 MHz,

Normal

operation

Peripheral module clocks are supplied

*

61

1

4

Peripheral module clocks are stopped

30

37

42

—

30

37

42

—

4,

5

*

Core

Mark

Peripheral module clocks are stopped

BCLK = 120 MHz,

BCLK pin = 60 MHz

4,

5

*

Sleep mode: Peripheral module clocks are

supplied*⁴

144

196

All module clock stop mode (reference value)

Increased by BGO Reading from the code flash

14

6

115

—

14

6

167

—

operation*⁸

memory while the data flash

memory is being programmed

Reading from the code flash

memory while the code flash

memory is being programmed

7

—

7

—

Increased by Trusted Secure IP operation

—

15

—

15

—

Low-speed operating mode 1: Peripheral module clocks

are stopped*⁴

4.2

All clocks 1 MHz

Low-speed operating mode 2: Peripheral module clocks

are stopped*⁴

4.2

—

4.2

—

All clocks 32.768

kHz

Software standby mode

3.95 107 3.95 155

Power is supplied to the standby RAM and USB

resume detecting unit (USB0 only)

15.5

70

15.5

98

μA

Power is not

Low power consumption

11.5

42

11.5

58

supplied to the

function of the power-on reset

standby RAM and circuit is disabled*⁶

USB resume

detecting unit

(USB0 only)

Low power consumption

function of the power-on reset

circuit is enabled*⁷

4.9

32

4.9

47

When a low C_Lcrystal is in

use

1

—

1

—

Increase current

by operating RTC

When a standard C_Lcrystal is

in use

2

When the RTC is

When a low C_Lcrystal is in

0.9

1.6

1.7

3.3

—

0.9

1.6

1.7

3.3

—

V_BATT= 2.0 V,

VCC = 0 V

operating while VCC is use

not supplied (Only the

RTC and sub-clock

oscillator operate with

the battery backup

function)

—

V_BATT= 3.3 V,

VCC = 0 V

When a standard C_Lcrystal is

in use

—

V_BATT= 2.0 V,

VCC = 0 V

—

V_BATT= 3.3 V,

VCC = 0 V

Inrush current*⁹

I_RUSH

211

mA

Inrush current on

returning from deep

software standby mode

Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.

Note 2. Peripheral module clocks are supplied.

Note 3. I_CCdepends on the f (ICLK) as follows.

(when ICLK : PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 4 : 2 : 1 : 2 : 1 and EXTAL = 12 MHz)

 D version

I_CCmax. = 0.77 × f + 74 (full operation in high-speed operating mode)

I_CCtyp. = 0.22 × f + 7 (normal operation in high-speed operating mode)

I_CCtyp. = 0.50 × f + 3.7 (ICLK 1 MHz max) (low-speed operating mode 1)

I_CCmax. = 0.29 × f + 74 (sleep mode)

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2. Electrical Characteristics

 G version

_CCmax. = 0.89 × f + 105 (full operation in high-speed operating mode)

I

I_CCtyp. = 0.22 × f + 7 (normal operation in high-speed operating mode)

I_CCtyp. = 0.50 × f + 3.7 (ICLK 1 MHz max) (low-speed operating mode 1)

I

_CCmax. = 0.37 × f + 105 (sleep mode)

Note 4. Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control

registers A to D.

Note 5. When the peripheral module clock is stopped, the settings of the clock frequency are as follows:

ICLK = 240 MHz and PCLKA = PCLKB = PCLKC = PCLKD = FCLK = BCLK = BCLK pin = 3.75 MHz (divided by 64).

Note 6. When the low power consumption function is disabled, the DEEPCUT[1:0] bits are set to 01b.

Note 7. When the low power consumption function is enabled, the DEEPCUT[1:0] bits are set to 11b.

Note 8. These are the increases during programming of the code flash memory after the code flash memory (limitations apply to the

combinations of address ranges of the program area and the readable area) or the data flash memory has been programmed or

erased.

Note 9. Reference value

Table 2.7

DC Characteristics (4)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

D version

G version

Item

Symbol

AI_CC

Unit

Test Conditions

Min. Typ. Max. Min. Typ. Max.

Analog

power

During 12-bit A/D conversion (unit 0)

—

0.8

1.7

1

—

0.8

1.7

1

mA IAVCC0_AD

During 12-bit A/D conversion (unit 0)

with channel-dedicated sample-and-

hold circuits (3 channels)

2.5

mA IAVCC0_AD + SH

supply

current*^1,

3

*

During 12-bit A/D conversion (unit 1)

—

0.6

0.7

1

—

0.6

0.7

1

mA IAVCC1_AD

During 12-bit A/D conversion (unit 1)

+ temperature sensor

1.1

mA IAVCC1_AD +

TEMP

During D/A

conversion

(2 channels)

Unbuffered output

Buffered output

—

0.25

0.75

0.4

1.1

—

0.25

0.75

0.4

1.1

mA IAVCC1_DA

mA

Waiting for A/D, D/A, and

temperature sensor conversion

(all units)

—

0.9

1.4

—

0.9

1.4

mA IAVCC0 +

IAVCC1

A/D, D/A, and temperature sensor

are in standby mode (all units)

—

1.4

6.7

—

1.4

9.0

μA IAVCC0 +

IAVCC1

Reference During 12-bit A/D conversion (unit 0) AI_REFH

—

38

60

—

38

60

μA IVREFH0

power

Waiting for 12-bit A/D conversion

0.07

0.5

0.07

0.6

supply

(unit 0)

current

12-bit A/D converter in module stop

—

0.07

0.4

—

0.07

0.5

μA IVREFH0

mode (unit 0)

USB

operating

current

Low speed

Full speed

USB0

I_CCUSBLS

I_CCUSBFS

—

3.7

4.2

6.5

10

—

3.7

4.2

6.5

10

mA VCC_USB

RAM retension voltage

VCC rising gradient

VCC falling gradient*²

V_RAM

SrVCC

SfVCC

2.7

8.4

—

2.7

—

V

20000 8.4

8.4

20000 μs/V

μs/V

—

Note 1. The reference power supply current is included in the power supply current value for 12-bit A/D converter (unit 1) and D/A

converter.

Note 2. This applies when V_BATTis used.

Note 3. Supply current values are measured when all output pins are unloaded.

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2. Electrical Characteristics

Table 2.8

Permissible Output Currents

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

I_OL

Min.

—

Typ.

—

Max.

2.0

Unit

mA

Permissible output low current

(average value per pin)

All output pins*¹

All output pins*²

All output pins*³

Normal drive

High drive

I_OL

—

3.8

High-speed interface

high-drive

I_OL

—

7.5

Permissible output low current

(max. value per pin)

All output pins*¹

All output pins*²

All output pins*³

Normal drive

High drive

I_OL

—

4.0

7.6

15

mA

High-speed interface

high-drive

Permissible output low current (total)

Total of all output pins

All output pins*¹

All output pins*²

All output pins*³

ΣI_OL

I_OH

—

80

mA

Permissible output high current

(average value per pin)

Normal drive

High drive

–2.0

–3.8

–7.5

High-speed interface

high-drive

Permissible output high current

(max. value per pin)

All output pins*¹

All output pins*²

All output pins*³

Normal drive

High drive

I_OH

—

–4.0

–7.6

–15

mA

High-speed interface

high-drive

Permissible output high current (total) Total of all output pins

ΣI_OH

—

–80

mA

Caution: To protect the MCU’s reliability, the output current values should not exceed the values in this table.

Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable.

Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to

which high driving ability is fixed.

Note 3. This is the value when high-speed interface high-driving ability is set with a pin for which high-speed interface high-driving ability

is selectable.

Table 2.9

Thermal Resistance Value (Reference)

Item

Thermal resistance

Package

Symbol

Max.

31.5

Unit

°C/W JESD51-2 and

JESD51-7 compliant

Test Conditions

176-pin LFQFP (PLQP0176KB-C)

_ja

224-pin LFBGA (PLBG0224GA-A)

176-pin LFBGA (PLBG0176GA-A)

176-pin LFQFP (PLQP0176KB-C)

23.1

30.5

0.4

JESD51-2 and

JESD51-9 compliant

_jt

°C/W JESD51-2 and

JESD51-7 compliant

224-pin LFBGA (PLBG0224GA-A)

176-pin LFBGA (PLBG0176GA-A)

0.2

0.3

JESD51-2 and

JESD51-9 compliant

Note:

The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of

the board. For details, refer to the JEDEC standards.

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RX72M Group

2. Electrical Characteristics

2.4

AC Characteristics

Table 2.10

Operating Frequency (High-Speed Operating Mode)

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f

Min.

—

Typ.

—

Max.

240

120

60

Unit

Operating

frequency

System clock (ICLK)

MHz

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)

Peripheral module clock (PCLKD)

Flash-IF clock (FCLK)

—

60

—

60

—*¹

—

60

External bus clock (BCLK)

BCLK pin output

120

80

—

SDRAM clock (SDCLK)

—

80

SDCLK pin output

—

80

Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the flash memory contents.

Table 2.11

Operating Frequency (Low-Speed Operating Mode 1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f

Min.

—

Typ.

—

Max.

Unit

Operating

frequency

System clock (ICLK)

1

MHz

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)*¹

Peripheral module clock (PCLKD)*¹

Flash-IF clock (FCLK)

External bus clock (BCLK)

BCLK pin output

SDRAM clock (SDCLK)

SDCLK pin output

Note 1. When the 12-bit A/D converter is used, the frequency must be set to at least 1 MHz.

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RX72M Group

2. Electrical Characteristics

Table 2.12

Operating Frequency (Low-Speed Operating Mode 2)

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f

Min.

32

—

Typ.

—

Max.

264

Unit

kHz

Operating

frequency

System clock (ICLK)

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)*¹

Peripheral module clock (PCLKD)*¹

Flash-IF clock (FCLK)

—

32

—

External bus clock (BCLK)

BCLK pin output

—

SDRAM clock (SDCLK)

—

SDCLK pin output

—

Note 1. The 12-bit A/D converter cannot be used.

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2.4.1

2. Electrical Characteristics

Reset Timing

Table 2.13

Reset Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

Figure 2.1

Figure 2.2

RES# pulse

width

Power-on

t_RESWP

t_RESWD

t_RESWS

1

—

ms

Deep software standby mode

0.6

0.3

Software standby mode, low-speed operating

mode 2

Programming or erasure of the code flash

memory, or programming, erasure or blank

checking of the data flash memory

t_RESWF

200

—

μs

Other than above

t_RESW

t_RESWT

t_RESW2

200

54

—

55

μs

Waiting time after release from the RES# pin reset

t_Lcyc

Figure 2.1

Internal reset time

100

108

(independent watchdog timer reset, watchdog timer reset,

software reset)

VCC

RES#

t_RESWP

Internal reset signal

(Low is valid)

t_RESWT

Figure 2.1

Reset Input Timing at Power-On

t_RESWD, t_RESWS, t_RESWF, t_RESW

RES#

Internal reset signal

(Low is valid)

t_RESWT

Figure 2.2

Reset Input Timing

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2.4.2

2. Electrical Characteristics

Clock Timing

Table 2.14

BCLK Pin Output, SDCLK Pin Output Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

BCLK pin output cycle time

t_Bcyc

t_CH

t_CL

t_Cr

12.5

3.25

—

3

ns

Figure 2.3

BCLK pin output high pulse width

BCLK pin output low pulse width

BCLK pin output rising time

BCLK pin output falling time

t_Cf

—

3

SDCLK pin output cycle time

SDCLK pin output high pulse width

SDCLK pin output low pulse width

SDCLK pin output rising time

SDCLK pin output falling time

t_Bcyc

t_CH

t_CL

t_Cr

12.5

3.25

—

3

t_Cf

—

3

t_Bcyc, t_SDcyc

t_CH

t_Cf

BCLK pin output, SDCLK pin output

t_Cr

t_CL

Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, C = 30 pF

Figure 2.3

BCLK Pin and SDCLK Pin Output Timing

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2. Electrical Characteristics

Table 2.15

EXTAL Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

f_EXMAIN≤ 24 MHz

f_EXMAIN> 24 MHz

Test

Conditions

Item

Symbol

Unit

Min.

Typ.

—

Max.

Min.

33.33

—

Typ.

—

Max.

—

30

—

5

EXTAL external clock input cycle time

EXTAL external clock input frequency

EXTAL external clock input high pulse width

EXTAL external clock input low pulse width

EXTAL external clock rising time

t_EXcyc

f_EXMAIN

t_EXH

41.66

—

24

—

5

ns

MHz

ns

Figure 2.4

—

15.83

—

13.33

—

t_EXL

—

ns

t_EXr

—

ns

EXTAL external clock falling time

t_EXf

—

5

—

5

ns

t_EXcyc

t_EXH

t_EXL

EXTAL external clock input

VCC × 0.5

t_EXr

t_EXf

Figure 2.4

Table 2.16

EXTAL External Clock Input Timing

Main Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Main clock oscillation frequency

f_MAIN

8

—

24

MHz

ms

Main clock oscillator stabilization time (crystal)

Main clock oscillation stabilization wait time (crystal)

t_MAINOSC

t_MAINOSCWT

—

—*¹

—*²

Figure 2.5

ms

Note 1. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation

provided by the manufacturer for the oscillation stabilization time.

Note 2. The number of cycles selected by the value of the MOSCWTCR.MSTS[7:0] bits determines the main clock oscillation

stabilization wait time in accord with the formula below.

t_MAINOSCWT= [(MSTS[7:0] bits × 32) + 10] / f_LOCO

MOSCCR.MOSTP

t_MAINOSC

Main clock oscillator output

t_MAINOSCWT

OSCOVFSR.MOOVF

Main clock

Figure 2.5

Main Clock Oscillation Start Timing

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2. Electrical Characteristics

Table 2.17

LOCO and IWDT-Dedicated Low-Speed Clock Timing

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

Figure 2.6

Figure 2.7

LOCO clock cycle time

t_Lcyc

f_LOCO

t_LOCOWT

t_ILcyc

f_ILOCO

t_ILOCOWT

4.63

216

—

4.16

240

—

3.78

264

44

μs

kHz

μs

LOCO clock oscillation frequency

LOCO clock oscillation stabilization wait time

IWDT-dedicated low-speed clock cycle time

IWDT-dedicated low-speed clock oscillation frequency

9.26

108

—

8.33

120

142

7.57

132

190

μs

kHz

μs

IWDT-dedicated low-speed clock oscillation stabilization wait

time

LOCOCR.LCSTP

On-chip oscillator output

t_LOCOWT

LOCO clock

Figure 2.6

LOCO Clock Oscillation Start Timing

ILOCOCR.ILCSTP

IWDT-dedicated on-chip

oscillator output

t_ILOCOWT

OSCOVFSR.ILCOVF

IWDT-dedicated

low-speed clock

Figure 2.7

IWDT-dedicated Low-Speed Clock Oscillation Start Timing

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2. Electrical Characteristics

Table 2.18

HOCO Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

f_HOCO

Min.

15.61

17.56

19.52

15.52

17.46

19.4

—

Typ.

16

Max.

16.39

18.44

20.48

16.48

18.54

20.6

Unit

Test Conditions

HOCO clock oscillation frequency

MHz

μs

–20°C ≤ T_a≤ 105°C

18

20

16

–40°C ≤ T_a< –20°C

18

20

HOCO clock oscillation stabilization wait time

HOCO clock power supply stabilization time

t_HOCOWT

t_HOCOP

105

—

149

Figure 2.8

Figure 2.9

—

150

μs

HOCOCR.HCSTP

High-speed on-chip

oscillator output

t_HOCOWT

OSCOVFSR.HCOVF

HOCO clock

Figure 2.8

HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the HOCOCR.HCSTP Bit)

HOCOPCR.HOCOPCNT

HOCOCR.HCSTP

t_HOCOP

Internal power supply for

high-speed on-chip oscillator

Figure 2.9

High-Speed On-Chip Oscillator Power Supply Control Timing

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2. Electrical Characteristics

Table 2.19

PLL/PPLL Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

PLL/PPLL clock oscillation frequency

f_PLL

120

—

240

320

MHz

μs

PLL/PPLL clock oscillation stabilization wait time

t_PLLWT

259

Figure 2.10

PLLCR2.PLLEN

PPLLCR2.PPLLEN

PLL/PPLL circuit output

t_PLLWT

OSCOVFSR.PLOVF

OSCOVFSR.PPLOVF

PLL/PPLL clock

Figure 2.10

Table 2.20

PLL/PPLL Clock Oscillation Start Timing

Sub-Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

V

= 2.0 to 3.6 V, T = T

BATT

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

—

Unit

Sub-clock oscillation frequency

f_SUB

—

32.768

—

kHz

s

1

Sub-clock oscillation stabilization time

Sub-clock oscillation stabilization wait time

t_SUBOSC

t_SUBOSCWT

*

Figure 2.11

2

—

*

s

Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation

provided by the manufacturer for the oscillation stabilization time.

Note 2. The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization

wait time in accord with the formula below.

t_SUBOSCWT= [(SSTS[7:0] bits × 16384) + 10] / f_LOCO

SOSCCR.SOSTP

t_SUBOSC

Sub-clock oscillator output

t_SUBOSCWT

OSCOVFSR.SOOVF

Sub-clock

Figure 2.11

Sub-Clock Oscillation Start Timing

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2. Electrical Characteristics

Table 2.21

CLKOUT Pin Output Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

V

= 2.0 to 3.6 V, T = T

,

BATT

a

opr

High-drive output is selected by the driving ability control register

Test

Conditions

Item

CLKOUT pin output cycle time

Symbol

Min.

Typ.

Max.

Unit

t_Ccyc

t_CH

t_CL

t_Cr

25

5

—

5

ns

Figure 2.12

_Ccyc= 25 ns

t

CLKOUT pin output high pulse width*¹

CLKOUT pin output low pulse width*¹

CLKOUT pin output rising time

5

—

CLKOUT pin output falling time

t_Cf

5

Note 1. If the main clock oscillator is selected by the CLKOUT output source select bit (CKOCR.CKOSEL[2:0]) and the external clock

input is selected by the main clock oscillator switching bit (MOFCR.MOSEL), the pulse width depends on the input clock wave

form.

t_Ccyc

t_CH

t_Cf

CLKOUT pin output

t_Cr

t_CL

Test Conditions VOH = VCC × 0.7, VOL = VCC × 0.3, C = 30pF

Figure 2.12

Table 2.22

CLKOUT Pin Output Timing

CLKOUT25M Pin Output Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

V

= 2.0 to 3.6 V, T = T

,

BATT

a

opr

High-speed interface high-drive is selected by the driving ability control register

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

CLKOUT25M pin output cycle time

CLKOUT25M pin output high pulse width

CLKOUT25M pin output low pulse width

CLKOUT25M pin output rising time

CLKOUT25M pin output falling time

t_Ccyc

t_CH

t_CL

t_Cr

—

13

—

40

—

3

ns

Figure 2.13

t_Cf

3

t_Ccyc

t_CH

t_Cf

CLKOUT25M pin output

t_Cr

t_CL

Test Conditions VOH = VCC × 0.7, VOL = VCC × 0.3, C = 30pF

CLKOUT25M Pin Output Timing

Figure 2.13

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2.4.3

2. Electrical Characteristics

Timing of Recovery from Low Power Consumption Modes

Table 2.23

Timing of Recovery from Low Power Consumption Modes (1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Max.

Test

Unit

Item

Symbol Min. Typ.

Conditions

2

3

t_SBYOSCWT

{(MSTS[7:0] bit × 32) 100 + 7 / f_ICLK

+ 76} / 0.216 2n / f_MAIN

*

t_SBYSEQ*

Recovery time Crystal

from software resonator

standby mode connected to

Main clock

oscillator

operating

t_SBYMC

—

+

μs Figure 2.14

1

*

main clock

oscillator

Main clock

oscillator and

PLL circuit

operating

t_SBYPC

{(MSTS[7:0] bit × 32) 100 + 7 / f_ICLK

+ 138} / 0.216

2n / f_PLL

External clock Main clock

input to main oscillator

clock oscillator operating

t_SBYEX

352

639

100 + 7 / f_ICLK

2n / f_EXMAIN

+

Main clock

oscillator and

PLL circuit

operating

t_SBYPE

100 + 7 / f_ICLK

2n / f_PLL

Sub-clock oscillator operating

t_SBYSC

{(SSTS[7:0] bit ×

16384) + 13} / 0.216

+ 10 / f_FCLK

100 + 4 / f_ICLK

2n / f_SUE

+

High-speed

on-chip

High-speed

on-chip

t_SBYHO

454

100 + 7 / f_ICLK

2n / f_HOCO

oscillator

operating

oscillator

operating

High-speed

on-chip

t_SBYPH

741

100 + 7 / f_ICLK

2n / f_PLL

+

oscillator

operatingand

PLL circuit

operating

Low-speed on-chip oscillator

operating*⁴

t_SBYLO

338

100 + 7 / f_ICLK

2n / f_LOCO

+

Note 1. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization

waiting time (t_SBYOSCWT) and the time required for operations by the software standby release sequencer (t_SBYSEQ).

Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization

waiting time t_SBYOSCWTis selected.

Note 3. For n, the greatest value is selected from among the internal clock division settings.

Note 4. This condition applies when f_ICLK:f_FCLK= 1:1, 2:1, or 4:1.

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2. Electrical Characteristics

Oscillator

(System clock)

t_SBYOSCWT

t_SBYSEQ

Oscillator

(Other than the system clock)

ICLK

IRQ

Software standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of the system clock oscillator is slower

Oscillator

(System clock)

t_SBYSEQ

t_SBYOSCWT

Oscillator

(Other than the system clock)

t_SBYOSCWT

ICLK

IRQ

Software standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of an oscillator other than the system clock is slower

Figure 2.14

Software Standby Mode Recovery Timing

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2. Electrical Characteristics

Table 2.24

Timing of Recovery from Low Power Consumption Modes (2)

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Recovery time from deep software standby mode

t_DSBY

—

0.9

24

ms

Figure 2.15

Wait time after recovery from deep software standby mode

t_DSBYWT

23

t_Lcyc

Oscillator

IRQ

Deep software standby reset

(Low is valid)

Internal reset

(Low is valid)

Deep software standby mode

t_DSBY

t_DSBYWT

Reset exception handling start

Figure 2.15

Deep Software Standby Mode Recovery Timing

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2.4.4

2. Electrical Characteristics

Control Signal Timing

Table 2.25

Control Signal Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

t_NMIW

Min.*¹

200

Typ.

—

Max.

—

Unit

ns

Test Conditions*¹

NMI pulse width

t_PBcyc× 2 ≤ 200 ns, Figure 2.16

t_PBcyc× 2 > 200 ns, Figure 2.16

t_PBcyc× 2 ≤ 200 ns, Figure 2.17

t_PBcyc× 2 > 200 ns, Figure 2.17

t_PBcyc× 2

200

—

ns

IRQ pulse width

t_IRQW

—

ns

t

_PBcyc× 2

—

ns

Note 1. t_PBcyc: PCLKB cycle

NMI

t_NMIW

Figure 2.16

NMI Interrupt Input Timing

IRQn

t_IRQW

Figure 2.17

IRQ Interrupt Input Timing

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2.4.5

2. Electrical Characteristics

Bus Timing

Table 2.26

Bus Timing

Conditions 1: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Conditions 2: VCC = AVCC0 = AVCC1 = VCC_USB = V = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, 60 MHz < BCLK = SDCLK ≤ 80 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5,

OH

OL

C = 15 pF for the SDCLK pin, C = 30 pF for other pins.

To control the drive capacity when using the SDRAM: set the PFBCR3.SDCLKDRV bit in external bus control

register 1 to 1 to select the drive capacity of the SDCLK pin,

and set the SDRAM pins other than the SDCLK pin as high-

speed-interface driving outputs.

Conditions 1

Conditions 2

Item

Symbol

Unit

Test Conditions

Min.

Max.

12.5

—

Min.

Max.

12.5

—

Address delay time

t_AD

t_BCD

—

12.5

0

—

12.5

0

ns

Figure 2.18 to

Figure 2.23

Byte control delay time

CS# delay time

t_CSD

ALE delay time

t_ALED

t_RSD

RD# delay time

Read data setup time

t_RDS

Read data hold time

t_RDH

—

WR# delay time

t_WRD

t_WDD

t_WDH

t_WTS

t_WTH

t_AD2

—

0

12.5

—

0

12.5

—

Write data delay time

Write data hold time

WAIT# setup time

12.5

0

—

12.5

0

—

Figure 2.24

Figure 2.25

WAIT# hold time

—

Address delay time 2 (SDRAM)

CS# delay time 2 (SDRAM)

DQM delay time (SDRAM)

CKE delay time (SDRAM)

Read data setup time 2 (SDRAM)

Read data hold time 2 (SDRAM)

Write data delay time 2 (SDRAM)

Write data hold time 2 (SDRAM)

WE# delay time (SDRAM)

RAS# delay time (SDRAM)

CAS# delay time (SDRAM)

1

12.5

—

1

10.0

—

t_CSD2

t_DQMD

t_CKED

t_RDS2

t_RDH2

t_WDD2

t_WDH2

t_WED

t_RASD

t_CASD

1

10

0

6.0

0

—

1

12.5

—

1

10.0

—

1

12.5

1

10.0

1

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2. Electrical Characteristics

Data cycle

T_end

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_n1

T_n2

T_W5

BCLK

t_AD

Address bus

t_RDSt_RDH

t_AD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_RSD

Data read

(RD#)

t_CSD

Chip select

(CS1#)

Figure 2.18

Address/Data Multiplexed Bus Read Access Timing

Data cycle

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_end

T_n1

T_n2

t_WDH

t_WRD

T_n3

T_W5

BCLK

t_AD

Address bus

t_AD

t_WDD

t_AD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_WRD

Data write

(WRm#)

t_CSD

Chip select

(CS1#)

Figure 2.19

Address/Data Multiplexed Bus Write Access Timing

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2. Electrical Characteristics

CSRWAIT:2

RDON:1

CSON:0

CSROFF:2

T_W1

T_W2

T_end

T_n1

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

A23 to A1

1-write strobe mode

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_RSD

RD# (Read)

t_RDS

t_RDH

D31 to D0 (Read)

Figure 2.20

External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)

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2. Electrical Characteristics

CSWWAIT:2

WRON:1

WDON:1 ^*1

CSWOFF:2

WDOFF:1 ^*1

T_n1

CSON:0

T_W1

T_W2

T_end

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

A23 to A1

1-write strobe mode

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_WRD

WR1# to WR0#, WR# (Write)

t_WDD

t_WDH

D31 to D0 (Write)

Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.

Figure 2.21

External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)

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2. Electrical Characteristics

CSRWAIT:2

RDON:1

CSON:0

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSROFF:2

T_W1

T_W2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_n1

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

A23 to A1

1-write strobe mode

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_RSD

RD# (Read)

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

D31 to D0 (Read)

Figure 2.22

External Bus Timing/Page Read Cycle (Bus Clock Synchronized)

CSPWWAIT:2

CSWOFF:2

CSWWAIT:2

WRON:1

WDON:1 ^*1

CSON:0

WRON:1

WDOFF:1 ^*1

T_dw1

WDOFF:1 ^*1

T_n1

WDOFF:1 ^*1

T_dw1

WDON:1^*1

T_pw1

WDON:1 ^*1

T_pw1

T_W2

T_end

T_pw2

T_W1

T_end

T_n2

BCLK

Byte strobe mode

t_AD

A23 to A0

A23 to A1

1-write strobe mode

t_AD

t_BCD

BC3# to BC0#

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7# to CS0#

t_WRD

WR1# to WR0#, WR# (Write)

D31 to D0 (Write)

t_WDD

t_WDH

Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.

Figure 2.23

External Bus Timing/Page Write Cycle (Bus Clock Synchronized)

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2. Electrical Characteristics

CSRWAIT:3

CSWWAIT:3

T_W1

T_W2

T_W3

(T_end

)

T_end

T_n1

T_n2

BCLK

A23 to A0

CS7# to CS0#

RD# (Read)

WR# (Write)

External wait

t_WTSt_WTHt_WTSt_WTH

WAIT#

Figure 2.24

External Bus Timing/External Wait Control

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2. Electrical Characteristics

SDRAM command

ACT

RD

PRA

SDCLK pin

t_AD2

Row

address

A18 to A0

AP*¹

Column address

t_AD2

PRA

command

t_CSD2

t_CSD2t_CSD2

SDCS#

RAS#

CAS#

t_RASD

t_CASD

t_WED

WE#

CKE

(High)

t_DQMD

DQMn

t_RDS2t_RDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 2.25

SDRAM Space Single Read Bus Timing

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2. Electrical Characteristics

SDRAM command

ACT

WR

PRA

SDCLK pin

t_AD2

Row

address

A18 to A0

AP*¹

Column address

t_AD2

PRA

command

t_CSD2

SDCS#

RAS#

CAS#

t_RASD

t_CASD

t_WED

WE#

CKE

(High)

t_DQMD

DQMn

t_WDD2

t_WDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 2.26

SDRAM Space Single Write Bus Timing

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2. Electrical Characteristics

ACT

RD RD RD RD PRA

SDCLK pin

t_AD2

t_AD2t_AD2

t_AD2t_AD2t_AD2t_AD2

t_AD2

Row

address

C0

(column address)

C1

C2

C3

A18 to A0

AP*¹

t_AD2t_AD2

t_AD2

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2

SDCS#

t_RASDt_RASD

t_RASD

RAS#

CAS#

WE#

t_CASD

t_WED

(High)

CKE

t_DQMD

DQMn

t_RDS2t_RDH2

t_RDS2

t_RDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 2.27

SDRAM Space Multiple Read Bus Timing

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2. Electrical Characteristics

ACT

WR WR WR PRA

WR

SDCLK pin

t_AD2t_AD2t_AD2

t_AD2t_AD2

C0

Row

address

C1

C2

C3

A18 to A0

AP*¹

(column address)

t_AD2

t_AD2t_AD2

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2t_CSD2

SDCS#

t_RASDt_RASD

t_RASDt_RASDt_RASD

RAS#

CAS#

t_CASD

t_WED

WE#

CKE

(High)

t_DQMD

DQMn

t_WDD2t_WDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 2.28

SDRAM Space Multiple Write Bus Timing

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2. Electrical Characteristics

ACT

RD

PRA

ACT

RD

PRA

SDRAM command

SDCLK pin

A18 to A0

AP*¹

t_AD2

t_AD2t_AD2t_AD2

t_AD2t_AD2t_AD2t_AD2

t_AD2t_AD2t_AD2t_AD2t_AD2

Row

address

C0

(column address 0)

C1

C2

C3

R1

C4

C5

C6

C7

t_AD2

t_AD2t_AD2

t_AD2

PRA

command

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2t_CSD2t_CSD2t_CSD2

t_CSD2

SDCS#

RAS#

CAS#

WE#

t_RASDt_RASD

t_RASDt_RASDt_RASDt_RASD

t_RASDt_RASD

t_CASD

t _WEDt _WED

(High)

CKE

t_DQMD

DQMn

t_RDS2t_RDH2

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 2.29

SDRAM Space Multiple Read Line Stride Bus Timing

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2. Electrical Characteristics

MRS

SDRAM command

SDCLK pin

t_AD2

A18 to A0

AP*¹

t_AD2

t_CSD2

SDCS#

RAS#

t_RASD

t_CASD

CAS#

t _WED

WE#

CKE

(High)

DQMn

(Hi-Z)

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 2.30

SDRAM Space Mode Register Set Bus Timing

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2. Electrical Characteristics

SDRAM command

SDCLK pin

Ts (RFA)

(RFS)

(RFX)

(RFA)

t_AD2

A18 to A0

AP*¹

t_AD2

t_CSD2t_CSD2

t_CSD2

t_RASD

t_CASD

t_CSD2

t_RASD

t_CASD

t_CSD2t_CSD2t_CSD2

t_RASDt_RASDt_RASD

t_CASDt_CASDt_CASD

SDCS#

RAS#

CAS#

WE#

t_RASDt_RASD

t_CASDt_CASD

(High)

t_CKED

CKE

t_DQMD

DQMn

(Hi-Z)

D31 to D0

Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.

Figure 2.31

SDRAM Space Self-Refresh Bus Timing

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2.4.6

2. Electrical Characteristics

EXDMAC Timing

Table 2.27

EXDMAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, BCLK = SDCLK = 8 to 80 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.

Max.

Unit

EXDMAC

EDREQ setup time

EDREQ hold time

EDACK delay time

t_EDRQS

t_EDRQH

t_EDACD

13

2

—

13

ns

Figure 2.32

—

Figure 2.33,

Figure 2.34

BCLK pin

t_EDRQSt_EDRQH

EDREQ0,

EDREQ1

Figure 2.32

EDREQ0 and EDREQ1 Input Timing

BCLK pin

t_EDACD

EDACK0,

EDACK1

Figure 2.33

EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)

BCLK pin

t_EDACD

EDACK0,

EDACK1

Figure 2.34

EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)

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2.4.7

2. Electrical Characteristics

Timing of On-Chip Peripheral Modules

Table 2.28

I/O Port Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_PRW

Min.

1.5

Max.

—

Conditions

I/O ports

Input data pulse width

t_PBcyc

Figure 2.35

Note 1. t_PBcyc: PCLKB cycle

PCLKB

Port

t_PRW

Figure 2.35

I/O Port Input Timing

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2. Electrical Characteristics

Table 2.29

TPU Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_TICW

Min.

Max.

Conditions

TPU

Input capture input pulse

width

Single-edge setting

Both-edge setting

Single-edge setting

Both-edge setting

Phase counting mode

1.5

2.5

1.5

2.5

—

t_PBcyc

Figure 2.36

Timer clock pulse width

t_TCKWH,

t_TCKWL

t_PBcyc

Figure 2.37

Note 1. t_PBcyc: PCLKB cycle

PCLKB

Input capture

input

t_TICW

Figure 2.36

TPU Input Capture Input Timing

PCLKB

TCLKA to

TCLKD

t_TCKWL

t_TCKWH

Figure 2.37

TPU Clock Input Timing

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2. Electrical Characteristics

Table 2.30

TMR Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

Min.

Max.

Conditions

TMR

Timer clock pulse width

Single-edge setting

Both-edge setting

t_TMCWH,

t_TMCWL

1.5

2.5

—

t_PBcyc

Figure 2.38

Note 1. t_PBcyc: PCLKB cycle

PCLKB

TMCI0 to TMCI3

t_TMCWL

t_TMCWH

Figure 2.38

Table 2.31

TMR Clock Input Timing

CMTW Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.

Max.

Unit*¹

t_PBcyc

CMTW

Input capture input pulse

width

Single-edge setting

Both-edge setting

t_CMTWTICW

1.5

2.5

—

Figure 2.39

Note 1. t_PBcyc: PCLKB cycle

PCLKB

Input capture

input

t_CMTWICW

Figure 2.39

CMTW Input Capture Input Timing

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2. Electrical Characteristics

Table 2.32

MTU Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_MTICW

Min.

Max.

Conditions

MTU

Input capture input pulse

width

Single-edge setting

Both-edge setting

Single-edge setting

Both-edge setting

Phase counting mode

1.5

2.5

1.5

2.5

—

t_PAcyc

Figure 2.40

Timer clock pulse width

t_MTCKWH,

t_MTCKWL

t_PAcyc

Figure 2.41

Note 1. t_PAcyc: PCLKA cycle

PCLKA

Input capture

input

t_MTICW

Figure 2.40

MTU Input Capture Input Timing

PCLKA

MTCLKA to

MTCLKD

t_MTCKWL

t_MTCKWH

Figure 2.41

MTU Clock Input Timing

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2. Electrical Characteristics

Table 2.33

POE and POEG Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Item

Symbol Min. Typ.

Max.

—

Unit*¹

Test Conditions

POE

POEn# input pulse width

(n = 0, 4, 8, 10, 11)

t_POEW

t_POEDI

1.5

—

t_PBcycFigure 2.42

Output

Transition of the POEn#

5 PCLKB + 0.24

µs

Figure 2.43

disable time signal level

When detecting falling edges

(ICSRm.POEnM[3:0] = 0000

(m = 1 to 5; n = 0, 4, 8, 10, 11))

Simultaneous conduction

of output pins

t_POEDO

t_POEDS

—

3 PCLKB + 0.2

1 PCLKB + 0.2

µs

Figure 2.44

Register setting

Figure 2.45

Time for access to the register

is not included.

Oscillation stop detection

t_POEDOS

t_POEGW

t_POEGDI

—

1.5

—

21

—

µs

Figure 2.46

POEG GTETRGn input pulse width (n = A to D)

Output Input level detection of the

t_PBcycFigure 2.47

3 PCLKB + 0.34

µs

Figure 2.48

disable time GTETRGn pin (via flag)

When the digital noise filter is

not in use (POEGGn.NFEN = 0

(n = A to D))

Detection of the output

stopping signal from

GPTW (deadtime error,

simultaneous high output,

or simultaneous low

output)

t_POEGDE

—

0.5

µs

Figure 2.49

Register setting

t_POEGDS

—

1 PCLKB + 0.3

21

µs

Figure 2.50

Time for access to the register

is not included.

Oscillation stop detection t_POEGDOS

Note 1. t_PBcyc: PCLKB cycle

Figure 2.51

PCLKB

POEn# input

(n = 0, 4, 8, 10, 11)

t_POEW

Figure 2.42

POE Input Timing

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POEn# input

(n = 0, 4, 8, 10, 11)

t_POEW

Outputs disabled

MTU PWM output pins

t_POEDI

Figure 2.43

Output Disable Time for POE in Response to Transition of the POEn# Signal Level

Simultaneous active-level outputs detected*¹

Outputs

MTU PWM output pins

disabled

t_POEDO

Note 1. When the active level is set to low.

Figure 2.44

Output Disable Time for POE in Response to the Simultaneous Conduction of Output Pins

Corresponding bit in

the SPOER register

Outputs disabled

MTU PWM output pins

t_POEDS

Figure 2.45

Output Disable Time for POE in Response to the Register Setting

Main clock

Oscillation stop detection

signal (internal signal)

Outputs disabled

MTU PWM output pins

t_POEDOS

Figure 2.46

Output Disable Time for POE in Response to the Oscillation Stop Detection

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2. Electrical Characteristics

PCLKB

GTETRGn input

(n = A to D)

t_POEGW

Figure 2.47

POEG Input Timing

GTETRGn input

(n = A to D)

t_POEGW

POEGGn.PIDF flag

(n = A to D)

Outputs disabled

GPTW PWM output pins

t_POEGDI

Figure 2.48

Output Disable Time for POEG via Detection Flag in Response to the Input Level Detection of the

GTETRGn pin

Output stopping signal

from GPTW*¹

Outputs disabled

GPTW PWM output pins

t_POEGDE

Note 1. GPTWn.GTST.DTEF (dead time error flag), GPTWn.GTST.OABLF (simultaneous low output flag),

or GPTWn.GTST.OABHF (simultaneous high output flag)

Figure 2.49

Output Disable Time for POEG in Response to Detection of the Output Stopping Signal from

GPTW

POEGGn.SSF bit

(n = A to D)

Outputs disabled

GPTW PWM output pins

t_POEGDS

Figure 2.50

Output Disable Time for POEG in Response to the Register Setting

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2. Electrical Characteristics

Main clock or PLL clock

GPTW PWM output pin

Output disabled

t_POEGOS

Figure 2.51

Output Disable Time of POEG in Response to the Oscillation Stop Detection

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2. Electrical Characteristics

Table 2.34

GPTW Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

2

Item

Symbol

t_GTICW

Min.

Max.

Unit*^1,

*

GPTW

Input capture input pulse width

Single-edge setting

Both-edge setting

1.5

2.5

1.5

2.5

—

t_PAcyc

Figure 2.52

External trigger input pulse width Single-edge setting

Both-edge setting

t_GTEW

t_PBcyc

Figure 2.53

Note 1. t_PAcyc: PCLKA cycle

Note 2. _PBcyc: PCLKB cycle

t

PCLKA

Input capture

input

t_GTICW

Figure 2.52

GPTW Input Capture Input Timing

PCLKB

GTETRGn input

(n = A to D)

t_GTEW

Figure 2.53

GPTW External Trigger Input Timing

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2. Electrical Characteristics

Table 2.35

A/D Converter Trigger Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_TRGW

Min.

1.5

Max.

—

Conditions

A/D

converter

A/D converter trigger input pulse width

t_PBcyc

Figure 2.54

Note 1. t_PBcyc: PCLKB cycle

PCLKB

ADTRG0#,

ADTRG1#

t_TRGW

Figure 2.54

Table 2.36

A/D Converter Trigger Input Timing

CAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

2

Item*^1,

*

Symbol

t_CACREF

Min.*^1,

*

Max.

—

Unit

ns

CAC

CACREF input pulse width

t

_PBcyc≤ t_cac

_PBcyc> t_cac

4.5 t_cac

+

3 t_PBcyc

5 t_cac

6.5 t_PBcyc

t

+

—

Note 1. t_PBcyc: PCLKB cycle

Note 2. t_cac: CAC count clock source cycle

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2. Electrical Characteristics

Table 2.37

SCI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit^*1

Item

SCIh, SCIj Input clock cycle

Symbol

t_Scyc

Min.

Max.

Conditions

Asynchronous

4

6

—

t_PBcycFigure 2.55

Clock

synchronous

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t_SCKW

t_SCKr

t_SCKf

t_Scyc

0.4

—

8

0.6

5

t_Scyc

ns

5

ns

Asynchronous^*2

—

t_PBcyc

Clock

4

synchronous

Output clock pulse width

Output clock rise time

Output clock fall time

Transmit data delay time

t_SCKW

t_SCKr

t_SCKf

t_TXD

0.4

—

0.6

5

t_Scyc

ns

5

ns

Clock

synchronous

28

ns

Figure 2.56

Receive data setup time

Receive data hold time

Input clock cycle

Clock

synchronous

t_RXS

t_RXH

t_Scyc

15

5

—

Clock

synchronous

SCIi

Asynchronous

4

—

t_PAcycFigure 2.55

Clock

12

synchronous

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t_SCKW

t_SCKr

t_SCKf

t_Scyc

0.4

—

8

0.6

5

t_Scyc

ns

5

ns

Asynchronous^*2

—

t_PAcyc

Clock

8

synchronous

Output clock pulse width

Output clock rise time

Output clock fall time

Transmit data delay time

t_SCKW

t_SCKr

t_SCKf

t_TXD

0.4

—

20

0.6

5

t_Scyc

ns

5

ns

Master

Slave

15

28

—

ns

Figure 2.56

Receive data setup time

Receive data hold time

Clock

synchronous

t_RXS

t_RXH

ns

Clock

5

—

synchronous

Note 1. t_PBcyc: PCLKB cycle; t_PAcyc: PCLKA cycle

Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1

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2. Electrical Characteristics

t_SCKW

t_SCKr

t_SCKf

SCKn

(n = 0 to 12)

t_Scyc

Figure 2.55

SCK Clock Input Timing

SCKn

t_TXD

TxDn

t_RXSt_RXH

RxDn

(n = 0 to 12)

Figure 2.56

SCI Input/Output Timing: Clock Synchronous Mode

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2. Electrical Characteristics

Table 2.38

Expansion Serial Sound Interface Timing

= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF

,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit

Item

Symbol

Min.

Max.

Conditions

AUDIO_CLK

SSIBCKn

Cycle

t_EXcyc

t_EXL/t_EXH

t_O

20

0.4

80

—

0.6

—

ns

t_EXcyc

ns

t_O

Figure 2.57

High/low level

Cycle

Master

Slave

Figure 2.58

t_I

80

—

Output clock high level

Output clock low level

Input clock high level

Input clock low level

Output clock rise time

Output clock fall time

Input clock rise time

Input clock fall time

Master

t_HC

0.35

—

t_LC

—

t_O

Slave

Master

Slave

t_HC

—

t_I

t_LC

—

t_I

t_RC

0.15

—

t_O

t_FC

—

t_O

t_RC

—

t_I

t_FC

—

t_I

SSILRCKn,SSITXD0, Input setup time

SSIRXD0, SSIDATA1

Master

Slave

t_SR

12

ns

Figure 2.59,

Figure 2.60

12

—

Input hold time

Master

Slave

t_HR

8

—

15

—

Output delay time

Master

Slave

t_DTR

–10

0

5

20

Output delay time from when an Slave

SSILRCK0 signal is changed*¹

t_DTRW

—

20

Figure 2.61

n = 0, 1

Note 1. The SSIE has a single path for transmission in slave mode. To generate the data for transmission, the signals input through the

SSILRCKn pin through the abovementioned path are used. After that, the data for transmission proceed to be used as the

logical outputs to the SSITXD0 or SSIDATA1 pin.

t_EXcyc

t_EXH

t_EXL

AUDIO_CLK

(input)

1/2 VCC

t_EXf

t_EXr

Figure 2.57

Clock Input Timing

t_HC

t_RC

t_FC

t_LC

SSIBCKn

(n = 0, 1)

t_I,t_O

Figure 2.58

SSIE Clock Input/Output Timing

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2. Electrical Characteristics

SSIBCKn

(input or output)

SSILRCKn (input),

SSIRXD0, SSIDATA1 (input)

t_SR

t_HR

SSILRCKn (output),

SSITXD0, SSIDATA1 (output)

(n = 0, 1)

t_DTR

Figure 2.59

Figure 2.60

Figure 2.61

Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 0

SSIBCKn

(input or output)

SSILRCKn (input),

SSIRXD0, SSIDATA1 (input)

t_SR

t_HR

SSILRCKn (output),

SSITXD0, SSIDATA1 (output)

(n = 0, 1)

t_DTR

Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 1

SSILRCKn (input)

SSITXD0, SSIDATA1 (output)

t_DTRW

(n = 0, 1)

MSB bit output timing in slave transmission from SSILRCKn with the settings

of DEL = 1, SDTA = 0, or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0]

Output Delay of the SSIE Data from When an SSILRCKn Signal is Changed

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2. Electrical Characteristics

Table 2.39

RSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Item

Symbol

t_SPcyc

Min.*¹

Max.*¹

Unit*¹

Conditions*²

RSPI RSPCK clock cycle

Master

Slave

2

4

—

t_PAcycFigure 2.62

RSPCK clock high pulse

width

Master

t_SPCKWH

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2 – 3

ns

Slave

Master

Slave

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2

—

RSPCK clock low pulse

width

t_SPCKWL

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2 – 3

ns

(t_SPcyc– t_SPCKr

– t_SPCKf) / 2

RSPCK clock rise/fall time Output

Input

t_SPCKr,

t_SPCKf

—

6

5

ns

μs

1

Data input setup time

Master

Slave

t_SU

—

ns

Figure 2.63 to

Figure 2.68

8.3

0

Data input hold time

Master PCLKA divi-

sion ratio set to

1/2

t_HF

ns

PCLKA divi-

sion ratio set to

a value other

than 1/2

t_H

t_PAcyc

—

Slave

8.3

—

8

SSL setup time

Master

Slave

t_LEAD

t_LAG

t_OD

1

t_SPcyc

t_PAcyc

t_SPcyc

t_PAcyc

ns

6

—

8

SSL hold time

Master

Slave

1

6

—

6.3

28

—

Data output delay time

Data output hold time

Master

Slave

—

Master

Slave

t_OH

0

ns

0

Successive transmission

delay time

Master

t_TD

t_SPcyc+ 2 × t_PAcyc

8 × t_SPcyc

+ 2 × t_PAcyc

Slave

Output

Input

6 × t_PAcyc

—

5

MOSI and MISO

rise/fall time

t_Dr,t_Df

—

ns

μs

ns

μs

ns

1

SSL

rise/fall time

Output

Input

t_SSLr,

5

tSSLf

1

Slave access time

t_SA

2 × t_PAcyc

+ 28

Figure 2.67,

Figure 2.68

Slave output release time

t_REL

—

2 × t_PAcyc

+ 28

ns

Note 1. t_PAcyc: PCLKA cycle

Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.

For the RSPI interface, the AC portion of the electrical characteristics is measured for each group.

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2. Electrical Characteristics

Table 2.40

Simple SPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_SPcyc

Min.

Max.

Conditions

Simple

SPI

SCK clock cycle output (master)

SCK clock cycle input (slave)

SCK clock high pulse width

SCK clock low pulse width

SCK clock rise/fall time

Data input setup time

Data input hold time

4

8

65536

0.6

20

t_PAcyc

Figure 2.62

t_SPCKWH

t_SPCKWL

t_SPCKr,t_SPCKf

t_SU

0.4

—

t_SPcyc

ns

33.3

1

—

ns

Figure 2.63 to

Figure 2.68

t_H

—

ns

SS input setup time

t_LEAD

—

t_SPcyc

ns

SS input hold time

t_LAG

1

—

Data output delay time

Data output hold time

Data rise/fall time

t_OD

—

33.3

—

t_OH

–10

—

ns

t

_Dr,t_Df

_SSLr,t_SSLf

t_SA

16.6

5

ns

SS input rise/fall time

Slave access time

t

—

ns

—

t_PBcyc

Figure 2.67,

Figure 2.68

Slave output release time

t_REL

—

5

Note 1. t_PAcyc: PCLKA cycle, t_PBcyc: PCLKB cycle

t_SPCKr

t_SPCKf

t_SPCKWH

Simple SPI

RSPI

RSPCKA

master select

output

V_OH

V_OL

V_OH

SCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

SCKn

slave select input

RSPCKA

slave select input

V_IL

t_SPCKWL

V_IL

t_SPcyc

(n = 0 to 12)

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Figure 2.62

RSPI Clock Timing and Simple SPI Clock Timing

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2. Electrical Characteristics

Simple SPI

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

SCKn

CKPOL = 0

output

RSPCKA

CPOL = 1

output

SCKn

CKPOL = 1

output

t_SU

t_H

MISOA

input

SMISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIA

output

SMOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 12)

Figure 2.63

RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other Than 1/2)

and Simple SPI Timing (Master, CKPH = 1)

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

RSPCKA

CPOL = 1

output

t_SU

t_HF

MISOA

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIA

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Figure 2.64

RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to 1/2)

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2. Electrical Characteristics

Simple SPI

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

SCKn

CKPOL = 1

output

RSPCKA

CPOL = 1

output

SCKn

CKPOL = 0

output

t_SU

t_H

MISOA

input

SMISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIA

output

SMOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 12)

Figure 2.65

RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to a Value Other Than 1/2)

and Simple SPI Timing (Master, CKPH = 0)

RSPI

t_TD

SSLA0 to

SSLA3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKA

CPOL = 0

output

RSPCKA

CPOL = 1

output

t_SU

t_HF

t_H

MISOA

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIA

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Figure 2.66

RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2)

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2. Electrical Characteristics

Simple SPI

RSPI

t_TD

SSLA0

input

SSn#

input

t_LEAD

t_LAG

RSPCKA

CPOL = 0

input

SCKn

CKPOL = 0

input

RSPCKA

CPOL = 1

input

SCKn

CKPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOA

output

SMISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

Invaild DATA

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIA

input

SMOSIn

input

MSB IN

DATA

(n = 0 to 12)

Figure 2.67

RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)

Simple SPI

RSPI

t_TD

SSLA0

input

SSn#

input

t_LEAD

t_LAG

RSPCKA

CPOL = 0

input

SCKn

CKPOL = 1

input

RSPCKA

CPOL = 1

input

SCKn

CKPOL = 0

input

t_SA

t_OH

t_OD

t_REL

MISOA

output

SMISOn

output

Invaild DATA

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIA

input

SMOSIn

input

MSB IN

DATA

LSB IN

(n = 0 to 12)

Figure 2.68

RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)

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2. Electrical Characteristics

Table 2.41

QSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

Min.

Max.

Conditions*²

QSPI

QSPCLK clock cycle

Data input setup time

Data input hold time

SS setup time

t_QScyc

t_Su

2

6.5

5

4080

—

t_PBcyc

ns

Figure 2.69

Figure 2.70,

Figure 2.71

t_IH

—

ns

t_LEAD

t_LAG

t_OD

1.5

1

8.5

8

t_QScyc

ns

SS hold time

Data output delay time

Data output hold time

Successive transmission delay time

—

–5

1

10.0

—

t_OH

ns

t_TD

8

t_QScyc

Note 1. t_PBcyc: PCLKB cycle

Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.

For the QSPI interface, the AC portion of the electrical characteristics is measured for each group.

QSPCLK

output

t_QScyc

Figure 2.69

QSPI Clock Timing

t_TD

QSSL

output

t_LEAD

t_LAG

QSPCLK

CPOL = 0

output

QSPCLK

CPOL = 1

output

t_SU

t_IH

QMI,

QIO0 to QIO3

input

MSB IN

DATA

LSB IN

t_OH

t_OD

QMO,

QIO0 to QIO3

output

MSB OUT

DATA

LSB OUT

IDLE

Figure 2.70

Transmit/Receive Timing (CPHA = 0)

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2. Electrical Characteristics

t_TD

QSSL

output

t_LEAD

t_LAG

QSPCLK

CPOL = 0

output

QSPCLK

CPOL = 1

output

t_SUt_IH

MSB IN

QMI,

QIO0 to QIO3

input

DATA

LSB IN

t_OH

t_OD

QMO,

QIO0 to QIO3

output

MSB OUT

DATA

LSB OUT

IDLE

Figure 2.71

Transmit/Receive Timing (CPHA = 1)

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2. Electrical Characteristics

Table 2.42

RIIC Timing (1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

High-drive output is selected by the driving ability control register.

Test

Conditions

2

Item

Symbol

Min.*^1,

*

Max.

Unit

RIIC

(Standard-mode,

SMBus)

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6(12) × t_IICcyc+ 1300

—

ns Figure 2.72

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

SCL, SDA input spike pulse removal time

SDA input bus free time

3(6) × t_IICcyc+ 300

—

ns

pF

ns

3(6) × t_IICcyc+ 300

—

ICFER.FMPE = 0

—

1000

t_Sf

—

300

t_SP

0

3(6) × t_IICcyc+ 300

t_IICcyc+ 300

1000

1(4) × t_IICcyc

t_BUF

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

—

Start condition input hold time

Restart condition input setup time

Stop condition input setup time

Data input setup time

—

1000

—

t_IICcyc+ 50

0

—

Data input hold time

—

SCL, SDA capacitive load

SCL input cycle time

—

400

—

RIIC

(Fast-mode)

ICFER.FMPE = 0

t_SCL

t_SCLH

t_SCLL

t_Sr

6(12) × t_IICcyc+ 600

3(6) × t_IICcyc+ 300

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

—

20 × (External pull-up

voltage/5.5V)

300

SCL, SDA input fall time

t_Sf

20 × (External pull-up

voltage/5.5V)

300

ns

SCL, SDA input spike pulse removal time

SDA input bus free time

t_SP

0

1(4) × t_IICcyc

ns

pF

t_BUF

3(6) × t_IICcyc+ 300

—

Start condition input hold time

Restart condition input setup time

Stop condition input setup time

Data input setup time

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

t_IICcyc+ 300

300

—

300

—

t_IICcyc+ 50

—

Data input hold time

0

—

SCL, SDA capacitive load

—

400

Note:

t_IICcyc: RIIC internal reference clock (IICφ) cycle

Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by

the setting ICFER.NFE = 1.

Note 2. Cb is the total capacitance of the bus lines.

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2. Electrical Characteristics

Table 2.43

RIIC Timing (2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

High-drive output is selected by the driving ability control register.

Test

Conditions

2

Item

Symbol

Min.*^1,

*

Max.

Unit

RIIC

(Fast-mode+)

ICFER.FMPE = 1

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6(12) × t_IICcyc+ 240

—

ns

pF

ns

pF

ns

pF

Figure 2.72

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

SCL, SDA input spike pulse removal time

SDA input bus free time

Start condition input hold time

Restart condition input setup time

Stop condition input setup time

Data input setup time

3(6) × t_IICcyc+ 120

—

3(6) × t_IICcyc+ 120

—

120

t_Sf

—

120

t_SP

0

1(4) × t_IICcyc

t_BUF

t_STAH

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

3(6) × t_IICcyc+ 120

—

t_IICcyc+ 120

120

—

120

—

t_IICcyc+ 20

—

Data input hold time

0

—

0

—

SCL, SDA capacitive load

SDA input rise time

550

1000

300

4 × t_PBcyc

—

Simple IIC

(Standard-mode)

t_Sr

SDA input fall time

t_Sf

SDA input spike pulse removal time

Data input setup time

t_SP

t_SDAS

t_SDAH

C_b

250

0

Data input hold time

—

SCL, SDA capacitive load

SCL, SDA input rise time

SCL, SDA input fall time

SCL, SDA input spike pulse removal time

Data input setup time

—

0

400

300

4 × t_PBcyc

—

Simple IIC

(Fast-mode)

t_Sr

t_Sf

t_SP

t_SDAS

t_SDAH

C_b

100

0

Data input hold time

—

SCL, SDA capacitive load

—

400

Note:

t_IICcyc: RIIC internal reference clock (IICφ) cycle, t_PBcyc: PCLKB cycle

Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by

the setting ICFER.NFE = 1.

Note 2. Cb is the total capacitance of the bus lines.

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V_IH

V_IL

SDA0 to SDA2

t_BUF

t_SCLH

t_STAS

t_STOS

t_STAH

t_SP

SCL0 to SCL2

P*¹

S*¹

Sr*¹

t_SCLL

t_Sr

t_Sf

t_SDAS

t_SCL

t_SDAH

Test conditions

Note 1. S, P, and Sr indicate the following conditions.

S: Start condition

V_IH= VCC × 0.7, V_IL= VCC × 0.3

V_OL= 0.6 V, I_OL= 6 mA (ICFER.FMPE = 0)

V_OL= 0.4 V, I_OL= 15 mA (ICFER.FMPE = 1)

P: Stop condition

Sr: Restart condition

Figure 2.72

RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output Timing

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2. Electrical Characteristics

Table 2.44

PMGI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Item Symbol

PMGIn_MDC output cycle

Test

Conditions

Min.

Max.

Unit

PMGI

t_MDC

80

20

0

—

20

ns

Figure 2.73

PMGIn_MDIO setup time (relative to PMGIn_MDC↑)

PMGIn_MDIO hold time (relative to PMGIn_MDC↑)

PMGIn_MDIO output delay time (relative to PMGIn_MDC↑)

t_SMDIO

t_HMDIO

t_DMDIO

0

n = 0, 1

t_MDC

PMGIn_MDC

(output)

t_SMDIO

t_HMDIO

PMGIn_MDIO

(input)

t_DMDIO

PMGIn_MDIO

(output)

(n = 0, 1)

Figure 2.73

Timing of Serial Management Access

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2. Electrical Characteristics

Table 2.45

ESC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

MII: High-drive output for the high-speed interface is selected in the drive capacity selection control register.

Test

Conditions

Item

Symbol

Min.

Max.

Unit

ESC (MII)

CATn_TX_CLK cycle time

t_Tcyc

t_TENd

t_MTDd

t_TRcyc

t_RDVs

t_RDVh

t_MRDs

t_MRDh

t_RERs

t_RERh

t_SMDIO

t_HMDIO

t_DMDIO

40

1

—

25

—

30

ns

—

CATn_TX_EN output delay time

CATn_ETXD0 to CATn_ETXD3 output delay time

CATn_RX_CLK cycle time

Figure 2.74

1

40

10

60

0

—

CATn_RX_DV setup time

Figure 2.75

CATn_RX_DV hold time

CATn_ERXD0 to CATn_ERXD3 setup time

CATn_ERXD0 to CATn_ERXD3 hold time

CATn_RX_ER setup time

Figure 2.76

Figure 2.77

CATn_RX_ER hold time

ESC

(MDIO)

CAT0_MDIO setup time (CAT0_MDC↑)

CAT0_MDIO hold time (CAT0_MDC↑)

CAT0_MDIO output delay time (CAT0_MDC↓)

0

n = 0, 1

CATn_TX_CLK

t_TENd

CATn_TX_EN

t_MTDd

CATn_ETXD[3:0]

(n = 0, 1)

Preamble

SFD

DATA

CRC

Figure 2.74

MII Transmission Timing (Normal Operation)

CATn_RX_CLK

t_RDVs

t_RDVh

CATn_RX_DV

t_MRDh

t_MRDs

CATn_ERXD[3:0]

Preamble

SFD

DATA

CRC

CATn_RX_ER

(n = 0, 1)

Figure 2.75

MII Reception Timing (Normal Operation)

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2. Electrical Characteristics

CATn_RX_CLK

CATn_RX_DV

CATn_ERXD[3:0]

Preamble

SFD

DATA

xxxx

t_RERh

t_RERs

CATn_RX_ER

(n = 0, 1)

Figure 2.76

MII Reception Timing (Error Occurrence)

CAT0_MDC

(output)

t_SMDIO

t_HMDIO

CAT0_MDIO

(input)

t_DMDIO

CAT0_MDIO

(output)

Figure 2.77

Timing of Serial Management Access

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2. Electrical Characteristics

Table 2.46

MMC Host Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Item

MMCIF MMC_CLK clock cycle

Symbol

Min.*¹

Max.

Unit

Conditions*²

t_MMCPP

t_MMCWH

t_MMCWL

t_MMCLH

2 × t_PBcyc

6.5

—

3

ns Figure 2.78

MMC_CLK clock high level width

MMC_CLK clock low level width

MMC_CLK clock rising time

MMC_CLK clock falling time

ns

6.5

—

t_MMCHL

—

3

MMC_CMD, MMC_D7 to MMC_D0 output data delay

(data transfer mode)

t_MMCODLY

–6.6

6.6

MMC_CMD, MMC_D7 to MMC_D0 input data setup

MMC_CMD, MMC_D7 to MMC_D0 input data hold

t_MMCISU

t_MMCIH

8

—

ns

2.5

Note 1. t_PBcyc: PCLKB cycle

Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.

For the MMC interface, the AC portion of the electrical characteristics is measured for each group.

t_MMCPP

t_MMCWL

t_MMCWH

MMC_CLK

t_MMCHL

t_MMCLH

t_MMCISUt_MMCIH

MMC_CMD,

MMC_D7 to MMC_D0 input

MMC_CMD,

MMC_D7 to MMC_D0 output

t_MMCODLY(max)

t_MMCODLY(min)

Figure 2.78

MMC Interface

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2. Electrical Characteristics

Table 2.47

ETHERC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

RMII: High-drive output for the high-speed interface is selected in the drive capacity selection control register.

MII: High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.

Max.

Unit

ETHERC

(RMII)

REF50CK cycle time

T_ck

—

20

—

35

0.5

2.5

3

—

ns

MHz

%

Figure 2.79 to

Figure 2.81

REF50CK frequency Typ. 50 MHz

REF50CK duty

50 + 100 ppm

—

65

3.5

15.0

—

REF50CK rise/fall time

T_ckr/ckf

T_co

ns

RMIIn_xxxx*¹output delay time

RMIIn_xxxx*²setup time

RMIIn_xxxx*²hold time

T_su

T_hd

1

—

RMIIn_xxxx*^1,*²rise/fall time

ETn_WOL output delay time

ETn_TX_CLK cycle time

ETn_TX_EN output delay time

ETn_ETXD0 to ETn_ETXD3 output delay time

ETn_CRS setup time

T_r/T_f

t_WOLd

t_Tcyc

t_TENd

t_MTDd

t_CRSs

t_CRSh

t_COLs

t_COLh

t_TRcyc

t_RDVs

t_RDVh

t_MRDs

t_MRDh

t_RERs

t_RERh

t_WOLd

—

1

5

23.5

—

Figure 2.83

—

ETHERC

(MII)

40

1

20

—

Figure 2.84

1

10

40

10

1

ETn_CRS hold time

—

ETn_COL setup time

—

Figure 2.85

ETn_COL hold time

—

ETn_RX_CLK cycle time

ETn_RX_DV setup time

—

Figure 2.86

ETn_RX_DV hold time

—

ETn_ERXD0 to ETn_ERXD3 setup time

ETn_ERXD0 to ETn_ERXD3 hold time

ETn_RX_ER setup time

—

Figure 2.87

Figure 2.88

ETn_RX_ER hold time

—

ETn_WOL output delay time

23.5

n = 0, 1

Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0

Note 2. RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER

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Tck

90%

Tckr

REF50CK 50%

Tckf

Tco

10%

Tsu

Thd

Tr

Tf

70%

*1

1

Change in

signal level

Change in

signal level

Change in

signal level

RMIIn_xxxx*

RMII0_xxxx

50%

30%

Signal

(n = 0, 1)

Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0, RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER

Figure 2.79

Timing with the REF50CK and RMII Signals

T_CK

REF50CK

T_CO

RMIIn_TXD_EN

RMII0_TXD_EN

T_CO

RRMMIIInI0__TTXXDD_11,,

RMIIn_TXD_0

RMII0_TXD0

Preamble

SFD

DATA

CRC

(n = 0, 1)

Figure 2.80

RMII Transmission Timing

REF50CK

Tsu

Thd

RRMMIIIIn0__CCRRSS__DDVV

Thd

Tsu

RMIIn_RXD_1,

RMII0_RXD1,

RMIIn_RXD_0

RMII0_RXD0

Preamble

DATA

CRC

SFD

RMIIn_RX_ER

RMII0_RX_ER

L

(n = 0, 1)

Figure 2.81

RMII Reception Timing (Normal Operation)

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REF50CK

RMIIn_CRS_DV

RMII0_CRS_DV

RMII0_RXD1,

Preamble

SFD

DATA

xxxx

RMIIn_RXD_1,

RMII0_RXD0

RMIIn_RXD_0

Thd

Tsu

RMIIn_RX_ER

RMII0_RX_ER

(n = 0, 1)

Figure 2.82

RMII Reception Timing (Error Occurrence)

REF50CK

t_WOLd

ETn_WOL

ET0_WOL

(n = 0, 1)

Figure 2.83

WOL Output Timing (RMII)

ETn_TX_CLK

ET0_TX_CLK

t_TENd

ETn_TX_EN

ET0_TX_EN

t_MTDd

ETn_ETXD[3:0]

ET0_ETXD[3:0]

Preamble

SFD

DATA

CRC

ETn_TX_ER

ET0_TX_ER

t_CRSs

t_CRSh

EETTn0__CCRRSS

ETn_COL

ET0_COL

(n = 0, 1)

Figure 2.84

MII Transmission Timing (Normal Operation)

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2. Electrical Characteristics

ETn_TX_CLK

ET0_TX_CLK

ETn_TX_EN

ET0_TX_EN

ETn_ETXD[3:0]

ET0_ETXD[3:0]

Preamble

JAM

ETn_TX_ER

ET0_TX_ER

ETn_CRS

ET0_CRS

t_COLs

t_COLh

ETn_COL

ET0_COL

(n = 0, 1)

Figure 2.85

MII Transmission Timing (Conflict Occurrence)

ETn_RX_CLK

ET0_RX_CLK

t_RDVs

t_RDVh

ETn_RX_DV

ET0_RX_DV

t_MRDh

t_MRDs

ETn_ERXD[3:0]

ET0_ERXD[3:0]

Preamble

SFD

DATA

CRC

ETn_RX_ER

ET0_RX_ER

(n = 0, 1)

Figure 2.86

MII Reception Timing (Normal Operation)

ETn_RX_CLK

ET0_RX_CLK

ETn_RX_DV

ET0_RX_DV

ET0_ERXD[3:0]

ETn_ERXD[3:0]

Preamble

SFD

DATA

xxxx

t_RERh

t_RERs

ETn_RX_ER

ET0_RX_ER

(n = 0, 1)

Figure 2.87

MII Reception Timing (Error Occurrence)

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2. Electrical Characteristics

ETn_RX_CLK

ET0_RX_CLK

t_WOLd

ETn_WOL

ET0_WOL

(n = 0, 1)

Figure 2.88

WOL Output Timing (MII)

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2. Electrical Characteristics

Table 2.48

PDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF

,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.*¹

Max.

Unit

PDC PIXCLK input cycle time

PIXCLK input high pulse width

PIXCLK input low pulse width

PIXCLK rising time

t_PIXcyc

t_PIXH

37

—

5

ns

Figure 2.89

10

t_PIXL

t_PIXr

—

PIXCLK falling time

t_PIXf

—

5

PCKO output cycle time

PCKO output high pulse width

PCKO output low pulse width

PCKO rising time

t_PCKcyc

t_PCKH

t_PCKL

t_PCKr

2 × t_PBcyc

—

5

Figure 2.90

Figure 2.91

(t_PCKcyc– t_PCKr– t_PCKf)/2 – 3

—

10

5

PCKO falling time

t_PCKf

5

VSYNC/HSYNC input setup time

VSYNC/HSYNC input hold time

PIXD input setup time

t_SYNCS

t_SYNCH

t_PIXDS

t_PIXDH

—

10

5

PIXD input hold time

Note 1. t_PBcyc: PCLKB cycle

t_PIXcyc

t_PIXH

t_PIXf

PIXCLK input

t_PIXr

t_PIXL

Figure 2.89

PDC Input Clock Timing

t_PCKcyc

t_PCKH

t_PCKf

PCKO pin output

t_PCKr

t_PCKL

Figure 2.90

PDC Output Clock Timing

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2. Electrical Characteristics

PIXCLK

VSYNC

HSYNC

t_SYNCS

t_SYNCH

t_SYNCS

t_SYNCH

t_PIXDS

t_PIXDH

PIXD7 to PIXD0

Figure 2.91

Table 2.49

PDC AC Timing

GLCDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

t_Ecyc

t_WL

Min.

—

Typ.

—

Max.

30*¹

0.55

30*¹

0.6

Unit

MHz

t_Ecyc

Test Conditions

Figure 2.92

LCD_EXTCLK Input clock frequency

LCD_EXTCLK Input clock Low pulse width

LCD_EXTCLK Input clock High pulse width

LCD_CLK Output clock frequency

LCD_CLK Output clock Low pulse width

LCD_CLK Output clock High pulse width

LCD data output Delay timing

0.45

—

t_WH

—

t_Lcyc

t_LOL

t_LOH

t_DD

—

MHz

t_Lcyc

ns

Figure 2.93

Figure 2.94

0.4

—

0.4

—

0.6

–3.5*²

—

4*²

Note 1. Parallel RGB888,666,565: Max. 27 MHz

Serial RGB888: Max. 30 MHz (4x speed)

Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc) to indicate group membership appended to their names as groups.

For the GLCDC interface, the AC portion of the electrical characteristics is measured for each group.

If we use group “-A” and “-B” combination, “LCD data output Delay timing (t_DD)” is Min = –5.0 ns, Max = 5.5 ns.

t_Dcyc,t_Ecyc

t_WH

t_WL

V_IHV_IH

1/2 Vcc

V_ILV_IL

LCD_EXTCLK

Figure 2.92

LCD_EXTCLK Clock Input Timing

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t_Lcyc

t_LOL

t_LOH

LCD_CLK

t_LOF

t_LOR

Figure 2.93

LCD_CLK Clock Output Timing

LCD_CLK

t_DD

Output on

falling edge

LCD_DATA23 to

LCD_DATA0,

LCD_TCON3 to

LCD_TCON0

t_DD

Output on

rising edge

Figure 2.94

LCD Output Data Timing

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2. Electrical Characteristics

Table 2.50

Δ-Σ Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = 8 to 60 MHz, T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF

,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Unit*¹

Item

Symbol

t_DScyc

Min.

Max.

Conditions

DSMIF

Clock cycle

Master

Slave

2

32

200

—

t_PBcyc

ns

Figure 2.95

40

16

15

10

0

Clock high level

Clock low level

Setup time

Master

Slave

t_DSCKWH

t_DSCKWL

t_SU

ns

—

ns

Master

Slave

—

ns

—

ns

Master

Slave

—

ns

Figure 2.96,

Figure 2.97

—

ns

Hold time

Master

Slave

t_H

—

ns

10

—

ns

Note 1. t_PBcyc: PCLKB cycle

t_DSCKWH

t_DSCKWL

DSMCLKn

(n = 0 to 5)

t_DScyc

Figure 2.95

Figure 2.96

Figure 2.97

Clock Input/Output Timing

DSMCLKn

(input or output)

DSMDATn (input)

(n = 0 to 5)

t_SU

t_H

Reception Timing (DSMCLKn Rising Synchronous)

DSMCLKn

(input or output)

DSMDATn (input)

t_SU

t_H

(n = 0 to 5)

Reception Timing (DSMCLKn Falling Synchronous)

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2. Electrical Characteristics

Table 2.51

SDHI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6V, 2.7V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = T

,

opr

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30pF

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions*

Item

Symbol

Min.

Max.

Unit

1

SDHI SDHI_CLK output cycle time

SDHI_CLK output width at high level

SDHI_CLK output width at low level

SDHI_CLK output rising time

t_PP(SD)

t_WH(SD)

t_WL(SD)

20

0.4 × t_PP(SD)

—

3

ns

Figure 2.98

t_TLH(SD)

t_THL(SD)

t_ODLY(SD)

SDHI_CLK output falling time

—

3

SDHI_CMD, SDHI_D3 to SDHI_D0 output data delay (data

transfer mode)

–6.5

4

SDHI_CMD, SDHI_D3 to SDHI_D0 input data setup time

SDHI_CMD, SDHI_D3 to SDHI_D0 input data hold time

t_ISU(SD)

t_IH(SD)

6

2

—

ns

Note 1. We recommend using pin names that have a letter (“-A”, “-B”, etc.) to indicate group membership per group in the test.

For the SDHI, the AC portion of the electrical characteristics is measured per group.

t_PP(SD)

t_WL(SD)

t_WH(SD)

V_IH

50% VCC

SDHI_CLK output

V_L

t_THL(SD)

t_TLH(SD)

t_ISU(SD)t_IH(SD)

SDHI_CMD, SDHI_D3 to SDHI_D0 input

SDHI_CMD, SDHI_D3 to SDHI_D0 output

t_ODLY(SD)

Figure 2.98

SD Host Interface Input/Output Signal Timing

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Page 137 of 158

RX72M Group

2. Electrical Characteristics

2.5

USB Characteristics

Table 2.52

On-Chip USB Low Speed (Host Only) Characteristics (DP and DM Pin Characteristics)

= 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

UCLK = 48 MHz, PCLKA = 8 to 120 MHz,

PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

V_IH

Min.

2.0

—

Typ.

—

Max.

—

Unit

V

Test Conditions

| DP – DM |

Input

characteristics

Input high level voltage

Input low level voltage

V_IL

0.8

V

Differential input sensitivity

V_DI

0.2

0.8

2.8

0.0

1.3

75

—

V

Differential common mode range

Output high level voltage

Output low level voltage

Cross-over voltage

Rise time

V_CM

V_OH

V_OL

V_CRS

t_LR

2.5

V

Output

characteristics

3.6

V

I_OH= –200 μA

I_OL= 2 mA

0.3

V

2.0

V

Figure 2.99

300

125

24.80

ns

%

kΩ

Fall time

t_LF

75

Rise/fall time ratio

t_LR/ t_LF

R_pd

80

t_LR/ t_LF

Pull-down

DP/DM pull-down resistance

14.25

characteristics (when the host controller function is

selected)

90%

V_CRS

DP, DM

10%

t_LR

10%

t_LF

Figure 2.99

DP and DM Output Timing (Low Speed)

Observation

point

dp

27

200 pF to

600 pF

3.6 V

1.5 k

dm

27

200 pF to

600 pF

Figure 2.100

Test Circuit (Low Speed)

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May 31, 2019

Page 138 of 158

RX72M Group

2. Electrical Characteristics

Table 2.53

On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics)

= 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

UCLK = 48 MHz, PCLKA = 8 to 120 MHz,

PCLKB = 8 to 60 MHz, T = T

a

opr

Item

Symbol

V_IH

Min.

2.0

—

Typ.

—

Max.

—

Unit

V

Test Conditions

| DP – DM |

Input

characteristics

Input high level voltage

Input low level voltage

V_IL

0.8

V

Differential input sensitivity

V_DI

0.2

0.8

2.8

0.0

1.3

4

—

V

Differential common mode range

Output high level voltage

Output low level voltage

Cross-over voltage

Rise time

V_CM

V_OH

V_OL

V_CRS

t_FR

2.5

V

Output

characteristics

3.6

V

I_OH= –200 μA

I_OL= 2 mA

0.3

V

2.0

V

Figure 2.101

20

ns

%

Ω

Fall time

t_FF

4

20

Rise/fall time ratio

Output resistance

t

_FR/ t_FF

Z_DRV

R_pu

90

111.11

44

t_FR/ t_FF

Rs = 27 Ω included

Idle state

28

Pull-up and

pull-down

DP pull-up resistance

(when the function controller

characteristics function is selected)

0.900

1.425

1.575

3.090

kΩ

At transmission and reception

DP/DM pull-down resistance

R_pd

14.25

—

24.80

kΩ

(when the host controller function

is selected)

90%

V_CRS

DP, DM

10%

t_FR

t_FF

Figure 2.101

DP and DM Output Timing (Full-Speed)

Observation

point

dp

27

50 pF

dm

27

Figure 2.102

Test Circuit (Full-Speed)

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 139 of 158

RX72M Group

2. Electrical Characteristics

2.6

A/D Conversion Characteristics

Table 2.54

12-Bit A/D (Unit 0) Conversion Characteristics

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKC = 1 MHz to 60 MHz, T = T_opr, Source impedance = 1.0 kΩ

a

Item

Min.

8

Typ.

—

Max.

12

Unit

Bit

Test Conditions

Resolution

Analog input capacitance

—

30

pF

Channel-dedi-

cated sample-and- (Operation at PCLKC = 60 MHz)

hold circuits in use

Conversion time*¹

1.06

—

μs

 Sampling of channel-

dedicated sample-and-

hold circuits in 24 states

 Sampling in 15 states

(0.4 + 0.25)

2

*

(AN000 to AN002)

Offset error

—

±1.5

±3.5

LSB

AN000 to AN002 = 0.25 V

Full-scale error

AN000 to AN002 = VREFH0

– 0.25 V

Quantization error

—

±0.5

±3.0

±1.0

±1.5

—

LSB

μs

Absolute accuracy

±5.5

±2.0

±3.0

20

DNL differential nonlinearity error

INL integral nonlinearity error

Holding characteristics of sample-and-

hold circuits

Dynamic range

0.25

—

VREFH0

– 0.25

V

Channel-dedi-

Conversion time*¹

cated sample-and- (Operation at PCLKC = 60 MHz)

0.48

(0.267)*²

—

μs

Sampling in 16 states

hold circuits not in

Offset error

use

—

±1.0

±0.5

±2.5

±0.5

±1.0

±2.5

—

LSB

Full-scale error

(AN000 to AN007)

Quantization error

Absolute accuracy

±4.5

±1.5

±2.5

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds

during A/D conversion, values may not fall within the above ranges.

Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states

is indicated.

Note 2. The value in parentheses indicates the sampling time.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 140 of 158

RX72M Group

2. Electrical Characteristics

Table 2.55

12-Bit A/D (Unit 1) Conversion Characteristics

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKD = 1 MHz to 60 MHz, T = T_opr, Source impedance = 1.0 kΩ

a

Item

Min.

8

Typ.

—

Max.

12

Unit

Bit

Test Conditions

Resolution

Conversion time*¹

(Operation at PCLKD = 60 MHz)

0.88

(0.633)*²

—

μs

Sampling in 38 states

(ADSAM.SAM = 1)

Conversion time*¹

(Operation at PCLKD = 30 MHz)

1

—

μs

Sampling in 15 states

(ADSAM.SAM = 1)

(0.500)*²

Analog input capacitance

Offset error

—

30

pF

±2.0

±0.5

±4.0

±1.5

±3.5

—

LSB

Full-scale error

Quantization error

Absolute accuracy

±6.0

±4.0

DNL differential nonlinearity error

(Operation at PCLKD = 60 MHz)

DNL differential nonlinearity error

(Operation at PCLKD = 30 MHz)

—

±1.5

±2.0

±2.5

±4.0

±3.5

LSB

INL integral nonlinearity error

(Operation at PCLKD = 60 MHz)

INL integral nonlinearity error

(Operation at PCLKD = 30 MHz)

Note:

The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds

during A/D conversion, values may not fall within the above ranges.

Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states

is indicated.

Note 2. The value in parentheses indicates the sampling time.

Table 2.56

A/D Internal Reference Voltage Characteristics

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = PCLKD = 60 MHz, T = T

a

opr

Test

Conditions

Item

Min.

1.13

Typ.

1.18

Max.

1.23

Unit

V

A/D internal reference voltage

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May 31, 2019

Page 141 of 158

RX72M Group

2. Electrical Characteristics

2.7

D/A Conversion Characteristics

Table 2.57

D/A Conversion Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

—

Min.

12

Typ.

12

Max.

12

Unit

Test Conditions

Resolution

Unbuffered output Absolute accuracy

Bit

—

±6.0

LSB

2-MΩ resistive load

10-bit conversion

Differential nonlinearity error

DNL

R_O

t_S

—

5

±1.0

8.6

—

±2.0

—

LSB

kΩ

μs

2-MΩ resistive load

Output resistance

Setting time

3

20-pF capacitive load

Buffered output

Load resistance

Load capacitance

Output voltage

R_L

—

kΩ

pF

V

C_L

—

0.2

—

50

V_O

—

AVCC1 –

0.2

Differential nonlinearity error

Integral nonlinearity error

Setting time

DNL

INL

t_S

—

±1.0

±2.0

—

±2.0

±4.0

4

LSB

μs

2.8

Temperature Sensor Characteristics

Table 2.58

Temperature Sensor Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Relative accuracy

Temperature slope

Min.

—

Typ.

±1

Max.

—

Unit

°C

Test Conditions

—

4

—

mV/°C

V

Output voltage (at 25°C)

Temperature sensor start time

Sampling time*¹

—

1.21

—

30

—

μs

4.15

—

μs

Note 1. Set the S12AD1.ADSSTRT register such that the sampling time of the 12-bit A/D converter satisfies this specification.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 142 of 158

RX72M Group

2. Electrical Characteristics

2.9

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Table 2.59

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Test

Conditions

Item

Symbol

V_POR

Min.

2.5

Typ.

2.6

Max.

Unit

V

Voltage detection

level

Power-on

reset (POR)

Low power consumption

function disabled*¹

2.7

Figure 2.103

Low power consumption

function enabled*²

1.8

2.25

Voltage detection circuit (LVD0)

Voltage detection circuit (LVD1)

Voltage detection circuit (LVD2)

V_{det0_1}

V_{det0_2}

V_{det0_3}

V_{det1_1}

V_{det1_2}

V_{det1_3}

V_{det2_1}

V_{det2_2}

V_{det2_3}

t_POR

2.84

2.77

2.70

2.89

2.82

2.75

2.89

2.82

2.75

—

2.94

2.87

2.80

2.99

2.92

2.85

2.99

2.92

2.85

4.6

3.04

2.97

2.90

3.09

3.02

2.95

3.09

3.02

2.95

—

Figure 2.104

Figure 2.105

Figure 2.106

Internal reset time Power-on reset time

LVD0 reset time

ms

Figure 2.103

Figure 2.104

Figure 2.105

Figure 2.106

t_LVD0

—

0.70

0.57

—

LVD1 reset time

t_LVD1

—

LVD2 reset time

t_LVD2

—

Minimum VCC down time

t_VOFF

200

—

μs

Figure 2.103,

Figure 2.104

Response delay time

t_det

—

200

Figure2.103to

Figure 2.106

LVD operation stabilization time (after LVD is enabled)

Hysteresis width (LVD1 and LVD2)

T_d(E-A)

V _LVH

—

10

—

μs

Figure 2.105,

Figure 2.106

70

mV

Note:

The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det1,

and V_det2for the POR/ LVD.

Note 1. The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b.

Note 2. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.

t_VOFF

V_POR

VCC

Internal reset signal

(Low is valid)

t_det

t_POR

t_det

t_dett_POR

Figure 2.103

Power-on Reset Timing

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 143 of 158

RX72M Group

2. Electrical Characteristics

t_VOFF

VCC

V_det0

Internal reset signal

(Low is valid)

t_det

t_LVD0

Figure 2.104

Voltage Detection Circuit Timing (V_det0

)

t_VOFF

V_LVH

VCC

V_det1

LVD1E

T_d(E-A)

LVD1

Comparator output

LVD1CMPE

LVD1MON

Internal reset signal

(Low is valid)

When LVD1RN = L

t_det

t_LVD1

t_det

When LVD1RN = H

t_LVD1

Figure 2.105

Voltage Detection Circuit Timing (V_det1)

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 144 of 158

RX72M Group

2. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det2

LVD2E

T_d(E-A)

LVD2

Comparator output

LVD2CMPE

LVD2MON

Internal reset signal

(Low is valid)

When LVD2RN = L

t_det

t_LVD2

When LVD2RN = H

t_LVD2

Figure 2.106

Voltage Detection Circuit Timing (V_det2)

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May 31, 2019

Page 145 of 158

RX72M Group

2. Electrical Characteristics

2.10 Oscillation Stop Detection Timing

Table 2.60

Oscillation Stop Detection Circuit Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

a

opr

Item

Symbol

t_dr

Min.

—

Typ.

—

Max.

1

Unit

ms

Test Conditions

Figure 2.107

Detection time

Main clock or

PLL clock

t_dr

OSTDSR.OSTDF

LOCO clock

ICLK

Figure 2.107

Oscillation Stop Detection Timing

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May 31, 2019

Page 146 of 158

RX72M Group

2. Electrical Characteristics

2.11 Battery Backup Function Characteristics

Table 2.61

Battery Backup Function Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

V

= 2.0 to 3.6 V, T = T

BATT

a

opr

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

V

Voltage level for switching to battery backup

V_DETBATT

V_BATTSW

2.50

2.70

2.60

—

2.70

—

Figure 2.108

Lower-limit V_BATTvoltage for power supply switching due to

VCC voltage drop

VCC-off period for starting power supply switching

t_VOFFBATT

200

—

μs

Note:

The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the

voltage level for switching to battery backup (V_DETBATT).

t_VOFFBATT

VCC voltage

guaranteed range

V_DETBATT

VCC

V_BATTSW

V

_BATTvoltage

V_BATT

guaranteed range

Switching

prohibited

V_BATT

Switching

prohibited

Backup power

area

V

_BATTsupply

VCC supply

Note.

The V_BATTvoltage when the supplied power source switches from VCC to V_BATTshould not be lower than V_BATTSW

,

the lower-limit V_BATTvoltage for switching between power supplies due to a drop in the VCC voltage.

Figure 2.108

Battery Backup Function Characteristics

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May 31, 2019

Page 147 of 158

RX72M Group

2. Electrical Characteristics

2.12 Flash Memory Characteristics

Table 2.62

Code Flash Memory Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Temperature range for programming/erasure: T = T

a

opr

FCLK = 4 MHz

FCLK = 15 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Unit

Item

Symbol

Min.

—

Typ.

0.75

49

Max.

Min.

Typ.

0.38

25

Max.

Min.

Typ.

0.34

22

Max.

Programming time 128 bytes

_PEC≤ 100 times

t_P128

t_P8K

13.2

176

704

15.8

212

848

216

864

260

1040

—

6.6

88

—

6

ms

N

8 Kbytes

—

80

32 Kbytes

t_P32K

t_P128

t_P8K

—

194

0.91

60

—

97

352

8

—

88

320

7.2

96

ms

Programming time 128 bytes

_PEC> 100 times

—

0.46

30

—

0.41

27

ms

N

8 Kbytes

32 Kbytes

8 Kbytes

32 Kbytes

8 Kbytes

32 Kbytes

—

106

424

132

528

158

632

—

ms

t_P32K

t_E8K

t_E32K

t_E8K

t_E32K

N_PEC

—

234

78

—

117

48

—

106

43

384

120

480

144

576

—

ms

Erasure time

_PEC≤ 100 times

—

ms

N

—

283

94

—

173

58

—

157

52

ms

Erasure time

_PEC> 100 times

—

ms

N

—

341

—

208

—

189

—

ms

Reprogramming/erasure cycle*¹

10000

Times

2

*

Suspend delay time during

programming

t_SPD

—

264

216

—

132

—

120

μs

First suspend delay time during

erasing

t_SESD1

(in suspend priority mode)

Second suspend delay time

during erasure

(in suspend priority mode)

t_SESD2

—

1.7

—

1.7

—

1.7

ms

Suspend delay time during

erasure

t_SEED

(in erasure priority mode)

Forced stop command

Data hold time*³

t_FD

—

32

—

22

—

20

—

μs

t_DRP

10

Year

Note 1. Definition of reprogram/erase cycle:

The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 1000),

erasing can be performed n times for each block. For instance, when 128-byte programming is performed 64 times for different

addresses in 8-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasing is not enabled (overwriting is prohibited).

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming (guaranteed range is from 1 to the

value of the minimum value).

Note 3. This shows the characteristics when reprogramming is performed within the specified range, including the minimum value.

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RX72M Group

2. Electrical Characteristics

Table 2.63

Data Flash Memory Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Temperature range for programming/erasure: T = T

a

opr

FCLK = 4 MHz

FCLK = 15 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Unit

Item

Symbol

Min.

—

Typ.

0.36

3.1

4.7

8.9

—

Max.

Min.

Typ.

0.18

1.9

2.9

5.4

—

Max.

Min.

Typ.

0.16

1.7

2.6

4.9

—

Max.

1.7

10

Programming time 4 bytes

t_DP4

3.8

18

—

1.9

11

—

ms

Erasure time

64 bytes

128 bytes

256 bytes

4 bytes

t_DP64

—

t_DP128

t_DP256

t_DBC4

—

27

—

16

—

15

ms

—

50

—

31

—

28

ms

Blank check time

—

84

—

33

—

30

μs

64 bytes

2 Kbytes

t_DBC64

t_DBC2K

N_DPEC

—

280

6160

—

110

2420

—

100

2200

—

μs

—

μs

Reprogramming/erasure cycle*¹

100000

—

100000

—

100000

—

Times

2

*

Suspend delay time during

programming

t_DSPD

—

264

—

132

—

120

μs

First suspend

delay time during

erasure

(in suspend prior-

ity mode)

64 bytes

128 bytes

256 bytes

—

216

—

132

—

120

μs

Second suspend

delay time during

erasure

(in suspend prior-

ity mode)

64 bytes

128 bytes

256 bytes

—

300

390

570

—

300

390

570

—

300

390

570

μs

Suspend delay

time during erasing

(in suspend prior-

ity mode)

64 bytes

128 bytes

256 bytes

—

10

—

300

390

570

32

—

10

—

300

390

570

22

—

10

—

300

390

570

20

μs

—

μs

Forced stop command

Data hold time*³

t_FD

μs

t_DDRP

—

Year

Note 1. Definition of reprogram/erase cycle:

The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),

erasing can be performed n times for each block. For instance, when 4-byte programming is performed 512 times for different

addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasing is not enabled (overwriting is prohibited).

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming (guaranteed range is from 1 to the

value of the minimum value).

Note 3. This shows the characteristics when reprogramming is performed within the specified range, including the minimum value.

R01DS0332EJ0100 Rev.1.00

May 31, 2019

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RX72M Group

2. Electrical Characteristics

• Suspension during programming

FCU command

Program

Ready

Suspend

t_SPD

FSTATR.FRDY

Not Ready

Ready

Programming pulse

Programming

• Suspension during erasure in suspend priority mode

FCU command

Erase

Suspend

Not Ready

Erasing

Resume

t_SESD1

t_SESD2

FSTATR.FRDY

Erasure pulse

Ready

Not Ready

Erasing

• Suspension during erasure in erasure priority mode

FCU command

FSTATR.FRDY

Erasure pulse

Erase

Suspend

Not Ready

Erasing

t_SEED

Ready

Figure 2.109

Flash Memory Programming/Erasure Suspension Timing

R01DS0332EJ0100 Rev.1.00

May 31, 2019

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RX72M Group

2. Electrical Characteristics

2.13 Boundary Scan

Table 2.64

Boundary Scan Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V

= 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

BATT

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

T = T

,

opr

a

Output load conditions: V = VCC × 0.5, V = VCC × 0.5, C = 30 pF,

OH

OL

High-drive output is selected by the driving ability control register.

Test

Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TRST# pulse width

TMS setup time

t_TCKcyc

t_TCKH

t_TCKL

t_TCKr

100

45

—

5

ns

Figure 2.110

t_TCKf

—

5

t_TRSTW

t_TMSS

t_TMSH

t_TDIS

20

—

40

t_TCKcycFigure 2.111

ns

Figure 2.112

TMS hold time

TDI setup time

TDI hold time

t_TDIH

TDO data delay time

t_TDOD

t_TCKcyc

t_TCKH

t_TCKf

TCK

t_TCKL

t_TCKr

Figure 2.110

Boundary Scan TCK Timing

TCK

RES#

TRST#

t_TRSTW

Figure 2.111

Boundary Scan TRST# Timing

R01DS0332EJ0100 Rev.1.00

May 31, 2019

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RX72M Group

2. Electrical Characteristics

TCK

t_TMSS

t_TMSH

TMS

t_TDIS

t_TDIH

TDI

t_TDOD

TDO

Figure 2.112

Boundary Scan Input/Output Timing

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 152 of 158

RX72M Group

Appendix 1. Package Dimensions

Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas

Electronics Corporation website.

RENESAS Code

Previous Code

MASS (Typ) [g]

JEITA Package Code

P-LFBGA224-13x13-0.80

PLBG0224GA-A

224FHE

0.4

Unit: mm

E

B

A

INDEX AREA

y

1

S

y CZ

e

(ZE)

R

P

N

M

L

Dimensions in millimeters

Min Nom Max

Reference

Symbol

K

J

D

E

A

A₁

e

b

x₁

x₂

y

y₁

n

12.9

ꢀ

13.0 13.1

H

G

F

E

D

C

B

A

ꢀ

1.40

0.35 0.40

0.80

0.45 0.50

0.30

ꢀ

0.40

ꢀ

0.15

0.08

0.10

0.20

ꢀ

1

2

3

4

5

6

7

8 9 10 11 12 13 14 15

ꢀ

n x ꢀb

x1

S A

S

B

ꢀ

224

0.90

x2

Z_D

Z_E

ꢀ

Figure A 224-Pin LFBGA (PLBG0224GA-A)

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 153 of 158

RX72M Group

Appendix 1. Package Dimensions

Figure B 176-Pin LFBGA (PLBG0176GA-A)

R01DS0332EJ0100 Rev.1.00

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RX72M Group

Appendix 1. Package Dimensions

Figure C 176-Pin LFQFP (PLQP0176KB-C)

R01DS0332EJ0100 Rev.1.00

May 31, 2019

Page 155 of 158

General Precautions in the Handling of Microprocessing Unit and Microcontroller

Unit Products

The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the

products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps

must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be

adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.

Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and

measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor

devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.

2. Processing at power-on

The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of

register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset

pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins

in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the

level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O

pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal

elements. Follow the guideline for input signal during power-off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are

generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of

the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal

become possible.

5. Clock signals

After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program

execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator

during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal

produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V_IL

(Max.) and V_IH(Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the

input level is fixed, and also in the transition period when the input level passes through the area between V_IL(Max.) and V_IH(Min.).

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these

addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.

The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms

of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,

operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-

evaluation test for the given product.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

equipment; industrial robots; etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause

serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all

liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	R5F572MNDGFC
厂家：	RENESAS TECHNOLOGY CORP
描述：	240-MHz 32-bit RX MCU, on-chip double-precision FPU, 1396 CoreMark
文件：	总158页 (文件大小：1828K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F572MNDGFC [RENESAS]

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