R5F64188PFB_技术文档

R32C/118 Group Datasheet

R32C/118 Group

RENESAS MCU

REJ03B0255-0100

Rev.1.00

Nov 19, 2009

1. Overview

1.1

Features

The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM

code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing

in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from

low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral

functions, provides support for a vast range of application fields.

The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory

space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,

multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on-

2

chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I C, and WDT enables to

minimize external components.

The R32C/100 Series, in particular, provides the R32C/118 Group as a standard product. This product,

provided as a 100/144-pin plastic molded LQFP package, configures nine channels of serial interface,

2

one channel of multi-master I C-bus interface, and two channels of CAN module.

1.1.1

Applications

Car audio, audio, printer, office/industrial equipment etc.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 1 of 122

R32C/118 Group

1. Overview

1.1.2

Performance Overview

Table 1.1 to Table 1.4 show the performance overview of the R32C/118 Group.

Table 1.1

Unit

R32C/118 Group Performance for the 144 pin-Package (1/2)

Function Performance

Central

CPU

R32C/100 Series CPU Core

• Basic instructions: 108

processing unit

• Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz)

• Multiplier: 32-bit × 32-bit ꢀ 64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit ꢀ 64-bit

• IEEE-754 floating point standard: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode,

(1)

microprocessor mode (optional

)

Memory

Flash memory: 384 Kbytes to 1 Mbyte

RAM: 40 K/48 K/63 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for memory size of each product group

(1)

Voltage

Detector

Low voltage

detector

Optional

Low voltage detection interrupt

Clock

Clock generator

• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/re-oscillation

detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

External Bus Bus and memory • Address space: 4 Gbytes (of which up to 64 Mbytes is user

Expansion

expansion

accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select

outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width

selectable (8/16/32 bits)

Interrupts

Interrupt vectors: 261

External interrupt inputs: NMI, INT × 9, key input × 4

Interrupt priority levels: 7 levels

Watchdog Timer

DMA

15 bits × 1 (selectable input frequency from prescaler output)

DMAC

4 channels

• Cycle-steal transfer mode

• Request sources: 57

• 2 transfer modes: Single transfer, repeat transfer

DMAC II

• Can be activated by any peripheral interrupt source

• 3 transfer functions: Immediate data transfer, calculation transfer,

chained transfer

I/O Ports

Note:

Programmable

I/O ports

• 2 input-only ports

• 120 CMOS inputs/outputs

• 32 ports are 5 V tolerant

• A pull-up resistor is selectable for every 4 input ports (except 5 V

tolerant inputs)

1. Please contact a Renesas sales office to use the optional feature.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 2 of 122

R32C/118 Group

1. Overview

Table 1.2

Unit

R32C/118 Group Performance for the 144-pin Package (2/2)

Function Performance

Timer A

Timer

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-

phase encoder input) × 3

Timer B

16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement

mode, pulse-width measurement mode

Three-phase

motor control

timer

Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Serial

UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels

2

Interface

• I C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

(1)

(2)

• IEBus

(optional ) (UART0 to UART6)

A/D Converter

10-bit resolution × 34 channels

Sample and hold functionality integrated

D/A Converter

CRC Calculator

X-Y Converter

Intelligent I/O

8-bit resolution × 2

16

12

5

CRC-CCITT (X + X + X + 1)

16 bits × 16 bits

Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 24

(1)

Serial interface: Variable-length synchronous serial I/O mode, IEBus

(2)

mode (optional

1 channel

)

2

Multi-master I C-bus Interface

CAN Module

2 channels

CAN functionality compliant with ISO11898-1

32 mailboxes

Flash Memory

Programming and erasure supply voltage:

VCC = 3.0 to 5.5 V

Minimum endurance: 1, 000 program/erase cycles

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

Operating Frequency/Supply

Voltage

50 MHz/VCC = 3.0 to 5.5 V

Operating Temperature

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

Current Consumption

35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

Package

Notes:

144-pin plastic molded LQFP (PLQP0144KA-A)

1. IEBus is a trademark of NEC Electronics Corporation.

2. Please contact a Renesas sales office to use the optional feature.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 3 of 122

R32C/118 Group

1. Overview

Table 1.3

Unit

R32C/118 Group Performance for the 100-pin Package (1/2)

Function Performance

Central

CPU

R32C/100 Series CPU Core

• Basic instructions: 108

processing unit

• Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz)

• Multiplier: 32-bit × 32-bit ꢀ 64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit ꢀ 64-bit

• IEEE-754 floating point standard: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode,

(1)

microprocessor mode (optional

)

Memory

Flash memory: 384 Kbytes to 1 Mbyte

RAM: 40 K/48 K/63 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for memory size of each product group

(1)

Voltage

Detector

Low voltage

detector

Optional

Low voltage detection interrupt

Clock

Clock generator

• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/re-oscillation

detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

External Bus Bus and memory • Address space: 4 Gbytes (of which up to 64 Mbytes is user

Expansion

expansion

accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select

outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width

selectable (8/16 bits)

Interrupts

Interrupt vectors: 261

External interrupt inputs: NMI, INT × 6, key input × 4

Interrupt priority levels: 7 levels

Watchdog Timer

DMA

15 bits × 1 (selectable input frequency from prescaler output)

DMAC

4 channels

• Cycle-steal transfer mode

• Request sources: 51

• 2 transfer modes: Single transfer, repeat transfer

DMAC II

• Can be activated by any peripheral interrupt source

• 3 transfer functions: Immediate data transfer, calculation transfer,

chained transfer

I/O Ports

Note:

Programmable

I/O ports

• 2 input-only ports

• 84 CMOS inputs/outputs

• 32 ports are 5 V tolerant

• A pull-up resistor is selectable for every 4 input ports (except 5 V

tolerant inputs)

1. Please contact a Renesas sales office to use the optional feature.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 4 of 122

R32C/118 Group

1. Overview

Table 1.4

Unit

R32C/118 Group Performance for the 100-pin Package (2/2)

Function Performance

Timer A

Timer

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-

phase encoder input) × 3

Timer B

16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement

mode, pulse-width measurement mode

Three-phase

motor control

timer

Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Serial

UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels

2

Interface

• I C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

(1)

(2)

• IEBus

(optional ) (UART0 to UART6)

A/D Converter

10-bit resolution × 26 channels

Sample and hold functionality integrated

D/A Converter

CRC Calculator

X-Y Converter

Intelligent I/O

8-bit resolution × 2

16

12

5

CRC-CCITT (X + X + X + 1)

16 bits × 16 bits

Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 19

(1)

Serial interface: Variable-length synchronous serial I/O mode, IEBus

(2)

mode (optional

1 channel

)

2

Multi-master I C-bus Interface

CAN Module

2 channels

CAN functionality compliant with ISO11898-1

32 mailboxes

Flash Memory

Programming and erasure supply voltage:

VCC = 3.0 to 5.5 V

Minimum endurance: 1, 000 program/erase cycles

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

Operating Frequency/Supply

Voltage

50 MHz/VCC = 3.0 to 5.5 V

Operating Temperature

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

Current Consumption

35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

Package

Notes:

100-pin plastic molded LQFP (PLQP0100KB-A)

1. IEBus is a trademark of NEC Electronics Corporation.

2. Please contact a Renesas sales office to use the optional feature.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 5 of 122

R32C/118 Group

1. Overview

1.2

Product Information

Table 1.5 lists the product information and Figure 1.1 shows the details of the part number.

Table 1.5

R32C/118 Group Product List

As of November, 2009

Package Code ⁽¹⁾ROM Capacity ⁽²⁾

Part Number

RAM Capacity

Remarks

R5F64185NFD

R5F64185DFD

R5F64185PFD

R5F64185NFB

R5F64185DFB

R5F64185PFB

R5F64186NFD

R5F64186DFD

R5F64186PFD

R5F64186NFB

R5F64186DFB

R5F64186PFB

R5F64187NFD

R5F64187DFD

R5F64187PFD

R5F64187NFB

R5F64187DFB

R5F64187PFB

R5F64188NFD

R5F64188DFD

R5F64188PFD

R5F64188NFB

R5F64188DFB

R5F64188PFB

R5F64189NFD

R5F64189DFD

R5F64189PFD

R5F64189NFB

R5F64189DFB

R5F64189PFB

(P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

-20°C to 85°C (version N)

-40°C to 85°C (version D)

-40°C to 85°C (version P)

PLQP0144KA-A

384 Kbytes

+ 8 Kbytes

PLQP0100KB-A

PLQP0144KA-A

40 Kbytes

512 Kbytes

+ 8 Kbytes

PLQP0100KB-A

PLQP0144KA-A

640 Kbytes

+ 8 Kbytes

48Kbytes

PLQP0100KB-A

PLQP0144KA-A

768 Kbytes

+ 8 Kbytes

PLQP0100KB-A

PLQP0144KA-A

63 Kbytes

1 Mbyte

+ 8 Kbytes

PLQP0100KB-A

(P): On planning phase

Notes:

1. The old package codes are as follows:PLQP0100KB-A: 100P6Q-A, PLQP0144KA-A: 144P6Q-A

2. Data flash memory provides an additional 8 Kbytes of ROM capacity.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 6 of 122

R32C/118 Group

1. Overview

Part Number

R5 F 64 18 9 P XXX FD

Package Code

FB : PLQP0100KB-A

FD : PLQP0144KA-A

ROM Number

Omitted in the flash memory version

Temperature Code

N : -20°C to 85°C

D : -40°C to 85°C

P : -40°C to 85°C

ROM/RAM Capacity

5 : 384 KB/40 KB

6 : 512 KB/40 KB

7 : 640 KB/48 KB

8 : 768 KB/63 KB

9 : 1 MB/63 KB

R32C/118 Group

R32C/100 Series

Memory Type

F : Flash memory version

Figure 1.1

Part Numbering

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 7 of 122

R32C/118 Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a block diagram of the R32C/118 Group.

8

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Peripheral functions

Timer:

Timer A 16 bits × 5 timers

Timer B 16 bits × 6 timers

Clock generator:

4 circuits

- XIN-XOUT

- XCIN-XCOUT

- On-chip oscillator

- PLL frequency synthesizer

A/D converter:

10 bits × 1 circuit

Standard: 10 inputs

Maximum: 34 inputs ⁽¹⁾

Three-phase motor

controller

D/A converter:

8 bits × 2 channels

Watchdog timer:

15 bits

Serial interface:

9 channels

X-Y converter:

16 bits × 16 bits

DMAC

Multi-master I²C-bus

interface:

CRC calculator (CCITT)

X¹⁶+ X¹²+ X⁵+ 1

DMAC II

1 channel

Memory

ROM

Intelligent I/O

Time Measurement: 16

Wave generation: 24 ⁽²⁾

Serial interface:

R32C/100 Series CPU Core

R2R0

FLG

INTB

ISP

USP

PC

SVF

SVP

VCT

R3R1

R6R4

- Variable-length

R7R5

RAM

R7R5

A0

synchronous serial I/O

A0

A1

- IEBus ⁽⁴⁾

A1

A2

A3

Multiplier

A3

FB

CAN module:

2 channels

FB

SB

Floating-point unit

Port P15

Port P14

Port P14_1

Port P13

Port P12

Port P11

8

4

8

5

(Note 5)

Notes:

1. 34 inputs are available in the 144-pin package. In the 100-pin package, up to 26 inputs are provided.

2. 24 outputs are available in the 144-pin package. In the 100-pin package, 19 outputs are provided.

3. Eight ports are available in the 144-pin package. In the 100-pin package, five I/O ports and one input-

only port (P9_1) are provided.

4. IEBus is a trademark of NEC Electronics Corporation.

5. Ports P11 to P15 are available in the 144-pin package only.

Figure 1.2

R32C/118 Group Block Diagram

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 8 of 122

R32C/118 Group

1. Overview

1.4

Pin Assignments

Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.6 to Table 1.12 show the pin

characteristics.

(Note 1)

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

IIO0_0 / IIO1_0 / D8 / P1_0

AN0_7 / D7 / P0_7

P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6

P4_5 / CS2 / A21 / CLK6

P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6

P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6

P12_5 / D21

AN0_6 / D6 / P0_6

AN0_5 / D5 / P0_5

AN0_4 / D4 / P0_4

WR3 / BC3 / P11_4

P12_6 / D22

IIO1_3 / RTS8 / CTS8 / WR2 / CS3 / P11_3

IIO1_2 / RXD8 / CS2 / P11_2

IIO1_1 / CLK8 / CS1 / P11_1

IIO1_0 / TXD8 / CS0 / P11_0

AN0_3 / D3 / P0_3

P12_7 / D23

P5_0 / WR0 / WR

P5_1 / WR1 / BC1

P5_2 / RD

P5_3 / CLKOUT / BCLK

P13_0 / D24 / OUTC2_4

P13_1 / D25 / OUTC2_5

VCC

AN0_2 / D2 / P0_2

AN0_1 / D1 / P0_1

AN0_0 / D0 / P0_0

IIO0_7 / RTS6 / CTS6 / SS6 / AN15_7 / P15_7

IIO0_6 / CLK6 / AN15_6 / P15_6

IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5

IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4

IIO0_3 / RTS7 / CTS7 / AN15_3 / P15_3

IIO0_2 / RXD7 / AN15_2 / P15_2

IIO0_1 / CLK7 / AN15_1 / P15_1

VSS

P13_2 / D26 / OUTC2_6

VSS

R32C/118 GROUP

(Note 2)

P13_3 / D27 / OUTC2_3

P5_4 / HLDA / CS1 / TXD7

P5_5 / HOLD / CLK7

PLQP0144KA-A

(144P6Q-A)

(Top view)

P5_6 / ALE / CS2 / RXD7

P5_7 / RDY / CS3 / CTS7 / RTS7

P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT

P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN

P13_6 / D30 / OUTC2_1 / ISCLK2

P13_7 / D31 / OUTC2_7

P6_0 / TB0IN / CTS0 / RTS0 / SS0

P6_1 / TB1IN / CLK0

IIO0_0 / TXD7 / AN15_0 / P15_0

VCC

KI3 / AN_7 / P10_7

KI2 / AN_6 / P10_6

KI1 / AN_5 / P10_5

KI0 / AN_4 / P10_4

P6_2 / TB2IN / RXD0 / SCL0 / STXD0

P6_3 / TXD0 / SDA0 / SRXD0

P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2

P6_5 / CLK1

AN_3 / P10_3

AN_2 / P10_2

AN_1 / P10_1

AVSS

VSS

AN_0 / P10_0

P6_6 / RXD1 / SCL1 / STXD1

VCC

VREF

AVCC

P6_7 / TXD1 / SDA1 / SRXD1

STXD4 / SCL4 / RXD4 / ADTRG / P9_7

P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA

(Note 3)

Notes:

1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.

2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3

3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.

Figure 1.3

Pin Assignment for the 144-pin Package (top view)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 9 of 122

R32C/118 Group

1. Overview

Table 1.6

Pin Characteristics for the 144-pin Package (1/4)

Pin Control

Interrupt

Analog BusControl

Port

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

No.

1

2

P9_6

TXD4/SDA4/SRXD4/

CAN1OUT

ANEX1

P9_5

CLK4/CAN1IN/

ANEX0

CAN1WU

3

4

5

P9_4

P9_3

P9_2

TB4IN

TB3IN

TB2IN

CTS4/RTS4/SS4

CTS3/RTS3/SS3

TXD3/SDA3/SRXD3

DA1

DA0

OUTC2_0/ISTXD2/

IEOUT

6

7

8

9

P9_1

P9_0

TB1IN

TB0IN

RXD3/SCL3/STXD3

CLK3

ISRXD2/IEIN

P14_6 INT8

P14_5 INT7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

P14_4

P14_3

INT6

VDC0

P14_1

VDC1

NSD

CNVSS

XCIN

P8_7

XCOUT P8_6

RESET

XOUT

VSS

XIN

VCC

P8_5 NMI

P8_4 INT2

P8_3 INT1

CAN0IN/CAN0WU/

CAN1IN/CAN1WU

27

28

29

30

P8_2 INT0

P8_1

CAN0OUT/CAN1OUT

TA4IN/U

CTS5/RTS5/SS5

IIO1_5/UD0B/UD1B

UD0A/UD1A

P8_0

TA4OUT/U RXD5/SCL5/STXD5

P7_7

TA3IN

CLK5/CAN0IN/

IIO1_4/UD0B/UD1B

CAN0WU

31

P7_6

TA3OUT

TXD5/SDA5/SRXD5/

IIO1_3/UD0A/UD1A

CTS8/RTS8/CAN0OUT

32

33

34

35

36

P7_5

P7_4

P7_3

P7_2

P7_1

TA2IN/W

RXD8

IIO1_2

IIO1_1

TA2OUT/W CLK8

TA1IN/V

CTS2/RTS2/SS2/TXD8 IIO1_0

TA1OUT/V CLK2

TB5IN/

TA0IN

RXD2/SCL2/STXD2/

MSCL

IIO1_7/OUTC2_2/

ISRXD2/IEIN

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 10 of 122

R32C/118 Group

1. Overview

Table 1.7

Pin Characteristics for the 144-pin Package (2/4)

Pin Control

Interrupt

Analog BusControl

Pin Pin

Port

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

No.

37

P7_0

TA0OUT

TXD2/SDA2/SRXD2/

MSDA

IIO1_6/OUTC2_0/

ISTXD2/IEOUT

38

39

40

41

42

43

44

45

46

47

48

49

50

P6_7

P6_6

TXD1/SDA1/SRXD1

VCC

RXD1/SCL1/STXD1

VSS

P6_5

P6_4

P6_3

P6_2

P6_1

P6_0

P13_7

P13_6

P13_5

CLK1

CTS1/RTS1/SS1

TXD0/SDA0/SRXD0

RXD0/SCL0/STXD0

CLK0

OUTC2_1/ISCLK2

TB2IN

TB1IN

TB0IN

CTS0/RTS0/SS0

OUTC2_7

D31

D30

D29

OUTC2_1/ISCLK2

OUTC2_2/ISRXD2/

IEIN

51

P13_4

OUTC2_0/ISTXD2/

IEOUT

D28

52

53

54

55

56

57

58

59

60

61

62

P5_7

P5_6

P5_5

P5_4

P13_3

CTS7/RTS7

RXD7

RDY/CS3

ALE/CS2

HOLD

CLK7

TXD7

HLDA/CS1

D27

OUTC2_3

OUTC2_6

VSS

VCC

P13_2

D26

P13_1

P13_0

P5_3

OUTC2_5

OUTC2_4

D25

D24

CLKOUT/

BCLK

63

64

65

66

67

68

69

70

71

72

73

P5_2

P5_1

P5_0

P12_7

P12_6

P12_5

P4_7

P4_6

P4_5

P4_4

P4_3

RD

WR1/BC1

WR0/WR

D23

D22

D21

TXD6/SDA6/SRXD6

RXD6/SCL6/STXD6

CLK6

CS0/A23

CS1/A22

CS2/A21

CS3/A20

A19

CTS6/RTS6/SS6

TXD3/SDA3/SRXD3

OUTC2_0/ISTXD2/

IEOUT

74

VCC

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 11 of 122

R32C/118 Group

1. Overview

Table 1.8

Pin Characteristics for the 144-pin Package (3/4)

Pin Control

Interrupt

Analog BusControl

Port

Timer Pin UART/CAN Module Pin

RXD3/SCL3/STXD3

Intelligent I/O Pin

ISRXD2/IEIN

No.

75

P4_2

A18

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

VSS

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

P3_3

P3_2

P3_1

P12_4

P12_3

P12_2

P12_1

P12_0

CLK3

CTS3/RTS3/SS3

TA4IN/U

A17

A16

A15(/D15)

A14(/D14)

A13(/D13)

A12(/D12)

A11(/D11)

A10(/D10)

A9(/D9)

D20

TA4OUT/U

TA2IN/W

TA2OUT/W

TA1IN/V

TA1OUT/V

TA3OUT

UD0B/UD1B

CTS6/RTS6/SS6

RXD6/SCL6/STXD6

CLK6

D19

D18

D17

TXD6/SDA6/SRXD6

D16

VCC

VSS

P3_0

TA0OUT

UD0A/UD1A

A8(/D8)

P2_7

P2_6

P2_5

P2_4

P2_3

P2_2

P2_1

AN2_7

AN2_6

AN2_5

AN2_4

AN2_3

AN2_2

AN2_1

A7(/D7)

A6(/D6)

A5(/D5)

A4(/D4)

A3(/D3)

A2(/D2)

A1(/D1)/

BC2(/D1)

101

P2_0

AN2_0

A0(/D0)/

BC0(/D0)

102

103

104

105

106

107

108

109

110

111

112

113

114

P1_7 INT5

P1_6 INT4

P1_5 INT3

P1_4

IIO0_7/IIO1_7

IIO0_6/IIO1_6

IIO0_5/IIO1_5

IIO0_4/IIO1_4

IIO0_3/IIO1_3

IIO0_2/IIO1_2

IIO0_1/IIO1_1

IIO0_0/IIO1_0

D15

D14

D13

D12

D11

D10

D9

P1_3

P1_2

P1_1

P1_0

D8

P0_7

AN0_7

AN0_6

AN0_5

AN0_4

D7

P0_6

D6

P0_5

D5

P0_4

D4

P11_4

BC3/WR3

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 12 of 122

R32C/118 Group

1. Overview

Table 1.9

Pin Characteristics for the 144-pin Package (4/4)

Pin Control

Interrupt

Analog BusControl

Port

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

No.

CS3/WR2

CS2

CS1

CS0

D3

115

P11_3

P11_2

P11_1

P11_0

P0_3

CTS8/RTS8

RXD8

IIO1_3

116

117

118

119

120

121

122

123

124

125

126

127

128

129

IIO1_2

IIO1_1

IIO1_0

CLK8

TXD8

AN0_3

P0_2

AN0_2

D2

P0_1

AN0_1

D1

P0_0

AN0_0

D0

P15_7

P15_6

P15_5

P15_4

P15_3

P15_2

P15_1

CTS6/RTS6/SS6

CLK6

IIO0_7

IIO0_6

IIO0_5

IIO0_4

IIO0_3

IIO0_2

IIO0_1

AN15_7

AN15_6

AN15_5

AN15_4

AN15_3

AN15_2

AN15_1

RXD6/SCL6/STXD6

TXD6/SDA6/SRXD6

CTS7/RTS7

RXD7

CLK7

130 VSS

131

P15_0

TXD7

IIO0_0

AN15_0

132 VCC

133

P10_7 KI3

P10_6 KI2

P10_5 KI1

P10_4 KI0

P10_3

AN_7

AN_6

AN_5

AN_4

AN_3

AN_2

AN_1

134

135

136

137

138

P10_2

139

P10_1

140 AVSS

141

P10_0

P9_7

AN_0

142 VREF

143 AVCC

144

RXD4/SCL4/STXD4

ADTRG

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 13 of 122

R32C/118 Group

1. Overview

(Note 1)

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

IIO0_2 / IIO1_2 / D10 / P1_2

P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN

P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT

P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6

P4_5 / CS2 / A21 / CLK6

IIO0_1 / IIO1_1 / D9 / P1_1

IIO0_0 / IIO1_0 / D8 / P1_0

AN0_7 / D7 / P0_7

AN0_6 / D6 / P0_6

P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6

P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6

P5_0 / WR0 / WR

AN0_5 / D5 / P0_5

AN0_4 / D4 / P0_4

AN0_3 / D3 / P0_3

P5_1 / WR1 / BC1

AN0_2 / D2 / P0_2

P5_2 / RD

AN0_1 / D1 / P0_1

P5_3 / CLKOUT / BCLK

R32C/118 GROUP

(Note 2)

AN0_0 / D0 / P0_0

P5_4 / HLDA / CS1 / TXD7

P5_5 / HOLD / CLK7

KI3 / AN_7 / P10_7

KI2 / AN_6 / P10_6

P5_6 / ALE / CS2 / RXD7

KI1 / AN_5 / P10_5

PLQP0100KB-A

(100P6Q-A)

(Top view)

P5_7 / RDY / CS3 / CTS7 / RTS7

P6_0 / TB0IN / CTS0 / RTS0 / SS0

P6_1 / TB1IN / CLK0

KI0 / AN_4 / P10_4

AN_3 / P10_3

AN_2 / P10_2

P6_2 / TB2IN / RXD0 / SCL0 / STXD0

P6_3 / TXD0 / SDA0 / SRXD0

P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2

P6_5 / CLK1

AN_1 / P10_1

AVSS

AN_0 / P10_0

VREF

P6_6 / RXD1 / SCL1 / STXD1

P6_7 / TXD1 / SDA1 / SRXD1

AVCC

STXD4 / SCL4 / RXD4 / ADTRG / P9_7

CAN1OUT / SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6

CAN1IN / CAN1WU / CLK4 / ANEX0 / P9_5

P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA

P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / MSCL

P7_2 / TA1OUT / V / CLK2

(Note 3)

Notes:

1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.

2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3

3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.

Figure 1.4

Pin Assignment for the 100-pin Package (top view)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 14 of 122

R32C/118 Group

1. Overview

Table 1.10

Pin Characteristics for the 100-pin Package (1/3)

Pin Control

Interrupt

Analog BusControl

Port

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

No.

DA1

DA0

1

2

3

4

5

6

7

8

9

P9_4

P9_3

TB4IN

TB3IN

CTS4/RTS4/SS4

VDC0

P9_1

VDC1

NSD

CNVSS

XCIN

P8_7

XCOUT P8_6

RESET

XOUT

VSS

10

11

12

13

14

15

16

17

XIN

VCC

P8_5 NMI

P8_4 INT2

P8_3 INT1

CAN0IN/CAN0WU/

CAN1IN/CAN1WU

18

19

20

21

P8_2 INT0

P8_1

CAN0OUT/CAN1OUT

TA4IN/U

CTS5/RTS5/SS5

IIO1_5/UD0B/UD1B

UD0A/UD1A

P8_0

TA4OUT/U RXD5/SCL5/STXD5

P7_7

TA3IN

CLK5/CAN0IN/

IIO1_4/UD0B/UD1B

CAN0WU

22

P7_6

TA3OUT

TA2IN/W

TXD5/SDA5/SRXD5/

CTS8/RTS8/CAN0OUT

IIO1_3/UD0A/UD1A

23

24

25

26

27

P7_5

P7_4

P7_3

P7_2

P7_1

RXD8

IIO1_2

IIO1_1

TA2OUT/W CLK8

TA1IN/V

CTS2/RTS2/SS2/TXD8 IIO1_0

TA1OUT/V CLK2

TB5IN/

TA0IN

RXD2/SCL2/STXD2/

MSCL

IIO1_7/OUTC2_2/

ISRXD2/IEIN

28

P7_0

TA0OUT

TXD2/SDA2/SRXD2/

MSDA

IIO1_6/OUTC2_0/

ISTXD2/IEOUT

29

30

31

32

33

34

35

36

37

38

P6_7

P6_6

P6_5

P6_4

P6_3

P6_2

P6_1

P6_0

P5_7

P5_6

TXD1/SDA1/SRXD1

RXD1/SCL1/STXD1

CLK1

CTS1/RTS1/SS1

TXD0/SDA0/SRXD0

RXD0/SCL0/STXD0

CLK0

OUTC2_1/ISCLK2

TB2IN

TB1IN

TB0IN

CTS0/RTS0/SS0

CTS7/RTS7

RDY/CS3

ALE/CS2

RXD7

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 15 of 122

R32C/118 Group

1. Overview

Table 1.11

Pin Characteristics for the 100-pin Package (2/3)

Pin Control

Interrupt

Analog BusControl

Port

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

No.

39

P5_5

P5_4

P5_3

CLK7

TXD7

HOLD

40

41

HLDA/CS1

CLKOUT/

BCLK

42

43

44

45

46

47

48

49

P5_2

P5_1

P5_0

P4_7

P4_6

P4_5

P4_4

P4_3

RD

WR1/BC1

WR0/WR

CS0/A23

CS1/A22

CS2/A21

CS3/A20

A19

TXD6/SDA6/SRXD6

RXD6/SCL6/STXD6

CLK6

CTS6/RTS6/SS6

TXD3/SDA3/SRXD3

OUTC2_0/ISTXD2/

IEOUT

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

P4_2

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

P3_3

P3_2

P3_1

RXD3/SCL3/STXD3

CLK3

ISRXD2/IEIN

A18

A17

CTS3/RTS3/SS3

TA4IN/U

A16

A15(/D15)

A14(/D14)

A13(/D13)

A12(/D12)

A11(/D11)

A10(/D10)

A9(/D9)

TA4OUT/U

TA2IN/W

TA2OUT/W

TA1IN/V

TA1OUT/V

TA3OUT

UD0B/UD1B

UD0A/UD1A

VCC

P3_0

TA0OUT

A8(/D8)

VSS

P2_7

P2_6

P2_5

P2_4

P2_3

P2_2

P2_1

P2_0

AN2_7

AN2_6

AN2_5

AN2_4

AN2_3

AN2_2

AN2_1

AN2_0

A7(/D7)

A6(/D6)

A5(/D5)

A4(/D4)

A3(/D3)

A2(/D2)

A1(/D1)

A0(/D0)/

BC0(/D0)

71

72

73

74

75

P1_7 INT5

P1_6 INT4

P1_5 INT3

P1_4

IIO0_7/IIO1_7

IIO0_6/IIO1_6

IIO0_5/IIO1_5

IIO0_4/IIO1_4

IIO0_3/IIO1_3

D15

D14

D13

D12

D11

P1_3

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 16 of 122

R32C/118 Group

1. Overview

Table 1.12

Pin Characteristics for the 100-pin Package (3/3)

Pin Control

Interrupt

Analog BusControl

Port

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

No.

76

P1_2

P1_1

P1_0

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

IIO0_2/IIO1_2

IIO0_1/IIO1_1

IIO0_0/IIO1_0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

AN0_7

AN0_6

AN0_5

AN0_4

AN0_3

AN0_2

AN0_1

AN0_0

AN_7

P10_7 KI3

P10_6 KI2

P10_5 KI1

P10_4 KI0

P10_3

AN_6

AN_5

AN_4

AN_3

P10_2

AN_2

P10_1

AN_1

AVSS

P10_0

AN_0

VREF

AVCC

P9_7

P9_6

RXD4/SCL4/STXD4

ADTRG

TXD4/SDA4/SRXD4/

CAN1OUT

ANEX1

100

P9_5

CLK4/CAN1IN/

ANEX0

CAN1WU

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 17 of 122

R32C/118 Group

1. Overview

1.5

Pin Definitions and Functions

Table 1.13 to Table 1.17 show the pin definitions and functions.

Table 1.13

Function

Power supply

Pin Definitions and Functions (1/4)

Symbol

VCC, VSS

I/O

I

Description

Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V

Connecting pins VDC0, VDC1

for decoupling

A decoupling capacitor for internal voltage should be

connected between VDC0 and VDC1

—

capacitor

Analog power

supply

AVCC, AVSS

Power supply for the A/D converter. AVCC and AVSS

should be connected to VCC and VSS, respectively

I

Reset input

CNVSS

RESET

CNVSS

NSD

I

The MCU is reset when this pin is driven low

This pin should be connected to VSS via a resistor

Debug port

This pin is to communicate with a debugger. It should be

connected to VCC via a resistor of 1 to 4.7 kΩ

I/O

Main clock input XIN

Input/output for the main clock oscillator. A crystal, or a

ceramic resonator should be connected between pins XIN

and XOUT. An external clock should be input at the XIN

while leaving the XOUT open

I

Main clock output XOUT

O

I

Sub clock input

XCIN

Input/output for the sub clock oscillator. A crystal oscillator

should be connected between pins XCIN and XCOUT. An

external clock should be input at the XCIN while leaving the

XCOUT open

Sub clock output XCOUT

O

BCLK output

Clock output

BCLK

O

BCLK output

CLKOUT

INT0 to INT8

Output of the clock with the same frequency as fC, f8, or f32

Input for external interrupts

(1)

External interrupt

input

I

NMI input

P8_5/NMI

I

Input for NMI

Key input interrupt KI0 to KI3

Input for the key input interrupt

Bus control pins D0 to D7

Input/output of data (D0 to D7) while accessing an external

memory space with a separate bus

I/O

D8 to D15

Input/output of data (D8 to D15) while accessing an

external memory space with 16-bit or 32-bit separate bus

(2)

Input/output of data (D16 to D31) while accessing an

external memory space with 32-bit separate bus

D16 to D31

A0 to A23

I/O

O

Output of address bits A0 to A23

A0/D0 to A7/D7

Output of address bits (A0 to A7) and input/output of data

I/O (D0 to D7) by time-division while accessing an external

memory space with multiplexed bus

A8/D8 to

A15/D15

Output of address bits (A8 to A15) and input/output of data

I/O (D8 to D15) by time-division while accessing an external

memory space with 16-bit or 32-bit multiplexed bus

Notes:

1. Pins INT6 to INT8 are available in the 144-pin package only.

2. Pins D16 to D31 are available in the 144-pin package only.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 18 of 122

R32C/118 Group

1. Overview

Table 1.14

Pin Definitions and Functions (2/4)

Symbol I/O

Function

Description

Output of byte control (BC0 and BC2) and input/output of

Bus control pins BC0/D0, BC2/D1

(1)

I/O data (D0 and D1) by time-division while accessing an

external memory space with multiplexed bus

CS0 to CS3

O

Chip select output

WR0/WR1/WR2/

WR3

Output of write, byte control, and read signals. Either WRx

or WR and BCx can be selected by a program.

Data is read when RD is low.

WR/BC0/BC1/

BC2/BC3

(1)

• When WR0, WR1, WR2, WR3, and RD are selected,

data is written to the following address:

4n+0, when WR0 is low

RD

4n+1, when WR1 is low

4n+2, when WR2 is low

4n+3, when WR3 is low

on 32-bit external data bus

or

an even address, when WR0 is low

an odd address, when WR1 is low

on 16-bit external data bus

O

• When WR, BC0, BC1, BC2, BC3, and RD are selected,

data is written, when WR is low

and

the following address is accessed:

4n+0, when BC0 is low

4n+1, when BC1 is low

4n+2, when BC2 is low

4n+3, when BC3 is low

on 32-bit external data bus

or

an even address, when BC0 is low

an odd address, when BC1 is low

on 16-bit external data bus

ALE

O

I

Latch enable signal in multiplexed bus format

HOLD

HLDA

RDY

The MCU is in a hold state while this pin is held low

This pin is driven low while the MCU is held in a hold state

O

Bus cycle is extended by the CPU if this pin is low on the

falling edge of the BCLK

I

Note:

1. Pins BC2/D1, WR2, WR3, BC2, and BC3 are available in the 144-pin package only.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 19 of 122

R32C/118 Group

1. Overview

Table 1.15

Pin Definitions and Functions (3/4)

Function

Symbol

I/O

Description

(1, 2)

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_7

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_4

P8_6, P8_7

I/O ports in CMOS. Each port can be programmed to input

or output under the control of the direction register.

Some ports are 5 V tolerant inputs.

Pull-up resistors and N-channel open drain setting can be

enabled on some ports. Refer to Table 1.17 “Pin

Specifications” for details

I/O port

I/O

P9_0 to P9_7

P10_0 to P10_7

P11_0 to P11_4

P12_0 to P12_7

P13_0 to P13_7

P14_3 to P14_6

P15_0 to P15_7

(2)

P9_1 (for 100-pin

package)

P14_1 (for 144-

pin package)

Input port in CMOS

Pull-up resistor is selectable.

Refer to Table 1.17 “Pin Specifications” for details

Input port

I

Timer A

Timer B

TA0OUT to

TA4OUT

Timers A0 to A4 input/output

I/O

TA0IN to TA4IN

TB0IN to TB5IN

U,U,V,V,W,W

I

Timers A0 to A4 input

Timers B0 to B5 input

Three-phase

motor control

timer output

Three-phase motor control timer output

O

Serial interface

CTS0 to CTS8

RTS0 to RTS8

CLK0 to CLK8

RXD0 to RXD8

TXD0 to TXD8

SDA0 to SDA6

SCL0 to SCL6

STXD0 to

I

Handshake input

Handshake output

O

I/O Transmit/receive clock input/output

I

Serial data input

Serial data output

O

2

I/O Serial data input/output

I C bus

(simplified)

I/O Transmit/receive clock input/output

Serial interface

special functions STXD6

Serial data output in slave mode

O

SRXD0 to

SRXD6

Serial data input in slave mode

I

SS0 to SS6

I

Input to control serial interface special functions

Notes:

1. Port P9_1 in the 100-pin package is an input-only port.

2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only.

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R32C/118 Group

1. Overview

Table 1.16

Function

Pin Definitions and Functions (4/4)

Symbol

I/O

Description

A/D converter

AN_0 to AN_7

AN0_0 to AN0_7

AN2_0 to AN2_7

AN15_0 to

Analog input for the A/D converter

I

(1)

AN15_7

ADTRG

I

External trigger input for the A/D converter

ANEX0

Expanded analog input for the A/D converter and output in

external op-amp connection mode

I/O

ANEX1

I

Expanded analog input for the A/D converter

Output for the D/A converter

D/A converter

DA0, DA1

O

Referencevoltage VREF

input

Reference voltage input for the A/D converter and D/A

converter

I

Intelligent I/O

IIO0_0 to IIO0_7

Input/output for the Intelligent I/O group 0. Either input

capture or output compare is selectable

I/O

I

IIO1_0 to IIO1_7

Input/output for the Intelligent I/O group 1. Either input

capture or output compare is selectable

UD0A, UD0B,

UD1A, UD1B

Input for the two-phase encoder

OUTC2_0 to

Output for OC (output compare) of the Intelligent I/O group

2

O

(2)

OUTC2_7

ISCLK2

ISRXD2

ISTXD2

IEIN

I/O Clock input/output for the serial interface

I

Receive data input for the serial interface

Transmit data output for the serial interface

Receive data input for the serial interface

Transmit data output for the serial interface

O

I

IEOUT

O

2

MSDA

I/O Serial data input/output

Multi-master I C-

bus

MSCL

I/O Transmit/receive clock input/output

CAN Module

CAN0IN, CAN1IN

I

Receive data input for the CAN communications

Transmit data output for the CAN communications

CAN0OUT,

CAN1OUT

O

CAN0WU,

CAN1WU

Input for the CAN wake-up interrupt

I

Notes:

1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.

2. Pins OUTC2_3 to OUTC2_7 are available in the 144-pin package only.

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R32C/118 Group

1. Overview

Table 1.17

Pin Specifications

Package

144- 100-

Selectable Functions

(3)

Pin names

5 V tolerant input

N-channel

(1)

Pull-up resistor

(2)

3

open drain

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_3

P5_4 to P5_7

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_3

P8_4, P8_6, P8_7

P9_0 to P9_3 (144-pin)

P9_1, P9_3 (100-pin)

P9_4 to P9_7

P10_0 to P10_7

P11_0 to P11_3

P11_4

3

P12_0 to P12_3

P12_4 to P12_7

P13_0 to P13_7

P14_1

P14_3 to P14_6

P15_0 to P15_7

3

Notes:

1. Pull-up resistors are selected in 4-pin units, but are only enabled for those pins set as input ports.

2. N-channel open drain output can be enabled on the applicable pins on a discrete pin basis.

3. 5 V tolerant input is enabled when an applicable pin is set as an input port. When it is set as an I/O

port, to enable 5 V tolerant input, this pin should be set as N-channel open drain output.

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R32C/118 Group

2. Central Processing Unit (CPU)

The CPU contains registers as shown below. There are two register banks each consisting of registers

R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.

General purpose

registers

b31

b23

b15

b7

b0

R2R0

R3R1

R6R4

R7R5

R2H

R2L

R3L

R0H

R1H

R0L

R1L

R3H

Data registers ⁽¹⁾

R6

R7

R4

R5

A0

A1

A2

A3

SB

FB

Address registers ⁽¹⁾

Static base register ⁽¹⁾

Frame base register ⁽¹⁾

USP

ISP

User stack pointer

Interrupt stack pointer

Interrupt vector table base register

Program counter

INTB

PC

FLG

Flag register

b31

b24 b23

b16 b15

b8 b7

b0

RND

IPL

U I O B S Z D C

DP

FU

FO

Blank fields represent reserved.

b31

b0

Fast interrupt

registers

SVF

SVP

VCT

Save flag register

Save PC register

Vector register

b23

b0

DMAC-associated

registers ⁽²⁾

DMD0

DMA mode register

DMD0

DCT0

DMA terminal count register

DMA terminal count reload register

DMA source address register

DMA source address reload register

DMA destination address register

DCT0

DCR0

DSA0

DSR0

DDA0

DDR0

DMA destination address reload register

Notes:

1.There are two banks of these registers.

2.There are four identical sets of DMAC-associated registers.

Figure 2.1

CPU Registers

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R32C/118 Group

2. Central Processing Unit (CPU)

2.1

2.1.1

General Purpose Registers

Data Registers (R2R0, R3R1, R6R4, and R7R5)

These 32-bit registers are primarily used for transfers and arithmetic/logic operations.

Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into

R2 and R0, R3R0 can be divided into R3 and R1, etc.

Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and

R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).

2.1.2

Address Registers (A0, A1, A2, and A3)

These 32-bit registers have functions similar to data registers. They are also used for address register

indirect addressing and address register relative addressing.

2.1.3

Static Base Register (SB)

This 32-bit register is used for SB relative addressing.

2.1.4

Frame Base Register (FB)

This 32-bit register is used for FB relative addressing.

2.1.5

Program Counter (PC)

This 32-bit counter indicates the address of the instruction to be executed next.

2.1.6

Interrupt Vector Table Base Register (INTB)

This 32-bit register indicates the start address of a relocatable vector table.

2.1.7

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack

pointer (ISP).

Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt

stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for

details.

To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer

(USP) or the interrupt stack pointer (ISP) to a multiple of 4.

2.1.8

Flag Register (FLG)

This 32-bit register indicates the CPU status.

2.1.8.1

Carry Flag (C flag)

This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic

logic unit (ALU).

2.1.8.2

Debug Flag (D flag)

This flag is only for debugging. Only set this bit to 0.

2.1.8.3

Zero Flag (Z flag)

This flag becomes 1 when the result of an operation is 0; otherwise it is 0.

2.1.8.4

Sign Flag (S flag)

This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.

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R32C/118 Group

2. Central Processing Unit (CPU)

2.1.8.5

Register Bank Select Flag (B flag)

This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the

register bank 1 is selected.

2.1.8.6

Overflow Flag (O flag)

This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.

2.1.8.7

Interrupt Enable Flag (I flag)

This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable

them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.

2.1.8.8

Stack Pointer Select Flag (U flag)

To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set

this flag to 1.

It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a

software interrupt number from 0 to 127 is executed.

2.1.8.9

Floating-point Underflow Flag (FU flag)

This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also

becomes 1 when the operand has invalid numbers (subnormal numbers).

2.1.8.10 Floating-point Overflow Flag (FO flag)

This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also

becomes 1 when the operand has invalid numbers (subnormal numbers).

2.1.8.11 Processor Interrupt Priority Level (IPL)

The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority

level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the

selected IPL.

When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.

2.1.8.12 Fixed-point Radix Point Designation Bit (DP bit)

This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result

to take. It is used in the MULX instruction.

2.1.8.13 Floating-point Rounding Mode (RND)

The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.

2.1.8.14 Reserved

Only set this bit to 0. The read value is undefined.

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R32C/118 Group

2. Central Processing Unit (CPU)

2.2

Fast Interrupt Registers

The following three registers are provided to minimize the overhead of interrupt sequence.

2.2.1

Save Flag Register (SVF)

This 32-bit register is used to save the flag register when a fast interrupt is generated.

2.2.2

Save PC Register (SVP)

This 32-bit register is used to save the program counter when a fast interrupt is generated.

2.2.3

Vector Register (VCT)

This 32-bit register is used to indicate a jump address when a fast interrupt is generated.

2.3

DMAC-associated Registers

There are seven types of DMAC-associated registers.

2.3.1

DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)

These 32-bit registers are used to set DMA transfer mode, bit rate etc.

2.3.2

DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)

These 24-bit registers are used to set DMA transfer counting.

2.3.3

DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)

These 24-bit registers are used to set the reloaded values for DMA terminal count registers.

2.3.4

DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)

These 32-bit registers are used to set DMA source addresses.

2.3.5

DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)

These 32-bit registers are used to set the reloaded value for DMA source address register.

2.3.6

DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)

These 32-bit registers are used to set DMA destination address.

2.3.7

DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and

DDR3)

These 32-bit registers are used to set reloaded values for DMA destination address registers.

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R32C/118 Group

3. Memory

Figure 3.1 shows the memory map of the R32C/118 Group.

The R32C/118 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.

The internal ROM is mapped to the end of the memory map with the ending address fixed at FFFFFFFFh.

Therefore, the 1-Mbyte internal ROM is mapped from FFF00000h to FFFFFFFFh.

The fixed interrupt vector table which contains each start address of interrupt handlers is mapped from

FFFFFFDCh to FFFFFFFFh.

The internal RAM is mapped to the beginning of the memory map with the starting address fixed at

00000400h. Therefore, the 63-Kbyte internal RAM is mapped from 00000400h to 0000FFFFh. Besides

being used for data storage, the internal RAM functions as a stack(s) for subroutines and/or interrupt

handlers.

Special Function Registers (SFRs), which are control registers for peripheral functions, are mapped from

00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved.

No access is allowed.

In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should

not be accessed.

00000000h

SFR1

00000400h

Internal RAM

XXXXXXXXh

Capacity XXXXXXXXh

40 Kbytes 0000A400h

48 Kbytes 0000C400h

63 Kbytes 00010000h

Reserved

00040000h

00050000h

00060000h

SFR2

Reserved

Internal ROM

(Data space) ⁽¹⁾

00062000h

00080000h

Internal ROM

Reserved

Capacity YYYYYYYYh

384 Kbytes FFFA0000h

512 Kbytes FFF80000h

640 Kbytes FFF60000h

768 Kbytes FFF40000h

FFFFFFDCh

Undefined instruction

Overflow

External space ⁽²⁾

BRK instruction

Reserved

FFE00000h

Reserved

Watchdog timer ⁽⁵⁾

Reserved ⁽³⁾

1 Mbyte

FFF00000h

Reserved

YYYYYYYYh

FFFFFFFFh

NMI

Internal ROM ⁽⁴⁾

Reset

FFFFFFFFh

Notes:

1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version.

2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h

to FDFFFFFFh are inaccessible.

3. This space is reserved in memory expansion mode. It can be external space in microprocessor mode.

4. This space can be used in single-chip mode or memory expansion mode. It can be external space in

microprocessor mode.

5. The watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low

voltage detection interrupt.

Figure 3.1

Memory Map

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Page 27 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List

(1) to Table 4.53 SFR List (53) list the SFR details.

Table 4.1

Address

000000h

000001h

000002h

000003h

SFR List (1)

Register

Symbol

Reset Value

000004h Clock Control Register

000005h

CCR

0001 1000b

000006h Flash Memory Control Register

000007h Protect Release Register

FMCR

PRR

0000 0001b

00h

000008h

000009h

00000Ah

00000Bh

00000Ch

00000Dh

00000Eh

00000Fh

000010h External Bus Control Register 3/Flash Memory Rewrite Bus

EBC3/FEBC3

CB23

0000h

00h

Control Register 3

000011h

000012h Chip Selects 2 and 3 Boundary Setting Register

000013h

000014h External Bus Control Register 2

000015h

000016h Chip Selects 1 and 2 Boundary Setting Register

EBC2

0000h

00h

CB12

000017h

000018h External Bus Control Register 1

000019h

00001Ah Chip selects 0 and 1 Boundary Setting Register

00001Bh

EBC1

0000h

00h

CB01

00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus

EBC0/FEBC0

PBC

0000h

0504h

Control Register 0

00001Dh

00001Eh Peripheral Bus Control Register

00001Fh

000020h to

00005Fh

X: Undefined

Blanks are reserved. No access is allowed.

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R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.2

Address

SFR List (2)

Register

Symbol

Reset Value

000060h

000061h Timer B5 Interrupt Control Register

000062h UART5 Transmit/NACK Interrupt Control Register

TB5IC

S5TIC

S2RIC/I2CLIC

XXXX X000b

UART2 Receive/ACK Interrupt Control Register/I²C Bus Line

Interrupt Control Register

000063h

000064h UART6 Transmit/NACK Interrupt Control Register

000065h UART3 Receive/ACK Interrupt Control Register

000066h UART5/6 Bus Collision, Start Condition/Stop Condition

Detection Interrupt Control Register

S6TIC

S3RIC

BCN5IC/BCN6IC

XXXX X000b

000067h UART4 Receive/ACK Interrupt Control Register

000068h DMA0 Transfer Complete Interrupt Control Register

000069h UART0/3 Bus Collision, Start Condition/Stop Condition

Detection Interrupt Control Register

S4RIC

DM0IC

BCN0IC/BCN3IC

XXXX X000b

00006Ah DMA2 Transfer Complete Interrupt Control Register

00006Bh A/D Converter 0 Convert Completion Interrupt Control Register

00006Ch Timer A0 Interrupt Control Register

00006Dh Intelligent I/O Interrupt Control Register 0

00006Eh Timer A2 Interrupt Control Register

00006Fh Intelligent I/O Interrupt Control Register 2

000070h Timer A4 Interrupt Control Register

000071h Intelligent I/O Interrupt Control Register 4

000072h UART0 Receive/ACK Interrupt Control Register

000073h Intelligent I/O Interrupt Control Register 6

000074h UART1 Receive/ACK Interrupt Control Register

000075h Intelligent I/O Interrupt Control Register 8

000076h Timer B1 Interrupt Control Register

000077h Intelligent I/O Interrupt Control Register 10

000078h Timer B3 Interrupt Control Register

000079h

DM2IC

AD0IC

TA0IC

IIO0IC

TA2IC

IIO2IC

TA4IC

IIO4IC

S0RIC

IIO6IC

S1RIC

IIO8IC

TB1IC

IIO10IC

TB3IC

XXXX X000b

00007Ah INT5 Interrupt Control Register

00007Bh CAN0 Wake-up Interrupt Control Register

00007Ch INT3 Interrupt Control Register

INT5IC

C0WIC

INT3IC

XX00 X000b

XXXX X000b

XX00 X000b

00007Dh

00007Eh INT1 Interrupt Control Register

00007Fh

000080h

INT1IC

XX00 X000b

XXXX X000b

UART2 Transmit/NACK Interrupt Control Register/I²C-Bus

Interrupt Control Register

000081h

S2TIC/I2CIC

000082h UART5 Receive/ACK Interrupt Control Register

000083h UART3 Transmit/NACK Interrupt Control Register

000084h UART6 Receive/ACK Interrupt Control Register

000085h UART4 Transmit/NACK Interrupt Control Register

000086h

S5RIC

S3TIC

S6RIC

S4TIC

XXXX X000b

000087h UART2 Bus Collision, Start Condition/Stop Condition Detection BCN2IC

XXXX X000b

Interrupt Control Register

X: Undefined

Blanks are reserved. No access is allowed.

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Page 29 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.3

SFR List (3)

Address

Register

Symbol

DM1IC

BCN1IC/BCN4IC

Reset Value

XXXX X000b

000088h DMA1 Transfer Complete Interrupt Control Register

000089h UART1/4 Bus Collision, Start Condition/Stop Condition

Detection Interrupt Control Register

00008Ah DMA3 Transfer Complete Interrupt Control Register

00008Bh Key Input Interrupt Control Register

00008Ch Timer A1 Interrupt Control Register

00008Dh Intelligent I/O Interrupt Control Register 1

00008Eh Timer A3 Interrupt Control Register

00008Fh Intelligent I/O Interrupt Control Register 3

000090h UART0 Transmit/NACK Interrupt Control Register

000091h Intelligent I/O Interrupt Control Register 5

000092h UART1 Transmit/NACK Interrupt Control Register

000093h Intelligent I/O Interrupt Control Register 7

000094h Timer B0 Interrupt Control Register

000095h Intelligent I/O Interrupt Control Register 9

000096h Timer B2 Interrupt Control Register

000097h Intelligent I/O Interrupt Control Register 11

000098h Timer B4 Interrupt Control Register

000099h

DM3IC

KUPIC

TA1IC

IIO1IC

TA3IC

IIO3IC

S0TIC

IIO5IC

S1TIC

IIO7IC

TB0IC

IIO9IC

TB2IC

IIO11IC

TB4IC

XXXX X000b

00009Ah INT4 Interrupt Control Register

00009Bh CAN1 Wake-up Interrupt Control Register

00009Ch INT2 Interrupt Control Register

00009Dh

INT4IC

C1WIC

INT2IC

XX00 X000b

XXXX X000b

XX00 X000b

00009Eh INT0 Interrupt Control Register

00009Fh

INT0IC

XX00 X000b

0000A0h Intelligent I/O Interrupt Request Register 0

0000A1h Intelligent I/O Interrupt Request Register 1

0000A2h Intelligent I/O Interrupt Request Register 2

0000A3h Intelligent I/O Interrupt Request Register 3

0000A4h Intelligent I/O Interrupt Request Register 4

0000A5h Intelligent I/O Interrupt Request Register 5

0000A6h Intelligent I/O Interrupt Request Register 6

0000A7h Intelligent I/O Interrupt Request Register 7

0000A8h Intelligent I/O Interrupt Request Register 8

0000A9h Intelligent I/O Interrupt Request Register 9

0000AAh Intelligent I/O Interrupt Request Register 10

0000ABh Intelligent I/O Interrupt Request Register 11

0000ACh

IIO0IR

IIO1IR

IIO2IR

IIO3IR

IIO4IR

IIO5IR

IIO6IR

IIO7IR

IIO8IR

IIO9IR

IIO10IR

IIO11IR

0000 0XX1b

0000 0X01b

0000 XXX1b

000X 0XX1b

X00X 0XX1b

XX0X 0XX1b

0X00 0XX1b

0000ADh

0000AEh

0000AFh

X: Undefined

Blanks are reserved. No access is allowed.

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R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.4

SFR List (4)

Address

Register

Symbol

Reset Value

0000B0h Intelligent I/O Interrupt Enable Register 0

0000B1h Intelligent I/O Interrupt Enable Register 1

0000B2h Intelligent I/O Interrupt Enable Register 2

0000B3h Intelligent I/O Interrupt Enable Register 3

0000B4h Intelligent I/O Interrupt Enable Register 4

0000B5h Intelligent I/O Interrupt Enable Register 5

0000B6h Intelligent I/O Interrupt Enable Register 6

0000B7h Intelligent I/O Interrupt Enable Register 7

0000B8h Intelligent I/O Interrupt Enable Register 8

0000B9h Intelligent I/O Interrupt Enable Register 9

0000BAh Intelligent I/O Interrupt Enable Register 10

0000BBh Intelligent I/O Interrupt Enable Register 11

IIO0IE

IIO1IE

IIO2IE

IIO3IE

IIO4IE

IIO5IE

IIO6IE

IIO7IE

IIO8IE

IIO9IE

00h

IIO10IE

IIO11IE

0000BCh

0000BDh

0000BEh

0000BFh

0000C0h

0000C1h CAN0 Transmit Interrupt Control Register

0000C2h

0000C3h CAN0 Error Interrupt Control Register

0000C4h

C0TIC

C0EIC

C1RIC

XXXX X000b

0000C5h CAN1 Receive Interrupt Control Register

0000C6h

0000C7h

0000C8h

0000C9h

0000CAh

0000CBh

0000CCh

0000CDh

0000CEh

0000CFh

0000D0h CAN0 Transmit FIFO Interrupt Control Register

0000D1h

0000D2h CAN1 Transmit FIFO Interrupt Control Register

C0FTIC

C1FTIC

XXXX X000b

0000D3h

0000D4h

0000D5h

0000D6h

0000D7h

0000D8h

0000D9h

0000DAh

0000DBh

0000DCh

0000DDh UART7 Transmit Interrupt Control Register

0000DEh INT7 Interrupt Control Register

0000DFh UART8 Transmit Interrupt Control Register

X: Undefined

S7TIC

INT7IC

S8TIC

XXXX X000b

XX00 X000b

XXXX X000b

Blanks are reserved. No access is allowed.

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R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.5

Address

SFR List (5)

Register

Symbol

C0RIC

Reset Value

XXXX X000b

0000E0h

0000E1h CAN0 Receive Interrupt Control Register

0000E2h

0000E3h CAN1 Transmit Interrupt Control Register

0000E4h

0000E5h CAN1 Error Interrupt Control Register

C1TIC

C1EIC

XXXX X000b

0000E6h

0000E7h

0000E8h

0000E9h

0000EAh

0000EBh

0000ECh

0000EDh

0000EEh

0000EFh

0000F0h CAN0 Receive FIFO Interrupt Control Register

0000F1h

0000F2h CAN1 Receive FIFO Interrupt Control Register

C0FRIC

C1FRIC

XXXX X000b

0000F3h

0000F4h

0000F5h

0000F6h

0000F7h

0000F8h

0000F9h

0000FAh

0000FBh

0000FCh INT8 Interrupt Control Register

0000FDh UART7 Receive Interrupt Control Register

0000FEh INT6 Interrupt Control Register

0000FFh UART8 Receive Interrupt Control Register

INT8IC

S7RIC

INT6IC

S8RIC

XX00 X000b

XXXX X000b

XX00 X000b

XXXX X000b

XXXXh

000100h Group 1 Time Measurement/Waveform Generation Register 0 G1TM0/G1PO0

000101h

000102h Group 1 Time Measurement/Waveform Generation Register 1 G1TM1/G1PO1

000103h

000104h Group 1 Time Measurement/Waveform Generation Register 2 G1TM2/G1PO2

000105h

XXXXh

000106h Group 1 Time Measurement/Waveform Generation Register 3 G1TM3/G1PO3

000107h

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 32 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.6

SFR List (6)

Address

Register

Symbol

Reset Value

XXXXh

000108h Group 1 Time Measurement/Waveform Generation Register 4 G1TM4/G1PO4

000109h

00010Ah Group 1 Time Measurement/Waveform Generation Register 5 G1TM5/G1PO5

00010Bh

00010Ch Group 1 Time Measurement/Waveform Generation Register 6 G1TM6/G1PO6

00010Dh

00010Eh Group 1 Time Measurement/Waveform Generation Register 7 G1TM7/G1PO7

00010Fh

XXXXh

000110h Group 1 Waveform Generation Control Register 0

000111h Group 1 Waveform Generation Control Register 1

000112h Group 1 Waveform Generation Control Register 2

000113h Group 1 Waveform Generation Control Register 3

000114h Group 1 Waveform Generation Control Register 4

000115h Group 1 Waveform Generation Control Register 5

000116h Group 1 Waveform Generation Control Register 6

000117h Group 1 Waveform Generation Control Register 7

000118h Group 1 Time Measurement Control Register 0

000119h Group 1 Time Measurement Control Register 1

00011Ah Group 1 Time Measurement Control Register 2

00011Bh Group 1 Time Measurement Control Register 3

00011Ch Group 1 Time Measurement Control Register 4

00011Dh Group 1 Time Measurement Control Register 5

00011Eh Group 1 Time Measurement Control Register 6

00011Fh Group 1 Time Measurement Control Register 7

000120h Group 1 Base Timer Register

000121h

G1POCR0

G1POCR1

G1POCR2

G1POCR3

G1POCR4

G1POCR5

G1POCR6

G1POCR7

G1TMCR0

G1TMCR1

G1TMCR2

G1TMCR3

G1TMCR4

G1TMCR5

G1TMCR6

G1TMCR7

G1BT

0000 X000b

0X00 X000b

00h

XXXXh

000122h Group 1 Base Timer Control Register 0

000123h Group 1 Base Timer Control Register 1

000124h Group 1 Timer Measurement Prescaler Register 6

000125h Group 1 Timer Measurement Prescaler Register 7

000126h Group 1 Function Enable Register

000127h Group 1 Function Select Register

000128h

G1BCR0

G1BCR1

G1TPR6

G1TPR7

G1FE

00h

0000 0000b

00h

G1FS

00h

000129h

00012Ah

00012Bh

00012Ch

00012Dh

00012Eh

00012Fh

000130h to

00013Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 33 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.7

SFR List (7)

Address

Register

Symbol

G2PO0

Reset Value

XXXXh

000140h Group 2 Waveform Generation Register 0

000141h

000142h Group 2 Waveform Generation Register 1

000143h

000144h Group 2 Waveform Generation Register 2

000145h

000146h Group 2 Waveform Generation Register 3

000147h

000148h Group 2 Waveform Generation Register 4

000149h

00014Ah Group 2 Waveform Generation Register 5

00014Bh

00014Ch Group 2 Waveform Generation Register 6

00014Dh

G2PO1

G2PO2

G2PO3

G2PO4

G2PO5

G2PO6

G2PO7

XXXXh

00014Eh Group 2 Waveform Generation Register 7

00014Fh

000150h Group 2 Waveform Generation Control Register 0

000151h Group 2 Waveform Generation Control Register 1

000152h Group 2 Waveform Generation Control Register 2

000153h Group 2 Waveform Generation Control Register 3

000154h Group 2 Waveform Generation Control Register 4

000155h Group 2 Waveform Generation Control Register 5

000156h Group 2 Waveform Generation Control Register 6

000157h Group 2 Waveform Generation Control Register 7

G2POCR0

G2POCR1

G2POCR2

G2POCR3

G2POCR4

G2POCR5

G2POCR6

G2POCR7

0000 0000b

000158h

000159h

00015Ah

00015Bh

00015Ch

00015Dh

00015Eh

00015Fh

000160h Group 2 Base Timer Register

000161h

G2BT

XXXXh

000162h Group 2 Base Timer Control Register 0

000163h Group 2 Base Timer Control Register 1

000164h Base Timer Start Register

000165h

G2BCR0

G2BCR1

BTSR

00h

0000 0000b

XXXX 0000b

000166h Group 2 Function Enable Register

000167h Group 2 RTP Output Buffer Register

000168h

G2FE

G2RTP

00h

000169h

00016Ah Group 2 Serial Interface Mode Register

00016Bh Group 2 Serial Interface Control Register

00016Ch Group 2 SI/O Transmit Buffer Register

00016Dh

G2MR

G2CR

G2TB

00XX X000b

0000 X110b

XXXXh

00016Eh Group 2 SI/O Receive Buffer Register

00016Fh

G2RB

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 34 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.8

SFR List (8)

Address

Register

Symbol

Reset Value

XXXXh

000170h Group 2 IE Bus Address Register

IEAR

000171h

000172h Group 2 IE Bus Control Register

000173h Group 2 IE Bus Transmit Interrupt Source Detect Register

000174h Group 2 IE Bus Receive Interrupt Source Detect Register

IECR

IETIF

IERIF

00XX X000b

XXX0 0000b

000175h

000176h

000177h

000178h

000179h

00017Ah

00017Bh

00017Ch

00017Dh

00017Eh

00017Fh

000180h Group 0 Time Measurement/Waveform Generation Register 0 G0TM0/G0PO0

000181h

000182h Group 0 Time Measurement/Waveform Generation Register 1 G0TM1/G0PO1

000183h

000184h Group 0 Time Measurement/Waveform Generation Register 2 G0TM2/G0PO2

000185h

000186h Group 0 Time Measurement/Waveform Generation Register 3 G0TM3/G0PO3

000187h

000188h Group 0 Time Measurement/Waveform Generation Register 4 G0TM4/G0PO4

000189h

00018Ah Group 0 Time Measurement/Waveform Generation Register 5 G0TM5/G0PO5

00018Bh

00018Ch Group 0 Time Measurement/Waveform Generation Register 6 G0TM6/G0PO6

00018Dh

00018Eh Group 0 Time Measurement/Waveform Generation Register 7 G0TM7/G0PO7

00018Fh

XXXXh

000190h Group 0 Waveform Generation Control Register 0

000191h Group 0 Waveform Generation Control Register 1

000192h Group 0 Waveform Generation Control Register 2

000193h Group 0 Waveform Generation Control Register 3

000194h Group 0 Waveform Generation Control Register 4

000195h Group 0 Waveform Generation Control Register 5

000196h Group 0 Waveform Generation Control Register 6

000197h Group 0 Waveform Generation Control Register 7

000198h Group 0 Time Measurement Control Register 0

000199h Group 0 Time Measurement Control Register 1

00019Ah Group 0 Time Measurement Control Register 2

00019Bh Group 0 Time Measurement Control Register 3

00019Ch Group 0 Time Measurement Control Register 4

00019Dh Group 0 Time Measurement Control Register 5

00019Eh Group 0 Time Measurement Control Register 6

00019Fh Group 0 Time Measurement Control Register 7

X: Undefined

G0POCR0

G0POCR1

G0POCR2

G0POCR3

G0POCR4

G0POCR5

G0POCR6

G0POCR7

G0TMCR0

G0TMCR1

G0TMCR2

G0TMCR3

G0TMCR4

G0TMCR5

G0TMCR6

G0TMCR7

0000 X000b

0X00 X000b

00h

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 35 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.9

SFR List (9)

Address

Register

Symbol

Reset Value

XXXXh

0001A0h Group 0 Base Timer Register

G0BT

0001A1h

0001A2h Group 0 Base Timer Control Register 0

0001A3h Group 0 Base Timer Control Register 1

0001A4h Group 0 Timer Measurement Prescaler Register 6

0001A5h Group 0 Timer Measurement Prescaler Register 7

G0BCR0

G0BCR1

G0TPR6

G0TPR7

G0FE

00h

0000 0000b

00h

0001A6h Group 0 Function Enable Register

0001A7h Group 0 Function Select Register

G0FS

00h

0001A8h

0001A9h

0001AAh

0001ABh

0001ACh

0001ADh

0001AEh

0001AFh

0001B0h

0001B1h

0001B2h

0001B3h

0001B4h

0001B5h

0001B6h

0001B7h

0001B8h

0001B9h

0001BAh

0001BBh

0001BCh

0001BDh

0001BEh

0001BFh

0001C0h

0001C1h

0001C2h

0001C3h

0001C4h UART5 Special Mode Register 4

0001C5h UART5 Special Mode Register 3

0001C6h UART5 Special Mode Register 2

0001C7h UART5 Special Mode Register

0001C8h UART5 Transmit/Receive Mode Register

0001C9h UART5 Bit Rate Register

0001CAh UART5 Transmit Buffer Register

0001CBh

U5SMR4

U5SMR3

U5SMR2

U5SMR

U5MR

00h

XXh

XXXXh

U5BRG

U5TB

0001CCh UART5 Transmit/Receive Control Register 0

0001CDh UART5 Transmit/Receive Control Register 1

0001CEh UART5 Receive Buffer Register

0001CFh

U5C0

U5C1

U5RB

0000 1000b

0000 0010b

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 36 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.10

Address

SFR List (10)

Register

Symbol

Reset Value

0001D0h

0001D1h

0001D2h

0001D3h

0001D4h UART6 Special Mode Register 4

0001D5h UART6 Special Mode Register 3

0001D6h UART6 Special Mode Register 2

0001D7h UART6 Special Mode Register

0001D8h UART6 Transmit/Receive Mode Register

0001D9h UART6 Bit Rate Register

0001DAh UART6 Transmit Buffer Register

U6SMR4

00h

XXh

U6SMR3

U6SMR2

U6SMR

U6MR

U6BRG

U6TB

XXXXh

0001DBh

0001DCh UART6 Transmit/Receive Control Register 0

0001DDh UART6 Transmit/Receive Control Register 1

0001DEh UART6 Receive Buffer Register

U6C0

U6C1

U6RB

0000 1000b

0000 0010b

XXXXh

0001DFh

0001E0h UART7 Transmit/Receive Mode Register

0001E1h UART7 Bit Rate Register

0001E2h UART7 Transmit Buffer Register

U7MR

U7BRG

U7TB

00h

XXh

XXXXh

0001E3h

0001E4h UART7 Transmit/Receive Control Register 0

0001E5h UART7 Transmit/Receive Control Register 1

0001E6h UART7 Receive Buffer Register

U7C0

U7C1

U7RB

00X0 1000b

XXXX 0010b

XXXXh

0001E7h

0001E8h UART8 Transmit/Receive Mode Register

0001E9h UART8 Bit Rate Register

0001EAh UART8 Transmit Buffer Register

U8MR

U8BRG

U8TB

00h

XXh

XXXXh

0001EBh

0001ECh UART8 Transmit/Receive Control Register 0

0001EDh UART8 Transmit/Receive Control Register 1

0001EEh UART8 Receive Buffer Register

U8C0

U8C1

U8RB

00X0 1000b

XXXX 0010b

XXXXh

0001EFh

0001F0h UART7, UART8 Transmit/Receive Control Register 2

U78CON

X000 0000b

0001F1h

0001F2h

0001F3h

0001F4h

0001F5h

0001F6h

0001F7h

0001F8h

0001F9h

0001FAh

0001FBh

0001FCh

0001FDh

0001FEh

0001FFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 37 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.11

SFR List (11)

Address

000200h to

0002BFh

Register

Symbol

Reset Value

0002C0h X0 Register/Y0 Register

0002C1h

X0R/Y0R

XXXXh

0002C2h X1 Register/Y1 Register

0002C3h

0002C4h X2 Register/Y2 Register

0002C5h

0002C6h X3 Register/Y3 Register

0002C7h

0002C8h X4 Register/Y4 Register

0002C9h

0002CAh X5 Register/Y5 Register

0002CBh

0002CCh X6 Register/Y6 Register

0002CDh

0002CEh X7 Register/Y7 Register

0002CFh

0002D0h X8 Register/Y8 Register

0002D1h

0002D2h X9 Register/Y9 Register

0002D3h

0002D4h X10 Register/Y10 Register

0002D5h

0002D6h X11 Register/Y11 Register

0002D7h

0002D8h X12 Register/Y12 Register

0002D9h

0002DAh X13 Register/Y13 Register

0002DBh

0002DCh X14 Register/Y14 Register

0002DDh

0002DEh X15 Register/Y15 Register

0002DFh

0002E0h XY Control Register

0002E1h

X1R/Y1R

X2R/Y2R

X3R/Y3R

X4R/Y4R

X5R/Y5R

X6R/Y6R

X7R/Y7R

X8R/Y8R

X9R/Y9R

X10R/Y10R

X11R/Y11R

X12R/Y12R

X13R/Y13R

X14R/Y14R

X15R/Y15R

XYC

XXXXh

XXXX XX00b

0002E2h

0002E3h

0002E4h UART1 Special Mode Register 4

0002E5h UART1 Special Mode Register 3

0002E6h UART1 Special Mode Register 2

0002E7h UART1 Special Mode Register

0002E8h UART1 Transmit/Receive Mode Register

0002E9h UART1 Bit Rate Register

0002EAh UART1 Transmit Buffer Register

0002EBh

U1SMR4

U1SMR3

U1SMR2

U1SMR

U1MR

00h

XXh

XXXXh

U1BRG

U1TB

0002ECh UART1 Transmit/Receive Control Register 0

0002EDh UART1 Transmit/Receive Control Register 1

0002EEh UART1 Receive Buffer Register

0002EFh

U1C0

U1C1

U1RB

0000 1000b

0000 0010b

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 38 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.12

Address

SFR List (12)

Register

Symbol

Reset Value

0002F0h

0002F1h

0002F2h

0002F3h

0002F4h UART4 Special Mode Register 4

0002F5h UART4 Special Mode Register 3

0002F6h UART4 Special Mode Register 2

0002F7h UART4 Special Mode Register

0002F8h UART4 Transmit/Receive Mode Register

0002F9h UART4 Bit Rate Register

0002FAh UART4 Transmit Buffer Register

0002FBh

U4SMR4

00h

XXh

U4SMR3

U4SMR2

U4SMR

U4MR

U4BRG

U4TB

XXXXh

0002FCh UART4 Transmit/Receive Control Register 0

0002FDh UART4 Transmit/Receive Control Register 1

0002FEh UART4 Receive Buffer Register

0002FFh

U4C0

U4C1

U4RB

0000 1000b

0000 0010b

XXXXh

000300h Count Start Register for Timers B3, B4 and B5

000301h

000302h Timer A1-1 Register

000303h

000304h Timer A2-1 Register

000305h

000306h Timer A4-1 Register

000307h

TBSR

TA11

TA21

TA41

000X XXXXb

XXXXh

000308h Three-phase PWM Control Register 0

000309h Three-phase PWM Control Register 1

00030Ah Three-phase Output Buffer Register 0

00030Bh Three-phase Output Buffer Register 1

00030Ch Dead Time Timer

00030Dh Timer B2 Interrupt Generating Frequency Set Counter

00030Eh

INVC0

INVC1

IDB0

IDB1

DTT

00h

XX11 1111b

XXh

ICTB2

XXh

00030Fh

000310h Timer B3 Register

000311h

000312h Timer B4 Register

000313h

000314h Timer B5 Register

000315h

TB3

TB4

TB5

XXXXh

000316h

000317h

000318h

000319h

00031Ah

00031Bh Timer B3 Mode Register

00031Ch Timer B4 Mode Register

00031Dh Timer B5 Mode Register

00031Eh

TB3MR

TB4MR

TB5MR

00XX 0000b

00031Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 39 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.13

Address

SFR List (13)

Register

Symbol

Reset Value

000320h

000321h

000322h

000323h

000324h UART3 Special Mode Register 4

000325h UART3 Special Mode Register 3

000326h UART3 Special Mode Register 2

000327h UART3 Special Mode Register

000328h UART3 Transmit/Receive Mode Register

000329h UART3 Bit Rate Register

00032Ah UART3 Transmit Buffer Register

00032Bh

U3SMR4

00h

XXh

U3SMR3

U3SMR2

U3SMR

U3MR

U3BRG

U3TB

XXXXh

00032Ch UART3 Transmit/Receive Control Register 0

00032Dh UART3 Transmit/Receive Control Register 1

00032Eh UART3 Receive Buffer Register

00032Fh

U3C0

U3C1

U3RB

0000 1000b

0000 0010b

XXXXh

000330h

000331h

000332h

000333h

000334h UART2 Special Mode Register 4

000335h UART2 Special Mode Register 3

000336h UART2 Special Mode Register 2

000337h UART2 Special Mode Register

000338h UART2 Transmission/Receive Mode Register

000339h UART2 Bit Rate Register

00033Ah UART2 Transmit Buffer Register

00033Bh

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

00h

XXh

XXXXh

U2BRG

U2TB

00033Ch UART2 Transmit/Receive Control Register 0

00033Dh UART2 Transmit/Receive Control Register 1

00033Eh UART2 Receive Buffer Register

00033Fh

U2C0

U2C1

U2RB

0000 1000b

0000 0010b

XXXXh

000340h Count Start Register

000341h Clock Prescaler Reset Register

000342h One-shot Start Register

000343h Trigger Select Register

000344h Increment/Decrement Counting Select Register

000345h

TABSR

CPSRF

ONSF

TRGSR

UDF

00h

0XXX XXXXb

00h

0000 0000b

000346h Timer A0 Register

000347h

000348h Timer A1 Register

000349h

00034Ah Timer A2 Register

00034Bh

00034Ch Timer A3 Register

00034Dh

00034Eh Timer A4 Register

00034Fh

TA0

TA1

TA2

TA3

TA4

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 40 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.14

SFR List (14)

Address

000350h Timer B0 Register

000351h

000352h Timer B1 Register

000353h

000354h Timer B2 Register

000355h

Register

Symbol

Reset Value

XXXXh

TB0

TB1

TB2

XXXXh

000356h Timer A0 Mode Register

000357h Timer A1 Mode Register

000358h Timer A2 Mode Register

000359h Timer A3 Mode Register

00035Ah Timer A4 Mode Register

00035Bh Timer B0 Mode Register

00035Ch Timer B1 Mode Register

00035Dh Timer B2 Mode Register

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

TCSPR

0000 0000b

00XX 0000b

XXXX XXX0b

0000 0000b

00035Eh Timer B2 Special Mode Register

00035Fh Count Source Prescaler Register

000360h

000361h

000362h

000363h

000364h UART0 Special Mode Register 4

000365h UART0 Special Mode Register 3

000366h UART0 Special Mode Register 2

000367h UART0 Special Mode Register

U0SMR4

U0SMR3

U0SMR2

U0SMR

U0MR

00h

000368h UART0 Transmit/Receive Mode Register

00h

000369h UART0 Bit Rate Register

00036Ah UART0 Transmit Buffer Register

U0BRG

U0TB

XXh

XXXXh

00036Bh

00036Ch UART0 Transmit/Receive Control Register 0

00036Dh UART0 Transmit/Receive Control Register 1

00036Eh UART0 Receive Buffer Register

U0C0

U0C1

U0RB

0000 1000b

0000 0010b

XXXXh

00036Fh

000370h

000371h

000372h

000373h

000374h

000375h

000376h

000377h

000378h

000379h

00037Ah

00037Bh

00037Ch CRC Data Register

00037Dh

00037Eh CRC Input Register

00037Fh

CRCD

CRCIN

XXXXh

XXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 41 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.15

SFR List (15)

Address

000380h A/D0 Register 0

000381h

000382h A/D0 Register 1

000383h

000384h A/D0 Register 2

000385h

000386h A/D0 Register 3

000387h

000388h A/D0 Register 4

000389h

00038Ah A/D0 Register 5

00038Bh

00038Ch A/D0 Register 6

00038Dh

Register

Symbol

Reset Value

00XXh

AD00

AD01

AD02

AD03

AD04

AD05

AD06

AD07

00XXh

00038Eh A/D0 Register 7

00038Fh

000390h

000391h

000392h A/D0 Control Register 4

000393h

AD0CON4

XXXX 00XXb

000394h A/D0 Control Register 2

000395h A/D0 Control Register 3

000396h A/D0 Control Register 0

000397h A/D0 Control Register 1

000398h D/A Register 0

000399h

AD0CON2

AD0CON3

AD0CON0

AD0CON1

DA0

X00X X000b

XXXX X000b

00h

XXh

00039Ah D/A Register 1

00039Bh

DA1

XXh

00039Ch D/A Control Register

00039Dh

DACON

XXXX XX00b

00039Eh

00039Fh

0003A0h

0003A1h

0003A2h

0003A3h

0003A4h

0003A5h

0003A6h

0003A7h

0003A8h

0003A9h

0003AAh

0003ABh

0003ACh

0003ADh

0003AEh

0003AFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 42 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.16

Address

SFR List (16)

Register

Symbol

Reset Value

0003B0h

0003B1h

0003B2h

0003B3h

0003B4h

0003B5h

0003B6h

0003B7h

0003B8h

0003B9h

0003BAh

0003BBh

0003BCh

0003BDh

0003BEh

0003BFh

0003C0h Port P0 Register

0003C1h Port P1 Register

P0

P1

XXh

0003C2h Port P0 Direction Register

0003C3h Port P1 Direction Register

0003C4h Port P2 Register

PD0

PD1

P2

0000 0000b

XXh

0003C5h Port P3 Register

P3

XXh

0003C6h Port P2 Direction Register

0003C7h Port P3 Direction Register

0003C8h Port P4 Register

PD2

PD3

P4

0000 0000b

XXh

0003C9h Port P5 Register

P5

XXh

0003CAh Port P4 Direction Register

0003CBh Port P5 Direction Register

0003CCh Port P6 Register

PD4

PD5

P6

0000 0000b

XXh

0003CDh Port P7 Register

P7

XXh

0003CEh Port P6 Direction Register

0003CFh Port P7 Direction Register

0003D0h Port P8 Register

PD6

PD7

P8

0000 0000b

XXh

0003D1h Port P9 Register

P9

XXh

0003D2h Port P8 Direction Register

0003D3h Port P9 Direction Register

0003D4h Port P10 Register

PD8

PD9

P10

P11

PD10

PD11

P12

P13

PD12

PD13

P14

P15

PD14

PD15

00X0 0000b

0000 0000b

XXh

0003D5h Port P11 Register

XXh

0003D6h Port P10 Direction Register

0003D7h Port P11 Direction Register

0003D8h Port P12 Register

0000 0000b

XXX0 0000b

XXh

0003D9h Port P13 Register

XXh

0003DAh Port P12 Direction Register

0003DBh Port P13 Direction Register

0003DCh Port P14 Register

0000 0000b

XXh

0003DDh Port P15 Register

XXh

0003DEh Port P14 Direction Register

0003DFh Port P15 Direction Register

X: Undefined

X000 0000b

0000 0000b

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 43 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.17

SFR List (17)

Address

0003E0h

0003E1h

0003E2h

0003E3h

0003E4h

0003E5h

0003E6h

0003E7h

0003E8h

0003E9h

0003EAh

0003EBh

0003ECh

0003EDh

0003EEh

0003EFh

Register

Symbol

Reset Value

0003F0h Pull-up Control Register 0

0003F1h Pull-up Control Register 1

0003F2h Pull-up Control Register 2

0003F3h Pull-up Control Register 3

PUR0

PUR1

PUR2

PUR3

PUR4

0000 0000b

XXXX X0XXb

000X XXXXb

0000 0000b

XXXX 0000b

0003F4h Pull-up Control Register 4

0003F5h

0003F6h

0003F7h

0003F8h

0003F9h

0003FAh

0003FBh

0003FCh

0003FDh

0003FEh

0003FFh Port Control Register

PCR

0XXX XXX0b

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 44 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.18

SFR List (18)

Address

Register

Symbol

Reset Value

0X01 XX00b

040000h Flash Memory Control Register 0

FMR0

040001h Flash Memory Status Register 0

FMSR0

1000 0000b

040002h

040003h

040004h

040005h

040006h

040007h

040008h Flash Register Protection Unlock Register 0

FPR0

00h

040009h Flash Memory Control Register 1

04000Ah Block Protect Bit Monitor Register 0

FMR1

FBPM0

FBPM1

0000 0010b

??X? ????b ⁽¹⁾

XXX? ????b ⁽¹⁾

04000Bh Block Protect Bit Monitor Register 1

04000Ch

04000Dh

04000Eh

04000Fh

040010h

???? ????b ⁽¹⁾

040011h Block Protect Bit Monitor Register 2

FBPM2

040012h

040013h

040014h

040015h

040016h

040017h

040018h

040019h

04001Ah

04001Bh

04001Ch

04001Dh

04001Eh

04001Fh

040020h PLL Control Register 0

040021h PLL Control Register 1

PLC0

PLC1

0000 0001b

0001 1111b

040022h

040023h

040024h

040025h

040026h

040027h

040028h

040029h

04002Ah

04002Bh

04002Ch

04002Dh

04002Eh

04002Fh

X: Undefined

Blanks are reserved. No access is allowed.

Note:

1. The status of protect bit of each block in flash memory is reflected.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 45 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.19

SFR List (19)

Address

040030h to

04003Fh

040040h

040041h

040042h

040043h

Register

Symbol

Reset Value

Processor Mode Register 0 ⁽¹⁾

040044h

PM0

1000 0000b

(CNVSS pin = Low)

0000 0011b

(CNVSS pin = High)

040045h

040046h System Clock Control Register 0

040047h System Clock Control Register 1

040048h Processor Mode Register 3

CM0

CM1

PM3

0000 1000b

0010 0000b

00h

040049h

04004Ah Protect Register

PRCR

XXXX X000b

04004Bh

04004Ch Protect Register 3

04004Dh Oscillator Stop Detection Register

PRCR3

CM2

0000 0000b

00h

04004Eh

04004Fh

040050h

040051h

040052h

040053h Processor Mode Register 2

PM2

00h

040054h Chip Select Output Pin Setting Register 0

040055h Chip Select Output Pin Setting Register 1

040056h Chip Select Output Pin Setting Register 2

CSOP0

CSOP1

CSOP2

1000 XXXXb

01X0 XXXXb

XXXX 0000b

040057h

040058h

040059h

04005Ah Low Speed Mode Clock Control Register

CM3

XXXX XX00b

04005Bh

04005Ch

04005Dh

04005Eh

04005Fh

040060h Voltage Regulator Control Register

040061h

040062h Low Voltage Detector Control Register

040063h

VRCR

LVDC

DVCR

0000 0000b

0000 XX00b

0000 XXXXb

040064h Detection Voltage Configuration Register

040065h

040066h

040067h

040068h to

040093h

X: Undefined

Blanks are reserved. No access is allowed.

Note:

1. The value in the PM0 register remains unchanged even after a software reset or watchdog timer reset.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 46 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.20

SFR List (20)

Address

040094h

040095h

040096h

Register

Symbol

Reset Value

040097h Three-phase Output Buffer Control Register

040098h Input Function Select Register 0

040099h Input Function Select Register 1

04009Ah Input Function Select Register 2

04009Bh Input Function Select Register 3

04009Ch

IOBC

IFS0

IFS1

IFS2

IFS3

0XXX XXXXb

X000 0000b

XXXX X0X0b

0000 00X0b

XXXX XX00b

04009Dh

04009Eh

04009Fh

0400A0h Port P0_0 Function Select Register

0400A1h Port P1_0 Function Select Register

0400A2h Port P0_1 Function Select Register

0400A3h Port P1_1 Function Select Register

0400A4h Port P0_2 Function Select Register

0400A5h Port P1_2 Function Select Register

0400A6h Port P0_3 Function Select Register

0400A7h Port P1_3 Function Select Register

0400A8h Port P0_4 Function Select Register

0400A9h Port P1_4 Function Select Register

0400AAh Port P0_5 Function Select Register

0400ABh Port P1_5 Function Select Register

0400ACh Port P0_6 Function Select Register

0400ADh Port P1_6 Function Select Register

0400AEh Port P0_7 Function Select Register

0400AFh Port P1_7 Function Select Register

0400B0h Port P2_0 Function Select Register

0400B1h Port P3_0 Function Select Register

0400B2h Port P2_1 Function Select Register

0400B3h Port P3_1 Function Select Register

0400B4h Port P2_2 Function Select Register

0400B5h Port P3_2 Function Select Register

0400B6h Port P2_3 Function Select Register

0400B7h Port P3_3 Function Select Register

0400B8h Port P2_4 Function Select Register

0400B9h Port P3_4 Function Select Register

0400BAh Port P2_5 Function Select Register

0400BBh Port P3_5 Function Select Register

0400BCh Port P2_6 Function Select Register

0400BDh Port P3_6 Function Select Register

0400BEh Port P2_7 Function Select Register

0400BFh Port P3_7 Function Select Register

X: Undefined

P0_0S

P1_0S

P0_1S

P1_1S

P0_2S

P1_2S

P0_3S

P1_3S

P0_4S

P1_4S

P0_5S

P1_5S

P0_6S

P1_6S

P0_7S

P1_7S

P2_0S

P3_0S

P2_1S

P3_1S

P2_2S

P3_2S

P2_3S

P3_3S

P2_4S

P3_4S

P2_5S

P3_5S

P2_6S

P3_6S

P2_7S

P3_7S

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 47 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.21

SFR List (21)

Address

Register

Symbol

P4_0S

Reset Value

X0XX X000b

0400C0h Port P4_0 Function Select Register

0400C1h Port P5_0 Function Select Register

0400C2h Port P4_1 Function Select Register

0400C3h Port P5_1 Function Select Register

0400C4h Port P4_2 Function Select Register

0400C5h Port P5_2 Function Select Register

0400C6h Port P4_3 Function Select Register

0400C7h Port P5_3 Function Select Register

0400C8h Port P4_4 Function Select Register

0400C9h Port P5_4 Function Select Register

0400CAh Port P4_5 Function Select Register

0400CBh Port P5_5 Function Select Register

0400CCh Port P4_6 Function Select Register

0400CDh Port P5_6 Function Select Register

0400CEh Port P4_7 Function Select Register

0400CFh Port P5_7 Function Select Register

0400D0h Port P6_0 Function Select Register

0400D1h Port P7_0 Function Select Register

0400D2h Port P6_1 Function Select Register

0400D3h Port P7_1 Function Select Register

0400D4h Port P6_2 Function Select Register

0400D5h Port P7_2 Function Select Register

0400D6h Port P6_3 Function Select Register

0400D7h Port P7_3 Function Select Register

0400D8h Port P6_4 Function Select Register

0400D9h Port P7_4 Function Select Register

0400DAh Port P6_5 Function Select Register

0400DBh Port P7_5 Function Select Register

0400DCh Port P6_6 Function Select Register

0400DDh Port P7_6 Function Select Register

0400DEh Port P6_7 Function Select Register

0400DFh Port P7_7 Function Select Register

0400E0h Port P8_0 Function Select Register

0400E1h Port P9_0 Function Select Register

0400E2h Port P8_1 Function Select Register

0400E3h Port P9_1 Function Select Register

0400E4h Port P8_2 Function Select Register

0400E5h Port P9_2 Function Select Register

0400E6h Port P8_3 Function Select Register

0400E7h Port P9_3 Function Select Register

0400E8h Port P8_4 Function Select Register

0400E9h Port P9_4 Function Select Register

0400EAh

P5_0S

P4_1S

P5_1S

P4_2S

P5_2S

P4_3S

P5_3S

P4_4S

P5_4S

P4_5S

P5_5S

P4_6S

P5_6S

P4_7S

P5_7S

P6_0S

P7_0S

P6_1S

P7_1S

P6_2S

P7_2S

P6_3S

P7_3S

P6_4S

P7_4S

P6_5S

P7_5S

P6_6S

P7_6S

P6_7S

P7_7S

P8_0S

P9_0S

P8_1S

P9_1S

P8_2S

P9_2S

P8_3S

P9_3S

P8_4S

P9_4S

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

00XX X000b

XXXX X000b

00XX X000b

0400EBh Port P9_5 Function Select Register

0400ECh Port P8_6 Function Select Register

0400EDh Port P9_6 Function Select Register

0400EEh Port P8_7 Function Select Register

0400EFh Port P9_7 Function Select Register

X: Undefined

P9_5S

P8_6S

P9_6S

P8_7S

P9_7S

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

X0XX X000b

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 48 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.22

SFR List (22)

Address

Register

Symbol

P10_0S

Reset Value

0XXX X000b

0400F0h Port P10_0 Function Select Register

0400F1h Port P11_0 Function Select Register

0400F2h Port P10_1 Function Select Register

0400F3h Port P11_1 Function Select Register

0400F4h Port P10_2 Function Select Register

0400F5h Port P11_2 Function Select Register

0400F6h Port P10_3 Function Select Register

0400F7h Port P11_3 Function Select Register

0400F8h Port P10_4 Function Select Register

0400F9h Port P11_4 Function Select Register

0400FAh Port P10_5 Function Select Register

0400FBh

P11_0S

P10_1S

P11_1S

P10_2S

P11_2S

P10_3S

P11_3S

P10_4S

P11_4S

P10_5S

X0XX X000b

0XXX X000b

X0XX X000b

0XXX X000b

X0XX X000b

0XXX X000b

X0XX X000b

0XXX X000b

XXXX X000b

0XXX X000b

0400FCh Port P10_6 Function Select Register

0400FDh

0400FEh Port P10_7 Function Select Register

0400FFh

P10_6S

P10_7S

0XXX X000b

040100h Port P12_0 Function Select Register

040101h Port P13_0 Function Select Register

040102h Port P12_1 Function Select Register

040103h Port P13_1 Function Select Register

040104h Port P12_2 Function Select Register

040105h Port P13_2 Function Select Register

040106h Port P12_3 Function Select Register

040107h Port P13_3 Function Select Register

040108h Port P12_4 Function Select Register

040109h Port P13_4 Function Select Register

04010Ah Port P12_5 Function Select Register

04010Bh Port P13_5 Function Select Register

04010Ch Port P12_6 Function Select Register

04010Dh Port P13_6 Function Select Register

04010Eh Port P12_7 Function Select Register

04010Fh Port P13_7 Function Select Register

040110h

P12_0S

P13_0S

P12_1S

P13_1S

P12_2S

P13_2S

P12_3S

P13_3S

P12_4S

P13_4S

P12_5S

P13_5S

P12_6S

P13_6S

P12_7S

P13_7S

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

040111h Port P15_0 Function Select Register

040112h

040113h Port P15_1 Function Select Register

040114h

P15_0S

P15_1S

00XX X000b

040115h Port P15_2 Function Select Register

040116h Port P14_3 Function Select Register

040117h Port P15_3 Function Select Register

040118h Port P14_4 Function Select Register

040119h Port P15_4 Function Select Register

04011Ah Port P14_5 Function Select Register

04011Bh Port P15_5 Function Select Register

04011Ch Port P14_6 Function Select Register

04011Dh Port P15_6 Function Select Register

04011Eh

P15_2S

P14_3S

P15_3S

P14_4S

P15_4S

P14_5S

P15_5S

P14_6S

P15_6S

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

04011Fh Port P15_7 Function Select Register

P15_7S

00XX X000b

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 49 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.23

SFR List (23)

Address

040120h to

04403Fh

044040h

044041h

044042h

044043h

044044h

044045h

044046h

044047h

044048h

044049h

04404Ah

04404Bh

04404Ch

04404Dh

Register

Symbol

Reset Value

04404Eh Watchdog Timer Start Register

04404Fh Watchdog Timer Control Register

WDTS

WDC

XXXX XXXXb

000X XXXXb

044050h

044051h

044052h

044053h

044054h

044055h

044056h

044057h

044058h

044059h

04405Ah

04405Bh

04405Ch

04405Dh

04405Eh

04405Fh Protect Register 2

PRCR2

0XXX XXXXb

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 50 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.24

Address

044060h

044061h

044062h

044063h

044064h

044065h

044066h

044067h

044068h

044069h

04406Ah

04406Bh

04406Ch

SFR List (24)

Register

Symbol

Reset Value

04406Dh External Interrupt Source Select Register 1

04406Eh

04406Fh External Interrupt Source Select Register 0

044070h DMA0 Request Source Select Register 2

044071h DMA1 Request Source Select Register 2

044072h DMA2 Request Source Select Register 2

044073h DMA3 Request Source Select Register 2

IFSR1

IFSR0

DM0SL2

DM1SL2

DM2SL2

DM3SL2

X0XX X000b

0000 0000b

XX00 0000b

044074h

044075h

044076h

044077h

044078h DMA0 Request Source Select Register

044079h DMA1 Request Source Select Register

04407Ah DMA2 Request Source Select Register

04407Bh DMA3 Request Source Select Register

DM0SL

DM1SL

DM2SL

DM3SL

XXX0 0000b

04407Ch

04407Dh Wake-up IPL Setting Register 2

04407Eh

04407Fh Wake-up IPL Setting Register 1

RIPL2

RIPL1

XX0X 0000b

044080h

044081h

044082h

044083h

044084h

044085h

044086h

044087h

044088h

044089h

04408Ah

04408Bh

04408Ch

04408Dh

04408Eh

04408Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 51 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.25

SFR List (25)

Address

044090h to

0443FFh

Register

Symbol

Reset Value

I²C Bus Transmit/Receive Shift Register

044400h

044401h

044402h

044403h

044404h

044405h

I2CTRSR

XXh

00h

I²C Bus Slave Address Register

I²C Bus Control Register 0

I²C Bus Clock Control Register

I²C Bus START Condition/STOP Condition Control

Register

I2CSAR

I2CCR0

I2CCCR

I2CSSCR

0000 0000b

I²C Bus Control Register 1

I²C Bus Control Register 2

I²C Bus Status Register

044406h

044407h

044408h

044409h

04440Ah

04440Bh

04440Ch

04440Dh

04440Eh

04440Fh

044410h

I2CCR1

I2CCR2

I2CSR

0000 0000b

I²C Bus Mode Register

I2CMR

0000 0000b

044411h

044412h

044413h

044414h

044415h

044416h

044417h

044418h

044419h

04441Ah

04441Bh

04441Ch

04441Dh

04441Eh

04441Fh

044420h to

0467FFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 52 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.26

SFR List (26)

Address

046800h to

0477FFh

Register

Symbol

Reset Value

047800h CAN1 Mailbox 0: Message Identifier

C1MB0

XXXX XXXXh

047801h

047802h

047803h

047804h

047805h CAN1 Mailbox 0: Data Length

XXh

047806h CAN1 Mailbox 0: Data Field

047807h

XXXX XXXX

XXXX XXXXh

047808h

047809h

04780Ah

04780Bh

04780Ch

04780Dh

04780Eh CAN1 Mailbox 0: Time Stamp

XXXXh

04780Fh

047810h CAN1 Mailbox 1: Message Identifier

C1MB1

XXXX XXXXh

047811h

047812h

047813h

047814h

047815h CAN1 Mailbox 1: Data Length

XXh

047816h CAN1 Mailbox 1: Data Field

047817h

XXXX XXXX

XXXX XXXXh

047818h

047819h

04781Ah

04781Bh

04781Ch

04781Dh

04781Eh CAN1 Mailbox 1: Time Stamp

XXXXh

04781Fh

047820h CAN1 Mailbox 2: Message Identifier

C1MB2

XXXX XXXXh

047821h

047822h

047823h

047824h

047825h CAN1 Mailbox 2: Data Length

XXh

047826h CAN1 Mailbox 2: Data Field

047827h

XXXX XXXX

XXXX XXXXh

047828h

047829h

04782Ah

04782Bh

04782Ch

04782Dh

04782Eh CAN1 Mailbox 2: Time Stamp

04782Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 53 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.27

SFR List (27)

Address

Register

Symbol

C1MB3

Reset Value

XXXX XXXXh

047830h CAN1 Mailbox 3: Message Identifier

047831h

047832h

047833h

047834h

047835h CAN1 Mailbox 3: Data Length

XXh

047836h CAN1 Mailbox 3: Data Field

047837h

XXXX XXXX

XXXX XXXXh

047838h

047839h

04783Ah

04783Bh

04783Ch

04783Dh

04783Eh CAN1 Mailbox 3: Time Stamp

XXXXh

04783Fh

047840h CAN1 Mailbox 4: Message Identifier

C1MB4

XXXX XXXXh

047841h

047842h

047843h

047844h

047845h CAN1 Mailbox 4: Data Length

XXh

047846h CAN1 Mailbox 4: Data Field

047847h

XXXX XXXX

XXXX XXXXh

047848h

047849h

04784Ah

04784Bh

04784Ch

04784Dh

04784Eh CAN1 Mailbox 4: Time Stamp

XXXXh

04784Fh

047850h CAN1 Mailbox 5: Message Identifier

C1MB5

XXXX XXXXh

047851h

047852h

047853h

047854h

047855h CAN1 Mailbox 5: Data Length

XXh

047856h CAN1 Mailbox 5: Data Field

047857h

XXXX XXXX

XXXX XXXXh

047858h

047859h

04785Ah

04785Bh

04785Ch

04785Dh

04785Eh CAN1 Mailbox 5: Time Stamp

04785Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 54 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.28

SFR List (28)

Address

Register

Symbol

C1MB6

Reset Value

XXXX XXXXh

047860h CAN1 Mailbox 6: Message Identifier

047861h

047862h

047863h

047864h

047865h CAN1 Mailbox 6: Data Length

XXh

047866h CAN1 Mailbox 6: Data Field

047867h

XXXX XXXX

XXXX XXXXh

047868h

047869h

04786Ah

04786Bh

04786Ch

04786Dh

04786Eh CAN1 Mailbox 6: Time Stamp

XXXXh

04786Fh

047870h CAN1 Mailbox 7: Message Identifier

C1MB7

XXXX XXXXh

047871h

047872h

047873h

047874h

047875h CAN1 Mailbox 7: Data Length

XXh

047876h CAN1 Mailbox 7: Data Field

047877h

XXXX XXXX

XXXX XXXXh

047878h

047879h

04787Ah

04787Bh

04787Ch

04787Dh

04787Eh CAN1 Mailbox 7: Time Stamp

XXXXh

04787Fh

047880h CAN1 Mailbox 8: Message Identifier

C1MB8

XXXX XXXXh

047881h

047882h

047883h

047884h

047885h CAN1 Mailbox 8: Data Length

XXh

047886h CAN1 Mailbox 8: Data Field

047887h

XXXX XXXX

XXXX XXXXh

047888h

047889h

04788Ah

04788Bh

04788Ch

04788Dh

04788Eh CAN1 Mailbox 8: Time Stamp

04788Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 55 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.29

SFR List (29)

Address

Register

Symbol

C1MB9

Reset Value

XXXX XXXXh

047890h CAN1 Mailbox 9: Message Identifier

047891h

047892h

047893h

047894h

047895h CAN1 Mailbox 9: Data Length

XXh

047896h CAN1 Mailbox 9: Data Field

047897h

XXXX XXXX

XXXX XXXXh

047898h

047899h

04789Ah

04789Bh

04789Ch

04789Dh

04789Eh CAN1 Mailbox 9: Time Stamp

XXXXh

04789Fh

0478A0h CAN1 Mailbox 10: Message Identifier

C1MB10

XXXX XXXXh

0478A1h

0478A2h

0478A3h

0478A4h

0478A5h CAN1 Mailbox 10: Data Length

XXh

0478A6h CAN1 Mailbox 10: Data Field

0478A7h

XXXX XXXX

XXXX XXXXh

0478A8h

0478A9h

0478AAh

0478ABh

0478ACh

0478ADh

0478AEh CAN1 Mailbox 10: Time Stamp

XXXXh

0478AFh

0478B0h CAN1 Mailbox 11: Message Identifier

C1MB11

XXXX XXXXh

0478B1h

0478B2h

0478B3h

0478B4h

0478B5h CAN1 Mailbox 11: Data Length

XXh

0478B6h CAN1 Mailbox 11: Data Field

0478B7h

XXXX XXXX

XXXX XXXXh

0478B8h

0478B9h

0478BAh

0478BBh

0478BCh

0478BDh

0478BEh CAN1 Mailbox 11: Time Stamp

0478BFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 56 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.30

SFR List (30)

Address

Register

Symbol

C1MB12

Reset Value

XXXX XXXXh

0478C0h CAN1 Mailbox 12: Message Identifier

0478C1h

0478C2h

0478C3h

0478C4h

0478C5h CAN1 Mailbox 12: Data Length

XXh

0478C6h CAN1 Mailbox 12: Data Field

0478C7h

XXXX XXXX

XXXX XXXXh

0478C8h

0478C9h

0478CAh

0478CBh

0478CCh

0478CDh

0478CEh CAN1 Mailbox 12: Time Stamp

XXXXh

0478CFh

0478D0h CAN1 Mailbox 13: Message Identifier

C1MB13

XXXX XXXXh

0478D1h

0478D2h

0478D3h

0478D4h

0478D5h CAN1 Mailbox 13: Data Length

XXh

0478D6h CAN1 Mailbox 13: Data Field

0478D7h

XXXX XXXX

XXXX XXXXh

0478D8h

0478D9h

0478DAh

0478DBh

0478DCh

0478DDh

0478DEh CAN1 Mailbox 13: Time Stamp

XXXXh

0478DFh

0478E0h CAN1 Mailbox 14: Message Identifier

C1MB14

XXXX XXXXh

0478E1h

0478E2h

0478E3h

0478E4h

0478E5h CAN1 Mailbox 14: Data Length

XXh

0478E6h CAN1 Mailbox 14: Data Field

0478E7h

XXXX XXXX

XXXX XXXXh

0478E8h

0478E9h

0478EAh

0478EBh

0478ECh

0478EDh

0478EEh CAN1 Mailbox 14: Time Stamp

0478EFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 57 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.31

SFR List (31)

Address

Register

Symbol

C1MB15

Reset Value

XXXX XXXXh

0478F0h CAN1 Mailbox 15: Message Identifier

0478F1h

0478F2h

0478F3h

0478F4h

0478F5h CAN1 Mailbox 15: Data Length

XXh

0478F6h CAN1 Mailbox 15: Data Field

0478F7h

XXXX XXXX

XXXX XXXXh

0478F8h

0478F9h

0478FAh

0478FBh

0478FCh

0478FDh

0478FEh CAN1 Mailbox 15: Time Stamp

XXXXh

0478FFh

047900h CAN1 Mailbox 16: Message Identifier

C1MB16

XXXX XXXXh

047901h

047902h

047903h

047904h

047905h CAN1 Mailbox 16: Data Length

XXh

047906h CAN1 Mailbox 16: Data Field

047907h

XXXX XXXX

XXXX XXXXh

047908h

047909h

04790Ah

04790Bh

04790Ch

04790Dh

04790Eh CAN1 Mailbox 16: Time Stamp

XXXXh

04790Fh

047910h CAN1 Mailbox 17: Message Identifier

C1MB17

XXXX XXXXh

047911h

047912h

047913h

047914h

047915h CAN1 Mailbox 17: Data Length

XXh

047916h CAN1 Mailbox 17: Data Field

047917h

XXXX XXXX

XXXX XXXXh

047918h

047919h

04791Ah

04791Bh

04791Ch

04791Dh

04791Eh CAN1 Mailbox 17: Time Stamp

04791Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 58 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.32

SFR List (32)

Address

Register

Symbol

C1MB18

Reset Value

XXXX XXXXh

047920h CAN1 Mailbox 18: Message Identifier

047921h

047922h

047923h

047924h

047925h CAN1 Mailbox 18: Data Length

XXh

047926h CAN1 Mailbox 18: Data Field

047927h

XXXX XXXX

XXXX XXXXh

047928h

047929h

04792Ah

04792Bh

04792Ch

04792Dh

04792Eh CAN1 Mailbox18: Time Stamp

XXXXh

04792Fh

047930h CAN1 Mailbox 19: Message Identifier

C1MB19

XXXX XXXXh

047931h

047932h

047933h

047934h

047935h CAN1 Mailbox 19: Data Length

XXh

047936h CAN1 Mailbox 19: Data Field

047937h

XXXX XXXX

XXXX XXXXh

047938h

047939h

04793Ah

04793Bh

04793Ch

04793Dh

04793Eh CAN1 Mailbox 19: Time Stamp

XXXXh

04793Fh

047940h CAN1 Mailbox 20: Message Identifier

C1MB20

XXXX XXXXh

047941h

047942h

047943h

047944h

047945h CAN1 Mailbox 20: Data Length

XXh

047946h CAN1 Mailbox 20: Data Field

047947h

XXXX XXXX

XXXX XXXXh

047948h

047949h

04794Ah

04794Bh

04794Ch

04794Dh

04794Eh CAN1 Mailbox 20: Time Stamp

04794Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 59 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.33

SFR List (33)

Address

Register

Symbol

C1MB21

Reset Value

XXXX XXXXh

047950h CAN1 Mailbox 21: Message Identifier

047951h

047952h

047953h

047954h

047955h CAN1 Mailbox 21: Data Length

XXh

047956h CAN1 Mailbox 21: Data Field

047957h

XXXX XXXX

XXXX XXXXh

047958h

047959h

04795Ah

04795Bh

04795Ch

04795Dh

04795Eh CAN1 Mailbox 21: Time Stamp

XXXXh

04795Fh

047960h CAN1 Mailbox 22: Identifier

C1MB22

XXXX XXXXh

047961h

047962h

047963h

047964h

047965h CAN1 Mailbox 22: Data Length

XXh

047966h CAN1 Mailbox 22: Data Field

047967h

XXXX XXXX

XXXX XXXXh

047968h

047969h

04796Ah

04796Bh

04796Ch

04796Dh

04796Eh CAN1 Mailbox 22: Time Stamp

XXXXh

04796Fh

047970h CAN1 Mailbox 23: Message Identifier

C1MB23

XXXX XXXXh

047971h

047972h

047973h

047974h

047975h CAN1 Mailbox 23: Data Length

XXh

047976h CAN1 Mailbox 23: Data Field

047977h

XXXX XXXX

XXXX XXXXh

047978h

047979h

04797Ah

04797Bh

04797Ch

04797Dh

04797Eh CAN1 Mailbox 23: Time Stamp

04797Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 60 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.34

SFR List (34)

Address

Register

Symbol

C1MB24

Reset Value

XXXX XXXXh

047980h CAN1 Mailbox 24: Message Identifier

047981h

047982h

047983h

047984h

047985h CAN1 Mailbox 24: Data Length

XXh

047986h CAN1 Mailbox 24: Data Field

047987h

XXXX XXXX

XXXX XXXXh

047988h

047989h

04798Ah

04798Bh

04798Ch

04798Dh

04798Eh CAN1 Mailbox 24: Time Stamp

XXXXh

04798Fh

047990h CAN1 Mailbox 25: Message Identifier

C1MB25

XXXX XXXXh

047991h

047992h

047993h

047994h

047995h CAN1 Mailbox 25: Data Length

XXh

047996h CAN1 Mailbox 25: Data Field

047997h

XXXX XXXX

XXXX XXXXh

047998h

047999h

04799Ah

04799Bh

04799Ch

04799Dh

04799Eh CAN1 Mailbox 25: Time Stamp

XXXXh

04799Fh

0479A0h CAN1 Mailbox 26: Message Identifier

C1MB26

XXXX XXXXh

0479A1h

0479A2h

0479A3h

0479A4h

0479A5h CAN1 Mailbox 26: Data Length

XXh

0479A6h CAN1 Mailbox 26: Data Field

0479A7h

XXXX XXXX

XXXX XXXXh

0479A8h

0479A9h

0479AAh

0479ABh

0479ACh

0479ADh

0479AEh CAN1 Mailbox 26: Time Stamp

0479AFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 61 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.35

SFR List (35)

Address

Register

Symbol

C1MB27

Reset Value

XXXX XXXXh

0479B0h CAN1 Mailbox 27: Message Identifier

0479B1h

0479B2h

0479B3h

0479B4h

0479B5h CAN1 Mailbox 27: Data Length

XXh

0479B6h CAN1 Mailbox 27: Data Field

0479B7h

XXXX XXXX

XXXX XXXXh

0479B8h

0479B9h

0479BAh

0479BBh

0479BCh

0479BDh

0479BEh CAN1 Mailbox 27: Time Stamp

XXXXh

0479BFh

0479C0h CAN1 Mailbox 28: Message Identifier

C1MB28

XXXX XXXXh

0479C1h

0479C2h

0479C3h

0479C4h

0479C5h CAN1 Mailbox 28: Data Length

XXh

0479C6h CAN1 Mailbox 28: Data Field

0479C7h

XXXX XXXX

XXXX XXXXh

0479C8h

0479C9h

0479CAh

0479CBh

0479CCh

0479CDh

0479CEh CAN1 Mailbox 28: Time Stamp

XXXXh

0479CFh

0479D0h CAN1 Mailbox 29: Message Identifier

C1MB29

XXXX XXXXh

0479D1h

0479D2h

0479D3h

0479D4h

0479D5h CAN1 Mailbox 29: Data Length

XXh

0479D6h CAN1 Mailbox 29: Data Field

0479D7h

XXXX XXXX

XXXX XXXXh

0479D8h

0479D9h

0479DAh

0479DBh

0479DCh

0479DDh

0479DEh CAN1 Mailbox 29: Time Stamp

0479DFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 62 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.36

SFR List (36)

Address

Register

Symbol

C1MB30

Reset Value

XXXX XXXXh

0479E0h CAN1 Mailbox 30: Message Identifier

0479E1h

0479E2h

0479E3h

0479E4h

0479E5h CAN1 Mailbox 30: Data Length

XXh

0479E6h CAN1 Mailbox 30: Data Field

0479E7h

XXXX XXXX

XXXX XXXXh

0479E8h

0479E9h

0479EAh

0479EBh

0479ECh

0479EDh

0479EEh CAN1 Mailbox 30: Time Stamp

XXXXh

0479EFh

0479F0h CAN1 Mailbox 31: Message Identifier

C1MB31

XXXX XXXXh

0479F1h

0479F2h

0479F3h

0479F4h

0479F5h CAN1 Mailbox 31: Data Length

XXh

0479F6h CAN1 Mailbox 31: Data Field

0479F7h

XXXX XXXX

XXXX XXXXh

0479F8h

0479F9h

0479FAh

0479FBh

0479FCh

0479FDh

0479FEh CAN1 Mailbox 31: Time Stamp

XXXXh

0479FFh

047A00h CAN1 Acceptance Mask Register 0

047A01h

047A02h

047A03h

047A04h CAN1 Acceptance Mask Register 1

047A05h

047A06h

047A07h

047A08h CAN1 Acceptance Mask Register 2

047A09h

047A0Ah

047A0Bh

C1MKR0

C1MKR1

C1MKR2

C1MKR3

XXXX XXXXh

047A0Ch CAN1 Acceptance Mask Register 3

047A0Dh

047A0Eh

047A0Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 63 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.37

SFR List (37)

Address

Register

Symbol

C1MKR4

Reset Value

XXXX XXXXh

047A10h CAN1 Acceptance Mask Register 4

047A11h

047A12h

047A13h

047A14h CAN1 Acceptance Mask Register 5

047A15h

047A16h

047A17h

047A18h CAN1 Acceptance Mask Register 6

047A19h

047A1Ah

047A1Bh

047A1Ch CAN1 Acceptance Mask Register 7

047A1Dh

047A1Eh

047A1Fh

047A20h CAN1 FIFO Received ID Compare Register 0

047A21h

047A22h

047A23h

047A24h CAN1 FIFO Received ID Compare Register 1

047A25h

047A26h

047A27h

047A28h CAN1 Mask Invalid Register

047A29h

047A2Ah

047A2Bh

C1MKR5

C1MKR6

C1MKR7

C1FIDCR0

C1FIDCR1

C1MKIVLR

C1MIER

XXXX XXXXh

047A2Ch CAN1 Mailbox Interrupt Enable Register

047A2Dh

047A2Eh

047A2Fh

047A30h

047A31h

047A32h

047A33h

047A34h

047A35h

047A36h

047A37h

047A38h

047A39h

047A3Ah

047A3Bh

047A3Ch

047A3Dh

047A3Eh

047A3Fh

047A40h to

047B1Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 64 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.38

SFR List (38)

Address

Register

Symbol

C1MCTL0

Reset Value

047B20h CAN1 Message Control Register 0

047B21h CAN1 Message Control Register 1

047B22h CAN1 Message Control Register 2

047B23h CAN1 Message Control Register 3

047B24h CAN1 Message Control Register 4

047B25h CAN1 Message Control Register 5

047B26h CAN1 Message Control Register 6

047B27h CAN1 Message Control Register 7

047B28h CAN1 Message Control Register 8

047B29h CAN1 Message Control Register 9

047B2Ah CAN1 Message Control Register 10

047B2Bh CAN1 Message Control Register 11

047B2Ch CAN1 Message Control Register 12

047B2Dh CAN1 Message Control Register 13

047B2Eh CAN1 Message Control Register 14

047B2Fh CAN1 Message Control Register 15

047B30h CAN1 Message Control Register 16

047B31h CAN1 Message Control Register 17

047B32h CAN1 Message Control Register 18

047B33h CAN1 Message Control Register 19

047B34h CAN1 Message Control Register 20

047B35h CAN1 Message Control Register 21

047B36h CAN1 Message Control Register 22

047B37h CAN1 Message Control Register 23

047B38h CAN1 Message Control Register 24

047B39h CAN1 Message Control Register 25

047B3Ah CAN1 Message Control Register 26

047B3Bh CAN1 Message Control Register 27

047B3Ch CAN1 Message Control Register 28

047B3Dh CAN1 Message Control Register 29

047B3Eh CAN1 Message Control Register 30

047B3Fh CAN1 Message Control Register 31

X: Undefined

00h

C1MCTL1

C1MCTL2

C1MCTL3

C1MCTL4

C1MCTL5

C1MCTL6

C1MCTL7

C1MCTL8

C1MCTL9

C1MCTL10

C1MCTL11

C1MCTL12

C1MCTL13

C1MCTL14

C1MCTL15

C1MCTL16

C1MCTL17

C1MCTL18

C1MCTL19

C1MCTL20

C1MCTL21

C1MCTL22

C1MCTL23

C1MCTL24

C1MCTL25

C1MCTL26

C1MCTL27

C1MCTL28

C1MCTL29

C1MCTL30

C1MCTL31

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 65 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.39

SFR List (39)

Address

047B40h CAN1 Control Register

047B41h

047B42h CAN1 Status Register

047B43h

047B44h CAN1 Bit Configuration Register

047B45h

Register

Symbol

C1CTLR

Reset Value

0000 0101b

0000 0000b

0000 0101b

0000 0000b

00 0000h

C1STR

C1BCR

047B46h

047B47h CAN1 Clock Select Register

047B48h CAN1 Receive FIFO Control Register

047B49h CAN1 Receive FIFO Pointer Control Register

047B4Ah CAN1 Transmit FIFO Control Register

047B4Bh CAN1 Transmit FIFO Pointer Control Register

047B4Ch CAN1 Error Interrupt Enable Register

047B4Dh CAN1 Error Interrupt Factor Judge Register

047B4Eh CAN1 Reception Error Count Register

047B4Fh CAN1 Transmission Error Count Register

047B50h CAN1 Error Code Store Register

047B51h CAN1 Channel Search Support Register

047B52h CAN1 Mailbox Search Status Register

047B53h CAN1 Mailbox Search Mode Register

047B54h CAN1 Time Stamp Register

047B55h

C1CLKR

C1RFCR

C1RFPCR

C1TFCR

C1TFPCR

C1EIER

000X 0000b

1000 0000b

XXh

1000 0000b

XXh

00h

XXh

1000 0000b

XXXX XX00b

0000h

C1EIFR

C1RECR

C1TECR

C1ECSR

C1CSSR

C1MSSR

C1MSMR

C1TSR

047B56h CAN1 Acceptance Filter Support Register

047B57h

047B58h CAN1 Test Control Register

047B59h

C1AFSR

C1TCR

XXXXh

00h

047B5Ah

047B5Bh

047B5Ch

047B5Dh

047B5Eh

047B5Fh

047B60h to

047BFFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 66 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.40

SFR List (40)

Address

Register

Symbol

C0MB0

Reset Value

XXXX XXXXh

047C00h CAN0 Mailbox 0: Message Identifier

047C01h

047C02h

047C03h

047C04h

047C05h CAN0 Mailbox 0: Data Length

XXh

047C06h CAN0 Mailbox 0: Data Field

047C07h

XXXX XXXX

XXXX XXXXh

047C08h

047C09h

047C0Ah

047C0Bh

047C0Ch

047C0Dh

047C0Eh CAN0 Mailbox 0: Time Stamp

XXXXh

047C0Fh

047C10h CAN0 Mailbox 1: Message Identifier

C0MB1

XXXX XXXXh

047C11h

047C12h

047C13h

047C14h

047C15h CAN0 Mailbox 1: Data Length

XXh

047C16h CAN0 Mailbox 1: Data Field

047C17h

XXXX XXXX

XXXX XXXXh

047C18h

047C19h

047C1Ah

047C1Bh

047C1Ch

047C1Dh

047C1Eh CAN0 Mailbox 1: Time Stamp

XXXXh

047C1Fh

047C20h CAN0 Mailbox 2: Message Identifier

C0MB2

XXXX XXXXh

047C21h

047C22h

047C23h

047C24h

047C25h CAN0 Mailbox 2: Data Length

XXh

047C26h CAN0 Mailbox 2: Data Field

047C27h

XXXX XXXX

XXXX XXXXh

047C28h

047C29h

047C2Ah

047C2Bh

047C2Ch

047C2Dh

047C2Eh CAN0 Mailbox 2: Time Stamp

047C2Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 67 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.41

SFR List (41)

Address

Register

Symbol

C0MB3

Reset Value

XXXX XXXXh

047C30h CAN0 Mailbox 3: Message Identifier

047C31h

047C32h

047C33h

047C34h

047C35h CAN0 Mailbox 3: Data Length

XXh

047C36h CAN0 Mailbox 3: Data Field

047C37h

XXXX XXXX

XXXX XXXXh

047C38h

047C39h

047C3Ah

047C3Bh

047C3Ch

047C3Dh

047C3Eh CAN0 Mailbox 3: Time Stamp

XXXXh

047C3Fh

047C40h CAN0 Mailbox 4: Message Identifier

C0MB4

XXXX XXXXh

047C41h

047C42h

047C43h

047C44h

047C45h CAN0 Mailbox 4: Data Length

XXh

047C46h CAN0 Mailbox 4: Data Field

047C47h

XXXX XXXX

XXXX XXXXh

047C48h

047C49h

047C4Ah

047C4Bh

047C4Ch

047C4Dh

047C4Eh CAN0 Mailbox 4: Time Stamp

XXXXh

047C4Fh

047C50h CAN0 Mailbox 5: Message Identifier

C0MB5

XXXX XXXXh

047C51h

047C52h

047C53h

047C54h

047C55h CAN0 Mailbox 5: Data Length

XXh

047C56h CAN0 Mailbox 5: Data Field

047C57h

XXXX XXXX

XXXX XXXXh

047C58h

047C59h

047C5Ah

047C5Bh

047C5Ch

047C5Dh

047C5Eh CAN0 Mailbox 5: Time Stamp

047C5Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 68 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.42

SFR List (42)

Address

Register

Symbol

C0MB6

Reset Value

XXXX XXXXh

047C60h CAN0 Mailbox 6: Message Identifier

047C61h

047C62h

047C63h

047C64h

047C65h CAN0 Mailbox 6: Data Length

XXh

047C66h CAN0 Mailbox 6: Data Field

047C67h

XXXX XXXX

XXXX XXXXh

047C68h

047C69h

047C6Ah

047C6Bh

047C6Ch

047C6Dh

047C6Eh CAN0 Mailbox 6: Time Stamp

XXXXh

047C6Fh

047C70h CAN0 Mailbox 7: Message Identifier

C0MB7

XXXX XXXXh

047C71h

047C72h

047C73h

047C74h

047C75h CAN0 Mailbox 7: Data Length

XXh

047C76h CAN0 Mailbox 7: Data Field

047C77h

XXXX XXXX

XXXX XXXXh

047C78h

047C79h

047C7Ah

047C7Bh

047C7Ch

047C7Dh

047C7Eh CAN0 Mailbox 7: Time Stamp

XXXXh

047C7Fh

047C80h CAN0 Mailbox 8: Message Identifier

C0MB8

XXXX XXXXh

047C81h

047C82h

047C83h

047C84h

047C85h CAN0 Mailbox 8: Data Length

XXh

047C86h CAN0 Mailbox 8: Data Field

047C87h

XXXX XXXX

XXXX XXXXh

047C88h

047C89h

047C8Ah

047C8Bh

047C8Ch

047C8Dh

047C8Eh CAN0 Mailbox 8: Time Stamp

047C8Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 69 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.43

SFR List (43)

Address

Register

Symbol

C0MB9

Reset Value

XXXX XXXXh

047C90h CAN0 Mailbox 9: Message Identifier

047C91h

047C92h

047C93h

047C94h

047C95h CAN0 Mailbox 9: Data Length

XXh

047C96h CAN0 Mailbox 9: Data Field

047C97h

XXXX XXXX

XXXX XXXXh

047C98h

047C99h

047C9Ah

047C9Bh

047C9Ch

047C9Dh

047C9Eh CAN0 Mailbox 9: Time Stamp

XXXXh

047C9Fh

047CA0h CAN0 Mailbox 10: Message Identifier

C0MB10

XXXX XXXXh

047CA1h

047CA2h

047CA3h

047CA4h

047CA5h CAN0 Mailbox 10: Data Length

XXh

047CA6h CAN0 Mailbox 10: Data Field

047CA7h

XXXX XXXX

XXXX XXXXh

047CA8h

047CA9h

047CAAh

047CABh

047CACh

047CADh

047CAEh CAN0 Mailbox 10: Time Stamp

XXXXh

047CAFh

047CB0h CAN0 Mailbox 11: Message Identifier

C0MB11

XXXX XXXXh

047CB1h

047CB2h

047CB3h

047CB4h

047CB5h CAN0 Mailbox 11: Data Length

XXh

047CB6h CAN0 Mailbox 11: Data Field

047CB7h

XXXX XXXX

XXXX XXXXh

047CB8h

047CB9h

047CBAh

047CBBh

047CBCh

047CBDh

047CBEh CAN0 Mailbox 11: Time Stamp

047CBFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 70 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.44

SFR List (44)

Address

Register

Symbol

C0MB12

Reset Value

XXXX XXXXh

047CC0h CAN0 Mailbox 12: Message Identifier

047CC1h

047CC2h

047CC3h

047CC4h

047CC5h CAN0 Mailbox 12: Data Length

XXh

047CC6h CAN0 Mailbox 12: Data Field

047CC7h

XXXX XXXX

XXXX XXXXh

047CC8h

047CC9h

047CCAh

047CCBh

047CCCh

047CCDh

047CCEh CAN0 Mailbox 12: Time Stamp

XXXXh

047CCFh

047CD0h CAN0 Mailbox 13: Message Identifier

C0MB13

XXXX XXXXh

047CD1h

047CD2h

047CD3h

047CD4h

047CD5h CAN0 Mailbox 13: Data Length

XXh

047CD6h CAN0 Mailbox 13: Data Field

047CD7h

XXXX XXXX

XXXX XXXXh

047CD8h

047CD9h

047CDAh

047CDBh

047CDCh

047CDDh

047CDEh CAN0 Mailbox 13: Time Stamp

XXXXh

047CDFh

047CE0h CAN0 Mailbox 14: Message Identifier

C0MB14

XXXX XXXXh

047CE1h

047CE2h

047CE3h

047CE4h

047CE5h CAN0 Mailbox 14: Data Length

XXh

047CE6h CAN0 Mailbox 14: Data Field

047CE7h

XXXX XXXX

XXXX XXXXh

047CE8h

047CE9h

047CEAh

047CEBh

047CECh

047CEDh

047CEEh CAN0 Mailbox 14: Time Stamp

047CEFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 71 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.45

SFR List (45)

Address

Register

Symbol

C0MB15

Reset Value

XXXX XXXXh

047CF0h CAN0 Mailbox 15: Message Identifier

047CF1h

047CF2h

047CF3h

047CF4h

047CF5h CAN0 Mailbox 15: Data Length

XXh

047CF6h CAN0 Mailbox 15: Data Field

047CF7h

XXXX XXXX

XXXX XXXXh

047CF8h

047CF9h

047CFAh

047CFBh

047CFCh

047CFDh

047CFEh CAN0 Mailbox 15: Time Stamp

XXXXh

047CFFh

047D00h CAN0 Mailbox 16: Message Identifier

C0MB16

XXXX XXXXh

047D01h

047D02h

047D03h

047D04h

047D05h CAN0 Mailbox 16: Data Length

XXh

047D06h CAN0 Mailbox 16: Data Field

047D07h

XXXX XXXX

XXXX XXXXh

047D08h

047D09h

047D0Ah

047D0Bh

047D0Ch

047D0Dh

047D0Eh CAN0 Mailbox 16: Time Stamp

XXXXh

047D0Fh

047D10h CAN0 Mailbox 17: Message Identifier

C0MB17

XXXX XXXXh

047D11h

047D12h

047D13h

047D14h

047D15h CAN0 Mailbox 17: Data Length

XXh

047D16h CAN0 Mailbox 17: Data Field

047D17h

XXXX XXXX

XXXX XXXXh

047D18h

047D19h

047D1Ah

047D1Bh

047D1Ch

047D1Dh

047D1Eh CAN0 Mailbox 17: Time Stamp

047D1Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 72 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.46

SFR List (46)

Address

Register

Symbol

C0MB18

Reset Value

XXXX XXXXh

047D20h CAN0 Mailbox 18: Message Identifier

047D21h

047D22h

047D23h

047D24h

047D25h CAN0 Mailbox 18: Data Length

XXh

047D26h CAN0 Mailbox 18: Data Field

047D27h

XXXX XXXX

XXXX XXXXh

047D28h

047D29h

047D2Ah

047D2Bh

047D2Ch

047D2Dh

047D2Eh CAN0 Mailbox 18: Time Stamp

XXXXh

047D2Fh

047D30h CAN0 Mailbox 19: Message Identifier

C0MB19

XXXX XXXXh

047D31h

047D32h

047D33h

047D34h

047D35h CAN0 Mailbox 19: Data Length

XXh

047D36h CAN0 Mailbox 19: Data Field

047D37h

XXXX XXXX

XXXX XXXXh

047D38h

047D39h

047D3Ah

047D3Bh

047D3Ch

047D3Dh

047D3Eh CAN0 Mailbox 19: Time Stamp

XXXXh

047D3Fh

047D40h CAN0 Mailbox 20: Message Identifier

C0MB20

XXXX XXXXh

047D41h

047D42h

047D43h

047D44h

047D45h CAN0 Mailbox 20: Data Length

XXh

047D46h CAN0 Mailbox 20: Data Field

047D47h

XXXX XXXX

XXXX XXXXh

047D48h

047D49h

047D4Ah

047D4Bh

047D4Ch

047D4Dh

047D4Eh CAN0 Mailbox 20: Time Stamp

047D4Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 73 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.47

SFR List (47)

Address

Register

Symbol

C0MB21

Reset Value

XXXX XXXXh

047D50h CAN0 Mailbox 21: Message Identifier

047D51h

047D52h

047D53h

047D54h

047D55h CAN0 Mailbox 21: Data Length

XXh

047D56h CAN0 Mailbox 21: Data Field

047D57h

XXXX XXXX

XXXX XXXXh

047D58h

047D59h

047D5Ah

047D5Bh

047D5Ch

047D5Dh

047D5Eh CAN0 Mailbox 21: Time Stamp

XXXXh

047D5Fh

047D60h CAN0 Mailbox 22: Message Identifier

C0MB22

XXXX XXXXh

047D61h

047D62h

047D63h

047D64h

047D65h CAN0 Mailbox 22: Data Length

XXh

047D66h CAN0 Mailbox 22: Data Field

047D67h

XXXX XXXX

XXXX XXXXh

047D68h

047D69h

047D6Ah

047D6Bh

047D6Ch

047D6Dh

047D6Eh CAN0 Mailbox 22: Time Stamp

XXXXh

047D6Fh

047D70h CAN0 Mailbox 23: Message Identifier

C0MB23

XXXX XXXXh

047D71h

047D72h

047D73h

047D74h

047D75h CAN0 Mailbox 23: Data Length

XXh

047D76h CAN0 Mailbox 23: Data Field

047D77h

XXXX XXXX

XXXX XXXXh

047D78h

047D79h

047D7Ah

047D7Bh

047D7Ch

047D7Dh

047D7Eh CAN0 Mailbox 23: Time Stamp

047D7Fh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 74 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.48

SFR List (48)

Address

Register

Symbol

C0MB24

Reset Value

XXXX XXXXh

047D80h CAN0 Mailbox 24: Message Identifier

047D81h

047D82h

047D83h

047D84h

047D85h CAN0 Mailbox 24: Data Length

XXh

047D86h CAN0 Mailbox 24: Data Field

047D87h

XXXX XXXX

XXXX XXXXh

047D88h

047D89h

047D8Ah

047D8Bh

047D8Ch

047D8Dh

047D8Eh CAN0 Mailbox 24: Time Stamp

XXXXh

047D8Fh

047D90h CAN0 Mailbox 25: Message Identifier

C0MB25

XXXX XXXXh

047D91h

047D92h

047D93h

047D94h

047D95h CAN0 Mailbox 25: Data Length

XXh

047D96h CAN0 Mailbox 25: Data Field

047D97h

XXXX XXXX

XXXX XXXXh

047D98h

047D99h

047D9Ah

047D9Bh

047D9Ch

047D9Dh

047D9Eh CAN0 Mailbox 25: Time Stamp

XXXXh

047D9Fh

047DA0h CAN0 Mailbox 26: Message Identifier

C0MB26

XXXX XXXXh

047DA1h

047DA2h

047DA3h

047DA4h

047DA5h CAN0 Mailbox 26: Data Length

XXh

047DA6h CAN0 Mailbox 26: Data Field

047DA7h

XXXX XXXX

XXXX XXXXh

047DA8h

047DA9h

047DAAh

047DABh

047DACh

047DADh

047DAEh CAN0 Mailbox 26: Time Stamp

047DAFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 75 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.49

SFR List (49)

Address

Register

Symbol

C0MB27

Reset Value

XXXX XXXXh

047DB0h CAN0 Mailbox 27: Message Identifier

047DB1h

047DB2h

047DB3h

047DB4h

047DB5h CAN0 Mailbox 27: Data Length

XXh

047DB6h CAN0 Mailbox 27: Data Field

047DB7h

XXXX XXXX

XXXX XXXXh

047DB8h

047DB9h

047DBAh

047DBBh

047DBCh

047DBDh

047DBEh CAN0 Mailbox 27: Time Stamp

XXXXh

047DBFh

047DC0h CAN0 Mailbox 28: Message Identifier

C0MB28

XXXX XXXXh

047DC1h

047DC2h

047DC3h

047DC4h

047DC5h CAN0 Mailbox 28: Data Length

XXh

047DC6h CAN0 Mailbox 28: Data Field

047DC7h

XXXX XXXX

XXXX XXXXh

047DC8h

047DC9h

047DCAh

047DCBh

047DCCh

047DCDh

047DCEh CAN0 Mailbox 28: Time Stamp

XXXXh

047DCFh

047DD0h CAN0 Mailbox 29: Message Identifier

C0MB29

XXXX XXXXh

047DD1h

047DD2h

047DD3h

047DD4h

047DD5h CAN0 Mailbox 29: Data Length

XXh

047DD6h CAN0 Mailbox 29: Data Field

047DD7h

XXXX XXXX

XXXX XXXXh

047DD8h

047DD9h

047DDAh

047DDBh

047DDCh

047DDDh

047DDEh CAN0 Mailbox 29: Time Stamp

047DDFh

XXXXh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 76 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.50

SFR List (50)

Address

Register

Symbol

C0MB30

Reset Value

XXXX XXXXh

047DE0h CAN0 Mailbox 30: Message Identifier

047DE1h

047DE2h

047DE3h

047DE4h

047DE5h CAN0 Mailbox 30: Data Length

XXh

047DE6h CAN0 Mailbox 30: Data Field

047DE7h

XXXX XXXX

XXXX XXXXh

047DE8h

047DE9h

047DEAh

047DEBh

047DECh

047DEDh

047DEEh CAN0 Mailbox 30: Time Stamp

XXXXh

047DEFh

047DF0h CAN0 Mailbox 31: Message Identifier

C0MB31

XXXX XXXXh

047DF1h

047DF2h

047DF3h

047DF4h

047DF5h CAN0 Mailbox 31: Data Length

XXh

047DF6h CAN0 Mailbox 31: Data Field

047DF7h

XXXX XXXX

XXXX XXXXh

047DF8h

047DF9h

047DFAh

047DFBh

047DFCh

047DFDh

047DFEh CAN0 Mailbox 31: Time Stamp

XXXXh

047DFFh

047E00h CAN0 Acceptance Mask Register 0

047E01h

047E02h

047E03h

047E04h CAN0 Acceptance Mask Register 1

047E05h

047E06h

047E07h

047E08h CAN0 Acceptance Mask Register 2

047E09h

047E0Ah

047E0Bh

C0MKR0

C0MKR1

C0MKR2

C0MKR3

XXXX XXXXh

047E0Ch CAN0 Acceptance Mask Register 3

047E0Dh

047E0Eh

047E0Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 77 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.51

SFR List (51)

Address

Register

Symbol

C0MKR4

Reset Value

XXXX XXXXh

047E10h CAN0 Acceptance Mask Register 4

047E11h

047E12h

047E13h

047E14h CAN0 Acceptance Mask Register 5

047E15h

047E16h

047E17h

047E18h CAN0 Acceptance Mask Register 6

047E19h

047E1Ah

047E1Bh

047E1Ch CAN0 Acceptance Mask Register 7

047E1Dh

047E1Eh

047E1Fh

047E20h CAN0 FIFO Receive ID Compare Register 0

047E21h

047E22h

047E23h

047E24h CAN0 FIFO Receive ID Compare Register 1

047E25h

047E26h

047E27h

047E28h CAN0 Mask Invalid Register

047E29h

047E2Ah

047E2Bh

C0MKR5

C0MKR6

C0MKR7

C0FIDCR0

C0FIDCR1

C0MKIVLR

C0MIER

XXXX XXXXh

047E2Ch CAN0 Mailbox Interrupt Enable Register

047E2Dh

047E2Eh

047E2Fh

047E30h

047E31h

047E32h

047E33h

047E34h

047E35h

047E36h

047E37h

047E38h

047E39h

047E3Ah

047E3Bh

047E3Ch

047E3Dh

047E3Eh

047E3Fh

047E40h to

047F1Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 78 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.52

SFR List (52)

Address

Register

Symbol

C0MCTL0

Reset Value

047F20h CAN0 Message Control Register 0

047F21h CAN0 Message Control Register 1

047F22h CAN0 Message Control Register 2

047F23h CAN0 Message Control Register 3

047F24h CAN0 Message Control Register 4

047F25h CAN0 Message Control Register 5

047F26h CAN0 Message Control Register 6

047F27h CAN0 Message Control Register 7

047F28h CAN0 Message Control Register 8

047F29h CAN0 Message Control Register 9

047F2Ah CAN0 Message Control Register 10

047F2Bh CAN0 Message Control Register 11

047F2Ch CAN0 Message Control Register 12

047F2Dh CAN0 Message Control Register 13

047F2Eh CAN0 Message Control Register 14

047F2Fh CAN0 Message Control Register 15

047F30h CAN0 Message Control Register 16

047F31h CAN0 Message Control Register 17

047F32h CAN0 Message Control Register 18

047F33h CAN0 Message Control Register 19

047F34h CAN0 Message Control Register 20

047F35h CAN0 Message Control Register 21

047F36h CAN0 Message Control Register 22

047F37h CAN0 Message Control Register 23

047F38h CAN0 Message Control Register 24

047F39h CAN0 Message Control Register 25

047F3Ah CAN0 Message Control Register 26

047F3Bh CAN0 Message Control Register 27

047F3Ch CAN0 Message Control Register 28

047F3Dh CAN0 Message Control Register 29

047F3Eh CAN0 Message Control Register 30

047F3Fh CAN0 Message Control Register 31

X: Undefined

00h

C0MCTL1

C0MCTL2

C0MCTL3

C0MCTL4

C0MCTL5

C0MCTL6

C0MCTL7

C0MCTL8

C0MCTL9

C0MCTL10

C0MCTL11

C0MCTL12

C0MCTL13

C0MCTL14

C0MCTL15

C0MCTL16

C0MCTL17

C0MCTL18

C0MCTL19

C0MCTL20

C0MCTL21

C0MCTL22

C0MCTL23

C0MCTL24

C0MCTL25

C0MCTL26

C0MCTL27

C0MCTL28

C0MCTL29

C0MCTL30

C0MCTL31

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 79 of 122

R32C/118 Group

4. Special Function Registers (SFRs)

Table 4.53

SFR List (53)

Address

047F40h CAN0 Control Register

047F41h

047F42h CAN0 Status Register

047F43h

047F44h CAN0 Bit Configuration Register

Register

Symbol

C0CTLR

Reset Value

0000 0101b

0000 0000b

0000 0101b

0000 0000b

00 0000h

C0STR

C0BCR

047F45h

047F46h

047F47h CAN0 Clock Select Register

047F48h CAN0 Receive FIFO Control Register

047F49h CAN0 Receive FIFO Pointer Control Register

047F4Ah CAN0 Transmit FIFO Control Register

047F4Bh CAN0 Transmit FIFO Pointer Control Register

047F4Ch CAN0 Error Interrupt Enable Register

047F4Dh CAN0 Error Interrupt Factor Judge Register

047F4Eh CAN0 Reception Error Count Register

047F4Fh CAN0 Transmission Error Count Register

047F50h CAN0 Error Code Store Register

047F51h CAN0 Channel Search Support Register

047F52h CAN0 Mailbox Search Status Register

047F53h CAN0 Mailbox Search Mode Register

047F54h CAN0 Time Stamp Register

047F55h

C0CLKR

C0RFCR

C0RFPCR

C0TFCR

C0TFPCR

C0EIER

000X 0000b

1000 0000b

XXh

1000 0000b

XXh

00h

XXh

1000 0000b

XXXX XX00b

0000h

C0EIFR

C0RECR

C0TECR

C0ECSR

C0CSSR

C0MSSR

C0MSMR

C0TSR

047F56h CAN0 Acceptance Filter Support Register

047F57h

047F58h CAN0 Test Control Register

047F59h

C0AFSR

C0TCR

XXXXh

00h

047F5Ah

047F5Bh

047F5Ch

047F5Dh

047F5Eh

047F5Fh

047F60h to

047FFFh

048000h to

04FFFFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 80 of 122

R32C/118 Group

5. Electrical Characteristics

(1)

Table 5.1

Absolute Maximum Ratings

Symbol

Characteristic

Condition

Value

Unit

V

Supply voltage

V

= AV

-0.3 to 6.0

CC

AV

Analog supply voltage

V

= AV

V

CC

V

Input voltage XIN, RESET, CNVSS, NSD, V

,

REF

I

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P5_0 to P5_3, P8_4 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1,

-0.3 to V + 0.3

V

CC

(2)

P14_3 to P14_6, P15_0 to P15_7

P4_0 to P4_7, P5_4 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_3

-0.3 to 6.0

V

Output

voltage

XOUT, P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

O

-0.3 to V + 0.3

V

CC

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_3 to P14_6,

(2)

P15_0 to P15_7

P

T

Power consumption

T = 25°C

a

500

mW

°C

d

—

Operating temperature range

Storage temperature range

-40 to 85

-65 to 150

°C

stg

Notes:

1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 81 of 122

R32C/118 Group

5. Electrical Characteristics

(1)

Table 5.2

Operating Conditions (1/5)

Value

Unit

Symbol

Characteristic

Min.

3.0

Typ.

5.0

Max.

5.5

V

Digital supply voltage

V

CC

V

AV

V

Analog supply voltage

Reference voltage

CC

V

3.0

V

REF

SS

CC

V

Digital ground voltage

Analog ground voltage

0

V

AV

V

SS

dV /dt V ramp up rate (V < 2.0 V)

0.05

V/ms

CC

V

High level XIN, RESET, CNVSS, NSD,

IH

input

P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_3,

(2)

voltage

0.8 × V

V

P8_4 to P8_7 , P9_0 to P9_7,

V

CC

P10_0 to P10_7, P11_0 to P11_4, P14_1,

(3)

P14_3 to P14_6, P15_0 to P15_7

P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7,

P7_0 to P7_7, P8_0 to P8_3

0.8 × V

6.0

V

CC

P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7,

P13_0 to P13_7

V

CC

(3)

(in single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7,

P13_0 to P13_7 (in memory expansion mode

0.5 × V

V

CC

(3)

or microprocessor mode)

V

Low level

input

XIN, RESET, CNVSS, NSD,

P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7,

P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

IL

voltage

0.2 × V

0

CC

(2)

P8_0 to P8_7 , P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4, P14_1,

(3)

P14_3 to P14_6, P15_0 to P15_7

P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7,

P13_0 to P13_7

0.2 × V

0

V

CC

(3)

(in single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7,

P13_0 to P13_7 (in memory expansion mode

0.16 × V

CC

(3)

or microprocessor mode)

T

Operating Version N

-20

-40

85

°C

opr

temperature

range

Version D

Version P

Notes:

1. The device is operationally guaranteed under these operating conditions.

2. and V for P8_7 are specified for P8_7 as a programmable port. These values are not applicable

V

IH

IL

to P8_7 as XCIN.

3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 82 of 122

R32C/118 Group

5. Electrical Characteristics

Table 5.3

Operating Conditions (2/5)

(1)

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

(2)

Value

Min. Typ. Max.

Symbol

Characteristic

Unit

C

Decoupling capacitance for voltage

regulator

Inter-pin voltage: 1.5 V

VDC

2.4

10.0 µF

Notes:

1. The device is operationally guaranteed under these operating conditions.

2. This value should be satisfied with due consideration of every condition as follows: operating

temperature, DC bias, aging, etc.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 83 of 122

R32C/118 Group

5. Electrical Characteristics

Table 5.4

Operating Conditions (3/5)

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

(1)

CC

SS

a

opr

Value

Typ.

Symbol

Characteristic

High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

Unit

Min.

Max.

I

OH

(peak)

peak

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

output

current

-10.0 mA

(2)

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

(3)

P14_3 to P14_6, P15_0 to P15_7

High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

average P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

OH

(avg)

output

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

-5.0

mA

(4)

current

(3)

P14_3 to P14_6, P15_0 to P15_7

Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

OL

(peak)

(avg)

peak

output

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

10.0 mA

(2)

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

(3)

P14_3 to P14_6, P15_0 to P15_7

Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

average P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

OL

output

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

5.0

mA

(4)

current

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

(3)

P14_3 to P14_6, P15_0 to P15_7

Notes:

1. The device is operationally guaranteed under these operating conditions.

2. The following conditions should be satisfied:

• The sum of I

of ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 is 80 mA or less.

of ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 is 80 mA or less.

of ports P0, P1, P2, and P11 is -40 mA or less.

OL(peak)

OH(peak)

of ports P8_6, P8_7, P9, P10, P14, and P15 is -40 mA or less.

of ports P3, P4, P5, P12, and P13 is -40 mA or less.

of ports P6, P7, and P8_0 to P8_4 is -40 mA or less.

3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

4. Average value within 100 ms.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 84 of 122

R32C/118 Group

5. Electrical Characteristics

Table 5.5

Operating Conditions (4/5)

(1)

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Typ.

Symbol

Characteristic

Unit

Min.

4

Max.

16

f

t

f

t

f

t

f

Main clock oscillator frequency

Reference clock frequency

PLL clock oscillator frequency

Base clock frequency

MHz

ns

(XIN)

2

4

(XRef)

(PLL)

96

128

50

(Base)

c(Base)

(CPU)

Base clock cycle time

20

40

CPU operating frequency

CPU clock cycle time

50

25

MHz

ns

(CPU)

c

Peripheral bus clock operating frequency

Peripheral bus clock cycle time

Peripheral clock source frequency

Sub clock oscillator frequency

MHz

ns

(BCLK)

c

32

MHz

kHz

(PER)

32.768

62.5

(XCIN)

Note:

1. The device is operationally guaranteed under these operating conditions.

t_c(Base)

Base clock

(Internal signal)

t_c(CPU)

CPU clock

(Internal signal)

t_c(BCLK)

Peripheral bus clock

(Internal signal)

Figure 5.1

Clock Cycle Time

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 85 of 122

R32C/118 Group

5. Electrical Characteristics

Table 5.6

Operating Conditions (5/5)

(1)

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Symbol

Characteristic

Unit

Min.

Typ. Max.

0.5

V

Allowable ripple voltage

V

= 5.0 V

= 3.0 V

= 5.0 V

= 3.0 V

Vp-p

r(VCC)

CC

0.3

dV

/dt Ripple voltage gradient

±0.3 V/ms

r(VCC)

f

Allowable ripple frequency

10

kHz

r(VCC)

Note:

1. The device is operationally guaranteed under these operating conditions.

1 / f_r(VCC)

V_CC

V_r(VCC)

Figure 5.2

Ripple Waveform

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 86 of 122

R32C/118 Group

5. Electrical Characteristics

Table 5.7

RAM Electrical Characteristics

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Measurement

Symbol

Characteristic

Unit

V

condition

Min.

2.0

Typ. Max.

V

RAM data retention voltage

in stop mode

RDR

Table 5.8

Flash Memory Electrical Characteristics

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Symbol

—

Characteristic

Unit

Min.

1000

10000

Typ. Max.

Programming and erasure endurance of flash Program area

times

µs

(1)

memory

Data area

—

4-word program time

Program area

Data area

150

300

70

900

1700 µs

500 µs

1000 µs

Lock bit-program time

Block erasure time

Program area

Data area

140

0.12

0.17

0.20

4 Kbyte block

32 Kbyte block

64 Kbyte block

3.0

s

(2)

(3)

T = 55°C

a

Data retention

—

10

years

Notes:

1. Program/erase definition

This value represents the number of erasures per block.

If the flash memory is programmed/erased n times, each block can be erased n times.

i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the

block is erased, it is considered the programming/erasure is performed just once.

However a write in the same address more than once for one erasure is disabled. (overwrite

disabled).

2. The data retention time includes the periods when the supply voltage is not applied and no clock is

provided.

3. Please contact a Renesas sales office regarding data retention time other than the above.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 87 of 122

R32C/118 Group

5. Electrical Characteristics

Table 5.9

Power Supply Circuit Timing Characteristics

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Measurement

condition

Symbol

Characteristic

Unit

ms

Min. Typ. Max.

t

Internal power supply start-up stabilization

time after the main power supply is turned on

d(P-R)

2

t_d(P-R)

Recommended

Internal power supply start-up

stabilization time after the main

power supply is turned on

V_CC

operating voltage

t_d(P-R)

Supply voltage for

internal logic

PLL oscillator-

output waveform

Figure 5.3

Power Supply Circuit Timing

Table 5.10

Electrical Characteristics of Voltage Regulator for Internal Logic

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Min. Typ. Max.

1.5

Measurement

condition

Symbol

Characteristics

Unit

V

Output voltage

VDC1

Table 5.11

Electrical Characteristics of Low Voltage Detector

(V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Measurement

Symbol

Characteristics

Unit

condition

Min. Typ. Max.

∆Vdet

Detected voltage error

±0.3

V

Vdet(R)-Vdet(F) Hysteresis width

Self-consuming current

0

V

= 5.0 V, low voltage

CC

—

4

µA

µs

detector enabled

Operation start time of low voltage detector

t

150

d(E-A)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 88 of 122

R32C/118 Group

5. Electrical Characteristics

Table 5.12

Electrical Characteristics of Oscillator

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Measurement

condition

Symbol

Characteristics

Unit

Min. Typ. Max.

f

PLL clock self-oscillation frequency

50

MHz

ms

35

65

1

SO(PLL)

(1)

t

PLL lock time

LOCK(PLL)

t

PLL jitter period (p-p)

2.0

ns

jitter(p-p)

f

On-chip oscillator frequency

62.5 125 250 kHz

(OCO)

Note:

1. This value is applicable only when the main clock oscillation is stable.

Table 5.13

Electrical Characteristics of Clock Circuitry

(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Measurement

condition

Symbol

Characteristics

Unit

Min. Typ. Max.

t

Recovery time from wait mode to low power mode

225 µs

rec(WAIT)

(1)

t

Recovery time from stop mode

rec(STOP)

Note:

1. This recovery time does not include the period until the main clock oscillator is stabilized. The CPU

starts operating before the oscillator is stabilized.

t_rec(WAIT)

Interrupt for exiting

wait mode

Recovery time from wait mode

to low power mode

Sub clock oscillator

output

On-chip oscillator

output

CPU clock

t_rec(WAIT)

t_rec(STOP)

Interrupt for exiting

stop mode

Recovery time from stop mode

Main clock oscillator

output

On-chip oscillator

output

CPU clock

t_rec(STOP)

Figure 5.4

Clock Circuit Timing

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 89 of 122

R32C/118 Group

5. Electrical Characteristics

Timing Requirements (V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.14

Flash Memory CPU Rewrite Mode Timing

Value

Min. Max.

Symbol

Characteristics

Unit

t

Read cycle time

200

0

ns

cR

t

Chip-select setup time for read

Chip-select hold time after read

Address setup time for read

Address hold time after read

Read pulse width

su(S-R)

t

h(R-S)

t

200

0

su(A-R)

t

h(R-A)

t

100

200

0

w(R)

t

Write cycle time

cW

t

Chip-select setup time for write

Chip-select hold time after write

Address setup time for write

Address hold time after write

Write pulse width

su(S-W)

t

30

0

h(W-S)

t

su(A-W)

t

30

50

h(W-A)

t

w(W)

t_cR

Read cycle

t_su(S-R)

t_h(R-S)

CS0

t_su(A-R)

t_h(R-A)

A23 to A0, BC0 to BC3

RD

t_w(R)

t_cW

Write cycle

t_su(S-W)

t_h(W-S)

CS0 to CS3

A23 to A0, BC0 to BC3

WR

t_su(A-W)

t_h(W-A)

t_w(W)

Figure 5.5

Flash Memory CPU Rewrite Mode Timing

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 90 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Table 5.15

Electrical Characteristics (1/3)

(V = 4.2 to 5.5 V, V = 0 V, T = T , and f = 50 MHz, unless otherwise noted)

(CPU)

CC

SS

a

opr

Value

Typ. Max.

Measurement

Symbol

Characteristic

Unit

condition

Min.

V

High

level

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

OH

output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

voltage P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4,

I

= -5 mA

V

- 2.0

V

OH

CC

P12_0 to P12_7, P13_0 to P13_7,

(1)

P14_3 to P14_6, P15_0 to P15_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4,

P12_0 to P12_7, P13_0 to P13_7,

I

= -200 µA V - 0.3

V

OH

CC

(1)

P14_3 to P14_6, P15_0 to P15_7

V

Low

level

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

OL

output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

voltage P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4,

I

= 5 mA

2.0

OL

P12_0 to P12_7, P13_0 to P13_7,

(1)

P14_3 to P14_6, P15_0 to P15_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

I

= 200 µA

0.45

OL

P10_0 to P10_7, P11_0 to P11_4,

P12_0 to P12_7, P13_0 to P13_7,

(1)

P14_3 to P14_6, P15_0 to P15_7

Note:

1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 91 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Table 5.16

Electrical Characteristics (2/3) (V = 4.2 to 5.5 V, V = 0 V, T = T , and

CC SS a opr

f

= 50 MHz, unless otherwise noted)

(CPU)

Value

Min. Typ. Max.

Measurement

condition

Symbol

Characteristic

Unit

V

- V

Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,

TA0IN to TA4IN, TA0OUT to TA4OUT,

TB0IN to TB5IN, CTS0 to CTS8,

T+

T-

CLK0 to CLK8, RXD0 to RXD8,

SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,

SRXD0 to SRXD6, ADTRG,

0.2

1.0

1.8

V

IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,

UD0B, UD1A, UD1B, ISCLK2, ISRXD2,

IEIN, CAN0IN, CAN1IN, CAN0WU,

(1)

CAN1WU

RESET

I

High level XIN, RESET, CNVSS, NSD,

IH

input

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

V = 5 V

5.0 µA

I

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

(2)

P15_0 to P15_7

I

Low level XIN, RESET, CNVSS, NSD,

IL

input

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

V = 0 V

-5.0 µA

I

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

(2)

P15_0 to P15_7

R

Pull-up

resistor

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

PULLUP

V = 0 V

30

50 170 kΩ

I

P13_0 to P13_7, P14_1, P14_3 to P14_6,

(2)

P15_0 to P15_7

R

Feedback XIN

resistor

XIN

f

1.5

15

MΩ

Feedback XCIN

resistor

XCIN

f

Notes:

1. Pins INT6 to INT8 are available in the 144-pin package only.

2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 92 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Table 5.17

Electrical Characteristics (3/3)

(V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Characte

ristic

Symbol

I_CC

Measurement condition

Unit

mA

Min. Typ. Max.

Power

supply

current

In single-chip mode,

f_(CPU)= 50 MHz, f_(BCLK)= 25 MHz,

output pins are left open

and others are

f_(XIN)= 8 MHz,

35

12

50

Active: XIN, PLL,

connected to V

SS

Stopped: XCIN, OCO

f

_(CPU)= f_SO(PLL)/24 MHz,

XIN-XOUT

Drive power: low

mA

Active: PLL (self-oscillation),

Stopped: XIN, XCIN, OCO

XCIN-XCOUT

Drive power: low

f_(CPU)= f_(BCLK)= f_(XIN)/256 MHz,

f

_(XIN)= 8 MHz,

1.2

Active: XIN,

Stopped: PLL, XCIN, OCO

f_(CPU)= f_(BCLK)= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown

220

230

µA

f

_(CPU)= f_(BCLK)= f_(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown

f_(CPU)= f_(BCLK)= f_(XIN)/256 MHz,

f_(XIN)= 8 MHz,

960 1600 µA

Active: XIN,

Stopped: PLL, XCIN, OCO,

T_a= 25°C, Wait mode

f_(CPU)= f_(BCLK)= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown,

T_a= 25°C, Wait mode

8

140

µA

f

_(CPU)= f_(BCLK)= f_(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown,

T_a= 25°C, Wait mode

10

5

150

70

µA

Stopped: all clocks,

Main regulator: shutdown,

T_a= 25°C

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 93 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Table 5.18

A/D Conversion Characteristics (V = AV = V

= 4.2 to 5.5 V, V = AV = 0 V,

CC

REF SS SS

T = T , and f = 25 MHz, unless otherwise noted)

(BCLK)

a

opr

Value

Min. Typ. Max.

Symbol

Characteristic

Measurement condition

Unit

Resolution

V

= V

CC

—

10 Bits

REF

Absolute error

= V = 5 V

AN_0 to AN_7,

CC

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

±3 LSB

—

(1)

ANEX0, ANEX1

External op-amp

connection mode

±7 LSB

±3 LSB

INL

Integral non-linearity

error

V

= V = 5 V

AN_0 to AN_7,

REF

CC

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

(1)

ANEX0, ANEX1

External op-amp

connection mode

±7 LSB

±1 LSB

DNL

Differential non-linearity

error

—

Offset error

Gain error

±3 LSB

—

LADDER

CONV

R

Resistor ladder

V

= V

4

20

kΩ

REF

CC

t

Conversion time

(10 bits)

φ

= 16 MHz, with sample and hold

AD

2.06

µs

function

= 16 MHz, without sample and hold

φ

AD

3.69

1.75

µs

function

= 16 MHz, with sample and hold

Conversion time

(8 bits)

φ

AD

CONV

function

= 16 MHz, without sample and hold

φ

AD

3.06

function

= 16 MHz

Sampling time

φ

AD

0.188

µs

V

SAMP

V

Analog input voltage

V

REF

0

0.25

1

IA

φ

Operating clock

frequency

without sample and hold function

with sample and hold function

16 MHz

AD

Note:

1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 94 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Table 5.19

D/A Conversion Characteristics (V = AV = V

= 4.2 to 5.5 V, V = AV = 0 V,

CC

REF SS SS

and T = T , unless otherwise noted)

a

opr

Value

Symbol

Characteristic

Measurement condition

Unit

Min. Typ. Max.

—

Resolution

8

1.0

3

Bits

%

Absolute precision

Settling time

t

µs

S

R

I

Output resistance

4

10

20

kΩ

O

(1)

Reference input current

1.5 mA

VREF

Note:

1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The

resistor ladder for A/D converter is not considered.

Even when the VCUT bit in the AD0CON1 register is set to 0 (V

disconnected), I

is supplied.

REF

VREF

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 95 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.20

External Clock Input

Value

Min.

Symbol

t

Characteristic

Unit

Max.

250

External clock input period

62.5

25

ns

%

(X)

c

t

External clock input high level pulse width

External clock input low level pulse width

External clock input rise time

w(XH)

w(XL)

25

5

(X)

r

External clock input fall time

(X)

f

t

/ t

External clock input duty

40

60

w

c

Table 5.21

External Bus Timing

Value

Symbol

t

Characteristic

Unit

Min.

Max.

Data setup time for read

Data hold time after read

Data disable time after read

ns

40

0

(D-R)

su

t

(R-D)

h

0.5 × t

+ 10

(R-D)

dis

c(Base)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 96 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.22

Timer A Input (Counting input in event counter mode)

Value

Min. Max.

Symbol

t

Characteristic

Unit

TAiIN input clock period

200

80

ns

(TA)

c

t

TAiIN input high level pulse width

TAiIN input low level pulse width

(TAH)

w

80

(TAL)

Table 5.23

Timer A Input (Gating input in timer mode)

Value

Symbol

t

Characteristic

Unit

Min.

400

Max.

TAiIN input clock period

ns

(TA)

c

t

TAiIN input high level pulse width

TAiIN input low level pulse width

180

(TAH)

w

(TAL)

Table 5.24

Timer A Input (External trigger input in one-shot timer mode)

Value

Symbol

t

Characteristic

Unit

Min.

200

TAiIN input clock period

ns

(TA)

c

t

TAiIN input high level pulse width

TAiIN input low level pulse width

80

(TAH)

w

(TAL)

Table 5.25

Timer A Input (External trigger input in pulse-width modulation mode)

Value

Symbol

t

Characteristic

Unit

Min.

80

TAiIN input high level pulse width

TAiIN input low level pulse width

ns

(TAH)

w

t

80

(TAL)

Table 5.26

Timer A Input (Increment/decrement count switching input in event counter mode)

Value

Symbol

t

Characteristic

TAiOUT input clock period

Unit

Min.

Max.

2000

ns

(UP)

c

t

TAiOUT input high level pulse width

TAiOUT input low level pulse width

TAiOUT input setup time

1000

400

(UPH)

w

su

(UPL)

(UP-TIN)

TAiOUT input hold time

400

(TIN-UP)

h

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 97 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.27

Timer B Input (Counting input in event counter mode)

Value

Min. Max.

Symbol

Characteristic

Unit

t

TBiIN input clock period (one edge counting)

200

80

ns

c(TB)

t

TBiIN input high level pulse width (one edge counting)

TBiIN input low level pulse width (one edge counting)

TBiIN input clock period (both edges counting)

(TBH)

w

t

80

(TBL)

200

80

(TB)

c

TBiIN input high level pulse width (both edges counting)

TBiIN input low level pulse width (both edges counting)

(TBH)

w

(TBL)

w

80

Table 5.28

Timer B Input (Pulse period measure mode)

Value

Max.

Symbol

Characteristic

Unit

Min.

400

t

TBiIN input clock period

ns

c(TB)

t

TBiIN input high level pulse width

TBiIN input low level pulse width

180

(TBH)

w

t

(TBL)

Table 5.29

Timer B Input (Pulse-width measure mode)

Value

Max.

Symbol

Characteristic

Unit

Min.

400

t

TBiIN input clock period

ns

c(TB)

t

TBiIN input high level pulse width

TBiIN input low level pulse width

180

(TBH)

w

t

(TBL)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 98 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Timing requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.30

Serial Interface

Value

Min. Max.

Symbol

t

Characteristic

Unit

CLKi input clock period

200

80

90

ns

(CK)

c

t

CLKi input high level pulse width

CLKi input low level pulse width

RXDi input setup time

(CKH)

w

su

(CKL)

(D-C)

RXDi input hold time

(C-D)

h

Table 5.31

A/D Trigger Input

Value

Symbol

t

Characteristic

ADTRG input high level pulse width

Unit

Min.

Max.

3

(ADH)

w

---------

ns

Hardware trigger input high level pulse width

φ

AD

t

ADTRG input low level pulse width

Hardware trigger input high level pulse width

(ADL)

w

125

Table 5.32

External Interrupt INTi Input

Value

Min.

250

+ 200

Symbol

t

Characteristic

Unit

Max.

INTi input high level pulse width

INTi input low level pulse width

Edge sensitive

Level sensitive

Edge sensitive

Level sensitive

ns

(INH)

w

t

(CPU)

c

t

250

+ 200

(INL)

w

(CPU)

Table 5.33

Intelligent I/O

Value

Min. Max.

Symbol

Characteristic

Unit

t

ISCLK2 input clock period

600

270

150

100

ns

c(ISCLK2)

t

ISCLK2 input high level pulse width

ISCLK2 input low level pulse width

ISRXD2 input setup time

w(ISCLK2H)

t

w(ISCLK2L)

t

su(RXD-ISCLK2)

t

ISRXD2 input hold time

h(ISCLK2-RXD)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 99 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Timing requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

2

Table 5.34

Multi-master I C-bus Interface

Value

Symbol

Characteristic

Standard-mode

Fast-mode

Min.

Unit

Min.

600

Max.

t

MSCL input high level pulse width

MSCL input low level pulse width

MSCL input rise time

600

ns

w(SCLH)

t

w(SCLL)

t

1000

300

r(SCL)

t

MSCL input fall time

f(SCL)

t

MSDA input rise time

1000

300

r(SDA)

t

MSDA input fall time

f(SDA)

t

MSCL high level hold time after start

condition/restart condition

h(SDA-SCL)S

su(SCL-SDA)P

w(SDAH)P

(1)

2 × t

4 × t

+ 40

ns

c(φIIC)

MSCL high level setup time for

restart condition/stop condition

MSDA high level pulse width after

stop condition

t

MSDA input setup time

MSDA input hold time

100

0

100

0

ns

su(SDA-SCL)

h(SCL-SDA)

Note:

1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in

the I2CSSCR register:

t

= SSC ÷ 2 × t

+ 40 [ns]

h(SDA-SCL)S

c(φIIC)

= (SSC ÷ 2 + 1) × t

+ 40 [ns]

su(SCL-SDA)P

c(φIIC)

= (SSC + 1) × t

+ 40 [ns]

c(φIIC)

w(SDAH)P

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 100 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Switching Characteristics (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.35

External Bus Timing (Separate bus)

Value

Measurement

Symbol

t

Characteristic

Unit

condition

Min.

Max.

(1)

Chip-select setup time for read

Chip-select hold time after read

Address setup time for read

Address hold time after read

Read pulse width

ns

(S-R)

su

t

- 15

(R-S)

h

c(Base)

(1)

(A-R)

su

t

(R-A)

h

c(Base)

(1)

(R)

w

(1)

Chip-select setup time for write

Chip-select hold time after write

Address setup time for write

Address hold time after write

Write pulse width

(S-W)

su

Refer to

Figure 5.6

1.5 × t

- 15

c(Base)

(W-S)

h

(1)

(A-W)

su

1.5 × t

- 15

(W-A)

h

c(Base)

(1)

(W)

w

(1)

Data setup time for write

Data hold time after write

(D-W)

su

0

(W-D)

h

Note:

1. The value is calculated by the following formulas based on the base clock cycles (t

) and

c(Base)

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For the details of how to set values,

refer to the Hardware manual.

t

= t

= Tsu(A-R) × t

- 15 [ns]

su(S-R)

su(A-R)

c(Base)

= Tw(R) × t

- 10 [ns]

w(R)

c(Base)

= t

= Tsu(A-W) × t

- 15 [ns]

su(S-W)

su(A-W)

c(Base)

= t

= Tw(W) × t

- 10 [ns]

w(W)

su(D-W)

c(Base)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 101 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Switching Characteristics (V = 4.2 to 5.5 V, V = 0 V, T = T , and unless otherwise noted)

CC

SS

a

opr

Table 5.36

External Bus Timing (Multiplexed bus)

Value

Measurement

condition

Symbol

t

Characteristic

Unit

Min.

Max.

(1)

Chip-select setup time for ALE

Chip-select hold time after read

Address setup time for ALE

Address hold time after ALE

Address hold time after read

ALE-read delay time

ns

(S-ALE)

su

t

1.5 × t

- 15

h(R-S)

c(Base)

(1)

su(A-ALE)

h(ALE-A)

h(R-A)

0.5 × t

1.5 × t

- 5

c(Base)

- 15

c(Base)

0.5 × t

- 5 0.5 × t

+ 10

d(ALE-R)

w(ALE)

dis(R-A)

w(R)

c(Base)

(1)

c(Base)

ALE pulse width

Refer to

Figure 5.6

Address disable time after read

Read pulse width

8

(1)

Chip-select hold time after write

Address hold time after write

ALE-write delay time

1.5 × t

- 15

h(W-S)

h(W-A)

d(ALE-W)

w(W)

c(Base)

- 15

c(Base)

0.5 × t

- 5 0.5 × t

+ 10

c(Base)

(1)

c(Base)

Write pulse width

(1)

Data setup time for write

Data hold time after write

su(D-W)

h(W-D)

0.5 × t

c(Base)

Note:

1. The value is calculated by the following formulas based on the base clock cycles (t

) and

c(Base)

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For the details of how to set values,

refer to the Hardware manual.

t

= t

= (Tsu(A-R) - 0.5) × t

-15 [ns]

su(S-ALE)

su(A-ALE)

w(ALE)

c(Base)

= Tw(R) × t

-10 [ns]

w(R)

c(Base)

= t

= Tw(W) × t

-10 [ns]

w(W)

su(D-W)

c(Base)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 102 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 5 V

Switching Characteristics (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.37

Serial Interface

Value

Max.

Measurement

condition

Symbol

t

Characteristic

Unit

Min.

TXDi output delay time

TXDi output hold time

80

ns

(C-Q)

d

h

Refer to

Figure 5.6

t

0

(C-Q)

Table 5.38

Intelligent I/O

Value

Measurement

condition

Symbol

t

Characteristic

Unit

Min.

Max.

180

ISTXD2 output delay time

ISTXD2 output hold time

ns

(ISCLK2-TXD)

d

h

Refer to

Figure 5.6

t

0

(ISCLK2-RXD)

2

Table 5.39

Multi-master I C-bus Interface (Standard-mode)

Value

Measurement

Characteristic

Symbol

Unit

condition

Min.

2

Max.

t

MSCL output fall time

ns

f(SCL)

t

MSDA output fall time

2

f(SDA)

t

MSCL output delay time after start

condition/restart condition

d(SDA-SCL)S

20 × t

- 120 52 × t - 40

c(φIIC)

ns

c(φIIC)

Refer to

Figure 5.6

t

Restart condition/stop condition

output delay time after MSCL

becomes high

d(SCL-SDA)P

20 × t

2 × t

+ 40 52 × t

+ 120

ns

c(φIIC)

t

MSDA output delay time

+ 40 3 × t

c(φIIC) c(φIIC)

d(SCL-SDA)

2

Table 5.40

Multi-master I C-bus Interface (Fast-mode)

Value

Measurement

Symbol

Characteristic

Unit

condition

Min.

Max.

(1)

t

MSCL output fall time

MSDA output fall time

ns

2

f(SCL)

(1)

t

2

f(SDA)

t

MSCL output delay time after start

condition/restart condition

d(SDA-SCL)S

10 × t

- 120 26 × t - 40

c(φIIC)

ns

c(φIIC)

Refer to

Figure 5.6

t

Restart condition/stop condition

output delay time after MSCL

becomes high

d(SCL-SDA)P

10 × t

2 × t

+ 40 26 × t

+ 120

ns

c(φIIC)

t

MSDA output delay time

+ 40 3 × t

c(φIIC) c(φIIC)

d(SCL-SDA)

Note:

2

1. External circuits are required to satisfy the I C-bus specification.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 103 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Table 5.41

Electrical Characteristics (1/3) (V = 3.0 to 3.6 V, V = 0 V, T = T , and

CC

SS

a

opr

f

= 50 MHz, unless otherwise noted)

(CPU)

Value

Measurement

condition

Symbol

Characteristic

Unit

V

Min.

Typ. Max.

V

High

level

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

voltage P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4,

OH

I

= -1 mA

V

- 0.6

V

OH

CC

P12_0 to P12_7, P13_0 to P13_7,

(1)

P14_3 to P14_6, P15_0 to P15_7

V

Low

level

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

OL

output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

voltage P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4,

I

= 1 mA

0.5

V

OL

P12_0 to P12_7, P13_0 to P13_7,

(1)

P14_3 to P14_6, P15_0 to P15_7

Notes:

1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 104 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Table 5.42

Electrical Characteristics (2/3) (V = 3.0 to 3.6 V, V = 0 V, T = T , and

CC SS a opr

f

= 50 MHz, unless otherwise noted)

(CPU)

Value

Min. Typ. Max.

Measurement

condition

Symbol

Characteristic

Unit

V

- V

Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,

TA0IN to TA4IN, TA0OUT to TA4OUT,

TB0IN to TB5IN, CTS0 to CTS8,

T+

T-

CLK0 to CLK8, RXD0 to RXD8,

SCL0 to SCL6, SDA0 to SDA6,

0.2

1.0

V

SS0 to SS6, SRXD0 to SRXD6, ADTRG,

IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,

UD0B, UD1A, UD1B, ISCLK2, ISRXD2,

IEIN, CAN0IN, CAN1IN, CAN0WU,

(1)

CAN1WU

RESET

1.8

4.0

V

I

High level XIN, RESET, CNVSS, NSD,

IH

input

current

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4,

P12_0 to P12_7, P13_0 to P13_7, P14_1,

V = 3.3 V

µA

I

(2)

P14_3 to P14_6, P15_0 to P15_7

I

Low level XIN, RESET, CNVSS, NSD,

IL

input

current

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_4,

P12_0 to P12_7, P13_0 to P13_7, P14_1,

V = 0 V

-4.0 µA

I

(2)

P14_3 to P14_6, P15_0 to P15_7

R

Pull-up

resistor

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

PULLUP

P5_0 to P5_3, P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

V = 0 V

50 100 500 kΩ

I

(2)

P15_0 to P15_7

R

Feedback XIN

resistor

XIN

f

3

MΩ

Feedback XCIN

resistor

XCIN

f

25

Notes:

1. Pins INT6 to INT8 are available in the 144-pin package only.

2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 105 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Table 5.43

Electrical Characteristics (3/3)

(V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Value

Characte

ristic

Symbol

I_CC

Measurement condition

Unit

mA

Min. Typ. Max.

Power

supply

current

In single-chip mode,

f_(CPU)= 50 MHz, f_(BCLK)= 25 MHz,

output pins are left open

and others are

f_(XIN)= 8 MHz,

32

9

45

Active: XIN, PLL,

connected to V_SS

Stopped: XCIN, OCO

f_(CPU)= f_SO(PLL)/24 MHz,

XIN-XOUT

Drive power: low

mA

µA

Active: PLL (self-oscillation),

Stopped: XIN, XCIN, OCO

XCIN-XCOUT

Drive power: low

f_(CPU)= f_(BCLK)= f_(XIN)/256 MHz,

f_(XIN)= 8 MHz,

670

Active: XIN,

Stopped: PLL, XCIN, OCO

f_(CPU)= f_(BCLK)= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown

180

190

µA

f_(CPU)= f_(BCLK)= f_(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown

f_(CPU)= f_(BCLK)= f_(XIN)/256 MHz,

f_(XIN)= 8 MHz,

500 900

µA

Active: XIN,

Stopped: PLL, XCIN, OCO,

T_a= 25°C, Wait mode

f_(CPU)= f_(BCLK)= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown,

T_a= 25°C, Wait mode

8

140

f

_(CPU)= f_(BCLK)= f_(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown,

T_a= 25°C, Wait mode

10

5

150

70

µA

Stopped: all clocks,

Main regulator: shutdown,

T_a= 25°C

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 106 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Table 5.44

A/D Conversion Characteristics (V = AV = V

= 3.0 to 3.6 V, V = AV = 0 V,

CC

REF SS SS

T = T , and f = 25 MHz, unless otherwise noted)

(BCLK)

a

opr

Value

Symbol

Characteristic

Measurement condition

Unit

Bits

Min. Typ. Max.

10

Resolution

V

= V

CC

—

REF

Absolute error

V

= V = 3.3 V AN_0 to AN_7,

CC

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

±5

±7

±5

LSB

—

(1)

ANEX0, ANEX1

External op-amp

connection mode

INL

Integral non-linearity

error

V

= V = 3.3 V AN_0 to AN_7,

REF

CC

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

(1)

ANEX0, ANEX1

External op-amp

connection mode

±7

±1

LSB

DNL

Differential non-

linearity error

V

= V = 3.3 V

REF

CC

—

Offset error

Gain error

±3

LSB

kΩ

—

LADDER

CONV

R

Resistor ladder

= V

4

20

REF

CC

t

Conversion time

(10 bits)

φ

= 10 MHz,

AD

3.3

µs

with sample and hold function

= 10 MHz,

Conversion time

(8 bits)

φ

AD

CONV

SAMP

2.8

0.3

µs

with sample and hold function

= 10 MHz

Sampling time

φ

AD

V

Analog input voltage

V

0

0.25

1

V

IA

REF

φ

Operating clock

frequency

without sample and hold function

with sample and hold function

10

MHz

AD

10

Note:

1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 107 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Table 5.45

D/A Conversion Characteristics (V = AV = V

= 3.0 to 3.6 V, V = AV = 0 V,

CC

REF SS SS

and T = T , unless otherwise noted)

a

opr

Measurement condition

Value

Symbol

Characteristic

Unit

Min. Typ. Max.

—

Resolution

8

1.0

3

Bits

%

Absolute precision

Settling time

t

µs

S

R

I

Output resistance

4

10

20

kΩ

O

(1)

Reference input current

1.0

mA

VREF

Note:

1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The

resistor ladder for A/D converter is not considered.

Even when the VCUT bit in the AD0CON1 register is set to 0 (V

disconnected), I

is supplied.

REF

VREF

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 108 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.46

External Clock Input

Value

Min.

Symbol

t

Characteristic

Unit

Max.

250

External clock input period

62.5

25

ns

%

(X)

c

t

External clock input high level pulse width

External clock input low level pulse width

External clock input rise time

w(XH)

w(XL)

r(X)

25

5

External clock input fall time

(X)

f

t

/ t

External clock input duty

40

60

w

c

Table 5.47

External Bus Timing

Value

Symbol

Characteristic

Unit

Min.

Max.

t

Data setup time for read

Data hold time after read

Data disable time after read

ns

40

0

su(D-R)

t

h(R-D)

t

0.5 × t

+ 10

dis(R-D)

c(Base)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 109 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.48

Timer A Input (Counting input in event counter mode)

Value

Min. Max.

Symbol

Characteristic

Unit

t

TAiIN input clock period

200

80

ns

c(TA)

t

TAiIN input high level pulse width

TAiIN input low level pulse width

w(TAH)

t

80

w(TAL)

Table 5.49

Timer A Input (Gating input in timer mode)

Value

Symbol

Characteristic

Unit

Min.

400

180

Max.

t

TAiIN input clock period

ns

c(TA)

t

TAiIN input high level pulse width

TAiIN input low level pulse width

w(TAH)

t

w(TAL)

Table 5.50

Timer A Input (External trigger input in one-shot timer mode)

Value

Symbol

Characteristic

Unit

Min.

200

80

t

TAiIN input clock period

ns

c(TA)

t

TAiIN input high level pulse width

TAiIN input low level pulse width

w(TAH)

t

80

w(TAL)

Table 5.51

Timer A Input (External trigger input in pulse-width modulation mode)

Value

Symbol

Characteristic

Unit

Min.

80

t

TAiIN input high level pulse width

TAiIN input low level pulse width

ns

w(TAH)

t

80

(TAL)

w

Table 5.52

Timer A Input (Increment/decrement count switching input in event counter mode)

Value

Symbol

Characteristic

TAiOUT input clock period

Unit

Min.

2000

1000

400

Max.

t

ns

c(UP)

t

TAiOUT input high level pulse width

TAiOUT input low level pulse width

TAiOUT input setup time

w(UPH)

t

w(UPL)

t

su(UP-TIN)

t

TAiOUT input hold time

400

h(TIN-UP)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 110 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.53

Timer B Input (Counting input in event counter mode)

Value

Min. Max.

Symbol

Characteristic

Unit

t

TBiIN input clock period (one edge counting)

200

80

ns

c(TB)

t

TBiIN input high level pulse width (one edge counting)

TBiIN input low level pulse width (one edge counting)

TBiIN input clock period (both edges counting)

w(TBH)

t

80

w(TBL)

t

200

80

c(TB)

t

TBiIN input high level pulse width (both edges counting)

TBiIN input low level pulse width (both edges counting)

w(TBH)

t

80

w(TBL)

Table 5.54

Timer B Input (Pulse period measure mode)

Value

Max.

Symbol

Characteristic

Unit

Min.

400

180

t

TBiIN input clock period

ns

c(TB)

t

TBiIN input high level pulse width

TBiIN input low level pulse width

w(TBH)

t

w(TBL)

Table 5.55

Timer B Input (Pulse-width measure mode)

Value

Max.

Symbol

Characteristic

Unit

Min.

400

180

t

TBiIN input clock period

ns

c(TB)

t

TBiIN input high level pulse width

TBiIN input low level pulse width

w(TBH)

t

w(TBL)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 111 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.56

Serial Interface

Value

Min. Max.

Symbol

Characteristic

Unit

t

CLKi input clock period

200

80

90

ns

c(CK)

t

CLKi input high level pulse width

CLKi input low level pulse width

RXDi input setup time

w(CKH)

t

w(CKL)

t

su(D-C)

t

RXDi input hold time

h(C-D)

Table 5.57

A/D Trigger Input

Value

Symbol

Characteristic

ADTRG input high level pulse width

Unit

ns

Min.

Max.

t

3

w(ADH)

---------

Hardware trigger input high level pulse width

φ

AD

t

ADTRG input low level pulse width

Hardware trigger input high level pulse width

w(ADL)

125

ns

Table 5.58

External Interrupt INTi Input

Value

Min.

250

+ 200

Symbol

Characteristic

Unit

Max.

t

INTi input high level pulse width

INTi input low level pulse width

Edge sensitive

Level sensitive

Edge sensitive

Level sensitive

ns

w(INH)

t

(CPU)

c

t

250

+ 200

(INL)

w

(CPU)

Table 5.59

Intelligent I/O

Value

Min. Max.

Symbol

t

Characteristic

Unit

ISCLK2 input clock period

600

270

150

100

ns

(ISCLK2)

c

t

ISCLK2 input high level pulse width

ISCLK2 input low level pulse width

ISRXD2 input setup time

(ISCLK2H)

(ISCLK2L)

w

su

(RXD-ISCLK2)

ISRXD2 input hold time

(ISCLK2-RXD)

h

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 112 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

2

Table 5.60

Multi-master I C-bus Interface

Value

Symbol

Characteristic

Standard-mode

Fast-mode

Min.

Unit

Min.

600

Max.

t

MSCL input high level pulse width

MSCL input low level pulse width

MSCL input rise time

600

ns

w(SCLH)

t

w(SCLL)

t

1000

300

r(SCL)

t

MSCL input fall time

f(SCL)

t

MSDA input rise time

1000

300

r(SDA)

t

MSDA input fall time

f(SDA)

t

MSCL high level hold time after start

condition/restart condition

h(SDA-SCL)S

su(SCL-SDA)P

w(SDAH)P

(1)

2 × t

4 × t

+ 40

ns

c(φIIC)

MSCL high level setup time for

restart condition/stop condition

MSDA high level pulse width after

stop condition

t

MSDA input setup time

MSDA input hold time

100

0

100

0

ns

su(SDA-SCL)

h(SCL-SDA)

Note:

1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in

the I2CSSCR register:

t

= SSC ÷ 2 × t

+ 40 [ns]

h(SDA-SCL)S

c(φIIC)

= (SSC ÷ 2 + 1) × t

+ 40 [ns]

su(SCL-SDA)P

c(φIIC)

= (SSC + 1) × t

+ 40 [ns]

c(φIIC)

w(SDAH)P

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 113 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Switching Characteristics (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.61

External Bus Timing (Separate bus)

Value

Measurement

Symbol

Characteristic

Unit

condition

Min.

Max.

(1)

t

Chip-select setup time for read

Chip-select hold time after read

Address setup time for read

Address hold time after read

Read pulse width

ns

su(S-R)

t

- 15

h(R-S)

c(Base)

(1)

t

su(A-R)

t

h(R-A)

c(Base)

(1)

t

w(R)

(1)

t

Chip-select setup time for write

Chip-select hold time after write

Address setup time for write

Address hold time after write

Write pulse width

su(S-W)

Refer to

Figure 5.6

t

1.5 × t

- 15

c(Base)

h(W-S)

(1)

t

su(A-W)

t

1.5 × t

- 15

h(W-A)

c(Base)

(1)

t

w(W)

(1)

t

Data setup time for write

Data hold time after write

su(D-W)

t

0

h(W-D)

Note:

1. The value is calculated by the following formulas based on the base clock cycles (t

) and

c(Base)

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For the details of how to set values,

refer to the Hardware manual.

t

= t

= Tsu(A-R) × t

- 15 [ns]

su(S-R)

su(A-R)

c(Base)

= Tw(R) × t

- 10 [ns]

w(R)

c(Base)

= t

= Tsu(A-W) × t

- 15 [ns]

su(S-W)

su(A-W)

c(Base)

= t

= Tw(W) × t

- 10 [ns]

w(W)

su(D-W)

c(Base)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 114 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Switching Characteristics (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.62

External Bus Timing (Multiplexed bus)

Value

Measurement

Symbol

Characteristic

Unit

condition

Min.

Max.

(1)

t

Chip-select setup time for ALE

Chip-select hold time after read

Address setup time for ALE

Address hold time after ALE

Address hold time after read

ALE-read delay time

ns

su(S-ALE)

t

1.5 × t

- 15

h(R-S)

c(Base)

(1)

t

su(A-ALE)

t

0.5 × t

1.5 × t

- 5

c(Base)

h(ALE-A)

t

- 15

c(Base)

h(R-A)

t

0.5 × t

- 5 0.5 × t

+ 10

d(ALE-R)

c(Base)

(1)

t

ALE pulse width

(ALE)

w

Refer to

Figure 5.6

t

Address disable time after read

Read pulse width

8

dis(R-A)

w(R)

(1)

Chip-select hold time after write

Address hold time after write

ALE-write delay time

1.5 × t

- 15

h(W-S)

h(W-A)

d(ALE-W)

w(W)

c(Base)

- 15

c(Base)

0.5 × t

- 5 0.5 × t

+ 10

c(Base)

(1)

c(Base)

Write pulse width

(1)

Data setup time for write

Data hold time after write

su(D-W)

h(W-D)

0.5 × t

c(Base)

Note:

1. The value is calculated by the following formulas based on the base clock cycles (t

) and

c(Base)

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For the details of how to set values,

refer to the Hardware manual.

t

= t

= (Tsu(A-R) - 0.5) × t

-15 [ns]

su(S-ALE)

su(A-ALE)

c(Base)

= (Tsu(A-R) - 0.5) × t

- 20 [ns]

w(ALE)

c(Base)

= Tw(R) × t

-10 [ns]

w(R)

c(Base)

= t

= Tw(W) × t

-10 [ns]

w(W)

su(D-W)

c(Base)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 115 of 122

R32C/118 Group

5. Electrical Characteristics

V_CC= 3.3 V

Switching Characteristics (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)

CC

SS

a

opr

Table 5.63

Serial Interface

Value

Max.

Measurement

condition

Symbol

t

Characteristic

Unit

Min.

TXDi output delay time

TXDi output hold time

80

ns

(C-Q)

d

h

Refer to

Figure 5.6

t

0

(C-Q)

Table 5.64

Intelligent I/O

Value

Measurement

condition

Symbol

t

Characteristic

Unit

Min.

Max.

180

ISTXD2 output delay time

ISTXD2 output hold time

ns

(ISCLK2-TXD)

d

h

Refer to

Figure 5.6

t

0

(ISCLK2-RXD)

2

Table 5.65

Multi-master I C-bus Interface (Standard-mode)

Value

Measurement

Characteristic

Symbol

Unit

condition

Min.

2

Max.

t

MSCL output fall time

ns

f(SCL)

t

MSDA output fall time

2

f(SDA)

t

MSCL output delay time after start

condition/restart condition

d(SDA-SCL)S

20 × t

- 120 52 × t - 40

c(φIIC)

ns

c(φIIC)

Refer to

Figure 5.6

t

Restart condition/stop condition

output delay time after MSCL

becomes high

d(SCL-SDA)P

20 × t

2 ×t

+ 40 52 × t

+ 120

ns

c(φIIC)

t

MSDA output delay time

+ 40 3 × t

c(φIIC) c(φIIC)

d(SCL-SDA)

2

Table 5.66

Multi-master I C-bus Interface (Fast-mode)

Value

Measurement

Symbol

Characteristic

Unit

condition

Min.

Max.

(1)

t

MSCL output fall time

MSDA output fall time

ns

2

f(SCL)

(1)

t

2

f(SDA)

t

MSCL output delay time after start

condition/restart condition

d(SDA-SCL)S

10 × t

- 120 26 × t - 40

c(φIIC)

ns

c(φIIC)

Refer to

Figure 5.6

t

Restart condition/stop condition

output delay time after MSCL

becomes high

d(SCL-SDA)P

10 × t

2 × t

+ 40 26 × t

+ 120

ns

c(φIIC)

t

MSDA output delay time

+ 40 3 × t

c(φIIC) c(φIIC)

d(SCL-SDA)

Note:

2

1. External circuits are required to satisfy the I C-bus specification.

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 116 of 122

R32C/118 Group

5. Electrical Characteristics

MCU

Pin to be

measured

30 pF

Figure 5.6

Switching Characteristic Measurement Circuit

t_c(X)

XIN

t_w(XH)

t_w(XL)

t_r(X)

t_f(X)

Figure 5.7

External Clock Input Timing

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 117 of 122

R32C/118 Group

5. Electrical Characteristics

External bus timing (Separate bus)

Read cycle

t_cR

t_su(S-R)

t_h(R-S)

CS0 to CS3

t_su(A-R)

t_h(R-A)

A23 to A0, BC0 to BC3

t_w(R)

RD

t_su(D-R)

t_h(R-D)

D31 to D0

Write cycle

t_cW

t_su(S-W)

t_h(W-S)

CS0 to CS3

t_su(A-W)

t_h(W-A)

A23 to A0, BC0 to BC3

WR, WR0 to WR3

D31 to D0

t_w(W)

t_su(D-W)

t_h(W-D)

Measurement conditions

V_CC= 4.2 to 5.5 V

V_CC= 3.0 to 3.6 V

Item

2.5 V

0.8 V

2.0 V

0.8 V

1.5 V

0.5 V

2.4 V

0.5 V

V_IH

V_IL

Criterion for

input voltage

V_OH

V_OL

Criterion for

output voltage

Figure 5.8

External Bus Timing (Separate Bus)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 118 of 122

R32C/118 Group

5. Electrical Characteristics

External bus timing (Multiplexed bus)

Read timing

t_cR

t_su(S-ALE)

t_su(A-ALE)

t_w(ALE)

t_h(R-S)

CS0 to CS3

t_h(R-A)

A23 to A8, BC0 to BC3

ALE

t_h(ALE-A)

t_su(A-ALE)

t_dis(R-A)

t_su(D-R)

Data

t_h(R-D)

t_dis(R-D)

t_h(R-D)

A15/D15 to A0/D0,

BC0/D0, BC2/D1

Address

t_d(ALE-R)

t_w(R)

RD

t_su(D-R)

D31 to D8

t_cW

Write cycle

t_su(S-ALE)

t_su(A-ALE)

t_w(ALE)

t_h(W-S)

CS0 to CS3

A23 to A8, BC0 to BC3

ALE

t_h(W-A)

t_su(A-ALE)

t_h(ALE-A)

t_su(D-W)

Data

t_h(W-D)

A15/D15 to A0/D0,

BC0/D0, BC2/D1

Address

t_d(ALE-W)

t_w(W)

WR, WR0 to WR3

D31 to D8

t_su(D-W)

t_h(W-D)

Measurement conditions

Item

V_CC= 4.2 to 5.5 V

V_CC= 3.0 to 3.6 V

2.5 V

0.8 V

2.0 V

0.8 V

1.5 V

0.5 V

2.4 V

0.5 V

V_IH

V_IL

Criterion for

input voltage

V_OH

V_OL

Criterion for

output voltage

Figure 5.9

External Bus Timing (Multiplexed Bus)

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 119 of 122

R32C/118 Group

5. Electrical Characteristics

t_c(TA)

t_w(TAL)

t_w(TAH)

TAiIN input

t_c(UP)

t_w(UPL)

t_w(UPH)

TAiOUT input

In event counter mode

TAiOUT input (input for increment/

decrement count switching)

t_su(UP-TIN)

t_h(TIN-UP)

TAiIN input (in falling edge counting)

TAiIN input (in rising edge counting)

t_c(TB)

t_w(TBH)

t_w(TBL)

TBiIN input

t_c(CK)

t_w(CKH)

t_w(CKL)

CLKi

TXDi

RXDi

t_d(C-Q)

t_h(C-Q)

t_su(D-C)

t_h(C-D)

t_w(ADL)

t_w(ADH)

ADTRG input

INTi input

t_w(INL)

t_w(INH)

2 CPU clock cycles +

300 ns or more

2 CPU clock cycles +

300 ns or more

NMI input

Figure 5.10 Timing of Peripheral Functions

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 120 of 122

R32C/118 Group

5. Electrical Characteristics

t_c(SCL)

MSCL

MSDA

t_w(SCLH)

t_w(SCLL)

t_r(SCL)

t_f(SCL)

t_r(SDA)

t_f(SDA)

t_w(SDAH)P

t_su(SCL-SDA)P

t_h(SDA-SCL)S

t_su(SCL-SDA)P

MSCL

MSDA (input)

t_h(SDA-SCL)S

t_d(SDA-SCL)S

t_d(SCL-SDA)P

MSCL

MSDA (output)

t_d(SDA-SCL)S

t_su(SDA-SCL)

t_h(SCL-SDA)

MSCL

MSDA (input)

t_d(SCL-SDA)

MSCL

MSDA (output)

2

Figure 5.11 Timing of Multi-master I C-bus Interface

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 121 of 122

R32C/118 Group

Appendix 1. Package Dimensions

JEITA Package Code

P-LQFP144-20x20-0.50

RENESAS Code

PLQP0144KA-A

Previous Code

144P6Q-A / FP-144L / FP-144LV

MASS[Typ.]

1.2g

H_D

*1

D

108

73

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

109

72

b_p

b₁

Dimension in Millimeters

Reference

Symbol

Min Nom Max

Terminal cross section

D

E

A₂

H_D

H_E

A

19.9 20.0 20.1

1.4

21.8 22.0 22.2

1.7

144

37

A₁

b_p

b₁

c

0.1

0.05

0.15

1

Z_D

36

0.17 0.22 0.27

0.20

c

Index mark

F

0.09

0.20

0.145

0.125

c₁

L

L₁

0°

8°

*3

e

x

y

0.5

b_p

e

y

x

Detail F

0.08

0.10

Z_D

Z_E

L

1.25

0.5

0.35

0.65

L₁

1.0

JEITA Package Code

P-LQFP100-14x14-0.50

RENESAS Code

PLQP0100KB-A

Previous Code

100P6Q-A / FP-100U / FP-100UV

MASS[Typ.]

0.6g

H_D

*1

D

51

75

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

76

50

b_p

b₁

Dimension in Millimeters

Reference

Symbol

Min Nom Max

D

E

A₂

H_D

H_E

A

13.9 14.0 14.1

1.4

15.8 16.0 16.2

1.7

Terminal cross section

100

26

A₁

b_p

b₁

c

0.1

0.05

0.15

1

25

Index mark

0.15 0.20 0.25

0.18

Z_D

F

0.145

0.125

0.09

0.20

c₁

c

0°

8°

e

0.5

y

*3

x

y

L

0.08

b_p

e

x

L₁

Z_D

Z_E

L

1.0

0.5

1.0

Detail F

0.35

0.65

L₁

REJ03B0255-0100 Rev.1.00 Nov 19, 2009

Page 122 of 122

REVISION HISTORY

R32C/118 Group Datasheet

Description

Summary

Rev.

1.00

Date

Page

—

Nov 19, 2009

Initial release

All trademarks and registered trademarks are the property of their respective owners.

A- 1

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Notes:

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes

warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property

rights or any other rights of Renesas or any third party with respect to the information in this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,

but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass

destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws

and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this

document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,

please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be

disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a

result of errors or omissions in the information included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability

of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular

application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications

or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality

and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or

undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall

have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing

applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,

movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages

arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain

rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage

caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software

alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as

swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.

Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have

any other inquiries.

RENESAS SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2377-3473

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

Renesas Technology Korea Co., Ltd.

Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

Renesas Technology Malaysia Sdn. Bhd

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

Colophon .7.2


型号：	R5F64188PFB
厂家：	RENESAS TECHNOLOGY CORP
描述：	RENESAS MCU 瑞萨MCU 微控制器和处理器外围集成电路时钟
文件：	总124页 (文件大小：1160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R5F64188PFB [RENESAS]

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