R7FA2L1AB2DFP [RENESAS]
Ultra low power 48 MHz Arm® Cortex-M23 core, up to 256-KB code flash memory;
| 型号： | R7FA2L1AB2DFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Ultra low power 48 MHz Arm® Cortex-M23 core, up to 256-KB code flash memory |
| 文件： | 总110页 (文件大小：1417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
R01DS0385EJ0100
Rev.1.00
RA2L1 Group
Renesas Microcontrollers
Aug 06, 2020
Ultra low power 48 MHz Arm® Cortex®-M23 core, up to 256-KB code flash memory, 32 KB SRAM, Capacitive Sensing Unit 2
(CTSU), 12-bit A/D Converter, 12-bit D/A Converter, Security and Safety features.
Features
● Middle-speed on-chip oscillator (MOCO) (8 MHz)
● Low-speed on-chip oscillator (LOCO) (32.768 kHz)
● Clock trim function for HOCO/MOCO/LOCO
● IWDT-dedicated on-chip oscillator (15 kHz)
● Clock out support
■ Arm Cortex-M23 Core
● Armv8-M architecture
● Maximum operating frequency: 48 MHz
● Arm Memory Protection Unit (Arm MPU) with 8 regions
● Debug and Trace: DWT, FPB, CoreSight MTB-M23
● CoreSight Debug Port: SW-DP
™
■ Up to 85 pins for general I/O ports
● 5-V tolerance, open drain, input pull-up
■ Memory
● Up to 256-KB code flash memory
● 8-KB data flash memory (100,000 program/erase (P/E) cycles)
● 32 KB SRAM
■ Operating Voltage
● VCC: 1.6 to 5.5 V
● Memory protection units
■ Operating Temperature and Packages
● Ta = -40℃ to +85℃
● 128-bit unique ID
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
– 48-pin LFQFP (7 mm × 7 mm, 0.50 mm pitch)
– 48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
● Ta = -40℃ to +105℃
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
– 48-pin LFQFP (7 mm × 7 mm, 0.50 mm pitch)
– 48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
■ Connectivity
● Serial Communications Interface (SCI) × 5
– Asynchronous interfaces
– 8-bit clock synchronous interface
– Simple IIC
– Simple SPI
– Smart card interface
● Serial Peripheral Interface (SPI) × 2
2
● I C bus interface (IIC) × 2
● CAN module (CAN)
■ Analog
● 12-bit A/D Converter (ADC12)
● 12-bit D/A Converter (DAC12)
● Low-Power Analog Comparator (ACMPLP) × 2
● Temperature Sensor (TSN)
■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 6
● Low Power Asynchronous General Purpose Timer (AGT) × 2
● Watchdog Timer (WDT)
■ Safety
● ECC in SRAM
● SRAM parity error check
● Flash area protection
● ADC self-diagnosis function
● Clock Frequency Accuracy Measurement Circuit (CAC)
● Cyclic Redundancy Check (CRC) calculator
● Data Operation Circuit (DOC)
● Port Output Enable for GPT (POEG)
● Independent Watchdog Timer (IWDT)
● GPIO readback level detection
● Register write protection
● Main oscillator stop detection
● Illegal memory access
■ Security and Encryption
● AES128/256
● True Random Number Generator (TRNG)
■ System and Power Management
● Low power modes
● Switching regulator
● Realtime Clock (RTC)
● Event Link Controller (ELC)
● Data Transfer Controller (DTC)
● Key Interrupt Function (KINT)
● Power-on reset
● Low Voltage Detection (LVD) with voltage settings
■ Human Machine Interface (HMI)
● Capacitive Sensing Unit 2 (CTSU)
■ Multiple Clock Sources
● Main clock oscillator (MOSC) （1 to 20 MHz）
● Sub-clock oscillator (SOSC) (32.768 kHz)
● High-speed on-chip oscillator (HOCO) (24/32/48/64 MHz)
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Aug 06, 2020
Page 1 of 110
RA2L1 Datasheet
1. Overview
1.
Overview
®
The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability.
®
The MCU in this series incorporates an energy-efficient Arm Cortex -M23 32-bit core, that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
● Up to 256-KB code flash memory
● 32-KB SRAM
● 12-bit A/D Converter (ADC12)
● 12-bit D/A Converter (DAC12)
● Security features
1.1
Function Outline
Table 1.1
Feature
Arm core
Functional description
Arm Cortex-M23 core
●
●
Maximum operating frequency: up to 48 MHz
Arm Cortex-M23 core:
–
–
–
–
Revision: r1p0-00rel0
Armv8-M architecture profile
Single-cycle integer multiplier
19-cycle integer divider
●
●
Arm Memory Protection Unit (Arm MPU):
–
–
Armv8 Protected Memory System Architecture
8 protect regions
SysTick timer:
Driven by SYSTICCLK (LOCO) or ICLK
–
Table 1.2
Memory
Feature
Functional description
Code flash memory
Data flash memory
Option-setting memory
SRAM
Maximum 256 KB of code flash memory.
8 KB of data flash memory.
The option-setting memory determines the state of the MCU after a reset.
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3
System (1 of 2)
Feature
Functional description
Operating modes
Two operating modes:
●
●
Single-chip mode
SCI boot mode
Resets
The MCU provides 13 resets. lists the reset names and sources.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
See section x, Low Voltage Detection (LVD).
Clocks
●
●
●
●
●
●
●
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator (IWDTLOCO)
Clock out support
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RA2L1 Datasheet
1. Overview
Table 1.3
Feature
System (2 of 2)
Functional description
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock selected as the
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.When measurement is
complete or the number of pulses within the time generated by the measurement reference clock
is not within the allowable range, an interrupt request is generated.
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also
controls non-maskable interrupts.
Key Interrupt Function (KINT)
Low power modes
The key interrupt function (KINT) is generated a key interrupt by detecting a valid edge on the
key interrupt input pin.
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
Register write protection
Memory Protection Unit (MPU)
Watchdog Timer (WDT)
The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function
are provided.
The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt or watchdog timer reset.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the
MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.
Table 1.4
Feature
Event link
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between the
modules without CPU intervention.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
Table 1.6
Feature
Timers (1 of 2)
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with
GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-
counter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
Port Output Enable for GPT (POEG)
The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state
Low power Asynchronous General
Purpose Timer (AGT)
The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
for pulse output, external pulse width or period measurement, and counting external events. This
timer consists of a reload register and a down counter. The reload register and the down counter
are allocated to the same address, and can be accessed with the AGT register.
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Aug 06, 2020
Page 3 of 110
RA2L1 Datasheet
1. Overview
Table 1.6
Timers (2 of 2)
Feature
Functional description
Realtime Clock (RTC)
The RTC has two operation modes, normal operation mode and low-consumption clock mode. In
each of the operation mode, the RTC has two counting modes, calendar count mode and binary
count mode, that are used by switching register settings. For calendar count mode, the RTC has
a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For
binary count mode, the RTC counts seconds and retains the information as a serial value. Binary
count mode can be used for calendars other than the Gregorian (Western) calendar.
Table 1.7
Communication interfaces
Feature
Functional description
Serial Communications Interface (SCI)
The Serial Communications Interface (SCI) × 5 channels have asynchronous and synchronous
serial interfaces:
●
Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
●
●
●
●
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol. SCIn (n = 0) has FIFO buffers to enable continuous and full-duplex
communication, and the data transfer speed can be configured independently using an on-chip
baud rate generator.
2
2
I C bus interface (IIC)
The I C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset
2
of the NXP I C (Inter-Integrated Circuit) bus interface functions.
Serial Peripheral Interface (SPI)
Control Area Network (CAN)
The Serial Peripheral Interface (SPI) provides high-speed full-duplex synchronous serial
communications with multiple processors and peripheral devices.
The Controller Area Network (CAN) module uses a message-based protocol to receive and
transmit data between multiple slaves and masters in electromagnetically noisy applications. The
module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32
mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO
modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN
module requires an additional external CAN transceiver.
Table 1.8
Feature
Analog
Functional description
12-bit A/D Converter (ADC12)
A 12-bit successive approximation A/D converter is provided. Up to 19 analog input channels are
selectable. Temperature sensor output and internal reference voltage are selectable for
conversion.
12-bit D/A Converter (DAC12)
Temperature Sensor (TSN)
A 12-bit D/A converter (DAC12) is provided.
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is fairly
linear. The output voltage is provided to the ADC12 for conversion and can be further used by
the end application.
Low-Power Analog Comparator
(ACMPLP)
The Low-Power Analog Comparator (ACMPLP) compares a reference input voltage with an
analog input voltage. Comparator channels ACMPLP0 and ACMPLP1 are independent of each
other.
The comparison result of the reference input voltage and analog input voltage can be read by
software. The comparison result can also be output externally. The reference input voltage can
be selected from either an input to the CMPREFi (i = 0, 1) pin or from the internal reference
voltage (Vref) generated internally in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting high-speed mode
decreases the response delay time, but increases current consumption. Setting low-speed mode
increases the response delay time, but decreases current consumption.
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
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RA2L1 Datasheet
1. Overview
Table 1.9
Human machine interfaces
Feature
Functional description
Capacitive Sensing Unit 2 (CTSU)
The Capacitive Sensing Unit 2 (CTSU) measures the electrostatic capacitance of the sensor.
Changes in the electrostatic capacitance are determined by software that enables the CTSU to
detect whether a finger is in contact with the sensor. The electrode surface of the sensor is
usually enclosed with a dielectric film so that a finger does not come into direct contact with the
electrode.
Table 1.10
Feature
Data processing
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generation polynomials are available. The snoop
function allows monitoring of reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected
condition applies, 16-bit data is compared and an interrupt can be generated.
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 5 of 110
RA2L1 Datasheet
1. Overview
1.2
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Bus
Memory
Arm Cortex-M23
MPU
System
256-KB code flash
Clocks
MPU
POR/LVD
Reset
MOSC/SOSC
8-KB data flash
32-KB SRAM
NVIC
(H/M/L) OCO
Mode control
Power control
ICU
System timer
DMA
DTC
Test and DBG Interface
CAC
Register write
protection
KINT
Timers
Communication interfaces
Human machine interfaces
CTSU
GPT32 × 4
GPT16 × 6
SCI × 5
IIC × 2
SPI × 2
CAN × 1
AGT × 2
RTC
WDT/IWDT
Event link
ELC
Data processing
Analogs
TSN
CRC
ADC12
DOC
Security
DAC12 × 1
ACMPLP × 2
AES + TRNG
Figure 1.1
Block diagram
1.3
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a
list of products.
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 6 of 110
RA2L1 Datasheet
1. Overview
Package type
R 7 F A2 L 1 AB 3 C F P
FP: LQFP 100 pins 0.5 mm pitch
FN: LQFP 80 pins 0.5 mm pitch
FM: LQFP 64 pins 0.5 mm pitch
FL: LFQFP 48 pins 0.5 mm pitch
NE: HWQFN 48 pins 0.5 mm pitch
Quality ID
C: Industrial applications
D: Consumer applications
Operating temperature
2: -40°C to +85°C
3: -40°C to +105°C
Code flash memory size
B: 256 KB
9: 128 KB
Feature set
A: Standard and security
Group name
L1: Low Power group
Core
2: Arm Cortex-M23
RA Family (Renesas Advanced)
Flash memory
Renesas microcontroller unit
Renesas
Figure 1.2
Table 1.11
Part numbering scheme
Product list (1 of 2)
Data
Operating
Product part number
Package code
PLQP0100KB-B
PLQP0080KB-B
PLQP0064KB-C
PLQP0048KB-B
TBD
Code flash
flash
SRAM
temperature
R7FA2L1AB3CFP
R7FA2L1AB3CFN
R7FA2L1AB3CFM
R7FA2L1AB3CFL
R7FA2L1AB3CNE
R7FA2L1AB2DFP
R7FA2L1AB2DFN
R7FA2L1AB2DFM
R7FA2L1AB2DFL
R7FA2L1AB2DNE
256 KB
8 KB
32 KB
-40 to +105°C
PLQP0100KB-B
PLQP0080KB-B
PLQP0064KB-C
PLQP0048KB-B
TBD
-40 to +85°C
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 7 of 110
RA2L1 Datasheet
1. Overview
Table 1.11
Product list (2 of 2)
Data
flash
Operating
temperature
Product part number
Package code
PLQP0100KB-B
PLQP0080KB-B
PLQP0064KB-C
PLQP0048KB-B
TBD
Code flash
SRAM
R7FA2L1A93CFP
R7FA2L1A93CFN
R7FA2L1A93CFM
R7FA2L1A93CFL
R7FA2L1A93CNE
R7FA2L1A92DFP
R7FA2L1A92DFN
R7FA2L1A92DFM
R7FA2L1A92DFL
R7FA2L1A92DNE
128 KB
8 KB
32 KB
-40 to +105°C
PLQP0100KB-B
PLQP0080KB-B
PLQP0064KB-C
PLQP0048KB-B
TBD
-40 to +85°C
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 8 of 110
RA2L1 Datasheet
1. Overview
1.4
Function Comparison
Table 1.12
Function Comparison
R7FA2L1A R7FA2L1A
B3CFL
93CFL
R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A
Parts number
Pin count
B3CFP
93CFP
100
B3CFN
93CFN
B3CFM
93CFM
64
B3CNE
93CNE
48
LQFP/QFN LQFP/QFN
256 KB 128 KB
80
Package
LQFP
256 KB
LQFP
128 KB
LQFP
LQFP
128 KB
LQFP
LQFP
128 KB
Code flash memory
Data flash memory
SRAM
256 KB
256 KB
8 KB
32 KB
16 KB
16 KB
Parity
ECC
System
CPU clock
48 MHz
Yes
Sub-clock
oscillator
ICU
Yes
KINT
8
6
5
3
Event control ELC
Yes
Yes
4
DMA
DTC
Timers
GPT32
GPT16
AGT
2
Yes
Yes
5
RTC
WDT/IWDT
Communicatio SCI
n
IIC
2
SPI
2
CAN
Yes
Analog
ADC12
19
17
13
DAC12
ACMPLP
TSN
1
2
Yes
HMI
CTSU
CRC
32
30
20
Data
processing
Yes
Yes
DOC
Security
AES and TRNG
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Aug 06, 2020
Page 9 of 110
RA2L1 Datasheet
1. Overview
1.5
Pin Functions
Table 1.13
Function
Pin functions (1 of 3)
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply. Connect
this pin to VSS by a 0.1-µF capacitor. Place the capacitor close to
the pin.
VCL
I/O
Connect this pin to the VSS pin by the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the
pin.
VSS
Input
Input
I/O
Ground pin. Connect it to the system power supply (0 V).
Switching regulator power supply pin
Switching regulator pin
VCC_DCDC
VLO
VSS_DCDC
Input
Switching regulator ground pin. Connect it to the system power
supply (0 V).
Clock
XTAL
Output
Input
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin.
EXTAL
XCIN
Input
Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
XCOUT
CLKOUT
Output
Output
Input
Clock output pin
Operating mode control
System control
MD
Pin for setting the operating mode. The signal level on this pin must
not be changed during operation mode transition on release from
the reset state.
RES
Input
Reset signal input pin. The MCU enters the reset state when this
signal goes low.
CAC
CACREF
Input
I/O
Measurement reference clock input pin
Serial wire debug data input/output pin
Serial wire clock pin
On-chip debug
SWDIO
SWCLK
Input
Input
Input
Input
I/O
Interrupt
GPT
NMI
Non-maskable interrupt request pin
Maskable interrupt request pins
External trigger input pins
IRQ0 to IRQ7
GTETRGA, GTETRGB
GTIOCnA (n = 0 to 9),
GTIOCnB (n = 0 to 9)
Input capture, output compare, or PWM output pins
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
Output
Output
Output
Output
Output
Input
3-phase PWM output for BLDC motor control (positive U phase)
3-phase PWM output for BLDC motor control (negative U phase)
3-phase PWM output for BLDC motor control (positive V phase)
3-phase PWM output for BLDC motor control (negative V phase)
3-phase PWM output for BLDC motor control (positive W phase)
3-phase PWM output for BLDC motor control (negative W phase)
External event input enable signals
GTOULO
GTOVUP
GTOVLO
GTOWUP
GTOWLO
AGT
AGTEE0, AGTEE1
AGTIO0, AGTIO1
AGTO0, AGTO1
AGTOA0, AGTOA1
AGTOB0, AGTOB1
I/O
External event input and pulse output pins
Pulse output pins
Output
Output
Output
Output compare match A output pins
Output compare match B output pins
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RA2L1 Datasheet
1. Overview
Table 1.13
Function
RTC
Pin functions (2 of 3)
Signal
I/O
Description
RTCOUT
Output
I/O
Output pin for 1-Hz or 64-Hz clock
SCI
SCKn (n = 0 to 3, 9)
RXDn (n = 0 to 3, 9)
Input/output pins for the clock (clock synchronous mode)
Input
Input pins for received data (asynchronous mode/clock synchronous
mode)
TXDn (n = 0 to 3, 9)
Output
I/O
Output pins for transmitted data (asynchronous mode/clock
synchronous mode)
CTSn_RTSn (n = 0 to 3,
9)
Input/output pins for controlling the start of transmission and
reception (asynchronous mode/clock synchronous mode), active-
low.
SCLn (n = 0 to 3, 9)
SDAn (n = 0 to 3, 9)
SCKn (n = 0 to 3, 9)
MISOn (n = 0 to 3, 9)
MOSIn (n = 0 to 3, 9)
SSn (n = 0 to 3, 9)
SCLn (n = 0, 1)
I/O
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
Input/output pins for the IIC clock (simple IIC mode)
Input/output pins for the IIC data (simple IIC mode)
Input/output pins for the clock (simple SPI mode)
Input/output pins for slave transmission of data (simple SPI mode)
Input/output pins for master transmission of data (simple SPI mode)
Chip-select input pins (simple SPI mode), active-low
Input/output pins for the clock
IIC
SDAn (n = 0, 1)
Input/output pins for data
SPI
RSPCKA, RSPCKB
MOSIA, MOSIB
Clock input/output pin
Input or output pins for data output from the master
Input or output pins for data output from the slave
Input or output pin for slave selection
MISOA, MISOB
SSLA0, SSLB0
SSLA1 to SSLA3, SSLB1 Output
to SSLB3
Output pins for slave selection
CAN
CRX0
Input
Output
Input
Input
Input
Receive data
CTX0
Transmit data
Analog power supply
AVCC0
AVSS0
VREFH0
Analog voltage supply pin for the ADC12, DAC12
Analog ground pin for the ADC12, DAC12
Analog reference voltage supply pin for the ADC12. Connect this pin
to AVCC0 when not using the ADC12.
VREFL0
Input
Analog reference ground pin for the ADC12. Connect this pin to
AVSS0 when not using the ADC12.
ADC12
AN000 to AN014, AN017 Input
to AN020
Input pins for the analog signals to be processed by the A/D
converter.
ADTRG0
Input
Input pin for the external trigger signals that start the A/D
conversion, active-low.
DAC12
DA0
Output
Output
Input
Output pin for the analog signals processed by the D/A converter.
Comparator output pin
ACMPLP
VCOUT
CMPREF0, CMPREF1
CMPIN0, CMPIN1
Reference voltage input pins
Input
Analog voltage input pins
CTSU
KINT
TS00, TS02-CFC, TS04
to TS07, TS08-CFC to
TS16-CFC, TS17, TS18,
TS21 to TS25, TS26-CFC
to TS35-CFC
Input
Capacitive touch detection pins (touch pins)
TSCAP
—
Secondary power supply pin for the touch driver
Key interrupt input pins
KR00 to KR07
Input
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 11 of 110
RA2L1 Datasheet
1. Overview
Table 1.13
Function
I/O ports
Pin functions (3 of 3)
Signal
I/O
Description
P000 to P008, P010 to
P015
I/O
General-purpose input/output pins
P100 to P115
P200
I/O
General-purpose input/output pins
General-purpose input pin
Input
I/O
P201 to P208, P212,
P213
General-purpose input/output pins
P214, P215
Input
I/O
General-purpose input pins
P300 to P307
P400 to P415
P500 to P505
General-purpose input/output pins
General-purpose input/output pins
General-purpose input/output pins
General-purpose input/output pins
I/O
I/O
P600 to P603, P608 to
P610
I/O
P708, P714
P808, P809
I/O
I/O
General-purpose input/output pins
General-purpose input/output pins
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 12 of 110
RA2L1 Datasheet
1. Overview
1.6
Pin Assignments
Figure 1.3 and Figure 1.4 show the pin assignments from the top view.
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P500
P300/SWCLK
P301
77
P501
78
P502
P302
79
P503
P303
80
P504
P809
81
P505
P808
82
VCC
P304
83
VSS
P305
84
P015
P306
85
P014
P307
86
P013
P200
87
P012
P201/MD
RES
88
AVCC0
R7FA2L1AB3CFP
89
AVSS0
VCC
90
P011/VREFL0
VSS
91
P010/VREFH0
P202
92
P008
P203
93
P007
P204
94
P006
P205
95
P005
P206
96
P004
P207
97
P003
P208
98
P002
VCC_DCDC
VLO
99
P001
100
P000
VSS_DCDC
Figure 1.3
Pin assignment for LQFP 100-pin (top view)
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 13 of 110
RA2L1 Datasheet
1. Overview
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P500
P501
P300/SWCLK
P301
P502
P302
P503
P303
P504
P809
P015
P808
P014
P304
P013
P305
P012
P306
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P006
P200
R7FA2L1AB3CFN
P201/MD
RES
P204
P205
P005
P206
P004
P207
P003
P208
P002
VCC_DCDC
VLO
P001
P000
VSS_DCDC
Figure 1.4
Pin assignment for LQFP 80-pin (top view)
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P500
P300/SWCLK
P301
50
P501
51
P502
P302
52
P015
P303
53
P014
P304
54
P013
P200
55
P012
P201/MD
RES
56
AVCC0
R7FA2L1AB3CFM
57
58
59
60
61
62
63
64
AVSS0
P011/VREFL0
P010/VREFH0
P004
P204
P205
P206
P207
P003
P208
P002
VCC_DCDC
VLO
P001
P000
VSS_DCDC
Figure 1.5
Pin assignment for LQFP 64-pin (top view)
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 14 of 110
RA2L1 Datasheet
1. Overview
24
23
22
21
20
19
18
17
16
15
14
13
P300/SWCLK
P301
37
38
39
40
41
42
43
44
45
46
47
48
P500
P015
P302
P014
P200
P013
P201/MD
RES
P012
AVCC0
AVSS0
R7FA2L1AB3CFL
P206
P207
P011/VREFL0
P010/VREFH0
P002
P208
VCC_DCDC
VLO
P001
VSS_DCDC
P000
Figure 1.6
Pin assignment for LQFP 48-pin (top view)
37
24
P500
P300/SWCLK
P301
38
23
22
21
20
19
18
17
16
15
14
13
P015
39
P014
P302
40
P013
P200
41
P012
P201/MD
RES
42
43
44
45
46
AVCC0
AVSS0
R7FA2L1AB3CNE
P206
P011/VREFL0
P010/VREFH0
P002
P207
P208
VCC_DCDC
VLO
P001 47
P000 48
VSS_DCDC
Figure 1.7
Pin assignment for QFN 48-pin (top view)
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 15 of 110
RA2L1 Datasheet
1. Overview
1.7
Pin Lists
Table 1.14
Pin list (1 of 4)
Num.
Timers
Communication interfaces
Analogs
HMI
1
2
1
2
1
2
1
2
CACREF
_C
P400
P401
AGTIO1_
C
—
GTIOC6A
_A
—
—
—
SCK0_B/
SCK1_B
SCL0_A
—
—
—
—
—
—
—
—
—
—
IRQ0_A
IRQ5
—
—
GTETRG
A_B
GTIOC6B
_A
CTX0_B
CTS0_RT SDA0_A
S0_B/
SS0_B/
TXD1_B/
MOSI1_B/
SDA1_B
3
4
3
4
3
4
—
—
—
—
P402
P403
AGTIO0_
E/
AGTIO1_
D
—
—
—
—
—
CRX0_B
RXD1_B/
MISO1_B/
SCL1_B
—
—
—
—
—
—
—
—
—
—
TS18
TS17
IRQ4
—
AGTIO0_
F/
GTIOC3A
_B
—
CTS1_RT
S1_B/
AGTIO1_
E
SS1_B
5
6
7
—
—
5
—
—
—
—
—
—
—
—
—
P404
P405
P406
—
—
—
—
—
—
GTIOC3B
_B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTIOC1A
_B
GTIOC1B
_B
8
6
—
5
—
3
—
P714
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
7
VCL
—
10
11
12
13
8
6
4
XCIN
XCOUT
VSS
P215
P214
—
—
9
7
5
—
10
11
8
6
—
9
7
XTAL
P213
GTETRG
A_D
GTIOC0A
_D
TXD1_A/
MOSI1_A/
SDA1_A
IRQ2_B
14
12
10
8
EXTAL
P212
AGTEE1
GTETRG
B_D
GTIOC0B
_D
—
—
RXD1_A/
MISO1_A/
SCL1_A
—
—
—
—
—
—
IRQ3_B
15
16
13
14
11
—
9
VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P708
RXD1_D/
MISO1_D
/SCL1_D
SSLA3_B
17
18
19
15
—
—
—
—
—
—
—
—
—
—
—
P415
P414
P413
—
—
—
—
—
GTIOC0A
_C
—
—
—
—
—
—
—
—
—
—
—
SSLA2_B
SSLA1_B
SSLA0_B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTIOC0B
_C
GTOUUP
_B
—
CTS0_RT
S0_E/
SS0_E
20
21
—
—
—
—
—
—
P412
P411
—
GTOULO
_B
—
—
—
—
—
SCK0_E
—
—
RSPCKA
_B
—
—
—
—
—
—
—
—
16
12
AGTOA1
GTOVUP
_B
GTIOC9A
_A
TXD0_B/
MOSI0_B/
SDA0_B/
CTS3_RT
S3_A/
MOSIA_B
TS07
IRQ4_B
SS3_A
22
17
13
—
—
P410
AGTOB1
GTOVLO
_B
GTIOC9B
_A
—
—
RXD0_B/
MISO0_B/
SCL0_B/
SCK3_A
—
—
MISOA_B
—
—
—
TS06
IRQ5_B
23
24
18
19
14
15
10
11
—
—
P409
P408
—
—
GTOWUP GTIOC5A
_B _B
—
—
—
—
TXD3_A/
MOSI3_A/
SDA3_A
—
—
—
—
—
—
—
—
TS05
TS04
IRQ6_B
IRQ7_B
GTOWLO GTIOC5B
_B
CTS1_RT SCL0_C
S1_D/
_B
SS1_D/
RXD3_A/
MISO3_A/
SCL3_A
25
20
16
12
—
P407
AGTIO0_
C
—
—
RTCOUT
—
CTS0_RT SDA0_B
S0_D/
SSLB3_A
ADTRG0_
B
—
—
—
—
SS0_D
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 16 of 110
RA2L1 Datasheet
1. Overview
Table 1.14
Pin list (2 of 4)
Num.
Timers
Communication interfaces
Analogs
HMI
26
21
17
13
VSS_DC
DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27
28
22
23
18
19
14
15
VLO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VCC_DC
DC
29
24
20
16
—
P208
AGTOB0_
A
—
—
—
—
—
—
—
—
—
—
—
—
—
30
31
25
26
21
22
17
18
—
—
P207
P206
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTIU_A
RXD0_D/
MISO0_D
/SCL0_D
SDA1_A
SSLB1_A
IRQ0
32
27
23
—
CLKOUT_ P205
A
AGTO1
GTIV_A
GTIOC4A
_B
—
—
TXD0_D/
MOSI0_D
/SDA0_D/
CTS9_RT
S9_A/
SCL1_A
SSLB0_A
—
—
—
—
IRQ1
SS9_A
33
34
28
—
24
—
—
—
CACREF
_A
P204
P203
AGTIO1_
A
GTIW_A
—
GTIOC4B
_B
—
—
—
—
SCK0_D/
SCK9_A
SCL0_B
—
RSPCKB
_A
—
—
—
—
—
—
TS00
—
—
—
—
—
—
CTS2_RT
S2_A/
MOSIB_A
SS2_A/
TXD9_A/
MOSI9_A/
SDA9_A
35
—
—
—
—
P202
—
—
—
—
—
SCK2_A/
RXD9_A/
MISO0_A/
SCL9_A
—
MISOB_A
—
—
—
—
—
36
37
38
39
40
41
42
43
44
—
—
29
30
31
—
32
33
34
—
—
25
26
27
—
—
—
28
—
—
19
20
21
—
—
—
—
VSS
VCC
RES
MD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NMI
—
—
—
—
—
—
P201
P200
P307
P306
P305
P304
—
—
—
—
GTIOC7A
_A
45
46
47
35
36
37
—
—
29
—
—
—
—
—
—
P808
P809
P303
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTIOC7B
_A
TS02-
CFC
48
49
38
39
30
31
22
23
—
—
P302
P301
—
GTOUUP
_A
GTIOC4A
_A
—
—
—
—
TXD2_A/
MOSI2_A/
SDA2_A
—
—
SSLB3_B
SSLB2_B
—
—
—
—
—
—
TS08-
CFC
IRQ5_A
IRQ6_A
AGTIO0_
D
GTOULO
_A
GTIOC4B
_A
RXD2_A/
MISO2_A/
SCL2_A/
CTS9_RT
S9_D/
TS09-
CFC
SS9_D
50
51
40
41
32
33
24
25
SWCLK
SWDIO
P300
P108
—
—
GTOUUP
_C
GTIOC0A
_A
—
—
—
—
—
—
—
SSLB1_B
SSLB0_B
—
—
—
—
—
—
—
—
—
—
GTOULO
_C
GTIOC0B
_A
CTS9_RT
S9_B/
SS9_B
52
53
42
43
34
35
26
27
CLKOUT_ P109
B
—
—
GTOVUP
_A
GTIOC1A
_A
—
—
CTX0_A
CRX0_A
SCK1_E/
TXD9_B/
MOSI9_B/
SDA9_B
—
—
MOSIB_B
MISOB_B
—
—
—
—
—
TS10-
CFC
—
—
—
P110
P111
GTOVLO
_A
GTIOC1B
_A
CTS2_RT
S2_B/
SS2_B/
RXD9_B/
MISO9_B/
SCL9_B
VCOUT
TS11-
CFC
IRQ3_A
54
44
36
28
AGTOA0
—
GTIOC3A
_A
—
—
SCK2_B/
SCK9_B
—
RSPCKB
_B
—
—
—
TS12-
CFC
IRQ4_A
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 17 of 110
RA2L1 Datasheet
1. Overview
Table 1.14
Pin list (3 of 4)
Num.
Timers
Communication interfaces
Analogs
HMI
55
45
37
29
—
P112
AGTOB0
—
GTIOC3B
_A
—
—
SCK1_D/
TXD2_B/
MOSI2_B/
SDA2_B
—
SSLB0_C
—
—
—
TSCAP-C
—
56
57
58
59
60
61
46
47
48
—
—
—
38
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P113
P114
P115
P608
P609
P610
—
—
—
—
—
—
—
—
—
—
—
—
GTIOC2A
_C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TS27-
CFC
—
—
—
—
—
—
GTIOC2B
_C
TS29-
CFC
GTIOC4A
_C
TS35-
CFC
GTIOC4B
_C
—
—
—
GTIOC5A
_C
GTIOC5B
_C
62
63
64
49
50
—
39
40
—
30
31
—
VCC
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P603
GTIOC7A
_B
CTS9_RT
S9_C/
SS9_C
65
66
—
—
—
—
—
—
—
P602
P601
—
—
—
—
GTIOC7B
_B
—
—
—
—
TXD9_C/
MOSI9_C
/SDA9_C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
51
GTIOC6A
_C
RXD9_C/
MISO9_C
/SCL9_C
67
68
69
70
71
52
53
54
55
56
—
41
42
43
44
—
—
—
—
32
—
—
—
—
—
P600
P107
P106
P105
P104
—
—
—
—
—
—
—
—
GTIOC6B
_C
—
—
—
—
—
—
—
—
—
—
SCK9_C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTIOC8A
_A
—
—
—
—
KR07
KR06
GTIOC8B
_A
SSLA3_A
SSLA2_A
SSLA1_A
GTETRG
A_C
GTIOC1A
_C
TS34-
CFC
KR05/
IRQ0_B
GTETRG
B_B
GTIOC1B
_C
RXD0_C/
MISO0_C
/SCL0_C
TS13-
CFC
KR04/
IRQ1_B
72
73
57
58
45
46
33
34
—
—
P103
P102
—
GTOWUP GTIOC2A
_A _A
—
—
CTX0_C
CRX0_C
CTS0_RT
S0_A/
SS0_A
—
—
SSLA0_A
—
—
—
CMPREF
1
TS14-
CFC
KR03
KR02
AGTO0
GTOWLO GTIOC2B
SCK0_A/
TXD2_D/
MOSI2_D
/SDA2_D
RSPCKA
_A
ADTRG0_
A
CMPIN1
TS15-
CFC
_A
_A
74
75
59
60
47
48
35
36
—
—
P101
P100
AGTEE0
GTETRG
B_A
GTIOC5A
_A
—
—
—
—
TXD0_A/
MOSI0_A/
SDA0_A/
CTS1_RT
S1_A/
SDA1_B
SCL1_B
MOSIA_A
MISOA_A
—
—
—
—
CMPREF
0
TS16-
CFC
KR01/
IRQ1_A
SS1_A
AGTIO0_
A
GTETRG
A_A
GTIOC5B
_A
RXD0_A/
MISO0_A/
SCL0_A/
SCK1_A
CMPIN0
TS26-
CFC
KR00/
IRQ2_A
76
77
61
62
49
50
37
—
—
—
P500
P501
—
—
GTIU_B
GTIV_B
GTIOC2A
_B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTIOC2B
_B
TXD1_C/
MOSI1_C
/SDA1_C
AN017
78
63
51
—
—
P502
—
GTIW_B
GTIOC3B
_C
—
—
RXD1_C/
MISO1_C
/SCL1_C
—
—
AN018
—
—
—
—
79
80
64
65
—
—
—
—
—
—
P503
P504
—
—
GTETRG
A_E
—
—
—
—
—
—
SCK1_C
—
—
—
—
AN019
AN020
—
—
—
—
—
—
—
—
GTETRG
B_E
CTS1_RT
S1_C/
SS1_C
81
82
—
—
—
—
—
—
—
P505
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VCC
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Aug 06, 2020
Page 18 of 110
RA2L1 Datasheet
1. Overview
Table 1.14
Pin list (4 of 4)
Num.
Timers
Communication interfaces
Analogs
HMI
83
84
—
—
—
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
66
52
38
P015
AN010
TS28-
CFC
IRQ7_A
85
86
67
68
53
54
39
40
—
—
P014
P013
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AN009
AN008
DA0
—
—
—
—
—
—
TS33-
CFC
87
69
55
41
—
P012
—
—
—
—
—
—
—
—
AN007
—
—
TS32-
CFC
—
88
89
90
70
71
72
56
57
58
42
43
44
AVCC0
AVSS0
VREFL0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P011
AN006
TS31-
CFC
91
73
59
45
VREFH0
P010
—
—
—
—
—
—
—
—
AN005
—
—
TS30-
CFC
—
92
93
94
95
96
97
98
99
100
—
—
74
75
76
77
78
79
80
—
—
—
—
60
61
62
63
64
—
—
—
—
—
—
46
47
48
—
—
—
—
—
—
—
—
—
P008
P007
P006
P005
P004
P003
P002
P001
P000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AN014
AN013
AN012
AN011
AN004
AN003
AN002
AN001
AN000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TS25
TS24
TS23
TS22
TS21
IRQ3
—
IRQ2
IRQ7
IRQ6
Note:
Several pin names have the added suffix of _A, _B, _C, _D, _E and _F. The suffix can be ignored when assigning functionality.
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 19 of 110
RA2L1 Datasheet
2. Electrical Characteristics
2.
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
*1
*2
VCC = AVCC0 = VCC_DCDC = 1.6 to 5.5 V, VREFH0 = 1.6 to AVCC0,
VSS = AVSS0 = VREFL0 = 0 V, Ta = T
opr
Note 1. The typical condition is set to VCC = 3.3 V.
Note 2. When VCC_DCDC is used. VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V.
Figure 2.1 shows the timing conditions.
For example, P300
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF
Figure 2.1
Input or output timing measurement conditions
The measurement conditions of the timing specifications for each peripheral are recommended for the best peripheral
operation. However, make sure to adjust driving abilities for each pin to meet the conditions of your system.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin
is mixed, the AC characteristics of each function are not guaranteed.
2.1
Absolute Maximum Ratings
Table 2.1
Parameter
Absolute maximum ratings (1 of 2)
Symbol
Value
Unit
V
Power supply voltage
Input voltage
VCC
-0.5 to +6.5
-0.3 to +6.5
*1
V
V
5V-tolerant ports
in
P000 to P008, P010 to P015
Others
V
V
-0.3 to AVCC0 + 0.3
-0.3 to VCC + 0.3
-0.3 to +6.5
V
V
V
V
V
V
in
in
Reference power supply voltage
Analog power supply voltage
VREFH0
AVCC0
-0.5 to +6.5
Switching regulator power supply voltage
VCC_DCDC
-0.5 to +6.5
Analog input voltage When AN000 to AN014 are
V
AN
-0.3 to AVCC0 + 0.3
used
When AN017 to AN020 are
used
-0.3 to VCC + 0.3
V
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Page 20 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.1
Absolute maximum ratings (2 of 2)
Parameter
Symbol
Value
Unit
*2 *3 *4
T
-40 to +85
-40 to +105
°C
Operating temperature
opr
Storage temperature
T
-55 to +125
°C
stg
Note 1. Ports P205, P206, P400, P401, and P407 are 5V-tolerant.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of
such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause
degradation of internal elements.
Note 2. See section 2.2.1. Tj/Ta Definition.
Note 3. Contact Renesas Electronics sales office for information on derating operation under Ta = +85°C to +105°C.
Derating is the systematic reduction of load for improved reliability.
Note 4. The upper limit of the operating temperature is 85°C or 105°C, depending on the product. For details, see section x.x. Part
Numbering.
Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors with high frequency
characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, and between the
VREFH0 and VREFL0 pins when VREFH0 is selected as the high potential reference voltage for the
ADC12. Place capacitors of the following value as close as possible to every power supply pin and use
the shortest and heaviest possible traces:
● VCC and VSS: about 0.1 µF
● AVCC0 and AVSS0: about 0.1 µF
● VREFH0 and VREFL0: about 0.1 µF
Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. Connect the VCC_DCDC pin to a VSS_DCDC pin
by a 1.0 µF capacitor. Each capacitor must be placed close to the pin.
Table 2.2
Parameter
Recommended operating conditions
Symbol
Value
Min
Typ
Max
Unit
*1 *2
Power supply voltages
1.6
—
5.5
V
VCC
VSS
—
0
—
V
V
V
Switching regulator power supply voltage
Analog power supply voltages
VCC_DCDC
VCC_DCDC = VCC
2.4
1.6
—
—
5.5
5.5
*1 *2
AVCC0
AVSS0
—
0
—
V
V
V
VREFH0
VREFL0
When used as ADC12
Reference
1.6
—
—
0
AVCC0
—
Note 1. Use AVCC0 and VCC under the following conditions:
AVCC0 = VCC
Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pins.
When powering off the VCC and AVCC0 pins, power them off at the same time or the AVCC0 pin first and then the VCC pins.
2.2
DC Characteristics
2.2.1
Tj/Ta Definition
Table 2.3
DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
Tj
—
125
°C
High-speed mode
Middle-speed mode
Low-speed mode
Subosc-speed mode
*1
105
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Aug 06, 2020
Page 21 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Note:
Make sure that Tj = T + θja × total power consumption (W), where total power consumption = (VCC - V ) × ΣI + V × ΣI
+
OL
a
OH
OH
OL
I
max × VCC.
CC
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section x.x. Part Numbering.
If the part number shows the operation temperature at 85°C, then the maximum value of Tj is 105°C, otherwise it is 125°C.
2.2.2
I/O V , V
IH
IL
Table 2.4
I/O VIH, VIL
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
Parameter
Symbol
Min
Typ
—
Max
Unit Conditions
*1
Schmitt trigger
input voltage
V
VCC × 0.7
—
5.8
V
—
IIC (except for SMBus)
IH
V
IL
V
IH
V
IL
—
VCC × 0.3
—
RES, NMI
VCC × 0.8
—
—
Other peripheral input pins
excluding IIC
—
VCC × 0.2
*2
Input voltage
(except for
Schmitt trigger
input pin)
V
IH
V
IH
V
IL
V
IL
2.2
2.0
—
—
—
—
—
—
VCC = 3.6 to
5.5 V
IIC (SMBus)
—
VCC = 2.7 to
3.6 V
0.8
0.5
VCC = 3.6 to
5.5 V
—
VCC = 2.7 to
3.6 V
*3
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VCC × 0.8
—
—
—
—
—
—
5.8
—
5V-tolerant ports
—
VCC × 0.2
—
P000 to P008, P010 to
P015
AVCC0 × 0.8
—
AVCC0 × 0.2
—
EXTAL
VCC × 0.8
—
Input ports pins except for
P000 to P008, P010 to
P015
VCC × 0.2
Note 1. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A (total 5 pins)
Note 2. SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SCL1_A, SCL1_B, SDA1_A, SDA1_B (total 9 pins)
Note 3. P205, P206, P400, P401, P407 (total 5 pins)
2.2.3
I/O I , I
OH OL
Table 2.5
I/O IOH, IOL (1 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
Parameter
Symbol
Min
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
Max
-4.0
8.0
Unit
mA
mA
mA
mA
mA
mA
mA
mA
conditions
Permissible output
current (average
value per pin)
Ports P000 to P008, P010 to P015, P205,
P206, P212, P213, P400, P401, P407
I
I
I
I
I
I
I
I
OH
OL
OH
OL
OH
OL
OH
OL
*1
-4.0
20.0
-4.0
8.0
Other output pins
Permissible output
current (max value
per pin)
Ports P000 to P008, P010 to P015, P205,
P206, P212, P213, P400, P401, P407
*1
-4.0
20.0
Other output pins
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 22 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.5
I/O IOH, IOL (2 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
Parameter
Symbol
Min
Typ
Max
Unit
conditions
Permissible output
current (max value
total pins)
Total of ports P000 to P008, P010 to
P015
ΣI
ΣI
ΣI
ΣI
—
—
-30
mA
AVCC0 = 2.7
to 5.5 V
OH (max)
OL (max)
OH
*2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
AVCC0 = 1.8
to 2.7 V
-4
AVCC0 = 1.6
to 1.8 V
50
4
AVCC0 = 2.7
to 5.5 V
AVCC0 = 1.8
to 2.7 V
2
AVCC0 = 1.6
to 1.8 V
Total of ports P212, P213
-8.0
-2
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
-1
VCC = 1.6 to
1.8 V
16.0
1.2
0.6
-30
-8
VCC = 2.7 to
5.5 V
OL
VCC = 1.8 to
2.7 V
VCC = 1.6 to
1.8 V
Total of ports P400 to 100 pin products ΣI
P415, P708, P714
VCC = 2.7 to
5.5 V
OH (max)
VCC = 1.8 to
2.7 V
-4
VCC = 1.6 to
1.8 V
ΣI
50
4
VCC = 2.7 to
5.5 V
OL (max)
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 23 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.5
I/O IOH, IOL (3 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
Parameter
Symbol
Min
Typ
Max
Unit
conditions
Permissible output
current (max value
total pins)
Total of ports P201 to 100 pin products ΣI
P208, P303 to P307,
P808, P809
—
—
-30
mA
VCC = 2.7 to
5.5 V
OH (max)
*2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-8
-4
50
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VCC = 1.8 to
2.7 V
VCC = 1.6 to
1.8 V
ΣI
VCC = 2.7 to
5.5 V
OL (max)
OH (max)
OL (max)
OH (max)
OL (max)
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of ports P108 to 100 pin products ΣI
P115, P300 to P302,
P600 to P603, P608
-30
-8
-4
50
4
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
to P610
VCC = 1.6 to
1.8 V
ΣI
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of ports P100 to 100 pin products ΣI
P107, P500 to P505
-30
-8
-4
50
4
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
VCC = 1.6 to
1.8 V
ΣI
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 24 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.5
I/O IOH, IOL (4 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
Parameter
Symbol
Min
—
Typ
—
Max
-100
100
-30
Unit
mA
mA
mA
conditions
Permissible output
current (max value
Total of all output pin 100 pin products ΣI
OH (max)
ΣI
—
—
*2
OL (max)
total pins)
Total of ports P204 to 80 pin products
P208, P400 to P403,
P406 to P411, P415,
ΣI
OH (max)
ΣI
OL (max)
ΣI
OH (max)
ΣI
OL (max)
—
—
VCC = 2.7 to
5.5 V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-8
-4
50
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VCC = 1.8 to
2.7 V
P708, P714
VCC = 1.6 to
1.8 V
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of ports P100 to 80 pin products
P115, P201, P300 to
P306, P500 to P504,
P600, P601, P808,
-30
-8
-4
50
4
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
P809
VCC = 1.6 to
1.8 V
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of all output pin 80 pin products
ΣI
ΣI
—
—
—
—
-60
mA
mA
OH (max)
100
OL (max)
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 25 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.5
I/O IOH, IOL (5 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
Parameter
Symbol
Min
Typ
Max
Unit
conditions
Permissible output
current (max value
total pins)
Total of ports P204 to 64 pin products
P208, P400 to P403,
P407 to P411
ΣI
OH (max)
ΣI
OL (max)
ΣI
OH (max)
ΣI
OL (max)
—
—
-30
mA
VCC = 2.7 to
5.5 V
*2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-8
-4
50
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VCC = 1.8 to
2.7 V
VCC = 1.6 to
1.8 V
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of ports P100 to 64 pin products
P113, P201, P300 to
P304, P500 to P502
-30
-8
-4
50
4
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
VCC = 1.6 to
1.8 V
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of all output pin 64 pin products
ΣI
ΣI
—
—
—
—
-60
mA
mA
OH (max)
100
OL (max)
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 26 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.5
I/O IOH, IOL (6 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
Parameter
Symbol
Min
Typ
Max
Unit
conditions
Permissible output
current (max value
total pins)
Total of ports P206 to 48 pin products
P208, P400, P401,
P407 to P409
ΣI
OH (max)
ΣI
OL (max)
ΣI
OH (max)
ΣI
OL (max)
—
—
-30
mA
VCC = 2.7 to
5.5 V
*2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-8
-4
50
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VCC = 1.8 to
2.7 V
VCC = 1.6 to
1.8 V
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of ports P100 to 48 pin products
P104, P108 to
P112,P201, P300 to
P302, P500
-30
-8
-4
50
4
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
VCC = 1.6 to
1.8 V
VCC = 2.7 to
5.5 V
VCC = 1.8 to
2.7 V
2
VCC = 1.6 to
1.8 V
Total of all output pin 48 pin products
ΣI
ΣI
—
—
—
—
-60
mA
mA
OH (max)
100
OL (max)
Note 1. Except for Ports P200, P214, and P215, which are input ports.
Note 2. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
Total output current of pins = (I × 0.7)/(n × 0.01)
OH
<Example> Where n = 80% and I = −30.0 mA
OH
Total output current of pins = (−30.0 × 0.7)/(80 × 0.01) ≅ −26.2 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in Table 2.5.
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RA2L1 Datasheet
2. Electrical Characteristics
2.2.4
I/O V , V , and Other Characteristics
OL
OH
Table 2.6
I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = 4.0 to 5.5 V
Parameter
Symbol
Min
Typ Max
Unit Test conditions
Output
voltage
Ports P000 to P008, P010 to P015
V
V
AVCC0 - 0.8
VCC - 0.8
—
—
—
—
V
I
I
= -4.0 mA
= -4.0 mA
OH
OH
OH
OH
Output pins except for P000 to P008 and
*1
P010 to P015
Ports P000 to P008, P010 to P015
V
V
—
—
—
—
0.8
0.8
I
I
= 8.0 mA
= 8.0 mA
OL
OL
Ports P205, P206, P212, P213, P400,
P401, P407
OL
OL
Output pins except for P000 to P008, P010
to P015, P205, P206, P212, P213, P400,
P401, and P407
V
—
—
1.2
I
= 20.0 mA
OL
OL
*1
Note 1. Except for Ports P200, P214, and P215, which are input ports.
Table 2.7
I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = 2.7 to 4.0 V
Parameter
Symbol
Min
Typ Max
Unit Test conditions
Output
voltage
Ports P000 to P008, P010 to P015
V
V
AVCC0 - 0.8
VCC - 0.8
—
—
—
—
V
I
I
= -4.0 mA
= -4.0 mA
OH
OH
OH
OH
Output pins except for P000 to P008 and
*1
P010 to P015
Ports P000 to P008, P010 to P015
V
V
—
—
—
—
0.8
0.8
I
I
= 8.0 mA
= 8.0 mA
OL
OL
Output pins except for P000 to P008 and
OL
OL
*1
P010 to P015
Note 1. Except for Ports P200, P214, and P215, which are input ports.
Table 2.8
I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = 1.6 to 2.7 V
Parameter
Symbol
Min
Typ Max
Unit Test conditions
= -1.0 mA
Output
voltage
Ports P000 to P008, P010 to P015
V
OH
V
OH
V
OL
V
OL
AVCC0 - 0.5
—
—
—
—
—
—
—
—
—
V
I
OH
AVCC0 = 1.8 to 2.7 V
I = -0.5 mA
OH
AVCC0 = 1.6 to 1.8 V
I = -1.0 mA
OH
VCC = 1.8 to 2.7 V
I = -0.5 mA
OH
AVCC0 - 0.5
—
Output pins except for P000 to P008
VCC - 0.5
—
*1
and P010 to P015
VCC - 0.5
—
VCC = 1.6 to 1.8 V
Ports P000 to P008, P010 to P015
—
—
—
—
0.4
0.4
0.4
0.4
I
OL
= 0.6 mA
AVCC0 = 1.8 to 2.7 V
I
OL
= 0.3 mA
AVCC0 = 1.6 to 1.8 V
Output pins except for P000 to P008
I
= 0.6 mA
OL
*1
and P010 to P015
VCC = 1.8 to 2.7 V
I
= 0.3 mA
OL
VCC = 1.6 to 1.8 V
Note 1. Except for Ports P200, P214, and P215, which are input ports.
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Page 28 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.9
I/O other characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current RES, ports P200, P214, P215
| I
in
|
—
—
1.0
µA
V
V
= 0 V
= VCC
in
in
*1
Three-state leakage
current (off state)
| I
TSI
|
—
—
—
—
1.0
1.0
µA
V
V
= 0 V
= 5.8 V
5V-tolerant ports
in
in
Other ports
V
V
= 0 V
= VCC
in
(except for P200, P214, P215, and
5V-tolerant ports)
in
Input pull-up resistor
Input capacitance
All ports
(except for P200, P214, P215)
R
C
10
20
100
kΩ
pF
V
= 0 V
U
in
P200
—
—
—
—
30
15
V
= 0 V
in
in
f = 1 MHz
T = 25°C
a
Other input pins
Note 1. P205, P206, P400, P401, and P407 (total 5 pins)
2.2.5
Operating and Standby Current
Table 2.10
Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
DCDC
*12
LDO mode
mode
Test
Conditions
*10
*10
Parameter
Symbol
Typ
Max
Typ
Max
Unit
*7 *11
*7
Supply
current
High-
speed
mode
Normal All peripheral
ICLK = 48 MHz
I
5.50
—
3.05
—
mA
CC
*1
mode
clocks disabled,
CoreMark code
executing from
ICLK = 32 MHz
ICLK = 16 MHz
ICLK = 8 MHz
ICLK = 48 MHz
3.65
2.20
1.45
—
—
2.20
1.35
0.90
—
—
*2
—
—
*5
flash
—
—
*9 *11
All peripheral
14.5
12.5
clocks enabled,
code executing
*5
from flash
*7
*7
Sleep
mode
All peripheral
clocks disabled
ICLK = 48 MHz
1.05
—
0.65
—
*5
ICLK = 32 MHz
ICLK = 16 MHz
ICLK = 8 MHz
ICLK = 48 MHz
0.85
0.70
0.60
4.85
—
—
—
—
0.55
0.45
0.35
2.95
—
—
—
—
*9
*8
All peripheral
clocks enabled
*5
ICLK = 32 MHz
ICLK = 16 MHz
4.68
2.55
1.50
2.1
—
—
—
—
2.85
1.55
0.95
1.95
—
—
—
—
ICLK = 8 MHz
*6
—
Increase during BGO operation
R01DS0385EJ0100 Rev.1.00
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Page 29 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.10
Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
DCDC
*12
LDO mode
mode
Test
Conditions
*10
*10
Parameter
Symbol
Typ
2.80
0.90
Max
Typ
Max
—
Unit
*7
Supply
current
Middle- Normal All peripheral
ICLK = 24 MHz
ICLK = 4 MHz
I
—
—
1.65
0.55
mA
CC
*1
speed
mode
mode
clocks disabled,
CoreMark code
executing from
—
*2
*5
flash
*8
All peripheral
ICLK = 24 MHz
—
10.0
—
8.8
clocks enabled,
code executing
*5
from flash
*7
*8
Sleep
mode
All peripheral
clocks disabled
ICLK = 24 MHz
ICLK = 4 MHz
ICLK = 24 MHz
0.70
0.55
3.50
0.95
2.00
—
—
—
—
—
0.45
0.35
2.10
0.60
1.65
—
—
—
—
—
*5
All peripheral
clocks enabled
*5
ICLK = 4 MHz
*6
—
Increase during BGO operation
Normal All peripheral
*7
Supply
current
Low-
speed
mode
ICLK = 2 MHz
ICLK = 2 MHz
I
0.33
—
—
—
mA
CC
*1
mode
clocks disabled,
CoreMark code
executing from
*3
*5
flash
*8
All peripheral
—
3.1
—
—
clocks enabled,
code executing
*5
from flash
*7
*8
*8
Sleep
mode
All peripheral
clocks disabled
ICLK = 2 MHz
ICLK = 2 MHz
0.13
0.35
—
—
—
—
—
—
—
—
*5
All peripheral
—
*5
clocks enabled
Subosc- Normal All peripheral
ICLK = 32.768
kHz
I
540
µA
CC
speed
mode
mode
clocks enabled,
code executing
*4
*5
from flash
*8
*8
Sleep
mode
All peripheral
clocks disabled
ICLK = 32.768
kHz
2.00
5.85
—
—
—
—
—
—
*5
All peripheral
clocks enabled
ICLK = 32.768
kHz
*5
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs
are in the off state.
In LDO mode, the supply current is total current flowing into VCC.
In DCDC mode, the supply current is total current flowing into VCC and VCC_DCDC.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO and A/D operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. PCLKB and PCLKD are set to divided by 64.
Note 8. PCLKB and PCLKD are the same frequency as that of ICLK.
Note 9. PCLKB are set to be divided by 2 and PCLKD is the same frequency as that of ICLK.
Note 10. VCC = 3.3 V.
Note 11. The prefetch is operating.
Note 12. VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V
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Page 30 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.11
Operating and standby current (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
*3
Parameter
Symbol Typ
Max
2.2
5.3
20
Unit
Test conditions
Supply
current
Software
Standby
All
T = 25°C
I
0.30
µA
—
a
CC
*1
SRAMs(0x2000_00
00 to
0x2000_7FFF) are
on
T = 55°C
a
0.65
2.0
*2
mode
T = 85°C
a
T = 105°C
a
4.0
70
Only 8KB SRAM
(0x2000_4000 to
0x2000_5FFF) is on
T = 25°C
0.25
0.6
2.2
5.3
20
a
T = 55°C
a
T = 85°C
a
1.8
T = 105°C
3.65
0.30
70
a
Increment for RTC operation with low-speed on-
—
—
*4
chip oscillator
Increment for RTC operation in normal operation
mode with sub-clock oscillator
0.20
0.95
0.11
0.90
—
—
—
—
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
RCR4.ROPSEL is 0 (RTC
operation in normal operation
mode)
*4
SOMCR.SODRV[1:0] are 00b
(normal mode)
RCR4.ROPSEL is 0 (RTC
operation in normal operation
mode)
Increment for RTC operation in low-consumption
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
RCR4.ROPSEL is 1 (RTC
operation in low-consumption
clock mode)
*4
clock mode with sub-clock oscillator
SOMCR.SODRV[1:0] are 00b
(normal mode)
RCR4.ROPSEL is 1 (RTC
operation in low-consumption
clock mode)
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOS
transistors are in the off state. The supply current is total current flowing into VCC.
Note 2. The IWDT and LVD are not operating.
Note 3. VCC = 3.3 V.
Note 4. Includes the low-speed on-chip oscillator or sub-oscillation circuit current.
Table 2.12
Operating and standby current (3) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Analog power
supply current
During 12-bit A/D conversion (at high-speed
conversion)
I
—
—
1.44
mA
—
AVCC0
During 12-bit A/D conversion (at low-power
conversion)
—
—
0.78
mA
—
*1
—
—
—
—
0.8
1.0
mA
µA
—
—
During 12-bit D/A conversion
Waiting for 12-bit A/D and 12-bit D/A
*2
conversion (all units)
Reference
power supply
current
During 12-bit A/D conversion
I
I
—
—
—
—
120
60
µA
nA
—
—
REFH0
Waiting for 12-bit A/D conversion
Temperature Sensor (TSN) operating current
—
95
—
µA
—
TNS
R01DS0385EJ0100 Rev.1.00
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Page 31 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.12
Operating and standby current (3) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
—
Typ
12
Max
—
Unit
µA
Test conditions
Low-power
Analog
Window comparator (high-speed mode)
I
—
—
—
CMPLP
Comparator (high-speed mode)
Comparator (low-speed mode)
—
6.4
1.8
—
µA
Comparator
(ACMPLP)
operating
current
—
—
µA
Note 1. The reference power supply current is included in the power supply current value for D/A conversion.
Note 2. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC120 module-stop bit) is in the module-stop state.
2.2.6
VCC Rise and Fall Gradient and Ripple Frequency
Table 2.13
Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = 0 to 5.5 V
Parameter
Symbol
Min
Typ
Max
2
Unit
Test conditions
Power-on VCC
rising gradient
Voltage monitor 0 reset disabled at startup
SrVCC
0.02
—
ms/V
—
*1 *2
—
Voltage monitor 0 reset enabled at startup
*2
2
SCI boot mode
Note 1. When OFS1.LVDAS = 0.
Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Table 2.14
Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency f
within the range between the VCC upper limit (5.5 V) and lower limit (1.6
r(VCC)
V).
When the VCC change exceeds VCC ± 10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Allowable ripple frequency
f
—
—
10
kHz
Figure 2.2
r(VCC)
V
≤ VCC × 0.2
r (VCC)
—
—
—
—
1
MHz
MHz
ms/V
Figure 2.2
≤ VCC × 0.08
V
r (VCC)
—
10
—
Figure 2.2
≤ VCC × 0.06
V
r (VCC)
Allowable voltage change rising and
falling gradient
dt/dVCC
1.0
When VCC change exceeds VCC ± 10%
1 / fr(VCC)
VCC
Vr(VCC)
Figure 2.2
Ripple waveform
2.3
AC Characteristics
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Page 32 of 110
RA2L1 Datasheet
2. Electrical Characteristics
2.3.1
Frequency
Table 2.15
Operation frequency in high-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
*5
Parameter
Symbol Min
0.032768
Typ
—
Max
48
Unit
*1*2*4
Operation
frequency
1.8 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
f
MHz
System clock (ICLK)
*4
—
—
—
32
Peripheral module clock (PCLKB)
Peripheral module clock (PCLKD)
*3 *4
—
64
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or
erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as
1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.
Note 4. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.
Table 2.16
Operation frequency in middle-speed mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
*5
Parameter
Symbol Min
0.032768
Typ
—
Max
24
4
Unit
*1*2*4
Operation
frequency
1.8 to 5.5 V
1.6 to 1.8 V
1.8 to 5.5 V
1.6 to 1.8 V
1.8 to 5.5 V
1.6 to 1.8 V
f
MHz
System clock (ICLK)
0.032768
—
*4
—
—
—
—
—
24
4
Peripheral module clock (PCLKB)
Peripheral module clock (PCLKD)
—
*3 *4
—
24
4
—
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or
erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as
1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.
Note 4. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.
Table 2.17
Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
*5
Parameter
Symbol Min
0.032768
Typ
—
Max
Unit
*1*2*4
Operation
frequency
1.6 to 5.5 V
1.6 to 5.5 V
1.6 to 5.5 V
f
2
2
2
MHz
System clock (ICLK)
*4
—
—
—
Peripheral module clock (PCLKB)
Peripheral module clock (PCLKD)
*3 *4
—
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.
Note 4. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.
R01DS0385EJ0100 Rev.1.00
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Page 33 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.18
Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol Min
Typ
Max
Unit
*1*3
Operation
frequency
1.6 to 5.5 V
1.6 to 5.5 V
1.6 to 5.5 V
f
27.8528 32.768
37.6832
37.6832
37.6832
kHz
System clock (ICLK)
*3
—
—
—
—
Peripheral module clock (PCLKB)
Peripheral module clock (PCLKD)
*2 *3
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The ADC12 cannot be used.
Note 3. See section x, Clock Generation Circuit for the relationship of frequencies between ICLK, PCLKB, and PCLKD.
2.3.2
Clock Timing
Table 2.19
Parameter
Clock timing
Symbol
Min
50
20
20
—
Typ
—
Max
—
—
—
5
Unit
ns
Test conditions
Figure 2.3
EXTAL external clock input cycle time
EXTAL external clock input high pulse width
EXTAL external clock input low pulse width
EXTAL external clock rising time
t
t
t
t
t
t
f
Xcyc
—
ns
XH
—
ns
XL
—
ns
Xr
EXTAL external clock falling time
—
—
5
ns
Xf
*1
0.3
—
—
µs
—
EXTAL external clock input wait time
EXWT
EXTAL
EXTAL external clock input frequency
—
—
20
MHz
1.8 ≤ VCC ≤ 5.5
—
—
4
1.6 ≤ VCC < 1.8
Main clock oscillator oscillation frequency
f
1
—
20
MHz
1.8 ≤ VCC ≤ 5.5
MAIN
1
—
4
1.6 ≤ VCC < 1.8
LOCO clock oscillation frequency
f
t
f
f
t
f
27.8528
—
32.768
—
37.6832
100
17.25
9.2
kHz
µs
—
LOCO
LOCO clock oscillation stabilization time
IWDT-dedicated clock oscillation frequency
MOCO clock oscillation frequency
Figure 2.4
LOCO
12.75
6.8
—
15
8
kHz
MHz
µs
—
—
—
ILOCO
MOCO
MOCO
HOCO24
MOCO clock oscillation stabilization time
HOCO clock oscillation frequency
—
1
23.76
24
24.24
MHz
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
f
f
f
31.68
47.52
63.36
—
32
48
64
1.9
32.32
48.48
64.64
—
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
HOCO32
HOCO48
HOCO64
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
*3 *4
t
t
t
t
µs
Figure 2.5
HOCO clock oscillation stabilization time
HOCO24
HOCO32
HOCO48
HOCO64
Sub-clock oscillator oscillation frequency
f
t
—
—
32.768
0.5
—
—
kHz
s
—
SUB
*2
Figure 2.6
Sub-clock oscillation stabilization time
SUBOSC
Note 1. Time until the clock can be used after the Main Clock Oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the
external clock is stable.
Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the sub-clock oscillator
after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time value recommended by the oscillator
manufacturer.
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RA2L1 Datasheet
2. Electrical Characteristics
Note 3. This is a characteristic when the HOCOCR.HCSTP bit is set to 0 (oscillation) in the MOCO stop state. When the HOCOCR.HCSTP
bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 µs.
Note 4. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
tXcyc
tXH
tXL
EXTAL external clock input
VCC × 0.5
tXr
tXf
Figure 2.3
EXTAL external clock input timing
LOCOCR.LCSTP
tLOCO
LOCO clock oscillator output
Figure 2.4
LOCO clock oscillation start timing
HOCOCR.HCSTP
HOCO clock
*1
tHOCOx
Note:
x = 24, 32, 48, 64
Figure 2.5
HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
Figure 2.6
Sub-clock oscillation start timing
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RA2L1 Datasheet
2. Electrical Characteristics
2.3.3
Reset Timing
Table 2.20
Reset timing
Test
Parameter
Symbol
Min
10
30
—
Typ
—
Max
—
Unit
ms
µs
conditions
Figure 2.7
Figure 2.8
Figure 2.7
RES pulse width
At power-on
t
t
t
RESWP
RESW
Not at power-on
—
—
*1
Wait time after RES cancellation (at
power-on)
0.9
0.2
0.9
0.2
0.9
0.15
—
ms
LVD0 enabled
RESWT
*2
—
—
LVD0 disabled
*1
Wait time after RES cancellation (during
powered-on state)
t
—
—
ms
ms
Figure 2.8
Figure 2.9
LVD0 enabled
RESWT2
RESWT3
*2
—
—
LVD0 disabled
*1
Wait time after internal reset
t
—
—
LVD0 enabled
cancellation (Watchdog timer reset,
SRAM parity error reset, SRAM ECC
error reset, bus master MPU error
reset, bus slave MPU error reset, stack
pointer error reset, software reset)
*2
—
—
LVD0 disabled
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
VCC
RES
tRESWP
Internal reset
tRESWT
Figure 2.7
Reset input timing at power-on
tRESW
RES
Internal reset
tRESWT2
Figure 2.8
Reset input timing (1)
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RA2L1 Datasheet
2. Electrical Characteristics
tRESWIW, tRESWIR
Independent watchdog timer reset
Software reset
Internal reset
tRESWT3
Figure 2.9
Reset input timing (2)
2.3.4
Wakeup Time
Table 2.21
Parameter
Timing of recovery from low power modes (1)
Symbol
Min
Typ
Max
Unit
Test conditions
Recovery
time from
Software
Standby
High-
speed
mode
Crystal
resonator
connected to clock oscillator (20
main clock
oscillator
System clock
source is main
t
—
2
3
ms
Figure 2.10
SBYMC
*2
MHz)
*1
mode
External clock System clock
input to main source is main
t
—
2.4
3.1
µs
SBYEX
clock
oscillator
clock oscillator (20
MHz)
*3
System clock source is HOCO
(HOCO clock is 32 MHz)
t
t
t
t
—
—
—
—
4.9
4.8
4.9
4
6.2
6
µs
µs
µs
µs
SBYHO
SBYHO
SBYHO
SBYMO
System clock source is HOCO
(HOCO clock is 48 MHz)
System clock source is HOCO
(HOCO clock is 64 MHz)
6.2
5
System clock source is MOCO (8
MHz)
Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.
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RA2L1 Datasheet
2. Electrical Characteristics
Table 2.22
Parameter
Timing of recovery from low power modes (2)
Symbol
Min
Typ
Max
Unit
Test conditions
Recovery
time from
Software
Standby
Middle-
speed
mode
Crystal
resonator
connected to clock oscillator (20
main clock
oscillator
System clock
source is main
t
—
2
3
ms
Figure 2.10
SBYMC
*2
MHz)
*1
mode
External clock System clock
input to main source is main
t
—
—
2.4
3.1
13
µs
SBYEX
clock
oscillator
clock oscillator (20
MHz)
*3
VCC = 1.8 V to 5.5
V
System clock
11.7
source is main
clock oscillator (20
*3
MHz)
VCC = 1.6 V to 1.8
V
System clock VCC = 1.8 V to 5.5
t
t
—
—
—
—
5.2
13.2
4
6.5
15
5
µs
µs
SBYHO
source is
HOCO
V
*4
VCC = 1.6 V to 1.8
V
System clock VCC = 1.8 V to 5.5
SBYMO
source is
MOCO (8
MHz)
V
VCC = 1.6 V to 1.8
V
7.2
9
Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.
Note 4. The system clock is 24 MHz.
Table 2.23
Parameter
Timing of recovery from low power modes (3)
Symbol
Min
Typ
Max
Unit
Test conditions
Recovery
time from
Software
Standby
Low-speed Crystal
mode resonator
System clock
source is main
t
—
2
3
ms
Figure 2.10
SBYMC
connected to clock oscillator (2
main clock
oscillator
*2
MHz)
*1
mode
External clock System clock
input to main source is main
t
t
—
—
14.5
12
16
15
µs
µs
SBYEX
SBYMO
clock
oscillator
clock oscillator (2
MHz)
*3
System clock source is MOCO (2
MHz)
Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.
Table 2.24
Parameter
Timing of recovery from low power modes (4)
Symbol
Min
Typ
Max
Unit
Test conditions
Recovery time
from Software
Standby mode
Subosc-speed mode System clock source is
sub-clock oscillator
t
—
0.85
1
ms
Figure 2.10
SBYSC
*1
(32.768 kHz)
System clock source is
LOCO (32.768 kHz)
t
—
0.85
1.2
ms
SBYLO
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RA2L1 Datasheet
2. Electrical Characteristics
Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode.
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX,
tSBYMO, tSBYHO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Figure 2.10
Software Standby mode cancellation timing
Table 2.25
Parameter
Timing of recovery from low power modes (5)
Symbol
Min
Typ
Max
Unit
Test conditions
Recovery time from Software High-speed mode
t
—
4.1
5.2
µs
Figure 2.11
SNZ
Standby mode to Snooze
mode
System clock source is
HOCO
Middle-speed mode
System clock source is
HOCO (24 MHz)
t
—
—
—
4.2
8.3
6.7
5.3
10
µs
µs
µs
SNZ
VCC = 1.8 V to 5.5 V
Middle-speed mode
System clock source is
HOCO (24 MHz)
t
t
SNZ
SNZ
VCC = 1.6 V to 1.8 V
Low-speed mode
System clock source is
MOCO (2 MHz)
8.0
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RA2L1 Datasheet
2. Electrical Characteristics
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.11
Recovery timing from Software Standby mode to Snooze mode
2.3.5
NMI and IRQ Noise Filter
Table 2.26
Parameter
NMI and IRQ noise filter
Symbol
Min
Typ
—
Max
—
Unit
Test conditions
NMI pulse
width
t
200
ns
NMI digital filter disabled
t
t
× 2 ≤ 200 ns
× 2 > 200 ns
NMIW
Pcyc
*1
—
—
t
× 2
Pcyc
Pcyc
200
—
—
—
—
NMI digital filter enabled
t
t
× 3 ≤ 200 ns
× 3 > 200 ns
NMICK
NMICK
t
×
NMICK
*2
3.5
IRQ pulse
width
t
200
—
—
—
—
ns
IRQ digital filter disabled
IRQ digital filter enabled
t
t
× 2 ≤ 200 ns
× 2 > 200 ns
IRQW
Pcyc
*1
t
× 2
Pcyc
Pcyc
200
—
—
—
—
t
t
× 3 ≤ 200 ns
× 3 > 200 ns
IRQCK
IRQCK
t
×
IRQCK
*3
3.5
Note:
Note:
200 ns minimum in Software Standby mode.
If the clock source is being switched it is needed to add 4 clock cycle of switched source.
Note 1.
Note 2.
Note 3.
t
t
t
indicates the PCLKB cycle.
Pcyc
indicates the cycle of the NMI digital filter sampling clock.
NMICK
IRQCK
indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
NMI
tNMIW
Figure 2.12
NMI interrupt input timing
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RA2L1 Datasheet
2. Electrical Characteristics
IRQ
tIRQW
Figure 2.13
IRQ interrupt input timing
2.3.6
I/O Ports, POEG, GPT, AGT, KINT, and ADC12 Trigger Timing
Table 2.27
I/O Ports, POEG, GPT, AGT, KINT, and ADC12 trigger timing
Test
Parameter
Symbol Min
Max
Unit
conditions
I/O Ports
Input data pulse width
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 2.4 V
t
2
—
t
Figure 2.14
PRW
Pcyc
3
4
POEG
GPT
POEG input trigger pulse width
Input capture pulse width
t
t
3
—
—
—
—
—
—
—
—
—
—
—
—
—
t
t
Figure 2.15
Figure 2.16
POEW
GTICW
Pcyc
Single edge
1.5
2.5
250
2000
100
800
62.5
125
250
500
1.5
250
PDcyc
Dual edge
*1
AGT
AGTIO, AGTEE input cycle
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
ns
ns
ns
ns
ns
ns
ns
ns
Figure 2.17
t
ACYC
AGTIO, AGTEE input high-level 1.8 V ≤ VCC ≤ 5.5 V
width, low-level width
t
t
,
ACKWH
ACKWL
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTO, AGTOA,
AGTOB output cycle
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
t
Figure 2.17
ACYC2
ADC12
KINT
12-bit A/D converter trigger input pulse width
KRn (n = 00 to 07) pulse width
t
t
t
Figure 2.18
Figure 2.19
TRGW
KR
Pcyc
ns
Note 1. Constraints on AGTIO input: t
× 2 (t
: PCLKB cycle) < t
.
Pcyc
Pcyc
ACYC
Port
tPRW
Figure 2.14
I/O ports input timing
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RA2L1 Datasheet
2. Electrical Characteristics
POEG input trigger
tPOEW
Figure 2.15
POEG input trigger timing
Input capture
tGTICW
Figure 2.16
GPT input capture timing
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.17
AGT I/O timing
ADTRG0
tTRGW
Figure 2.18
ADC12 trigger input timing
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RA2L1 Datasheet
2. Electrical Characteristics
KR00 to KR07
tKR
Figure 2.19
Key interrupt input timing
2.3.7
CAC Timing
Table 2.28
CAC timing
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol Min
4.5 × t
Typ
Max
Unit
Test conditions
*1
*1
*2
*2
CAC
CACREF input pulse
width
t
+ 3 × t
—
—
ns
—
t
t
≤ t
> t
CACREF
CAC
Pcyc
Pcyc
CAC
5 × t
+ 6.5 × t
—
—
ns
CAC
Pcyc
Pcyc
CAC
Note 1.
Note 2.
t
t
: PCLKB cycle.
: CAC count clock source cycle.
Pcyc
CAC
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RA2L1 Datasheet
2. Electrical Characteristics
2.3.8
SCI Timing
Table 2.29
SCI timing (1)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
*1
Parameter
Symbol
Min
125
250
500
1000
187.5
375
750
1500
0.4
Max
—
—
—
—
—
—
—
—
0.6
20
20
—
—
—
—
—
—
—
—
0.6
20
30
20
30
40
45
Unit
Test conditions
SCI
Input clock cycle Asynchronous
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
t
ns
Figure 2.20
Scyc
Clock
synchronous
Input clock pulse width
Input clock rise time
Input clock fall time
t
t
t
t
t
Scyc
SCKW
SCKr
SCKf
Scyc
—
ns
ns
ns
—
Output clock
cycle
Asynchronous
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
187.5
375
750
1500
125
250
500
1000
0.4
Clock
synchronous
Output clock pulse width
Output clock rise time
t
t
t
Scyc
SCKW
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
—
ns
ns
ns
SCKr
—
Output clock fall time
t
t
—
SCKf
—
Transmit data
delay time
(master)
Clock
synchronous
—
Figure 2.21
TXD
—
Transmit data
delay time (slave) synchronous
Clock
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 2.7 V
—
55
60
100
125
—
ns
—
—
—
Receive data
setup time
(master)
Clock
synchronous
t
45
55
90
110
40
45
ns
RXS
—
—
—
Receive data
setup time
(slave)
Clock
synchronous
—
ns
ns
ns
—
Receive data
hold time
(master)
Clock synchronous
Clock synchronous
t
t
5
—
—
RXH
Receive data
40
RXH
hold time (slave)
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RA2L1 Datasheet
2. Electrical Characteristics
Note 1.
t
: PCLKB cycle.
Pcyc
tSCKW
tSCKr
tSCKf
SCKn
tScyc
Note:
n = 0 to 3, 9
Figure 2.20
SCK clock input timing
SCKn
TXDn
RXDn
tTXD
tRXS tRXH
Note:
n = 0 to 3, 9
Figure 2.21
SCI input/output timing in clock synchronous mode
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Page 45 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.30
SCI timing (2) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
conditions
*1
Parameter
Symbol
Min
125
250
500
1000
187.5
375
750
1500
0.4
0.4
—
Max
—
Unit
Simple SCK clock cycle output
2.7 V ≤ VCC ≤ 5.5 V
t
ns
Figure 2.22
SPcyc
SPI
(master)
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
—
—
—
SCK clock cycle input
(slave)
—
—
—
—
SCK clock high pulse width
SCK clock low pulse width
t
t
0.6
0.6
20
30
—
t
t
SPCKWH
SPcyc
SPCKWL
SPcyc
SCK clock rise and fall
time
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 2.7 V
t
t
,
ns
SPCKr
SPCKf
—
Data input
setup time
Master
t
45
ns
Figure 2.23 to
Figure 2.26
SU
55
—
80
—
110
40
—
Slave
—
45
—
Data input
hold time
Master
Slave
t
33.3
40
—
ns
H
—
SS input setup time
SS input hold time
t
t
t
1
—
t
t
LEAD
LAG
OD
SPcyc
1
—
SPcyc
Data output
delay time
Master
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
—
40
50
65
100
125
—
ns
ns
ns
—
Slave
—
—
—
Data output
hold time
Master
t
t
-10
-20
-30
-40
-10
—
OH
—
—
—
Slave
—
Data rise and
fall time
Master
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
, t
20
30
20
30
Dr Df
—
Slave
—
—
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Page 46 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.30
SCI timing (2) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Test
conditions
*1
Parameter
Symbol
Min
—
Max
6
Unit
Simple Slave access time
SPI
2.4 V ≤ VCC ≤ 5.5 V
t
t
Figure 2.26
SA
Pcyc
1.8 V ≤ VCC < 2.4 V 24 MHz ≤ PCLKB ≤
32 MHz
—
7
PCLKB < 24 MHz
—
—
—
—
6
6
6
7
1.6 V ≤ VCC < 1.8 V
Slave output release time 2.4 V ≤ VCC ≤ 5.5 V
t
t
REL
Pcyc
1.8 V ≤ VCC < 2.4 V 24 MHz ≤ PCLKB ≤
32 MHz
PCLKB < 24 MHz
—
—
6
6
1.6 V ≤ VCC < 1.8 V
Note 1.
t
: PCLKB cycle.
Pcyc
tSPCKr
tSPCKf
tSPCKWH
VOH
VOH
VOL
VOH
VOH
SCKn
master select
VOL
tSPCKWL
VOL
output
tSPcyc
tSPCKr
tSPCKf
tSPCKWH
VIH
VIH
VIL
VIH
VIH
SCKn
slave select input
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n = 0 to 3, 9
Figure 2.22
SCI simple SPI mode clock timing
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RA2L1 Datasheet
2. Electrical Characteristics
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = 0 to 3, 9
Figure 2.23
SCI simple SPI mode timing (master, CKPH = 1)
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = 0 to 3, 9
Figure 2.24
SCI simple SPI mode timing (master, CKPH = 0)
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 48 of 110
RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
MSB OUT
DATA
LSB OUT
LSB IN
MSB IN
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
Note:
n = 0 to 3, 9
Figure 2.25
SCI simple SPI mode timing (slave, CKPH = 1)
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
tREL
MISOn
output
LSB OUT
(Last data)
MSB OUT
tH
DATA
LSB OUT
MSB OUT
MSB IN
tSU
tDr, tDf
MOSIn
input
MSB IN
DATA
LSB IN
Note:
n = 0 to 3, 9
Figure 2.26
SCI simple SPI mode timing (slave, CKPH = 0)
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Page 49 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.31
SCI timing (3)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
Symbol
Min
—
—
0
Max
1000
300
Unit
ns
Test conditions
Simple IIC
SDA input rise time
t
t
t
Figure 2.27
Sr
(Standard mode)
SDA input fall time
ns
Sf
*1
SDA input spike pulse removal time
ns
4 × t
SP
IICcyc
Data input setup time
Data input hold time
t
t
250
0
—
ns
ns
pF
SDAS
—
SDAH
*2
SCL, SDA capacitive load
—
400
C
b
Sr
Sf
Simple IIC (Fast SDA input rise time
t
t
t
—
—
0
300
300
ns
ns
ns
Figure 2.27
mode)
SDA input fall time
*1
SDA input spike pulse removal time
4 × t
—
SP
IICcyc
Data input setup time
Data input hold time
t
t
100
0
ns
ns
pF
SDAS
—
SDAH
*2
SCL, SDA capacitive load
—
400
C
b
Note 1.
t
: Clock cycle selected by the SMR.CKS[1:0] bits.
IICcyc
Note 2. C indicates the total capacity of the bus line.
b
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
P*1
P*1
S*1
Sr*1
tSDAH
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Note:
n = 0 to 3, 9
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.27
SCI simple IIC mode timing
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RA2L1 Datasheet
2. Electrical Characteristics
2.3.9
SPI Timing
Table 2.32
SPI timing (1 of 3)
Test
conditions
*1
Parameter
Symbol Min
Max
—
—
—
—
—
—
—
—
—
Unit
SPI RSPCK
Master 2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
t
62.5
125
ns
Figure 2.28
C = 30 pF
SPcyc
clock cycle
1.8 V ≤ VCC < 2.4 V
250
1.6 V ≤ VCC < 1.8 V
500
Slave
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
187.5
375
750
1500
RSPCK
clock high
pulse width
Master
t
t
(t
-
-
ns
ns
SPCKWH
SPcyc
t
t
SPCKr
) / 2 -
SPCKf
3
Slave
3 × t
—
—
Pcyc
RSPCK
Master
(t
-
SPCKWL
SPcyc
clock low
pulse width
t
t
-
SPCKr
) / 2 -
SPCKf
3
Slave
3 × t
—
—
—
—
—
—
10
15
20
30
1
Pcyc
RSPCK
clock rise
and fall time
Output 2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC ≤ 2.4 V
1.6 V ≤ VCC < 1.8 V
Input
t
t
,
ns
µs
SPCKr
SPCKf
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Page 51 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.32
SPI timing (2 of 3)
Test
conditions
*1
Parameter
Symbol Min
Max
—
Unit
SPI Data input
setup time
Master 2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V 16 MHz < PCLKB ≤ 32
t
10
30
ns
Figure 2.29
to Figure
2.34
SU
—
MHz
C = 30 pF
PCLKB ≤ 16 MHz
10
55
—
—
1.8 V ≤ VCC < 2.4 V 16 MHz < PCLKB ≤ 32
MHz
8 MHz < PCLKB ≤ 16
MHz
30
—
PCLKB ≤ 8 MHz
1.6 V ≤ VCC < 1.8 V
10
10
10
15
20
0
—
—
—
—
—
—
Slave
2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Data input
hold time
Master
t
t
ns
ns
HF
(RSPCK is PCLKB/2)
Master
t
—
H
Pcyc
(RSPCK is not PCLKB/2)
Slave
t
t
20
—
—
H
SPI SSL setup
time
Master 1.8 V ≤ VCC ≤ 5.5 V
-30 + N ×
LEAD
*2
t
SPcyc
1.6 V ≤ VCC < 1.8 V
-50 + N ×
—
*2
t
SPcyc
Slave
6 × t
—
—
ns
ns
Pcyc
SSL hold
time
Master
t
t
-30 + N ×
LAG
*3
t
SPcyc
Slave
6 × t
—
—
—
—
—
—
—
—
0
—
ns
ns
Pcyc
Data output Master 2.7 V ≤ VCC ≤ 5.5 V
14
20
25
30
50
60
85
110
—
OD
delay time
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Slave
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Data output Master
t
t
ns
ns
OH
TD
hold time
Slave
0
—
Successive Master
transmission
t
t
+ 2 × 8 × t
2 × t
+
SPcyc
SPcyc
Pcyc
Pcyc
delay time
Slave
6 × t
—
Pcyc
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RA2L1 Datasheet
2. Electrical Characteristics
Table 2.32
SPI timing (3 of 3)
Test
conditions
*1
Parameter
Symbol Min
Max
10
15
20
30
1
Unit
SPI MOSI and
MISO rise
Output 2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Input
t
, t
—
—
—
—
—
—
—
—
—
—
—
ns
Figure 2.29
to Figure
2.34
Dr Df
and fall time
C = 30 pF
µs
ns
SSL rise and Output 2.7 V ≤ VCC ≤ 5.5 V
fall time
t
t
,
10
15
20
30
1
SSLr
SSLf
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Input
µs
ns
Slave access time
2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
t
2 × t
100
+
+
+
+
+
+
Figure 2.33
and Figure
2.34
SA
Pcyc
Pcyc
Pcyc
Pcyc
Pcyc
Pcyc
—
—
—
—
—
2 × t
140
C = 30 pF
2 × t
180
Slave output release
time
t
2 × t
100
ns
REL
2 × t
140
2 × t
180
Note 1.
t
: PCLKB cycle.
Pcyc
Note 2. N is set as an integer from 1 to 8 by the SPCKD register.
Note 3. N is set as an integer from 1 to 8 by the SSLND register.
tSPCKr
tSPCKf
tSPCKWH
VOH
VOH
VOL
VOH
VOH
RSPCKn
master select
output
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKf
tSPCKWH
VIH
VIH
VIL
VIH
VIH
RSPCKn
slave select input
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n = A or B
Figure 2.28
SPI clock timing
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RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = A or B
Figure 2.29
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tHF
tHF
MISOn
input
LSB IN
MSB IN
DATA
MSB IN
tDr, tDf
tOH
tOD
MOSIn
output
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
Note:
n = A or B
Figure 2.30
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2)
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Page 54 of 110
RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = A or B
Figure 2.31
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tHF
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = A or B
Figure 2.32
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2)
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Page 55 of 110
RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
MSB OUT
DATA
LSB OUT
LSB IN
MSB IN
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
Note:
n = A or B
Figure 2.33
SPI timing (slave, CPHA = 0)
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
LSB OUT
(Last data)
MSB OUT
tH
DATA
LSB OUT
MSB OUT
MSB IN
tSU
tDr, tDf
MOSIn
input
MSB IN
DATA
LSB IN
Note:
n = A or B
Figure 2.34
SPI timing (slave, CPHA = 1)
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Page 56 of 110
RA2L1 Datasheet
2. Electrical Characteristics
2.3.10
IIC Timing
Table 2.33
IIC timing (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
*1
Parameter
Symbol
Min
Max
—
Unit Test conditions
IIC (standard mode, SCL input cycle time
SMBus)
t
t
t
t
t
t
6 (12) × t
+ 1300
IICcyc
ns
ns
ns
ns
ns
ns
Figure 2.35
SCL
SCLH
SCLL
Sr
SCL input high pulse width
3 (6) × t
+ 300
+ 300
—
IICcyc
IICcyc
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
3 (6) × t
—
—
—
0
1000
300
1 (4) × t
Sf
SCL, SDA input spike pulse
removal time
SP
IICcyc
SDA input bus free time (when
wakeup function is disabled)
t
t
3 (6) × t
3 (6) × t
+ 300
+ 4 ×
—
—
ns
ns
BUF
BUF
IICcyc
SDA input bus free time (when
wakeup function is enabled)
IICcyc
t
+ 300
Pcyc
START condition input hold time
(when wakeup function is disabled)
t
t
t
t
+ 300
—
—
—
ns
ns
ns
STAH
STAH
IICcyc
START condition input hold time
(when wakeup function is enabled)
1 (5) × t
300
+ t
+
Pcyc
IICcyc
Repeated START condition input
setup time
1000
STAS
STOP condition input setup time
Data input setup time
t
t
t
1000
—
ns
ns
ns
pF
STOS
SDAS
SDAH
t
+ 50
—
IICcyc
Data input hold time
0
—
SCL, SDA capacitive load
C
—
400
b
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Page 57 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.33
IIC timing (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
*1
Parameter
Symbol
Min
Max
—
Unit Test conditions
IIC (Fast mode)
SCL input cycle time
t
t
t
t
t
t
6 (12) × t
+ 600
IICcyc
ns
ns
ns
ns
ns
ns
Figure 2.35
SCL
SCLH
SCLL
Sr
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
3 (6) × t
+ 300
+ 300
—
IICcyc
IICcyc
3 (6) × t
—
—
—
0
300
300
1 (4) × t
Sf
SCL, SDA input spike pulse
removal time
SP
IICcyc
SDA input bus free time (When
wakeup function is disabled)
t
t
3 (6) × t
3 (6) × t
+ 300
+ 4 ×
—
—
ns
ns
BUF
BUF
IICcyc
SDA input bus free time (When
wakeup function is enabled)
IICcyc
t
+ 300
Pcyc
START condition input hold time
(When wakeup function is
disabled)
t
t
+ 300
—
ns
STAH
IICcyc
START condition input hold time
(When wakeup function is enabled)
t
t
1 (5) × t
300
+ t +
Pcyc
—
—
ns
ns
STAH
IICcyc
Repeated START condition input
setup time
300
STAS
STOP condition input setup time
Data input setup time
t
t
t
300
—
ns
ns
ns
pF
STOS
SDAS
SDAH
t
+ 50
—
IICcyc
Data input hold time
0
—
SCL, SDA capacitive load
C
—
400
b
Note:
t
: IIC internal reference clock (IICφ) cycle, t
: PCLKB cycle
Pcyc
IICcyc
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
VIH
SDA0 and SDA1
VIL
tBUF
tSCLH
tSTAS
tSTOS
tSTAH
tSP
SCL0 and SCL1
P*1
P*1
S*1
tSf
Sr*1
tSCLL
tSr
tSDAS
tSCL
tSDAH
Note:
n = 0, 1
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
I2C bus interface input/output timing
Figure 2.35
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Page 58 of 110
RA2L1 Datasheet
2. Electrical Characteristics
2.3.11
CLKOUT Timing
Table 2.34
Parameter
CLKOUT
CLKOUT timing
Symbol
Min
62.5
125
250
15
Max
—
Unit
Test conditions
*1
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
t
ns
Figure 2.36
CLKOUT pin output cycle
Ccyc
—
—
CLKOUT pin high pulse
t
t
t
t
—
ns
ns
ns
ns
CH
CL
Cr
*2
width
30
—
150
15
—
CLKOUT pin low pulse
—
*2
width
30
—
150
—
—
CLKOUT pin output rise time 2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
12
25
50
12
25
50
—
1.6 V ≤ VCC < 1.8 V
—
CLKOUT pin output fall time
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
—
Cf
—
—
Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the
CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, specifications in Table 2.34 should be satisfied with 45% to 55% of
input duty cycle.
Note 2. When MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio to
be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
tCcyc
tCH
tCf
CLKOUT
tCr
tCL
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 2.36
CLKOUT output timing
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Page 59 of 110
RA2L1 Datasheet
2. Electrical Characteristics
2.4
ADC12 Characteristics
VREFH0
5.5
VREFH0
5.5
A/D Conversion
Characteristics (1)
5.0
4.0
3.0
5.0
4.0
3.0
A/D Conversion
Characteristics (2)
A/D Conversion
Characteristics (4)
A/D Conversion
Characteristics (5)
A/D Conversion
Characteristics (3)
2.7
2.4
2.7
2.4
A/D Conversion
2.0
2.0
1.8
1.6
Characteristics (6)
A/D Conversion
Characteristics (7)
1.0
1.0
2.42.7
3.0
5.5
AVCC0
1.8 2.42.7
1.0 1.6 2.0 3.0
5.5
AVCC0
1.0
2.0
4.0
5.0
4.0
5.0
ADCSR.ADHSC = 0
ADCSR.ADHSC = 1
Figure 2.37
Table 2.35
AVCC0 to VREFH0 voltage range
A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 4.5 to 5.5 V , VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
64
Unit
MHz
MHz
pF
Test conditions
PCLKD (ADCLK) frequency
1
—
ADACSR.ADSAC = 0
ADACSR.ADSAC = 1
High-precision channel
48
*2
*3
Cs
Rs
—
—
—
—
—
—
—
—
Analog input capacitance
9
*3
pF
kΩ
kΩ
Normal-precision channel
High-precision channel
Normal-precision channel
10
*3
Analog input resistance
1.3
5.0
*3
Analog input voltage range Ain
0
—
—
—
VREFH0
V
—
—
Resolution
—
12
—
Bit
µs
*1
Permissible 0.70
signal
source
impedance
Max. = 0.3
kΩ
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0D
ADACSR.ADSAC = 0
Conversion time
(Operation at PCLKD = 64
MHz)
*4
*4
(0.211)
1.34
(0.852)
—
—
—
—
—
—
µs
µs
µs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x36
ADACSR.ADSAC = 0
*1
Permissible 0.67
signal
source
impedance
Max. = 0.3
kΩ
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
Conversion time
*4
*4
(Operation at PCLKD = 48
MHz)
(0.219)
1.29
(0.844)
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x28
ADACSR.ADSAC = 1
Offset error
—
—
±1.0
±1.0
±4.5
±6.0
±4.5
±6.0
LSB
LSB
LSB
LSB
High-precision channel
Other than specified
High-precision channel
Other than specified
Full-scale error
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2. Electrical Characteristics
Table 2.35
A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 4.5 to 5.5 V , VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
—
Typ
±0.5
±2.5
Max
—
Unit
LSB
LSB
LSB
LSB
LSB
Test conditions
Quantization error
Absolute accuracy
—
—
±5.0
±8.0
—
High-precision channel
Other than specified
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
±1.0
±1.5
—
—
±3.0
Note:
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Note 4. ( ) lists sampling time.
Note 5. When VREFH0 < AVCC0, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.36
A/D conversion characteristics (2) in high-speed A/D conversion mode
*5
Conditions: VCC = AVCC0 = VREFH0 = 2.7 to 5.5 V , VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
1
Typ
—
Max
Unit
MHz
pF
Test conditions
—
PCLKD (ADCLK) frequency
48
*2
*3
Cs
Rs
—
—
High-precision channel
Analog input capacitance
9
*3
—
—
—
—
—
—
pF
kΩ
kΩ
Normal-precision channel
High-precision channel
Normal-precision channel
10
*3
Analog input resistance
1.9
*3
6.0
Analog input voltage range Ain
0
—
—
—
VREFH0
V
—
—
Resolution
—
12
—
Bit
µs
*1
Permissible 0.67
signal
source
impedance
Max. = 0.3
kΩ
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
Conversion time
(Operation at PCLKD = 48
MHz)
*4
*4
(0.219)
1.29
(0.844)
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x28
ADACSR.ADSAC = 1
Offset error
—
—
±1.0
±1.0
±5.5
±7.0
±5.5
±7.0
—
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
High-precision channel
Other than specified
High-precision channel
Other than specified
—
Full-scale error
Quantization error
Absolute accuracy
—
—
±0.5
±2.5
±6.0
±9.0
—
High-precision channel
Other than specified
—
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
±1.0
±1.5
±3.0
—
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2. Electrical Characteristics
Note:
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Note 4. ( ) lists sampling time.
Note 5. When VREFH0 < AVCC0, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.37
A/D conversion characteristics (3) in high-speed A/D conversion mode
*5
Conditions: VCC = AVCC0 = VREFH0 = 2.4 to 5.5 V , VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
1
Max
Unit
MHz
pF
Test conditions
—
PCLKD (ADCLK) frequency
—
—
32
*2
*3
Cs
Rs
—
High-precision channel
Analog input capacitance
9
*3
—
—
—
—
—
—
pF
kΩ
kΩ
Normal-precision channel
High-precision channel
Normal-precision channel
10
*3
Analog input resistance
2.2
*3
7.0
Analog input voltage range Ain
0
—
—
—
VREFH0
V
—
—
Resolution
—
12
—
Bit
µs
*1
Permissible 1.00
signal
source
impedance
Max. = 1.3
kΩ
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
Conversion time
(Operation at PCLKD = 32
MHz)
*4
*4
(0.328)
1.94
(1.266)
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x28
ADACSR.ADSAC = 1
Offset error
—
—
±1.0
±1.0
±5.5
±7.0
±5.5
±7.0
—
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
High-precision channel
Other than specified
High-precision channel
Other than specified
—
Full-scale error
Quantization error
Absolute accuracy
—
—
±0.5
±2.50
±6.0
±9.0
—
High-precision channel
Other than specified
—
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
±1.0
±1.5
±3.0
—
Note:
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Note 4. ( ) lists sampling time.
Note 5. When VREFH0 < AVCC0, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
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2. Electrical Characteristics
Table 2.38
A/D conversion characteristics (4) in low-power A/D conversion mode
*5
Conditions: VCC = AVCC0 = VREFH0 = 2.7 to 5.5 V , VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
1
Typ
—
Max
Unit
MHz
pF
Test conditions
—
PCLKD (ADCLK) frequency
24
*2
*3
Cs
Rs
—
—
High-precision channel
Analog input capacitance
9
*3
—
—
—
—
—
—
pF
kΩ
kΩ
Normal-precision channel
High-precision channel
Normal-precision channel
10
*3
Analog input resistance
1.9
*3
6
Analog input voltage range Ain
0
—
—
—
VREFH0
V
—
—
Resolution
—
12
—
Bit
µs
*1
Permissible 1.58
signal
source
impedance
Max. = 1.1
kΩ
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
Conversion time
(Operation at PCLKD = 24
MHz)
*4
(0.438)
*4
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
2.0 (0.854)
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
Offset error
—
—
±1.25
±1.25
±6.0
±7.5
±6.0
±7.5
—
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
High-precision channel
Other than specified
High-precision channel
Other than specified
—
Full-scale error
Quantization error
Absolute accuracy
—
—
±0.5
±3.25
±7.0
±10.0
—
High-precision channel
Other than specified
—
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
±1.5
±1.75
±4.0
—
Note:
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Note 4. ( ) lists sampling time.
Note 5. When VREFH0 < AVCC0, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.39
A/D conversion characteristics (5) in low-power A/D conversion mode (1 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 2.4 to 5.5 V , VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
1
Typ
—
Max
Unit
MHz
pF
Test conditions
—
PCLKD (ADCLK) frequency
16
*2
*3
Cs
Rs
—
—
High-precision channel
Analog input capacitance
9
*3
—
—
—
—
—
—
pF
kΩ
kΩ
Normal-precision channel
High-precision channel
Normal-precision channel
10
*3
Analog input resistance
2.2
*3
7
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2. Electrical Characteristics
Table 2.39
A/D conversion characteristics (5) in low-power A/D conversion mode (2 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 2.4 to 5.5 V , VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
0
Typ
—
Max
VREFH0
12
Unit
V
Test conditions
Analog input voltage range Ain
—
—
Resolution
—
—
Bit
µs
*1
Permissible 2.38
—
—
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
Conversion time
(Operation at PCLKD = 16
MHz)
*4
signal
(0.656)
source
impedance
Max. = 2.2
kΩ
*4
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
3.0 (1.281)
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
Offset error
—
—
±1.25
±1.25
±6.0
±7.5
±6.0
±7.5
—
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
High-precision channel
Other than specified
High-precision channel
Other than specified
—
Full-scale error
Quantization error
Absolute accuracy
—
—
±0.5
±3.25
±7.0
±10.0
—
High-precision channel
Other than specified
—
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
±1.5
±1.75
±4.0
—
Note:
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Note 4. ( ) lists sampling time.
Note 5. When VREFH0 < AVCC0, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.40
A/D conversion characteristics (6) in low-power A/D conversion mode (1 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
1
Typ
—
Max
Unit
MHz
pF
Test conditions
—
PCLKD (ADCLK) frequency
8
*2
*3
Cs
Rs
—
—
High-precision channel
Analog input capacitance
9
*3
—
—
—
—
—
—
pF
kΩ
kΩ
Normal-precision channel
High-precision channel
Normal-precision channel
10
*3
Analog input resistance
6
*3
14
Analog input voltage range Ain
Resolution
0
—
—
VREFH0
12
V
—
—
—
Bit
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2. Electrical Characteristics
Table 2.40
A/D conversion characteristics (6) in low-power A/D conversion mode (2 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
*1
Permissible 4.75
—
—
µs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
Conversion time
*4
signal
source
(Operation at PCLKD = 8
MHz)
(1.313)
impedance
Max. = 5 kΩ
*4
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
6.0 (2.563)
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
Offset error
—
—
±1.25
±1.5
±7.5
±10.0
±7.5
±10.0
—
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
High-precision channel
Other than specified
High-precision channel
Other than specified
—
Full-scale error
Quantization error
Absolute accuracy
—
—
±0.5
±3.75
±9.5
±13.5
—
High-precision channel
Other than specified
—
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
±2.0
±2.25
±4.5
—
Note:
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Note 4. ( ) lists sampling time.
Note 5. When VREFH0 < AVCC0, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.41
A/D conversion characteristics (7) in low-power A/D conversion mode (1 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
1
Typ
—
Max
Unit
MHz
pF
Test conditions
—
PCLKD (ADCLK) frequency
4
*2
*3
Cs
Rs
—
—
High-precision channel
Analog input capacitance
9
*3
—
—
—
—
—
—
pF
kΩ
kΩ
Normal-precision channel
High-precision channel
Normal-precision channel
10
*3
Analog input resistance
12
*3
28
Analog input voltage range Ain
0
—
—
—
VREFH0
V
—
—
Resolution
—
12
—
Bit
µs
*1
*4
Permissible
signal
source
impedance
Max. = 9.9
kΩ
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
Conversion time
(Operation at PCLKD = 4
MHz)
9.5 (2.625)
12.0
(5.125)
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
*4
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
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2. Electrical Characteristics
Table 2.41
A/D conversion characteristics (7) in low-power A/D conversion mode (2 of 2)
*5
Conditions: VCC = AVCC0 = VREFH0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
±7.5
±10.0
±7.5
±10.0
—
Unit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Test conditions
High-precision channel
Other than specified
High-precision channel
Other than specified
—
Offset error
—
±1.25
Full-scale error
—
±1.5
Quantization error
Absolute accuracy
—
—
±0.5
±3.75
±9.5
±13.5
—
High-precision channel
Other than specified
—
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
±2.0
±2.25
±4.5
—
Note:
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Note 4. ( ) lists sampling time.
Note 5. When VREFH0 < AVCC0, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between AVCC0 and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Figure 2.38 shows the equivalent circuit for analog input.
MCU
Analog input
Rs
ADC12
ANn
Vi
Cin
Cs
Note:
Terminal leakage current is not shown in this figure.
Figure 2.38
Table 2.42
Equivalent circuit for analog input
12-bit A/D converter channel classification
Classification
Channel
Conditions
Remarks
High-precision channel
Normal-precision channel
AN000 to AN014
AN017 to AN020
AVCC0 = 1.6 to 5.5 V
Pins AN000 to AN014 cannot
be used as general I/O, TS
transmission, when the A/D
converter is in use.
Internal reference voltage input channel
Temperature sensor input channel
Input channel from CTSU
Internal reference voltage
AVCC0 = 1.8 to 5.5 V
AVCC0 = 1.8 to 5.5 V
AVCC0 = 1.6 to 5.5 V
—
—
—
Temperature sensor output
CTSU TSCAP voltage
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2. Electrical Characteristics
Table 2.43
A/D internal reference voltage characteristics
*1
Conditions: VCC = AVCC0 = VREFH0 = 1.8 to 5.5 V
Parameter
Min
1.42
1
Typ
1.48
—
Max
1.54
2
Unit
Test conditions
*2
V
—
Internal reference voltage input channel
*3
MHz
µs
—
—
PCLKD (ADCLK) frequency
*4
5.0
—
—
Sampling time
Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 1.8 V.
Note 2. The 12-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 12-bit A/D
converter.
Note 3. When the internal reference voltage is selected as the high-potential reference voltage.
Note 4. When the internal reference voltage is converted.
0xFFF
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
Offset error
0x000
0
Analog input voltage
VREFH0
(full-scale)
Figure 2.39
Illustration of 12-bit A/D converter characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
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RA2L1 Datasheet
2. Electrical Characteristics
input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion result
is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical A/D conversion
characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors
are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and
the width of the actual output code.
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
2.5
DAC12 Characteristics
Table 2.44
12-bit D/A conversion characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Reference voltage = AVCC0 or AVSS0 selected
Parameter
Min
—
Typ
—
Max
Unit
bit
Test conditions
Resolution
12
—
—
—
—
—
—
—
—
—
—
Resistive load
30
—
—
—
kΩ
pF
Capacitive load
—
50
Output voltage range
DNL differential nonlinearity error
INL integral nonlinearity error
Offset error
0.35
—
—
AVCC0-0.47
V
±0.5
±2.0
—
±2.0
±8.0
±30
±30
—
LSB
LSB
mV
mV
Ω
—
—
Full-scale error
—
—
Output impedance
Conversion time
—
5
—
—
30
µs
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2. Electrical Characteristics
Gain error
Full-scale error
Upper output limit
Integral nonlinearity error (INL)
Offset error
1-LSB width for ideal D/A conversion
characteristic
Output analog voltage
Ideal output voltage
Differential nonlinearity error
(DNL)
*1
Lower output limit
Actual D/A conversion characteristic
Offset error
Ideal output voltage
0x000
0xFFF
D/A converter input code
Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed.
Figure 2.40
Illustration of D/A converter characteristic terms
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion
characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion
characteristics and the width of the actual output voltage.
Offset error
Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal
output voltage based on the input code.
Full-scale error
Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal
output voltage based on the input code.
2.6
TSN Characteristics
Table 2.45
TSN characteristics (1 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
—
Typ
Max
—
Unit
°C
Test conditions
2.4 V or above
Below 2.4 V
Relative accuracy
—
± 1.5
± 2.0
—
—
°C
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RA2L1 Datasheet
2. Electrical Characteristics
Table 2.45
TSN characteristics (2 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
—
—
—
5
Typ
-3.3
1.05
—
Max
—
Unit
mV/°C
V
Test conditions
Temperature slope
Output voltage (at 25°C)
Temperature sensor start time
Sampling time
—
—
—
—
VCC = 3.3 V
—
t
5
µs
START
—
—
—
µs
2.7
OSC Stop Detect Characteristics
Table 2.46
Parameter
Oscillation stop detection circuit characteristics
Symbol
Min
Typ
Max
Unit
ms
Test conditions
Detection time
t
—
—
1
Figure 2.41
dr
Main clock
tdr
OSTDSR.OSTDF
MOCO clock
ICLK
Figure 2.41
Oscillation stop detection timing
2.8
POR and LVD Characteristics
Table 2.47
Power-on reset circuit and voltage detection circuit characteristics (1) (1 of 2)
Parameter
Symbol
Min
Typ
Max
1.55
1.54
4.06
4.00
3.01
2.96
2.70
2.64
2.07
2.02
1.88
1.82
Unit
Test Conditions
Figure 2.42
Voltage detection
Power-on reset
(POR)
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
V
V
V
1.47
1.46
3.74
3.68
2.73
2.68
2.44
2.38
1.83
1.78
1.66
1.60
1.51
1.50
3.91
3.85
2.9
V
POR
*1
level
Figure 2.43
PDR
Voltage detection
V
Figure 2.44
At falling edge
VCC
det0_0
*2
circuit (LVD0)
V
det0_1
V
det0_2
V
det0_3
V
det0_4
2.85
2.59
2.53
1.95
1.90
1.75
1.69
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RA2L1 Datasheet
2. Electrical Characteristics
Table 2.47
Power-on reset circuit and voltage detection circuit characteristics (1) (2 of 2)
Parameter
Symbol
Min
Typ
Max
4.55
4.45
4.39
4.30
4.29
4.18
4.06
4.00
3.29
3.22
3.17
3.11
3.08
3.01
2.96
2.90
2.85
2.78
2.75
2.68
2.63
2.58
2.36
2.30
2.09
2.05
1.99
1.95
1.88
1.84
1.78
1.73
4.57
4.48
4.42
4.34
4.28
4.20
4.08
4.01
Unit
Test Conditions
Voltage detection
Voltage detection
circuit (LVD1)
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
When power supply rise
When power supply fall
V
det1_0
V
det1_1
V
det1_2
V
det1_3
V
det1_4
V
det1_5
V
det1_6
V
det1_7
V
det1_8
V
det1_9
V
det1_A
V
det1_B
V
det1_C
V
det1_D
V
det1_E
V
det1_F
V
det2_0
V
det2_1
V
det2_2
V
det2_3
4.23
4.13
4.07
3.98
3.97
3.86
3.74
3.68
3.05
2.98
2.95
2.89
2.86
2.79
2.74
2.68
2.63
2.58
2.54
2.48
2.43
2.38
2.16
2.10
1.88
1.84
1.78
1.74
1.67
1.63
1.65
1.60
4.20
4.11
4.05
3.97
3.91
3.83
3.71
3.64
4.39
4.29
4.25
4.16
4.14
4.03
3.92
3.86
3.17
3.10
3.06
3.00
2.97
2.90
2.85
2.79
2.75
2.68
2.64
2.58
2.53
2.48
2.26
2.20
2
V
Figure 2.45
At falling edge
VCC
*1
*3
level
Voltage detection
Voltage detection
V
Figure 2.45
At falling edge
VCC
*1
*3
level
circuit (LVD1)
1.96
1.9
1.86
1.79
1.75
1.7
1.65
4.40
4.31
4.25
4.17
4.11
4.03
3.91
3.84
Voltage detection
Voltage detection
V
Figure 2.46
At falling edge
VCC
*1
*4
level
circuit (LVD2)
Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection
level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage detection.
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2. Electrical Characteristics
Note 2. # in the symbol V
Note 3. # in the symbol V
Note 4. # in the symbol V
denotes the value of the OFS1.VDSEL1[2:0] bits.
denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
det0_#
det1_#
det2_#
Table 2.48
Power-on reset circuit and voltage detection circuit characteristics (2)
Parameter
Symbol
Min
—
Typ
4.3
3.7
1.4
0.7
Max
—
Unit
ms
ms
ms
ms
Test Conditions
Wait time after power-on LVD0: enable
reset cancellation
t
t
t
t
t
t
t
t
t
—
—
—
—
POR
LVD0: disable
—
—
POR
*1
Wait time after voltage
monitor 0, 1, 2 reset
cancellation
—
—
LVD0: enable
LVD0,1,2
LVD1,2
*2
—
—
LVD0: disable
*3
—
—
—
—
—
—
500
500
350
600
—
µs
µs
µs
µs
µs
Figure 2.42, Figure 2.43
Figure 2.44
Power-on reset response delay time
det
*3
—
LVD0 response delay time
det
*3
—
Figure 2.45
LVD1 response delay time
det
*3
—
Figure 2.46
LVD2 response delay time
det
Minimum VCC down time
Power-on reset enable time
500
Figure 2.42, VCC = 1.0 V or
above
VOFF
t
1
—
—
—
—
ms
µs
µs
Figure 2.43, VCC = below 1.0
V
W (POR)
LVD1 operation stabilization time (after LVD1 is
enabled)
T
T
—
—
300
1200
Figure 2.45
d (E-A)
d (E-A)
LVD2 operation stabilization time (after LVD2 is
enabled)
Figure 2.46
Hysteresis width (POR)
V
V
—
—
—
—
—
—
—
10
60
110
70
60
50
90
—
—
—
—
—
—
—
mV
mV
—
PORH
Hysteresis width (LVD0, LVD1 and LVD2)
LVD0 selected
LVH
V
det1_0
V
det1_3
V
det1_A
V
det1_C
to V
to V
to V
selected
selected
selected
selected
det1_2
det1_9
det1_B
to V
det1_F
LVD2 selected
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V
, V
POR
,
det0
V
, and V
det1
for the POR/LVD.
det2
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2. Electrical Characteristics
tVOFF
VCC
VPOR
1.0 V
Internal reset signal
(active-low)
tdet
tdet tPOR
Figure 2.42
Voltage detection reset timing
VPOR
VCC
1.0 V
tw(POR)
*1
Internal reset signal
(active-low)
tdet tPOR
Note 1.
t
is the time required for a power-on reset to be enabled while the external power VCC is being held below the
w(POR)
valid voltage (1.0 V).
When VCC turns on, maintain t
for 1.0 ms or more.
w(POR)
Figure 2.43
Power-on reset timing
tVOFF
VLVH
VCC
Vdet0
Internal reset signal
(active-low)
tdet
tdet
tLVD0
Figure 2.44
Voltage detection circuit timing (Vdet0)
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2. Electrical Characteristics
tVOFF
VLVH
VCC
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tLVD1
tdet
When LVD1CR0.RN = 1
tLVD1
Figure 2.45
Voltage detection circuit timing (Vdet1)
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2. Electrical Characteristics
tVOFF
VLVH
VCC
Vdet2
LVCMPCR.LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.46
Voltage detection circuit timing (Vdet2
)
2.9
CTSU Characteristics
Table 2.49
CTSU characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
10
Max
11
Unit
Test conditions
External capacitance connected to TSCAP pin
C
tscap
9
nF
—
2.10
Comparator Characteristics
Table 2.50
ACMPLP characteristics (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Min
0
Typ
—
Max
Unit
Test conditions
Reference voltage range
Input voltage range
V
V
VCC-1.4
VCC
V
V
V
—
REF
I
0
—
—
*1
—
1.34
1.44
1.54
—
Internal reference voltage
Output delay time
High-speed mode
Low-speed mode
Window mode
T
d
—
—
—
—
—
—
1.2
9
µs
µs
µs
VCC = 3.0 V
2
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RA2L1 Datasheet
2. Electrical Characteristics
Table 2.50
ACMPLP characteristics (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Min
—
Typ
Max
50
40
60
—
Unit
Test conditions
Offset voltage
High-speed mode
Low-speed mode
Window mode
—
—
—
—
mV
mV
mV
V
—
—
—
—
—
—
—
—
—
—
Internal reference voltage for window mode
V
V
—
0.76 × VCC
RFH
RFL
cmp
—
0.24 × VCC
—
V
Operation
stabilization wait
time
High-speed mode
Low-speed mode
T
100
200
—
—
—
µs
—
Note 1. The internal reference voltage can be selected as ACMPLP reference voltage only when 2.94 V ≤ VCC ≤ 5.50 V.
Output voltage
Td
Td
+100 mV
Reference voltage
-100 mV
Input voltage
Figure 2.47
Output delay time
2.11
Flash Memory Characteristics
2.11.1
Code Flash Memory Characteristics
Table 2.51
Code flash characteristics (1)
Parameter
Symbol
Min
Typ
—
Max
—
Unit
Conditions
*1
N
PEC
1000
Times
Year
—
Reprogramming/erasure cycle
*2 *3
Data hold time After 1000 times N
t
—
—
T = +85°C
a
20
PEC
DRP
T = +105°C
a
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000),
erasing can be performed n times for each block. For instance, when 4-byte programming is performed 512 times for different
addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address for several times as one erasure is not enabled (overwriting is prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. This result is target spec, may changed after reliability testing.
Table 2.52
Code flash characteristics (2) (1 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 1 MHz
ICLK = 48 MHz
Parameter
Symbol Min
Typ
86
Max
732
355
Min
—
Typ
34
Max
Unit
µs
Programming time
Erasure time
4-byte
2-KB
t
P4
—
—
321
215
t
12.5
—
5.6
ms
E2K
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RA2L1 Datasheet
2. Electrical Characteristics
Table 2.52
Code flash characteristics (2) (2 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 1 MHz
ICLK = 48 MHz
Parameter
Symbol Min
Typ
—
Max
46.5
3681
22.3
570
Min
—
Typ
—
Max
8.3
Unit
µs
Blank check time
4-byte
2-KB
t
t
t
t
—
—
—
—
BC4
—
—
—
240
10.5
423
µs
BC2K
SED
Erase suspended time
—
—
—
µs
Access window information program
Start-up area selection and security
setting time
21.2
—
11.4
ms
AWSSAS
OCD/serial programmer ID setting
time
t
—
84.7
2280
—
45.3
1690
ms
OSIS
*1
Flash memory mode transition wait
time 1
t
t
2
—
—
—
—
2
—
—
—
—
µs
µs
DIS
MS
Flash memory mode transition wait
time 2
15
15
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note:
Note 1. Total time of four commands.
Table 2.53
Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
*2
ICLK = 1 MHz
ICLK = 8 MHz
Parameter
Symbol Min
Typ
86
Max
732
Min
—
Typ
39
Max
Unit
µs
Programming time
Erasure time
4-byte
2-KB
t
t
t
t
t
t
—
—
—
—
—
—
356
227
11.3
534
11.7
435
P4
12.5
—
355
—
6.2
—
ms
µs
E2K
Blank check time
4-byte
2-KB
46.5
3681
22.3
570
—
BC4
—
—
—
µs
BC2K
SED
Erase suspended time
—
—
—
µs
Access window information program
Start-up area selection and security
setting time
21.2
—
12.2
ms
AWSSAS
OCD/serial programmer ID setting
time
t
—
84.7
2280
—
48.7
1740
ms
OSIS
*1
Flash memory mode transition wait
time 1
t
t
2
—
—
—
—
2
—
—
—
—
µs
µs
DIS
MS
Flash memory mode transition wait
time 2
15
15
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note:
Note 1. Total time of four commands.
Note 2. When 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V
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2. Electrical Characteristics
Table 2.54
Code flash characteristics (4)
Low-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
ICLK = 1 MHz
ICLK = 2 MHz
Parameter
Symbol Min
Typ
86
Max
732
Min
—
Typ
57
Max
502
Unit
µs
Programming time
Erasure time
4-byte
2-KB
t
t
t
t
t
t
—
—
—
—
—
—
P4
12.5
—
355
—
8.8
—
280
ms
µs
E2K
Blank check time
4-byte
2-KB
46.5
3681
22.3
570
—
23.3
1841
16.2
491
BC4
—
—
—
µs
BC2K
SED
Erase suspended time
—
—
—
µs
Access window information program
Start-up area selection and security
setting time
21.2
—
15.9
ms
AWSSAS
OCD/serial programmer ID setting
time
t
—
84.7
2280
—
63.5
1964
ms
OSIS
*1
Flash memory mode transition wait
time 1
t
t
2
—
—
—
—
2
—
—
—
—
µs
µs
DIS
MS
Flash memory mode transition wait
time 2
15
15
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz or 2 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note:
Note 1. Total time of four commands.
2.11.2
Data Flash Memory Characteristics
Table 2.55
Parameter
Data flash characteristics (1)
Symbol
Min
Typ
Max
—
Unit
Times
Year
Year
Year
Conditions
*1
N
DPEC
100000
1000000
—
—
Reprogramming/erasure cycle
Data hold time
*2 *3
After 10000 times of N
t
—
Ta = +85°C
Ta = +105°C
20
DPEC
DDRP
*2 *3
After 100000 times of N
—
—
5
DPEC
*2 *3
After 1000000 times of N
—
—
Ta = +25°C
1
DPEC
Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different
addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.)
Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. These results are target spec, may changed after reliability testing.
Table 2.56
Data flash characteristics (2) (1 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 4 MHz
ICLK = 48 MHz
Parameter
Symbol
Min
—
Typ
45
8.8
—
Max
404
Min
—
Typ
34
6.1
—
Max
Unit
µs
Programming time
Erasure time
1-byte
1-KB
t
t
t
t
t
321
224
8.3
DP1
—
280
—
ms
µs
DE1K
DBC1
DBC1K
DSED
Blank check time
1-byte
1-KB
—
15.2
1832
13.2
—
—
—
—
—
466
10.5
µs
Suspended time during erasing
—
—
—
—
µs
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 78 of 110
RA2L1 Datasheet
2. Electrical Characteristics
Table 2.56
Data flash characteristics (2) (2 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 4 MHz
ICLK = 48 MHz
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Data flash STOP recovery time
t
250
—
—
250
—
—
ns
DSTOP
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note:
Table 2.57
Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
*1
ICLK = 4 MHz
ICLK = 8 MHz
Parameter
Symbol
Min
—
Typ
45
8.8
—
Max
404
280
15.2
1.84
13.2
—
Min
—
Typ
39
7.3
—
Max
Unit
µs
Programming time
Erasure time
1-byte
1-KB
t
t
t
t
t
t
356
248
11.3
1.06
11.7
—
DP1
—
—
ms
µs
DE1K
DBC1
DBC1K
DSED
DSTOP
Blank check time
1-byte
1-KB
—
—
—
—
—
—
ms
µs
Suspended time during erasing
Data flash STOP recovery time
—
—
—
—
250
—
250
—
ns
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note:
Note 1. When 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V
Table 2.58
Data flash characteristics (4)
Low-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
ICLK = 1 MHz
ICLK = 2 MHz
Parameter
Symbol
Min
—
Typ
86
Max
732
504
46.5
7.3
Min
—
Typ
57
Max
502
354
23.3
3.66
16.2
—
Unit
µs
Programming time
Erasure time
1-byte
1-KB
t
t
t
t
t
t
DP1
—
19.7
—
—
12.4
—
ms
µs
DE1K
DBC1
DBC1K
DSED
DSTOP
Blank check time
1-byte
1-KB
—
—
—
—
—
—
ms
µs
Suspended time during erasing
Data flash STOP recovery time
—
—
22.3
—
—
—
250
—
250
—
ns
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 2 MHz, the
frequency can be set to 1 MHz or 2 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note:
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 79 of 110
RA2L1 Datasheet
2. Electrical Characteristics
2.11.3
Serial Wire Debug (SWD)
Table 2.59
SWD characteristics (1)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter
Symbol
Min
80
35
35
—
—
16
16
2
Typ
—
—
—
—
—
—
—
—
Max
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions
SWCLK clock cycle time
SWCLK clock high pulse width
SWCLK clock low pulse width
SWCLK clock rise time
SWCLK clock fall time
SWDIO setup time
t
t
t
t
t
t
t
t
Figure 2.48
SWCKcyc
SWCKH
SWCKL
SWCKr
SWCKf
SWDS
5
—
—
70
Figure 2.49
SWDIO hold time
SWDH
SWDIO data delay time
SWDD
Table 2.60
SWD characteristics (2)
Conditions: VCC = AVCC0 = 1.6 to 2.4 V
Parameter
Symbol
Min
250
120
120
—
Typ
—
—
—
—
—
—
—
—
Max
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions
SWCLK clock cycle time
SWCLK clock high pulse width
SWCLK clock low pulse width
SWCLK clock rise time
SWCLK clock fall time
SWDIO setup time
t
t
t
t
t
t
t
t
Figure 2.48
SWCKcyc
SWCKH
SWCKL
SWCKr
SWCKf
SWDS
—
5
50
—
—
170
Figure 2.49
SWDIO hold time
50
SWDH
SWDIO data delay time
2
SWDD
tSWCKcyc
tSWCKH
tSWCKf
SWCLK
tSWCKr
tSWCKL
Figure 2.48
SWD SWCLK timing
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 80 of 110
RA2L1 Datasheet
2. Electrical Characteristics
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
tSWDD
tSWDD
SWDIO
(Output)
SWDIO
(Output)
SWDIO
(Output)
Figure 2.49
SWD input/output timing
2.12
DCDC Characteristics
Table 2.61
DCDC characteristics
Conditions: VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
1.50
—
Max
Unit
V
Test conditions
DCDC output Voltage
Power switching stabilization time
—
—
1.42
—
1.58
22
—
µs
Switch from LDO power to DCDC
power
—
—
—
—
—
—
60
60
µs
µs
Switch from DCDC power to LDO
power
Switch from DCDC power to LDO
power in the LC boost mode
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 81 of 110
RA2L1 Datasheet
Appendix 1. Port States in each Processing Mode
Appendix 1.
Port States in each Processing Mode
Table 1.1
Port name
Port states in each processing mode (1 of 4)
Reset
Hi-Z
Software Standby Mode
*1
P000/AN000/TS21/IRQ6
P001/AN001/TS22/IRQ7
P002/AN002/TS23/IRQ2
Keep-O
*1
Hi-Z
Keep-O
*1
Hi-Z
Keep-O
P003/AN003/TS24
Hi-Z
Hi-Z
Keep-O
*1
P004/AN004/TS25/IRQ3
Keep-O
P005/AN011
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
P006/AN012
P007/AN013
P008/AN014
P010/AN005/TS30-CFC
P011/AN006/TS31-CFC
P012/AN007/TS32-CFC
P013/AN008/TS33-CFC
P014/AN009/DA0
[DA0 output (DACE0 = 1)]
DA0 output retained
[Other than the above (DACE0 = 0)]
Keep-O
*1
P015/AN010/TS28-CFC/IRQ7_A
Hi-Z
Hi-Z
Keep-O
P100/CMPIN0/TS26-CFC/AGTIO0_A/GTETRGA_A/GTIOC5B_A/RXD0_A/
MISO0_A/SCL0_A/SCK1_A/SCL1_B/MISOA_A/KRM00/IRQ2_A
[AGTIO0_A output selected]
AGTIO0_A output
*2
[Other than the above]
*1
Keep-O
*1
P101/CMPREF0/TS16-CFC/AGTEE0/GTETRGB_A/GTIOC5A_A/TXD0_A/
MOSI0_A/SDA0_A/CTS1_RTS1_A/SDA1_B/MOSIA_A/KRM01/IRQ1_A
Hi-Z
Hi-Z
Keep-O
P102/CMPIN1/ADTRG0_A/TS15-CFC/AGTO0/GTOWLO_A/GTIOC2B_A/
CRX0_C /SCK0_A/TXD2_D/MOSI2_D/SDA2_D/RSPCKA_A/KRM02
[AGTO0 selected]
AGTO0 output
*2
[Other than the above]
*1
Keep-O
*1
P103/CMPREF1/TS14-CFC/GTOWUP_A/GTIOC2A_A/CTX0_C/
CTS0_RTS0_A/SSLA0_A/KRM03
Hi-Z
Hi-Z
Keep-O
*1
P104/TS13-CFC/GTETRGB_B/GTIOC1B_C/RXD0_C/MISO0_C/SCL0_C/
SSLA1_A/KRM04/IRQ1_B
Keep-O
*1
P105/TS34-CFC/GTETRGA_C/GTIOC1A_C/SSLA2_A/KRM05/IRQ0_B
P106/GTIOC8B_A/SSLA3_A/KRM06
Hi-Z
Hi-Z
Hi-Z
Keep-O
*1
Keep-O
*1
P107/GTIOC8A_A/KRM07
Keep-O
P108/SWDIO/GTOULO_C/GTIOC0B_A/CTS9_RTS9_B/SSLB0_B
Pull-up
Hi-Z
Keep-O
P109/TS10-CFC/GTOVUP_A/GTIOC1A_A/CTX0_A//SCK1_E/TXD9_B/
MOSI9_B/SDA9_B/MOSIB_B/CLKOUT_B
[CLKOUT selected]
CLKOUT output
[Other than the above]
Keep-O
P110/TS11-CFC/GTOVLO_A/GTIOC1B_A/CRX0_A/CTS2_RTS2_B/RXD9_B/ Hi-Z
MISO9_B/SCL9_B/MISOB_B/IRQ3_A/VCOUT
[ACMPLP selected]
VCOUT output
[Other than the above]
*1
Keep-O
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 82 of 110
RA2L1 Datasheet
Appendix 1. Port States in each Processing Mode
Table 1.1
Port name
Port states in each processing mode (2 of 4)
Reset
Software Standby Mode
P111/TS12-CFC/AGTOA0/GTIOC3A_A/SCK2_B/SCK9_B/RSPCKB_B/
IRQ4_A
Hi-Z
[AGTOA0 selected]
AGTOA0 output
*2
[Other than the above]
*1
Keep-O
P112/TSCAP_C/AGTOB0/GTIOC3B_A/TXD2_B/MOSI2_B/SDA2_B/SCK1_D/ Hi-Z
SSLB0_C
[AGTOB0 selected]
AGTOB0 output
*2
[Other than the above]
Keep-O
P113/TS27-CFC/GTIOC2A_C
P114/TS29-CFC/GTIOC2B_C
P115/TS35-CFC/GTIOC4A_C
P200/NMI
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pull-up
Hi-Z
Hi-Z
Hi-Z
Keep-O
Keep-O
Keep-O
Hi-Z
P201/MD
Keep-O
P202/SCK2_A/RXD9_A/MISO9_A/SCL9_A/MISOB_A
P203/CTS2_RTS2_A/TXD9_A/MOSI9_A/SDA9_A/MOSIB_A
Keep-O
Keep-O
P204/CACREF_A/TS0/AGTIO1_A/GTIW_A/GTIOC4B_B/SCK0_D/SCK9_A/
SCL0_B/RSPCKB_A
[AGTIO1_A output selected]
AGTIO1_A output
*2
[Other than the above]
*1
Keep-O
P205/AGTO1/GTIV_A/GTIOC4A_B/TXD0_D/MOSI0_D/SDA0_D/
CTS9_RTS9_A/ SCL1_A/SSLB0_A/IRQ1/CLKOUT_A
Hi-Z
[AGTO1 selected]
AGTO1 output
*2
[CLKOUT selected]
CLKOUT output
[Other than the above]
*1
Keep-O
*1
P206/GTIU_A/RXD0_D/MISO0_D/SCL0_D/SDA1_A/SSLB1_A/IRQ0
Hi-Z
Keep-O
P207
Hi-Z
Hi-Z
Keep-O
P208/AGTOB0_A
[AGTOB0_A selected]
AGTOB0_A output
*2
[Other than the above]
Keep-O
*1
P212/EXTAL /AGTEE1/GTETRGB_D/GTIOC0B_D/RXD1_A/MISO1_A/
SCL1_A/IRQ3_B
Hi-Z
Keep-O
*1
P213/XTAL /GTETRGA_D/GTIOC0A_D/TXD1_A/MOSI1_A/SDA1_A/IRQ2_B Hi-Z
Keep-O
P214/XCOUT, P215/XCIN
Hi-Z
[Sub-clock Oscillator selected]
Sub-clock Oscillator is operating
[Other than the above]
Hi-Z
P300/SWCLK/GTOUUP_C/GTIOC0A_A/SSLB1_B
Pull-up
Hi-Z
Keep-O
P301/TS9-CFC/AGTIO0_D/GTOULO_A/GTIOC4B_A/RXD2_A/MISO2_A/
SCL2_A/CTS9_RTS9_D/SSLB2_B/IRQ6_A
[AGTIO0_D output selected]
AGTIO0_D output
*2
[Other than the above]
*1
Keep-O
*1
P302/TS8-CFC/GTOUUP_A/GTIOC4A_A/TXD2_A/MOSI2_A/SDA2_A/
SSLB3_B/IRQ5_A
Hi-Z
Keep-O
P303/TS2-CFC/GTIOC7B_A
P304/GTIOC7A_A
Hi-Z
Hi-Z
Hi-Z
Keep-O
Keep-O
Keep-O
P305, P306, P307
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 83 of 110
RA2L1 Datasheet
Appendix 1. Port States in each Processing Mode
Table 1.1
Port name
Port states in each processing mode (3 of 4)
Reset
Software Standby Mode
P400/CACREF_C/AGTIO1_C/GTIOC6A_A/SCK0_B/SCK1_B/SCL0_A/
IRQ0_A
Hi-Z
[AGTIO1_C output selected]
AGTIO1_C output
*2
[Other than the above]
*1
Keep-O
*1
P401/GTETRGA_B/GTIOC6B_A/CTX0_B/CTS0_RTS0_B/TXD1_B/MOSI1_B/ Hi-Z
SDA1_B/SDA0_A/IRQ5
Keep-O
P402/TS18/AGTIO0_E/AGTIO1_D/CRX0_B/RXD1_B/MISO1_B/SCL1_B/
IRQ4
Hi-Z
[AGTIO0_E, AGTIO1_D output
selected]
*2
AGTIO0_E, AGTIO1_D output
[Other than the above]
*1
Keep-O
P403/TS17/AGTIO0_F/AGTIO1_E/GTIOC3A_B/CTS1_RTS1_B
Hi-Z
[AGTIO0_F, AGTIO1_E output
selected]
*2
AGTIO0_F, AGTIO1_E output
[Other than the above]
Keep-O
*1
P404/GTIOC3B_B,
P405/GTIOC1A_B,
P406/GTIOC1B_B
Hi-Z
Hi-Z
Keep-O
P407/ADTRG0_B/AGTIO0_C/RTCOUT/CTS0_RTS0_D/SDA0_B/SSLB3_A
[AGTIO0_C output selected]
AGTIO0_C output
*2
[RTCOUT selected]
RTCOUT output
[Other than the above]
*1
Keep-O
*1
P408/TS4/GTOWLO_B/GTIOC5B_B/CTS1_RTS1_D/RXD3_A/MISO3_A/
SCL3_A/SCL0_C/IRQ7_B
Hi-Z
Keep-O
*1
P409/TS5/GTOWUP_B/GTIOC5A_B/TXD3_A/MOSI3_A/SDA3_A/IRQ6_B
Hi-Z
Hi-Z
Keep-O
P410/TS6/AGTOB1/GTOVLO_B/GTIOC9B_A/RXD0_B/MISO0_B/SCL0_B/
SCK3_A/MISOA_B/IRQ5_B
[AGTOB1 selected]
AGTOB1 output
*2
[Other than the above]
*1
Keep-O
P411/TS7/AGTOA1/GTOVUP_B/GTIOC9A_A/TXD0_B/MOSI0_B/SDA0_B/
CTS3_RTS3_A/MOSIA_B/IRQ4_B
Hi-Z
[AGTOA1 selected]
AGTOA1 output
*2
[Other than the above]
*1
Keep-O
P412/GTOULO_B/SCK0_E/RSPCKA_B
P413/GTOUUP_B/CTS0_RTS0_E/SSLA0_B
P414/GTIOC0B_C/SSLA1_B
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
Keep-O
P415/GTIOC0A_C/SSLA2_B
P500/GTIU_B/GTIOC2A_B
P501/AN017/GTIV_B/GTIOC2B_B/TXD1_C/MOSI1_C/SDA1_C
P502/AN018/GTIW_B/GTIOC3B_C/RXD1_C/MISO1_C/SCL1_C
P503/AN019/GTETRGA_E/SCK1_C
P504/AN020/GTETRGB_E/CTS1_RTS1_C
P505
P600/GTIOC6B_C/SCK9_C
P601/GTIOC6A_C/RXD9_C/MISO9_C/SCL9_C
P602/GTIOC7B_B/TXD9_C/MOSI9_C/SDA9_C
P603/GTIOC7A_B/CTS9_RTS9_C
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 84 of 110
RA2L1 Datasheet
Appendix 1. Port States in each Processing Mode
Table 1.1
Port states in each processing mode (4 of 4)
Port name
Reset
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Software Standby Mode
Keep-O
P608/GTIOC4B_C
P609/GTIOC5A_C
P610/GTIOC5B_C
P708/RXD1_D/MISO1_D/SCL1_D/SSLA3_B
P714
Keep-O
Keep-O
Keep-O
Keep-O
P808, P809
Keep-O
Note:
Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins become high-impedance.
Note 1. Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin.
Note 2. AGTIO output is enabled while LOCO or SOSC is selected as a count source.
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 85 of 110
RA2L1 Datasheet
Appendix 2. Package Dimensions
Appendix 2.
Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
RENESAS Code
Previous Code
MASS (Typ) [g]
JEITA Package Code
0.6
P-LFQFP100-14x14-0.50
PLQP0100KB-B
—
HD
Unit: mm
*1
D
75
51
76
50
100
26
1
25
NOTE 4
NOTE)
Index area
NOTE 3
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
F
S
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Dimensions in millimeters
Min Nom Max
Reference
Symbol
y
S
*3
b
p
e
M
D
E
13.9
13.9
14.0 14.1
14.0 14.1
A2
HD
HE
A
1.4
15.8
15.8
16.0 16.2
16.0 16.2
1.7
A1
bp
c
0.05
0.15
0.09
0
0.15
0.20 0.27
3.5
0.5
0.20
8
Lp
L1
e
Detail F
x
0.08
0.08
0.75
y
Lp
L1
0.45
0.6
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.1
LQFP 100-pin
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 86 of 110
RA2L1 Datasheet
Appendix 2. Package Dimensions
RENESAS Code
Previous Code
MASS (Typ) [g]
JEITA Package Code
P-LFQFP80-12x12-0.50
0.5
PLQP0080KB-B
—
HD
Unit: mm
*1
D
60
41
61
40
21
80
1
20
NOTE)
NOTE 4
Index area
NOTE 3
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
F
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Dimensions in millimeters
Reference
S
Symbol
Min Nom Max
D
E
11.9
11.9
12.0 12.1
12.0 12.1
y
S
A2
HD
HE
A
1.4
*3
13.8
13.8
14.0 14.2
14.0 14.2
b
p
e
M
1.7
A1
bp
c
0.05
0.15
0.09
0
0.15
0.20 0.27
3.5
0.5
0.20
8
e
x
0.08
0.08
0.75
y
Lp
L1
Lp
L1
0.45
0.6
1.0
Detail F
© 2017 Renesas Electronics Corporation. All rights reserved.
Figure 2.2
LQFP 80-pin
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 87 of 110
RA2L1 Datasheet
Appendix 2. Package Dimensions
RENESAS Code
Previous Code
MASS (Typ) [g]
JEITA Package Code
P-LFQFP64-10x10-0.50
0.3
PLQP0064KB-C
—
Unit: mm
HD
*1
D
48
33
49
32
64
17
1
16
NOTE 4
Index area
NOTE 3
NOTE)
F
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
S
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
y
S
*3
Dimensions in millimeters
Min Nom Max
Reference
Symbol
b
p
e
M
D
E
9.9
9.9
10.0 10.1
10.0 10.1
A2
HD
HE
A
1.4
11.8
11.8
12.0 12.2
12.0 12.2
1.7
A1
bp
c
0.05
0.15
0.09
0
0.15
0.20 0.27
3.5
0.5
0.20
8
Lp
L1
e
Detail F
x
0.08
0.08
0.75
y
Lp
L1
0.45
0.6
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.3
LQFP 64-pin
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 88 of 110
RA2L1 Datasheet
Appendix 2. Package Dimensions
RENESAS Code
Previous Code
MASS (Typ) [g]
JEITA Package Code
0.2
P-LFQFP48-7x7-0.50
PLQP0048KB-B
—
HD
D
Unit: mm
*1
36
25
37
24
48
13
1
12
NOTE 4
Index area
NOTE 3
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
F
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
S
Dimensions in millimeters
Min Nom Max
Reference
Symbol
D
E
6.9
6.9
7.0
7.0
1.4
9.0
9.0
7.1
7.1
y
S
*3
b
e
p
M
A2
HD
HE
A
8.8
8.8
9.2
9.2
1.7
0.15
A1
bp
c
0.05
0.17
0.09
0
0.20 0.27
3.5
0.5
0.20
8
Lp
L1
e
x
0.08
0.08
0.75
Detail F
y
Lp
L1
0.45
0.6
1.0
Figure 2.4
LQFP 48-pin
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 89 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Appendix 3.
I/O Registers
This appendix describes I/O register addresses, access cycles, and reset values by function.
3.1
Peripheral Base Addresses
This section provides the base addresses for peripherals described in this manual.
Table 3.1 shows the name, description, and the base address of each peripheral.
Table 3.1
Name
MPU
Peripheral base address (1 of 2)
Description
Base address
Memory Protection Unit
0x4000_0000
0x4000_2000
0x4000_3000
0x4000_5400
0x4000_6000
0x4001_B000
0x4001_E000
0x4004_0000
0x4004_0020
0x4004_0040
0x4004_0060
0x4004_0080
0x4004_00A0
0x4004_00C0
0x4004_00E0
0x4004_0100
0x4004_0800
0x4004_1000
0x4004_2000
0x4004_4000
0x4004_4200
0x4004_4400
0x4004_4600
0x4004_7000
0x4005_0000
0x4005_3000
0x4005_3014
0x4005_3100
0x4005_4100
0x4005_C000
0x4005_E000
0x4007_0000
0x4007_0020
0x4007_0040
0x4007_0060
SRAM
BUS
SRAM Control
BUS Control
DTC
Data Transfer Controller
Interrupt Controller
ICU
DBG
Debug Function
SYSC
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PFS
System Control
Port 0 Control Registers
Port 1 Control Registers
Port 2 Control Registers
Port 3 Control Registers
Port 4 Control Registers
Port 5 Control Registers
Port 6 Control Registers
Port 7 Control Registers
Port 8 Control Registers
Pmn Pin Function Control Register
Event Link Controller
ELC
POEG
RTC
Port Output Enable Module for GPT
Realtime Clock
WDT
Watchdog Timer
IWDT
CAC
Independent Watchdog Timer
Clock Frequency Accuracy Measurement Circuit
Module Stop Control B, C, D
CAN0 Module
MSTP
CAN0
IIC0
Inter-Integrated Circuit 0
Inter-Integrated Circuit 0 Wakeup Unit
Inter-Integrated Circuit 1
Data Operation Circuit
IIC0WU
IIC1
DOC
ADC12
DAC12
SCI0
12-bit A/D Converter
12-bit D/A Converter
Serial Communication Interface 0
Serial Communication Interface 1
Serial Communication Interface 2
Serial Communication Interface 3
SCI1
SCI2
SCI3
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 90 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.1
Name
Peripheral base address (2 of 2)
Description
Base address
SCI9
Serial Communication Interface 9
Serial Peripheral Interface 0
Serial Peripheral Interface 1
CRC Calculator
0x4007_0120
0x4007_2000
0x4007_2100
0x4007_4000
0x4007_8000
0x4007_8100
0x4007_8200
0x4007_8300
0x4007_8400
0x4007_8500
0x4007_8600
0x4007_8700
0x4007_8800
0x4007_8900
0x4007_8FF0
0x4008_0000
0x4008_2000
0x4008_4000
0x4008_4100
0x4008_5E00
0x407E_C000
SPI0
SPI1
CRC
GPT320
GPT321
GPT322
GPT323
GPT164
GPT165
GPT166
GPT167
GPT168
GPT169
GPT_OPS
KINT
General PWM Timer 0 (32-bit)
General PWM Timer 1 (32-bit)
General PWM Timer 2 (32-bit)
General PWM Timer 3 (32-bit)
General PWM Timer 4 (16-bit)
General PWM Timer 5 (16-bit)
General PWM Timer 6 (16-bit)
General PWM Timer 7 (16-bit)
General PWM Timer 8 (16-bit)
General PWM Timer 9 (16-bit)
Output Phase Switching Controller
Key Interrupt Function
CTSU
Capacitive Sensing Unit 2
AGT0
Low Power Asynchronous General Purpose Timer 0
Low Power Asynchronous General Purpose Timer 1
Low-Power Analog Comparator
Flash I/O Registers
AGT1
ACMPLP
FLCN
Note:
Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral
3.2
Access Cycles
This section provides access cycle information for the I/O registers described in this manual.
The following information applies to Table 3.2:
● Registers are grouped by associated module.
● The number of access cycles indicates the number of cycles based on the specified reference clock.
● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations
cannot be guaranteed.
● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization
cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio
between ICLK and PCLK.
● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always
constant.
● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.
Note:
This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the
external memory or bus access from other bus master such as DTC.
Table 3.2 shows the register access cycles for non-GPT modules.
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 91 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.2
Access cycles for non-GPT modules
Number of access cycles
*1
Address
From
ICLK = PCLK
Read Write
ICLK > PCLK
Cycle
unit
Peripherals
To
Read Write
Related function
MPU, SRAM, BUS,
DTC, ICU, DBG
0x4000_2000 0x4001_BFFF
0x4001_E000 0x4001_E6FF
0x4004_0000 0x4004_7FFF
3
4
ICLK
Memory Protection Unit, SRAM,
Buses, Data Transfer Controller,
Interrupt Controller, CPU, Flash
Memory
SYSC
ICLK
Low Power Modes, Resets, Low
Voltage Detection, Clock
Generation Circuit, Register
Write Protection
PORTn, PFS, ELC,
POEG, RTC, WDT,
IWDT, CAC, MSTP
3
3
2 to 3
PCLKB
I/O Ports, Event Link Controller,
Port Output Enable for GPT,
Realtime Clock, Watchdog Timer,
Independent Watchdog Timer,
Clock Frequency Accuracy
Measurement Circuit, Module
Stop Control
CAN0,IICn (n = 0,
1),IIC0WU, DOC,
ADC12, DAC12
0x4005_0000 0x4005_EFFF
2 to 3
PCLKB
Controller Area Network Module,
2
I C Bus Interface, Data
Operation Circuit, 12-bit A/D
Converter
*2
0x4007_0000 0x4007_0EFF
0x4007_2000 0x4007_2FFF
0x4007_4000 0x4007_4FFF
5
5
3
2 to 3
2 to 3
2 to 3
PCLKB
PCLKB
Serial Communications Interface
Serial Peripheral Interface
SCIn (n = 0 to 2, 9)
*3
SPIn (n = 0, 1)
CRC
PCLKB
PCLKB
CRC Calculator
GPT32n (n = 0 to 3), 0x4007_8000 0x4007_BFFF
See Table 3.3.
General PWM Timer
GPT16n (n = 4 to 9),
GPT_OPS
KINT, CTSU
0x4008_0000 0x4008_2FFF
0x4008_4000 0x4008_4FFF
3
3
2 to 3
PCLKB
PCLKB
Key interrupt Function,
Capacitive Sensing Unit 2
AGTn
2 to 3
Low Power Asynchronous
General Purpose Timer
ACMPLP
FLCN
0x4008_5000 0x4008_6FFF
0x407E_C000 0x407E_FFFF
3
7
2 to 3
7
PCLKB
ICLK
Low-Power Analog Comparator
Data Flash, Temperature Sensor,
Capacitive Sensing Unit 2, Flash
Control
Note 1. If the number of PCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the maximum
value is rounded up to the decimal point. For example, 1.5 to 2.5 is 1 to 3.
Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in
Table 3.2. When accessing an 8-bit register (FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in Table 3.2.
Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit
register (SPDR_HA), the access cycles are as shown in Table 3.2.
Table 3.3 shows register access cycles for GPT modules.
Table 3.3
Access cycles for GPT modules (1 of 2)
Number of access cycles
Frequency ratio between ICLK
and PCLK
Read
Write
Cycle unit
PCLKB
PCLKB
PCLKB
PCLKB
PCLKB
ICLK > PCLKD = PCLKB
ICLK > PCLKD > PCLKB
PCLKD = ICLK = PCLKB
PCLKD = ICLK > PCLKB
PCLKD > ICLK = PCLKB
5 to 6
3 to 4
6
3 to 4
2 to 3
4
2 to 3
4
1 to 2
3
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 92 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.3
Access cycles for GPT modules (2 of 2)
Number of access cycles
Frequency ratio between ICLK
and PCLK
Read
Write
Cycle unit
PCLKD > ICLK > PCLKB
2 to 3
1 to 2
PCLKB
3.3
Register Descriptions
This section provides information associated with registers described in this manual.
Table 3.4 shows a list of registers including address offsets, address sizes, access rights, and reset values.
Table 3.4
Register description (1 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xFFFF
MPU
MPU
MPU
—
—
4
—
—
—
—
MMPUCTLA
MMPUPTA
Bus Master MPU Control Register
Group A Protection of Register
0x000
0x102
0x200
16
16
16
R/W 0x0000
R/W 0x0000
R/W 0x0000
0xFFFF
0x010 0-3
0x010 0-3
0x010 0-3
MMPUACA%s
Group A Region %s access control
register
0xFFFF
MPU
4
MMPUSA%s
Group A Region %s Start Address
Register
0x204
32
R/W 0x00000000
0x00000003
MPU
MPU
MPU
MPU
4
MMPUEA%s
SMPUCTL
Group A Region %s End Address Register 0x208
Slave MPU Control Register 0xC00
Access Control Register for Memory Bus 1 0xC10
32
16
16
16
R/W 0x00000003
R/W 0x0000
R/W 0x0000
R/W 0x0000
0x00000003
0xFFFF
—
—
—
—
—
—
—
—
—
SMPUMBIU
SMPUFBIU
0xFFFF
Access Control Register for Internal
Peripheral Bus 9
0xC14
0xFFFF
MPU
MPU
—
—
—
—
—
—
SMPUSRAM0
SMPUP0BIU
Access Control Register for Memory Bus 4 0xC18
16
16
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
Access Control Register for Internal
Peripheral Bus 1
0xC20
0xC24
0xC28
0xD00
0xD04
MPU
MPU
MPU
MPU
—
—
—
—
—
—
—
—
—
—
—
—
SMPUP2BIU
SMPUP6BIU
MSPMPUOAD
MSPMPUCTL
Access Control Register for Internal
Peripheral Bus 3
16
16
16
16
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
0xFFFF
0xFEFF
Access Control Register for Internal
Peripheral Bus 7
Stack Pointer Monitor Operation After
Detection Register
Stack Pointer Monitor Access Control
Register
MPU
MPU
—
—
—
—
—
—
MSPMPUPT
MSPMPUSA
Stack Pointer Monitor Protection Register
0xD06
0xD08
16
32
R/W 0x0000
0xFFFF
Main Stack Pointer (MSP) Monitor Start
Address Register
R/W 0x00000000
0x00000000
MPU
MPU
MPU
—
—
—
—
—
—
—
—
—
MSPMPUEA
PSPMPUOAD
PSPMPUCTL
Main Stack Pointer (MSP) Monitor End
Address Register
0xD0C
0xD10
0xD14
0xD16
32
16
16
R/W 0x00000000
R/W 0x0000
0x00000000
0xFFFF
Stack Pointer Monitor Operation After
Detection Register
Stack Pointer Monitor Access Control
Register
R/W 0x0000
0xFEFF
MPU
MPU
—
—
—
—
—
—
PSPMPUPT
PSPMPUSA
Stack Pointer Monitor Protection Register
16
32
R/W 0x0000
0xFFFF
Process Stack Pointer (PSP) Monitor Start 0xD18
Address Register
R/W 0x00000000
0x00000000
MPU
—
—
—
—
—
—
PSPMPUEA
PARIOAD
Process Stack Pointer (PSP) Monitor End
Address Register
0xD1C
32
8
R/W 0x00000000
R/W 0x00
0x00000000
0xFF
SRAM
SRAM Parity Error Operation After
Detection Register
0x00
SRAM
SRAM
SRAM
SRAM
—
—
—
—
—
—
—
—
—
—
—
—
SRAMPRCR
ECCMODE
ECC2STS
SRAM Protection Register
0x04
0xC0
0xC1
0xC2
8
8
8
8
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0xFF
0xFF
0xFF
0xFF
ECC Operating Mode Control Register
ECC 2-Bit Error Status Register
ECC1STSEN
ECC 1-Bit Error Information Update
Enable Register
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 93 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (2 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xFF
SRAM
SRAM
SRAM
SRAM
SRAM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ECC1STS
ECCETST
ECCPRCR
ECCPRCR2
ECCOAD
ECC 1-Bit Error Status Register
ECC Test Control Register
ECC Protection Register
ECC Protection Register 2
0xC3
0xC4
0xC4
0xD0
0xD8
8
8
8
8
8
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0xFF
0xFF
0xFF
SRAM ECC Error Operation After
Detection Register
0xFF
BUS
BUS
BUS
BUS
BUS
BUS
DTC
DTC
DTC
DTC
ICU
—
—
—
—
—
—
—
—
—
—
8
—
—
—
—
—
—
—
—
—
—
0x1
—
—
—
—
—
—
—
—
—
—
—
—
—
0-7
—
—
—
BUSMCNTSYS
BUSMCNTDMA
BUS3ERRADD
BUS3ERRSTAT
BUS4ERRADD
BUS4ERRSTAT
DTCCR
Master Bus Control Register SYS
Master Bus Control Register DMA
Bus Error Address Register 3
BUS Error Status Register 3
Bus Error Address Register 4
BUS Error Status Register 4
DTC Control Register
0x1008
0x100C
0x1820
0x1824
0x1830
0x1834
0x00
16
16
32
8
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
0x00000000
0xFE
R
R
R
R
0x00000000
0x00
32
8
0x00000000
0x00
0x00000000
0xFE
8
R/W 0x08
0xFF
DTCVBR
DTC Vector Base Register
DTC Module Start Register
DTC Status Register
0x04
32
8
R/W 0x00000000
R/W 0x00
0xFFFFFFFF
0xFF
DTCST
0x0C
DTCSTS
0x0E
16
8
R
0x0000
0xFFFF
0xFF
IRQCR%s
IRQ Control Register
0x000
0x100
0x120
0x130
R/W 0x00
ICU
—
—
—
NMICR
NMI Pin Interrupt Control Register
Non-Maskable Interrupt Enable Register
8
R/W 0x00
0xFF
ICU
NMIER
16
16
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
ICU
NMICLR
Non-Maskable Interrupt Status Clear
Register
ICU
—
—
—
—
32
—
—
—
—
—
—
—
—
—
—
—
0x4
—
—
—
—
—
—
—
—
—
—
—
0-31
—
—
—
—
—
—
—
NMISR
Non-Maskable Interrupt Status Register
Wake Up Interrupt Enable Register
ICU event Enable Register
0x140
0x1A0
0x1C0
0x200
0x300
0x00
16
32
8
R
0x0000
0xFFFF
ICU
WUPEN
R/W 0x00000000
R/W 0x00
0xFFFFFFFF
0xFF
ICU
IELEN
ICU
SELSR0
SYS Event Link Setting Register
ICU Event Link Setting Register %s
Debug Status Register
16
32
32
32
16
32
32
8
R/W 0x0000
0xFFFF
ICU
IELSR%s
DBGSTR
DBGSTOPCR
SBYCR
R/W 0x00000000
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFF
DBG
DBG
SYSC
SYSC
SYSC
SYSC
SYSC
R
0x00000000
Debug Stop Control Register
0x10
R/W 0x00000003
R/W 0x0000
Standby Control Register
0x00C
0x01C
0x020
0x026
0x031
MSTPCRA
SCKDIVCR
SCKSCR
MEMWAIT
Module Stop Control Register A
System Clock Division Control Register
System Clock Source Control Register
R/W 0xFFBFFFFF 0xFFFFFFFF
R/W 0x04000404
R/W 0x01
0xFFFFFFFF
0xFF
Memory Wait Cycle Control Register for
Code Flash
8
R/W 0x00
0xFF
SYSC
SYSC
—
—
—
—
—
—
MOSCCR
HOCOCR
Main Clock Oscillator Control Register
0x032
0x036
8
8
R/W 0x01
R/W 0x00
0xFF
0xFE
High-Speed On-Chip Oscillator Control
Register
SYSC
—
—
—
MOCOCR
Middle-Speed On-Chip Oscillator Control
Register
0x038
8
R/W 0x00
0xFF
SYSC
SYSC
SYSC
SYSC
SYSC
SYSC
SYSC
SYSC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OSCSF
Oscillation Stabilization Flag Register
Clock Out Control Register
0x03C
0x03E
8
8
8
8
8
8
8
8
R
0x00
0xFE
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
CKOCR
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
OSTDCR
OSTDSR
LPOPT
Oscillation Stop Detection Control Register 0x040
Oscillation Stop Detection Status Register 0x041
Lower Power Operation Control Register
MOCO User Trimming Control Register
HOCO User Trimming Control Register
Snooze Control Register
0x04C
0x061
0x062
0x092
MOCOUTCR
HOCOUTCR
SNZCR
R01DS0385EJ0100 Rev.1.00
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RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (3 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xFF
SYSC
SYSC
SYSC
SYSC
SYSC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SNZEDCR0
SNZREQCR
PSMCR
Snooze End Control Register
Snooze Request Control Register
Power Save Memory Control Register
Operating Power Control Register
0x094
0x098
0x09F
0x0A0
0x0A2
8
R/W 0x00
32
8
R/W 0x00000000
R/W 0x00
0xFFFFFFFF
0xFF
OPCCR
8
R/W 0x01
0xFF
MOSCWTCR
Main Clock Oscillator Wait Control
Register
8
R/W 0x05
0xFF
SYSC
SYSC
SYSC
SYSC
SYSC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SOPCCR
RSTSR1
LVD1CR1
LVD1SR
LVD2CR1
Sub Operating Power Control Register
Reset Status Register 1
0x0AA
0x0C0
0x0E0
0x0E1
0x0E2
8
R/W 0x00
R/W 0x0000
R/W 0x01
R/W 0x02
R/W 0x01
0xFF
16
8
0xE0F8
0xFF
Voltage Monitor 1 Circuit Control Register
Voltage Monitor 1 Circuit Status Register
8
0xFF
Voltage Monitor 2 Circuit Control Register
1
8
0xFF
SYSC
SYSC
SYSC
SYSC
SYSC
SYSC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LVD2SR
PRCR
Voltage Monitor 2 Circuit Status Register
Protect Register
0x0E3
0x3FE
0x040E
0x410
0x411
0x413
8
R/W 0x02
R/W 0x0000
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0xFF
0xFFFF
0xFF
0xF0
16
8
SYOCDCR
RSTSR0
RSTSR2
MOMCR
System Control OCD Control Register
Reset Status Register 0
8
Reset Status Register 2
8
0xFE
0xFF
Main Clock Oscillator Mode Oscillation
Control Register
8
SYSC
SYSC
SYSC
—
—
—
—
—
—
—
—
—
LVCMPCR
LVDLVLR
LVD1CR0
Voltage Monitor Circuit Control Register
Voltage Detection Level Select Register
0x417
0x418
0x41A
8
8
8
R/W 0x00
R/W 0x07
R/W 0x80
0xFF
0xFF
0xF7
Voltage Monitor 1 Circuit Control Register
0
SYSC
—
—
—
LVD2CR0
Voltage Monitor 2 Circuit Control Register
0
0x41B
8
R/W 0x80
0xF7
SYSC
SYSC
SYSC
SYSC
—
—
—
—
—
—
—
—
—
—
—
—
DCDCCTL
VCCSEL
SOSCCR
SOMCR
DCDC/LDO Control Register
0x440
0x441
0x480
0x481
8
8
8
8
R/W 0xC0
R/W 0x00
R/W 0x01
R/W 0x00
0xFF
0xFF
0xFF
0xFF
Voltage Level Selection Control Register
Sub-Clock Oscillator Control Register
Sub-Clock Oscillator Mode Control
Register
SYSC
SYSC
—
—
—
—
—
—
SOMRG
Sub-Clock Oscillator Margin Check
Register
0x482
0x490
8
8
R/W 0x00
R/W 0x00
0xFF
0xFF
LOCOCR
Low-Speed On-Chip Oscillator Control
Register
SYSC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LOCOUTCR
PCNTR1
PODR
LOCO User Trimming Control Register
Port Control Register 1
Port Control Register 1
Port Control Register 1
Port Control Register 2
Port Control Register 2
Port Control Register 3
Port Control Register 3
Port Control Register 3
Port Control Register 1
Port Control Register 1
Port Control Register 1
Port Control Register 2
Port Control Register 2
0x492
0x000
0x000
0x002
0x004
0x006
0x008
0x008
0x00A
0x000
0x000
0x002
0x004
0x004
8
R/W 0x00
0xFF
PORT0,3-8
PORT0,3-8
PORT0,3-8
PORT0,3-8
PORT0,3-8
PORT0,3-8
PORT0,3-8
PORT0,3-8
PORT1-2
PORT1-2
PORT1-2
PORT1-2
PORT1-2
32
16
16
32
16
32
16
16
32
16
16
32
16
R/W 0x00000000
R/W 0x0000
R/W 0x0000
0xFFFFFFFF
0xFFFF
PDR
0xFFFF
PCNTR2
PIDR
R
0x00000000
0x0000
0xFFFF0000
0x0000
R
PCNTR3
PORR
W
W
W
0x00000000
0x0000
0xFFFFFFFF
0xFFFF
POSR
0x0000
0xFFFF
PCNTR1
PODR
R/W 0x00000000
R/W 0x0000
0xFFFFFFFF
0xFFFF
PDR
R/W 0x0000
0xFFFF
PCNTR2
EIDR
R
R
0x00000000
0x0000
0xFFFF0000
0xFFFF
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 95 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (4 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0x0000
PORT1-2
PORT1-2
PORT1-2
PORT1-2
PORT1-2
PORT1-2
PORT1-2
PFS
—
—
—
—
—
—
—
9
—
—
PIDR
Port Control Register 2
0x006
0x008
0x008
0x00A
0x00C
0x00C
0x00E
0x000
0x002
0x003
0x028
0x02A
0x02B
0x040
0x042
0x043
0x060
0x062
0x063
0x064
0x066
0x067
0x068
0x06A
0x06B
0x080
0x082
0x083
0x084
0x086
0x087
0x088
0x08A
0x08B
0x0B0
0x0B2
0x0B3
0x0C0
0x0C2
0x0C3
0x0C4
0x0C6
0x0C7
0x100
0x102
16
32
16
16
32
16
16
32
16
8
R
0x0000
—
—
PCNTR3
Port Control Register 3
W
W
W
0x00000000
0x0000
0xFFFFFFFF
0xFFFF
—
—
PORR
Port Control Register 3
—
—
POSR
Port Control Register 3
0x0000
0xFFFF
—
—
PCNTR4
Port Control Register 4
R/W 0x00000000
R/W 0x0000
R/W 0x0000
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
—
—
EORR
Port Control Register 4
—
—
EOSR
Port Control Register 4
0xFFFF
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
—
0-8
0-8
0-8
10-15
10-15
10-15
0-7
0-7
0-7
—
P00%sPFS
P00%sPFS_HA
P00%sPFS_BY
P0%sPFS
Port 00%s Pin Function Select Register
Port 00%s Pin Function Select Register
Port 00%s Pin Function Select Register
Port 0%s Pin Function Select Register
Port 0%s Pin Function Select Register
Port 0%s Pin Function Select Register
Port 10%s Pin Function Select Register
Port 10%s Pin Function Select Register
Port 10%s Pin Function Select Register
Port 108 Pin Function Select Register
Port 108 Pin Function Select Register
Port 108 Pin Function Select Register
Port 109 Pin Function Select Register
Port 109 Pin Function Select Register
Port 109 Pin Function Select Register
Port 1%s Pin Function Select Register
Port 1%s Pin Function Select Register
Port 1%s Pin Function Select Register
Port 200 Pin Function Select Register
Port 200 Pin Function Select Register
Port 200 Pin Function Select Register
Port 201 Pin Function Select Register
Port 201 Pin Function Select Register
Port 201 Pin Function Select Register
Port 20%s Pin Function Select Register
Port 20%s Pin Function Select Register
Port 20%s Pin Function Select Register
Port 2%s Pin Function Select Register
Port 2%s Pin Function Select Register
Port 2%s Pin Function Select Register
Port 300 Pin Function Select Register
Port 300 Pin Function Select Register
Port 300 Pin Function Select Register
Port 30%s Pin Function Select Register
Port 30%s Pin Function Select Register
Port 30%s Pin Function Select Register
Port 40%s Pin Function Select Register
Port 40%s Pin Function Select Register
0xFFFFFFFD
0xFFFD
PFS
9
PFS
9
0xFD
PFS
6
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
6
P0%sPFS_HA
P0%sPFS_BY
P10%sPFS
P10%sPFS_HA
P10%sPFS_BY
P108PFS
PFS
6
0xFD
PFS
8
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
8
PFS
8
0xFD
PFS
—
—
—
—
—
—
6
32
16
8
R/W 0x00010010
R/W 0x0010
R/W 0x10
0xFFFFFFFD
0xFFFD
PFS
—
—
P108PFS_HA
P108PFS_BY
P109PFS
PFS
—
—
0xFD
PFS
—
—
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
—
—
P109PFS_HA
P109PFS_BY
P1%sPFS
PFS
—
—
0xFD
PFS
0x4
0x4
0x4
—
10-15
10-15
10-15
—
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
6
P1%sPFS_HA
P1%sPFS_BY
P200PFS
PFS
6
0xFD
PFS
—
—
—
—
—
—
7
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
—
—
P200PFS_HA
P200PFS_BY
P201PFS
PFS
—
—
0xFD
PFS
—
—
32
16
8
R/W 0x00000010
R/W 0x0010
R/W 0x10
0xFFFFFFFD
0xFFFD
PFS
—
—
P201PFS_HA
P201PFS_BY
P20%sPFS
P20%sPFS_HA
P20%sPFS_BY
P2%sPFS
PFS
—
—
0xFD
PFS
0x4
0x4
0x4
0x4
0x4
0x4
—
2-8
2-8
2-8
12-15
12-15
12-15
—
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
7
PFS
7
0xFD
PFS
4
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
4
P2%sPFS_HA
P2%sPFS_BY
P300PFS
PFS
4
0xFD
PFS
—
—
—
7
32
16
8
R/W 0x00010000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
—
—
P300PFS_HA
P300PFS_BY
P30%sPFS
P30%sPFS_HA
P30%sPFS_BY
P40%sPFS
P40%sPFS_HA
PFS
—
—
0xFD
PFS
0x4
0x4
0x4
0x4
0x4
1-7
1-7
1-7
0-9
0-9
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
PFS
7
PFS
7
0xFD
PFS
10
10
32
16
R/W 0x00000000
R/W 0x0000
0xFFFFFFFD
0xFFFD
PFS
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 96 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (5 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xFD
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
PFS
ELC
ELC
10
6
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
—
0-9
10-15
10-15
10-15
0-5
0-5
0-5
0-3
0-3
0-3
8-9
8-9
8-9
—
P40%sPFS_BY
P4%sPFS
Port 40%s Pin Function Select Register
Port 4%s Pin Function Select Register
Port 4%s Pin Function Select Register
Port 4%s Pin Function Select Register
Port 50%s Pin Function Select Register
Port 50%s Pin Function Select Register
Port 50%s Pin Function Select Register
Port 60%s Pin Function Select Register
Port 60%s Pin Function Select Register
Port 60%s Pin Function Select Register
Port 60%s Pin Function Select Register
Port 60%s Pin Function Select Register
Port 60%s Pin Function Select Register
Port 610 Pin Function Select Register
Port 610 Pin Function Select Register
Port 610 Pin Function Select Register
Port 708 Pin Function Select Register
Port 708 Pin Function Select Register
Port 708 Pin Function Select Register
Port 714 Pin Function Select Register
Port 714 Pin Function Select Register
Port 714 Pin Function Select Register
Port 80%s Pin Function Select Register
Port 80%s Pin Function Select Register
Port 80%s Pin Function Select Register
Write-Protect Register
0x103
0x128
0x12A
0x12B
0x140
0x142
0x143
0x180
0x182
0x183
0x1A0
0x1A2
0x1A3
0x1A8
0x1AA
0x1AB
0x1E0
0x1E2
0x1E3
0x1F8
0x1FA
0x1FB
0x220
0x222
0x223
0x503
0x50F
0x00
8
R/W 0x00
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
6
P4%sPFS_HA
P4%sPFS_BY
P50%sPFS
6
6
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
6
P50%sPFS_HA
P50%sPFS_BY
P60%sPFS
6
4
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
4
P60%sPFS_HA
P60%sPFS_BY
P60%sPFS
4
2
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
2
P60%sPFS_HA
P60%sPFS_BY
P610PFS
2
—
—
—
—
—
—
—
—
—
2
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
—
—
P610PFS_HA
P610PFS_BY
P708PFS
—
—
—
—
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
—
—
P708PFS_HA
P708PFS_BY
P714PFS
—
—
—
—
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
—
—
P714PFS_HA
P714PFS_BY
P80%sPFS
—
—
0x4
0x4
0x4
—
8-9
8-9
8-9
—
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFD
0xFFFD
0xFD
2
P80%sPFS_HA
P80%sPFS_BY
PWPR
2
—
—
—
2
8
R/W 0x80
0xFF
—
—
PRWCNTR
Port Read Wait Control Register
8
R/W 0x01
0xFF
—
—
ELCR
Event Link Controller Register
8
R/W 0x00
0xFF
0x02
0-1
ELSEGR%s
Event Link Software Event Generation
Register %s
0x02
8
R/W 0x80
0xFF
ELC
ELC
ELC
ELC
ELC
POEG
POEG
RTC
RTC
RTC
RTC
RTC
RTC
4
0x04
0x04
—
0-3
8-9
—
ELSR%s
ELSR%s
ELSR12
Event Link Setting Register %s
Event Link Setting Register %s
Event Link Setting Register 12
Event Link Setting Register %s
Event Link Setting Register 18
POEG Group A Setting Register
POEG Group B Setting Register
64-Hz Counter
0x10
0x30
0x40
0x48
0x58
0x000
0x100
0x00
0x02
16
16
16
16
16
32
32
8
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x00000000
R/W 0x00000000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFFFFFF
0xFFFFFFFF
0x00
2
—
2
0x04
—
14-15
—
ELSR%s
ELSR18
—
—
—
—
4
—
—
POEGGA
POEGGB
R64CNT
BCNT%s
RSECCNT
RMINCNT
RHRCNT
RWKCNT
—
—
—
—
R
0x00
0x02
—
0-3
—
Binary Counter %s
8
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0x00
—
—
—
—
Second Counter (in Calendar Count Mode) 0x02
Minute Counter (in Calendar Count Mode) 0x04
8
0x00
—
—
8
0x00
—
—
Hour Counter (in Calendar Count Mode)
0x06
0x08
8
0x00
—
—
Day-of-Week Counter (in Calendar Count
Mode)
8
0x00
RTC
RTC
—
—
—
—
—
—
RDAYCNT
RMONCNT
Day Counter
0x0A
0x0C
8
8
R/W 0x00
R/W 0x00
0xC0
0xE0
Month Counter
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 97 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (6 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xFF00
0x00
RTC
RTC
RTC
—
4
—
—
RYRCNT
Year Counter
0x0E
0x10
16
8
R/W 0x0000
R/W 0x00
R/W 0x00
0x02
—
0-3
—
BCNT%sAR
RSECAR
Binary Counter %s Alarm Register
—
Second Alarm Register (in Calendar Count 0x10
Mode)
8
0x00
RTC
RTC
RTC
—
—
—
—
—
—
—
—
—
RMINAR
RHRAR
RWKAR
Minute Alarm Register (in Calendar Count 0x12
Mode)
8
8
8
R/W 0x00
R/W 0x00
R/W 0x00
0x00
0x00
0x00
Hour Alarm Register (in Calendar Count
Mode)
0x14
Day-of-Week Alarm Register (in Calendar
Count Mode)
0x16
RTC
RTC
2
0x02
—
0-1
—
BCNT%sAER
RDAYAR
Binary Counter %s Alarm Enable Register 0x18
8
8
R/W 0x00
R/W 0x00
0x00
0x00
—
Date Alarm Register (in Calendar Count
Mode)
0x18
RTC
—
—
—
RMONAR
Month Alarm Register (in Calendar Count
Mode)
0x1A
8
R/W 0x00
0x00
RTC
RTC
—
—
—
—
—
—
BCNT2AER
RYRAR
Binary Counter 2 Alarm Enable Register
0x1C
0x1C
16
16
R/W 0x0000
R/W 0x0000
0xFF00
0xFF00
Year Alarm Register (in Calendar Count
Mode)
RTC
RTC
—
—
—
—
—
—
BCNT3AER
RYRAREN
Binary Counter 3 Alarm Enable Register
0x1E
0x1E
8
8
R/W 0x00
R/W 0x00
0x00
0x00
Year Alarm Enable Register (in Calendar
Count Mode)
RTC
RTC
—
—
—
—
—
—
RCR1
RCR2
RTC Control Register 1
0x22
8
8
R/W 0x00
R/W 0x00
0x0A
0x0E
RTC Control Register 2 (in Calendar Count 0x24
Mode)
RTC
—
—
—
RCR2
RTC Control Register 2 (in Binary Count
Mode)
0x24
8
R/W 0x00
0x0E
RTC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCR4
RTC Control Register 4
0x28
0x2A
0x2C
0x2E
0x00
0x02
0x04
0x06
0x08
0x00
0x04
0x00
0x01
0x02
0x03
0x04
0x06
0x08
0x0A
0x000
0x004
0x008
0x00C
8
R/W 0x00
R/W 0x0000
R/W 0x0000
R/W 0x00
R/W 0xFF
R/W 0x0000
R/W 0x0000
R/W 0x80
R/W 0x80
R/W 0xFF
R/W 0x0000
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0x7E
RTC
RFRH
Frequency Register H
16
16
8
0xFFFE
0x0000
0x00
RTC
RFRL
Frequency Register L
RTC
RADJ
Time Error Adjustment Register
WDT Refresh Register
WDT
WDT
WDT
WDT
WDT
IWDT
IWDT
CAC
CAC
CAC
CAC
CAC
CAC
CAC
CAC
MSTP
MSTP
MSTP
MSTP
WDTRR
WDTCR
WDTSR
WDTRCR
WDTCSTPR
IWDTRR
IWDTSR
CACR0
8
0xFF
WDT Control Register
16
16
8
0xFFFF
0xFFFF
0xFF
WDT Status Register
WDT Reset Control Register
WDT Count Stop Control Register
IWDT Refresh Register
8
0xFF
8
0xFF
IWDT Status Register
16
8
0xFFFF
0xFF
CAC Control Register 0
CACR1
CAC Control Register 1
8
0xFF
CACR2
CAC Control Register 2
8
0xFF
CAICR
CAC Interrupt Control Register
CAC Status Register
8
0xFF
CASTR
8
R
0x00
0xFF
CAULVR
CALLVR
CACNTBR
MSTPCRB
MSTPCRC
MSTPCRD
LSMRWDIS
CAC Upper-Limit Value Setting Register
CAC Lower-Limit Value Setting Register
CAC Counter Buffer Register
Module Stop Control Register B
Module Stop Control Register C
Module Stop Control Register D
16
16
16
32
32
32
16
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
0xFFFF
R
0x0000
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
Low Speed Module R/W Disable Control
Register
R/W 0x0000
0xFFFF
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 98 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (7 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0x00000001
0x0000
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
32
32
32
32
32
32
32
32
32
32
32
8
0x10
0x10
0x10
0x10
0x10
0x10
0x10
0x10
0x10
0x10
0x10
0x04
0x04
—
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
0-31
—
MB%s_ID
MB%s_DL
MB%s_D0
MB%s_D1
MB%s_D2
MB%s_D3
MB%s_D4
MB%s_D5
MB%s_D6
MB%s_D7
MB%s_TS
MKR[%s]
FIDCR%s
MKIVLR
Mailbox ID Register %s
0x200
0x204
0x206
0x207
0x208
0x209
0x20A
0x20B
0x20C
0x20D
0x20E
0x400
0x420
0x428
0x42C
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
Mailbox Data Length Register %s
Mailbox Data Register %s
Mailbox Data Register %s
Mailbox Data Register %s
Mailbox Data Register %s
Mailbox Data Register %s
Mailbox Data Register %s
Mailbox Data Register %s
Mailbox Data Register %s
Mailbox Time Stamp Register %s
Mask Register %s
0x00
8
R/W 0x00
0x00
8
R/W 0x00
0x00
8
R/W 0x00
0x00
8
R/W 0x00
0x00
8
R/W 0x00
0x00
8
R/W 0x00
0x00
8
R/W 0x00
0x00
16
32
32
32
32
32
R/W 0x0000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
0x0000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
2
0-1
FIFO Received ID Compare Register %s
Mask Invalid Register
—
—
—
—
—
—
MIER
Mailbox Interrupt Enable Register
—
—
MIER_FIFO
Mailbox Interrupt Enable Register for FIFO 0x42C
Mailbox Mode
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
32
32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x01
0x01
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCTL_RX[%s]
MCTL_TX[%s]
CTLR
Message Control Register for Receive
Message Control Register for Transmit
Control Register
0x820
0x820
0x840
0x842
0x844
0x848
0x849
0x84A
0x84B
0x84C
0x84D
0x84E
0x84F
0x850
0x851
0x852
0x853
0x854
0x856
0x858
0x00
8
R/W 0x00
R/W 0x00
R/W 0x0500
0xFF
8
0xFF
16
16
32
8
0xFFFF
0xFFFF
0xFFFFFFFF
0xFF
STR
Status Register
R
0x0500
BCR
Bit Configuration Register
R/W 0x00000000
R/W 0x80
RFCR
RFPCR
TFCR
Receive FIFO Control Register
Receive FIFO Pointer Control Register
Transmit FIFO Control Register
Transmit FIFO Pointer Control Register
Error Interrupt Enable Register
Error Interrupt Factor Judge Register
Receive Error Count Register
Transmit Error Count Register
Error Code Store Register
8
W
0x00
R/W 0x80
0x00
0x00
8
0xFF
TFPCR
EIER
8
W
0x00
8
R/W 0x00
R/W 0x00
0xFF
EIFR
8
0xFF
RECR
TECR
8
R
R
0x00
0x00
0xFF
8
0xFF
ECSR
CSSR
MSSR
MSMR
TSR
8
R/W 0x00
R/W 0x00
0xFF
Channel Search Support Register
Mailbox Search Status Register
Mailbox Search Mode Register
Time Stamp Register
8
0x00
8
R
0x80
0xFF
8
R/W 0x00
0xFF
16
16
8
R
0x0000
0xFFFF
0x0000
0xFF
AFSR
Acceptance Filter Support Register
Test Control Register
R/W 0x0000
R/W 0x00
R/W 0x1F
R/W 0x00
R/W 0x08
R/W 0x06
R/W 0x00
R/W 0x72
R/W 0x09
R/W 0x00
TCR
ICCR1
ICCR2
ICMR1
ICMR2
ICMR3
ICFER
ICSER
ICIER
I2C Bus Control Register 1
8
0xFF
I2C Bus Control Register 2
0x01
8
0xFF
I2C Bus Mode Register 1
0x02
8
0xFF
I2C Bus Mode Register 2
0x03
8
0xFF
I2C Bus Mode Register 3
0x04
8
0xFF
I2C Bus Function Enable Register
I2C Bus Status Enable Register
I2C Bus Interrupt Enable Register
0x05
8
0xFF
0x06
8
0xFF
0x07
8
0xFF
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 99 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (8 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xFF
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0-1
IIC0WU
IIC0WU
DOC
—
—
3
—
—
—
0-2
0-2
—
—
—
—
—
—
—
—
—
—
—
—
—
ICSR1
I2C Bus Status Register 1
I2C Bus Status Register 2
Slave Address Register Ly
Slave Address Register Uy
I2C Bus Bit Rate Low-Level Register
I2C Bus Bit Rate High-Level Register
I2C Bus Transmit Data Register
I2C Bus Receive Data Register
I2C Bus Wakeup Unit Register
I2C Bus Wakeup Unit Register 2
DOC Control Register
0x08
0x09
0x0A
0x0B
0x10
0x11
8
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0xFF
R/W 0xFF
R/W 0xFF
—
ICSR2
8
0xFF
0x02
0x02
—
SARL%s
SARU%s
ICBRL
8
0xFF
3
8
0xFF
—
—
—
—
—
—
—
—
—
—
—
—
—
8
0xFF
—
ICBRH
8
0xFF
—
ICDRT
0x12
0x13
0x02
0x03
0x00
0x02
0x04
0x000
0x004
0x006
0x008
8
0xFF
—
ICDRR
8
R
0x00
0xFF
—
ICWUR
ICWUR2
DOCR
8
R/W 0x10
0xFF
—
8
R/W 0xFD
R/W 0x00
0xFF
—
8
0xFF
DOC
—
DODIR
DOC Data Input Register
16
16
16
16
16
16
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
DOC
—
DODSR
ADCSR
ADANSA0
ADANSA1
ADADS0
DOC Data Setting Register
A/D Control Register
ADC12
ADC12
ADC12
ADC12
—
—
A/D Channel Select Register A0
A/D Channel Select Register A1
—
—
A/D-Converted Value Addition/Average
Channel Select Register 0
ADC12
ADC12
—
—
—
—
—
—
ADADS1
ADADC
A/D-Converted Value Addition/Average
Channel Select Register 1
0x00A
0x00C
16
8
R/W 0x0000
R/W 0x00
0xFFFF
0xFF
A/D-Converted Value Addition/Average
Count Select Register
ADC12
ADC12
—
—
—
—
—
—
ADCER
A/D Control Extended Register
0x00E
0x010
16
16
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
ADSTRGR
A/D Conversion Start Trigger Select
Register
ADC12
—
—
—
ADEXICR
A/D Conversion Extended Input Control
Registers
0x012
16
R/W 0x0000
0xFFFF
ADC12
ADC12
ADC12
ADC12
ADC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADANSB0
ADANSB1
ADDBLDR
ADTSDR
ADOCDR
A/D Channel Select Register B0
A/D Channel Select Register B1
A/D Data Duplexing Register
0x014
0x016
0x018
0x01A
0x01C
16
16
16
16
16
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
R
R
R
0x0000
0x0000
0x0000
A/D Temperature Sensor Data Register
A/D Internal Reference Voltage Data
Register
ADC12
ADC12
ADC12
ADC12
ADC12
—
15
—
4
—
—
ADRD
A/D Self-Diagnosis Data Register
A/D Data Registers %s
0x01E
0x020
0x040
0x042
0x07A
16
16
16
16
8
R
R
R
R
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF
0x2
—
0-14
—
ADDR%s
ADCTDR
ADDR%s
ADDISCR
A/D CTSU TSCAP Voltage Data Register
A/D Data Registers %s
0x2
—
17-20
—
—
A/D Disconnection Detection Control
Register
R/W 0x00
R/W 0x00
R/W 0x0000
ADC12
—
—
—
ADACSR
A/D Conversion Operation Mode Select
Register
0x07E
8
0xFF
ADC12
ADC12
ADC12
ADC12
—
—
—
—
—
—
—
—
—
—
—
—
ADGSPCR
A/D Group Scan Priority Control Register
A/D Data Duplexing Register A
0x080
0x084
0x086
0x08A
16
16
16
8
0xFFFF
0xFFFF
0xFFFF
0xFF
ADDBLDRA
ADDBLDRB
ADHVREFCNT
R
R
0x0000
0x0000
A/D Data Duplexing Register B
A/D High-Potential/Low-Potential
Reference Voltage Control Register
R/W 0x00
ADC12
ADC12
—
—
—
—
—
—
ADWINMON
ADCMPCR
A/D Compare Function Window A/B Status 0x08C
Monitor Register
8
R
0x00
0xFF
A/D Compare Function Control Register
0x090
16
R/W 0x0000
0xFFFF
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 100 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (9 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
ADC12
—
—
—
ADCMPANSER
A/D Compare Function Window A
Extended Input Select Register
0x092
8
R/W 0x00
0xFF
ADC12
—
—
—
ADCMPLER
A/D Compare Function Window A
Extended Input Comparison Condition
Setting Register
0x093
8
R/W 0x00
0xFF
ADC12
ADC12
ADC12
ADC12
ADC12
ADC12
ADC12
ADC12
ADC12
ADC12
ADC12
ADC12
—
—
—
—
2
—
—
—
—
0x2
—
—
—
—
—
—
—
—
—
—
—
0-1
—
—
—
—
—
—
—
ADCMPANSR0
ADCMPANSR1
ADCMPLR0
ADCMPLR1
ADCMPDR%s
ADCMPSR0
ADCMPSR1
ADCMPSER
ADCMPBNSR
ADWINLLB
A/D Compare Function Window A Channel 0x094
Select Register 0
16
16
16
16
16
16
16
8
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0x00
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF
A/D Compare Function Window A Channel 0x096
Select Register 1
A/D Compare Function Window A
Comparison Condition Setting Register 0
0x098
0x09A
0x09C
A/D Compare Function Window A
Comparison Condition Setting Register 1
A/D Compare Function Window A Lower-
Side/Upper-Side Level Setting Register
—
—
—
—
—
—
—
A/D Compare Function Window A Channel 0x0A0
Status Register 0
A/D Compare Function Window A Channel 0x0A2
Status Register1
A/D Compare Function Window A
0x0A4
Extended Input Channel Status Register
A/D Compare Function Window B Channel 0x0A6
Select Register
8
R/W 0x00
0xFF
A/D Compare Function Window B Lower-
Side/Upper-Side Level Setting Register
0x0A8
0x0AA
0x0AC
16
16
8
R/W 0x0000
R/W 0x0000
R/W 0x00
0xFFFF
0xFFFF
0xFF
ADWINULB
A/D Compare Function Window B Lower-
Side/Upper-Side Level Setting Register
ADCMPBSR
A/D Compare Function Window B Status
Register
ADC12
ADC12
ADC12
ADC12
DAC12
DAC12
DAC12
DAC12
—
—
—
15
—
—
—
—
—
—
—
0x1
—
—
—
—
—
ADSSTRL
ADSSTRT
ADSSTRO
ADSSTR%s
DADR0
A/D Sampling State Register
A/D Sampling State Register
A/D Sampling State Register
A/D Sampling State Register
D/A Data Register 0
0x0DD
0x0DE
0x0DF
0x0E0
0x00
8
R/W 0x0D
R/W 0x0D
R/W 0x0D
R/W 0x0D
R/W 0x0000
R/W 0x1F
R/W 0x00
R/W 0x00
0xFF
0xFF
0xFF
0xFF
0xFFFF
0xFF
0xFF
0xFF
—
8
—
8
0-14
—
8
16
8
—
DACR
D/A Control Register
0x04
—
DADPR
DADR0 Format Select Register
0x05
8
—
DAADSCR
D/A A/D Synchronous Start Control
Register
0x06
8
DAC12
SCI0
—
—
—
—
—
—
DAVREFCR
SMR
D/A VREF Control Register
0x07
0x00
8
8
R/W 0x00
R/W 0x00
0xFF
0xFF
Serial Mode Register for Non-Smart Card
Interface Mode (SCMR.SMIF = 0)
SCI0
—
—
—
SMR_SMCI
Serial Mode Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x00
0x01
8
R/W 0x00
0xFF
SCI0
SCI0
—
—
—
—
—
—
BRR
SCR
Bit Rate Register
8
8
R/W 0xFF
R/W 0x00
0xFF
0xFF
Serial Control Register for Non-Smart Card 0x02
Interface Mode (SCMR.SMIF = 0)
SCI0
—
—
—
SCR_SMCI
Serial Control Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x02
8
R/W 0x00
0xFF
SCI0
SCI0
—
—
—
—
—
—
TDR
SSR
Transmit Data Register
0x03
8
8
R/W 0xFF
R/W 0x84
0xFF
0xFF
Serial Status Register for Non-Smart Card 0x04
Interface and Non-FIFO Mode
(SCMR.SMIF = 0 and FCR.FM = 0)
SCI0
—
—
—
SSR_FIFO
Serial Status Register for Non-Smart Card 0x04
Interface and FIFO Mode (SCMR.SMIF = 0
and FCR.FM = 1)
8
R/W 0x80
0xFD
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 101 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (10 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
SCI0
—
—
—
SSR_SMCI
Serial Status Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x04
8
R/W 0x84
0xFF
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI0
SCI1-3,9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RDR
Receive Data Register
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x10
0x0E
0x10
0x10
0x0E
0x11
0x0F
0x12
0x13
0x14
0x16
0x18
0x1A
0x1C
0x00
8
R/W 0x00
R/W 0xF2
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0xFF
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
IIC Mode Register 1
8
0xFF
8
0xFF
8
0xFF
8
0xFF
IIC Mode Register 2
8
0xFF
IIC Mode Register 3
8
0xFF
IIC Status Register
8
R
0x00
0xCB
0xFF
SPMR
TDRHL
FRDRHL
FTDRHL
RDRHL
FRDRH
FTDRH
FRDRL
FTDRL
MDDR
DCCR
FCR
SPI Mode Register
8
R/W 0x00
Transmit Data Register
Receive FIFO Data Register
Transmit FIFO Data Register
Receive Data Register
16
16
16
16
8
R/W 0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF
R
0x0000
0xFFFF
0x0000
0x00
W
R
Receive FIFO Data Register
Transmit FIFO Data Register
Receive FIFO Data Register
Transmit FIFO Data Register
Modulation Duty Register
Data Compare Match Control Register
FIFO Control Register
R
8
W
R
0xFF
0xFF
8
0x00
0xFF
8
W
0xFF
0xFF
8
R/W 0xFF
R/W 0x40
R/W 0xF800
0xFF
8
0xFF
16
16
16
16
8
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF
FDR
FIFO Data Count Register
Line Status Register
R
R
0x0000
0x0000
LSR
CDR
Compare Match Data Register
Serial Port Register
R/W 0x0000
R/W 0x03
R/W 0x00
SPTR
SMR
Serial Mode Register for Non-Smart Card
Interface Mode (SCMR.SMIF = 0)
8
0xFF
SCI1-3,9
—
—
—
SMR_SMCI
Serial Mode Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x00
8
R/W 0x00
0xFF
SCI1-3,9
SCI1-3,9
—
—
—
—
—
—
BRR
SCR
Bit Rate Register
0x01
8
8
R/W 0xFF
R/W 0x00
0xFF
0xFF
Serial Control Register for Non-Smart Card 0x02
Interface Mode (SCMR.SMIF = 0)
SCI1-3,9
—
—
—
SCR_SMCI
Serial Control Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x02
8
R/W 0x00
0xFF
SCI1-3,9
SCI1-3,9
—
—
—
—
—
—
TDR
SSR
Transmit Data Register
0x03
8
8
R/W 0xFF
R/W 0x84
0xFF
0xFF
Serial Status Register for Non-Smart Card 0x04
Interface and Non-FIFO Mode
(SCMR.SMIF = 0 and FCR.FM = 0)
SCI1-3,9
—
—
—
SSR_SMCI
Serial Status Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x04
8
R/W 0x84
0xFF
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RDR
Receive Data Register
Smart Card Mode Register
Serial Extended Mode Register
Noise Filter Setting Register
IIC Mode Register 1
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
8
8
8
8
8
8
8
R/W 0x00
R/W 0xF2
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
IIC Mode Register 2
IIC Mode Register 3
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 102 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (11 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xCB
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SCI1-3,9
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
SPI0-1
CRC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SISR
IIC Status Register
0x0C
0x0D
0x0E
0x10
0x12
0x13
0x1A
0x1C
0x00
0x01
0x02
0x03
0x04
0x04
0x0A
0x0B
0x0C
8
R
0x00
SPMR
SPI Mode Register
8
R/W 0x00
0xFF
TDRHL
RDRHL
MDDR
Transmit Data Register
Receive Data Register
Modulation Duty Register
Data Compare Match Control Register
Compare Match Data Register
Serial Port Register
16
16
8
R/W 0xFFFF
0xFFFF
0xFFFF
0xFF
R
0x0000
R/W 0xFF
DCCR
8
R/W 0x40
0xFF
CDR
16
8
R/W 0x0000
R/W 0x03
0xFFFF
0xFF
SPTR
SPCR
SPI Control Register
8
R/W 0x00
0xFF
SSLP
SPI Slave Select Polarity Register
SPI Pin Control Register
SPI Status Register
8
R/W 0x00
0xFF
SPPCR
SPSR
8
R/W 0x00
0xFF
8
R/W 0x20
0xFF
SPDR
SPI Data Register
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0xFF
0xFFFFFFFF
0xFFFF
0xFF
SPDR_HA
SPBR
SPI Data Register
SPI Bit Rate Register
SPI Data Control Register
SPI Clock Delay Register
SPDCR
SPCKD
SSLND
SPND
8
R/W 0x00
0xFF
8
R/W 0x00
0xFF
SPI Slave Select Negation Delay Register 0x0D
8
R/W 0x00
0xFF
SPI Next-Access Delay Register
SPI Control Register 2
0x0E
0x0F
0x10
0x00
0x01
0x04
0x04
0x08
0x08
0x08
0x0C
0x00
8
R/W 0x00
0xFF
SPCR2
SPCMD0
CRCCR0
CRCCR1
CRCDIR
CRCDIR_BY
CRCDOR
CRCDOR_HA
CRCDOR_BY
CRCSAR
GTWP
8
R/W 0x00
0xFF
SPI Command Register 0
CRC Control Register 0
CRC Control Register 1
CRC Data Input Register
CRC Data Input Register
CRC Data Output Register
CRC Data Output Register
CRC Data Output Register
Snoop Address Register
16
8
R/W 0x070D
R/W 0x00
0xFFFF
0xFF
CRC
8
R/W 0x00
0xFF
CRC
32
8
R/W 0x00000000
R/W 0x00
0xFFFFFFFF
0xFF
CRC
CRC
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
0xFF
CRC
CRC
CRC
16
32
R/W 0x0000
R/W 0x00000000
0xFFFF
0xFFFFFFFF
GPT320-3
General PWM Timer Write-Protection
Register
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTSTR
GTSTP
General PWM Timer Software Start
Register
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
32
32
32
32
32
32
32
32
32
R/W 0x00000000
0xFFFFFFFF
General PWM Timer Software Stop
Register
R/W 0xFFFFFFFF 0xFFFFFFFF
GTCLR
GTSSR
GTPSR
GTCSR
GTUPSR
GTDNSR
GTICASR
General PWM Timer Software Clear
Register
W
0x00000000
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
General PWM Timer Start Source Select
Register
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
General PWM Timer Stop Source Select
Register
General PWM Timer Clear Source Select
Register
General PWM Timer Up Count Source
Select Register
General PWM Timer Down Count Source
Select Register
General PWM Timer Input Capture Source 0x24
Select Register A
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 103 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (12 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
GPT320-3
—
—
—
GTICBSR
General PWM Timer Input Capture Source 0x28
Select Register B
32
R/W 0x00000000
0xFFFFFFFF
GPT320-3
GPT320-3
—
—
—
—
—
—
GTCR
General PWM Timer Control Register
0x2C
0x30
32
32
R/W 0x00000000
R/W 0x00000001
0xFFFFFFFF
0xFFFFFFFF
GTUDDTYC
General PWM Timer Count Direction and
Duty Setting Register
GPT320-3
GPT320-3
—
—
—
—
—
—
GTIOR
General PWM Timer I/O Control Register
0x34
0x38
32
32
R/W 0x00000000
R/W 0x00000000
0xFFFFFFFF
0xFFFFFFFF
GTINTAD
General PWM Timer Interrupt Output
Setting Register
GPT320-3
GPT320-3
—
—
—
—
—
—
GTST
General PWM Timer Status Register
0x3C
0x40
32
32
R/W 0x00008000
R/W 0x00000000
0xFFFFFFFF
0xFFFFFFFF
GTBER
General PWM Timer Buffer Enable
Register
GPT320-3
GPT320-3
—
—
—
—
—
—
GTCNT
General PWM Timer Counter
0x48
0x4C
32
32
R/W 0x00000000
0xFFFFFFFF
GTCCRA
General PWM Timer Compare Capture
Register A
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT320-3
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
General PWM Timer Compare Capture
Register B
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x88
0x8C
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
General PWM Timer Compare Capture
Register C
General PWM Timer Compare Capture
Register E
General PWM Timer Compare Capture
Register D
General PWM Timer Compare Capture
Register F
General PWM Timer Cycle Setting
Register
GTPBR
GTDTCR
GTDVU
GTWP
General PWM Timer Cycle Setting Buffer
Register
General PWM Timer Dead Time Control
Register
R/W 0x00000000
0xFFFFFFFF
General PWM Timer Dead Time Value
Register U
R/W 0xFFFFFFFF 0xFFFFFFFF
General PWM Timer Write-Protection
Register
R/W 0x00000000
R/W 0x00000000
0xFFFFFFFF
0xFFFFFFFF
GTSTR
General PWM Timer Software Start
Register
GTSTP
General PWM Timer Software Stop
Register
R/W 0xFFFFFFFF 0xFFFFFFFF
GTCLR
General PWM Timer Software Clear
Register
W
0x00000000
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
GTSSR
GTPSR
GTCSR
GTUPSR
GTDNSR
GTICASR
GTICBSR
GTCR
General PWM Timer Start Source Select
Register
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
General PWM Timer Stop Source Select
Register
General PWM Timer Clear Source Select
Register
General PWM Timer Up Count Source
Select Register
General PWM Timer Down Count Source
Select Register
General PWM Timer Input Capture Source 0x24
Select Register A
General PWM Timer Input Capture Source 0x28
Select Register B
General PWM Timer Control Register
0x2C
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 104 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (13 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
GPT164-9
—
—
—
GTUDDTYC
General PWM Timer Count Direction and
Duty Setting Register
0x30
32
R/W 0x00000001
0xFFFFFFFF
GPT164-9
GPT164-9
—
—
—
—
—
—
GTIOR
General PWM Timer I/O Control Register
0x34
0x38
32
32
R/W 0x00000000
R/W 0x00000000
0xFFFFFFFF
0xFFFFFFFF
GTINTAD
General PWM Timer Interrupt Output
Setting Register
GPT164-9
GPT164-9
—
—
—
—
—
—
GTST
General PWM Timer Status Register
0x3C
0x40
32
32
R/W 0x00008000
R/W 0x00000000
0xFFFFFFFF
0xFFFFFFFF
GTBER
General PWM Timer Buffer Enable
Register
GPT164-9
GPT164-9
—
—
—
—
—
—
GTCNT
General PWM Timer Counter
0x48
0x4C
32
32
R/W 0x00000000
0xFFFFFFFF
GTCCRA
General PWM Timer Compare Capture
Register A
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
R/W 0xFFFFFFFF 0xFFFFFFFF
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
GPT164-9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GTCCRB
GTCCRC
GTCCRE
GTCCRD
GTCCRF
GTPR
General PWM Timer Compare Capture
Register B
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x88
0x8C
32
32
32
32
32
32
32
32
32
General PWM Timer Compare Capture
Register C
General PWM Timer Compare Capture
Register E
General PWM Timer Compare Capture
Register D
General PWM Timer Compare Capture
Register F
General PWM Timer Cycle Setting
Register
GTPBR
General PWM Timer Cycle Setting Buffer
Register
GTDTCR
GTDVU
General PWM Timer Dead Time Control
Register
R/W 0x00000000
0xFFFFFFFF
General PWM Timer Dead Time Value
Register U
R/W 0xFFFFFFFF 0xFFFFFFFF
GPT_OPS
KINT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OPSCR
Output Phase Switching Control Register
Key Return Control Register
Key Return Flag Register
0x00
0x00
0x04
0x08
0x00
0x00
0x00
0x01
0x02
0x03
0x04
0x04
0x04
0x05
0x06
0x07
0x08
0x08
0x08
0x09
0x0A
0x0A
32
8
R/W 0x00000000
R/W 0x00
0xFFFFFFFF
0xFF
KRCTL
KINT
KRF
8
R/W 0x00
0xFF
KINT
KRM
Key Return Mode Register
8
R/W 0x00
0xFF
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSUCRA
CTSUCRAL
CTSUCR0
CTSUCR1
CTSUCR2
CTSUCR3
CTSUCRB
CTSUCRBL
CTSUSDPRS
CTSUSST
CTSUCRBH
CTSUDCLKC
CTSUMCH
CTSUMCHL
CTSUMCH0
CTSUMCH1
CTSUMCHH
CTSUMFAF
CTSU Control Register A
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
0xFF
CTSU Control Register A
CTSU Control Register A
CTSU Control Register A
8
R/W 0x00
0xFF
CTSU Control Register A
8
R/W 0x00
0xFF
CTSU Control Register A
8
R/W 0x00
0xFF
CTSU Control Register B
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
0xFF
CTSU Control Register B
CTSU Control Register B
CTSU Control Register B
8
R/W 0x00
0xFF
CTSU Control Register B
16
8
R/W 0x0000
R/W 0x00
0xFFFF
0xFF
CTSU Control Register B
CTSU Measurement Channel Register
CTSU Measurement Channel Register
CTSU Measurement Channel Register
CTSU Measurement Channel Register
CTSU Measurement Channel Register
CTSU Measurement Channel Register
32
16
8
R/W 0x00003F3F
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
0xFF
8
R/W 0x00
0xFF
16
8
R/W 0x3F3F
R/W 0x3F
0xFFFF
0xFF
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 105 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (14 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
0xFFFFFFFF
0xFFFF
0xFF
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CTSUCHACA
CTSUCHACAL
CTSUCHAC0
CTSUCHAC1
CTSUCHACAH
CTSUCHAC2
CTSUCHAC3
CTSUCHACB
CTSUCHACBL
CTSUCHAC4
CTSUCHTRCA
CTSU Channel Enable Control Register A 0x0C
CTSU Channel Enable Control Register A 0x0C
CTSU Channel Enable Control Register A 0x0C
CTSU Channel Enable Control Register A 0x0D
CTSU Channel Enable Control Register A 0x0E
CTSU Channel Enable Control Register A 0x0E
CTSU Channel Enable Control Register A 0x0F
CTSU Channel Enable Control Register B 0x10
CTSU Channel Enable Control Register B 0x10
CTSU Channel Enable Control Register B 0x10
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
8
R/W 0x00
0xFF
16
8
R/W 0x0000
R/W 0x00
0xFFFF
0xFF
8
R/W 0x00
0xFF
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
0xFF
CTSU Channel Transmit/Receive Control
Register A
0x14
0x14
0x14
0x15
0x16
0x16
0x17
0x18
0x18
0x18
32
R/W 0x00000000
0xFFFFFFFF
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CTSUCHTRCAL CTSU Channel Transmit/Receive Control
Register A
16
8
R/W 0x0000
R/W 0x00
0xFFFF
0xFF
CTSUCHTRC0
CTSU Channel Transmit/Receive Control
Register A
CTSUCHTRC1
CTSU Channel Transmit/Receive Control
Register A
8
R/W 0x00
0xFF
CTSUCHTRCAH CTSU Channel Transmit/Receive Control
Register A
16
8
R/W 0x0000
R/W 0x00
0xFFFF
0xFF
CTSUCHTRC2
CTSUCHTRC3
CTSUCHTRCB
CTSU Channel Transmit/Receive Control
Register A
CTSU Channel Transmit/Receive Control
Register A
8
R/W 0x00
0xFF
CTSU Channel Transmit/Receive Control
Register B
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
0xFF
CTSUCHTRCBL CTSU Channel Transmit/Receive Control
Register B
CTSUCHTRC4
CTSU Channel Transmit/Receive Control
Register B
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
CTSU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CTSUSR
CTSU Status Register
0x1C
0x1C
0x1C
0x1D
0x1E
0x1E
0x20
0x20
0x22
0x24
0x24
0x28
0x28
0x2A
0x2C
32
16
8
R/W 0x00000000
R/W 0x0000
R/W 0x00
0xFFFFFFFF
0xFFFF
CTSUSRL
CTSUSR0
CTSUST
CTSU Status Register
CTSU Status Register
0xFF
CTSU Status Register
8
R/W 0x00
0xFF
CTSUSRH
CTSUSR2
CTSUSO
CTSU Status Register
16
8
R/W 0x0000
R/W 0x00
0xFFFF
CTSU Status Register
0xFF
CTSU Sensor Offset Register
CTSU Sensor Offset Register
CTSU Sensor Offset Register
CTSU Sensor Counter Register
CTSU Sensor Counter Register
CTSU Calibration Register
CTSU Calibration Register
CTSU Calibration Register
32
16
16
32
16
32
16
16
32
R/W 0x00000000
R/W 0x0000
R/W 0x0000
0xFFFFFFFF
0xFFFF
CTSUSO0
CTSUSO1
CTSUSCNT
CTSUSC
0xFFFF
R
R
0x00000000
0x0000
0xFFFFFFFF
0xFFFF
CTSUCALIB
CTSUDBGR0
CTSUDBGR1
CTSUSUCLKA
R/W 0x00000000
R/W 0x0000
0xFFFFFFFF
0xFFFF
R/W 0x0000
0xFFFF
CTSU Sensor Unit Clock Control Register
A
R/W 0x00000000
0xFFFFFFFF
CTSU
CTSU
—
—
—
—
—
—
CTSUSUCLK0
CTSUSUCLK1
CTSU Sensor Unit Clock Control Register
A
0x2C
0x2E
16
16
R/W 0x0000
R/W 0x0000
0xFFFF
0xFFFF
CTSU Sensor Unit Clock Control Register
A
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 106 of 110
RA2L1 Datasheet
Appendix 3. I/O Registers
Table 3.4
Register description (15 of 15)
Peripheral
name
Dim
Dim inc.
Dim
index
Register
name
Address
offset
Description
Size R/W Reset value
Reset mask
CTSU
CTSU
CTSU
—
—
—
—
—
—
—
—
—
CTSUSUCLKB
CTSUSUCLK2
CTSUSUCLK3
CTSUCFCCNT
CTSU Sensor Unit Clock Control Register
B
0x30
0x30
0x32
32
16
16
R/W 0x00000000
0xFFFFFFFF
CTSU Sensor Unit Clock Control Register
B
R/W 0x0000
0xFFFF
0xFFFF
CTSU Sensor Unit Clock Control Register
B
R/W 0x0000
CTSU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CTSU CFC Counter Register
0x34
0x34
0x00
0x00
0x02
0x08
0x09
0x0A
0x0C
0x0D
0x0E
32
16
16
16
16
8
R
R
0x00000000
0x0000
0xFFFFFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF
CTSU
CTSUCFCCNTL CTSU CFC Counter Register
AGT0-1
AGT0-1
AGT0-1
AGT0-1
AGT0-1
AGT0-1
AGT0-1
AGT0-1
AGT0-1
AGT
AGT Counter Register
R/W 0xFFFF
R/W 0xFFFF
R/W 0xFFFF
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
AGTCMB
AGTCMA
AGTCR
AGT Compare Match B Register
AGT Compare Match A Register
AGT Control Register
AGTMR1
AGTMR2
AGTIOC
AGTISR
AGTCMSR
AGT Mode Register 1
8
0xFF
AGT Mode Register 2
8
0xFF
AGT I/O Control Register
AGT Event Pin Select Register
8
0xFF
8
0xFF
AGT Compare Match Function Select
Register
8
0xFF
AGT0-1
ACMPLP
ACMPLP
ACMPLP
FLCN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AGTIOSEL
COMPMDR
COMPFIR
COMPOCR
DFLCTL
AGT Pin Select Register
0x00F
0x00
8
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
ACMPLP Mode Setting Register
ACMPLP Filter Control Register
ACMPLP Output Control Register
Data Flash Enable Register
8
0x01
8
0x02
8
0x0090
0x0228
8
FLCN
TSCDR
Temperature Sensor Calibration Data
Register
16
R
0x00
FLCN
FLCN
—
—
—
—
—
—
CTSUTRIMA
FLDWAITR
CTSU Trimming Register A
0x03A4
0x3FC4
32
8
R/W 0x00000000
R/W 0x00
0x00000000
0xFF
Memory Wait Cycle Control Register for
Data Flash
FLCN
—
—
—
PFBER
Prefetch Buffer Enable Register
0x3FC8
8
R/W 0x00
0xFF
Note:
Peripheral name = Name of peripheral
Dim = Number of elements in an array of registers
Dim inc. = Address increment between two simultaneous registers of a register array in the address map
Dim index = Sub string that replaces the %s placeholder within the register name
Register name = Name of register
Description = Register description
Address offset = Address of the register relative to the base address defined by the peripheral of the register
Size = Bit width of the register
Reset value = Default reset value of a register
Reset mask = Identifies which register bits have a defined reset value
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 107 of 110
RA2L1 Datasheet
Revision History
Revision History
Revision 1.00 — Aug 06, 2020
First edition, issued
R01DS0385EJ0100 Rev.1.00
Aug 06, 2020
Page 108 of 110
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of
these circuits, software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or
other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this
document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any
and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The intended applications for
each Renesas Electronics product depends on the product's quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home
electronic appliances; machine tools; personal electronic equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key
financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to
human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system;
undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims
any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is
inconsistent with any Renesas Electronics data sheet, user's manual or other Renesas Electronics document.
6. When using Renesas Electronics products, refer to the latest product information (data sheets, user's manuals, application notes, "General Notes for
Handling and Using Semiconductor Devices" in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by
Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas
Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such
specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific
characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability
product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products
are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury,
injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety
design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging
degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are
responsible for evaluating the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas
Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of
controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these
applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance
with applicable laws and regulations.
9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations
promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or
transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas
Electronics products.
(Note1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled
subsidiaries.
(Note2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
Corporate Headquarters
TOYOSU FORESIA, 3-2-24 Toyosu,
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www.renesas.com
Contact Information
For further information on a product, technology, the most up-to-date
version of a document, or your nearest sales office, please visit:
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© 2020 Renesas Electronics Corporation. All rights reserved.
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