R7FA4M1AB3CFM_技术文档

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Renesas RA4M1 Group

32

Datasheet

32-bit MCU

Renesas Advanced (RA) Family

Renesas RA4 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

Rev.1.00 Oct 2019

RA4M1 Group

Datasheet

High efficiency 48-MHz Arm^®Cortex^®-M4 core, 256-KB code flash memory, 32-KB SRAM, Segment LCD Controller,

Capacitive Touch Sensing Unit, USB 2.0 Full-Speed Module, 14-bit A/D Converter, 12-bit D/A Converter, security and

safety features

Features

■ Arm Cortex-M4 Core with Floating Point Unit (FPU)

 Armv7E-M architecture with DSP instruction set

 Maximum operating frequency: 48 MHz

■ System and Power Management

 Low power modes

 Realtime Clock (RTC) with calendar and Battery Backup support

 Event Link Controller (ELC)

 DMA Controller (DMAC) × 4

 Data Transfer Controller (DTC)

 Key Interrupt Function (KINT)

 Power-on reset

 Low Voltage Detection (LVD) with voltage settings

 Support for 4-GB address space

 Arm Memory Protection Unit (Arm MPU) with 8 regions

 Debug and Trace: ITM, DWT, FPB, TPIU, ETB

 CoreSight™ Debug Port: JTAG-DP and SW-DP

■ Memory

 256-KB code flash memory

 8-KB data flash memory (100,000 program/erase (P/E) cycles)

 32-KB SRAM

 Flash Cache (FCACHE)

 Memory Protection Unit (MPU)

 128-bit unique ID

■ Security and Encryption

 AES128/256

 GHASH

 True Random Number Generator (TRNG)

■ Human Machine Interface (HMI)

 Segment LCD Controller (SLCDC)

- Up to 38 segments × 4 commons

- Up to 34 segments × 8 commons

 Capacitive Touch Sensing Unit (CTSU)

■ Connectivity

 USB 2.0 Full-Speed Module (USBFS)

- On-chip transceiver with voltage regulator

- Compliant with USB Battery Charging Specification 1.2

 Serial Communications Interface (SCI) × 4

- UART

■ Multiple Clock Sources

 Main clock oscillator (MOSC)

- Simple IIC

(1 to 20 MHz when VCC = 2.4 to 5.5 V)

(1 to 8 MHz when VCC = 1.8 to 2.4 V)

(1 to 4 MHz when VCC = 1.6 to 1.8 V)

 Sub-clock oscillator (SOSC) (32.768 kHz)

 High-speed on-chip oscillator (HOCO)

(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)

(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)

(24, 32 MHz when VCC = 1.6 to 5.5 V)

 Middle-speed on-chip oscillator (MOCO) (8 MHz)

 Low-speed on-chip oscillator (LOCO) (32.768 kHz)

 IWDT-dedicated on-chip oscillator (15 kHz)

 Clock trim function for HOCO/MOCO/LOCO

 Clock out support

- Simple SPI

 Serial Peripheral Interface (SPI) × 2

 I²C bus interface (IIC) × 2

 Controller Area Network (CAN) module

 Serial Sound Interface Enhanced (SSIE)

■ Analog

 14-bit A/D Converter (ADC14)

 12-bit D/A Converter (DAC12)

 8-bit D/A Converter (DAC8) ×2 (for ACMPLP)

 Low-Power Analog Comparator (ACMPLP) × 2

 Operational Amplifier (OPAMP) × 4

 Temperature Sensor (TSN)

■ General Purpose I/O Ports

 Up to 84 input/output pins

- Up to 3 CMOS input

■ Timers

 General PWM Timer 32-Bit (GPT32) × 2

 General PWM Timer 16-Bit (GPT16) × 6

 Asynchronous General-Purpose Timer (AGT) × 2

 Watchdog Timer (WDT)

- Up to 81 CMOS input/output

- Up to 9 input/output 5-V tolerant

- Up to 2 high current (20 mA)

■ Safety

■ Operating Voltage

 VCC: 1.6 to 5.5 V

 Error Correction Code (ECC) in SRAM

 SRAM parity error check

 Flash area protection

■ Operating Temperature and Packages

 Ta = -40°C to +85°C

- 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)

 Ta = -40°C to +105°C

 ADC self-diagnosis function

 Clock Frequency Accuracy Measurement Circuit (CAC)

 Cyclic Redundancy Check (CRC) calculator

 Data Operation Circuit (DOC)

 Port Output Enable for GPT (POEG)

 Independent Watchdog Timer (IWDT)

 GPIO readback level detection

 Register write protection

- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)

- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)

- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)

- 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch)

- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)

- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)

 Main oscillator stop detection

 Illegal memory access

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RA4M1 Group

1. Overview

1.

Overview

®

The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set

of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

®

The MCU provides an optimal combination of low-power, high-performance Arm Cortex -M4 core running up to

48 MHz with the following features:



256-KB code flash memory

32-KB SRAM

Segment LCD Controller (SLCDC)

Capacitive Touch Sensing Unit (CTSU)

USB 2.0 Full-Speed Module (USBFS)

14-bit A/D Converter (ADC14)

12-bit D/A Converter (DAC12)

Security features.

1.1

Function Outline

Table 1.1

Feature

Arm core

Functional description

Arm Cortex-M4 core

 Maximum operating frequency: up to 48 MHz

 Arm Cortex-M4 core

- Revision: r0p1-01rel0

- Armv7E-M architecture profile

- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.

 Arm Memory Protection Unit (Arm MPU)

- Armv7 Protected Memory System Architecture

- 8 protected regions.

 SysTick timer

- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2

Memory

Feature

Functional description

Code flash memory

Data flash memory

Option-setting memory

Maximum 256-KB code flash memory. See section 44, Flash Memory in User’s Manual.

8-KB data flash memory. See section 44, Flash Memory in User’s Manual.

The option-setting memory determines the state of the MCU after a reset. See section 6,

Option-Setting Memory in User’s Manual.

SRAM

On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). An area in

SRAM0 provides error correction capability using ECC. See section 43, SRAM in User’s

Manual.

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RA4M1 Group

1. Overview

Table 1.3

Feature

System (1 of 2)

Functional description

Operating modes

Two operating modes:

 Single-chip mode

 SCI/USB boot mode.

See section 3, Operating Modes in User’s Manual.

Resets

14 resets:

 RES pin reset

 Power-on reset

 VBATT-selected voltage power-on reset

 Independent watchdog timer reset

 Watchdog timer reset

 Voltage monitor 0 reset

 Voltage monitor 1 reset

 Voltage monitor 2 reset

 SRAM parity error reset

 SRAM ECC error reset

 Bus master MPU error reset

 Bus slave MPU error reset

 CPU stack pointer error reset

 Software reset.

See section 5, Resets in User’s Manual.

Low Voltage Detection (LVD)

Clocks

Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and the

detection level can be selected using a software program. See section 7, Low Voltage

Detection (LVD) in User’s Manual.

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 PLL frequency synthesizer

 IWDT-dedicated on-chip oscillator

 Clock out support.

See section 8, Clock Generation Circuit in User’s Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock to be used as a

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.

When measurement is complete or the number of pulses within the time generated by the

measurement reference clock is not within the allowable range, an interrupt request is

generated.

See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual.

Interrupt Controller Unit (ICU)

Key Interrupt Function (KINT)

Low power modes

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module and DMAC module. The ICU also controls NMI interrupts. See section 13, Interrupt

Controller Unit (ICU) in User’s Manual.

A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting

a rising or falling edge to the key interrupt input pins. See section 20, Key Interrupt Function

(KINT) in User’s Manual.

Power consumption can be reduced in multiple ways, such as by setting clock dividers,

stopping modules, selecting power control mode in normal operation, and transitioning to low

power modes. See section 10, Low Power Modes in User’s Manual.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery powered

area includes RTC, SOSC, LOCO, wakeup control, backup memory, VBATT_R low voltage

detection, and switches between VCC and VBATT.

During normal operation, the battery powered area is powered by the main power supply,

which is the VCC pin. When a VCC voltage drop is detected, the power source is switched to

the dedicated battery backup power pin, the VBATT pin.

When the voltage rises again, the power source is switched from the VBATT pin to the VCC

pin. See section 11, Battery Backup Function in User’s Manual.

Register write protection

The register write protection function protects important registers from being overwritten

because of software errors. See section 12, Register Write Protection in User’s Manual.

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RA4M1 Group

1. Overview

Table 1.3

Feature

System (2 of 2)

Functional description

Memory Protection Unit (MPU)

Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided

for memory protection. See section 15, Memory Protection Unit (MPU) in User’s Manual.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A

refresh-permitted period can be set to refresh the counter and used as the condition to detect

when the system runs out of control. See section 25, Watchdog Timer (WDT) in User’s

Manual.

Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. It can be used to reset the MCU or to

generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates

with an independent, dedicated clock source, it is particularly useful in returning the MCU to a

known state as a fail-safe mechanism when the system runs out of control. The IWDT can be

triggered automatically on a reset, underflow, refresh error, or by a refresh of the count value in

the registers. See section 26, Independent Watchdog Timer (IWDT) in User’s Manual.

Table 1.4

Feature

Event link

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 18, Event Link Controller (ELC) in

User’s Manual.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request. See section 17, Data Transfer Controller (DTC) in User’s Manual.

DMA Controller (DMAC)

A 4-channel DMA Controller (DMAC) module is provided for transferring data without the CPU.

When a DMA transfer request is generated, the DMAC transfers data stored at the transfer

source address to the transfer destination address. See section 16, DMA Controller (DMAC) in

User’s Manual.

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RA4M1 Group

1. Overview

Table 1.6

Feature

Timers

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with 2 channels and a 16-bit timer with 6

channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or

the up- and down-counter. In addition, PWM waveforms can be generated for controlling

brushless DC motors. The GPT can also be used as a general-purpose timer. See section 22,

General PWM Timer (GPT) in User’s Manual.

Port Output Enable for GPT (POEG)

Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 21, Port Output Enable for GPT (POEG).

Asynchronous General Purpose

Timer (AGT)

The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse

output, external pulse width or period measurement, and counting of external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and they can be accessed with the AGT

register. See section 23, Asynchronous General Purpose Timer (AGT) in User’s Manual.

Realtime Clock (RTC)

The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count

mode, that are controlled by the register settings.

For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and

automatically adjusts dates for leap years.

For binary count mode, the RTC counts seconds and retains the information as a serial value.

Binary count mode can be used for calendars other than the Gregorian (Western) calendar.

See section 24, Realtime Clock (RTC) in User’s Manual.

Table 1.7

Feature

Communication interfaces (1 of 2)

Functional description

Serial Communications Interface

(SCI)

The Serial Communications Interface (SCI) is configurable to five asynchronous and

synchronous serial interfaces:

 Asynchronous interfaces (UART and asynchronous communications interface adapter

(ACIA))

 8-bit clock synchronous interface

 Simple IIC (master-only)

 Simple SPI

 Smart card interface.

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol.

SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and

the data transfer speed can be configured independently using an on-chip baud rate generator.

See section 28, Serial Communications Interface (SCI) in User’s Manual.

I²C Bus Interface (IIC)

The 3-channel I²C Bus Interface (IIC) module conforms with and provides a subset of the NXP

I²C bus (Inter-Integrated Circuit bus) interface functions. See section 29, I2C Bus Interface

(IIC) in User’s Manual.

Serial Peripheral Interface (SPI)

Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-

duplex synchronous serial communications with multiple processors and peripheral devices.

See section 31, Serial Peripheral Interface (SPI) in User’s Manual.

Serial Sound Interface Enhanced

(SSIE)

The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with

digital audio devices for transmitting PCM audio data over a serial bus with the MCU. The

SSIE supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or

master receiver, transmitter, or transceiver to suit various applications. The SSIE includes 8-

stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven

data reception and transmission. See section 33, Serial Sound Interface Enhanced (SSIE) in

User’s Manual.

Controller Area Network (CAN)

module

The Controller Area Network (CAN) module provides functionality to receive and transmit data

using a message-based protocol between multiple slaves and masters in electromagnetically

noisy applications.

The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports

up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox

and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are

supported. See section 30, Controller Area Network (CAN) Module in User’s Manual.

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RA4M1 Group

1. Overview

Table 1.7

Feature

Communication interfaces (2 of 2)

Functional description

USB 2.0 Full-Speed Module (USBFS) The USB 2.0 Full-Speed Module (USBFS) can operate as a host controller or device controller.

The module supports full-speed and low-speed (only for the host controller) transfer as defined

in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and

supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB

has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be

assigned any endpoint number based on the peripheral devices used for communication or

based on the user system. The MCU supports revision 1.2 of the Battery Charging

specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the

internal USB transceiver power supply at 3.3 V. See section 27, USB 2.0 Full-Speed Module

(USBFS) in User’s Manual.

Table 1.8

Feature

Analog

Functional description

14-bit A/D Converter (ADC14)

A 14-bit successive approximation A/D converter is provided. Up to 25 analog input channels

are selectable. Temperature sensor output and internal reference voltage are selectable for

conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion

making it possible to optimize the tradeoff between speed and resolution in generating a digital

value. See section 35, 14-Bit A/D Converter (ADC14) in User’s Manual.

12-Bit D/A Converter (DAC12)

The 12-Bit D/A Converter (DAC12) converts data and includes an output amplifier. See section

36, 12-Bit D/A Converter (DAC12) in User’s Manual.

8-Bit D/A Converter (DAC8)

for ACMPLP

The 8-Bit D/A Converter (DAC8) converts data and does not include an output amplifier

(DAC8). The DAC8 is used only as the reference voltage for ACMPLP. See section 40, 8-Bit D/

A Converter (DAC8) in User’s Manual.

Temperature Sensor (TSN)

The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for

reliable operation of the device. The sensor outputs a voltage directly proportional to the die

temperature, and the relationship between the die temperature and the output voltage is linear.

The output voltage is provided to the ADC14 for conversion and can be further used by the end

application. See section 37, Temperature Sensor (TSN) in User’s Manual.

Low-Power Analog Comparator

(ACMPLP)

The Low-Power Analog Comparator (ACMPLP) compares the reference input voltage and

analog input voltage. The comparison result can be read through software and also be output

externally. The reference voltage can be selected from an input to the CMPREFi(i = 0,1) pin,

an internal 8-bit D/A converter output, or the internal reference voltage (Vref) generated

internally in the MCU.

The ACMPLP response speed can be set before starting an operation. Setting the high-speed

mode decreases the response delay time, but increases current consumption. Setting the low-

speed mode increases the response delay time, but decreases current consumption. See

section 39, Low-Power Analog Comparator (ACMPLP) in User’s Manual.

Operational Amplifier (OPAMP)

The Operational Amplifier (OPAMP) amplifies small analog input voltages and outputs the

amplified voltages. A total of four differential operational amplifier units with two input pins and

one output pin are provided. See section 38, Operational Amplifier (OPAMP) in User’s Manual.

Table 1.9

Human machine interfaces

Feature

Functional description

Segment LCD Controller (SLCDC)

The Segment LCD Controller (SLCDC) provides the following functions:

 Waveform A or B selectable

 The LCD driver voltage generator can switch between an internal voltage boosting method,

a capacitor split method, and an external resistance division method

 Automatic output of segment and common signals based on automatic display data register

read

 The reference voltage generated when operating the voltage boost circuit can be selected in

16 steps (contrast adjustment)

 The LCD can be made to blink.

See section 45, Segment LCD Controller (SLCDC) in User’s Manual.

Capacitive Touch Sensing Unit

(CTSU)

The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the

touch sensor. Changes in the electrostatic capacitance are determined by software, which

enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode

surface of the touch sensor is usually enclosed within an electrical insulator so that fingers do

not come into direct contact with the electrode. See section 41, Capacitive Touch Sensing Unit

(CTSU) in User’s Manual.

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RA4M1 Group

1. Overview

Table 1.10

Feature

Data processing

Functional description

Cyclic Redundancy Check (CRC)

calculator

The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the

data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first

communication. Additionally, various CRC generation polynomials are available. The snoop

function allows monitoring reads from and writes to specific addresses. This function is useful

in applications that require CRC code to be generated automatically in certain events, such as

monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See

section 32, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.

Data Operation Circuit (DOC)

The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 42,

Data Operation Circuit (DOC) in User’s Manual.

Table 1.11

Feature

Security

Functional description

Secure Crypto Engine 5 (SCE5)

 Security algorithm

- Symmetric algorithm: AES.

 Other support features

- TRNG (True Random Number Generator)

- Hash-value generation: GHASH.

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RA4M1 Group

1. Overview

1.2

Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the

features.

Bus

Memory

Arm Cortex-M4

System

Clocks

256 KB Code Flash

DSP

FPU

POR/LVD

Reset

MPU

MOSC/SOSC

8 KB Data Flash

32 KB SRAM

MPU

(HOCO/

MOCO/

LOCO)

NVIC

Mode Control

Power Control

PLL

System Timer

DMA

DTC

CAC

Test and DBG Interface

ICU

Battery Backup

Register Write

Protection

DMAC × 4

KINT

Timers

Communication interfaces

Human machine interfaces

GPT32 × 2

CAN × 1

CTSU

SLCDC

SCI × 4

IIC × 2

GPT16 × 6

AGT × 2

RTC

USBFS

with Battery

Charging

revision 1.2

SPI × 2

SSIE × 1

WDT/IWDT

Event Link

ELC

Data processing

Analog

CRC

ADC14

DAC12

TSN

OPAMP × 4

ACMPLP × 2

DOC

DAC8

Security

SCE5

Figure 1.1

Block diagram

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RA4M1 Group

1. Overview

1.3

Part Numbering

Figure 1.2 shows the product part number information, including memory capacity, and package type. Table 1.12 shows

a product list.

# A A

R 7 F A 4 M 1 A B 3 C F P

0

Production identification code

Packaging, Terminal material (Pb-free)

#AA: Tray/Sn (Tin) only

#AC: Tray/others

Package type

FP: LQFP 100 pins

FM: LQFP 64 pins

FL: LQFP 48 pins

LJ: LGA 100 pins

NB: QFN 64 pins

NE: QFN 48 pins

NF: QFN 40 pins

Quality Grade

Operating temperature

2: -40^°C to 85^°C

3: -40^°C to 105^°C

Code flash memory size

B: 256 KB

Feature set

Group number

Series name

RA family

Flash memory

Renesas microcontroller

Figure 1.2

Part numbering scheme

Product list

Table 1.12

Operating

Code flash Data flash SRAM temperature

Product part number

R7FA4M1AB3CFP

R7FA4M1AB2CLJ

R7FA4M1AB3CFM

R7FA4M1AB3CNB

R7FA4M1AB3CFL

R7FA4M1AB3CNE

R7FA4M1AB3CNF

Orderable part number

R7FA4M1AB3CFP#AA0

R7FA4M1AB2CLJ#AC0

R7FA4M1AB3CFM#AA0

R7FA4M1AB3CNB#AC0

R7FA4M1AB3CFL#AA0

R7FA4M1AB3CNE#AC0

R7FA4M1AB3CNF#AC0

Package code

PLQP0100KB-B

PTLG0100JA-A

PLQP0064KB-C

PWQN0064LA-A

PLQP0048KB-B

PWQN0048KB-A

PWQN0040KC-A

256 KB

8 KB

32 KB

-40 to +105°C

-40 to +85°C

-40 to +105°C

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RA4M1 Group

1. Overview

1.4

Function Comparison

Table 1.13

Function comparison

R7FA4M1AB3CFM/

R7FA4M1AB3CNB

R7FA4M1AB3CFL/

R7FA4M1AB3CNE

Part numbers

Pin count

R7FA4M1AB3CFP

100

R7FA4M1AB2CLJ

R7FA4M1AB3CNF

100

64

LQFP/QFN

256 KB

8 KB

48

40

Package

LQFP

LGA

LQFP/QFN

QFN

Code flash memory

Data flash memory

SRAM

32 KB

Parity

16 KB

ECC

16 KB

System

CPU clock

48 MHz

512 bytes

Backup

registers

ICU

Yes

KINT

8

5

3

Event control

DMA

ELC

Yes

4

DTC

DMAC

External bus

GPT32

GPT16

AGT

Bus

No

2

Timers

6

2

4

2

No

RTC

Yes

4

WDT/IWDT

Communication SCI

IIC

2

SPI

2

1

SSIE

1

No

14

QSPI

No

1

SDHI

CAN

USBFS

ADC14

DAC12

DAC8

Yes

18

1

Analog

25

11

2

ACMPLP

OPAMP

TSN

2

1

4

3

1

No

Yes

HMI

SLCDC

4 com × 38 seg or 8 com × 34 seg

27

4 com × 21 seg or

8 com × 17 seg

No

CTSU

CRC

DOC

24

Yes

15

10

Data

processing

Yes

Security

SCE5

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 11 of 130

RA4M1 Group

1. Overview

1.5

Pin Functions

Table 1.14

Pin functions (1 of 4)

Function

Signal

I/O

Description

Power supply

VCC

Input

Power supply pin. Connect this pin to the system power supply. Connect it to

VSS through a 0.1-μF capacitor. The capacitor should be placed close to the

pin.

VCL

I/O

Connect this pin to the VSS pin through the smoothing capacitor used to

stabilize the internal power supply. Place the capacitor close to the pin.

VSS

Input

Ground pin. Connect to the system power supply (0 V).

Backup power supply pin

VBATT

XTAL

Input

Clock

Output

Input

Pins for a crystal resonator. An external clock signal can be input through the

EXTAL pin.

EXTAL

XCIN

Input

Input/output pins for the sub-clock oscillator. Connect a crystal resonator

between XCOUT and XCIN.

XCOUT

CLKOUT

MD

Output

Input

Clock output pin

Operating mode

control

Pins for setting the operating mode. The signal levels on these pins must not

be changed during operation mode transition on release from the reset state.

System control

RES

Input

Reset signal input pin. The MCU enters the reset state when this signal goes

low.

CAC

CACREF

NMI

Input

Measurement reference clock input pin

Non-maskable interrupt request pin

Maskable interrupt request pins

Interrupt

IRQ0 to IRQ12,

IRQ14, IRQ15

KINT

KR00 to KR07

Input

Key interrupt input pins.

A key interrupt (KINT) can be generated by inputting a falling edge to the key

interrupt input pins.

On-chip debug

TMS

I/O

On-chip emulator or boundary scan pins

TDI

Input

Output

I/O

TCK

TDO

SWDIO

SWCLK

SWO

Serial wire debug data input/output pin

Serial wire clock pin

Input

Output

I/O

Serial wire trace output pin

Battery Backup

GPT

VBATWIO0 to

VBATWIO2

Output wakeup signal for the VBATT wakeup control function.

External event input for the VBATT wakeup control function.

GTETRGA,

GTETRGB

Input

I/O

External trigger input pin

GTIOC0A to

GTIOC7A,

GTIOC0B to

GTIOC7B

Input capture, output capture, or PWM output pin

GTIU

Input

Hall sensor input pin U

GTIV

Input

Hall sensor input pin V

GTIW

Input

Hall sensor input pin W

GTOUUP

GTOULO

GTOVUP

GTOVLO

GTOWUP

GTOWLO

Output

3-phase PWM output for BLDC motor control (positive U phase)

3-phase PWM output for BLDC motor control (negative U phase)

3-phase PWM output for BLDC motor control (positive V phase)

3-phase PWM output for BLDC motor control (negative V phase)

3-phase PWM output for BLDC motor control (positive W phase)

3-phase PWM output for BLDC motor control (negative W phase)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 12 of 130

RA4M1 Group

1. Overview

Table 1.14

Pin functions (2 of 4)

Function

Signal

I/O

Description

AGT

AGTEE0, AGTEE1

AGTIO0, AGTIO1

AGTO0, AGTO1

AGTOA0, AGTOA1

AGTOB0, AGTOB1

RTCOUT

Input

I/O

External event input enable signals

External event input and pulse output pins

Pulse output pins

Output

Input

I/O

Output compare match A output pins

Output compare match B output pins

Output pin for 1-Hz/64-Hz clock

Time capture event input pins

Clock (clock synchronous mode) input/output pins

RTC

SCI

RTCIC0 to RTCIC2

SCK0 to SCK2,

SCK9

RXD0 to RXD2,

RXD9

Input

Output

I/O

Received data (asynchronous mode/clock synchronous mode) input pins

Transmitted data (asynchronous mode/clock synchronous mode) output pins

TXD0 to TXD2,

TXD9

CTS0_RTS0 to

CTS2_RTS2,

CTS9_RTS9

Input/output pins for controlling the start of transmission and reception

(asynchronous mode/clock synchronous mode), active-low

SCL0 to SCL2,

SCL9

I/O

I²C clock (simple IIC) input/output pins

SDA0 to SDA2,

SDA9

I²C data (simple IIC) input/output pins

SCK0 to SCK2,

SCK9

Clock (simple SPI) input/output pins

MISO0 to MISO2,

MISO9

Slave transmission of data (simple SPI) input/output pins

Master transmission of data (simple SPI) input/output pins

MOSI0 to MOSI2,

MOSI9

SS0 to SS2, SS9

SCL0, SCL1

Input

I/O

Slave-select input pins (simple SPI), active-low

Clock input/output pins

IIC

SDA0, SDA1

SSIBCK0

I/O

Data input/output pins

SSIE

I/O

SSIE serial bit clock pin

SSILRCK0/SSIFS0

SSITXD0

I/O

Word select pins

Output

Input

I/O

Serial data output pin

SSIRXD0

Serial data input pin

AUDIO_CLK

External clock pin for audio (input oversampling clock)

Clock input/output pin

SPI

RSPCKA, RSPCKB

MOSIA, MOSIB

MISOA, MISOB

SSLA0, SSLB0

I/O

Input/output pins for data output from the master

Input/output pins for data output from the slave

Input/output pins for slave selection

Output pins for slave selection

I/O

SSLA1, SSLA2,

SSLA3, SSLB1,

SSLB2, SSLB3

Output

CAN

CRX0

CTX0

Input

Receive data

Transmit data

Output

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 13 of 130

RA4M1 Group

1. Overview

Table 1.14

Pin functions (3 of 4)

Function

Signal

I/O

Description

USBFS

VSS_USB

VCC_USB_LDO

VCC_USB

Input

I/O

Ground pin

Power supply pin for USB LDO regulator

Input: USB transceiver power supply pin.

Output: USB LDO regulator output pin. This pin should be connected to an

external capacitor.

USB_DP

I/O

D+ I/O pin of the USB on-chip transceiver. This pin should be connected to the

D+ pin of the USB bus.

USB_DM

USB_VBUS

I/O

D- I/O pin of the USB on-chip transceiver. This pin should be connected to the

D- pin of the USB bus.

Input

USB cable connection monitor pin. This pin should be connected to VBUS of

the USB bus. The VBUS pin status (connected or disconnected) can be

detected when the USB module is operating as a device controller.

USB_EXICEN

USB_VBUSEN

Output

Input

Low power control signal for external power supply (OTG) chip

VBUS (5 V) supply enable signal for external power supply chip

USB_OVRCURA,

USB_OVRCURB

Connect the external overcurrent detection signals to these pins. Connect the

VBUS comparator signals to these pins when the OTG power supply chip is

connected.

USB_ID

Input

Connect the MicroAB connector ID input signal to this pin during operation in

OTG mode

Analog power

supply

AVCC0

AVSS0

VREFH0

VREFL0

VREFH

VREFL

Input

Analog voltage supply pin

Analog voltage supply ground pin

Analog reference voltage supply pin

Reference power supply ground pin

Analog reference voltage supply pin for D/A converter

Analog reference ground pin for D/A converter

Input pins for the analog signals to be processed by the A/D converter

ADC14

DAC12

AN000 to AN014,

AN016 to AN025

ADTRG0

Input

Input pins for the external trigger signals that start the A/D conversion, active-

low

DA0

Output

Output pins for the analog signals to be processed by the D/A converter

Comparator output pin

Comparator

output

VCOUT

ACMPLP

OPAMP

CMPREF0,

CMPREF1

Input

Reference voltage input pin

CMPIN0, CMPIN1

AMP0+ to AMP3+

AMP0- to AMP3-

AMP0O to AMP3O

Input

Output

Input

Analog voltage input pins

Analog voltage output pins

Capacitive touch detection pins (touch pins)

CTSU

TS00 to TS13,

TS17 to TS22,

TS27 to TS31,

TS34, TS35

TSCAP

-

Secondary power supply pin for the touch driver

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 14 of 130

RA4M1 Group

1. Overview

Table 1.14

Pin functions (4 of 4)

Signal

Function

I/O

Description

I/O ports

P000 to P008,

P010 to P015

I/O

General-purpose input/output pins

P100 to P115

P200

I/O

General-purpose input/output pins

General-purpose input pin

Input

I/O

P201 to P206,

P212, P213

General-purpose input/output pins

P214, P215

Input

I/O

General-purpose input pins

P300 to P307

P400 to P415

P500 to P505

General-purpose input/output pins

I/O

P600 to P603,

P608 to P610

I/O

P708

I/O

General-purpose input/output pins

P808, P809

I/O

General-purpose input/output pins

P914, P915

I/O

General-purpose input/output pins

SLCDC

VL1, VL2, VL3, VL4

CAPH, CAPL

COM0 to COM7

SEG00 to SEG37

I/O

Voltage pin for driving the LCD

I/O

Capacitor connection pin for the LCD controller/driver

Common signal output pins for the LCD controller/driver

Segment signal output pins for the LCD controller/driver

Output

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 15 of 130

RA4M1 Group

1. Overview

1.6

Pin Assignments

Figure 1.3 to Figure 1.6 show the pin assignments.

76

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P500

P300/TCK/SWCLK

P301

77

P501

78

P502

P302

79

P503

P303

80

P504

P809

81

P505

P808

82

VCC

P304

83

VSS

P305

84

P015

P306

85

P014

P307

86

P013/VREFL

P200

87

P012/VREFH

P201/MD

RES

R7FA4M1AB3CFP

88

89

90

91

92

93

94

95

96

97

98

99

100

AVCC0

AVSS0

P011/VREFL0

P010/VREFH0

P008

VCC

VSS

P202

P203

P007

P204

P006

P205

P005

P206

P004

VCC_USB_LDO

VCC_USB

P914/USB_DP

P915/USB_DM

VSS_USB

P003

P002

P001

P000

Figure 1.3

Pin assignment for 100-pin LQFP (top view)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 16 of 130

RA4M1 Group

1. Overview

R7FA4M1AB2CLJ

A

B

C

D

E

F

G

H

J

K

P212/

EXTAL

P215/

XCIN

10 P407

P409

P412

VCC

VCL

P403

P400

P000 10

P915/

9

P914/

USB_DM USB_DP

P213/

XTAL

P214/

XCOUT

P413

VSS

P411

P408

P203

RES

P306

VBATT

P404

P006

P505

P504

P503

P107

P106

P405

P003

P401

P004

P001

P002

9

8

7

6

5

4

3

2

1

VCC_

USB

VSS_ VCC_US

USB

8

7

6

5

4

3

2

1

P415

P414

P410

P113

P115

P609

P610

P708

P406

P402

P600

P601

P602

P603

B_LDO

P205

VSS

P204

P206

P007

P008

P005

P011/

VREFL0 VREFH0

P010/

VCC

P202

AVSS0

AVCC0

P100

P013/

VREFL VREFH

P012/

P200 P201/MD P307

P305

P809

P304

P808

P015

VSS

P014

VCC

P502

P303 P110/TDI P111

P103

P300/

TCK/

SWCLK

P302

P301

P114

P101

P501

P108/

TMS/

P109/

TDO/

SWO

P112

C

P608

D

VCC

E

VSS

F

P105

G

P104

H

P102

J

P500

K

SWDIO

A

B

Figure 1.4

Pin assignment for 100-pin LGA (upper perspective view)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 17 of 130

RA4M1 Group

1. Overview

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P500

P501

P300/TCK/SWCLK

P301

P502

P302

P015

P303

P014

P304

P013/VREFL

P012/VREFH

AVCC0

P200

P201/MD

RES

R7FA4M1AB3CFM

AVSS0

P204

P011/VREFL0

P010/VREFH0

P004

P205

P206

VCC_USB_LDO

VCC_USB

P914/USB_DP

P915/USB_DM

VSS_USB

P003

P002

P001

P000

Figure 1.5

Pin assignment for 64-pin LQFP (top view)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 18 of 130

RA4M1 Group

1. Overview

P500

P501

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32 P300/TCK/SWCLK

31

P301

30

P502

P015

P302

29

P303

28

P014

P304

27

P013/VREFL

P012/VREFH

AVCC0

P200

26

P201/MD

25

RES

R7FA4M1AB3CNB

24

AVSS0

P011/VREFL0

P204

23

P205

22

P010/VREFH0

P004

P206

21

VCC_USB_LDO

20

P003

VCC_USB

19

P002

P001

P914/USB_DP

18 P915/USB_DM

17

P000

VSS_USB

Figure 1.6

Pin assignment for 64-pin QFN (upper perspective view)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 19 of 130

RA4M1 Group

1. Overview

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

P500

P015

P300/TCK/SWCLK

P301

P014

P302

P013/VREFL

P012/VREFH

AVCC0

P200

P201/MD

RES

R7FA4M1AB3CFL

AVSS0

P206

P011/VREFL0

P010/VREFH0

P002

VCC_USB_LDO

VCC_USB

P914/USB_DP

P915/USB_DM

VSS_USB

P001

P000

Figure 1.7

Pin assignment for 48-pin LQFP (top view)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 20 of 130

RA4M1 Group

1. Overview

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

P500

P015

P014

P300/TCK/SWCLK

P301

P302

P013/VREFL

P012/VREFH

AVCC0

P200

P201/MD

RES

R7FA4M1AB3CNE

AVSS0

P011/VREFL0

P010/VREFH0

P002

P206

VCC_USB_LDO

VCC_USB

P914/USB_DP

P001

14 P915/USB_DM

13

P000

VSS_USB

Figure 1.8

Pin assignment for 48-pin QFN (top view)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 21 of 130

RA4M1 Group

1. Overview

31

32

33

34

35

36

37

38

39

40

20

19

18

17

16

15

14

13

12

11

P015

P300/TCK/SWCLK

P014

P013/VREFL

P012/VREFH

AVCC0

P301

P200

P201/MD

RES

R7FA4M1AB3CNF

AVSS0

VCC_USB_LDO

VCC_USB

P914/USB_DP

P915/USB_DM

P011/VREFL0

P010/VREFH0

P001

P000

VSS_USB

Figure 1.9

Pin assignment for 40-pin QFN (top view)

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 22 of 130

RA4M1 Group

1. Overview

1.7

Pin Lists

Pin number

Timers

Communication interfaces

Analogs

HMI

1

2

J10

J9

1

2

1

2

1

CACREF

IRQ0

IRQ5

P400

P401

AGTIO1

GTIOC6A

SCK0 SCL0

SCK1

AUDIO_CL

K

SEG04 TS20

SEG05 TS19

GTETRGA GTIOC6B

CTX0

CTS0_ SDA0

RTS0/

SS0

TXD1/

MOSI1/

SDA1

3

4

F6

3

VBATWIO0 IRQ4

VBATWIO1

P402

P403

AGTIO0/

AGTIO1

RTCIC0 CRX0

RXD1/

MISO1/

SCL1

SEG06 TS18

TS17

H10

AGTIO0/

AGTIO1

GTIOC3A RTCIC1

CTS1_

RTS1/

SS1

SSIBCK0

5

6

7

8

9

G8

H9

F7

VBATWIO2

P404

P405

P406

GTIOC3B RTCIC2

GTIOC1A

SSILRCK0/

SSIFS0

SSITXD0

GTIOC1B

SSIRXD0

G9

G10

4

5

6

7

8

9

4

5

6

7

8

9

2

3

4

5

6

7

2

3

4

5

6

7

1

2

3

4

5

6

VBATT

VCL

10 F10

11 F9

12 D9

13 E9

XCIN

XCOUT

VSS

P215

P214

XTAL

EXTAL

VCC

IRQ2

IRQ3

P213

P212

GTETRGA GTIOC0A

TXD1/

MOSI1/

SDA1

14 E10 10 10

8

9

8

9

7

8

AGTEE1 GTETRGB GTIOC0B

RXD1/

MISO1/

SCL1

15 D10 11 11

16 F8

P708

RXD1/

MISO1/

SCL1

SSLA3

17 E8

18 E7

19 C9

IRQ8

IRQ9

P415

P414

P413

GTIOC0A

GTIOC0B

SSLA2

SSLA1

SSLA0

CTS0_

RTS0/

SS0

20 C10

P412

P411

SCK0

RSPCKA

MOSIA

21 D8 12 12

IRQ4

IRQ5

AGTOA1 GTOVUP GTIOC6A

AGTOB1 GTOVLO GTIOC6B

TXD0/

MOSI0/

SDA0

SEG07 TS07

SEG08 TS06

22 E6 13 13

P410

RXD0/

MISO0/

SCL0

MISOA

23 B10 14 14 10 10

24 D7 15 15 11 11

IRQ6

IRQ7

P409

P408

GTOWUP GTIOC5A

GTOWLO GTIOC5B

USB_EXI TXD9/

SEG09 TS05

SEG10 TS04

CEN

MOSI9/

SDA9

9

USB_ID CTS1_ SCL0

RTS1/

SS1

RXD9/

MISO9/

SCL9

25 A10 16 16 12 12 10

P407

AGTIO0

RTCOUT USB_VB CTS0_ SDA0 SSLB3

ADTRG0

SEG11 TS03

US

RTS0/

SS0

26 B8 17 17 13 13 11 VSS_USB

27 A9 18 18 14 14 12

P915

P914

USB_DM

USB_DP

28 B9 19 19 15 15 13

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Oct 8, 2019

Page 23 of 130

RA4M1 Group

1. Overview

Pin number

Timers

Communication interfaces

Analogs

HMI

29 A8 20 20 16 16 14 VCC_USB

30 C8 21 21 17 17 15 VCC_USB_

LDO

31 C7 22 22 18 18

IRQ0

IRQ1

P206

P205

GTIU

USB_VB RXD0/ SDA1 SSLB1

SEG12 TS01

USEN

MISO0/

SCL0

32 A7 23 23

CLKOUT

CACREF

AGTO1 GTIV

GTIOC4A

USB_OV TXD0/ SCL1

SSLB0

SEG13 TSCAP

RCURA MOSI0/

SDA0

CTS9_

RTS9/

SS9

33 B7 24 24

P204

P203

AGTIO1 GTIW

GTIOC4B

GTIOC5A

USB_OV SCK0 SCL0

RCURB SCK9

RSPCKB

MOSIB

SEG14 TS00

34 D6

CTS2_

RTS2/

SS2

SEG15 TSCAP

TXD9/

MOSI9/

SDA9

35 C6

P202

GTIOC5B

SCK2

RXD9/

MISO9/

SCL9

MISOB

SEG16

36 A6

37 B6

VSS

VCC

38 D5 25 25 19 19 16 RES

39 B5 26 26 20 20 17 MD

40 A5 27 27 21 21 18

41 C5

P201

P200

P307

P306

P305

P304

P808

P809

P303

P302

NMI

SEG17

42 D4

SEG18

43 A4

IRQ8

IRQ9

SEG19

44 B4 28 28

45 C4

GTIOC7A

GTIOC7B

SEG20 TS11

SEG21

46 A3

SEG22

47 B3 29 29

48 B2 30 30 22 22

SEG03/ TS02

COM7

IRQ5

IRQ6

GTOUUP GTIOC4A

TXD2/

MOSI2/

SDA2

SSLB3

SSLB2

SEG02/ TS08

COM6

49 C2 31 31 23 23 19

P301

AGTIO0 GTOULO GTIOC4B

RXD2/

MISO2/

SCL2

SEG01/ TS09

COM5

CTS9_

RTS9/

SS9

50 A2 32 32 24 24 20 TCK/

P300

P108

GTOUUP GTIOC0A

GTOULO GTIOC0B

SSLB1

SSLB0

SWCLK

51 A1 33 33 25 25 21 TMS/

CTS9_

RTS9/

SS9

SWDIO

52 B1 34 34 26 26 22 TDO/SWO/

CLKOUT

P109

GTOVUP GTIOC1A

CTX0

CRX0

SCK1

TXD9/

MOSI9/

SDA9

MOSIB

SEG23 TS10

53 C3 35 35 27 27 23 TDI

IRQ3

P110

GTOVLO GTIOC1B

CTS2_

RTS2/

SS2

MISOB

VCOUT

SEG24

RXD9/

MISO9/

SCL9

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Oct 8, 2019

Page 24 of 130

RA4M1 Group

1. Overview

Pin number

Timers

Communication interfaces

Analogs

HMI

54 D3 36 36 28 28 24

IRQ4

P111

P112

GTIOC3A

GTIOC3B

SCK2

SCK9

RSPCKB

CAPH TS12

55 C1 37 37 29 29 25

TXD2/

MOSI2/

SDA2

SCK1

SSLB0

SSIBCK0

CAPL TSCAP

56 E5 38 38

P113

P114

P115

P608

P609

P610

GTIOC2A

GTIOC2B

GTIOC4A

GTIOC4B

GTIOC5A

GTIOC5B

SSILRCK0/

SSIFS0

SEG00/ TS27

COM4

57 D2

SSIRXD0

SEG25 TS29

SEG26 TS35

SEG27

58 E4

SSITXD0

59 D1

60 E3

SEG28

61 E2

SEG29

62 E1 39 39 30 30 26 VCC

63 F1 40 40 31 31 27 VSS

64 F2

P603

P602

P601

GTIOC7A

GTIOC7B

GTIOC6A

CTS9_

RTS9/

SS9

SEG30

SEG31

SEG32

65 F3

66 F4

TXD9/

MOSI9/

SDA9

RXD9/

MISO9/

SCL9

67 F5

P600

P107

P106

GTIOC6B

GTIOC0A

SCK9

SEG33

68 G3 41 41

69 G2 42 42

70 G1 43 43

71 H1 44 44 32 32

KR07

KR06

COM3

GTIOC0B

SSLA3

SSLA2

SSLA1

COM2

KR05/ P105

IRQ0

GTETRGA GTIOC1A

GTETRGB GTIOC1B

COM1 TS34

COM0 TS13

KR04/ P104

IRQ1

RXD0/

MISO0/

SCL0

72 H3 45 45 33 33

KR03

KR02

P103

P102

GTOWUP GTIOC2A

CTX0

CRX0

CTS0_

RTS0/

SS0

SSLA0

AN019

CMPREF1 VL4

73 J1 46 46 34 34 28

AGTO0 GTOWLO GTIOC2B

AGTEE0 GTETRGB GTIOC5A

AGTIO0 GTETRGA GTIOC5B

SCK0

TXD2/

MOSI2/

SDA2

RSPCKA

AN020/

ADTRG0

CMPIN1

VL3

74 H2 47 47 35 35 29

KR01/ P101

IRQ1

TXD0/ SDA1 MOSIA

AN021

AN022

CMPREF0 VL2

MOSI0/

SDA0

CTS1_

RTS1/

SS1

75 H4 48 48 36 36 30

KR00/ P100

IRQ2

RXD0/ SCL1

MISO0/

MISOA

CMPIN0

VL1

SCL0

SCK1

76 K1 49 49 37 37

77 J2 50 50

P500

AGTOA0 GTIU

AGTOB0 GTIV

GTIOC2A

GTIOC2B

USB_VB

USEN

AN016

AN017

CMPREF1 SEG34

IRQ11 P501

USB_OV TXD1/

RCURA MOSI1/

SDA1

CMPIN1

SEG35

78 K2 51 51

IRQ12 P502

GTIW

GTIOC3B

USB_OV RXD1/

RCURB MISO1/

SCL1

AN018

CMPREF0 SEG36

79 G4

80 G5

P503

P504

USB_EXI SCK1

CEN

AN023

AN024

CMPIN0

SEG37

USB_ID CTS1_

RTS1/

SS1

81 G6

IRQ14 P505

AN025

82 K3

VCC

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Page 25 of 130

RA4M1 Group

1. Overview

Pin number

Timers

Communication interfaces

Analogs

HMI

83 J3

VSS

84 J4 52 52 38 38 31

85 K4 53 53 39 39 32

IRQ7

P015

P014

P013

P012

AN010

AN009

AN008

AN007

TS28

DA0

86 J5 54 54 40 40 33 VREFL

87 K5 55 55 41 41 34 VREFH

88 H5 56 56 42 42 35 AVCC0

89 H6 57 57 43 43 36 AVSS0

90 J6 58 58 44 44 37 VREFL0

91 K6 59 59 45 45 38 VREFH0

92 J7

AMP1+

AMP1-

IRQ15 P011

P010

AN006

AN005

AN014

AN013

AN012

AN011

AN004

AN003

AN002

AN001

AN000

AMP2+

AMP2-

TS31

TS30

P008

93 H7

P007

AMP3O

AMP3-

AMP3+

AMP2O

AMP1O

AMP0O

AMP0-

AMP0+

94 G7

P006

95 K7

IRQ10 P005

96 J8 60 60

IRQ3

P004

P003

P002

P001

P000

97 H8 61 61

98 K8 62 62 46 46

99 K9 63 63 47 47 39

100 K10 64 64 48 48 40

IRQ2

IRQ7

IRQ6

TS22

TS21

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Page 26 of 130

RA4M1 Group

2. Electrical Characteristics

2.

Electrical Characteristics

Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:

VCC*¹= AVCC0 = VCC_USB*²= VCC_USB_LDO*²= 1.6 to 5.5V, VREFH = VREFH0 = 1.6 to AVCC0, VBATT =

1.6 to 3.6V, VSS = AVSS0 = VREFL = VREFL0 = VSS_USB = 0V, T = T

.

a

opr

Note 1. The typical condition is set to VCC = 3.3V.

Note 2. When USBFS is not used.

Figure 2.1 shows the timing conditions.

For example P100

C

V_OH= VCC × 0.7, V_OL= VCC × 0.3

_IH= VCC × 0.7, V_IL= VCC × 0.3

V

Load capacitance C = 30 pF

Figure 2.1

Input or output timing measurement conditions

The recommended measurement conditions for the timing specification of each peripheral provided are for the best

peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.

Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function

pin is mixed, the AC specification of each function is not guaranteed.

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Page 27 of 130

RA4M1 Group

2. Electrical Characteristics

2.1

Absolute Maximum Ratings

Table 2.1

Parameter

Absolute maximum ratings

Symbol

VCC

Value

Unit

Power supply voltage

Input voltage

-0.5 to +6.5

V

5 V-tolerant ports*¹

V_in

-0.3 to +6.5

P000 to P008, P010 to P015 V_in

-0.3 to AVCC0 + 0.3

-0.3 to VCC + 0.3

-0.3 to +6.5

Others

V_in

Reference power supply voltage

VREFH0

VREFH

VBATT

VBATT power supply voltage

Analog power supply voltage

USB power supply voltage

-0.5 to +6.5

AVCC0

-0.5 to +6.5

VCC_USB

VCC_USB_LDO

V_AN

-0.5 to +6.5

Analog input voltage

LCD voltage

When AN000 to AN014 are

used

-0.3 to AVCC0 + 0.3

When AN016 to AN025 are

used

-0.3 to VCC + 0.3

V

VL1 voltage

VL2 voltage

VL3 voltage

VL4 voltage

V_L1

V_L2

V_L3

V_L4

T_opr

-0.3 to +2.8

-0.3 to +6.5

-40 to +105

-40 to +85

V

Operating temperature*^2,*^3,*⁴

Storage temperature

°C

T_stg

-55 to +125

°C

Caution:

Permanent damage to the MCU may result if absolute maximum ratings are exceeded.

To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics

between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins,

between the VREFH0 and VREFL0 pins, and between the VREFH and VREFL pins. Place capacitors of about 0.1 μF

as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect

capacitors as stabilization capacitance.

Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. The capacitor must be placed close to the pin.

Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that

results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in

the device at this time might cause degradation of internal elements.

Note 1. Ports P205, P206, P400 to P404, P407, P408 are 5 V tolerant.

Note 2. See section 2.2.1, Tj/Ta Definition.

Note 3. Contact a Renesas Electronics sales office for information on derating operation under T_a= +85°C to +105°C. Derating is the

systematic reduction of load for improved reliability.

Note 4. The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part

Numbering.

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Page 28 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.2

Recommended operating conditions

Parameter

Symbol

Value

Min

Typ

Max

Unit

Power supply voltages

VCC^{*1, *2}

When USBFS is not

used

1.6

-

5.5

V

When USBFS is used VCC_USB

USB Regulator

Disable

-

3.6

5.5

V

When USBFS is used VCC_USB

USB Regulator

Enable

_LDO

VSS

-

0

-

V

USB power supply voltages

VCC_USB

When USBFS is not

used

VCC

When USBFS is used 3.0

USB Regulator

Disable

3.3

3.6

V

(Input)

VCC_USB_LDO

When USBFS is not

used

-

VCC

-

V

When USBFS is used

USB Regulator

Disable

When USBFS is used 3.8

USB Regulator

Enable

-

5.5

V

VSS_USB

VBATT

-

0

-

V

VBATT power supply voltage

Analog power supply voltages

When the battery

backup function is not

used

-

VCC

When the battery

backup function is

used

1.6

-

3.6

V

AVCC0^{*1, *2}

AVSS0

1.6

-

5.5

V

0

-

VREFH0

VREFL0

VREFH

When used as

ADC14 Reference

1.6

-

AVCC0

0

-

When used as

DAC12 Reference

1.6

-

AVCC0

-

VREFL

0

Note 1. Use AVCC0 and VCC under the following conditions:

AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V.

AVCC0 = VCC when VCC < 2.2 V or AVCC0 < 2.2 V.

Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time, or power the VCC pin first and then the AVCC0

pin.

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Page 29 of 130

RA4M1 Group

2. Electrical Characteristics

2.2

DC Characteristics

2.2.1

Tj/T Definition

a

Table 2.3

DC Characteristics

Conditions: Products with operating temperature (T_a) -40 to +105°C

Parameter

Symbol

Typ

Max

125

Unit

Test conditions

Permissible junction temperature

Tj

-

°C

High-speed mode

Middle-speed mode

Low-voltage mode

Low-speed mode

Subosc-speed mode

105*¹

Note:

Make sure that Tj = T_a+ θja × total power consumption (W),

where total power consumption = (VCC - V_OH) × ΣI_OH+ V_OL× ΣI_OL+ I_CCmax × VCC.

Note 1. The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part

Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of T_jis +105°C, otherwise, it

is +125°C.

2.2.2

I/O V , V

IH IL

Table 2.4

I/O V_IH, V_IL(1)

Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 5.5V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V

Parameter

Symbol

V_IH

Min

Typ

Max

Unit

Test conditions

Schmitt trigger IIC*¹(except for SMBus)

input voltage

VCC × 0.7

-

5.8

V

-

V_IL

-

VCC × 0.3

ΔV_T

V_IH

VCC × 0.05

-

RES, NMI

Other peripheral input pins

excluding IIC

VCC × 0.8

-

V_IL

-

VCC × 0.2

ΔV_T

V_IH

VCC × 0.1

-

Input voltage

(except for

Schmitt trigger

input pin)

IIC (SMBus)*²

2.2

-

VCC = 3.6 to 5.5 V

V_IH

2.0

-

VCC = 2.7 to 3.6 V

-

V_IL

-

0.8

5 V-tolerant ports*³

P914, P915

V_IH

VCC × 0.8

5.8

V_IL

-

VCC × 0.2

VCC_USB + 0.3

VCC_USB × 0.2

-

V_IH

VCC_USB × 0.8

V_IL

-

P000 to P008, P010 to P015 V_IH

V_IL

AVCC0 × 0.8

-

AVCC0 × 0.2

-

EXTAL

V_IH

V_IL

VCC × 0.8

-

Input ports pins except for

P000 to P008, P010 to

P015, P914, P915

VCC × 0.2

When V_BATT

power supply is

selected

P402, P403, P404

V_IH

V_IL

V_BATT× 0.8

-

V_BATT+ 0.3

V_BATT× 0.2

-

ΔV_T

V_BATT× 0.05

Note 1. P205, P206, P400, P401, P407, P408 (total 6 pins).

Note 2. P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins).

Note 3. P205, P206, P400 to P404, P407, P408 (total 9 pins).

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Page 30 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.5

I/O V_IH, V_IL(2)

Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V

Test

Parameter

Symbol

V_IH

Min

Typ

Max

Unit conditions

Schmitt trigger

input voltage

RES, NMI

Peripheral input pins

VCC × 0.8

-

V

-

V_IL

-

VCC × 0.2

ΔV_T

V_IH

VCC × 0.01

-

Input voltage

(except for

Schmitt trigger

input pin)

5 V-tolerant ports*¹

P914, P915

VCC × 0.8

5.8

V_IL

-

VCC × 0.2

VCC_USB + 0.3

VCC_USB × 0.2

-

V_IH

VCC_USB × 0.8

V_IL

-

P000 to P008, P010 to P015 V_IH

V_IL

AVCC0 × 0.8

-

AVCC0 × 0.2

-

EXTAL

V_IH

V_IL

VCC × 0.8

-

Input ports pins except for

P000 to P008, P010 to P015,

P914, P915

VCC × 0.2

When V_BATT

power supply is

selected

P402, P403, P404

V_IH

V_IL

V_BATT× 0.8

-

V_BATT+ 0.3

V_BATT× 0.2

-

ΔV_T

V_BATT× 0.01

Note 1. P205, P206, P400 to P404, P407, P408 (total 9 pins)

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Page 31 of 130

RA4M1 Group

2. Electrical Characteristics

2.2.3

I/O I , I

OH OL

Table 2.6

I/O I_OH, I_OL(1 of 2)

Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V

Parameter

Symbol

I_OH

I_OL

Min

Typ

Max

-4.0

4.0

Unit

mA

Permissible output current

(average value per pin)

Ports P212, P213

Port P408

-

1

Low drive*

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

I_OH

I_OL

-4.0

4.0

Middle drive for IIC

Fast-mode*

VCC = 2.7 to 5.5 V

-8.0

8.0

4

2

Middle drive*

VCC = 3.0 to 5.5 V

-20.0

20.0

-4.0

4.0

Port P409

Low drive*¹

Middle drive*²

VCC = 2.7 to 3.0 V

-8.0

8.0

Middle drive*²

VCC = 3.0 to 5.5 V

-20.0

20.0

-4.0

4.0

Ports P100 to P115,

Low drive*¹

Middle drive*²

-

P201 to P204, P300 to P307,

P500 to P503, P600 to P603,

P608 to P610, P808, P809

(total 41 pins)

-4.0

8.0

Ports P914, P915

Other output pin*³

-4.0

4.0

Low drive*¹

Middle drive*²

-4.0

4.0

-8.0

8.0

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Page 32 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.6

I/O I_OH, I_OL(2 of 2)

Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V

Parameter

Symbol

I_OH

Min

-

Typ

Max

-4.0

4.0

Unit

mA

Permissible output current

(Max value per pin)

Ports P212, P213

Port P408

-

I_OL

-

1

Low drive*

I_OH

-

-4.0

4.0

I_OL

-

Middle drive for IIC

Fast-mode*

VCC = 2.7 to 5.5 V

I_OH

-

-8.0

8.0

4

I_OL

-

2

Middle drive*

VCC = 3.0 to 5.5 V

I_OH

-

-20.0

20.0

-4.0

4.0

I_OL

-

Port P409

Low drive*¹

I_OH

-

I_OL

-

Middle drive*²

VCC = 2.7 to 3.0 V

I_OH

-

-8.0

8.0

I_OL

-

Middle drive*²

VCC = 3.0 to 5.5 V

I_OH

-

-20.0

20.0

-4.0

4.0

I_OL

-

Low drive*¹

I_OH

-

Ports P100 to P115,

P201 to P204, P300 to P307,

P500 to P503, P600 to P603,

P608 to P610, P808, P809

(total 41 pins)

I_OL

-

Middle drive*²

-

I_OH

-

-4.0

8.0

I_OL

-

Ports P914, P915

Other output pin*³

I_OH

-

-4.0

4.0

I_OL

-

Low drive*¹

I_OH

-

-4.0

4.0

I_OL

-

Middle drive*²

I_OH

-

-8.0

8.0

I_OL

-

Permissible output current

(max value total pins)

Total of ports P000 to P008, P010 to P015

Ports P914, P915

ΣI_{OH (max)}

ΣI_{OL (max)}

ΣI_{OH (max)}

ΣI_{OL (min)}

ΣI_{OH (max)}

ΣI_{OL (max)}

-

-30

-

30

-

-2.0

2.0

-

Total of all output pin*⁵

-

-60

-

60

Caution:

To protect the reliability of the MCU, the output current values should not exceed the values in this table. The

average output current indicates the average value of current measured during 100 μs.

Note 1. This is the value when low driving ability is selected with the Port Drive Capability bit in PmnPFS register.

Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register.

Note 3. Except for ports P200, P214, P215, which are input ports.

Note 4. This is the value when middle driving ability for IIC Fast-mode is selected with the Port Drive Capability bit in PmnPFS register.

Note 5. For details on the permissible output current used with CTSU, see section 2.11, CTSU Characteristics.

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RA4M1 Group

2. Electrical Characteristics

2.2.4

I/O V , V , and Other Characteristics

OH OL

Table 2.7

I/O V_OH, V_OL(1)

Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 4.0 to 5.5 V

Parameter

Symbol

V_OL

Min

Typ

Max

0.4

0.6

-

Unit

Test conditions

I_OL= 3.0 mA

I_OL= 6.0 mA

I_OH= -20 mA

I_OL= 20 mA

Output voltage IIC*¹

-

V

V_OL*^2,*⁵

V_OH

V_OL

-

3

Ports P408, P409*^2,

*

VCC - 1.0

-

1.0

-

Ports P000 to P008, Low drive

P010 to P015

V_OH

V_OL

AVCC0 - 0.8

I_OH= -2.0 mA

I_OL= 2.0 mA

I_OH= -4.0 mA

I_OL= 4.0 mA

I_OH= -2.0 mA

I_OL= 2.0 mA

I_OH= -2.0 mA

I_OL= 2.0 mA

I_OH= -4.0 mA

I_OL= 4.0 mA

-

0.8

-

Middle drive

V_OH

V_OL

AVCC0 - 0.8

-

0.8

-

Ports P914, P915

V_OH

V_OL

VCC_USB - 0.8

-

0.8

-

Other output pins*⁴Low drive

V_OH

V_OL

VCC - 0.8

-

0.8

-

Middle

drive*⁶

V_OH

V_OL

VCC - 0.8

-

0.8

Note 1. P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins).

Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register.

Note 3. Based on characterization data, not tested in production.

Note 4. Except for ports P200, P214, P215, which are input ports.

Note 5. This is the value when middle driving ability for IIC is selected in the Port Drive Capability bit in PmnPFS register for P408.

Note 6. Except for P212, P213.

Table 2.8

I/O V_OH, V_OL(2)

Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 2.7 to 4.0 V

Parameter

Symbol

Min

Typ

Max

0.4

0.6

-

Unit

Test conditions

I_OL= 3.0 mA

Output voltage IIC*¹

V_OL

-

V

2, 5

V

* *

-

I_OL= 6.0 mA

OL

3

Ports P408, P409*^2,

*

V_OH

VCC - 1.0

I_OH= -20 mA

VCC = 3.3 V

V_OL

-

1.0

I_OL= 20 mA

VCC = 3.3 V

Ports P000 to P008, Low drive

P010 to P015

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

AVCC0 - 0.5

-

I_OH= -1.0 mA

I_OL= 1.0 mA

I_OH= -2.0 mA

I_OL= 2.0 mA

I_OH= -1.0 mA

I_OL= 1.0 mA

I_OH= -1.0 mA

I_OL= 1.0 mA

I_OH= -2.0 mA

I_OL= 2.0 mA

-

0.5

-

Middle drive

AVCC0 - 0.5

-

0.5

-

Ports P914, P915

VCC_USB - 0.5

-

0.5

-

Other output pins*⁴

Low drive

VCC - 0.5

-

0.5

-

Middle

drive*⁶

VCC - 0.5

-

0.5

Note 1. P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins).

Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register.

Note 3. Based on characterization data, not tested in production.

Note 4. Except for ports P200, P214, P215, which are input ports.

Note 5. This is the value when middle driving ability for IIC is selected in the Port Drive Capability bit in PmnPFS register for P408.

Note 6. Except for P212, P213.

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RA4M1 Group

2. Electrical Characteristics

Table 2.9

I/O V_OH, V_OL(3)

Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 2.7 V

Parameter

Symbol Min

Typ

Max

-

Unit

Test conditions

I_OH= -0.5 mA

I_OL= 0.5 mA

I_OH= -1.0 mA

I_OL= 1.0 mA

I_OH= -0.5 mA

I_OL= 0.5 mA

I_OH= -0.5 mA

I_OL= 0.5 mA

I_OH= -1.0 mA

I_OL= 1.0 mA

Output voltage Ports P000 to P015

Low drive

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

AVCC0 - 0.3

-

V

-

0.3

-

Middle drive

AVCC0 - 0.3

-

0.3

-

Ports P914, P915

Other output pins*¹

VCC_USB - 0.3

-

0.3

-

Low drive

VCC - 0.3

-

0.3

-

Middle

drive*²

VCC - 0.3

-

0.3

Note 1. Except for ports P200, P214, P215, which are input ports.

Note 2. Except for P212, P213.

Table 2.10

I/O other characteristics

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

| I_in

Min

Typ

Max

Unit

Test conditions

Input leakage current

RES, P200, P214, P215

|

-

1.0

μA

V_in= 0 V

V_in= VCC

Three-state leakage

current (off state)

5 V-tolerant ports

| I_TSI

|

-

μA

V_in= 0 V

V_in= 5.8 V

Other ports

V_in= 0 V

(except for ports P200, P214,

P215 and 5 V tolerant)

V_in= VCC

Input pull-up resistor

Input capacitance

All ports

(except for ports P200, P214,

P215, P914, P915)

R_U

C_in

10

-

20

-

50

30

15

kΩ

pF

V_in= 0 V

P914, P915,

P100 to P103, P111, P112,

P200

V_in= 0 V

f = 1 MHz

T_a= 25°C

Other input pins

-

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RA4M1 Group

2. Electrical Characteristics

2.2.5

I/O Pin Output Characteristics of Low Drive Capacity

I_OH/I_OLvs V_OH/V_OL

60

50

40

30

VCC = 5.5 V

VCC = 3.3 V

VCC = 2.7 V

20

10

0

VCC = 1.6 V

-10

VCC = 2.7 V

-20

VCC = 3.3 V

-30

-40

-50

VCC = 5.5 V

-60

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.2

V_OH/V_OLand I_OH/I_OLVoltage Characteristics at T_a= 25°C when low drive output is selected

(reference data)

I

_OH/I_OLvs V_OH/V_OL

3

2

Ta = -40°C

Ta = 25°C

Ta = 105°C

1

0

-1

-2

-3

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH/V_OL[V]

Figure 2.3

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 1.6 V when low drive output is selected

(reference data)

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RA4M1 Group

2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

20

15

10

5

Ta = -40°C

Ta = 25°C

Ta = 105°C

0

-5

Ta = 105°C

Ta = 25°C

-10

-15

-20

Ta = -40°C

0

0.5

1

1.5

2

2.5

3

V_OH/V_OL[V]

Figure 2.4

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 2.7 V when low drive output is selected

(reference data)

I_OH/I_OLvs V_OH/V_OL

30

20

Ta = -40°C

Ta = 25°C

Ta = 105°C

10

0

-10

-20

-30

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

0.5

1

1.5

V_OH/V_OL[V]

2

2.5

3

3.5

Figure 2.5

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 3.3 V when low drive output is selected

(reference data)

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RA4M1 Group

2. Electrical Characteristics

I

_OH/I_OLvs V_OH/V_OL

60

40

20

0

Ta = -40°C

Ta = 25°C

Ta = 105°C

-20

-40

-60

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.6

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 5.5 V when low drive output is selected

(reference data)

2.2.6

I/O Pin Output Characteristics of Middle Drive Capacity

I_OH/I_OLvs V_OH/V_OL

140

120

100

80

VCC = 5.5 V

60

VCC = 3.3 V

VCC = 2.7 V

40

20

VCC = 1.6 V

0

VCC = 1.6 V

-20

-40

-60

-80

-100

-120

-140

VCC = 2.7 V

VCC = 3.3 V

VCC = 5.5 V

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.7

V_OH/V_OLand I_OH/I_OLvoltage characteristics at T_a= 25°C when middle drive output is selected

(reference data)

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RA4M1 Group

2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

6

4

Ta = -40°C

Ta = 25°C

Ta = 105°C

2

0

-2

-4

-6

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH/V_OL[V]

Figure 2.8

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 1.6 V when middle drive output is

selected (reference data)

I_OH/I_OLvs V_OH/V_OL

40

30

Ta = -40°C

Ta = 25°C

Ta = 105°C

20

10

0

-10

-20

-30

-40

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

0.5

1

1.5

2

2.5

3

V_OH/V_OL[V]

Figure 2.9

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 2.7 V when middle drive output is

selected (reference data)

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RA4M1 Group

2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

60

40

Ta = -40°C

Ta = 25°C

Ta = 105°C

20

0

-20

-40

-60

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

0.5

1

1.5

V_OH/V_OL[V]

2

2.5

3

3.5

Figure 2.10

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 3.3 V when middle drive output is

selected (reference data)

I_OH/I_OLvs V_OH/V_OL

140

120

Ta = -40°C

Ta = 25°C

100

Ta = 105°C

80

60

40

20

0

-20

-40

-60

-80

Ta = 105°C

-100

Ta = 25°C

-120

Ta = -40°C

-140

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.11

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 5.5 V when middle drive output is

selected (reference data)

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RA4M1 Group

2. Electrical Characteristics

2.2.7

P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity

I_OH/I_OLvs V_OH/V_OL

200

180

160

140

120

100

80

VCC = 5.5 V

VCC = 3.3 V

VCC = 2.7 V

60

40

20

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

VCC = 2.7 V

VCC = 3.3 V

VCC = 5.5 V

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.12

V_OH/V_OLand I_OH/I_OLvoltage characteristics at Ta = 25°C when middle drive output is selected

(reference data)

I_OH/I_OLvs V_OH/V_OL

60

40

Ta = -40°C

Ta = 25°C

Ta = 105°C

20

0

-20

-40

-60

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

0.5

1

1.5

2

2.5

3

V_OH/V_OL[V]

Figure 2.13

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 2.7 V when middle drive output is

selected (reference data)

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RA4M1 Group

2. Electrical Characteristics

I_OH/I_OLvs V_OH/V_OL

100

80

60

40

20

0

Ta = -40°C

Ta = 25°C

Ta = 105°C

-20

-40

-60

Ta = 105°C

Ta = 25°C

-80 Ta = -40°C

-100

0

0.5

1

1.5

V_OH/V_OL[V]

2

2.5

3

3.5

Figure 2.14

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 3.3 V when middle drive output is

selected (reference data)

I_OH/I_OLvs V_OH/V_OL

220

Ta = -40°C

180

140

100

60

Ta = 25°C

Ta = 105°C

20

-20

-60

-100

-140

-180

-220

Ta = 105°C

Ta = 25°C

Ta = -40°C

0

1

2

3

4

5

6

V_OH/V_OL[V]

Figure 2.15

V_OH/V_OLand I_OH/I_OLtemperature characteristics at VCC = 5.5 V when middle drive output is

selected (reference data)

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2. Electrical Characteristics

2.2.8

IIC I/O Pin Output Characteristics

I_OLvs V_OL

120

110

100

90

VCC = 5.5 V (Middle drive)

80

70

60

50

VCC = 3.3V (Middle drive)

VCC = 5.5V (Low drive)

40

30

20

10

0

VCC = 2.7V (Middle drive)

VCC = 3.3V (Low drive)

VCC = 2.7V (Low drive)

0

1

2

3

4

5

6

V_OL[V]

Figure 2.16

V_OH/V_OLand I_OH/I_OLvoltage characteristics at Ta = 25°C

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RA4M1 Group

2.2.9

2. Electrical Characteristics

Operating and Standby Current

Table 2.11

Operating and standby current (1) (1 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Test

conditions

10

Parameter

Symbol Typ*

I_CC

Max

Unit

7

Supply

High-speed

mode*²

Normal mode

All peripheral clock

ICLK = 48 MHz

ICLK = 32 MHz

ICLK = 16 MHz

ICLK = 8 MHz

ICLK = 48 MHz

ICLK = 32 MHz

ICLK = 16 MHz

ICLK = 8 MHz

ICLK = 48 MHz

ICLK = 32 MHz

ICLK = 16 MHz

ICLK = 8 MHz

ICLK = 48 MHz

8.3

5.8

3.5

2.2

16.4

11.3

6.4

4.0

18.5

13.8

7.7

4.5

-

mA

*

current*¹

disabled, while (1) code

-

executing from flash*⁵

-

All peripheral clock

-

disabled, CoreMark code

-

executing from flash*⁵

-

9

All peripheral clock

-

*

enabled, while (1) code

8

executing from flash*⁵

-

*

-

9

All peripheral clock

enabled, code executing

from SRAM*⁵

50.0

*

7

Sleep mode

All peripheral clock

disabled*⁵

ICLK = 48 MHz

ICLK = 32 MHz

ICLK = 16 MHz

ICLK = 8 MHz

ICLK = 48 MHz

ICLK = 32 MHz

ICLK = 16 MHz

ICLK = 8 MHz

3.3

2.4

1.8

1.4

13.4

10.4

6.0

3.6

2.5

2.0

0.9

4.7

3.7

1.2

5.7

4.3

1.5

-

*

-

9

All peripheral clock

enabled*⁵

-

*

8

-

*

-

Increase during BGO operation*⁶

-

7

Middle-speed Normal mode

mode*²

All peripheral clock

ICLK = 12 MHz

ICLK = 8 MHz

ICLK = 1 MHz

ICLK = 12 MHz

ICLK = 8 MHz

ICLK = 1 MHz

ICLK = 12 MHz

ICLK = 8 MHz

ICLK = 1 MHz

ICLK = 12 MHz

I_CC

-

mA

*

disabled, while (1) code

-

executing from flash*⁵

-

All peripheral clock

-

disabled, CoreMark code

-

executing from flash*⁵

-

8

All peripheral clock

-

*

enabled, while (1) code

-

executing from flash*⁵

-

All peripheral clock

enabled, code executing

from SRAM*⁵

20.0

7

Sleep mode

All peripheral clock

disabled*⁵

ICLK = 12 MHz

ICLK = 8 MHz

ICLK = 1 MHz

ICLK = 12 MHz

ICLK = 8 MHz

ICLK = 1 MHz

1.2

0.8

4.4

3.4

1.4

2.5

-

*

8

All peripheral clock

enabled*⁵

*

Increase during BGO operation*⁶

-

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RA4M1 Group

2. Electrical Characteristics

Table 2.11

Operating and standby current (1) (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Test

conditions

10

Parameter

Symbol Typ*

Max

Unit

7

Supply

Low-speed

mode*³

Normal mode

ICLK = 1 MHz

I_CC

0.4

-

mA

All peripheral clock

*

current*¹

disabled, while (1) code

executing from flash*⁵

All peripheral clock

ICLK = 1 MHz

0.6

1.0

-

disabled, CoreMark code

executing from flash*⁵

8

All peripheral clock

-

*

enabled, while (1) code

executing from flash*⁵

All peripheral clock

enabled, code executing

from SRAM*⁵

2.2

7

Sleep mode

All peripheral clock

disabled*⁵

ICLK = 1 MHz

ICLK = 4 MHz

0.3

0.9

1.7

-

*

8

All peripheral clock

enabled*⁵

*

7

Low-voltage

mode*³

Normal mode

All peripheral clock

I_CC

mA

*

disabled, while (1) code

executing from flash*⁵

All peripheral clock

ICLK = 4 MHz

2.8

3.0

-

disabled, CoreMark code

executing from flash*⁵

8

All peripheral clock

-

*

enabled, while (1) code

executing from flash*⁵

All peripheral clock

enabled, code executing

from SRAM*⁵

8.0

7

Sleep mode

All peripheral clock

disabled*⁵

ICLK = 4 MHz

1.3

2.5

8.5

-

*

8

All peripheral clock

enabled*⁵

ICLK = 4 MHz

*

8

Subosc-

speed

Normal mode

All peripheral clock

ICLK = 32.768 kHz

I_CC

μA

*

disabled, while (1) code

mode*⁴

executing from flash*⁵

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 32.768 kHz

14.9

-

*5

All peripheral clock

83.0

enabled, code executing

*5

from SRAM

Sleep mode

All peripheral clock

disabled*⁵

ICLK = 32.768 kHz

5.0

-

All peripheral clock

enabled*⁵

11.4

Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up

MOSs are in the off state.

Note 2. The clock source is HOCO.

Note 3. The clock source is MOCO.

Note 4. The clock source is the sub-clock oscillator.

Note 5. This does not include BGO operation.

Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.

Note 7. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64.

Note 8. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are the same frequency as that of ICLK.

Note 9. FCLK and PCLKB are set to divided by 2 and PCLKA, PCLKC, and PCLKD are the same frequency as that of ICLK.

Note 10. VCC = 3.3 V.

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RA4M1 Group

2. Electrical Characteristics

4 0

3 5

3 0

2 5

2 0

1 5

1 0

5



* 2

T a

=

1 0 5 C , IC L K

=

4 8 M H z

3 2 M H z



* 2

T a

=

1 0 5 C , IC L K



* 1

2 5 C , IC L K

= 4 8 M H z



* 2

* 1

* 2

T a

=

1 0 5

2 5

C

,

IC L K

=

1 6 M H z

3 2 M H z



IC L K

C



1 0 5

C

,

IC L K

=

8

M H z



IC L K

=

1 6 M H z * 1

* 2

M H z

M H z * 1

2 5

C



1 0 5 C , IC L K

=

4

8

4



,

IC L K

2 5

C

0

1 .5

2 .0

2 .5

3 .0

3 .5

4 .0

4 .5

5 .0

5 .5

6 .0

V C C (V )



T a

=

2 5 C , IC L K

=

4 8 M H z * 1

3 2 M H z *1

1 6 M H z * 1

T a

=

1 0 5 C , IC L K

=

4 8 M H z *2

3 2 M H z *2

1 6 M H z *2

2 5C



,

IC L K

T a

1 0 5 C , IC L K



1 0 5 C , IC L K



2 5

C

,



,

8

4

M H z * 1

1 0 5

C

,

IC L K

8

M H z *2



,

1 0 5

,

=

4

Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual

measurements of the sample cores during product evaluation.

Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the

actual measurements for the upper limit samples during product evaluation.

Figure 2.17

Voltage dependency in high-speed operating mode (reference data)

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RA4M1 Group

2. Electrical Characteristics

12

10

8



*2

Ta = 105 C, ICLK = 12 MHz



*2

, ICLK = 8 MHz

Ta = 105 C

6



*1

*2

*1

Ta = 25 C, ICLK = 12 MHz



Ta = 105 C, ICLK = 4 MHz



, ICLK = 8 MHz

Ta = 25 C

4



, ICLK = 4 MHz*1

Ta = 25 C



*2

, ICLK = 1 MHz

Ta = 105 C

2

*1



Ta = 25 C, ICLK = 1 MHz

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VCC (V)

Ta = 25C, ICLK = 12 MHz *1

Ta = 105C, ICLK = 12 MHz *2



Ta = 105 C, ICLK = 8 MHz *2

Ta = 25 C, ICLK = 8 MHz *1



Ta = 105 C

Ta = 25 C, ICLK = 4 MHz *1

, ICLK = 4 MHz *2



Ta = 25 C, ICLK = 1 MHz *1

Ta = 105 C, ICLK = 1 MHz *2

Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual

measurements of the sample cores during product evaluation.

Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the

actual measurements for the upper limit samples during product evaluation.

Figure 2.18

Voltage dependency in middle-speed operating mode (reference data)

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2. Electrical Characteristics

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2



*2

*1

Ta = 105 C, ICLK = 1 MHz



Ta = 25 C, ICLK = 1 MHz

0.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VCC (V)



Ta = 25 C, ICLK = 1 MHz *1

Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the

actual measurements of the sample cores during product evaluation.

Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the

actual measurements for the upper limit samples during product evaluation.

Figure 2.19

Voltage dependency in Low-speed mode (reference data)

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RA4M1 Group

2. Electrical Characteristics

6

5

4

3

2

1



*2

*1

Ta = 105 C, ICLK = 4 MHz



, ICLK = 4 MHz

Ta = 25 C



*2

Ta = 105 C, ICLK = 1 MHz

*1



Ta = 25 C, ICLK = 1 MHz

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VCC (V)

*1



, ICLK = 4 MHz *2

Ta = 105 C

Ta = 25 C

, ICLK = 4 MHz

, ICLK = 1 MHz ^*1



*2



Ta = 25 C

, ICLK = 1 MHz

Ta = 105 C

Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the

actual measurements of the sample cores during product evaluation.

Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the

actual measurements for the upper limit samples during product evaluation.

Figure 2.20

Voltage dependency in low-voltage mode (reference data)

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RA4M1 Group

2. Electrical Characteristics

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0



*2

Ta = 105 C, ICLK = 32 MHz



*1

Ta = 25 C, ICLK = 32 MHz

0.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VCC (V)

*1

*2



, ICLK = 32 MHz

Ta = 25 C

Ta = 105 C

, ICLK = 32 MHz

Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the

actual measurements of the sample cores during product evaluation.

Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the

actual measurements for the upper limit samples during product evaluation.

Figure 2.21

Voltage dependency in Subosc-speed mode (reference data)

Operating and standby current (2)

Table 2.12

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol Typ*⁴

Max

4.5

7.1

20.2

53.7

-

Unit

Test conditions

Supply

current*¹

Software Standby T_a= 25°C

I_CC

0.8

1.3

3.5

8.7

0.5

μA

-

mode*²

T_a= 55°C

T_a= 85°C

T_a= 105°C

Increment for RTC operation with

low-speed on-chip oscillator*³

-

Increment for RTC operation with

sub-clock oscillator*³

0.4

1.2

-

SOMCR.SODRV[1:0] are 11b

(Low power mode 3)

SOMCR.SODRV[1:0] are 00b

(Normal mode)

Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up

MOSs are in the off state.

Note 2. The IWDT and LVD are not operating.

Note 3. Includes the current of sub-oscillation circuit or low-speed on-chip oscillator.

Note 4. VCC = 3.3 V.

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RA4M1 Group

100

2. Electrical Characteristics

10

1

0.1

-40

-20

0

20

40

Ta ( C)

60

80

100



Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.22

Table 2.13

Temperature dependency in Software Standby mode all SRAM (reference data)

Operating and standby current (3)

Conditions: VCC = AVCC0 = 0V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0V

Parameter

Symbol Typ

I_CC

Max

Unit

Test conditions

Supply

current*¹

RTC operation

when VCC is off

T_a= 25°C

T_a= 55°C

T_a= 85°C

T_a= 105°C

T_a= 25°C

T_a= 55°C

T_a= 85°C

T_a= 105°C

T_a= 25°C

T_a= 55°C

T_a= 85°C

T_a= 105°C

T_a= 25°C

T_a= 55°C

T_a= 85°C

T_a= 105°C

0.8

0.9

1.0

1.1

0.9

1.0

1.1

1.2

1.5

1.7

2.0

2.2

1.6

1.8

2.1

2.3

-

μA

VBATT = 2.0 V

SOMCR.SORDRV[1:0] = 11b

(Low power mode 3)

VBATT = 3.3 V

SOMCR.SORDRV[1:0] = 11b

(Low power mode 3)

VBATT = 2.0 V

SOMCR.SORDRV[1:0] = 00b

(Normal mode)

VBATT = 3.3 V

SOMCR.SORDRV[1:0] = 00b

(Normal mode)

Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up

MOSs are in the off state.

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RA4M1 Group

2. Electrical Characteristics

10

Normal drive capacity*1

1

Low drive capacity*1

0

-40

-20

0

20

40

60

80

100

120



Ta ( C)

Low drive capacity*1

Normal drive capacity*1

Note 1. Average value of the tested middle sample during product evaluatio.n

Figure 2.23

Temperature dependency of RTC operation with VCC off (reference data)

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RA4M1 Group

2. Electrical Characteristics

Table 2.14

Operating and standby current (4)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VREFH0 = 2.7 V to AVCC0

Test

Parameter

Symbol Min Typ

Max

3.0

1.0

0.8

1.0

150

60

Unit

mA

μA

nA

μA

conditions

Analog power

supply current

During A/D conversion (at high-speed conversion)

During A/D conversion (at low-power conversion)

During D/A conversion (per channel)*¹

Waiting for A/D and D/A conversion (all units)*⁶

During A/D conversion

I_AVCC

-

0.4

-

Reference

power supply

current

I_REFH0

-

Waiting for A/D conversion (all units)

During D/A conversion

-

I_REFH

50

-

100

-

Waiting for D/A conversion (all units)

Temperature sensor

I_TNS

75

15

10

2

Low-Power

Analog

Comparator

operating

current

Window mode

I_CMPLP

-

Comparator High-speed mode

Comparator Low-speed mode

Comparator Low-speed mode using DAC8

-

820

2.5

4.5

6.5

8.5

140

280

420

560

0.34

-

Operational

Amplifier

operating

current

Low power mode

1 unit operating

2 units operating

3 units operating

4 units operating

1 unit operating

2 units operating

3 units operating

4 units operating

I_AMP

4.0

8.0

11.0

14.0

220

410

600

780

-

High-speed mode

5

LCD operating

current

External resistance division method

f = f = 128 Hz, 1/3 bias, and 4-time slice

LCD

I_LCD1

I_LCD2

I_LCD3

*

SUB

Internal voltage boosting method (VLCD.VLCD = 04)

= f = 128 Hz, 1/3 bias, and 4-time slice

-

0.92

0.19

-

μA

mA

-

f

LCD

SUB

Capacitor split method

= f = 128 Hz, 1/3 bias, and 4-time slice

f

LCD

SUB

2

USB operating

current

During USB communication operation under the

following settings and conditions:

I_USBH

*

4.3 (VCC)

0.9 (VCC_USB)*⁴

 Host controller operation is set to full-speed mode

Bulk OUT transfer (64 bytes) × 1,

bulk IN transfer (64 bytes) × 1

 Connect peripheral devices via a 1-meter USB

cable from the USB port.

2

During USB communication operation under the

following settings and conditions:

 Device controller operation is set to full-speed mode

Bulk OUT transfer (64 bytes) × 1,

bulk IN transfer (64 bytes) × 1

 Connect the host device via a 1-meter USB cable

from the USB port.

I_USBF

*

-

3.6 (VCC)

-

mA

-

1.1 (VCC_USB)*⁴

3

During suspended state under the following setting

and conditions:

I_SUSP

*

0.35 (VCC)

170 (VCC_USB)*⁴

μA

 Device controller operation is set to full-speed mode

(pull up the USB_DP pin)

 Software standby mode

 Connect the host device via a 1-meter USB cable

from the USB port.

Note 1. The reference power supply current is included in the power supply current value for D/A conversion.

Note 2. Current consumed only by the USBFS.

Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition

to the current consumed by the MCU during the suspended state.

Note 4. When VCC = VCC_USB = 3.3 V.

Note 5. Current flowing only to the LCD controller. Not including the current that flows through the LCD panel.

Note 6. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC140 module stop bit) is in the module-stop

state.

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2.2.10

2. Electrical Characteristics

VCC Rise and Fall Gradient and Ripple Frequency

Table 2.15

Rise and fall gradient characteristics

Conditions: VCC = AVCC0 = 0 to 5.5 V

Parameter

Symbol Min

Typ

Max

Unit

Test conditions

Power-on VCC

rising gradient

Voltage monitor 0 reset disabled at startup (normal SrVCC 0.02

startup)

-

2

ms/V

-

Voltage monitor 0 reset enabled at startup*¹

SCI/USB boot mode*²

0.02

-

2

Note 1. When OFS1.LVDAS = 0.

Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.

Table 2.16

Rising and falling gradient and ripple frequency characteristics

Conditions: VCC = AVCC0 = VCC_USB = 1.6 to 5.5 V

The ripple voltage must meet the allowable ripple frequency f_r(VCC)within the range between the VCC upper limit (5.5 V) and lower limit

(1.6 V).

When VCC change exceeds VCC ±10%, the allowable voltage change rising/falling gradient dt/dVCC must be met.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Allowable ripple frequency

f_{r (VCC)}

-

10

kHz

Figure 2.24

V_{r (VCC)}≤ VCC × 0.2

-

1

MHz

ms/V

Figure 2.24

V_{r (VCC)}≤ VCC × 0.08

-

10

-

Figure 2.24

V_{r (VCC)}≤ VCC × 0.06

Allowable voltage change rising and

falling gradient

dt/dVCC

1.0

When VCC change exceeds VCC ±10%

1/f_r(VCC)

VCC

V_r(VCC)

Figure 2.24

Ripple waveform

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2. Electrical Characteristics

2.3

AC Characteristics

2.3.1

Frequency

Table 2.17

Operation frequency value in high-speed operating mode

Conditions: VCC = AVCC0 = 2.4 to 5.5 V

Parameter

Symbol

Min

Typ

Max*⁵

48

Unit

Operation

frequency

System clock (ICLK)*⁴

2.7 to 5.5 V

2.4 to 2.7 V

2.7 to 5.5 V

2.4 to 2.7 V

2.7 to 5.5 V

2.4 to 2.7 V

2.7 to 5.5 V

2.4 to 2.7 V

2.7 to 5.5 V

2.4 to 2.7 V

2.7 to 5.5 V

2.4 to 2.7 V

f

0.032768

-

MHz

0.032768

16

Flash interface clock (FCLK)*^1,

*

0.032768

32

2,

4

0.032768

16

Peripheral module clock (PCLKA)*⁴

Peripheral module clock (PCLKB)*⁴

Peripheral module clock (PCLKC)*^3,

Peripheral module clock (PCLKD)*⁴

-

48

16

32

16

4

*

64

16

64

16

Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer

frequency such as 1.5 MHz cannot be set.

Note 2. The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency

accuracy of the clock source.

Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in

use.

Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, and FCLK.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed

operation, see Table 2.22, Clock timing.

Table 2.18

Operation frequency value in Middle-speed mode

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max*⁵

12

8

Unit

Operation

frequency

System clock (ICLK)*⁴

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

f

0.032768

-

MHz

0.032768

Flash interface clock (FCLK)*^1,

*

0.032768

12

8

2,

4

0.032768

Peripheral module clock (PCLKA)*⁴

Peripheral module clock (PCLKB)*⁴

Peripheral module clock (PCLKC)*^3,

Peripheral module clock (PCLKD)*⁴

-

12

8

12

8

4

*

12

8

12

8

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2. Electrical Characteristics

Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer

frequency such as 1.5 MHz cannot be set.

Note 2. The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency

accuracy of the clock source.

Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use.

Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed

operation, see Table 2.22, Clock timing.

Table 2.19

Operation frequency value in Low-speed mode

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max*⁴

Unit

Operation

frequency

System clock (ICLK)*³

1.8 to 5.5 V

f

0.032768

-

1

MHz

Flash interface clock (FCLK)*^1,

*

0.032768

3

Peripheral module clock (PCLKA)*³

Peripheral module clock (PCLKB)*³

Peripheral module clock (PCLKC)*^2,

Peripheral module clock (PCLKD)*³

-

3

*

Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory.

Note 2. The lower-limit frequency of PCLKC is 1 MHz when the A/D converter is in use.

Note 3. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK.

Note 4. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed

operation, see Table 2.22, Clock timing.

Table 2.20

Operation frequency value in low-voltage mode

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Typ

Max*⁵

Unit

Operation

frequency

System clock (ICLK)*⁴

1.6 to 5.5 V

f

0.032768

-

4

MHz

Flash interface clock (FCLK)*^1,

*

0.032768

2,

4

Peripheral module clock (PCLKA)*⁴

Peripheral module clock (PCLKB)*⁴

Peripheral module clock (PCLKC)*^3,

Peripheral module clock (PCLKD)*⁴

-

4

*

Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer

frequency such as 1.5 MHz cannot be set.

Note 2. The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency

accuracy of the clock source.

Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-Bit A/D converter is in

use.

Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed

operation, see Table 2.22, Clock timing.

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2. Electrical Characteristics

Table 2.21

Operation frequency value in Subosc-speed mode

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Operation

frequency

System clock (ICLK)*³

1.8 to 5.5 V

f

27.8528 32.768

37.6832

kHz

Flash interface clock (FCLK)*^1,

*

3

Peripheral module clock (PCLKA)*³

Peripheral module clock (PCLKB)*³

Peripheral module clock (PCLKC)*^2,

Peripheral module clock (PCLKD)*³

-

3

*

Note 1. Programming and erasing the flash memory is not possible.

Note 2. The 14-bit A/D converter cannot be used.

Note 3. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK.

2.3.2

Clock Timing

Table 2.22

Clock timing (1 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

ns

Test conditions

EXTAL external clock input cycle time

EXTAL external clock input high pulse width

EXTAL external clock input low pulse width

EXTAL external clock rising time

t

50

-

Figure 2.25

Xcyc

t

20

-

ns

XH

t

20

-

ns

XL

t

-

5

ns

Xr

EXTAL external clock falling time

t

-

5

ns

Xf

EXTAL external clock input wait time*¹

EXTAL external clock input frequency

t

0.3

-

μs

-

EXWT

f_EXTAL

-

20

MHz

2.4 ≤ VCC ≤ 5.5

-

8

1.8 ≤ VCC < 2.4

-

1

1.6 ≤ VCC < 1.8

Main clock oscillator oscillation frequency

f

1

-

20

MHz

2.4 ≤ VCC ≤ 5.5

MAIN

1

-

8

1.8 ≤ VCC < 2.4

1

-

4

1.6 ≤ VCC < 1.8

Main clock oscillation stabilization wait time (crystal)*⁹

LOCO clock oscillation frequency

t_MAINOSCWT

-

-*⁹

ms

-

f

27.8528

32.768

37.6832

100

17.25

9.2

kHz

μs

-

LOCO

LOCO clock oscillation stabilization time

IWDT-dedicated clock oscillation frequency

MOCO clock oscillation frequency

t

-

Figure 2.26

LOCO

f

12.75

6.8

-

15

8

-

kHz

MHz

μs

-

ILOCO

f_MOCO

t_MOCO

MOCO clock oscillation stabilization time

1

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RA4M1 Group

2. Electrical Characteristics

Table 2.22

Clock timing (2 of 2)

Parameter

Symbol

f

Min

Typ

Max

Unit

Test conditions

HOCO clock oscillation frequency

23.64

24

24.36

MHz

T_a= -40 to -20°C

1.8 ≤ VCC ≤ 5.5

HOCO24

22.68

23.76

23.52

31.52

30.24

31.68

31.36

47.28

47.52

47.04

63.04

63.36

62.72

-

24

32

48

64

-

25.32

24.24

24.48

32.48

33.76

32.32

32.64

48.72

48.48

48.96

64.96

64.64

65.28

37.1

T_a= -40 to 85°C

1.6 ≤ VCC < 1.8

T_a= -20 to 85°C

1.8 ≤ VCC ≤ 5.5

T_a= 85 to 105°C

2.4 ≤ VCC ≤ 5.5

f

HOCO32

T_a= -40 to -20°C

1.8 ≤ VCC ≤ 5.5

T_a= -40 to 85°C

1.6 ≤ VCC < 1.8

T_a= -20 to 85°C

1.8 ≤ VCC ≤ 5.5

T_a= 85 to 105°C

2.4 ≤ VCC ≤ 5.5

4

f

*

T_a= -40 to -20°C

1.8 ≤ VCC ≤ 5.5

HOCO48

T_a= -20 to 85°C

1.8 ≤ VCC ≤ 5.5

T_a= 85 to 105°C

2.4 ≤ VCC ≤ 5.5

5

*

T_a= -40 to -20°C

2.4 ≤ VCC ≤ 5.5

HOCO64

T_a= -20 to 85°C

2.4 ≤ VCC ≤ 5.5

T_a= 85 to 105°C

2.4 ≤ VCC ≤ 5.5

HOCO clock oscillation

7

μs

Figure 2.27

Except Low-Voltage t_HOCO24

stabilization time*^6,

*

mode

t_HOCO32

t_HOCO48

t_HOCO64

-

43.3

80.6

100.9

Low-Voltage mode

t_HOCO24

t_HOCO32

t_HOCO48

t_HOCO64

PLL input frequency*²

f

4

24

-

12.5

64

55.5

-

MHz

μs

-

PLLIN

PLL circuit oscillation frequency*²

f

-

PLL

PLL clock oscillation stabilization time*⁸

PLL free-running oscillation frequency

Sub-clock oscillator oscillation frequency

Sub-clock oscillation stabilization time*³

t

-

Figure 2.29

PLL

f

-

8

MHz

kHz

s

-

PLLFR

f

-

32.768

-

SUB

t

-

-*³

Figure 2.30

SUBOSC

Note 1. Time until the clock can be used after the Main Clock Oscillator Stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the

external clock is stable.

Note 2. The VCC range that the PLL can be used is 2.4 to 5.5 V.

Note 3. After changing the setting of the SOSCCR.SOSTP bit so that the sub-clock oscillator operates, only start using the sub-clock

after the sub-clock oscillation stabilization wait time elapses, that is greater than or equal to the value recommended by the

oscillator manufacturer.

Note 4. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V.

Note 5. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V.

Note 6. This is a characteristic when HOCOCR.HCSTP bit is set to 0 (oscillation) in MOCO stop state.

When HOCOCR.HCSTP bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 μs.

Note 7. Whether stabilization time has elapsed can be confirmed by OSCSF.HOCOSF.

Note 8. This is a characteristic when PLLCR.PLLSTP bit is set to 0 (operation) in MOCO stop state.

When PLLCR.PLLSTP bit is set to 0 (operation) during MOCO oscillation, this specification is shortened by 1 μs.

Note 9. When setting up the main clock, ask the oscillator manufacturer for an oscillation evaluation and use the results as the

recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended

stabilization time. After changing the setting of the MOSCCR.MOSTP bit so that the main clock oscillator operates, read the

OSCSF.MOSCSF flag to confirm that it is 1, then start using the main clock.

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RA4M1 Group

2. Electrical Characteristics

t_Xcyc

t_XH

t_XL

EXTAL external clock input

VCC × 0.5

t_Xr

t_Xf

Figure 2.25

EXTAL external clock input timing

LOCOCR.LCSTP

t_LOCO

LOCO clock oscillator output

Figure 2.26

LOCO clock oscillation start timing

HOCOCR.HCSTP

HOCO clock

*1

t_HOCOx

Note 1. x = 24, 32, 48, 64

Figure 2.27

HOCO clock oscillation start timing (started by setting HOCOCR.HCSTP bit)

MOSCCR.MOSTP

Main clock oscillator output

t_MAINOSCWT

Main clock

Figure 2.28

Main clock oscillation start timing

PLLCR.PLLSTP

t_PLL

PLL clock

Figure 2.29

PLL clock oscillation start timing (PLL is operated after main clock oscillation has settled)

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RA4M1 Group

2. Electrical Characteristics

SOSCCR.SOSTP

t_SUBOSC

Sub-clock oscillator output

Figure 2.30

Sub-clock oscillation start timing

MOCOCR.MCSTP

t_MOCO

MOCO clock oscillator output

Figure 2.31

MOCO clock oscillation start timing

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RA4M1 Group

2. Electrical Characteristics

2.3.3

Reset Timing

Table 2.23

Parameter

Reset timing

Test

Symbol

t_RESWP

t_RESW

Min

3

Typ

-

Max

Unit

ms

μs

conditions

Figure 2.32

Figure 2.33

Figure 2.32

-

RES pulse width

At power-on

30

-

Other than above

LVD0: enable*¹

LVD0: disable*²

LVD0: enable*¹

LVD0: disable*²

-

0.7

0.3

0.5

0.05

0.6

0.15

Wait time after RES cancellation

(at power-on)

t_RESWT

-

ms

Wait time after RES cancellation

(during powered-on state)

t_RESWT2

ms

Figure 2.33

-

Internal reset cancellation time (Watchdog LVD0: enable*¹

timer reset, SRAM parity error reset,

SRAM ECC error reset, Bus master MPU

t_RESWT3

LVD0: disable*²

error reset, Bus slave MPU error reset,

Stack pointer error reset, Software reset)

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

VCC

RES

t_RESWP

Internal reset

t_RESWT

Figure 2.32

Reset input timing at power-on

t_RESW

RES

Internal reset

t_RESWT2

Figure 2.33

Reset input timing

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Oct 8, 2019

Page 61 of 130

RA4M1 Group

2. Electrical Characteristics

2.3.4

Wakeup Time

Table 2.24

Parameter

Timing of recovery from low power modes (1)

Test

Symbol Min Typ Max Unit conditions

Recovery time

from Software

Standby mode^*1

High-speed

mode

Crystal

System clock source is

main clock oscillator

(20 MHz)^*2

t_SBYMC

t_SBYPC

t_SBYEX

t_SBYPE

-

2

3

ms

μs

Figure 2.34

resonator

connected to

main clock

oscillator

System clock source is

PLL (48 MHz) with main

clock oscillator^*2

2

3

External clock

input to main

clock oscillator

System clock source is

main clock oscillator

(20 MHz)^*3

14

53

25

76

System clock source is

PLL (48 MHz) with main

clock oscillator^*3

μs

System clock source is HOCO^*4

(HOCO clock is 32 MHz)

t_SBYHO

t_SBYMO

-

43

44

82

16

52

μs

System clock source is HOCO^*4

(HOCO clock is 48 MHz)

52

System clock source is HOCO^*5

(HOCO clock is 64 MHz)

110

25

System clock source is MOCO

Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time

is determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.

Note 4. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h.

Note 5. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h.

Table 2.25

Parameter

Timing of recovery from low power modes (2)

Test

Symbol Min Typ Max Unit conditions

Recovery time

from Software

Standby mode*

Middle-speed Crystal

mode resonator

System clock source is

main clock oscillator

(12 MHz)*

t_SBYMC

t_SBYPC

t_SBYEX

t_SBYPE

-

2

3

ms

μs

Figure 2.34

1

2

connected to

main clock

oscillator

System clock source is

PLL (24 MHz) with main

2

3

2

clock oscillator*

External clock

input to main

clock oscillator

System clock source is

main clock oscillator

2.9

49

10

76

3

(12 MHz)*

System clock source is

PLL (24 MHz) with main

μs

3

clock oscillator*

System clock source is HOCO (24 MHz)

System clock source is MOCO

t_SBYHO

t_SBYMO

-

38

50

μs

3.5

5.5

Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time

is determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 62 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.26

Parameter

Timing of recovery from low power modes (3)

Test

Symbol Min Typ Max Unit conditions

Recovery time

from Software

Standby mode*

Low-speed

mode

Crystal

System clock source is

main clock oscillator

(1 MHz)*

t_SBYMC

-

2

3

ms

Figure 2.34

resonator

connected to

main clock

oscillator

1

2

External clock

input to main

clock oscillator

System clock source is

main clock oscillator

(1 MHz)*

t_SBYEX

-

28

25

50

35

μs

3

System clock source is MOCO

t_SBYMO

Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time

is determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.

Table 2.27

Parameter

Timing of recovery from low power modes (4)

Test

Symbol Min Typ Max Unit conditions

Recovery time

from Software

Standby mode*

Low-voltage

mode

Crystal

System clock source is

main clock oscillator

(4 MHz)*

t_SBYMC

-

2

3

ms

Figure 2.34

resonator

connected to

main clock

oscillator

1

2

External clock

input to main

clock oscillator

System clock source is

main clock oscillator

(4 MHz)*

t_SBYEX

-

108

130

μs

3

System clock source is HOCO

t_SBYHO

Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time

is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined by the

following expression.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.

Table 2.28

Parameter

Timing of recovery from low power modes (5)

Test

Symbol Min Typ Max Unit conditions

Recovery time

from Software

Standby mode*¹

Subosc-speed mode

System clock source is sub-clock t_SBYSC

oscillator (32.768 kHz)

-

0.85

1

ms

Figure 2.34

System clock source is LOCO

(32.768 kHz)

t_SBYLO

-

0.85 1.2

ms

Note 1. The sub-clock oscillator or LOCO itself continues to oscillate in Software Standby mode during Subosc-speed mode.

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Page 63 of 130

RA4M1 Group

2. Electrical Characteristics

Oscillator

ICLK

IRQ

Software Standby mode

t_SBYMC,t_SBYPC,t_SBYEX,

t_SBYPE, t_SBYMO, t_SBYHO

Oscillator

ICLK

IRQ

Software Standby mode

t_SBYSC, t_SBYLO

Figure 2.34

Table 2.29

Software Standby mode cancellation timing

Timing of recovery from low power modes (6)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery time from High-speed mode

t_SNZ

-

36

45

μs

Figure 2.35

Software Standby

mode to Snooze

mode

System clock source is HOCO

Middle-speed mode

System clock source is MOCO

t_SNZ

-

1.3

10

87

3.6

13

μs

Low-speed mode

System clock source is MOCO

Low-voltage mode

110

System clock source is HOCO

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 64 of 130

RA4M1 Group

2. Electrical Characteristics

Oscillator

ICLK (except DTC, SRAM)

ICLK (to DTC, SRAM)^*1

PCLK

IRQ

Software Standby mode

Snooze mode

t_SNZ

Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.35

Software Standby mode to Snooze mode recovery timing

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Page 65 of 130

RA4M1 Group

2.3.5

2. Electrical Characteristics

NMI and IRQ Noise Filter

Table 2.30

NMI and IRQ noise filter

Parameter

Symbol Min

t_NMIW200

_Pcyc× 2*

200

Typ

Max

Unit

Test conditions

-

NMI pulse width

ns

NMI digital filter disabled

t_Pcyc× 2 ≤ 200 ns

t_Pcyc× 2 > 200 ns

t_NMICK× 3 ≤ 200 ns

t_NMICK× 3 > 200 ns

t_Pcyc× 2 ≤ 200 ns

t_Pcyc× 2 > 200 ns

t_IRQCK× 3 ≤ 200 ns

t_IRQCK× 3 > 200 ns

1

t

NMI digital filter enabled

IRQ digital filter disabled

IRQ digital filter enabled

2

t_NMICK× 3.5*

200

IRQ pulse width

t_IRQW

ns

1

t_Pcyc× 2*

200

3

t_IRQCK× 3.5*

Note:

Note 1.

200 ns minimum in Software Standby mode.

If the clock source is switched, add 4 clock cycles of the switched source.

_Pcycindicates the cycle of PCLKB.

t

Note 2. t_NMICKindicates the cycle of the NMI digital filter sampling clock.

Note 3.

t_IRQCKindicates the cycle of the IRQi digital filter sampling clock (i = 0 to 12, 14, 15).

NMI

t_NMIW

Figure 2.36

NMI interrupt input timing

IRQ

t_IRQW

Figure 2.37

IRQ interrupt input timing

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Page 66 of 130

RA4M1 Group

2.3.6

2. Electrical Characteristics

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing

Table 2.31

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing

Test

Parameter

Symbol Min

Max

Unit

t_Pcyc

us

conditions

I/O ports

Input data pulse width

t_PRW

1.5

-

Figure 2.38

Input/output data cycle (P002, P003, P004, P007)

POEG input trigger pulse width

t_POcyc

t_POEW

t_GTICW

10

POEG

GPT

3

t_Pcyc

t_PDcyc

Figure 2.39

Figure 2.40

Input capture pulse width

Single edge

Dual edge

1.5

2.5

1

AGT

AGTIO, AGTEE input cycle

2.7 V ≤ VCC ≤ 5.5 V t_ACYC

*

250

500

1000

2000

100

200

400

800

62.5

125

250

ns

Figure 2.41

2.4 V ≤ VCC < 2.7 V

1.8 V ≤ VCC < 2.4 V

1.6 V ≤ VCC < 1.8 V

AGTIO, AGTEE input high level

width, low-level width

2.7 V ≤ VCC ≤ 5.5 V t_ACKWH,

t_ACKWL

2.4 V ≤ VCC < 2.7 V

1.8 V ≤ VCC < 2.4 V

1.6 V ≤ VCC < 1.8 V

2.7 V ≤ VCC ≤ 5.5 V t_ACYC2

2.4 V ≤ VCC < 2.7 V

1.8 V ≤ VCC < 2.4 V

AGTIO, AGTO, AGTOA, AGTOB

output cycle

Figure 2.41

1.6 V ≤ VCC < 1.8 V

500

1.5

-

ns

ADC14

KINT

14-bit A/D converter trigger input pulse width

KRn (n = 00 to 07) pulse width

t_TRGW

t_KR

t_Pcyc

ns

Figure 2.42

Figure 2.43

250

Note 1. Constraints on input cycle:

When not switching the source clock: t_Pcyc× 2 < t_ACYCshould be satisfied.

When switching the source clock: t_Pcyc× 6 < t_ACYCshould be satisfied.

_Pcyc: PCLKB cycle, t_PDcyc: PCLKD cycle

Note:

t

Port

t_PRW

Figure 2.38

I/O ports input timing

POEG input trigger

t_POEW

Figure 2.39

POEG input trigger timing

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Page 67 of 130

RA4M1 Group

2. Electrical Characteristics

Input capture

t_GTICW

Figure 2.40

GPT input capture timing

t_ACYC

t_ACKWL

t_ACKWH

AGTIO, AGTEE

(input)

t_ACYC2

AGTIO, AGTO,

AGTOA, AGTOB

(output)

Figure 2.41

AGT I/O timing

ADTRG0

t_TRGW

Figure 2.42

ADC14 trigger input timing

KR00 to KR07

t_KR

Figure 2.43

Key interrupt input timing

2.3.7

CAC Timing

Table 2.32

Parameter

CAC timing

Test

conditions

Symbol Min

Typ

Max

Unit

ns

2

1

CAC

CACREF input pulse width

t_PBcyc*¹≤ t_cac

_PBcyc*¹> t_cac

*

t_CACREF4.5 × t_cac+ 3 × t_PBcyc

5 × t_cac+ 6.5 × t_PBcyc

*

-

t

*

ns

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Page 68 of 130

RA4M1 Group

2. Electrical Characteristics

Note 1. t_PBcyc: PCLKB cycle.

Note 2.

t_cac: CAC count clock source cycle.

2.3.8

SCI Timing

Table 2.33

SCI timing (1)

Test

conditions

Parameter

Symbol

Min

4

Max

-

Unit^*1

SCI

Input clock cycle

Asynchronous

t_Scyc

t_Pcyc

Figure 2.44

Clock synchronous

6

-

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t_SCKW

t_SCKr

t_SCKf

t_Scyc

0.4

-

0.6

20

-

t_Scyc

ns

-

ns

Asynchronous

6

t_Pcyc

Clock synchronous

4

-

Output clock pulse width

Output clock rise time

t_SCKW

0.4

-

0.6

20

30

20

30

40

45

55

60

100

125

-

t_Scyc

ns

1.8 V or above t_SCKr

1.6 V or above

-

Output clock fall time

1.8 V or above t_SCKf

1.6 V or above

-

ns

-

Transmit data delay Clock

1.8 V or above t_TXD

1.6 V or above

-

Figure 2.45

(master)

synchronous

-

Transmit data delay Clock

2.7 V or above

-

(slave)

synchronous

2.4 V or above

-

1.8 V or above

-

1.6 V or above

-

Receive data setup Clock

2.7 V or above t_RXS

2.4 V or above

45

55

90

110

40

45

5

ns

time (master)

synchronous

-

1.8 V or above

-

1.6 V or above

-

Receive data setup Clock

2.7 V or above

-

time (slave)

synchronous

1.6 V or above

-

Receive data hold

time (master)

Clock synchronous

t_RXH

-

ns

Receive data hold

time (slave)

Clock synchronous

40

-

Note 1. t_Pcyc: PCLKA cycle.

t_SCKW

t_SCKr

t_SCKf

SCKn

(n = 0 to 2, 9)

t_Scyc

Figure 2.44

SCK clock input timing

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Page 69 of 130

RA4M1 Group

2. Electrical Characteristics

SCKn

TXDn

t_TXD

t_RXSt_RXH

RXDn

(n = 0 to 2, 9)

Figure 2.45

Table 2.34

SCI input/output timing in clock synchronous mode

SCI timing (2) (1 of 2)

Parameter

Symbol

Min

4

Max

Unit

Test conditions

Simple SCK clock cycle output (master)

t_SPcyc

65,536

t_Pcyc

Figure 2.46

SPI

SCK clock cycle input (slave)

6

65,536

SCK clock high pulse width

SCK clock low pulse width

SCK clock rise and fall time

t_SPCKWH

t_SPCKWL

0.4

-

0.6

20

30

-

t_SPcyc

ns

1.8 V or above t_SPCKr,

t_SPCKf

1.6 V or above

-

Data input setup

time

Master

2.7 V or above t_SU

2.4 V or above

1.8 V or above

1.6 V or above

2.7 V or above

1.6 V or above

t_H

45

55

80

110

40

45

33.3

40

1

ns

Figure 2.47 to

Figure 2.50

-

Slave

-

Data input hold time Master

Slave

-

ns

-

SS input setup time

SS input hold time

t_LEAD

t_LAG

-

t_SPcyc

ns

1

-

Data output delay

Master

Slave

1.8 V or above t_OD

1.6 V or above

2.4 V or above

1.8 V or above

1.6 V or above

2.7 V or above t_OH

2.4 V or above

1.8 V or above

1.6 V or above

-

40

50

65

100

125

-

Data output hold

time

Master

-10

-20

-30

-40

-10

-

ns

-

Slave

-

Data rise and fall

time

Master

1.8 V or above t_Dr,t_Df

1.6 V or above

20

30

20

30

-

Slave

1.8 V or above

-

1.6 V or above

-

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RA4M1 Group

2. Electrical Characteristics

Table 2.34

Parameter

SCI timing (2) (2 of 2)

Symbol

Min

Max

Unit

Test conditions

Simple Slave access time

SPI

t_SA

-

10 (PCLKA > t_Pcyc

32 MHz),

Figure 2.49 and

Figure 2.50

6 (PCLKA ≤

32 MHz)

Slave output release time

t_REL

-

10 (PCLKA > t_Pcyc

32 MHz),

6 (PCLKA ≤

32 MHz)

t_SPCKr

t_SPCKf

t_SPCKWH

V_OH

V_OL

V_OH

SCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

SCKn

slave select input

V_IL

t_SPCKWL

V_IL

(n = 0 to 2, 9)

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Figure 2.46

SCI simple SPI mode clock timing

SCKn

CKPOL = 0

output

SCKn

CKPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 2, 9)

Figure 2.47

SCI simple SPI mode timing for master when CKPH = 1

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RA4M1 Group

2. Electrical Characteristics

SCKn

CKPOL = 1

output

SCKn

CKPOL = 0

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 2, 9)

Figure 2.48

SCI simple SPI mode timing for master when CKPH = 0

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 0

input

SCKn

CKPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

(n = 0 to 2, 9)

Figure 2.49

SCI simple SPI mode timing for slave when CKPH = 1

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RA4M1 Group

2. Electrical Characteristics

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(Last data)

MSB OUT

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

LSB IN

(n = 0 to 2, 9)

Figure 2.50

Table 2.35

SCI simple SPI mode timing for slave when CKPH = 0

SCI timing (3)

Conditions: VCC = 2.7 to 5.5 V

Parameter

Symbol

t_Sr

Min

Max

Unit

ns

pF

ns

pF

Test conditions

Simple I²C

(Standard mode)

SDA input rise time

-

1000

Figure 2.51

SDA input fall time

t_Sf

-

300

1

SDA input spike pulse removal time

Data input setup time

t_SP

0

4 × t_IICcyc*

t_SDAS

t_SDAH

C_b*²

t_Sr

250

-

Data input hold time

0

-

SCL, SDA capacitive load

SDA input rise time

-

400

Simple I²C

(Fast mode)

-

300

Figure 2.51

For all ports

SDA input fall time

t_Sf

-

300

except P408, use

PmnPFS.DSCR

of middle drive.

For port P408,

use

PmnPFS.DSCR1

/DSCR of middle

drive for IIC

1

SDA input spike pulse removal time

Data input setup time

t_SP

0

4 × t_IICcyc*

t_SDAS

t_SDAH

C_b*¹

100

-

Data input hold time

0

-

SCL, SDA capacitive load

400

fast-mode.

Note 1. tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.

Note 2. Cb indicates the total capacity of the bus line.

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2. Electrical Characteristics

V_IH

V_IL

SDAn

t_Sr

t_Sf

t_SP

SCLn

P*¹

S*¹

Sr*¹

(n = 0 to 2, 9)

t_SDAH

t_SDAS

Note 1. S, P, and Sr indicate the following:

S: Start condition

Test conditions:

_IH= VCC × 0.7, V_IL= VCC × 0.3

V_OL= 0.6 V, I_OL= 6 mA

V

P: Stop condition

Sr: Restart condition

Figure 2.51

SCI simple IIC mode timing

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Page 74 of 130

RA4M1 Group

2.3.9

2. Electrical Characteristics

SPI Timing

Table 2.36

SPI timing (1 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register

*1

Parameter

SPI RSPCK clock cycle

Symbol

Min

2*⁴

6

Max

4096

-

Unit

Test conditions

Master

Slave

t_SPcyc

t_Pcyc

Figure 2.52

RSPCK clock high

pulse width

Master

t_SPCKWH(t_SPcyc

t_SPCKr

_SPCKf) / 2 -

-

ns

-

t

3

Slave

3 × t_Pcyc

-

RSPCK clock low

pulse width

Master

t_SPCKWL

(t_SPcyc

t_SPCKr

_SPCKf) / 2 -

-

t

3

Slave

3 × t_Pcyc

-

RSPCK clock rise

and fall time

Output

2.7 V or above

2.4 V or above

1.8 V or above

1.6 V or above

t_SPCKr,

t_SPCKf

-

10

15

20

30

1

ns

Input

µs

ns

Data input setup time Master

Slave

t_SU

10

15

20

0

-

Figure 2.53 to

Figure 2.58

2.4 V or above

1.8 V or above

1.6 V or above

Data input hold time

Master

(RSPCK is PCLKA/2)

t_HF

t_H

ns

Master

(RSPCK is other than

above.)

t_Pcyc

-

Slave

t_H

20

-

SSL setup time

SSL hold time

Master

1.8 V or above

1.6 V or above

t_LEAD

-30 + N ×

t_Spcyc

2

*

-50 + N ×

t_Spcyc

-

2

*

Slave

6 × t_Pcyc

-

Master

t_LAG

-30 + N ×

t_Spcyc

3

*

Slave

6 × t_Pcyc

-

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RA4M1 Group

2. Electrical Characteristics

Table 2.36

SPI timing (2 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register

*1

Parameter

SPI Data output delay

Symbol

Min

Max

14

20

25

30

50

60

85

110

-

Unit

Test conditions

Master

Slave

2.7 V or above

2.4 V or above

1.8 V or above

1.6 V or above

2.7 V or above

2.4 V or above

1.8 V or above

1.6 V or above

t_OD

-

ns

Figure 2.53 to

Figure 2.58

-

Data output hold time Master

Slave

t_OH

0

ns

-

Successive

Master

t_TD

t_SPcyc+ 2 × 8 × t_SPcyc

transmission delay

t_Pcyc

+ 2 × t_Pcyc

Slave

6 × t_Pcyc

-

MOSI and MISO rise Output

and fall time

2.7 V or above

2.4 V or above

1.8 V or above

1.6 V or above

t_Dr,t_Df

-

10

15

20

30

1

ns

Input

µs

ns

SSL rise and fall time Output

2.7 V or above

2.4 V or above

1.8 V or above

1.6 V or above

t_SSLr,

t_SSLf

10

15

20

30

1

Input

µs

Slave access time

2.4 V or above

1.8 V or above

1.6 V or above

2.4 V or above

1.8 V or above

1.6 V or above

t_SA

2 × t_Pcyc+ 100 ns

2 × t_Pcyc+ 140

Figure 2.57 and

Figure 2.58

2 × t_Pcyc+ 180

Slave output release time

t_REL

2 × t_Pcyc+ 100 ns

2 × t_Pcyc+ 140

2 × t_Pcyc+ 180

Note 1. t_Pcyc: PCLKA cycle.

Note 2. N is set as an integer from 1 to 8 by the SPCKD register.

Note 3. N is set as an integer from 1 to 8 by the SSLND register.

Note 4. The upper limit of RSPCK is 16 MHz.

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2. Electrical Characteristics

t_SPCKr

t_SPCKf

t_SPCKWH

V_OH

V_OL

V_OH

RSPCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

RSPCKn

slave select input

V_IL

t_SPCKWL

V_IL

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

n = A or B

Figure 2.52

SPI clock timing

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.53

SPI timing for master when CPHA = 0 and the bit rate is set to any value other than PCLKA/2

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2. Electrical Characteristics

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_HF

t_SU

t_HF

MISOn

input

LSB IN

MSB IN

DATA

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.54

SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.55

SPI timing for master when CPHA = 1 and the bit rate is set to any value other than PCLKA/2

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2. Electrical Characteristics

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

n = A or B

DATA

t_SU

t_HF

t_H

MISOn

input

MSB IN

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

DATA

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.56

SPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2

t_TD

SSLn0

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

n = A or B

Figure 2.57

SPI timing for slave when CPHA = 0

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2. Electrical Characteristics

t_TD

SSLn0

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(Last data)

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIn

input

MSB IN

LSB IN

n = A or B

Figure 2.58

SPI timing for slave when CPHA = 1

2.3.10

IIC Timing

Table 2.37

IIC timing (1 of 2)

Conditions: VCC = 2.7 to 5.5 V

Test

Parameter

Symbol Min*¹

Max

Unit conditions

IIC

SCL input cycle time

t_SCL

6 (12) × t_IICcyc

1300

+

-

ns

Figure 2.59

(standard mode,

SMBus)

SCL input high pulse width

SCL input low pulse width

t_SCLH

t_SCLL

3 (6) × t_IICcyc

300

+

-

3 (6) × t_IICcyc

300

+

SCL, SDA input rise time

SCL, SDA input fall time

t_Sr

t_Sf

-

1,000

ns

-

300

SCL, SDA input spike pulse removal

time

t_SP

0

1 (4) × t_IICcyc

SDA input bus free time

(When wakeup function is disabled)

t_BUF

3 (6) × t_IICcyc

300

+

-

ns

SDA input bus free time

(When wakeup function is enabled)

t_BUF

3 (6) × t_IICcyc

4 × t_Pcyc+ 300

START condition input hold time

(When wakeup function is disabled)

t_STAH

t_IICcyc+ 300

START condition input hold time

(When wakeup function is enabled)

1 (5) × t_IICcyc

t_Pcyc+ 300

+

Repeated START condition input setup t_STAS

time

1,000

STOP condition input setup time

Data input setup time

t_STOS

t_SDAS

t_SDAH

C_b

1,000

-

ns

pF

t_IICcyc+ 50

-

Data input hold time

0

-

SCL, SDA capacitive load

400

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2. Electrical Characteristics

Table 2.37

IIC timing (2 of 2)

Conditions: VCC = 2.7 to 5.5 V

Test

Parameter

Symbol Min*¹

Max

Unit conditions

IIC

SCL input cycle time

t_SCL

6 (12) × t_IICcyc

600

+

-

ns

Figure 2.59

For all ports

except P408,

use

PmnPFS.DSC

R of middle

drive.

(Fast mode)

SCL input high pulse width

SCL input low pulse width

t_SCLH

t_SCLL

3 (6) × t_IICcyc

300

+

-

3 (6) × t_IICcyc

300

+

For port P408,

use

SCL, SDA input rise time

SCL, SDA input fall time

t_Sr

t_Sf

-

300

ns

-

300

PmnPFS.DSC

R1/DSCR of

middle drive

for IIC fast-

mode.

SCL, SDA input spike pulse removal

time

t_SP

0

1 (4) × t_IICcyc

SDA input bus free time

(When wakeup function is disabled)

t_BUF

3 (6) × t_IICcyc

300

+

-

ns

SDA input bus free time

(When wakeup function is enabled)

t_BUF

3 (6) × t_IICcyc

4 × t_Pcyc+ 300

START condition input hold time

(When wakeup function is disabled)

t_STAH

t_IICcyc+ 300

START condition input hold time

(When wakeup function is enabled)

1(5) × t_IICcyc

_Pcyc+ 300

+

t

Repeated START condition input setup t_STAS

time

300

STOP condition input setup time

Data input setup time

t_STOS

t_SDAS

t_SDAH

C_b

300

-

ns

pF

t_IICcyc+ 50

-

Data input hold time

0

-

SCL, SDA capacitive load

400

Note:

t_IICcyc: IIC internal reference clock (IICφ) cycle, t_Pcyc: PCLKB cycle

Note 1. The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

V_IH

SDA0 to SDA1

V_IL

t_BUF

t_SCLH

t_STAS

t_STOS

t_STAH

t_SP

SCL0 to SCL1

P*¹

S*¹

Sr*¹

t_SCLL

t_Sr

t_Sf

t_SDAS

t_SCL

t_SDAH

Note 1. S, P, and Sr indicate the following conditions.

S: Start condition

P: Stop condition

Sr: Restart condition.

Figure 2.59

IIC bus interface input/output timing

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2.3.11

2. Electrical Characteristics

SSIE Timing

Table 2.38

SSIE timing

Conditions: VCC = 1.6 to 5.5 V

Test conditions

Parameter

Symbol

Min

-

Max

Unit

SSIE

AUDIO_CLK input

frequency

2.7 V or above

1.6 V or above

t_AUDIO

25

MHz

-

4

Output clock period

Input clock period

t_O

t_I

250

100

200

100

200

-

ns

Figure 2.60

-

Clock high pulse

width

1.8 V or above

1.6 V or above

1.8 V or above

1.6 V or above

t_HC

-

Clock low pulse

width

t_LC

-

ns

-

Clock rise time

Data delay

t_RC

25

65

105

140

-

ns

2.7 V or above

1.8 V or above

1.6 V or above

2.7 V or above

1.8 V or above

1.6 V or above

t_DTR

-

Figure 2.61,

Figure 2.62

-

Set-up time

t_SR

65

90

140

40

-

ns

-

Hold time

t_HTR

-

ns

SSITXD0 output

delay from

SSILRCK0/SSIFS0

change time

1.8 V or above

1.6 V or above

T_DTRW

105

140

Figure 2.63

-

t_HC

t_RC

t_LC

SSIBCK0

t_I, t_O

Figure 2.60

SSIE clock input/output timing

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2. Electrical Characteristics

SSIBCK0

(Input or Output)

SSILRCK0/SSIFS0,

SSIRXD0

(Input)

t_SR

t_HTR

SSILRCK0/SSIFS0,

SSITXD0

(Output)

t_DTR

Figure 2.61

SSIE data transmit/receive timing (SSICR.BCKP = 0)

SSIBCK0

(Input or Output)

SSILRCK0/SSIFS0,

SSIRXD0

(Input)

t_SR

t_HTR

SSILRCK0/SSIFS0,

SSITXD0

(Output)

t_DTR

Figure 2.62

SSIE data transmit/receive timing (SSICR.BCKP = 1)

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2. Electrical Characteristics

SSILRCK0/SSIFS0

(Input)

SSITXD0 (Output)

t_DTRW

MSB bit output delay from SSILRCK0/SSIFS0 change time for

slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0]

SSIE data output delay from SSILRCK0/SSIFS0 change time

CLKOUT Timing

Figure 2.63

2.3.12

Table 2.39

Parameter

CLKOUT timing

Symbol

Min

62.5

125

250

15

30

150

15

30

150

-

Max

Unit*¹

Test conditions

1

CLKOUT

CLKOUT pin output cycle*

VCC = 2.7 V or above

VCC = 1.8 V or above

VCC = 1.6 V or above

VCC = 2.7 V or above

VCC = 1.8 V or above

VCC = 1.6 V or above

VCC = 2.7 V or above

VCC = 1.8 V or above

VCC = 1.6 V or above

VCC = 2.7 V or above

VCC = 1.8 V or above

VCC = 1.6 V or above

VCC = 2.7 V or above

VCC = 1.8 V or above

VCC = 1.6 V or above

t

-

ns

Figure 2.64

Ccyc

CH

CL

Cr

-

2

CLKOUT pin high pulse width*

-

ns

-

2

CLKOUT pin low pulse width*

CLKOUT pin output rise time

CLKOUT pin output fall time

-

12

25

50

12

25

50

-

Cf

-

Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and

the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to

55%.

Note 2. When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division

ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).

t_Ccyc

t_CH

t_Cf

CLKOUT pin output

t_Cr

t_CL

Test conditions: V_OH= VCC × 0.7, V_OL= VCC × 0.3, I_OH= -1.0 mA, I_OL= 1.0 mA, C = 30 pF

Figure 2.64

CLKOUT output timing

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2. Electrical Characteristics

2.4

USB Characteristics

2.4.1

USBFS Timing

Table 2.40

USB characteristics

Conditions: VCC = VCC_USB = 3.0 to 3.6 V, T = -20 to +85°C (USBCLKSEL = 1), T = -40 to +105°C (USBCLKSEL = 0)

a

Max

-

Parameter

Symbol

Min

2.0

-

Unit

V

Test conditions

Input

Input high level voltage

Input low level voltage

V

-

IH

IL

characteristics

0.8

-

V

-

Differential input sensitivity

0.2

0.8

V

|USB_DP - USB_DM |

-

DI

Differential common mode

range

2.5

V

CM

Output

characteristics

Output high level voltage

Output low level voltage

Cross-over voltage

V

2.8

0.0

1.3

4

VCC_USB

0.3

V

I

= -200 μA

= 2 mA

OH

OL

V

OL

2.0

V

Figure 2.65,

Figure 2.66,

Figure 2.67

CRS

Rise time

FS

LS

FS

LS

t

20

ns

r

75

4

300

Fall time

t

20

ns

%

Ω

f

75

90

80

28

300

Rise/fall time ratio FS

LS

t /t

111.11

125

r

f

Output resistance

Z

44

(Adjusting the resistance

of external elements is not

necessary.)

DRV

VBUS

characteristics

VBUS input voltage

V

VCC × 0.8

-

V

-

IH

-

VCC × 0.2

24.80

1.575

3.09

175

V

-

IL

Pull-up,

pull-down

Pull-down resistor

Pull-up resistor

R

14.25

0.9

1.425

25

kΩ

μA

V

-

PD

During idle state

PUI

During reception

PUA

Battery Charging D + sink current

Specification

D - sink current

Ver 1.2

I

-

DP_SINK

DM_SINK

DP_SRC

25

175

-

DCD source current

Data detection voltage

D + source voltage

D - source voltage

7

13

-

V

0.25

0.5

0.4

-

DAT_REF

DP_SRC

DM_SRC

0.7

V

Output current = 250 μA

0.7

V

90%

USB_DP,

USB_DM

V_CRS

10%

t_r

t_f

Figure 2.65

USB_DP and USB_DM output timing

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2. Electrical Characteristics

Observation

point

DP

50 pF

DM

50 pF

Figure 2.66

Test circuit for Full-Speed (FS) connection

Observation

point

DP

200 pF to

600 pF

3.6 V

1.5 K

DM

200 pF to

600 pF

Observation

point

Figure 2.67

Test circuit for Low-Speed (LS) connection

2.4.2

USB External Supply

Table 2.41

Parameter

USB regulator

Min

Typ

Max

Unit

Test conditions

VCC_USB supply current VCC_USB_LDO ≥ 3.8V

VCC_USB_LDO ≥ 4.5V

-

50

mA

V

-

100

3.6

VCC_USB supply voltage

3.0

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RA4M1 Group

2. Electrical Characteristics

2.5

ADC14 Characteristics

VREFH0

5.5

A/D Conversion

Characteristics (1)

5.0

4.0

3.0

5.0

4.0

3.0

A/D Conversion

Characteristics (2)

A/D Conversion

Characteristics (4)

A/D Conversion

Characteristics (5)

A/D Conversion

Characteristics (3)

2.7

2.4

2.7

2.4

A/D Conversion

2.0

Characteristics (6)

2.0

1.8

1.6

A/D Conversion

Characteristics (7)

1.0

2.42.7

3.0

5.5 AVCC0

1.8 2.42.7

1.0 1.6 2.0 3.0

5.5 AVCC0

5.0

1.0

2.0

4.0

5.0

4.0

ADCSR.ADHSC = 0

ADCSR.ADHSC = 1

Figure 2.68

Table 2.42

AVCC0 to VREFH0 voltage range

A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2)

Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

Test conditions

-

Frequency

1

-

64

MHz

2

Analog input capacitance*

Cs

Rs

8 (reference data) pF

9 (reference data) pF

High-precision channel

Normal-precision channel

High-precision channel

-

Analog input resistance

-

2.5 (reference

data)

kΩ

V

-

6.7 (reference

data)

Normal-precision channel

-

Analog input voltage range

12-bit mode

Ain

0

VREFH0

Resolution

-

12

-

Bit

μs

-

1

Conversion time*

(Operation at

PCLKC = 64 MHz)

Permissible signal

source impedance

Max. = 0.3 kΩ

0.70

High-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 0Dh

1.13

-

μs

Normal-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 28h

Offset error

-

±0.5

±4.5

±6.0

±4.5

±6.0

-

LSB

High-precision channel

Other than above

Full-scale error

±0.75

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

-

±1.25

±5.0

±8.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

14-bit mode

-

±1.0

-

±3.0

Resolution

-

14

Bit

-

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2. Electrical Characteristics

Table 2.42

A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2)

Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

Test conditions

1

Conversion time*

(Operation at

Permissible signal

source impedance

Max. = 0.3 kΩ

0.80

-

μs

High-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 0Dh

PCLKC = 64 MHz)

1.22

-

μs

Normal-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 28h

Offset error

-

±2.0

±3.0

±18

±24.0

±18

±24.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

±5.0

-

±20

±32.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±4.0

-

±12.0

Note:

The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not

include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do

not include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for

the test conditions.

Note 2. Except for I/O input capacitance (C ), see section 2.2.4, I/O V , V , and Other Characteristics.

in

OH

OL

Table 2.43

A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2)

Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

MHz

pF

Test conditions

-

Frequency

1

-

48

2

Analog input capacitance*

Cs

Rs

Ain

8 (reference data)

9 (reference data)

2.5 (reference data)

6.7 (reference data)

VREFH0

High-precision channel

Normal-precision channel

High-precision channel

Normal-precision channel

-

pF

Analog input resistance

-

kΩ

V

-

Analog input voltage range

12-bit mode

0

Resolution

-

12

-

Bit

μs

-

1

Conversion time*

(Operation at

PCLKC = 48 MHz)

Permissible signal

source impedance

Max. = 0.3 kΩ

0.94

High-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 0Dh

1.50

-

μs

Normal-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 28h

Offset error

-

±0.5

±4.5

±6.0

±4.5

±6.0

-

LSB

High-precision channel

Other than above

Full-scale error

±0.75

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

-

±1.25

±5.0

±8.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±1.0

-

±3.0

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2. Electrical Characteristics

Table 2.43

A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2)

Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

14-bit mode

Resolution

Min

Typ

Max

Unit

Test conditions

-

14

-

Bit

μs

-

1

Conversion time*

(Operation at

PCLKC = 48 MHz)

Permissible signal

source impedance

Max. = 0.3 kΩ

1.06

High-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 0Dh

1.63

-

μs

Normal-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 28h

Offset error

-

±2.0

±3.0

±18

±24.0

±18

±24.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

±5.0

-

±20

±32.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±4.0

-

±12.0

Note:

The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not

include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do

not include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for

the test conditions.

Note 2. Except for I/O input capacitance (C ), see section 2.2.4, I/O V , V , and Other Characteristics.

in

OH

OL

Table 2.44

A/D conversion characteristics (3) in high-speed A/D conversion mode (1 of 2)

Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

MHz

pF

Test conditions

-

Frequency

1

-

32

2

Analog input capacitance*

Cs

Rs

Ain

8 (reference data)

9 (reference data)

High-precision channel

Normal-precision channel

High-precision channel

Normal-precision channel

-

pF

Analog input resistance

-

2.5 (reference data) kΩ

6.7 (reference data) kΩ

-

Analog input voltage range

12-bit mode

0

VREFH0

V

Resolution

-

12

-

Bit

μs

-

1

Conversion time*

(Operation at

Permissible signal

source impedance

1.41

High-precision channel

ADCSR.ADHSC = 0

PCLKC = 32 MHz) Max. = 1.3 kΩ

ADSSTRn.SST[7:0] = 0Dh

2.25

-

μs

Normal-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 28h

Offset error

-

±0.5

±4.5

±6.0

±4.5

±6.0

-

LSB

High-precision channel

Other than above

High-precision channel

Other than above

-

Full-scale error

±0.75

Quantization error

Absolute accuracy

-

±0.5

±1.25

±5.0

±8.0

High-precision channel

Other than above

R01DS0355EJ0100 Rev.1.00

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2. Electrical Characteristics

Table 2.44

A/D conversion characteristics (3) in high-speed A/D conversion mode (2 of 2)

Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

±1.0

Max

-

Unit

LSB

Test conditions

DNL differential nonlinearity error

INL integral nonlinearity error

14-bit mode

-

±3.0

Resolution

-

14

-

Bit

μs

-

1

Conversion time*

(Operation at

Permissible signal

source impedance

1.59

High-precision channel

ADCSR.ADHSC = 0

PCLKC = 32 MHz) Max. = 1.3 kΩ

ADSSTRn.SST[7:0] = 0Dh

2.44

-

μs

Normal-precision channel

ADCSR.ADHSC = 0

ADSSTRn.SST[7:0] = 28h

Offset error

-

±2.0

±3.0

±18

±24.0

±18

±24.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

±5.0

-

±20

±32.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±4.0

-

±12.0

Note:

The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not

include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do

not include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for

the test conditions.

Note 2. Except for I/O input capacitance (C ), see section 2.2.4, I/O V , V , and Other Characteristics.

in

OH

OL

Table 2.45

A/D conversion characteristics (4) in low power A/D conversion mode (1 of 2)

Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

MHz

pF

Test conditions

-

Frequency

1

-

24

2

Analog input capacitance*

Cs

Rs

Ain

8 (reference data)

9 (reference data)

2.5 (reference data)

6.7 (reference data)

VREFH0

High-precision channel

Normal-precision channel

High-precision channel

Normal-precision channel

-

pF

Analog input resistance

-

kΩ

V

-

Analog input voltage range

12-bit mode

0

Resolution

-

12

-

Bit

μs

-

1

Conversion time*

(Operation at

Permissible

signal source

2.25

High-precision channel

ADCSR.ADHSC = 1

PCLKC = 24 MHz) impedance Max.

= 1.1 kΩ

ADSSTRn.SST[7:0] = 0Dh

3.38

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

Offset error

-

±0.5

±0.75

±0.5

±4.5

±6.0

±4.5

±6.0

-

LSB

High-precision channel

Other than above

High-precision channel

Other than above

-

Full-scale error

Quantization error

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 90 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.45

A/D conversion characteristics (4) in low power A/D conversion mode (2 of 2)

Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

±5.0

±8.0

-

Unit

LSB

Test conditions

Absolute accuracy

-

±1.25

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

14-bit mode

-

±1.0

-

±3.0

Resolution

-

14

-

Bit

μs

-

1

Conversion time*

(Operation at

Permissible

signal source

2.50

High-precision channel

ADCSR.ADHSC = 1

PCLKC = 24 MHz) impedance Max.

= 1.1 kΩ

ADSSTRn.SST[7:0] = 0Dh

3.63

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

Offset error

-

±2.0

±3.0

±18

±24.0

±18

±24.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

±5.0

-

±20

±32.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±4.0

-

±12.0

Note:

The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not

include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do

not include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for

the test conditions.

Note 2. Except for I/O input capacitance (C ), see section 2.2.4, I/O V , V , and Other Characteristics.

in

OH

OL

Table 2.46

A/D conversion characteristics (5) in low power A/D conversion mode (1 of 2)

Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

MHz

pF

Test conditions

-

Frequency

1

-

16

2

Analog input capacitance*

Cs

Rs

Ain

8 (reference data)

9 (reference data)

2.5 (reference data)

6.7 (reference data)

VREFH0

High-precision channel

Normal-precision channel

High-precision channel

Normal-precision channel

-

pF

Analog input resistance

-

kΩ

V

-

Analog input voltage range

12-bit mode

0

Resolution

-

12

-

Bit

μs

-

1

Conversion time*

(Operation at

PCLKC = 16 MHz)

Permissible signal 3.38

sourceimpedance

Max. = 2.2 kΩ

High-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 0Dh

5.06

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

Offset error

-

±0.5

±4.5

±6.0

LSB

High-precision channel

Other than above

R01DS0355EJ0100 Rev.1.00

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Page 91 of 130

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2. Electrical Characteristics

Table 2.46

A/D conversion characteristics (5) in low power A/D conversion mode (2 of 2)

Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

±4.5

±6.0

-

Unit

LSB

Test conditions

Full-scale error

-

±0.75

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

-

±1.25

±5.0

±8.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

14-bit mode

-

±1.0

-

±3.0

Resolution

-

14

-

Bit

μs

-

1

Conversion time*

(Operation at

PCLKC = 16 MHz)

Permissible signal 3.75

sourceimpedance

Max. = 2.2 kΩ

High-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 0Dh

5.44

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

Offset error

-

±2.0

±3.0

±18

±24.0

±18

±24.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

±5.0

-

±20

±32.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±4.0

-

±12.0

Note:

The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not

include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do

not include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for

the test conditions.

Note 2. Except for I/O input capacitance (C ), see section 2.2.4, I/O V , V , and Other Characteristics.

in

OH

OL

Table 2.47

A/D conversion characteristics (6) in low power A/D conversion mode (1 of 2)

Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

MHz

pF

Test conditions

-

Frequency

1

-

8

2

Analog input capacitance*

Cs

Rs

Ain

8 (reference data)

9 (reference data)

High-precision channel

Normal-precision channel

High-precision channel

Normal-precision channel

-

pF

Analog input resistance

-

3.8 (reference data) kΩ

8.2 (reference data) kΩ

-

Analog input voltage range

12-bit mode

0

VREFH0

V

Resolution

-

12

-

Bit

μs

-

1

Conversion time*

(Operation at

Permissible signal 6.75

source

High-precision channel

ADCSR.ADHSC = 1

PCLKC = 8 MHz)

impedance Max.

ADSSTRn.SST[7:0] = 0Dh

= 5 kΩ

10.13

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

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2. Electrical Characteristics

Table 2.47

A/D conversion characteristics (6) in low power A/D conversion mode (2 of 2)

Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

±7.5

±10.0

±7.5

±10.0

-

Unit

LSB

Test conditions

High-precision channel

Other than above

High-precision channel

Other than above

-

Offset error

-

±1.0

Full-scale error

-

±1.5

Quantization error

Absolute accuracy

-

±0.5

±3.0

±8.0

±12.0

-

High-precision channel

Other than above

-

DNL differential nonlinearity error

INL integral nonlinearity error

14-bit mode

-

±1.0

±3.0

-

Resolution

-

14

-

Bit

μs

-

1

Conversion time*

(Operation at

Permissible signal 7.50

source

High-precision channel

ADCSR.ADHSC = 1

PCLKC = 8 MHz)

impedance Max.

ADSSTRn.SST[7:0] = 0Dh

= 5 kΩ

10.88

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

Offset error

-

±4.0

±6.0

±30.0

±40.0

±30.0

±40.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

-

±12.0

±32.0

±48.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±4.0

-

±12.0

Note:

The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not

include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do

not include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for

the test conditions.

Note 2. Except for I/O input capacitance (C ), see section 2.2.4, I/O V , V , and Other Characteristics.

in

OH

OL

Table 2.48

A/D conversion characteristics (7) in low power A/D conversion mode (1 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

MHz

pF

Test conditions

-

Frequency

1

-

4

2

Analog input capacitance*

Cs

Rs

Ain

8 (reference data)

9 (reference data)

13.1 (reference data)

14.3 (reference data)

VREFH0

High-precision channel

Normal-precision channel

High-precision channel

Normal-precision channel

-

pF

Analog input resistance

-

kΩ

V

-

Analog input voltage range

12-bit mode

0

Resolution

-

12

Bit

-

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 93 of 130

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2. Electrical Characteristics

Table 2.48

A/D conversion characteristics (7) in low power A/D conversion mode (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V

Reference voltage range applied to the VREFH0 and VREFL0.

Parameter

Min

Typ

Max

Unit

Test conditions

1

Conversion time*

(Operation at

Permissible

signal source

impedance Max.

= 9.9 kΩ

13.5

-

μs

High-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 0Dh

PCLKC = 4 MHz)

20.25

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

Offset error

-

±1.0

±1.5

±7.5

±10.0

±7.5

±10.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

±3.0

-

±8.0

±12.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

14-bit mode

-

±1.0

-

±3.0

Resolution

-

14

-

Bit

μs

-

1

Conversion time*

(Operation at

PCLKC = 4 MHz)

Permissible

signal source

impedance Max.

= 9.9 kΩ

15.0

High-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 0Dh

21.75

-

μs

Normal-precision channel

ADCSR.ADHSC = 1

ADSSTRn.SST[7:0] = 28h

Offset error

-

±4.0

±6.0

±30.0

±40.0

±30.0

±40.0

-

LSB

High-precision channel

Other than above

Full-scale error

High-precision channel

Other than above

Quantization error

Absolute accuracy

-

±0.5

-

±12.0

±32.0

±48.0

-

High-precision channel

Other than above

DNL differential nonlinearity error

INL integral nonlinearity error

-

±4.0

-

±12.0

Note:

The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not

include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do

not include quantization errors.

Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for

the test conditions.

Note 2. Except for I/O input capacitance (C ), see section 2.2.4, I/O V , V , and Other Characteristics.

in

OH

OL

R01DS0355EJ0100 Rev.1.00

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2. Electrical Characteristics

MCU

Analog input

ANn

Rs

Sensor

Cin

ADC

Cs

Analog input

ANn

Rs

Cin

Figure 2.69

Table 2.49

Equivalent circuit for analog input

14-Bit A/D converter channel classification

Classification

Channel

Conditions

Remarks

High-precision channel

Normal-precision channel

AN000 to AN014

AN016 to AN025

AVCC0 = 1.6 to 5.5 V

Pins AN000 to AN014 cannot be used

as general I/O, IRQ2, IRQ3 inputs,

and TS transmission, when the A/D

converter is in use

Internal reference voltage

input channel

Internal reference voltage

Temperature sensor output

AVCC0 = 2.0 to 5.5 V

-

Temperature sensor input

channel

-

Table 2.50

A/D internal reference voltage characteristics

1

Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*

Parameter

Min

Typ

Max

Unit

Test conditions

Internal reference voltage input

channel*

1.36

1.43

1.50

V

-

2

3

Frequency*

1

-

2

-

MHz

μs

-

4

Sampling time*

5.0

Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.

Note 2. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 14-bit A/D

converter.

Note 3. This is a parameter for ADC14 when the internal reference voltage is used as the high-potential reference voltage.

Note 4. This is a parameter for ADC14 when the internal reference voltage is selected for an analog input channel in ADC14.

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2. Electrical Characteristics

3FFFh

Full-scale error

Integral nonlinearity

error (INL)

A/D converter

output code

Ideal line of actual A/D

conversion characteristic

Actual A/D conversion

characteristic

Ideal A/D conversion

characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

0000h

Offset error

0

Analog input voltage

VREFH0

(full-scale)

Figure 2.70

Illustration of 14-bit A/D converter characteristic terms

Absolute accuracy

Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the

actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog

input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D

conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference

voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog

input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion

result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D

conversion characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale

errors are zeroed, and the actual output code.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics

and the width of the actually output code.

Offset error

Offset error is the difference between the transition point of the ideal first output code and the actual first output code.

Full-scale error

Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

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2. Electrical Characteristics

2.6

DAC12 Characteristics

Table 2.51

D/A conversion characteristics (1)

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Reference voltage = VREFH or VREFL selected

Parameter

Min

Typ

Max

Unit

Test conditions

Resolution

-

12

bit

-

Resistive load

30

-

kΩ

pF

V

Load capacitance

Output voltage range

DNL differential nonlinearity error

INL integral nonlinearity error

Offset error

-

50

0.35

-

AVCC0 - 0.47

-

±0.5

±1.0

±8.0

±20

-

LSB

mV

Ω

±2.0

-

Full-scale error

-

Output impedance

Conversion time

5

-

30

μs

Table 2.52

D/A conversion characteristics (2)

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Reference voltage = AVCC0 or AVSS0 selected

Parameter

Min

Typ

Max

Unit

bit

Test conditions

Resolution

-

12

-

Resistive load

30

-

kΩ

pF

Load capacitance

Output voltage range

DNL differential nonlinearity error

INL integral nonlinearity error

Offset error

-

50

0.35

-

AVCC0 - 0.47

V

-

±0.5

±2.0

±8.0

±30

-

LSB

mV

Ω

±2.0

-

Full-scale error

-

Output impedance

Conversion time

5

-

30

μs

Table 2.53

D/A conversion characteristics (3)

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Reference voltage = internal reference voltage selected

Parameter

Min

Typ

Max

12

Unit

bit

Test conditions

Resolution

-

Internal reference voltage (Vbgr)

Resistive load

1.36

1.43

1.50

-

V

30

-

kΩ

pF

V

Load capacitance

-

50

Output voltage range

DNL differential nonlinearity error

INL integral nonlinearity error

Offset error

0.35

-

Vbgr

±16.0

±30

-

±2.0

LSB

mV

Ω

±8.0

-

Output impedance

Conversion time

5

-

30

μs

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2. Electrical Characteristics

Gain error

Full-scale error

Upper output limit

Integral nonlinearity error (INL)

Offset error

1-LSB width for ideal D/A conversion

characteristic

Output analog voltage

Ideal output voltage

Differential nonlinearity error

(DNL)

*1

Lower output limit

Actual D/A conversion characteristic

Offset error

Ideal output voltage

FFFh

000h

D/A converter input code

Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed.

Figure 2.71

Illustration of D/A converter characteristic terms

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion

characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion

characteristics and the width of the actual output voltage.

Offset error

Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the

ideal output voltage based on the input code.

Full-scale error

Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the

ideal output voltage based on the input code.

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2. Electrical Characteristics

2.7

TSN Characteristics

Table 2.54

TSN characteristics

Conditions: VCC = AVCC0 = 2.0 to 5.5 V

Parameter

Symbol

Min

Typ

±1.5

±2.0

-3.65

1.05

-

Max

Unit

°C

Test conditions

Relative accuracy

-

2.4 V or above

-

°C

Below 2.4 V

Temperature slope

-

mV/°C

V

-

Output voltage (at 25°C)

Temperature sensor start time

Sampling time

-

VCC = 3.3 V

t

-

5

-

μs

-

START

-

5

-

μs

2.8

OSC Stop Detect Characteristics

Table 2.55

Oscillation stop detection circuit characteristics

Parameter

Symbol

Min

Typ

Max

Unit

ms

Test conditions

Detection time

t

-

1

Figure 2.72

dr

Main clock

OSTDSR.OSTDF

PLL clock

tdr

OSTDSR.OSTDF

MOCO clock

ICLK

MOCO clock

ICLK

When the main clock is selected

When the PLL clock is selected

Figure 2.72

Oscillation stop detection timing

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2. Electrical Characteristics

2.9

POR and LVD Characteristics

Table 2.56

Power-on reset circuit and voltage detection circuit characteristics (1)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Voltage detection

level*

Power-on reset (POR)

V

1.27

1.42

1.57

V

Figure 2.73,

Figure 2.74

POR

1

2

Voltage detection circuit (LVD0)*

V

3.68

2.68

2.38

1.78

1.60

4.13

3.98

3.86

3.68

2.98

2.89

2.79

2.68

2.58

2.48

2.38

2.10

1.84

1.74

1.63

1.60

4.11

3.97

3.83

3.64

3.85

2.85

2.53

1.90

1.69

4.29

4.16

4.03

3.86

3.10

3.00

2.90

2.79

2.68

2.58

2.48

2.20

1.96

1.86

1.75

1.65

4.31

4.17

4.03

3.84

4.00

2.96

2.64

2.02

1.82

4.45

4.30

4.18

4.00

3.22

3.11

3.01

2.90

2.78

2.68

2.58

2.30

2.05

1.95

1.84

1.73

4.48

4.34

4.20

4.01

V

Figure 2.75

At falling edge

VCC

det0_0

det0_1

det0_2

det0_3

det0_4

det1_0

det1_1

det1_2

det1_3

det1_4

det1_5

det1_6

det1_7

det1_8

det1_9

det1_A

det1_B

det1_C

det1_D

det1_E

det1_F

det2_0

det2_1

det2_2

det2_3

3

Voltage detection circuit (LVD1)*

V

Figure 2.76

At falling edge

VCC

4

Voltage detection circuit (LVD2)*

V

Figure 2.77

At falling edge

VCC

Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection

level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage

detection.

Note 2. # in the symbol V

Note 3. # in the symbol V

Note 4. # in the symbol V

denotes the value of the OFS1.VDSEL1[2:0] bits.

denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.

denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.

det0_#

det1_#

det2_#

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2. Electrical Characteristics

Table 2.57

Parameter

Power-on reset circuit and voltage detection circuit characteristics (2)

Symbol

Min

Typ

Max

Unit

Test conditions

Wait time after power-on

reset cancellation

LVD0:enable

LVD0:disable

LVD0:enable*

t

-

1.7

-

ms

-

POR

-

1.3

0.6

0.2

-

ms

μs

-

POR

1

Wait time after voltage

monitor 0,1,2 reset

cancellation

-

LVD0,1,2

LVD1,2

det

2

LVD0:disable*

-

3

Response delay*

350

Figure 2.73,

Figure 2.74

Minimum VCC down time

Power-on reset enable time

t

450

-

μs

ms

μs

Figure 2.73,

VCC = 1.0 V or above

VOFF

1

-

Figure 2.74,

VCC = below 1.0 V

W (POR)

LVD operation stabilization time (after LVD is

enabled)

T

300

Figure 2.76,

Figure 2.77

d (E-A)

Hysteresis width (POR)

V

-

110

60

-

mV

-

PORH

Hysteresis width (LVD0, LVD1 and LVD2)

LVD0 selected

LVH

100

60

V

to V

selected.

det1_0

det1_3

det1_A

det1_C

det1_2

det1_9

50

or V

det1_B

det1_F

40

60

LVD2 selected

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V

,

POR

V

, V

, and V for the POR/LVD.

det2

det0

det1

t_VOFF

VCC

V_POR

1.0 V

Internal reset signal

(active-low)

t_det

t_dett_POR

Figure 2.73

Voltage detection reset timing

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2. Electrical Characteristics

V_POR

VCC

1.0 V

t_W(POR)

*1

Internal reset signal

(active-low)

t_dett_POR

Note:

t_W(POR)is the time required for a power-on reset to be enabled while the external power VCC is being held

below the valid voltage (1.0 V).

When VCC turns on, maintain t_W(POR)for 1.0 ms or more.

Figure 2.74

Power-on reset timing

t_VOFF

V_LVH

VCC

V_det0

Internal reset signal

(active-low)

t_det

t_LVD0

Figure 2.75

Voltage detection circuit timing (V_det0)

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2. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det1

LVCMPCR.LVD1E

T_d(E-A)

LVD1

Comparator output

LVD1CR0.CMPE

LVD1SR.MON

Internal reset signal

(active-low)

When LVD1CR0.RN = 0

t_det

t_LVD1

t_det

When LVD1CR0.RN = 1

t_LVD1

Figure 2.76

Voltage detection circuit timing (V_det1)

t_VOFF

V_LVH

VCC

V_det2

LVCMPCR.LVD2E

T_d(E-A)

LVD2

Comparator output

LVD2CR0.CMPE

LVD2SR.MON

Internal reset signal

(active-low)

When LVD2CR0.RN = 0

t_det

t_LVD2

When LVD2CR0.RN = 1

t_LVD2

Figure 2.77

Voltage detection circuit timing (V_det2)

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2. Electrical Characteristics

2.10 VBATT Characteristics

Table 2.58

Battery backup function characteristics

Conditions: VCC = AVCC0 = 1.6V to 5.5V, VBATT = 1.6 to 3.6 V

Parameter

Symbol

Min

1.99

-

Typ

2.09

100

-

Max

2.19

-

Unit

V

Test conditions

Voltage level for switching to battery backup (falling)

Hysteresis width for switching to battery back up

VCC-off period for starting power supply switching

V_DETBATT

V_VBATTH

t_VOFFBATT

V_VBATPOR

Figure 2.78,

Figure 2.79

mV

μs

V

300

1.30

-

Voltage detection level

VBATT_Power-on reset (VBATT_POR)

1.40

1.50

Figure 2.78,

Figure 2.79

Wait time after VBATT_POR reset time cancellation

t_VBATPOR

-

3

mS

V

-

Level for detection of voltage drop on

the VBATT pin (falling)

VBTLVDLVL[1:0] = 10b V_DETBATLVD2.11

2.2

2.29

2.08

-

Figure 2.80

VBTLVDLVL[1:0] = 11b

1.92

2

50

-

V

Hysteresis width for VBATT pin LVD

V_VBATLVDTH

t_{d_vbat}

-

mV

μs

VBATT pin LVD operation stabilization time

VBATT pin LVD response delay time

-

300

350

-

Figure 2.80

t_{det_vbat}

-

Allowable voltage change rising/falling gradient

VCC voltage level for access to the VBATT backup registers

dt/dVCC

V_{_BKBATT}

1.0

1.8

-

ms/V

V

-

Note:

The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the

voltage level for switching to battery backup (V_DETBATT).

V_LVH

V_det0

VCC

V_VBATH

V_DETBATT

V_POR

VBATT

V_VBATPOR

Internal reset signal

(active-low)

t_det

VCC supplied

t_LVD0

Backup power area

VBATT supplied

VCC supplied

Figure 2.78

Power supply switching and LVD0 reset timing

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2. Electrical Characteristics

VCC

V_VBATH

V_DETBATT

VBATT

V_VBATPOR

VBATT_POR

(active-low)

t_VBATPOR

Backup power area

VCC supplied

VBATT supplied

not supplied

VCC supplied

Figure 2.79

VBATT_POR reset timing

V_VBATLVDTH

VBATT

V_DETBATLVD

VBTCR2.VBTLVDEN

T_{d_vbat}

VBATT pin LVD

Comparator output

VBTCMPCR.VBTCMPE

VBTSR.VBTBLDF

t_{det_vbat}

Figure 2.80

VBATT pin voltage detection circuit timing

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2. Electrical Characteristics

Table 2.59

Parameter

VBATT-I/O characteristics

Symbol

V_OH

Min

Typ

Max

-

Unit

Test conditions

I_OH= -200 µA

I_OL= 200 µA

I_OH= -100 µA

I_OL= 100 µA

I_OH= -50 µA

I_OL= 50 µA

VBATWIOnI/O VCC > V_DETBATTVCC = 4.0 to 5.5 V

output

characteristics

(n = 0 to 2)

VCC - 0.8

-

V

V_OL

-

0.8

-

VCC = 2.7 to 4.0 V

V_OH

VCC - 0.5

V_OL

-

0.5

-

VCC = V_DETBATTto 2.7 V V_OH

V_OL

VCC - 0.3

-

0.3

-

VCC < V_DETBATTVBATT = 2.7 to 3.6 V

V_OH

V_OL

V_OH

V_OL

V_BATT- 0.5

I_OH= -100 µA

I_OL= 100 µA

I_OH= -50 µA

I_OL= 50 µA

-

0.5

-

VBATT = 1.6 to 2.7 V

V_BATT- 0.3

-

0.3

2.11 CTSU Characteristics

Table 2.60

CTSU characteristics

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

C_tscap

C_base

Min

Typ

Max

11

Unit

Test conditions

External capacitance connected to TSCAP pin

TS pin capacitive load

9

-

10

-

nF

pF

mA

-

50

Permissible output high current

ΣIoH

-

-24

When the mutual

capacitance method

is applied

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RA4M1 Group

2. Electrical Characteristics

2.12 Segment LCD Controller Characteristics

2.12.1

Resistance Division Method

[Static Display Mode]

Table 2.61

Resistance division method LCD characteristics (1)

Conditions: VL4 ≤ VCC ≤ 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

LCD drive voltage

V_L4

2.0

-

VCC

V

-

[1/2 Bias Method, 1/4 Bias Method]

Table 2.62

Resistance division method LCD characteristics (2)

Conditions: VL4 ≤ VCC ≤ 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

LCD drive voltage

V_L4

2.7

-

VCC

V

-

[1/3 Bias Method]

Table 2.63

Resistance division method LCD characteristics (3)

Conditions: VL4 ≤ VCC ≤ 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

LCD drive voltage

V_L4

2.5

-

VCC

V

-

2.12.2

Internal Voltage Boosting Method

[1/3 Bias Method]

Table 2.64 Internal voltage boosting method LCD characteristics

Conditions: VCC = 1.8 V to 5.5 V

Test

Parameter

Symbol Conditions

Min

Typ

Max

1.08

1.13

1.18

1.23

1.28

1.33

1.38

1.43

1.48

1.53

1.58

1.63

1.68

1.73

1.78

1.83

Unit

V

conditions

LCD output voltage

variation range

V_L1

C1 to C4*¹= 0.47 μF VLCD = 04h

VLCD = 05h

0.90

0.95

1.00

1.05

1.10

1.15

1.0

-

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

V

-

VLCD = 06h

V

-

VLCD = 07h

V

-

VLCD = 08h

V

-

VLCD = 09h

V

-

VLCD = 0Ah 1.20

VLCD = 0Bh 1.25

VLCD = 0Ch 1.30

VLCD = 0Dh 1.35

VLCD = 0Eh 1.40

V

-

V

-

V

-

V

-

V

-

VLCD = 0Fh

VLCD = 10h

VLCD = 11h

VLCD = 12h

VLCD = 13h

1.45

V

-

1.50

V

-

1.55

V

-

1.60

V

-

1.65

V

-

Doubler output voltage V_L2

C1 to C4*¹= 0.47 μF

2 × V_L1- 0.1

2 × V_L12 × V_L1

V

-

Tripler output voltage

V_L4

3 × V_L1- 0.15 3 × V_L13 × V_L1

V

-

Reference voltage

setup time*²

t_VL1S

5

-

ms

Figure 2.81

LCD output voltage

variation range*³

t_VLWT

C1 to C4*¹= 0.47 μF

500

-

ms

Note 1. This is a capacitor that is connected between voltage pins used to drive the LCD.

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2. Electrical Characteristics

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between VL1 and GND

C3: A capacitor connected between VL2 and GND

C4: A capacitor connected between VL4 and GND

C1 = C2 = C3 = C4 = 0.47 μF ±30%.

Note 2. This is the time required to wait from when the reference voltage is specified using the VLCD register (or when the internal

voltage boosting method is selected (by setting the MDSET[1:0] bits in the LCDM0 register to 01b) if the default value reference

voltage is used) until voltage boosting starts (VLCON = 1).

Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).

[1/4 Bias Method]

Table 2.65

Internal voltage boosting method LCD characteristics

Conditions: VCC = 1.8 V to 5.5 V

Test

Parameter

Symbol Conditions

Min

Typ

1.0

Max

1.08

1.13

1.18

1.23

1.28

1.33

1.38

1.43

1.48

2V_L1

3V_L1

4V_L1

Unit

V

conditions

LCD output voltage

variation range

V_L1

C1 to C5*¹= 0.47 μF

VLCD = 04h

VLCD = 05h

VLCD = 06h

VLCD = 07h

VLCD = 08h

VLCD = 09h

0.90

0.95

1.00

1.05

1.10

1.15

-

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

V

VLCD = 0Ah 1.20

VLCD = 0Bh 1.25

VLCD = 0Ch 1.30

V

Doubler output voltage V_L2

C1 to C5*¹= 0.47 μF

2V_L1- 0.08 2V_L1

3V_L1- 0.12 3V_L1

4V_L1- 0.16 4V_L1

V

Tripler output voltage

V_L3

V_L4

V

4

Quadruply output

voltage

*

V

Reference voltage

setup time*²

t_VL1S

5

-

ms

Figure 2.81

LCD output voltage

variation range*³

t_VLWT

C1 to C5*¹= 0.47 μF

500

Note 1. This is a capacitor that is connected between voltage pins used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between V_L1and GND

C3: A capacitor connected between V_L2and GND

C4: A capacitor connected between V_L3and GND

C5: A capacitor connected between V_L4and GND

C1 = C2 = C3 = C4 = C5 = 0.47 μF ± 30%

Note 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal

voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits in the LCDM0 register to 01b) if the default

value reference voltage is used) until voltage boosting starts (VLCON = 1).

Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).

Note 4.

V_L4must be 5.5 V or lower.

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2. Electrical Characteristics

2.12.3

Capacitor Split Method

[1/3 Bias Method]

Table 2.66

Internal voltage boosting method LCD characteristics

Conditions: VCC = 2.2 V to 5.5 V

Test

Parameter

Symbol Conditions

Min

Typ

Max

Unit conditions

VL4 voltage*¹

VL2 voltage*¹

VL1 voltage*¹

V_L4

V_L2

V_L1

C1 to C4 = 0.47 μF*²

-

VCC

-

V

-

C1 to C4 = 0.47 μF*²2/3 × V_L4- 0.07 2/3 × V_L4

C1 to C4 = 0.47 μF*²1/3 × V_L4- 0.08 1/3 × V_L4

2/3 × V_L4+ 0.07

V

-

1/3 × V_L4+ 0.08

-

V

-

Capacitor split wait time*¹t_WAIT

100

-

ms

Figure 2.81

Note 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).

Note 2. This is a capacitor that is connected between voltage pins used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between V_L1and GND

C3: A capacitor connected between V_L2and GND

C4: A capacitor connected between V_L4and GND

C1 = C2 = C3 = C4 = 0.47 μF ± 30%.

MDSET0,

MDSET1

00b

01b or 10b

t_VL1S

VLCON

t_VLWT,t_WAIT

LCDON

Figure 2.81

LCD reference voltage setup time, voltage boosting wait time, and capacitor split wait time

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2. Electrical Characteristics

2.13 Comparator Characteristics

Table 2.67

ACMPLP characteristics

Conditions: VCC = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Reference voltage range

Standard

IVREFn (n= 0,1)

VREF

0

-

VCC-1.4

V

-

mode

Window

mode*²

IVREF1

IVREF0

VREFH

1.4

-

VCC

VCC-1.4

VCC

1.50

1.2

5

V

-

VREFL

0

-

V

Input voltage range

Internal reference voltage

Output delay

VI

-

0

-

V

1.36

1.44

V

High-speed mode

Low-speed mode

Window mode

Td

-

μs

mV

μs

VCC = 3.0

Slew rate of input

signal > 50 mV/μs

-

2

Offset voltage*¹

High-speed mode

Low-speed mode

Window mode

-

50

-

40

-

60

Operation stabilization wait time

T_cmp

100

-

Note 1. When 8-bit DAC output is used as the reference voltage, the offset voltage increases up to 2.5 x VCC/256.

Note 2. In window mode, be sure to satisfy the following condition: IVREF1 - IVREF0 ≥ 0.2 V.

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2. Electrical Characteristics

2.14 OPAMP Characteristics

Table 2.68

OPAMP characteristics

Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V)

Parameter

Symbol

Vicm1

Vicm2

Vo1

Conditions

Min

0.2

0.3

0.1

-10

60

-

Typ

-

Max

Unit

V

Common mode input

range

Low power mode

High-speed mode

Low power mode

High-speed mode

3σ

AVCC0 - 0.5

-

AVCC0 - 0.6

V

Output voltage range

-

AVCC0 - 0.1

V

Vo2

-

AVCC0 - 0.1

V

Input offset voltage

Open gain

Vioff

-

10

-

mV

Av

120

0.04

1.7

-

dB

Gain-bandwidth (GB)

product

GBW1

GBW2

PM

Low power mode

High-speed mode

CL = 20 pF

f = 1 kHz

-

MHz

deg

dB

-

Phase margin

50

10

-

Gain margin

GM

-

Equivalent input noise

Vnoise1

Vnoise2

Vnoise3

Vnoise4

PSRR

Low power mode

High-speed mode

230

200

90

70

90

-

nV/√Hz

dB

f = 10 kHz

-

f = 1 kHz

-

f = 2 kHz

-

Power supply

reduction ratio

-

Common mode signal

reduction ratio

CMRR

-

90

-

dB

Stabilization wait time

Tstd1

Tstd2

Tstd3

Tstd4

CL = 20 pF

Only operational amplifier is

activated *¹

Low power mode

High-speed mode

Low power mode

High-speed mode

650

13

-

μs

CL = 20 pF

650

13

Operational amplifier and

reference current circuit are

activated simultaneously

Settling time

Slew rate

Tset1

Tset2

Tslew1

Tslew2

Iload1

Iload2

CL

CL = 20 pF

Low power mode

High-speed mode

Low power mode

High-speed mode

-

750

13

-

μs

-

μs

CL = 20 pF

-

0.02

V/μs

μA

-

1.1

-

Load current

Load capacitance

Low-power mode

High-speed mode

-100

-

100

20

μA

pF

Note 1. When the operational amplifier reference current circuit is activated in advance.

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 111 of 130

RA4M1 Group

2. Electrical Characteristics

2.15 Flash Memory Characteristics

2.15.1

Code Flash Memory Characteristics

Table 2.69

Parameter

Code flash characteristics (1)

Symbol

Min

Typ

Max

Unit

Test conditions

Reprogramming/erasure cycle*¹

Data hold time

N_PEC

1000

20*^2,

-

Times

Year

-

3

After 1000 times of N_PECt_DRP

*

T_a= +85°C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000),

erasing can be done n times for each block. For instance, when 8-byte programming is performed 256 times for different

addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasure is not enabled (overwriting is prohibited).

Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.

Note 3. This result is obtained from reliability testing.

Table 2.70

Code flash characteristics (2)

High-speed operating mode

Conditions: VCC = 2.7 to 5.5 V

FCLK = 1 MHz

FCLK = 32 MHz

Parameter

Symbol Min

Typ

116

9.03

-

Max

Min

Typ

54

5.67

-

Max

Unit

μs

Programming time

Erasure time

8-byte

t_P8

-

2

998

287

56.8

1899

22.5

585

-

2

506

222

16.6

140

10.7

447

-

2-KB

8-byte

2-KB

t_E2K

t_BC8

t_BC2K

t_SED

t_SAS

t_AWS

ms

μs

Blank check time

-

μs

Erase suspended time

-

μs

Startup area switching setting time

Access window time

21.7

-

12.1

-

ms

μs

OCD/serial programmer ID setting time t_OSIS

Flash memory mode transition wait

time 1

t_DIS

Flash memory mode transition wait

time 2

t_MS

5

-

5

-

μs

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

Note:

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 112 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.71

Code flash characteristics (3)

Middle-speed operating mode

Conditions: VCC = 1.8 to 5.5 V, T_a= -40 to +85°C

FCLK = 1 MHz

FCLK = 8 MHz

Parameter

Symbol Min

Typ

Max

Min

Typ

Max

966

228

52.5

414

21.6

464

-

Unit

μs

Programming time

Erasure time

8-byte

2-KB

t_P8

-

157

1411

289

87.7

1930

32.7

592

-

101

t_E2K

t_BC8

t_BC2K

t_SED

t_SAS

t_AWS

t_OSIS

-

9.10

-

6.10

ms

μs

Blank check time

8-byte

2-KB

-

μs

Erase suspended time

-

μs

Startup area switching setting time

Access window time

-

22.5

-

14.0

-

ms

μs

-

OCD/serial programmer ID setting time

-

Flash memory mode transition wait time 1 t_DIS

Flash memory mode transition wait time 2 t_MS

2

720

-

720

-

ns

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

Note:

2.15.2

Data Flash Memory Characteristics

Table 2.72

Parameter

Data flash characteristics (1)

Symbol

N_DPEC

t_DDRP

Min

Typ

Max

Unit

Test conditions

Reprogramming/erasure cycle*¹

Data hold time After 10,000 times of N_DPEC

100,000

1,000,000

-

Times

Year

-

20*^2,

*

T_a= +85°C

3

After 100,000 times of N_DPEC

5*^2,

-

*

-

3

After 1,000,000 times of

N_DPEC

1*^2,

*

T_a= +25°C

Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),

erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different

addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasure is not enabled. Overwriting is prohibited.

Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.

Note 3. These results are obtained from reliability testing.

Table 2.73

Data flash characteristics (2)

High-speed operating mode

Conditions: VCC = 2.7 to 5.5 V

FCLK = 4 MHz

FCLK = 32 MHz

Parameter

Symbol

t_DP1

Min

Typ

Max

Min

Typ

Max

Unit

μs

Programming time

Erasure time

1-byte

-

52.4

463

286

24.3

1872

13.0

-

42.1

387

237

16.6

512

10.7

-

1-KB

1-byte

1-KB

t_DE1K

-

8.98

-

6.42

ms

μs

Blank check time

t_DBC1

-

t_DBC1K

t_DSED

t_DSTOP

-

μs

Suspended time during erasing

Data flash STOP recovery time

-

μs

5

μs

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

Note:

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 113 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.74

Data flash characteristics (3)

Middle-speed operating mode

Conditions: VCC = 1.8 to 5.5 V, T_a= -40 to +85°C

FCLK = 4 MHz

FCLK = 8 MHz

Parameter

Symbol

t_DP1

Min

Typ

Max

Min

Typ

Max

849

273

52.5

1.51

21.7

-

Unit

μs

Programming time

Erasure time

1-byte

1-KB

-

94.7

886

299

56.2

2.17

23.0

-

89.3

t_DE1K

-

9.59

-

8.29

ms

μs

Blank check time

1-byte

1-KB

t_DBC1

-

t_DBC1K

t_DSED

t_DSTOP

-

ms

μs

Suspended time during erasing

Data flash STOP recovery time

-

720

ns

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below

4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.

The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

Note:

2.16 Boundary Scan

Table 2.75

Boundary scan

Conditions: VCC = AVCC0 = 2.4 to 5.5 V

Parameter

Symbol

t_TCKcyc

t_TCKH

t_TCKL

Min

100

45

-

Typ

Max

Unit

ns

-

Test conditions

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TMS setup time

-

Figure 2.82

-

t_TCKr

5

-

t_TCKf

-

t_TMSS

t_TMSH

t_TDIS

20

-

Figure 2.83

Figure 2.84

TMS hold time

-

TDI setup time

-

TDI hold time

t_TDIH

-

TDO data delay

t_TDOD

t_BSSTUP

70

-

Boundary Scan circuit start up time*¹

t_RESWP

Note 1. Boundary scan does not function until power-on-reset becomes negative.

t_TCKcyc

t_TCKH

t_TCKf

TCK

t_TCKr

t_TCKL

Figure 2.82

Boundary scan TCK timing

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 114 of 130

RA4M1 Group

2. Electrical Characteristics

TCK

TMS

TDI

t_TMSS

t_TMSH

t_TDIS

t_TDIH

t_TDOD

TDO

Figure 2.83

Boundary scan input/output timing

VCC

RES

t_BSSTUP

(= t_RESWP

Boundary scan

execute

)

Figure 2.84

Boundary scan circuit start up timing

2.17 Joint Test Action Group (JTAG)

Table 2.76

JTAG (debug) characteristics (1)

Conditions: VCC = 2.4 to 5.5 V

Parameter

Symbol

t_TCKcyc

t_TCKH

t_TCKL

t_TCKr

Min

80

35

-

Typ

Max

Unit

ns

Test conditions

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TMS setup time

-

Figure 2.85

-

5

-

t_TCKf

-

t_TMSS

t_TMSH

t_TDIS

16

-

Figure 2.86

TMS hold time

-

TDI setup time

-

TDI hold time

t_TDIH

-

TDO data delay time

t_TDOD

70

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 115 of 130

RA4M1 Group

2. Electrical Characteristics

Table 2.77

JTAG (debug) characteristics (2)

Conditions: VCC = 1.6 to 2.4 V

Parameter

Symbol

t_TCKcyc

t_TCKH

t_TCKL

t_TCKr

Min

250

120

-

Typ

Max

Unit

ns

Test conditions

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TMS setup time

-

Figure 2.85

-

5

t_TCKf

-

5

t_TMSS

t_TMSH

t_TDIS

50

-

Figure 2.86

TMS hold time

-

TDI setup time

-

TDI hold time

t_TDIH

-

TDO data delay time

t_TDOD

150

t_TCKcyc

t_TCKH

TCK

t_TCKf

t_TCKr

t_TCKL

Figure 2.85

JTAG TCK timing

TCK

TMS

t_TMSS

t_TMSH

t_TDIS

t_TDIH

TDI

t_TDOD

TDO

Figure 2.86

JTAG input/output timing

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 116 of 130

RA4M1 Group

2.17.1

2. Electrical Characteristics

Serial Wire Debug (SWD)

Table 2.78

SWD characteristics (1)

Conditions: VCC = 2.4 to 5.5 V

Parameter

Symbol

t_SWCKcyc

t_SWCKH

t_SWCKL

t_SWCKr

t_SWCKf

t_SWDS

Min

80

35

-

Typ

Max

Unit

ns

Test conditions

SWCLK clock cycle time

SWCLK clock high pulse width

SWCLK clock low pulse width

SWCLK clock rise time

SWCLK clock fall time

SWDIO setup time

-

Figure 2.87

-

5

-

16

2

Figure 2.88

SWDIO hold time

t_SWDH

-

SWDIO data delay time

t_SWDD

70

Table 2.79

SWD characteristics (2)

Conditions: VCC = 1.6 to 2.4 V

Parameter

Symbol

t_SWCKcyc

t_SWCKH

t_SWCKL

t_SWCKr

t_SWCKf

t_SWDS

Min

250

120

-

Typ

Max

Unit

ns

Test conditions

SWCLK clock cycle time

SWCLK clock high pulse width

SWCLK clock low pulse width

SWCLK clock rise time

SWCLK clock fall time

SWDIO setup time

-

Figure 2.87

-

5

-

5

50

2

-

Figure 2.88

SWDIO hold time

t_SWDH

-

SWDIO data delay time

t_SWDD

150

t_SWCKcyc

t_SWCKH

SWCLK

t_SWCKf

t_SWCKr

t_SWCKL

Figure 2.87

SWD SWCLK timing

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 117 of 130

RA4M1 Group

2. Electrical Characteristics

SWCLK

t_SWDSt_SWDH

SWDIO

(Input)

t_SWDD

SWDIO

(Output)

t_SWDD

SWDIO

(Output)

t_SWDD

SWDIO

(Output)

Figure 2.88

SWD input/output timing

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 118 of 130

RA4M1 Group

Appendix 1. Package Dimensions

Appendix 1.Package Dimensions

Information on the latest version of the package dimensions or mountings is shown in “Packages” on the Renesas

Electronics Corporation website.

JEITA Package Code

P-TFLGA100-7x7-0.65

RENESAS Code

PTLG0100JA-A

Previous Code

100F0G

MASS[Typ.]

0.1g

φ b₁

φ

×

M

S

AB

φ b

D

φ×

M

S

AB

w

S A

Z_D

e

A

K

J

H

G

F

B

E

D

C

B

A

Dimension in Millimeters

Reference

Symbol

Min Nom Max

7.0

1

2

3

4

5

6

7

8

9

10

y

S

×

4

D

E

v

Index mark

S

(Laser mark)

0.15

w

A

e

0.20

1.05

0.65

0.31 0.35 0.39

b

b₁0.385 0.435 0.485

x

0.08

0.10

y

Z_D

Z_E

0.575

Figure 1.1

100-pin LGA

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 119 of 130

RA4M1 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

0.6

P-LFQFP100-14x14-0.50

PLQP0100KB-B

—

H_D

Unit: mm

*1

D

75

51

76

50

100

26

1

25

NOTE 4

NOTE)

Index area

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

NOTE 3

F

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Dimensions in millimeters

Min Nom Max

Reference

Symbol

y

S

*3

b

p

e

M

D

E

A₂

H_D

H_E

A

A₁

b_p

c

13.9

14.0 14.1

1.4

15.8

16.0 16.2

1.7

0.15

0.05

0.15

0.09

0q

0.20 0.27

3.5q

0.5

0.20

8q

L_p

L₁

T

e

x

y

L_p

L₁

Detail F

0.08

0.75

0.45

0.6

1.0

Figure 1.2

100-pin LQFP

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 120 of 130

RA4M1 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

0.3

P-LFQFP64-10x10-0.50

PLQP0064KB-C

—

Unit: mm

H_D

*1

D

48

33

49

32

64

17

1

16

NOTE 4

Index area

NOTE 3

NOTE)

F

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

y

S

*3

Dimensions in millimeters

Min Nom Max

Reference

Symbol

b

p

e

M

D

E

A₂

H_D

H_E

A

A₁

b_p

c

9.9

10.0 10.1

1.4

11.8

12.0 12.2

1.7

0.15

0.05

0.15

0.09

0q

0.20 0.27

3.5q

0.5

0.20

8q

L_p

L₁

T

e

x

y

L_p

L₁

Detail F

0.08

0.75

0.45

0.6

1.0

Figure 1.3

64-pin LQFP

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 121 of 130

RA4M1 Group

Appendix 1. Package Dimensions

JEITA Package code

RENESAS code

Previous code

MASS(TYP.)[g]

P-HWQFN64-8x8-0.40

PWQN0064LA-A

P64K8-40-9B5-3

0.16

D

33

48

32

49

DETAIL OF A PART

E

A

A₁

c₂

64

17

16

1

INDEX AREA

A

S

y

S

Dimension in Millimeters

Referance

Symbol

Nom

8.00

Max

8.05

0.80

Min

7.95

D

E

D₂

A

EXPOSED DIE PAD

Lp

A

16

1

A₁

b

0.00

0.17

0.23

0.20

0.40

64

17

e

0.30

0.15

0.50

0.05

Lp

x

B

E₂

y

Z_D

Z_E

c₂

1.00

0.20

6.50

Z_E

32

49

0.25

48

33

D₂

E₂

Z_D

e

M

b

x

S A B

Figure 1.4

64-pin QFN

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 122 of 130

RA4M1 Group

Appendix 1. Package Dimensions

RENESAS Code

Previous Code

MASS (Typ) [g]

JEITA Package Code

0.2

P-LFQFP48-7x7-0.50

PLQP0048KB-B

—

H_D

D

Unit: mm

*1

36

25

37

24

48

13

1

12

NOTE 4

Index area

NOTE 3

NOTE)

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

F

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

S

Dimensions in millimeters

Min Nom Max

Reference

Symbol

D

E

6.9

7.0

1.4

9.0

7.1

y

S

*3

b

p

e

M

A₂

H_D

H_E

A

8.8

9.2

1.7

0.15

A₁

b_p

c

0.05

0.17

0.09

0q

0.20 0.27

3.5q

0.5

0.20

8q

T

L_p

L₁

e

x

0.08

0.75

Detail F

y

L_p

L₁

0.45

0.6

1.0

Figure 1.5

48-pin LQFP

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 123 of 130

RA4M1 Group

Appendix 1. Package Dimensions

JEITA Package code

RENESAS code

Previous code

MASS(TYP.)[g]

48PJN-A

P48K8-50-5B4-6

P-HWQFN48-7x7-0.50

PWQN0048KB-A

0.13

D

25

36

24

37

DETAIL OF A PART

E

A

A₁

c₂

13

48

12

1

INDEX AREA

A

S

y

S

Dimension in Millimeters

Referance

Symbol

Nom

7.00

Max

7.05

0.80

Min

6.95

D

E

D₂

A

EXPOSED DIE PAD

Lp

A

12

1

A₁

b

0.00

0.18

13

0.30

0.25

0.50

0.40

48

e

0.30

0.15

0.50

0.05

Lp

x

B

E₂

y

Z_D

Z_E

c₂

0.75

0.20

5.50

Z_E

37

24

0.25

36

25

D₂

E₂

Z_D

e

M

b

x

S A B

Figure 1.6

48-pin QFN

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 124 of 130

RA4M1 Group

Appendix 1. Package Dimensions

JEITA Package code

RENESAS code

Previous code

MASS(TYP.)[g]

P-HWQFN40-6x6-0.50

PWQN0040KC-A

P40K8-50-4B4-5

0.09

D

21

30

20

31

DETAIL OF A PART

E

A

40

11

A₁

c₂

10

1

INDEX AREA

A

S

y

S

Dimension in Millimeters

Referance

Symbol

Nom

6.00

Max

6.05

0.80

Min

5.95

D

E

D₂

A

Lp

EXPOSED DIE PAD

A

1

10

A₁

b

0.00

0.18

0.30

11

0.25

0.50

0.40

40

e

0.30

0.15

0.50

0.05

Lp

x

B

E₂

y

Z_D

Z_E

c₂

0.75

0.20

4.50

Z_E

20

31

0.25

30

21

D₂

E₂

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e

M

b

x

S

A B

Figure 1.7

40-pin QFN

R01DS0355EJ0100 Rev.1.00

Oct 8, 2019

Page 125 of 130

Revision History

RA4M1Group Datasheet

Rev.

1.00

Date

Summary

Oct 8, 2019

First release

Proprietary Notice

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part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated,

transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior

written consent from Renesas.

®

Arm and Cortex are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.

®

CoreMark is a registered trademark of the Embedded Microprocessor Benchmark Consortium.

Magic Packet™ is a trademark of Advanced Micro Devices, Inc.

®

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States

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Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective

holders.

Colophon

RA4M1 Group Datasheet

Publication Date:

Published by:

Rev.1.00

Oct 8, 2019

Renesas Electronics Corporation

Address List

General Precautions

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately

degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and

quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.

This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be

stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit

boards with mounted semiconductor devices.

2. Processing at power-on

The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are

indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished

product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time

when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset

by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches

the level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results

from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in

the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-

off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins

of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,

extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,

and malfunctions occur due to the false recognition of the pin state as an input signal become possible.

5. Clock signals

After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the

clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated

with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full

stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or

by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device

stays in the area between V (Max.) and V (Min.) due to noise, for example, the device may malfunction. Take care to

IL

IH

prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the

input level passes through the area between V (Max.) and V (Min.).

IL

IH

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of

functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the

change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the

same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and

other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,

immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a

system-evaluation test for the given product.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

equipment; industrial robots; etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

not intended or authorized for use in products or systems that may pose

a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause

serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all

liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	R7FA4M1AB3CFM
厂家：	RENESAS TECHNOLOGY CORP
描述：	High efficiency 48-MHz Arm Cortex-M4 core, 256-KB code flash memory
文件：	总130页 (文件大小：1782K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R7FA4M1AB3CFM [RENESAS]

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