R7FA6M1AD3CFP_技术文档

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Renesas RA6M1 Group

32

Datasheet

32-bit MCU

Renesas Advanced (RA) Family

Renesas RA6 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

Rev.1.00 Oct 2019

RA6M1 Group

Datasheet

Leading performance 120-MHz Arm^®Cortex^®-M4 core, 512-KB code flash memory, 256-KB SRAM, Capacitive

Touch Sensing Unit, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog.

Features

■ Arm Cortex-M4 Core with Floating Point Unit (FPU)

 Armv7E-M architecture with DSP instruction set

 Maximum operating frequency: 120 MHz

■ System and Power Management

 Low power modes

 Realtime Clock (RTC) with calendar and VBATT support

 Event Link Controller (ELC)

 DMA Controller (DMAC) × 8

 Support for 4-GB address space

 On-chip debugging system: JTAG, SWD, and ETM

 Boundary scan and Arm Memory Protection Unit (Arm MPU)

 Data Transfer Controller (DTC)

 Key Interrupt Function (KINT)

 Power-on reset

■ Memory

 512-KB code flash memory (40 MHz zero wait states)

 8-KB data flash memory (125,000 erase/write cycles)

 256-KB SRAM

 Low Voltage Detection (LVD) with voltage settings

■ Security and Encryption

 AES128/192/256

 3DES/ARC4

 SHA1/SHA224/SHA256/MD5

 GHASH

 RSA/DSA/ECC

 True Random Number Generator (TRNG)

 Flash Cache (FCACHE)

 Memory Protection Units (MPU)

 Memory Mirror Function (MMF)

 128-bit unique ID

■ Connectivity

 USB 2.0 Full-Speed (USBFS) module

- On-chip transceiver

■ Human Machine Interface (HMI)

 Serial Communications Interface (SCI) with FIFO × 7

 Serial Peripheral Interface (SPI) × 2

 I²C bus interface (IIC) × 2

 Capacitive Touch Sensing Unit (CTSU)

■ Multiple Clock Sources

 Main clock oscillator (MOSC) (8 to 24 MHz)

 Sub-clock oscillator (SOSC) (32.768 kHz)

 High-speed on-chip oscillator (HOCO) (16/18/20 MHz)

 Middle-speed on-chip oscillator (MOCO) (8 MHz)

 Low-speed on-chip oscillator (LOCO) (32.768 kHz)

 IWDT-dedicated on-chip oscillator (15 kHz)

 Clock trim function for HOCO/MOCO/LOCO

 Clock out support

 CAN module (CAN) × 2

 Serial Sound Interface Enhanced (SSIE)

 SD/MMC Host Interface (SDHI) × 2

 Quad Serial Peripheral Interface (QSPI)

 IrDA interface

 Sampling Rate Converter (SRC)

 External address space

- 8-bit bus space

■ General-Purpose I/O Ports

 Up to 76 input/output pins

- Up to 9 CMOS input

■ Analog

 12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits

each × 2

 12-bit D/A Converter (DAC12) × 2

 High-Speed Analog Comparator (ACMPHS) × 6

 Programmable Gain Amplifier (PGA) × 6

 Temperature Sensor (TSN)

- Up to 67 CMOS input/output

- Up to 14 input/output 5 V tolerant

- Up to 13 high current (20 mA)

■ Operating Voltage

 VCC: 2.7 to 3.6 V

■ Timers

■ Operating Temperature and Packages

 Ta = -40°C to +85°C

- 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)

 Ta = -40°C to +105°C

 General PWM Timer 32-bit Enhanced High Resolution

(GPT32EH) × 4

 General PWM Timer 32-bit Enhanced (GPT32E) × 4

 General PWM Timer 32-bit (GPT32) × 5

 Asynchronous General-Purpose Timer (AGT) × 2

 Watchdog Timer (WDT)

- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)

- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)

- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)

■ Safety

 Error Code Correction (ECC) in SRAM

 SRAM parity error check

 Flash area protection

 ADC self-diagnosis function

 Clock Frequency Accuracy Measurement Circuit (CAC)

 Cyclic Redundancy Check (CRC) calculator

 Data Operation Circuit (DOC)

 Port Output Enable for GPT (POEG)

 Independent Watchdog Timer (IWDT)

 GPIO readback level detection

 Register write protection

 Main oscillator stop detection

 Illegal memory access

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RA6M1 Group

1. Overview

1.

Overview

®

The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set

of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

®

The MCU in this series incorporates a high-performance Arm Cortex -M4 core running up to 120 MHz with the

following features:



512-KB code flash memory

256-KB SRAM

Capacitive Touch Sensing Unit (CTSU)

USBFS

SD/MMC Host Interface

Quad Serial Peripheral Interface (QSPI)

Security and safety features

12-bit A/D Converter (ADC12)

12-bit D/A Converter (DAC12)

Analog peripherals.

1.1

Function Outline

Table 1.1

Feature

Arm core

Functional description

Arm Cortex-M4 core

 Maximum operating frequency: up to 120 MHz

 Arm Cortex-M4 core:

- Revision: r0p1-01rel0

- Armv7E-M architecture profile

- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.

 Arm Memory Protection Unit (Arm MPU):

- Armv7 Protected Memory System Architecture

- 8 protect regions.

 SysTick timer:

- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2

Memory

Feature

Functional description

Code flash memory

Data flash memory

Memory Mirror Function (MMF)

512-KB code flash memory. See section 50, Flash Memory in User’s Manual.

8-KB data flash memory. See section 50, Flash Memory in User’s Manual.

The Memory Mirror Function (MMF) can be configured to mirror the target application image

load address in code flash memory to the application image link address in the 23-bit unused

memory space (memory mirror space addresses). Your application code is developed and

linked to run from this MMF destination address. Your application code does not need to know

the load location where it is stored in code flash memory. See section 5, Memory Mirror

Function (MMF) in User’s Manual.

Option-setting memory

SRAM

The option-setting memory determines the state of the MCU after a reset. See section 7,

Option-Setting Memory in User’s Manual.

On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). The first

32 KB of SRAM0 provides error correction capability using ECC. Parity check is performed for

other areas. See section 48, SRAM in User’s Manual.

Standby SRAM

On-chip SRAM that can retain data in Deep Software Standby mode. See section 49, Standby

SRAM in User’s Manual.

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1. Overview

Table 1.3

Feature

System (1 of 2)

Functional description

Operating modes

Two operating modes:

 Single-chip mode

 SCI or USB boot mode.

See section 3, Operating Modes in User’s Manual.

Resets

14 resets:

 RES pin reset

 Power-on reset

 Voltage monitor 0 reset

 Voltage monitor 1 reset

 Voltage monitor 2 reset

 Independent watchdog timer reset

 Watchdog timer reset

 Deep Software Standby reset

 SRAM parity error reset

 SRAM ECC error reset

 Bus master MPU error reset

 Bus slave MPU error reset

 Stack pointer error reset

 Software reset.

See section 6, Resets in User’s Manual.

Low Voltage Detection (LVD)

Clocks

The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and

the detection level can be selected using a software program. See section 8, Low Voltage

Detection (LVD) in User’s Manual.

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 PLL frequency synthesizer

 IDWT-dedicated on-chip oscillator

 Clock out support.

See section 9, Clock Generation Circuit in User’s Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock to be used as a

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.

When measurement is complete or the number of pulses within the time generated by the

measurement reference clock is not within the allowable range, an interrupt request is

generated.

See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual.

Interrupt Controller Unit (ICU)

Key Interrupt Function (KINT)

Low power modes

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt

Controller Unit (ICU) in User’s Manual in User’s Manual.

A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting

a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function

(KINT) in User’s Manual.

Power consumption can be reduced in multiple ways, such as by setting clock dividers,

controlling EBCLK output, stopping modules, selecting power control mode in normal

operation, and transitioning to low power modes. See section 11, Low Power Modes in User’s

Manual.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery-powered

area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See

section 12, Battery Backup Function in User’s Manual.

Register write protection

The register write protection function protects important registers from being overwritten

because of software errors. See section 13, Register Write Protection in User’s Manual.

Memory Protection Unit (MPU)

Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided

for memory protection. See section 16, Memory Protection Unit (MPU) in User’s Manual.

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1. Overview

Table 1.3

Feature

System (2 of 2)

Functional description

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow.

A refresh-permitted period can be set to refresh the counter and used as the condition for

detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in

User’s Manual.

Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt or interrupt for a timer underflow. Because

the timer operates with an independent, dedicated clock source, it is particularly useful in

returning the MCU to a known state as a fail-safe mechanism when the system runs out of

control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by

a refresh of the count value in the registers. See section 28, Independent Watchdog Timer

(IWDT) in User’s Manual.

Table 1.4

Feature

Event link

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 19, Event Link Controller (ELC)

in User’s Manual.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request. See section 18, Data Transfer Controller (DTC) in User’s Manual.

DMA Controller (DMAC)

An 8-channel DMA Controller (DMAC) module is provided for transferring data without the

CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the

transfer source address to the transfer destination address. See section 17, DMA Controller

(DMAC) in User’s Manual.

Table 1.6

External bus interface

Feature

Functional description

External buses

 CS area (EXBIU): Connected to the external devices (external memory interface)

 QSPI area (EXBIUT2): Connected to the QSPI (external device interface).

Table 1.7

Feature

Timers (1 of 2)

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with 13 channels. PWM waveforms can be

generated by controlling the up-counter, down-counter, or up- and down-counter. In addition,

PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be

used as a general-purpose timer. See section 23, General PWM Timer (GPT) in User’s

Manual.

Port Output Enable for GPT (POEG)

Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in

User’s Manual.

Asynchronous General-Purpose

Timer (AGT)

The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse

output, external pulse width or period measurement, and counting of external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and can be accessed with the AGT register.

See section 25, Asynchronous General-Purpose Timer (AGT) in User’s Manual.

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1. Overview

Table 1.7

Feature

Timers (2 of 2)

Functional description

Realtime Clock (RTC)

The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count

mode, that are controlled by the register settings.

For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and

automatically adjusts dates for leap years.

For binary count mode, the RTC counts seconds and retains the information as a serial value.

Binary count mode can be used for calendars other than the Gregorian (Western) calendar.

See section 26, Realtime Clock (RTC) in User’s Manual.

Table 1.8

Feature

Communication interfaces (1 of 2)

Functional description

Serial Communications Interface

(SCI)

The Serial Communications Interface (SCI) is configurable to five asynchronous and

synchronous serial interfaces:

 Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter

(ACIA))

 8-bit clock synchronous interface

 Simple IIC (master-only)

 Simple SPI

 Smart card interface.

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol.

Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data

transfer speed can section 30, Serial Communications Interface (SCI)be configured

independently using an on-chip baud rate generator. See in User’s Manual.

IrDA Interface (IrDA)

The IrDA interface sends and receives IrDA data communication waveforms in cooperation

with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 31,

IrDA Interface in User’s Manual.

I²C bus interface (IIC)

The 2-channel I²C bus interface (IIC) conforms with and provides a subset of the NXP I²C

(Inter-Integrated Circuit) bus interface functions. See section 32, I2C Bus Interface (IIC) in

User’s Manual.

Serial Peripheral Interface (SPI)

Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-

duplex synchronous serial communications with multiple processors and peripheral devices.

See section 34, Serial Peripheral Interface (SPI) in User’s Manual.

Serial Sound Interface Enhanced

(SSIE)

The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with

digital audio devices for transmitting I²S (Inter-Integrated Sound) 2ch, 4ch, 6ch, 8ch, Word

Select (WS) Continue/Monaural/TDM audio data over a serial bus. The SSIE supports an

audio clock frequency of up to 50 MHz, and can be operated as a slave or master receiver,

transmitter, or transceiver to suit various applications. The SSIE includes 32-stage FIFO

buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception

and transmission. See section 37, Serial Sound Interface Enhanced (SSIE) in User’s Manual.

Quad Serial Peripheral Interface

(QSPI)

The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial

ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM)

that has an SPI-compatible interface. See section 35, Quad Serial Peripheral Interface (QSPI)

in User’s Manual.

Controller Area Network (CAN)

module

The Controller Area Network (CAN) module provides functionality to receive and transmit data

using a message-based protocol between multiple slaves and masters in electromagnetically-

noisy applications.

The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports

up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox

and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are

supported. See section 33, Controller Area Network (CAN) Module in User’s Manual.

USB 2.0 Full-Speed Module (USBFS) The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller.

module

The module supports full-speed and low-speed (host controller only) transfer as defined in the

Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and

supports all of the transfer types defined in the Universal Serial Bus Specification 2.0.

The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9

can be assigned any endpoint number based on the peripheral devices used for

communication or based on your system. See section 29, USB 2.0 Full-Speed Module

(USBFS) in User’s Manual.

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RA6M1 Group

1. Overview

Table 1.8

Feature

Communication interfaces (2 of 2)

Functional description

SD/MMC Host Interface (SDHI)

The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to

connect a variety of external memory cards to the MCU. The SDHI supports both 1-bit and 4-

bit buses for connecting memory cards that support SD, SDHC, and SDXC formats. When

developing host devices that are compliant with the SD Specifications, you must comply with

the SD Host/Ancillary Product License Agreement (SD HALA).

The MMC interface supports 1-bit and 4-bit MMC buses that provide eMMC 4.51 (JEDEC

Standard JESD 84-B451) device access. This interface also provides backward compatibility

and supports high-speed SDR transfer modes. See section 39, SD/MMC Host Interface

(SDHI) in User’s Manual.

Table 1.9

Feature

Analog

Functional description

12-bit A/D Converter (ADC12)

Up to two successive approximation 12-bit A/D Converters (ADC12) are provided. In unit 0, up

to 11 analog input channels are selectable. In unit 1, up to eight analog input channels, the

temperature sensor output, and an internal reference voltage are selectable for conversion.

The A/D conversion accuracy is selectable from 12-bit, 10-bit, and 8-bit conversion, making it

possible to optimize the tradeoff between speed and resolution in generating a digital value.

See section 42, 12-Bit A/D Converter (ADC12) in User’s Manual.

12-bit D/A Converter (DAC12)

Temperature Sensor (TSN)

A 12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section

43, 12-Bit D/A Converter (DAC12) in User’s Manual.

The on-chip Temperature Sensor (TSN) can determine and monitor the die temperature for

reliable operation of the device. The sensor outputs a voltage directly proportional to the die

temperature, and the relationship between the die temperature and the output voltage is linear.

The output voltage is provided to the ADC12 for conversion and can also be used by the end

application. See section 44, Temperature Sensor (TSN) in User’s Manual.

High-Speed Analog Comparator

(ACMPHS)

The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference

voltage and provides a digital output based on the conversion result.

Both the test and reference voltages can be provided to the comparator from internal sources

such as the DAC12 output and internal reference voltage, and an external source with or

without an internal PGA.

Such flexibility is useful in applications that require go/no-go comparisons to be performed

between analog signals without necessarily requiring A/D conversion. See section 45, High-

Speed Analog Comparator (ACMPHS) in User’s Manual.

Table 1.10

Feature

Human machine interfaces

Functional description

Capacitive Touch Sensing Unit

(CTSU)

The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the

touch sensor. Changes in the electrostatic capacitance are determined by software, which

enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode

surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do

not come into direct contact with the electrodes. See section 46, Capacitive Touch Sensing

Unit (CTSU) in User’s Manual.

Table 1.11

Feature

Data processing (1 of 2)

Functional description

Cyclic Redundancy Check (CRC)

calculator

The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the

data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first

communication. Additionally, various CRC-generating polynomials are available. The snoop

function allows monitoring reads from and writes to specific addresses. This function is useful

in applications that require CRC code to be generated automatically in certain events, such as

monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See

section 36, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.

Data Operation Circuit (DOC)

The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 47,

Data Operation Circuit (DOC) in User’s Manual.

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1. Overview

Table 1.11

Feature

Data processing (2 of 2)

Functional description

Sampling Rate Converter (SRC)

The Sampling Rate Converter (SRC) converts the sampling rate of data produced by various

audio decoders, such as the WMA, MP3, and AAC. Both 16-bit stereo and monaural data are

supported.

See section 38, Sampling Rate Converter (SRC) in User’s Manual.

Table 1.12

Feature

Security

Functional description

Secure Crypto Engine 7 (SCE7)

 Security algorithms:

- Symmetric algorithms: AES, 3DES, and ARC4

- Asymmetric algorithms: RSA, DSA, and ECC.

 Other support features:

- TRNG (True Random Number Generator)

- Hash-value generation: SHA1, SHA224, SHA256, GHASH, and MD5

- 128-bit unique ID.

1.2

Block Diagram

Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the

features.

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RA6M1 Group

1. Overview

Memory

Bus

Arm Cortex-M4

System

Clocks

512 KB code flash

8 KB data flash

256 KB SRAM

DSP

FPU

POR/LVD

Reset

External

CSC

MOSC/SOSC

(H/M/L) OCO

PLL

MPU

NVIC

MPU

Mode control

8 KB Standby

SRAM

System timer

Test and DBG interface

Power control

ICU

CAC

DMA

DTC

Battery backup

Register write

protection

KINT

DMAC × 8

Timers

Communication interfaces

Human machine interfaces

CTSU

SCI × 7

QSPI

GPT32EH x 4

GPT32E x 4

GPT32 x 5

IrDA × 1

IIC × 2

SDHI × 2

CAN × 2

SPI × 2

AGT × 2

RTC

SSIE

USBFS

WDT/IWDT

Event link

ELC

Data processing

Analog

TSN

ADC12 with

PGA × 2

CRC

SRC

DOC

DAC12

ACMPHS × 6

Security

SCE7

Figure 1.1

Block diagram

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RA6M1 Group

1. Overview

1.3

Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.13 shows a

list of products.

# A A

R 7 F A 6 M 1 A D 3 C F P

0

Production identification code

Packaging, Terminal material (Pb-free)

#AA: Tray/Sn (Tin) only

#AC: Tray/others

Package type

FP: LQFP 100 pins

FM: LQFP 64 pins

LJ: LGA 100 pins

NB: QFN 64 pins

Quality Grade

Operating temperature

2: -40^°C to 85^°C

3: -40^°C to 105^°C

Code flash memory size

D: 512 KB

Feature set

Group number

Series name

RA family

Flash memory

Renesas microcontroller

Figure 1.2

Part numbering scheme

Product list

Table 1.13

Operating

temperature

Product part number

R7FA6M1AD2CLJ

R7FA6M1AD3CFP

R7FA6M1AD3CFM

R7FA6M1AD3CNB

Orderable part number

R7FA6M1AD2CLJ#AC0

R7FA6M1AD3CFP#AA0

R7FA6M1AD3CFM#AA0

R7FA6M1AD3CNB#AC0

Package code

PTLG0100JA-A

PLQP0100KB-B

PLQP0064KB-C

PWQN0064LA-A

Code flash Data flash SRAM

512 KB

8 KB

256 KB -40 to +85°C

-40 to +105°C

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RA6M1 Group

1. Overview

1.4

Function Comparison

Table 1.14

Functional comparison

Part numbers

R7FA6M1AD2CLJ

100

Function

R7FA6M1AD3CFP

100

R7FA6M1AD3CFM

R7FA6M1AD3CNB

Pin count

64

Package

LGA

LQFP

QFN

Code flash memory

Data flash memory

SRAM

512 KB

8 KB

256 KB

224 KB

32 KB

Parity

ECC

Standby SRAM

System

8 KB

CPU clock

120 MHz

512 B

Backup

registers

ICU

Yes

8

KINT

Event link

DMA

ELC

Yes

8

DTC

DMAC

External bus

GPT32EH

GPT32E

GPT32

AGT

BUS

8-bit bus

No

Timers

4

5

3

4

2

Yes

7

RTC

WDT/IWDT

SCI

Communication

IIC

2

SPI

2

SSIE

1

2

No

QSPI

1

SDHI

CAN

2

USBFS

ADC12

DAC12

ACMPHS

TSN

Yes

Analog

HMI

19

12

10

7

2

6

Yes

CTSU

Data processing CRC

Yes

DOC

SRC

Yes

Security

SCE7

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 11 of 92

RA6M1 Group

1. Overview

1.5

Pin Functions

Table 1.15

Pin functions (1 of 4)

Function

Signal

I/O

Description

Power supply

VCC

Input

Power supply pin. This is used as the digital power supply for the respective

modules and internal voltage regulator, and used to monitor the voltage of

the POR/LVD. Connect this pin to the system power supply. Connect it to

VSS by a 0.1-μF capacitor. Place the capacitor close to the pin.

VCL0

VCL

Input

Connect this pin to VSS through a 0.1-μF smoothing capacitor used to

stabilize the internal power supply. Place the capacitor close to the pin.

Input

VSS

Input

Ground pin. Connect to the system power supply (0 V).

Backup power pin

VBATT

XTAL

Input

Clock

Output

Input

Pins for a crystal resonator. An external clock signal can be input through the

EXTAL pin.

EXTAL

XCIN

Input

Input/output pins for the sub-clock oscillator. Connect a crystal resonator

between XCOUT and XCIN.

XCOUT

EBCLK

CLKOUT

MD

Output

Input

Outputs the external bus clock for external devices

Clock output pin

Operating mode

control

Pin for setting the operating mode. The signal level on this pin must not be

changed during operation mode transition on release from the reset state.

System control

RES

Input

Reset signal input pin. The MCU enters the reset state when this signal goes

low.

CAC

CACREF

Input

Measurement reference clock input pin

Non-maskable interrupt request pin

Maskable interrupt request pins

Interrupt

NMI

IRQ0 to IRQ13

KR00 to KR07

KINT

A key interrupt can be generated by inputting a falling edge to the key

interrupt input pins

On-chip emulator

TMS

I/O

On-chip emulator or boundary scan pins

TDI

Input

Output

I/O

TCK

TDO

TCLK

This pin outputs the clock for synchronization with the trace data

Trace data output

TDATA0 to TDATA3

SWDIO

SWCLK

SWO

Serial wire debug data input/output pin

Serial wire clock pin

Input

Output

Serial wire trace output pin

External bus

interface

RD

Strobe signal indicating that reading from the external bus interface space is

in progress, active-low

WR0

Output

Strobe signal indicating that writing to the external bus interface space is in

progress, active-low

ALE

Output

Input

Address latch signal when address/data multiplexed bus is selected

Input pin for wait request signals in access to the external space, active-low

Select signals for CS areas, active-low

WAIT

CS0, CS1,

Output

CS4 to CS7

A00 to A12

D00 to D07

Output

I/O

Address bus

Data bus

A00/D00 to A07/D07 I/O

Address/data multiplexed bus

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 12 of 92

RA6M1 Group

1. Overview

Table 1.15

Pin functions (2 of 4)

Signal

Function

I/O

Description

GPT

GTETRGA,

GTETRGB,

GTETRGC,

GTETRGD

Input

External trigger input pins

GTIOC0A to

GTIOC12A,

GTIOC0B to

GTIOC12B

I/O

Input capture, output compare, or PWM output pins

GTIU

Input

Hall sensor input pin U

GTIV

Input

Hall sensor input pin V

GTIW

Input

Hall sensor input pin W

GTOUUP

Output

Input

3-phase PWM output for BLDC motor control (positive U phase)

3-phase PWM output for BLDC motor control (negative U phase)

3-phase PWM output for BLDC motor control (positive V phase)

3-phase PWM output for BLDC motor control (negative V phase)

3-phase PWM output for BLDC motor control (positive W phase)

3-phase PWM output for BLDC motor control (negative W phase)

External event input enable signals

GTOULO

GTOVUP

GTOVLO

GTOWUP

GTOWLO

AGT

AGTEE0, AGTEE1

AGTIO0, AGTIO1

AGTO0, AGTO1

AGTOA0, AGTOA1

AGTOB0, AGTOB1

RTCOUT

I/O

External event input and pulse output pins

Pulse output pins

Output

Input

Output compare match A output pins

Output compare match B output pins

RTC

SCI

Output pin for 1-Hz or 64-Hz clock

RTCIC0 to RTCIC2

Time capture event input pins

SCK0 to SCK4,

SCK8, SCK9

I/O

Input/output pins for the clock (clock synchronous mode)

RXD0 to RXD4,

RXD8, RXD9

Input

Output

I/O

Input pins for received data (asynchronous mode/clock synchronous mode)

TXD0 to TXD4,

TXD8, TXD9

Output pins for transmitted data (asynchronous mode/clock synchronous

mode)

CTS0_RTS0 to

CTS4_RTS4,

CTS8_RTS8,

CTS9_RTS9

Input/output pins for controlling the start of transmission and reception

(asynchronous mode/clock synchronous mode), active-low

SCL0 to SCL4,

SCL8, SCL9

I/O

Input/output pins for the IIC clock (simple IIC mode)

Input/output pins for the IIC data (simple IIC mode)

SDA0 to SDA4,

SDA8, SDA9

I/O

SCK0 to SCK4,

SCK8, SCK9

I/O

Input/output pins for the clock (simple SPI mode)

MISO0 to MISO4,

MISO8, MISO9

I/O

Input/output pins for slave transmission of data (simple SPI mode)

Input/output pins for master transmission of data (simple SPI mode)

Chip-select input pins (simple SPI mode), active-low

MOSI0 to MOSI4,

MOSI8, MOSI9

I/O

SS0 to SS4, SS8,

SS9

Input

IIC

SCL0, SCL1

SDA0, SDA1

SSIBCK0

I/O

Input/output pins for the clock

Input/output pins for data

I/O

SSIE

I/O

SSIE serial bit clock pins

SSILRCK0/SSIFS0

SSITXD0

I/O

LR clock/frame synchronization pins

Serial data output pins

Output

Input

SSIRXD0

Serial data input pins

AUDIO_CLK

External clock pin for audio (input oversampling clock)

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 13 of 92

RA6M1 Group

1. Overview

Table 1.15

Pin functions (3 of 4)

Function

Signal

I/O

Description

SPI

RSPCKA, RSPCKB

MOSIA, MOSIB

MISOA, MISOB

SSLA0, SSLB0

I/O

Clock input/output pin

I/O

Input or output pins for data output from the master

Input or output pins for data output from the slave

Input or output pin for slave selection

Output pins for slave selection

I/O

SSLA1 to SSLA3,

SSLB1 to SSLB3

Output

QSPI

QSPCLK

Output

I/O

QSPI clock output pin

QSPI slave output pin

Data0 to Data3

Receive data

QSSL

QIO0 to QIO3

CRX0, CRX1

CTX0, CTX1

VCC_USB

VSS_USB

USB_DP

CAN

Input

Output

Input

I/O

Transmit data

USBFS

Power supply pins

Ground pins

D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of

the USB bus

USB_DM

I/O

D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of

the USB bus

USB_VBUS

Input

USB cable connection monitor pin. Connect this pin to VBUS of the USB

bus. The VBUS pin status (connected or disconnected) can be detected

when the USB module is operating as a device controller.

USB_EXICEN

USB_VBUSEN

Output

Input

Low-power control signal for external power supply (OTG) chip

VBUS (5 V) supply enable signal for external power supply chip

USB_OVRCURA,

USB_OVRCURB

Connect the external overcurrent detection signals to these pins. Connect

the VBUS comparator signals to these pins when the OTG power supply

chip is connected.

USB_ID

Input

Connect the MicroAB connector ID input signal to this pin during operation in

OTG mode

SDHI

SD0CLK, SD1CLK

SD0CMD, SD1CMD

Output

I/O

SD clock output pins

Command output pin and response input signal pins

SD and MMC data bus pins

SD0DAT0 to

SD0DAT3,

SD1DAT0 to

SD1DAT3

I/O

SD0CD

SD0WP

AVCC0

Input

SD card detection pins

SD write-protect signals

Analog power

supply

Analog voltage supply pin. This is used as the analog power supply for the

respective modules. Supply this pin with the same voltage as the VCC pin.

AVSS0

Input

Analog ground pin. This is used as the analog ground for the respective

modules. Supply this pin with the same voltage as the VSS pin.

VREFH0

Analog reference voltage supply pin for the ADC12 (unit 0). Connect this pin

to VCC when not using the ADC12 (unit 0) and sample-and-hold circuit for

AN000 to AN002.

VREFL0

VREFH

VREFL

Input

Analog reference ground pin for the ADC12. Connect this pin to VSS when

not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to

AN002

Analog reference voltage supply pin for the ADC12 (unit 1) and D/A

Converter. Connect this pin to VCC when not using the ADC12 (unit 1),

sample-and-hold circuit for AN100 to AN102, and D/A Converter.

Analog reference ground pin for the ADC12 and D/A Converter. Connect this

pin to VSS when not using the ADC12 (unit 1), sample-and-hold circuit for

AN100 to AN102, and D/A Converter.

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 14 of 92

RA6M1 Group

1. Overview

Table 1.15

Pin functions (4 of 4)

Signal

Function

I/O

Description

ADC12

AN000 to AN003,

AN005 to AN007,

AN016 to AN018,

AN020

Input

Input pins for the analog signals to be processed by the ADC12

AN100 to AN102,

AN105 to AN107,

AN116, AN117

Input

ADTRG0

ADTRG1

Input

Input pins for the external trigger signals that start the A/D conversion

Differential input pins

PGAVSS000,

PGAVSS100

DAC12

DA0, DA1

Output

Input

-

Output pins for the analog signals processed by the D/A converter

Comparator output pin

ACMPHS

VCOUT

IVREF0 to IVREF3

IVCMP0 to IVCMP3

TS01 to TS12

TSCAP

Reference voltage input pins for comparator

Analog voltage input pins for comparator

Capacitive touch detection pins (touch pins)

Secondary power supply pin for the touch driver

General-purpose input pins

CTSU

I/O ports

P000 to P007

P008, P014, P015

P100 to P115

P200

Input

I/O

General-purpose input/output pins

General-purpose input pin

I/O

Input

I/O

P201, P205 to P214

P300 to P307

P400 to P415

P500 to P504, P508

General-purpose input/output pins

I/O

P600 to P602,

P608 to P610

I/O

P708

I/O

General-purpose input/output pin

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 15 of 92

RA6M1 Group

1. Overview

1.6

Pin Assignments

Figure 1.3 to Figure 1.6 show the pin assignments.

R7FA6M1AD2CLJ

A

B

C

D

E

F

G

H

J

K

P212/

EXTAL

10 P407

P409

P412

VCC

XCOUT

VCL0

P403

P400

P000 10

P213/

XTAL

9

8

7

6

5

4

3

2

1

USB_DM USB_DP P411

VSS

P413

P408

P211

RES

P306

XCIN

P708

P406

P402

P600

P601

P602

VSS

VBATT

P404

P006

P508

P504

P503

P107

P106

P405

P003

P007

P401

P004

P008

P001

P002

P005

9

8

7

6

5

4

3

2

1

VCC_

USB

VSS_

USB

P207

P206

P210

P415

P414

P410

P113

P115

P609

P610

P205

P209

P214

P208

AVSS0 VREFL0 VREFH0

AVCC0 VREFL VREFH

P200 P201/MD P307

VCC

VSS

P304

P305

P100

P103

P101

P015

VSS

P014

VCC

P502

P303 P110/TDI P111

P300/

TCK/

P302

P301

P114

P501

SWCLK

P108/

TMS/

SWDIO

P109/

TDO

P112

C

P608

D

VCC

E

VCL

F

P105

G

P104

H

P102

J

P500

K

A

B

Figure 1.3

Pin assignment for 100-pin LGA (top view)

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 16 of 92

RA6M1 Group

1. Overview

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P500

P501

P300/TCK/SWCLK

P301

P502

P302

P503

P303

P504

VCC

P508

VSS

VCC

P304

VSS

P305

P015

P306

P014

P307

VREFL

VREFH

AVCC0

AVSS0

VREFL0

VREFH0

P008

P200

P201/MD

RES

R7FA6M1AD3CFP

P208

P209

P210

P211

P007

P214

P006

P205

P005

P206

P004

P207

P003

VCC_USB

USB_DP

USB_DM

VSS_USB

P002

P001

P000

Figure 1.4

Pin assignment for 100-pin LQFP (top view)

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 17 of 92

RA6M1 Group

1. Overview

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P500

P501

P300/TCK/SWCLK

P301

VCC

P302

VSS

VCC

P015

VSS

P014

P200

VREFL

VREFH

AVCC0

AVSS0

P201/MD

RES

R7FA6M1AD3CFM

P210

P205

VREFL0

VREFH0

P003

P206

P207

VCC_USB

USB_DP

USB_DM

VSS_USB

P002

P001

P000

Figure 1.5

Pin assignment for 64-pin LQFP (top view)

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 18 of 92

RA6M1 Group

1. Overview

P500

P501

VCC

VSS

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32 P300/TCK/SWCLK

31

P301

30

P302

29

VCC

28

P015

P014

VREFL

VREFH

AVCC0

AVSS0

VSS

27

P200

26

P201/MD

25

RES

R7FA6M1AD3CNB

24

P210

23

P205

22

VREFL0

VREFH0

P003

P206

21

P207

20

VCC_USB

19

P002

P001

USB_DP

18 USB_DM

17

P000

VSS_USB

Figure 1.6

Pin assignment for 64-pin QFN (top view)

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 19 of 92

RA6M1 Group

1. Overview

1.7

Pin Lists

Pin number

Timers

Communication interfaces

Analog

HMI

J10

J9

1

2

3

4

5

1

2

3

-

1

2

3

-

IRQ0

P400

-

AGTIO1

-

GTIOC6

A

-

SCK4

-

SCL0_

A

-

AUDIO_

CLK

-

ADTRG1

-

IRQ5- P401

DS

GTETRGA

GTIOC6

B

CTX0 CTS4_RT

S4/SS4

SDA0_

A

-

F6

CACREF IRQ4- P402

DS

AGTIO0/A

GTIO1

-

RTCI CRX0

C0

-

AUDIO_

CLK

H10

G8

-

P403

AGTIO0/A

GTIO1

GTIOC3 RTCI

C1

GTIOC3 RTCI

-

SSIBCK

0_A

A

-

P404

-

SSILRC

K0/SSIF

S0_A

B

C2

H9

F7

6

7

-

P405

P406

-

GTIOC1

A

-

SSITXD

0_A

-

GTIOC1

B

SSIRXD

0_A

G9

G10

F9

8

4

5

6

7

8

9

4

5

6

7

8

9

VBATT

VCL0

XCIN

-

9

-

10

11

12

13

-

F10

D9

XCOUT

VSS

-

E9

XTAL

IRQ2

P213

GTETRGC

GTIOC0

A

TXD1/MO

SI1/SDA1

ADTRG1

E10

14

10

EXTAL

IRQ3

P212

-

AGTEE1 GTETRGD

GTIOC0

B

-

RXD1/MIS

O1/SCL1

-

D10

F8

15

16

11

-

11

-

VCC

-

CACREF IRQ11 P708

RXD1/MIS

O1/SCL1

SSLA3_ AUDIO_

B

TS12

CLK

E8

17

18

19

20

21

22

23

24

25

-

IRQ8

IRQ9

-

P415

P414

P413

P412

P411

P410

P409

P408

P407

-

GTIOC0

A

-

USB_V

BUSEN

-

SSLA2_

B

-

SD0CD

SD0WP

-

TS11

TS10

TS09

TS08

TS07

TS06

TS05

TS04

TS03

E7

-

GTIOC0

B

-

SSLA1_

B

-

D8

-

GTOUUP

-

CTS0_RT

S0/SS0

SSLA0_

B

SD0CLK

_A

-

C10

C9

-

AGTEE1 GTOULO

AGTOA1 GTOVUP

AGTOB1 GTOVLO

-

SCK0

RSPCK

A_B

SD0CMD

_A

-

12

13

14

15

16

12

13

14

15

16

IRQ4

IRQ5

IRQ6

IRQ7

-

GTIOC9

A

TXD0/MO CTS3_RT

SI0/SDA0 S3/SS3

MOSIA_

B

SD0DAT

0_A

-

E6

GTIOC9

B

RXD0/MIS SCK3

O0/SCL0

MISOA_

B

SD0DAT

1_A

-

B10

D7

-

GTOWUP

GTOWLO

-

GTIOC10 -

A

USB_E

XICEN

-

TXD3/MO

SI3/SDA3

-

GTIOC10 -

B

USB_ID -

RXD3/MIS SCL0_

O3/SCL3

-

B

A10

AGTIO0

-

RTCO USB_V CTS4_RT

UT

-

SDA0_

B

ADTRG0

BUS

S4/SS4

B8

A9

26

27

17

18

17

18

VSS_USB

-

USB_D

M

B9

28

19

-

USB_D

P

-

A8

C8

C7

29

30

31

20

21

22

20

21

22

VCC_USB

-

P207

-

QSSL

-

TS02

TS01

IRQ0- P206 WAIT

DS

GTIU

USB_V RXD4/MIS

BUSEN O4/SCL4

SDA1_

A

SD0DAT

2_A

A7

32

23

CLKOUT IRQ1- P205

DS

-

AGTO1

GTIV

GTIOC4

A

-

USB_O TXD4/MO CTS9_RT SCL1_

-

SD0DAT

3_A

-

TSCAP

VRCUR SI4/SDA4 S9/SS9

A-DS

A

-

B7

D6

33

34

-

TRCLK

-

P214

-

GTIU

GTIV

-

QSPCL

K

-

SD0CLK

_B

-

TRDATA0

P211 CS7

-

QIO0

SD0CMD

_B

C6

A6

B6

35

36

37

24

-

24

-

TRDATA1

TRDATA2

TRDATA3

-

P210 CS6

P209 CS5

P208 CS4

-

GTIW

-

QIO1

QIO2

QIO3

-

SD0CD

SD0WP

-

GTOVUP

GTOVLO

-

SD0DAT

0_B

D5

B5

A5

C5

D4

C4

38

39

40

41

42

43

25

26

27

-

25

26

27

-

RES

-

MD

-

P201

P200

-

NMI

-

P307 A12

P306 A11

P305 A10

GTOUUP

GTOULO

GTOWUP

QIO0

QSSL

-

IRQ8

QSPCL

K

B4

44

-

IRQ9

P304 A09

-

GTOWLO

GTIOC7

A

-

A3

A4

B3

45

46

47

28

29

-

28

29

-

VSS

VCC

-

P303 A08

P302 A07

P301 A06

GTIOC7

B

B2

C2

A2

A1

48

49

50

51

30

31

32

33

30

31

32

33

-

IRQ5

-

GTOUUP

GTOULO

GTOUUP

GTOULO

GTIOC4

A

-

TXD2/MO

SI2/SDA2

-

SSLB3_

B

-

IRQ6

AGTIO0

GTIOC4

B

RXD2/MIS CTS9_RT

O2/SCL2 S9/SS9

SSLB2_

B

TCK/SWC

LK

-

P300

P108

-

GTIOC0

A_A

-

SSLB1_

B

TMS/SWD

IO

GTIOC0

B_A

-

CTS9_RT

S9/SS9

SSLB0_

B

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 20 of 92

RA6M1 Group

1. Overview

Pin number

Timers

Communication interfaces

Analog

HMI

B1

C3

D3

C1

E5

52

53

54

55

56

34

35

36

37

-

34

35

36

37

-

CLKOUT/T -

DO/SWO

P109

P110

P111

-

GTOVUP

GTIOC1

A_A

-

CTX1

-

TXD9/MO

SI9/SDA9

-

MOSIB_

B

-

TDI

IRQ3

-

GTOVLO

GTIOC1

B_A

CRX1 CTS2_RT RXD9/MIS

MISOB_

B

VCOUT

-

S2/SS2

O9/SCL9

-

IRQ4

A05

-

GTIOC3

A_A

-

SCK2

SCK9

RSPCK

B_B

-

P112 A04

P113 A03

GTIOC3

B_A

TXD2/MO SCK1

SI2/SDA2

SSLB0_ SSIBCK

B

0_B

GTIOC2

A

RXD2/MIS

O2/SCL2

-

SSILRC

K0/SSIF

S0_B

D2

E4

D1

E3

E2

57

58

59

60

61

-

P114 A02

P115 A01

P608 A00

P609 CS1

P610 CS0

-

GTIOC2

B

-

SSIRXD

0_B

-

GTIOC4

A

-

SSITXD

0_B

GTIOC4

B

-

GTIOC5

A

CTX1

CRX1

GTIOC5

B

E1

F2

F1

F3

62

63

64

65

38

39

40

-

38

39

40

-

VCC

VSS

VCL

-

P602 EBCL

K

GTIOC7

B

TXD9

F4

F5

G3

66

67

68

-

P601 WR0

-

GTIOC6

A

-

RXD9

SCK9

-

CLKOUT/

CACREF

-

P600 RD

GTIOC6

B

-

41

-

KR07

P107 D07[A AGTOA0

GTIOC8

A

CTS8_RT

S8/SS8

QIO3

07/D0

7]

G2

G1

H1

H3

J1

69

70

71

72

73

74

75

42

43

44

45

46

47

48

42

43

44

45

46

47

48

KR06

P106 D06[A AGTOB0

-

GTIOC8

B

-

SCK8

-

SSLA3_

A/QIO2

-

06/D0

6]

IRQ0/K P105 D05[A

R05

-

GTETRGA

GTETRGB

GTOWUP

GTOWLO

GTIOC1

A

TXD8/MO

SI8/SDA8

SSLA2_

A/QIO1

05/D0

5]

IRQ1/K P104 D04[A

R04

GTIOC1

B

RXD8/MIS

O8/SCL8

SSLA1_

A/QIO0

04/D0

4]

KR03

P103 D03[A

GTIOC2

A_A

CTX0 CTS0_RT

S0/SS0

SSLA0_

A

03/D0

3]

KR02

P102 D02[A AGTO0

GTIOC2

B_A

CRX0 SCK0

RSPCK

A_A

ADTRG0

02/D0

2]

H2

H4

IRQ1/K P101 D01[A AGTEE0 GTETRGB

R01

GTIOC5

A

-

TXD0/MO CTS1_RT SDA1_ MOSIA_

SI0/SDA0 S1/SS1

-

01/D0

1]

B

A

IRQ2/K P100 D00[A AGTIO0

R00

GTETRGA

GTIOC5

B

RXD0/MIS SCK1

O0/SCL0

SCL1_ MISOA_

B

00/D0

0]

A

K1

J2

76

77

49

50

49

50

-

P500

-

AGTOA0 GTIU

AGTOB0 GTIV

GTIOC11

A

-

USB_V

BUSEN

-

QSPCL

K

-

SD1CLK AN016

_A

IVREF0

IVREF1

-

IRQ11 P501

IRQ12 P502

-

GTIOC11

B

USB_O

VRCUR

A

-

QSSL

SD1CMD AN116

_A

K2

78

-

GTIW

GTIOC12 -

A

USB_O

VRCUR

B

-

QIO0

-

SD1DAT AN017

0_A

IVCMP0

-

G4

G5

G6

79

80

81

-

P503

-

GTETRGC

GTETRGD

-

GTIOC12 -

B

USB_E

XICEN

-

QIO1

QIO2

-

SD1DAT AN117

1_A

-

P504 ALE

-

USB_ID -

SD1DAT AN018

2_A

P508

-

SD1DAT AN020

3_A

K3

J3

J4

82

83

84

51

52

53

51

52

53

VCC

VSS

-

IRQ13 P015

AN006/A DA1/

N106

IVCMP1

K4

85

54

-

P014

-

AN005/A DA0/

-

N105

IVREF3

J5

86

87

88

89

90

91

92

55

56

57

58

59

60

-

55

56

57

58

59

60

-

VREFL

VREFH

AVCC0

AVSS0

VREFL0

VREFH0

-

K5

H5

H6

J6

-

K6

J7

-

IRQ12- P008

DS

AN003

H7

G7

K7

J8

93

94

95

96

97

98

-

P007

-

PGAVSS1 -

00/AN107

-

IRQ11- P006

DS

AN102

AN101

AN100

IVCMP2

-

IRQ10- P005

DS

IVCMP2

-

IRQ9- P004

DS

H8

K8

61

62

61

62

-

P003

PGAVSS0 -

00/AN007

IRQ8- P002

DS

AN002

IVCMP2

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 21 of 92

RA6M1 Group

1. Overview

Pin number

Timers

Communication interfaces

Analog

HMI

K9

99

63

64

63

64

-

IRQ7- P001

DS

-

AN001

AN000

IVCMP2

-

K10

100

IRQ6- P000

DS

Note:

Some pin names have the added suffix of _A and _B. When assigning the GPT, IIC, SPI, SSIE, and SDHI functionality, select

the functional pins with the same suffix.

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Oct 8, 2019

Page 22 of 92

RA6M1 Group

2. Electrical Characteristics

2.

Electrical Characteristics

Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:



VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V

2.7 ≤ VREFH0/VREFH ≤ AVCC0

VSS = AVSS0 = VREFL0/VREFL = VSS_USB = 0 V

T = T

.

opr

a

Figure 2.1 shows the timing conditions.

For example P100

C

V_OH= VCC × 0.7, V_OL= VCC × 0.3

V

_IH= VCC × 0.7, V_IL= VCC × 0.3

Load capacitance C = 30 pF

Figure 2.1

Input or output timing measurement conditions

The measurement conditions for the timing specification of each peripheral are recommended for the best peripheral

operation. However, make sure to adjust the driving abilities of each pin to meet the conditions of your system.

Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function

pin is mixed, the A/C specification of each function is not guaranteed.

2.1

Absolute Maximum Ratings

Table 2.1

Absolute maximum ratings

Parameter

Symbol

Value

Unit

V

Power supply voltage

VCC, VCC_USB *²

-0.3 to +4.0

VBATT power supply voltage

Input voltage (except for 5 V-tolerant ports*¹)

Input voltage (5 V-tolerant ports*¹)

Reference power supply voltage

Analog power supply voltage

Analog input voltage (except for P000 to P007)

VBATT

-0.3 to +4.0

V

V_in

-0.3 to VCC + 0.3

-0.3 to + VCC + 4.0 (max. 5.8)

-0.3 to AVCC0 + 0.3

-0.3 to +4.0

V

V_in

V

VREFH/VREFH0

AVCC0 *²

V_AN

V

-0.3 to AVCC0 + 0.3

V

Analog input voltage (P000 to P007) when PGA

differential input is disabled

V_AN

V

Analog input voltage (P000 to P002, P004 to P006)

when PGA differential input is enabled

V_AN

-1.3 to AVCC0 + 0.3

-0.8 to AVCC0 + 0.3

V

Analog input voltage (P003, P007) when PGA differential V_AN

input is enabled

V

4,

5

Operating temperature*^3,

*

T_opr

-40 to +85

-40 to +105

°C

Storage temperature

T_stg

-55 to +125

Caution:

Permanent damage to the MCU might result if absolute maximum ratings are exceeded.

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 23 of 92

RA6M1 Group

2. Electrical Characteristics

Note 1. Ports P205, P206, P400, P401, P407 to P415, and P708 are 5 V tolerant.

Note 2. Connect AVCC0 and VCC_USB to VCC.

Note 3. See section 2.2.1, T_j/T_aDefinition.

Note 4. Contact Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the

systematic reduction of load for improved reliability.

Note 5. The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part

Numbering.

Table 2.2

Recommended operating conditions

Parameter

Symbol

Value

Min

Typ

Max

Unit

V

Power supply voltages

VCC

When USB is not used

When USB is used

2.7

-

3.6

3.0

-

3.6

V

VSS

-

0

-

V

USB power supply voltages

VCC_USB

VSS_USB

VBATT

-

VCC

-

V

-

0

-

V

VBATT power supply voltage

Analog power supply voltages

1.8

-

3.6

V

AVCC0*¹

AVSS0

-

VCC

0

-

V

Note 1. Connect AVCC0 to VCC. When the A/D converter, the D/A converter, or the comparator are not in use, do not leave the

AVCC0, VREFH/VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC,

and the AVSS0 and VREFL/VREFL0 pins to VSS, respectively.

2.2

DC Characteristics

T /T Definition

2.2.1

j

a

Table 2.3

DC characteristics

Conditions: Products with operating temperature (T_a) -40 to +105°C.

Parameter

Symbol Typ

T_j

Max

Unit

Test conditions

Permissible junction temperature

100-pin LQFP

64-pin LQFP

-

125

°C

High-speed mode

Low-speed mode

Subosc-speed mode.

64-pin QFN

100-pin LGA

117

105

Note:

Make sure that T_j= T_a+ θja × total power consumption (W),

where total power consumption = (VCC - V_OH) × ΣI_OH+ V_OL× ΣI_OL+ I_CCmax × VCC.

The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part

Numbering.

2.2.2

I/O V , V

IH IL

Table 2.4

Parameter

I/O V_IH, V_IL(1 of 2)

Symbo

l

Min

Typ Max

Unit

Input voltage

(except for

Schmitt trigger pin

input pins)

Peripheral EXTAL(external clock input), WAIT, SPI

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

VCC × 0.8

-

V

function

(except RSPCK)

-

VCC × 0.2

D00 to D07

VCC × 0.7

-

VCC × 0.3

IIC (SMBus)*¹

IIC (SMBus)*²

2.1

-

0.8

2.1

VCC + 3.6

(max 5.8)

V_IL

-

0.8

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Oct 8, 2019

Page 24 of 92

RA6M1 Group

2. Electrical Characteristics

Table 2.4

Parameter

I/O V_IH, V_IL(2 of 2)

Symbo

l

Min

Typ Max

Unit

Schmitt trigger Peripheral IIC (except for SMBus)*¹

V_IH

V_IL

VCC × 0.7

-

V

input voltage

function

VCC × 0.3

-

ΔV_T

V_IH

VCC × 0.05

VCC × 0.7

IIC (except for SMBus)*²

VCC + 3.6

(max 5.8)

V

V_IL

-

VCC × 0.3

-

ΔV_T

V_IH

VCC × 0.05

VCC × 0.8

7

5 V-tolerant ports*^3,

*

VCC + 3.6

(max 5.8)

V_IL

-

VCC × 0.2

ΔV_T

V_IH

VCC × 0.05

-

RTCIC0, When using the When VBATT

VBATT ×

0.8

VBATT + 0.3

RTCIC1, battery backup

RTCIC2 function

power supply is

selected

V_IL

-

VBATT × 0.2

-

ΔV_T

VBATT ×

0.05

When VCC

power supply is

selected

V_IH

VCC × 0.8

-

Higher

voltage

either

VCC + 0.3 V

or

VBATT + 0.3

V

V_IL

-

VCC × 0.2

ΔV_T

VCC × 0.05

VCC × 0.8

-

When not using the battery backup V_IH

VCC + 0.3

function

V_IL

VCC × 0.2

ΔV_T

VCC × 0.05

VCC × 0.8

-

Other input pins*⁴

V_IH

V_IL

-

VCC × 0.2

-

ΔV_T

V_IH

VCC × 0.05

VCC × 0.8

7

Ports

5 V-tolerant ports*^5,

Other input pins*⁶

*

VCC + 3.6

(max 5.8)

V

V_IL

V_IH

V_IL

-

VCC × 0.2

-

VCC × 0.8

-

VCC × 0.2

Note 1. SCL1_B, SDA1_B (total 2 pins).

Note 2. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A (total 6 pins).

Note 3. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P708 (total 15 pins).

Note 4. All input pins except for the peripheral function pins already described in the table.

Note 5. P205, P206, P400, P401, P407 to P415, P708 (total 14 pins).

Note 6. All input pins except for the ports already described in the table.

Note 7. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur

because 5 V-tolerant ports are electrically controlled so as not to violate the breakdown voltage.

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 25 of 92

RA6M1 Group

2. Electrical Characteristics

2.2.3

I/O I , I

OH OL

Table 2.5

Parameter

I/O I_OH, I_OL

Symbol

Min

Typ

Max

-2.0

2.0

-4.0

4.0

-2.0

2.0

-4.0

4.0

-20

20

Unit

mA

Permissible output current

(average value per pin)

Ports P008, P201

Ports P014, P015

-

I

-

OH

I

OL

-

I

OH

I

OL

1

Ports P205, P206, P407 to P415,

P602, P708 (total 13 pins)

Low drive*

I

OH

I

OL

2

Middle drive*

I

OH

I

OL

3

High drive*

I

OH

I

OL

4

1

Other output pins*

Low drive*

I

-2.0

2.0

-4.0

4.0

-16

16

OH

I

OL

2

Middle drive*

I

OH

I

OL

3

High drive*

I

OH

I

OL

Permissible output current

(max value per pin)

Ports P008, P201

Ports P014, P015

-

I

-4.0

4.0

-8.0

8.0

-4.0

4.0

-8.0

8.0

-40

40

OH

I

OL

I

OH

I

OL

1

Ports P205, P206, P407 to P415,

P602, P708 (total 13 pins)

Low drive*

I

OH

I

OL

2

Middle drive*

I

OH

I

OL

3

High drive*

I

OH

I

OL

4

1

Other output pins*

Low drive*

I

-4.0

4.0

-8.0

8.0

-32

32

OH

I

OL

2

Middle drive*

I

OH

I

OL

3

High drive*

I

OH

I

OL

Permissible output current

(max value of total of all pins)

Maximum of all output pins

ΣI

-80

80

OH (max)

ΣI

OL (max)

Caution:

To protect the reliability of the MCU, the output current values should not exceed the values in this table. The

average output current indicates the average value of current measured during 100 μs.

Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving

ability is retained in Deep Software Standby mode.

Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected

driving ability is retained in Deep Software Standby mode.

Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected

driving ability is retained in Deep Software Standby mode.

Note 4. Except for P000 to P007, P200, which are input ports.

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Page 26 of 92

RA6M1 Group

2. Electrical Characteristics

2.2.4

I/O V , V , and Other Characteristics

OH OL

Table 2.6

I/O V_OH, V_OL, and other characteristics

Parameter

Symbol

Min

Typ

Max

0.4

Unit

Test conditions

Output voltage

IIC

V

-

V

I

= 3.0 mA

= 6.0 mA

= 15.0 mA

OL

V

0.6

IIC*¹

0.4

(ICFER.FMPE = 1)

V

-

0.4

-

I = 20.0 mA

OL

OH

OL

OH

OL

(ICFER.FMPE = 1)

Ports P205, P206, P407 to P415,

P602, P708 (total of 13 pins)*

VCC - 1.0

-

I

= -20 mA

OH

VCC = 3.3 V

2

1.0

I

= 20 mA

OL

VCC = 3.3 V

Other output pins

RES

V

|I

VCC - 0.5

-

I

= -1.0 mA

= 1.0 mA

OH

OL

-

0.5

5.0

I

OL

|

Input leakage current

μA

V

= 0 V

= 5.5 V

in

Ports P000 to P002, P004 to P006,

P200

-

1.0

45.0

1.0

5.0

1.0

-10

16

V

= 0 V

= VCC

in

Ports P003, P007 Before

-

V

= 0 V

= VCC

in

3

initialization*

After

initialization*

-

V

= 0 V

= VCC

in

4

Three-state leakage

current (off state)

5 V-tolerant ports

|I

I

|

-

μA

V

= 0 V

= 5.5 V

TSI

in

Other ports (except for ports P000

to P007, P200)

-

V

= 0 V

= VCC

in

Input pull-up MOS current

Input capacitance

Ports P0 to P7 (except for ports

P000 to P007)

-300

-

μA

pF

VCC = 2.7 to 3.6 V

= 0 V

p

V

in

USB_DP, USB_DM, and ports

P003, P007, P014, P015, P400,

P401

C

Vbias = 0 V

Vamp = 20 mV

f = 1 MHz

in

T

= 25°C

a

Other input pins

-

8

Note 1. SCL0_A, SDA0_A (total 2 pins).

Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register.

The selected driving ability is retained in Deep Software Standby mode.

Note 3. P0nPFS.ASEL(n = 3 or 7) = 1

Note 4. P0nPFS.ASEL(n = 3 or 7) = 0

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Oct 8, 2019

Page 27 of 92

RA6M1 Group

2. Electrical Characteristics

2.2.5

Operating and Standby Current

Table 2.7

Operating and standby current (1 of 2)

Parameter

Symbol

Min

Typ

-

Max

Unit

Test conditions

2

3

Supply

Maximum*

I

*

-

87

-

mA

ICLK = 120 MHz

PCLKA = 120 MHz

PCLKB = 60 MHz

PCLKC = 60 MHz

PCLKD = 120 MHz

FCLK = 60 MHz

BCLK = 120 MHz

CC

current*¹

® 5

CoreMark *

17

24

Normal mode

All peripheral clocks enabled,

while (1) code executing from

flash*

-

4

All peripheral clocks disabled,

while (1) code executing from

-

12

-

5,

6

flash*

*

5,

6

Sleep mode*

*

-

9

33.5

-

Increase during BGO

operation

Data flash P/E

Code flash P/E

6

8

-

Low-speed mode*⁵

1.2

1.0

1.3

28

-

ICLK = 1 MHz

ICLK = 32.768 kHz

Ta ≤ 85°C

Ta ≤ 105°C

Ta ≤ 85°C

Ta ≤ 105°C

Ta ≤ 85°C

Ta ≤ 105°C

Ta ≤ 85°C

Ta ≤ 105°C

-

Subosc-speed mode*⁵

Software Standby mode

-

13

21

65

93

28

32

21

26

-

Power supplied to Standby SRAM and USB resume

detecting unit

μA

28

Power not supplied to

SRAM or USB resume

detecting unit

Power-on reset circuit low

power function disabled

11.6

4.9

4.4

Power-on reset circuit low

power function enabled

Increase when the RTC

and AGT are operating

When the low-speed on-chip

oscillator (LOCO) is in use

When a crystal oscillator for

low clock loads is in use

-

1.0

1.4

0.9

1.1

1.0

1.6

-

When a crystal oscillator for

standard clock loads is in use

RTC operating while VCC is off (with When a crystal

the battery backup function, only the oscillator for low clock

VBATT = 1.8 V,

VCC = 0 V

RTC and sub-clock oscillator

operate)

loads is in use

VBATT = 3.3 V,

VCC = 0 V

When a crystal

oscillator for standard

clock loads is in use

VBATT = 1.8 V,

VCC = 0 V

VBATT = 3.3 V,

VCC = 0 V

Analog

power

supply

current

During 12-bit A/D conversion

AI

-

0.8

2.3

1

1.1

3.3

3

mA

µA

-

CC

During 12-bit A/D conversion with S/H amp

PGA (1ch)

ACMPHS (1 unit)

100

0.1

0.6

0.9

2

150

0.2

1.1

1.6

8

Temperature sensor

mA

µA

During D/A conversion (per unit)

Without AMP output

With AMP output

Waiting for A/D, D/A conversion (all units)

ADC12, DAC12 in standby modes (all units)*

During 12-bit A/D conversion (unit 0)

Waiting for 12-bit A/D conversion (unit 0)

ADC12 in standby modes (unit 0)

7

Reference

power

supply

current

(VREFH0)

70

120

0.5

μA

AI_REFH0

0.07

μA

µA

Reference

power

supply

current

(VREFH)

During 12-bit A/D conversion (unit 1)

-

70

120

0.4

0.8

µA

mA

µA

-

AI_REFH

During D/A conversion

(per unit)

Without AMP output

With AMP ouput

0.1

Waiting for 12-bit A/D (unit 1), D/A (all units) conversion

ADC12 unit 1 in standby modes

0.07

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Oct 8, 2019

Page 28 of 92

RA6M1 Group

2. Electrical Characteristics

Table 2.7

Operating and standby current (2 of 2)

Parameter

Symbol

Min

Typ

3.5

4.0

Max

6.5

Unit

mA

Test conditions

VCC_USB

USB

operating

current

Low speed

Full speed

USB

I

-

CCUSBLS

USB

I

10.0

VCC_USB

CCUSBFS

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOS transistors in the off state.

Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.

Note 3. I_CCdepends on f (ICLK) as follows. (ICLK:PCLKA:PCLKB:PCLKC:PCLKD:BCK:EBCLK = 2:2:1:1:2:1:1)

I_CCMax. = 0.53 x f + 23 (maximum operation in High-speed mode)

I_CCTyp. = 0.08 x f + 2.4 (normal operation in High-speed mode)

I_CCTyp. = 0.1 x f + 1.1 (Low-speed mode)

I_CCMax. = 0.09 x f + 23 (Sleep mode).

Note 4. This does not include the BGO operation.

Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 6. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.75 MHz).

Note 7. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-bit A/D Converter 0 Module Stop bit) and

MSTPCRD.MSTPD15 (12-bit A/D Converter 1 Module Stop bit) are in the module-stop state.

See section 42.6.8, Available functions and register settings of AN000 to AN002, AN007, AN100 to AN102, and AN107 in

User’s Manual.

Figure 2.2

Temperature dependency in Software Standby mode (reference data)

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2. Electrical Characteristics

Figure 2.3

Temperature dependency in Deep Software Standby mode, power supplied to standby SRAM and

USB resume detecting unit (reference data)

Figure 2.4

Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB

resume detecting unit, power-on reset circuit low power function disabled (reference data)

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2. Electrical Characteristics

Figure 2.5

Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB

resume detecting unit, power-on reset circuit low power function enabled (reference data)

2.2.6

VCC Rise and Fall Gradient and Ripple Frequency

Table 2.8

Parameter

Rise and fall gradient characteristics

Symbol Min

Typ

Max

20

-

Unit

Test conditions

VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.0084

-

ms/V

-

Voltage monitor 0 reset enabled at startup

SCI/USB boot mode*¹

0.0084

20

-

VCC falling gradient*²

SfVCC

ms/V

Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.

Note 2. This applies when VBATT is used.

Table 2.9

Rise and fall gradient and ripple frequency characteristics

The ripple voltage must meet the allowable ripple frequency f_r(VCC)within the range between the VCC upper limit (3.6 V) and lower limit

(2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Allowable ripple frequency

f_{r (VCC)}

-

10

kHz

Figure 2.6

V_{r (VCC)}≤ VCC × 0.2

-

1

MHz

ms/V

Figure 2.6

V_{r (VCC)}≤ VCC × 0.08

-

10

-

Figure 2.6

V_{r (VCC)}≤ VCC × 0.06

Allowable voltage change rising

and falling gradient

dt/dVCC

1.0

When VCC change exceeds VCC ±10%

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2. Electrical Characteristics

1/f_r(VCC)

VCC

V_r(VCC)

Figure 2.6

Ripple waveform

2.3

AC Characteristics

Frequency

2.3.1

Table 2.10

Parameter

Operation frequency value in high-speed mode

Symbol

Min

Typ

Max

120

60

Unit

Operation frequency

System clock (ICLK*²)

f

-

MHz

Peripheral module clock (PCLKA)*²

Peripheral module clock (PCLKB)*²

Peripheral module clock (PCLKC)*²

Peripheral module clock (PCLKD)*²

Flash interface clock (FCLK)*²

External bus clock (BCLK)*²

EBCLK pin output

3

-*

60

-

120

60

1

-*

-

120

60

Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

Table 2.11

Parameter

Operation frequency value in low-speed mode

Symbol

Min

Typ

Max

1

Unit

Operation frequency

System clock (ICLK)*²

f

-

MHz

Peripheral module clock (PCLKA)*²

Peripheral module clock (PCLKB)*²

Peripheral module clock (PCLKC)*²,*³

-

1

-

1

-*³

-

1

Peripheral module clock (PCLKD)*²

1

2

Flash interface clock (FCLK)*^1,

External bus clock (BCLK)

EBCLK pin output

*

-

1

-

1

-

1

Note 1. Programming or erasing the flash memory is disabled in Low-speed mode.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

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2. Electrical Characteristics

Table 2.12

Parameter

Operation frequency value in Subosc-speed mode

Symbol

Min

Typ

Max

36.1

Unit

Operation frequency

System clock (ICLK)*²

f

29.4

-

kHz

Peripheral module clock (PCLKA)*²

Peripheral module clock (PCLKB)*²

Peripheral module clock (PCLKC)*²,*³

-

Peripheral module clock (PCLKD)*²

-

2

Flash interface clock (FCLK)*^1,

External bus clock (BCLK)*²

EBCLK pin output

*

29.4

-

Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3. The ADC12 cannot be used.

2.3.2

Clock Timing

Table 2.13

Clock timing except for sub-clock oscillator (1 of 2)

Parameter

Symbol

t_Bcyc

t_CH

Min

Typ

Max

-

Unit

ns

Test conditions

EBCLK pin output cycle time

EBCLK pin output high pulse width

EBCLK pin output low pulse width

EBCLK pin output rise time

16.6

-

Figure 2.7

3.3

-

ns

t_CL

3.3

-

ns

t_Cr

-

5.0

-

ns

EBCLK pin output fall time

t_Cf

-

ns

EXTAL external clock input cycle time

EXTAL external clock input high pulse width

EXTAL external clock input low pulse width

EXTAL external clock rise time

EXTAL external clock fall time

Main clock oscillator frequency

t_EXcyc

t_EXH

t_EXL

41.66

ns

Figure 2.8

15.83

-

ns

15.83

-

ns

t_EXr

-

5.0

24

-*¹

ns

t_EXf

-

ns

f_MAIN

t_MAINOSCWT

8

-

MHz

ms

-

Main clock oscillation stabilization wait time

(crystal) *¹

Figure 2.9

LOCO clock oscillation frequency

f_LOCO

29.4912

-

32.768

-

36.0448

60.4

kHz

μs

-

LOCO clock oscillation stabilization wait time

ILOCO clock oscillation frequency

t_LOCOWT

f_ILOCO

Figure 2.10

13.5

15

8

16.5

kHz

MHz

μs

-

MOCO clock oscillation frequency

F_MOCO

6.8

9.2

-

MOCO clock oscillation stabilization wait time

t_MOCOWT

f_HOCO16

f_HOCO18

f_HOCO20

f_HOCO16

f_HOCO18

f_HOCO20

f_HOCO16

f_HOCO18

f_HOCO20

-

15.0

-

HOCO clock oscillator

oscillation frequency

Without FLL

15.78

17.75

19.72

15.71

17.68

19.64

15.955

17.949

19.944

16

18

20

16

18

20

16

18

20

16.22

18.25

20.28

16.29

18.32

20.36

16.045

18.051

20.056

MHz

-20 ≤ Ta ≤ 105°C

-40 ≤ Ta ≤ -20°C

With FLL

-40 ≤ Ta ≤ 105°C

Sub-clock

frequency accuracy

is ±50 ppm.

HOCO clock oscillation stabilization wait time*²

FLL stabilization wait time

t_HOCOWT

t_FLLWT

f_PLL

-

64.7

1.8

μs

-

ms

PLL clock frequency

120

240

MHz

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2. Electrical Characteristics

Table 2.13

Clock timing except for sub-clock oscillator (2 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

PLL clock oscillation stabilization wait time

t_PLLWT

-

174.9

μs

Figure 2.11

Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as

the recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the

recommended value.

After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm

that it is 1, and then start using the main clock oscillator.

Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed

operation.

Table 2.14

Parameter

Clock timing for the sub-clock oscillator

Symbol

Min

Typ

32.768

-

Max

-

Unit

kHz

s

Test conditions

Sub-clock frequency

f_SUB

-

Sub-clock oscillation stabilization wait time

t_SUBOSCWT

-*¹

Figure 2.12

Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the

recommended oscillation stabilization time.

After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after

the sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is

recommended.

t_Bcyc

t_CH

t_Cf

EBCLK pin output

t_Cr

t_CL

Figure 2.7

Figure 2.8

Figure 2.9

EBCLK output timing

t_EXcyc

t_EXH

t_EXL

EXTAL external clock input

VCC × 0.5

t_EXr

t_EXf

EXTAL external clock input timing

MOSCCR.MOSTP

Main clock oscillator output

Main clock

t_MAINOSCWT

Main clock oscillation start timing

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2. Electrical Characteristics

LOCOCR.LCSTP

On-chip oscillator output

t_LOCOWT

LOCO clock

Figure 2.10

LOCO clock oscillation start timing

PLLCR.PLLSTP

PLL circuit output

t_PLLWT

OSCSF.PLLSF

PLL clock

Figure 2.11

PLL clock oscillation start timing

Note:

Only operate the PLL after the main clock oscillation has stabilized.

SOSCCR.SOSTP

Sub-clock oscillator output

t_SUBOSCWT

Sub-clock

Figure 2.12

Sub-clock oscillation start timing

2.3.3

Reset Timing

Table 2.15

Parameter

Reset timing (1 of 2)

Test

Symbol

t_RESWP

t_RESWD

t_RESWS

Min

1

Typ

Max

Unit

ms

conditions

Figure 2.13

Figure 2.14

RES pulse width

Power-on

-

Deep Software Standby mode

0.6

0.3

ms

Software Standby mode, Subosc-speed

mode

ms

All other

t_RESW

200

-

μs

Wait time after RES cancellation

t_RESWT

29

32

Figure 2.13

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2. Electrical Characteristics

Table 2.15

Parameter

Reset timing (2 of 2)

Test

conditions

Symbol

Min

Typ

Max

Unit

Wait time after internal reset cancellation (IWDT reset, WDT

reset, software reset, SRAM parity error reset, SRAM ECC error

reset, bus master MPU error reset, bus slave MPU error reset,

stack pointer error reset)

t_RESW2

-

320

390

μs

-

VCC

RES

t_RESWP

Internal reset signal

(active-low)

t_RESWT

Figure 2.13

Power-on reset timing

t_RESWD, t_RESWS, t_RESW

RES

Internal reset signal

(active-low)

t_RESWT

Figure 2.14

Reset input timing

2.3.4

Wakeup Timing

Table 2.16

Parameter

Timing of recovery from low power modes (1 of 2)

Symbol

Test

conditions

Min

Typ

Max

Unit

Recovery time

from Software

Standby mode*¹

Crystal

System clock source is main

clock oscillator*²

t_SBYMC

-

2.4*⁹

2.8*⁹

ms

Figure 2.15

The division

ratio of all

resonator

connected

to main

clock

System clock source is PLL

with main clock oscillator*³

t_SBYPC

-

2.7*⁹

3.2*⁹

ms

oscillators is 1.

oscillator

External

clock input

to main

clock

System clock source is main

clock oscillator*⁴

t_SBYEX

t_SBYPE

-

230*⁹

570*⁹

280*⁹

700*⁹

μs

System clock source is PLL

with main clock oscillator*⁵

oscillator

System clock source is sub-clock

oscillator*⁸

t_SBYSC

-

1.2*⁹

1.3*⁹

1.4*⁹

ms

System clock source is LOCO*⁸

System clock source is HOCO*⁶

t_SBYLO

t_SBYHO

-

1.2*⁹

ms

µs

240*^9,

*

300

10

9, 10

*

System clock source is MOCO*⁷

t_SBYMO

-

220*⁹

300*⁹

µs

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2. Electrical Characteristics

Table 2.16

Parameter

Timing of recovery from low power modes (2 of 2)

Symbol

Test

conditions

Min

Typ

0.65

-

Max

1.0

35

Unit

ms

t_cyc

μs

Recovery time from Deep Software Standby mode

t_DSBY

t_DSBYWT

t_SNZ

-

Figure 2.16

Wait time after cancellation of Deep Software Standby mode

34

-

10

Recovery time

from Software

Standby mode to

Snooze mode

High-speed mode when system clock

source is HOCO (20 MHz)

35*^9,

*

70

Figure 2.17

9, 10

*

High-speed mode when system clock

source is MOCO (8 MHz)

t_SNZ

-

11*⁹

14*⁹

μs

Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be

determined with the following equation:

Total recovery time = recovery time for an oscillator as the system clock source + the longest oscillation stabilization time of any

oscillators requiring longer stabilization times than the system clock source + 2 LOCO cycles (when LOCO is operating) + 3

SOSC cycles (when Subosc is oscillating and MSTPC0 = 0 (CAC module stop)).

Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For

other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 05h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

05h))

Note 3. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other

settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 05h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

05h))

Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h).

For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 00h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

00h))

Note 5. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h). For other

settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 00h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

00h))

Note 6. The HOCO frequency is 20 MHz.

Note 7. The MOCO frequency is 8 MHz.

Note 8. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.

Note 9. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time:

STCONR.STCON[1:0] = 00b:16 µs (typical), 34 µs (maximum)

STCONR.STCON[1:0] = 11b:16 µs (typical), 104 µs (maximum).

Note 10. When the SNZCR.RXDREQEN bit is set to 0, 16 μs (typical) or 18 μs (maximum) is added as the HOCO wait time.

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2. Electrical Characteristics

Oscillator

(system clock)

t_SBYOSCWT

t_SBYSEQ

Oscillator

(not the system clock)

ICLK

IRQ

Software Standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of the system clock oscillator is slower

Oscillator

(system clock)

t_SBYSEQ

t_SBYOSCWT

Oscillator

(not the system clock)

t_SBYOSCWT

ICLK

IRQ

Software Standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of an oscillator other than the system clock is slower

Figure 2.15

Software Standby mode cancellation timing

Oscillator

IRQ

Deep Software Standby reset

(active-low)

Internal reset

(active-low)

Deep Software Standby mode

t_DSBY

t_DSBYWT

Reset exception handling start

Figure 2.16

Deep Software Standby mode cancellation timing

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2. Electrical Characteristics

Oscillator

ICLK(except DTC, SRAM)

ICLK(to DTC, SRAM)^*1PCLK

IRQ

Software Standby mode

Snooze mode

t_SNZ

Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.17

Recovery timing from Software Standby mode to Snooze mode

2.3.5

NMI and IRQ Noise Filter

Table 2.17

NMI and IRQ noise filter

Parameter

Symbol Min

Typ

Max

Unit

Test conditions

NMI pulse width

t_NMIW

200

-

ns

NMI digital filter disabled

NMI digital filter enabled

IRQ digital filter disabled

IRQ digital filter enabled

t_Pcyc× 2 ≤ 200 ns

t_Pcyc× 2 > 200 ns

1

t_Pcyc× 2*

200

t

_NMICK× 3 ≤ 200 ns

2

t_NMICK× 3.5*

t_NMICK× 3 > 200 ns

t_Pcyc× 2 ≤ 200 ns

t_Pcyc× 2 > 200 ns

t_IRQCK× 3 ≤ 200 ns

t_IRQCK× 3 > 200 ns

IRQ pulse width

t_IRQW

200

ns

1

t

_Pcyc× 2*

200

_IRQCK× 3.5*

3

t

Note:

200 ns minimum in Software Standby mode.

If the clock source is switched, add 4 clock cycles of the switched source.

Note 1. t_Pcycindicates the PCLKB cycle.

Note 2. t_NMICKindicates the cycle of the NMI digital filter sampling clock.

Note 3. t_IRQCKindicates the cycle of the IRQi digital filter sampling clock.

NMI

t_NMIW

Figure 2.18

NMI interrupt input timing

IRQ

t_IRQW

Figure 2.19

IRQ interrupt input timing

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2. Electrical Characteristics

2.3.6

Bus Timing

Table 2.18

Conditions:

Bus timing

BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz.

VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0.

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF.

EBCLK: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Others: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

t_AD

Min

Max

12.5

-

Unit

ns

Test conditions

Address delay

CS delay

-

Figure 2.20 to

Figure 2.25

t_CSD

-

ALE delay time

RD delay

t_ALED

t_RSD

-

Read data setup time

Read data hold time

WR0 delay

t_RDS

12.5

t_RDH

t_WRD

t_WDD

t_WDH

t_WTS

t_WTH

0

-

12.5

-

Write data delay

Write data hold time

WAIT setup time

WAIT hold time

-

0

12.5

0

-

Figure 2.26

-

Data cycle

T_end

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_n1

T_n2

T_W5

EBCLK

t_AD

Address bus

t_RDSt_RDH

t_AD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_RSD

Data read

(RD)

t_CSD

Chip select

(CSn)

Figure 2.20

Address/data multiplexed bus read access timing

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2. Electrical Characteristics

Address cycle

Data cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_end

T_n1

T_n2

T_n3

T_W5

EBCLK

t_AD

Address bus

t_AD

t_WDD

t_WDH

t_AD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_WRD

Data write

(WR0)

t_CSD

Chip select

(CSn)

Figure 2.21

Address/data multiplexed bus write access timing

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2. Electrical Characteristics

CSRWAIT: 2

RDON:1

CSON: 0

CSROFF: 2

T_W1

T_W2

T_end

T_n1

T_n2

EBCLK

t_AD

A12 to A00

t_CSD

CS7 to CS4, CS1, CS0

t_RSD

RD (read)

t_RDS

t_RDH

D07 to D00 (read)

Figure 2.22

External bus timing for normal read cycle with bus clock synchronized

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2. Electrical Characteristics

CSWWAIT: 2

WRON: 1

WDON: 1*¹

CSWOFF: 2

WDOFF: 1*¹

T_n1

CSON:0

T_W1

T_W2

T_end

T_n2

EBCLK

t_AD

A12 to A00

t_CSD

CS7 to CS4, CS1, CS0

t_WRD

WR0 (write)

t_WDD

t_WDH

D07 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.23

External bus timing for normal write cycle with bus clock synchronized

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2. Electrical Characteristics

CSRWAIT:2

RDON:1

CSON:0

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSROFF:2

T_W1

T_W2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_n1

T_n2

EBCLK

t_AD

A12 to A00

t_CSD

CS7 to CS4, CS1, CS0

RD (Read)

t_RSD

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

D07 to D00 (Read)

Figure 2.24

External bus timing for page read cycle with bus clock synchronized

CSPWWAIT:2

CSWWAIT:2

WRON:1

WDON:1*¹

CSON:0

CSPWWAIT:2

CSWOFF:2

WRON:1

WDOFF:1*¹

T_dw1

WDOFF:1*¹

T_n1

WDOFF:1*¹

T_dw1

WDON:1*¹

T_pw1

WDON:1*¹

T_pw1

T_W2

T_end

T_pw2

T_W1

T_end

T_n2

EBCLK

t_AD

A12 to A00

t_CSD

CS7 to CS4, CS1, CS0

t_WRD

WR0 (write)

t_WDD

t_WDH

D07 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.25

External bus timing for page write cycle with bus clock synchronized

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2. Electrical Characteristics

CSRWAIT:3

CSWWAIT:3

T_W1

T_W2

T_W3

(T_end

)

T_end

T_n1

T_n2

EBCLK

A12 to A00

CS7 to CS4, CS1, CS0

RD (read)

WR0 (write)

External wait

t_WTSt_WTHt_WTSt_WTH

WAIT

Figure 2.26

External bus timing for external wait control

2.3.7

I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing

Table 2.19

I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (1 of 2)

GPT32 conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

AGT conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test

Parameter

I/O ports

POEG

Symbol Min

Max

Unit

conditions

Input data pulse width

t_PRW

1.5

-

t_Pcyc

t_PDcyc

Figure 2.27

Figure 2.28

Figure 2.29

POEG input trigger pulse width

Input capture pulse width

t_POEW

t_GTICW

3

-

GPT32

Single edge

1.5

-

Dual edge

2.5

-

1

GTIOCxY output skew

(x = 0 to 7, Y= A or B)

Middle drive buffer

High drive buffer

Middle drive buffer

High drive buffer

Middle drive buffer

High drive buffer

t_GTISK

*

-

4

6

5

ns

Figure 2.30

GTIOCxY output skew

(x = 8 to 12, Y = A or B)

GTIOCxY output skew

(x = 0 to 12, Y = A or B)

OPS output skew

GTOUUP, GTOULO, GTOVUP,

GTOVLO, GTOWUP, GTOWLO

t_GTOSK

ns

Figure 2.31

Figure 2.32

2

GPT

GTIOCxY_Z output skew

t_HRSK

*

-

2.0

(PWM Delay

Generation

Circuit)

(x = 0 to 3, Y = A or B, Z = A)

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2. Electrical Characteristics

Table 2.19

I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (2 of 2)

GPT32 conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

AGT conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test

Parameter

Symbol Min

Max

Unit

ns

conditions

3

AGT

AGTIO, AGTEE input cycle

t_ACYC

*

100

40

-

Figure 2.33

AGTIO, AGTEE input high width, low width

t_ACKWH

t_ACKWL

,

ns

AGTIO, AGTO, AGTOA, AGTOB output cycle

ADC12 trigger input pulse width

t_ACYC2

t_TRGW

62.5

1.5

-

ns

ADC12

KINT

t_Pcyc

Figure 2.34

Figure 2.35

KRn(n = 00 to 07) pulse width

t_KR

250

-

ns

Note:

t_Pcyc: PCLKB cycle, t_PDcyc: PCLKD cycle.

Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not

guaranteed.

Note 2. The load is 30 pF.

Note 3. Constraints on input cycle:

When not switching the source clock: t_Pcyc× 2 < t_ACYCshould be satisfied.

When switching the source clock: t_Pcyc× 6 < t_ACYCshould be satisfied.

Port

t_PRW

Figure 2.27

I/O ports input timing

POEG input trigger

t_POEW

Figure 2.28

POEG input trigger timing

Input capture

t_GTICW

Figure 2.29

GPT32 input capture timing

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2. Electrical Characteristics

PCLKD

Output delay

GPT32 output

t_GTISK

Figure 2.30

Figure 2.31

Figure 2.32

GPT32 output delay skew

PCLKD

Output delay

GPT32 output

t_GTOSK

GPT32 output delay skew for OPS

PCLKD

Output delay

GPT32 output

(PWM delay

generation circuit)

t_HRSK

GPT32 (PWM delay generation circuit) output delay skew

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2. Electrical Characteristics

t_ACYC

t_ACKWL

t_ACKWH

AGTIO, AGTEE

(input)

t_ACYC2

AGTIO, AGTO,

AGTOA, AGTOB

(output)

Figure 2.33

AGT input/output timing

ADTRG0,

ADTRG1

t_TRGW

Figure 2.34

ADC12 trigger input timing

KR00 to KR07

t_KR

Figure 2.35

Key interrupt input timing

2.3.8

PWM Delay Generation Circuit Timing

Table 2.20

PWM Delay Generation Circuit timing

Parameter

Min

Typ

-

Max

Unit

Test conditions

Operation frequency

Resolution

80

-

120

MHz

ps

-

260

±2.0

-

PCLKD = 120 MHz

-

DNL*¹

-

LSB

Note 1. This value normalizes the differences between lines in 1-LSB resolution.

2.3.9

CAC Timing

Table 2.21

CAC timing

Test

Parameter

Symbol Min

Typ

Max

Unit

ns

conditions

2

CAC

CACREF input pulse width

t_PBcyc≤ t_cac

*

t_CACREF4.5 × t_cac+ 3 × t_PBcyc

5 × t_cac+ 6.5 × t_PBcyc

-

t_PBcyc> t_cac

*

ns

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2. Electrical Characteristics

Note 1. t_PBcyc: PCLKB cycle.

Note 2. t_cac: CAC count clock source cycle.

2.3.10

SCI Timing

Table 2.22

SCI timing (1)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SCK0 to SCK4,

SCK8, SCK9.

For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test

conditions

Parameter

Symbol Min

Max

Unit^*1

SCI

Input clock cycle

Asynchronous

t_Scyc

4

6

-

t_Pcyc

Figure 2.36

Clock

synchronous

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t_SCKW

t_SCKr

t_SCKf

t_Scyc

0.4

-

0.6

5

t_Scyc

ns

-

5

ns

Asynchronous

6

-

t_Pcyc

Clock

4

-

synchronous

Output clock pulse width

Output clock rise time

Output clock fall time

Transmit data delay

t_SCKW

t_SCKr

t_SCKf

t_TXD

0.4

0.6

5

t_Scyc

ns

-

5

ns

Clock

25

ns

Figure 2.37

synchronous

Receive data setup time

Receive data hold time

Clock

synchronous

t_RXS

t_RXH

15

5

-

ns

Clock

synchronous

Note 1. t_Pcyc: PCLKA cycle.

t_SCKW

t_SCKr

t_SCKf

SCKn

(n = 0 to 4, 8, 9)

t_Scyc

Figure 2.36

SCK clock input/output timing

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2. Electrical Characteristics

SCKn

TxDn

t_TXD

t_RXSt_RXH

RxDn

(n = 0 to 4, 8, 9)

Figure 2.37

Table 2.23

SCI input/output timing in clock synchronous mode

SCI timing (2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SCK0 to SCK4,

SCK8, SCK9.

For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test

Parameter

Symbol

Min

Max

Unit

conditions

Simple SCK clock cycle output

t_SPcyc

4 (PCLKA ≤ 60 MHz)

8 (PCLKA > 60 MHz)

65536

t_Pcyc

Figure 2.38

SPI

(master)

SCK clock cycle input (slave)

-

6 (PCLKA ≤ 60 MHz)

12 (PCLKA > 60 MHz)

65536

SCK clock high pulse width

SCK clock low pulse width

SCK clock rise and fall time

Data input setup time

Data input hold time

t_SPCKWH

t_SPCKWL

t_SPCKr, t_SPCKf

t_SU

0.4

0.6

t_SPcyc

ns

0.4

0.6

-

20

33.3

-

ns

Figure 2.39 to

Figure 2.42

t_H

33.3

-

ns

SS input setup time

t_LEAD

t_LAG

1

-

t_SPcyc

ns

SS input hold time

1

-

Data output delay

t_OD

-

33.3

-

Data output hold time

Data rise and fall time

SS input rise and fall time

Slave access time

t_OH

-10

ns

t

_Dr, t_Df

-

16.6

ns

_SSLr, t_SSLf

ns

t_SA

4 (PCLKA ≤ 60 MHz)

8 (PCLKA > 60 MHz)

t_Pcyc

Figure 2.42

Slave output release time

t_REL

-

5 (PCLKA ≤ 60 MHz)

10 (PCLKA > 60 MHz)

t_Pcyc

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2. Electrical Characteristics

t_SPCKr

t_SPCKf

t_SPCKWH

V_OH

V_OL

V_OH

SCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

SCKn

slave select input

V_IL

t_SPCKWL

V_IL

(n = 0 to 4, 8, 9)

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Figure 2.38

SCI simple SPI mode clock timing

SCKn

CKPOL = 0

output

SCKn

CKPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 4, 8, 9)

Figure 2.39

SCI simple SPI mode timing for master when CKPH = 1

SCKn

CKPOL = 1

output

SCKn

CKPOL = 0

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 4, 8, 9)

Figure 2.40

SCI simple SPI mode timing for master when CKPH = 0

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2. Electrical Characteristics

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 0

input

SCKn

CKPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

(n = 0 to 4, 8, 9)

Figure 2.41

SCI simple SPI mode timing for slave when CKPH = 1

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(Last data)

MSB OUT

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

LSB IN

(n = 0 to 4, 8, 9)

Figure 2.42

SCI simple SPI mode timing for slave when CKPH = 0

Table 2.24

SCI timing (3) (1 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

t_Sr

Min

Max

1000

300

Unit

ns

Test conditions

Simple IIC

(Standard mode)

SDA input rise time

-

Figure 2.43

SDA input fall time

t_Sf

-

ns

SDA input spike pulse removal time

Data input setup time

t_SP

0

4 × t_IICcyc

ns

t_SDAS

t_SDAH

250

-

ns

Data input hold time

0

-

ns

1

SCL, SDA capacitive load

C_b*

400

pF

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2. Electrical Characteristics

Table 2.24

SCI timing (3) (2 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

t_Sr

Min

Max

Unit

ns

Test conditions

Simple IIC

SDA input rise time

-

300

Figure 2.43

(Fast mode)

SDA input fall time

t_Sf

-

300

ns

SDA input spike pulse removal time

Data input setup time

t_SP

0

4 × t_IICcyc

ns

t_SDAS

t_SDAH

100

-

ns

Data input hold time

0

-

ns

1

SCL, SDA capacitive load

C_b*

400

pF

Note:

t_IICcyc: IIC internal reference clock (IICφ) cycle.

Note 1. Cb indicates the total capacity of the bus line.

V_IH

V_IL

SDAn

t_Sr

t_Sf

t_SP

SCLn

P*¹

S*¹

Sr*¹

(n = 0 to 4, 8, 9)

t_SDAH

t_SDAS

Note 1. S, P, and Sr indicate the following:

S: Start condition

Test conditions:

_IH= VCC × 0.7, V_IL= VCC × 0.3

V_OL= 0.6 V, I_OL= 6 mA

V

P: Stop condition

Sr: Restart condition

Figure 2.43

SCI simple IIC mode timing

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2. Electrical Characteristics

2.3.11

SPI Timing

Table 2.25

Conditions:

SPI timing

For RSPCKA and RSPCKB pins, high drive output is selected with the Port Drive Capability bit in the PmnPFS register.

For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

SPI RSPCK clock cycle

Symbol Min

t_SPcyc2 (PCLKA  60 MHz)

Max

Unit*¹Test conditions*²

Master

4096

t_Pcyc

Figure 2.44

C = 30 pF

4 (PCLKA > 60 MHz)

Slave

4

4096

-

RSPCK clock high

pulse width

Master

t_SPCKWH(t_SPcyc- t_SPCKr

_SPCKf) / 2 - 3

-

ns

t

Slave

2 × t_Pcyc

-

RSPCK clock low pulse Master

width

t_SPCKWL(t_SPcyc- t_SPCKr

ns

t

_SPCKf) / 2 - 3

Slave

2 × t_Pcyc

-

RSPCK clock rise and Master

t_SPCKr,

t_SPCKf

-

5

1

-

ns

µs

ns

fall time

Slave

-

Data input setup time

Data input hold time

Master

Slave

t_SU

4

5

0

Figure 2.45 to

Figure 2.50

C = 30 pF

-

Master

t_HF

-

ns

(PCLKA division ratio

set to 1/2)

Master

t_H

t_Pcyc

-

(PCLKA division ratio

set to a value other

than 1/2)

Slave

t_H

20

-

SSL setup time

SSL hold time

Master

t_LEAD

N × t_SPcyc- 10*³

N ×

t_SPcyc

100*³

ns

+

Slave

6 x t_Pcyc

-

ns

Master

t_LAG

N × t_SPcyc- 10 *⁴

N ×

t_SPcyc

100*⁴

Slave

6 x t_Pcyc

-

ns

Data output delay

Master

Slave

t_OD

t_OH

t_TD

-

6.3

20

-

Data output hold time

Master

Slave

0

ns

0

-

Successive

Master

t_SPcyc+ 2 × t_Pcyc

8 ×

transmission delay

t_SPcyc

+

2 × t_Pcyc

Slave

Output

Input

6 × t_Pcyc

MOSI and MISO rise

and fall time

t_Dr,t_Df

-

5

1

5

1

ns

μs

ns

μs

SSL rise and fall time

Output

Input

t_SSLr,

t_SSLf

Slave access time

t_SA

2 x t_Pcycns

+ 28

Figure 2.49 and

Figure 2.50

C = 30_PF

Slave output release time

t_REL

-

2 x t_Pcyc

+ 28

Note 1. t_Pcyc: PCLKA cycle.

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2. Electrical Characteristics

Note 2. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SPI

interface, the AC portion of the electrical characteristics is measured for each group.

Note 3. N is set to an integer from 1 to 8 by the SPCKD register.

Note 4. N is set to an integer from 1 to 8 by the SSLND register.

t_SPCKr

t_SPCKf

t_SPCKWH

SPI

V_OH

V_OL

V_OH

RSPCKn

master select

output

V_OL

t_SPCKWL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

RSPCKn

slave select input

V_IL

t_SPCKWL

t_SPcyc

n = A or B

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Figure 2.44

SPI clock timing

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.45

SPI timing for master when CPHA = 0

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2. Electrical Characteristics

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_HF

MISOn

input

LSB IN

MSB IN

DATA

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.46

SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.47

SPI timing for master when CPHA = 1

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2. Electrical Characteristics

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_HF

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.48

RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2

SPI

t_TD

SSLn0

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

MSB OUT

t_H

MSB IN

t_OD

t_REL

MSB IN

MISOn

output

DATA

LSB OUT

LSB IN

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIn

input

DATA

n = A or B

Figure 2.49

SPI timing for slave when CPHA = 0

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2. Electrical Characteristics

SPI

t_TD

SSLAn

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(last data)

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIn

input

MSB IN

LSB IN

n = A or B

Figure 2.50

SPI timing for slave when CPHA = 1

2.3.12

QSPI Timing

Table 2.26

QSPI timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

QSPI QSPCK clock cycle

Symbol

t_QScyc

t_QSWH

t_QSWL

t_Su

Min

Max

Unit*¹

t_Pcyc

ns

Test conditions

2

48

Figure 2.51

QSPCK clock high pulse width

QSPCK clock low pulse width

Data input setup time

t_QScyc× 0.4

-

t_QScyc× 0.4

-

ns

8

-

ns

Figure 2.52

Data input hold time

t_IH

0

-

ns

QSSL setup time

t_LEAD

(N+0.5) x

t

(N+0.5) x

t

_Qscyc+100 *²

ns

_Qscyc- 5 *²

QSSL hold time

t_LAG

(N+0.5) x

_Qscyc- 5 *³

(N+0.5) x

t

_Qscyc+100 *³

ns

t

Data output delay

t_OD

t_OH

t_TD

-

4

ns

Data output hold time

Successive transmission delay

-3.3

1

-

ns

16

t_QScyc

Note 1. t_Pcyc: PCLKA cycle.

Note 2. N is set to 0 or 1 in SFMSLD.

Note 3. N is set to 0 or 1 in SFMSHD.

t_QSWH

t_QSWL

QSPCLK output

t_QScyc

Figure 2.51

QSPI clock timing

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2. Electrical Characteristics

t_TD

QSSL

output

t_LEAD

t_LAG

QSPCLK

output

t_SU

t_H

QIO0-3

input

MSB IN

DATA

LSB IN

t_OH

t_OD

QIO0-3

output

MSB OUT

DATA

LSB OUT

IDLE

Figure 2.52

Transmit and receive timing

2.3.13

IIC Timing

Table 2.27

IIC timing (1) (1 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.

(2) The following pins do not require setting: SCL0_A, SDA0_A.

(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Test

Parameter

Symbol Min*¹

Max

Unit conditions*³

IIC

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 1300

-

ns

Figure 2.53

(Standard mode,

SMBus)

ICFER.FMPE = 0

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

3 (6) × t_IICcyc+ 300

-

3 (6) × t_IICcyc+ 300

-

1000

t_Sf

-

300

SCL, SDA input spike pulse removal t_SP

time

0

1 (4) × t_IICcyc

SDA input bus free time when

wakeup function is disabled

t_BUF

3 (6) × t_IICcyc+ 300

-

ns

SDA input bus free time when

wakeup function is enabled

t_BUF

3 (6) × t_IICcyc+ 4 × t_Pcyc

+ 300

START condition input hold time

when wakeup function is disabled

t_STAH

t_STAS

t_IICcyc+ 300

START condition input hold time

when wakeup function is enabled

1 (5) × t_IICcyc+ t_Pcyc

300

+

Repeated START condition input

setup time

1000

STOP condition input setup time

Data input setup time

t_STOS

t_SDAS

t_SDAH

C_b

1000

-

ns

pF

t_IICcyc+ 50

-

Data input hold time

0

-

SCL, SDA capacitive load

400

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2. Electrical Characteristics

Table 2.27

IIC timing (1) (2 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.

(2) The following pins do not require setting: SCL0_A, SDA0_A.

(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Test

Parameter

Symbol Min*¹

Max

Unit conditions*³

IIC

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 600

-

ns

Figure 2.53

(Fast mode)

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

3 (6) × t_IICcyc+ 300

-

20 × (external pullup

voltage/5.5V)*²

300

SCL, SDA input fall time

t_Sf

20 × (external pullup

voltage/5.5V)*²

300

ns

SCL, SDA input spike pulse removal t_SP

time

0

1 (4) × t_IICcyc

SDA input bus free time when

wakeup function is disabled

t_BUF

3 (6) × t_IICcyc+ 300

-

SDA input bus free time when

wakeup function is enabled

t_BUF

3 (6) × t_IICcyc+ 4 × t_Pcyc

+ 300

START condition input hold time

when wakeup function is disabled

t_STAH

t_STAS

t_IICcyc+ 300

START condition input hold time

when wakeup function is enabled

1 (5) × t_IICcyc+ t_Pcyc

300

+

Repeated START condition input

setup time

300

STOP condition input setup time

Data input setup time

t_STOS

t_SDAS

t_SDAH

C_b

300

-

ns

pF

t_IICcyc+ 50

-

Data input hold time

0

-

SCL, SDA capacitive load

400

Note:

t_IICcyc: IIC internal reference clock (IICφ) cycle, t_Pcyc: PCLKB cycle.

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 2. Only supported for SCL0_A, SDA0_A.

Note 3. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC

interface, the AC portion of the electrical characteristics is measured for each group.

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2. Electrical Characteristics

Table 2.28

IIC timing (2)

Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.

Test

Parameter

Symbol Min*^1,*²

Max

Unit conditions

IIC

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 240

-

ns

Figure 2.53

(Fast mode+)

ICFER.FMPE = 1

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

3 (6) × t_IICcyc+ 120

-

3 (6) × t_IICcyc+ 120

-

120

t_Sf

-

120

SCL, SDA input spike pulse removal

time

t_SP

0

1 (4) × t_IICcyc

SDA input bus free time when

wakeup function is disabled

t_BUF

3 (6) × t_IICcyc+ 120

-

ns

SDA input bus free time when

wakeup function is enabled

t_BUF

3 (6) × t_IICcyc+ 4 × t_Pcyc

+ 120

Start condition input hold time when

wakeup function is disabled

t_STAH

t_IICcyc+ 120

START condition input hold time

when wakeup function is enabled

1 (5) × t_IICcyc+ t_Pcyc

120

+

Restart condition input setup time

Stop condition input setup time

Data input setup time

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

120

-

ns

pF

120

-

t_IICcyc+ 30

-

Data input hold time

0

-

SCL, SDA capacitive load

550

Note:

t_IICcyc: IIC internal reference clock (IICφ) cycle, t_Pcyc: PCLKB cycle.

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 2. Cb indicates the total capacity of the bus line.

V_IH

SDA0, SDA1

V_IL

t_BUF

t_SCLH

t_STAS

t_STOS

t_STAH

t_SP

SCL0, SCL1

P*¹

S*¹

Sr*¹

t_SCLL

t_Sr

t_Sf

t_SDAS

t_SCL

t_SDAH

Test conditions:

Note 1. S, P, and Sr indicate the following:

S: Start condition

V

_IH= VCC × 0.7, V_IL= VCC × 0.3

_OL= 0.6 V, I_OL= 6 mA (ICFER.FMPE = 0)

_OL= 0.4 V, I_OL= 15 mA (ICFER.FMPE = 1)

P: Stop condition

Sr: Restart condition

Figure 2.53

I²C bus interface input/output timing

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2.3.14

2. Electrical Characteristics

SSIE Timing

Table 2.29

SSIE timing

(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.

(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface,

the AC portion of the electrical characteristics is measured for each group.

Target specification

Parameter

Symbol

Min.

80

0.35

-

Max.

Unit

ns

Comments

SSIBCK0

Cycle

Master

Slave

t_O

-

Figure 2.54

t_I

-

ns

High level/low level

Master

Slave

t_HC/t_LC

-

t_O

-

t_I

Rising time/falling time Master

Slave

t_RC/t_FC

0.15

t_O/ t_I

ns

-

0.15

SSILRCK0/SSIFS0, Input set up time

SSITXD0, SSIRXD0

Master

Slave

t_SR

12

8

-

Figure 2.56,

Figure 2.57

-

ns

Input hold time

Master

Slave

t_HR

-

ns

15

-10

0

-

ns

Output delay time

Master

Slave

t_DTR

5

20

ns

Figure 2.56,

Figure 2.57

Output delay time from Slave

SSILRCK0/SSIFS0

change

t_DTRW

-

20

ns

Figure 2.58*¹

GTIOC1A,

AUDIO_CLK

Cycle

t_EXcyc

t_EXL

t_EXH

20

-

ns

Figure 2.55

High level/low level

/

0.4

0.6

t_EXcyc

Note 1. For slave-mode transmission, SSIE has a path through which the signal input from the SSILRCK0/SSIFS0 pin is used to

generate transmit data, and the transmit data is logically output to the SSITXD0 pin.

t_HC

t_RC

t_FC

t_LC

SSIBCK0

t_O, t_I

Figure 2.54

SSIE clock input/output timing

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2. Electrical Characteristics

t_EXcyc

t_EXH

t_EXL

GTIOC1A,

AUDIO_CLK

(input)

1/2 VCC

t_EXf

t_EXr

Figure 2.55

Clock input timing

SSIBCK0

(input or output)

SSILRCK0/SSIFS0 (input),

SSIRXD0 (input)

t_SR

t_HR

SSILRCK0/SSIFS0 (output),

SSITXD0 (output)

t_DTR

Figure 2.56

SSIE data transmit and receive timing when SSICR.BCKP = 0

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2. Electrical Characteristics

SSIBCK0

(input or output)

SSILRCK0/SSIFS0 (input),

SSIRXD0 (input)

t_SR

t_HR

SSILRCK0/SSIFS0 (output),

SSITXD0 (output)

t_DTR

Figure 2.57

SSIE data transmit and receive timing when SSICR.BCKP = 1

SSILRCK0/SSIFS0 (input)

SSITXD0 (output)

t_DTRW

MSB bit output delay after SSILRCK0/SSIFS0 change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.

Figure 2.58

SSIE data output delay after SSILRCK0/SSIFS0 change

2.3.15

SD/MMC Host Interface Timing

Table 2.30

SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Parameter

Symbol

T_SDCYC

T_SDWH

T_SDWL

T_SDLH

Min

20

6.5

-

Max

Unit

ns

Test conditions*¹

SDCLK clock cycle

-

Figure 2.59

SDCLK clock high pulse width

SDCLK clock low pulse width

SDCLK clock rise time

-

3

5

-

SDCLK clock fall time

T_SDHL

-

SDCMD/SDDAT output data delay

SDCMD/SDDAT input data setup

SDCMD/SDDAT input data hold

T_SDODLY

T_SDIS

-6

4

T_SDIH

2

-

Note 1. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership.

For the SD/MMC Host interface, the AC portion of the electrical characteristics is measured for each group.

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2. Electrical Characteristics

T_SDCYC

T_SDWL

T_SDWH

SDnCLK

(output)

T_SDLH

T_SDHL

T_SDODLY(max)

T_SDODLY(min)

SDnCMD/SDnDATm

(output)

T_SDIS

T_SDIH

SDnCMD/SDnDATm

(input)

n = 0, 1, m = 0 to 3

Figure 2.59

SD/MMC Host Interface signal timing

2.4

USB Characteristics

2.4.1

USBFS Timing

Table 2.31

USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, UCLK = 48 MHz

Parameter

Symbol

V_IH

Min

2.0

-

Typ

Max

-

Unit

V

Test conditions

Input

characteristics

Input high voltage

-

Input low voltage

V_IL

0.8

-

V

-

Differential input sensitivity

V_DI

0.2

0.8

V

| USB_DP - USB_DM |

-

Differential common-mode

range

V_CM

2.5

V

Output

characteristics

Output high voltage

Output low voltage

Cross-over voltage

Rise time

V_OH

V_OL

V_CRS

t_LR

2.8

0.0

1.3

75

-

3.6

V

I_OH= -200 μA

I_OL= 2 mA

0.3

V

2.0

V

Figure 2.60

300

125

24.80

ns

%

kΩ

Fall time

t_LF

75

Rise/fall time ratio

t

_LR/ t_LF

80

t_LR/ t_LF

-

Pull-up and pull-

down

characteristics

USB_DP and USB_DM pull-

down resistance in host

controller mode

R_pd

14.25

90%

V_CRS

USB_DP,

USB_DM

10%

t_LR

USB_DP and USB_DM output timing in low-speed mode

10%

t_LF

Figure 2.60

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2. Electrical Characteristics

Observation

point

USB_DP

USB_DM

200 pF to

600 pF

3.6 V

27 

1.5 K

200 pF to

600 pF

Figure 2.61

Table 2.32

Test circuit in low-speed mode

USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, UCLK = 48 MHz

Parameter

Symbol

V_IH

Min

2.0

-

Typ

Max

-

Unit

V

Test conditions

Input

characteristics

Input high voltage

-

Input low voltage

V_IL

0.8

-

V

-

Differential input sensitivity

V_DI

0.2

0.8

V

| USB_DP - USB_DM |

-

Differential common-mode

range

V_CM

2.5

V

Output

characteristics

Output high voltage

Output low voltage

Cross-over voltage

Rise time

V_OH

V_OL

2.8

0.0

1.3

4

-

3.6

V

I_OH= -200 μA

I_OL= 2 mA

0.3

V

V_CRS

t_LR

2.0

V

Figure 2.62

20

ns

%

Ω

Fall time

t_LF

4

20

Rise/fall time ratio

Output resistance

t_LR/ t_LF

Z_DRV

R_pu

90

111.11

44

t_FR/ t_FF

28

USBFS: Rs = 27 Ω included

During idle state

Pull-up and pull- DM pull-up resistance in

down

characteristics

0.900

1.425

1.575

3.090

kΩ

device controller mode

During transmission and

reception

USB_DP and USB_DM pull-

down resistance in host

controller mode

R_pd

14.25

-

24.80

kΩ

-

90%

V_CRS

USB_DP,

USB_DM

10%

t_FR

10%

t_FF

Figure 2.62

USB_DP and USB_DM output timing in full-speed mode

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2. Electrical Characteristics

Observation

point

USB_DP

USB_DM

50 pF

27 

Figure 2.63

Test circuit in full-speed mode

2.5

ADC12 Characteristics

Table 2.33

A/D conversion characteristics for unit 0 (1 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

60

30

-

Unit

MHz

pF

Test conditions

Frequency

1

-

Analog input capacitance

Quantization error

Resolution

-

±0.5

LSB

Bits

μs

-

12

-

Channel-dedicated

sample-and-hold

circuits in use*³

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

1.06

(0.4 + 0.25)*²

 Sampling of channel-

dedicated sample-and-hold

circuits in 24 states

(AN000 to AN002)

 Sampling in 15 states

Offset error

-

±1.5

±3.5

LSB

AN000 to AN002 = 0.25 V

Full-scale error

AN000 to AN002 =

VREFH0- 0.25 V

Absolute accuracy

-

±2.5

±1.0

±1.5

-

±5.5

±2.0

±3.0

20

LSB

μs

-

DNL differential nonlinearity error

INL integral nonlinearity error

Holding characteristics of sample-and hold

circuits

Dynamic range

0.25

-

VREFH0

- 0.25

V

-

Channel-dedicated

sample-and-hold

circuits not in use

(AN000 to AN002)

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.48 (0.267)*²

-

μs

Sampling in 16 states

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

High-precision

channels

(AN003, AN005,

AN006)

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.48 (0.267)*²

Sampling in 16 states

Max. = 400 Ω

0.40 (0.183)*²

-

μs

Sampling in 11 states

VCC = AVCC0 = 3.0 to 3.6 V

3.0 V ≤ VREFH0 ≤ AVCC0

Offset error

-

±1.0

±2.0

±0.5

±2.5

±4.5

±1.5

LSB

-

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

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2. Electrical Characteristics

Table 2.33

A/D conversion characteristics for unit 0 (2 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

Unit

Test conditions

High-precision

channels

INL integral nonlinearity error

-

±1.0

±2.5

LSB

-

(AN003, AN005,

AN006)

High-precision

channels

(AN007)

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.75 (0.533)*²

-

μs

Sampling in 32 states

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

Normal-precision

channels

Conversion time*¹

(Operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.88 (0.667)*²

Sampling in 40 states

(AN016 to AN018,

AN020)

Offset error

-

±1.0

±2.0

±0.5

±1.0

±5.5

±7.5

±4.5

±5.5

LSB

-

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during

A/D conversion, the values might not fall within the indicated ranges.

The use of ports 0 as digital outputs is not allowed when the 12-bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage

are stable.

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Note 2. Values in parentheses indicate the sampling time.

Note 3. When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.35.

Table 2.34

A/D conversion characteristics for unit 1 (1 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

60

30

-

Unit

MHz

pF

Test conditions

Frequency

1

-

Analog input capacitance

Quantization error

Resolution

-

±0.5

LSB

Bits

μs

-

12

-

Channel-dedicated Conversion time*¹

sample-and-hold

circuits in use*³

(AN100 to AN102)

Permissible signal

source impedance

Max. = 1 kΩ

1.06

(0.4 + 0.25)*²

 Sampling of channel-

dedicated sample-and-hold

circuits in 24 states

(operation at

PCLKC = 60 MHz)

 Sampling in 15 states

Offset error

-

±1.5

±3.5

LSB

AN100 to AN102 = 0.25 V

Full-scale error

AN100 to AN102 =

VREFH - 0.25 V

Absolute accuracy

-

±2.5

±1.0

±1.5

-

±5.5

±2.0

±3.0

20

LSB

μs

-

DNL differential nonlinearity error

INL integral nonlinearity error

Holding characteristics of sample-and

hold circuits

Dynamic range

0.25

-

VREFH - 0.25

V

-

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2. Electrical Characteristics

Table 2.34

A/D conversion characteristics for unit 1 (2 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

Unit

Test conditions

Channel-dedicated Conversion time*¹

Permissible signal

source impedance

Max. = 1 kΩ

0.48

-

μs

Sampling in 16 states

sample-and-hold

circuits not in use

(AN100 to AN102)

(Operation at

PCLKC = 60 MHz)

(0.267)*²

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

High-precision

channels

Conversion time*¹

(Operation at

Permissible signal

source impedance

Max. = 1 kΩ

0.48

(0.267)*²

Sampling in 16 states

(AN105, AN106)

PCLKC = 60 MHz)

Max. = 400 Ω

0.40

(0.183)*²

-

μs

Sampling in 11 states

VCC = AVCC0 = 3.0 to 3.6 V

3.0 V ≤ VREFH ≤ AVCC0

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

High-precision

channels

Conversion time*¹

(Operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.75

(0.533)*²

Sampling in 32 states

(AN107)

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

Normal-precision

channels

Conversion time*¹

(Operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.88

(0.667)*²

Sampling in 40 states

(AN116, AN117)

Offset error

-

±1.0

±2.0

±0.5

±1.0

±5.5

±7.5

±4.5

±5.5

LSB

-

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during

A/D conversion, the values might not fall within the indicated ranges.

The use of ports 0 as digital outputs is not allowed when the 12-bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage

are stable.

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Note 2. Values in parentheses indicate the sampling time.

Note 3. When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.35.

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2. Electrical Characteristics

Table 2.35

A/D conversion characteristics for simultaneous use of channel-dedicated sample-and-hold

circuits in unit 0 and unit 1

Conditions: PCLKC = 30/60 MHz

Parameter

Min

Typ

±1.5

±2.5

±4.0

±1.5

±2.5

±4.0

±1.5

±3.0

±1.5

±3.0

Max

±5.0

Test conditions

-

Channel-dedicated sample-and-hold circuits in use Offset error

with continious sampling function enabled

(AN000 to AN002)

 PCLKC = 60 MHz

 Sampling in 15 states

Full-scale error

±5.0

Absolute accuracy

±8.0

Channel-dedicated sample-and-hold circuits in use Offset error

with continious sampling function enabled

(AN100 to AN102)

±5.0

Full-scale error

±5.0

Absolute accuracy

±8.0

Channel-dedicated sample-and-hold circuits in use Offset error

with continious sampling function enabled

(AN000 to AN002)

±3.5

 PCLKC = 30 MHz

 Sampling in 7 states

Full-scale error

±3.5

Absolute accuracy

+4.5/-6.5

±3.5

Channel-dedicated sample-and-hold circuits in use Offset error

with continious sampling function enabled

(AN100 to AN102)

Full-scale error

±3.5

Absolute accuracy

+4.5/-6.5

Note:

When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, setting the ADSHMSR.SHMD bit

to 1 is recommended.

Table 2.36

A/D internal reference voltage characteristics

Parameter

Min

1.13

4.15

Typ

Max

1.23

-

Unit

V

Test conditions

A/D internal reference voltage

Sampling time

1.18

-

μs

FFFh

Full-scale error

Integral nonlinearity

error (INL)

A/D converter

output code

Ideal line of actual A/D

conversion characteristic

Actual A/D conversion

characteristic

Ideal A/D conversion

characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

000h

Offset error

0

Analog input voltage

VREFH0

(full-scale)

Figure 2.64

Illustration of ADC12 characteristic terms

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2. Electrical Characteristics

Absolute accuracy

Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the

actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog

input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D

conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference

voltage VREFH0 is 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the

analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D

conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical

A/D conversion characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale

errors are zeroed, and the actual output code.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion

characteristics and the width of the actual output code.

Offset error

Offset error is the difference between the transition point of the ideal first output code and the actual first output code.

Full-scale error

Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.6

DAC12 Characteristics

Table 2.37

D/A conversion characteristics

Parameter

Min

Typ

Max

Unit

Test conditions

Resolution

-

12

Bits

-

Without output amplifier

Absolute accuracy

INL

-

±24

±8.0

±2.0

-

LSB

kΩ

Resistive load 2 MΩ

±2.0

±1.0

8.5

-

Resistive load 2 MΩ

DNL

-

Output impedance

Conversion time

3.0

μs

Resistive load 2 MΩ,

Capacitive load 20 pF

Output voltage range

With output amplifier

INL

0

-

VREFH

V

-

±2.0

±4.0

LSB

μs

-

DNL

-

±1.0

±2.0

Conversion time

Resistive load

Capacitive load

Output voltage range

-

4.0

5

-

kΩ

pF

-

50

0.2

VREFH - 0.2

V

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2. Electrical Characteristics

2.7

TSN Characteristics

Table 2.38

Parameter

TSN characteristics

Symbol

Min

Typ

±1.0

4.0

1.24

-

Max

Unit

°C

Test conditions

Relative accuracy

-

Temperature slope

-

mV/°C

V

Output voltage (at 25°C)

Temperature sensor start time

Sampling time

-

t_START

-

30

-

μs

4.15

-

μs

2.8

OSC Stop Detect Characteristics

Table 2.39

Oscillation stop detection circuit characteristics

Parameter

Symbol

Min

Typ

Max

Unit

ms

Test conditions

Detection time

t_dr

-

1

Figure 2.65

Main clock

tdr

OSTDSR.OSTDF

MOCO clock

ICLK

Figure 2.65

Oscillation stop detection timing

2.9

POR and LVD Characteristics

Table 2.40

Parameter

Power-on reset circuit and voltage detection circuit characteristics (1 of 2)

Test

conditions

Symbol

DPSBYCR.DEEPCUT[1:0] = V_POR

Min

Typ

Max

Unit

Voltage detection

level

Power-on reset

(POR)

2.5

2.6

2.7

V

Figure 2.66

00b or 01b

DPSBYCR.DEEPCUT[1:0] =

11b

1.8

2.25

2.7

Voltage detection circuit (LVD0)

Voltage detection circuit (LVD1)

Voltage detection circuit (LVD2)

V_{det0_1}

V_{det0_2}

V_{det0_3}

V_{det1_1}

V_{det1_2}

V_{det1_3}

V_{det2_1}

V_{det2_2}

V_{det2_3}

2.84

2.77

2.70

2.89

2.82

2.75

2.89

2.82

2.75

2.94

2.87

2.80

2.99

2.92

2.85

2.99

2.92

2.85

3.04

2.97

2.90

3.09

3.02

2.95

3.09

3.02

2.95

Figure 2.67

Figure 2.68

Figure 2.69

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2. Electrical Characteristics

Table 2.40

Power-on reset circuit and voltage detection circuit characteristics (2 of 2)

Test

Parameter

Symbol

t_POR

Min

Typ

4.5

Max

Unit

conditions

Internal reset time Power-on reset time

LVD0 reset time

-

ms

Figure 2.66

Figure 2.67

Figure 2.68

Figure 2.69

t_LVD0

t_LVD1

t_LVD2

t_VOFF

-

0.51

0.38

-

LVD1 reset time

-

LVD2 reset time

-

Minimum VCC down time*¹

200

μs

Figure 2.66,

Figure 2.67

Response delay

t_det

-

200

Figure 2.66 to

Figure 2.69

LVD operation stabilization time (after LVD is enabled)

Hysteresis width (LVD1 and LVD2)

t_d(E-A)

V_LVH

-

10

-

μs

Figure 2.68,

Figure 2.69

70

mV

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR

,

V_det1, and V_det2for POR and LVD.

t_VOFF

V_POR

VCC

Internal reset signal

(active-low)

t_det

t_POR

t_det

t_dett_POR

Figure 2.66

Power-on reset timing

t_VOFF

VCC

V_det0

Internal reset signal

(active-low)

t_det

t_LVD0

Figure 2.67

Voltage detection circuit timing (V_det0)

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2. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det1

LVCMPCR.LVD1E

t_d(E-A)

LVD1

Comparator output

LVD1CR0.CMPE

LVD1SR.MON

Internal reset signal

(active-low)

When LVD1CR0.RN = 0

t_det

t_LVD1

t_det

When LVD1CR0.RN = 1

t_LVD1

Figure 2.68

Voltage detection circuit timing (V_det1)

t_VOFF

V_LVH

VCC

V_det2

LVCMPCR.LVD2E

t_d(E-A)

LVD2

Comparator output

LVD2CR0.CMPE

LVD2SR.MON

Internal reset signal

(active-low)

When LVD2CR0.RN = 0

t_det

t_LVD2

When LVD2CR0.RN = 1

t_LVD2

Figure 2.69

Voltage detection circuit timing (V_det2)

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2. Electrical Characteristics

2.10 VBATT Characteristics

Table 2.41

Battery backup function characteristics

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.8 to 3.6 V

Parameter

Symbol

Min

2.50

2.70

Typ

2.60

-

Max

2.70

-

Unit

V

Test conditions

Voltage level for switching to battery backup

V_DETBATT

V_BATTSW

Figure 2.70

Lower-limit VBATT voltage for power supply

switching caused by VCC voltage drop

V

VCC-off period for starting power supply switching t_VOFFBATT

200

-

μs

Note:

The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum

value of the voltage level for switching to battery backup (V_DETBATT).

t_VOFFBATT

V_DETBATT

VCC

V_BATT

V_BATTSW

Backup power

area

VCC supply

V_BATTsupply

VCC supply

Figure 2.70

Battery backup function characteristics

2.11 CTSU Characteristics

Table 2.42

Parameter

CTSU characteristics

Symbol

C_tscap

C_base

Σ_IoH

Min

Typ

Max

11

Unit

Test conditions

External capacitance connected to TSCAP pin

TS pin capacitive load

9

-

10

-

nF

pF

mA

-

50

Permissible output high current

-

-40

When the mutual

capacitance method

is applied

2.12 ACMPHS Characteristics

Table 2.43

Parameter

ACMPHS characteristics

Symbol

VREF

VI

Min

Typ

-

Max

Unit

V

Test conditions

Reference voltage range

Input voltage range

Output delay*¹

0

AVCC0

100

-

0

-

V

-

Td

-

50

1.18

ns

V

VI = VREF ± 100 mV

-

Internal reference voltage

Vref

1.13

1.23

Note 1. This value is the internal propagation delay.

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2. Electrical Characteristics

2.13 PGA Characteristics

Table 2.44

PGA characteristics in single mode

Parameter

Symbol

Min

Typ

Max

Unit

PGAVSS input voltage range

PGAVSS

0

-

0

V

AIN0 (G = 2.000)

AIN1 (G = 2.500)

AIN2 (G = 2.667)

AIN3 (G = 2.857)

AIN4 (G = 3.077)

AIN5 (G = 3.333)

AIN6 (G = 3.636)

AIN7 (G = 4.000)

AIN8 (G = 4.444)

AIN9 (G = 5.000)

AIN10 (G = 5.714)

AIN11 (G = 6.667)

AIN12 (G = 8.000)

AIN13 (G = 10.000)

AIN14 (G = 13.333)

Gerr0 (G = 2.000)

Gerr1 (G = 2.500)

Gerr2 (G = 2.667)

Gerr3 (G = 2.857)

Gerr4 (G = 3.077)

Gerr5 (G = 3.333)

Gerr6 (G = 3.636)

Gerr7 (G = 4.000)

Gerr8 (G = 4.444)

Gerr9 (G = 5.000)

Gerr10 (G = 5.714)

Gerr11 (G = 6.667)

Gerr12 (G = 8.000)

Gerr13 (G = 10.000)

Gerr14 (G = 13.333)

Voff

0.050 × AVCC0

0.047 × AVCC0

0.046 × AVCC0

0.045 × AVCC0

0.044 × AVCC0

0.042 × AVCC0

0.040 × AVCC0

0.036 × AVCC0

0.033 × AVCC0

0.031 × AVCC0

0.029 × AVCC0

0.027 × AVCC0

0.025 × AVCC0

0.023 × AVCC0

-1.0

0.45 × AVCC0

V

0.360 × AVCC0

V

0.337 × AVCC0

V

0.32 × AVCC0

V

0.292 × AVCC0

V

0.265 × AVCC0

V

0.247 × AVCC0

V

0.212 × AVCC0

V

0.191 × AVCC0

V

0.17 × AVCC0

V

0.148 × AVCC0

V

0.127 × AVCC0

V

0.09 × AVCC0

V

0.08 × AVCC0

V

0.06 × AVCC0

V

Gain error

1.0

1.5

2.0

8

%

mV

-1.0

-1.5

-2.0

Offset error

-8

Table 2.45

Parameter

PGA characteristics in differential mode (1 of 2)

Symbol

Min

-0.5

-0.4

-0.2

-0.15

Typ

Max

0.3

Unit

V

PGAVSS input voltage range

PGAVSS

-

Differential input

voltage range

G = 1.500

AIN-PGAVSS

0.5

V

G = 2.333

G = 4.000

G = 5.667

0.4

V

0.2

V

0.15

V

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2. Electrical Characteristics

Table 2.45

PGA characteristics in differential mode (2 of 2)

Symbol

Parameter

Min

-1.0

Typ

Max

1.0

Unit

Gain error

G = 1.500

G = 2.333

G = 4.000

G = 5.667

Gerr

-

%

2.14 Flash Memory Characteristics

2.14.1

Code Flash Memory Characteristics

Table 2.46

Code flash memory characteristics

Conditions: Program or erase: FCLK = 4 to 60 MHz

Read: FCLK ≤ 60 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Test

Parameter

Symbol

t_P128

t_P8K

Min

Typ

0.75

49

Max

13.2

Min

Typ

0.34

22

Max

6.0

80

Unit

ms

Times

μs

conditions

Programming time

N_PEC 100 times

128-byte

8-KB

-

176

704

15.8

212

848

216

864

260

1040

-

32-KB

128-byte

8-KB

t_P32K

t_P128

t_P8K

-

194

0.91

60

-

88

320

7.2

96

Programming time

-

0.41

27

N_PEC> 100 times

-

32-KB

8-KB

t_P32K

t_E8K

t_E32K

t_E8K

t_E32K

N_PEC

-

234

78

-

106

43

384

120

480

144

576

-

Erasure time

N_PEC 100 times

-

32-KB

8-KB

-

283

94

-

157

52

Erasure time

N_PEC> 100 times

-

32-KB

-

341

-

189

-

Reprogramming/erasure cycle*⁴

10000*¹

Suspend delay during programming t_SPD

-

264

216

-

120

First suspend delay during erasure in t_SESD1

suspend priority mode

-

μs

Second suspend delay during

erasure in suspend priority mode

t_SESD2

-

1.7

-

1.7

ms

Suspend delay during erasure in

erasure priority mode

t_SEED

Forced stop command

Data hold time*²

t_FD

-

32

-

20

-

μs

3

t_DRP

10*^2,

30*^2,

*

10*^2,

30*^2,

*

Years

3

*

-

*

-

Ta = +85°C

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1

to the minimum value.

Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 3. This result is obtained from reliability testing.

Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10000),

erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different

addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address several times as one erasure is not enabled. Overwriting is prohibited.

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2. Electrical Characteristics

• Suspension during programming

FCU command

Program

Ready

Suspend

t_SPD

FSTATR0.FRDY

Not Ready

Ready

Programming pulse

Programming

• Suspension during erasure in suspend priority mode

FCU command

Erase

Suspend

Not Ready

Erasing

Resume

t_SESD1

t_SESD2

FSTATR0.FRDY

Erasure pulse

Ready

Not Ready

Erasing

• Suspension during erasure in erasure priority mode

FCU command

FSTATR0.FRDY

Erasure pulse

Erase

Suspend

Not Ready

Erasing

t_SEED

Ready

• Forced Stop

Forced Stop

Not Ready

FACI command

t_FD

FSTATR.FRDY

Ready

Figure 2.71

Suspension and forced stop timing for flash memory programming and erasure

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2.14.2

2. Electrical Characteristics

Data Flash Memory Characteristics

Table 2.47

Data flash memory characteristics

Conditions: Program or erase: FCLK = 4 to 60 MHz

Read: FCLK ≤ 60 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Test

Parameter

Symbol

t_DP4

Min

Typ

Max

Min

Typ

Max

1.7

1.8

2.0

10

Unit conditions

Programming time

4-byte

-

0.36

3.8

4.0

4.5

18

-

0.16

ms

8-byte

t_DP8

-

0.38

-

0.17

16-byte

64-byte

128-byte

256-byte

4-byte

t_DP16

-

0.42

-

0.19

Erasure time

t_DE64

-

3.1

-

1.7

ms

t_DE128

t_DE256

t_DBC4

N_DPEC

t_DSPD

-

4.7

27

-

2.6

15

-

8.9

-

50

-

4.9

-

28

Blank check time

-

84

-

30

μs

-

Reprogramming/erasure cycle*¹

125000*²

-

125000*²

-

Suspend delay during 4-byte

-

264

216

300

390

570

300

390

570

32

-

120

300

390

570

300

390

570

20

μs

programming

8-byte

-

16-byte

-

First suspend delay

during erasure in

suspend priority mode

64-byte

t_DSESD1

t_DSESD2

t_DSEED

-

μs

128-byte

256-byte

64-byte

-

Second suspend

delay during erasure

in suspend priority

mode

-

128-byte

256-byte

-

Suspend delay during 64-byte

-

erasing in erasure

priority mode

128-byte

-

256-byte

Forced stop command

Data hold time*³

-

t_FD

-

μs

t_DRP

10*^{3, 4}

*

-

10*^3,*⁴

-

Year

30*^{3, 4}

*

-

30*^{3, 4}

*

-

Ta = +85°C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125000),

erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different

addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address several times as one erasure is not enabled. Overwriting is prohibited.

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1

to the minimum value.

Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 4. This result is obtained from reliability testing.

2.15 Boundary Scan

Table 2.48

Boundary scan characteristics (1 of 2)

Test

Parameter

Symbol

t_TCKcyc

t_TCKH

t_TCKL

Min

100

45

-

Typ

Max

Unit

ns

conditions

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

-

Figure 2.72

-

ns

-

ns

t_TCKr

5

ns

t_TCKf

-

ns

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2. Electrical Characteristics

Table 2.48

Boundary scan characteristics (2 of 2)

Test

Parameter

Symbol

t_TMSS

Min

20

Typ

Max

Unit

conditions

TMS setup time

TMS hold time

-

ns

-

Figure 2.73

t_TMSH

t_TDIS

20

-

TDI setup time

20

-

TDI hold time

t_TDIH

20

-

TDO data delay

Boundary scan circuit startup time*¹

t_TDOD

T_BSSTUP

-

40

-

t_RESWP

Figure 2.74

Note 1. Boundary scan does not function until the power-on reset becomes negative.

t_TCKcyc

t_TCKH

t_TCKf

TCK

t_TCKr

t_TCKL

Figure 2.72

Boundary scan TCK timing

TCK

TMS

TDI

t_TMSS

t_TMSH

t_TDIS

t_TDIH

t_TDOD

TDO

Figure 2.73

Boundary scan input/output timing

VCC

RES

t_BSSTUP

₍₌t_RESWP)

Boundary scan

execute

Figure 2.74

Boundary scan circuit startup timing

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2. Electrical Characteristics

2.16 Joint Test Action Group (JTAG)

Table 2.49

Parameter

JTAG

Test

conditions

Symbol

t_TCKcyc

t_TCKH

t_TCKL

t_TCKr

Min

40

15

-

Typ

Max

Unit

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TMS setup time

-

ns

Figure 2.72

-

5

-

t_TCKf

-

t_TMSS

t_TMSH

t_TDIS

8

Figure 2.73

TMS hold time

8

-

TDI setup time

8

-

TDI hold time

t_TDIH

8

-

TDO data delay time

t_TDOD

-

20

t_TCKcyc

t_TCKH

TCK

t_TCKf

t_TCKr

t_TCKL

Figure 2.75

JTAG TCK timing

TCK

t_TMSS

t_TMSH

TMS

t_TDIS

t_TDIH

TDI

t_TDOD

TDO

Figure 2.76

JTAG input/output timing

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 81 of 92

RA6M1 Group

2. Electrical Characteristics

2.17 Serial Wire Debug (SWD)

Table 2.50

Parameter

SWD

Test

conditions

Symbol

t_SWCKcyc

t_SWCKH

t_SWCKL

t_SWCKr

t_SWCKf

t_SWDS

Min

40

15

-

Typ

Max

Unit

SWCLK clock cycle time

SWCLK clock high pulse width

SWCLK clock low pulse width

SWCLK clock rise time

SWCLK clock fall time

SWDIO setup time

-

ns

Figure 2.77

-

5

-

8

Figure 2.78

SWDIO hold time

t_SWDH

8

-

SWDIO data delay time

t_SWDD

2

28

t_SWCKcyc

t_SWCKH

SWCLK

t_SWCKL

Figure 2.77

SWD SWCLK timing

SWCLK

t_SWDS

t_SWDH

SWDIO

(input)

t_SWDD

SWDIO

(output)

t_SWDD

SWDIO

(output)

t_SWDD

SWDIO

(output)

Figure 2.78

SWD input/output timing

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 82 of 92

RA6M1 Group

2. Electrical Characteristics

2.18 Embedded Trace Macro Interface (ETM)

Table 2.51

ETM

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test

Parameter

Symbol

t_TCLKcyc

t_TCLKH

t_TCLKL

t_TCLKr

Min

33.3

13.6

-

Typ

Max

Unit

conditions

TCLK clock cycle time

TCLK clock high pulse width

TCLK clock low pulse width

TCLK clock rise time

-

ns

Figure 2.79

-

3

-

TCLK clock fall time

t_TCLKf

-

TDATA[3:0] output setup time

TDATA[3:0] output hold time

t_TRDS

3.5

2.5

Figure 2.80

t_TRDH

-

t_TCLKcyc

t_TCLKH

TCLK

t_TCLKf

t_TCLKr

t_TCLKL

Figure 2.79

ETM TCLK timing

TCLK

t_TRDS

t_TRDH

t_TRDS

t_TRDH

TDATA[3:0]

Figure 2.80

ETM output timing

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 83 of 92

RA6M1 Group

Appendix 1. Package Dimensions

Appendix 1.Package Dimensions

Information on the latest version of the package dimensions or mountings is shown in “Packages” on the Renesas

Electronics Corporation website.

JEITA Package Code

P-TFLGA100-7x7-0.65

RENESAS Code

PTLG0100JA-A

Previous Code

100F0G

MASS[Typ.]

0.1g

φ b₁

φ×

M

S

AB

φ b

D

φ×

M

S

AB

w

S A

Z_D

e

A

K

J

H

G

F

B

E

D

C

B

A

Dimension in Millimeters

Reference

Symbol

Min Nom Max

7.0

1

2

3

4

5

6

7

8

9

10

y

S

× 4

D

E

v

Index mark

S

(Laser mark)

0.15

w

A

e

0.20

1.05

0.65

0.31 0.35 0.39

b

b₁0.385 0.435 0.485

x

0.08

0.10

y

Z_D

Z_E

0.575

Figure 1.1

100-pin LGA

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 84 of 92

RA6M1 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

0.6

P-LFQFP100-14x14-0.50

PLQP0100KB-B

—

H_D

Unit: mm

*1

D

75

51

76

50

100

26

1

25

NOTE 4

NOTE)

Index area

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

NOTE 3

F

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Dimensions in millimeters

Min Nom Max

Reference

Symbol

y

S

*3

b

p

e

M

D

E

A₂

H_D

H_E

A

A₁

b_p

c

13.9

14.0 14.1

1.4

15.8

16.0 16.2

1.7

0.15

0.05

0.15

0.09

0q

0.20 0.27

3.5q

0.5

0.20

8q

L_p

L₁

T

e

x

y

L_p

L₁

Detail F

0.08

0.75

0.45

0.6

1.0

Figure 1.2

100-pin LQFP

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 85 of 92

RA6M1 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

0.3

P-LFQFP64-10x10-0.50

PLQP0064KB-C

—

Unit: mm

H_D

*1

D

48

33

49

32

64

17

1

16

NOTE 4

Index area

NOTE 3

NOTE)

F

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

y

S

*3

Dimensions in millimeters

Min Nom Max

Reference

Symbol

b

p

e

M

D

E

A₂

H_D

H_E

A

A₁

b_p

c

9.9

10.0 10.1

1.4

11.8

12.0 12.2

1.7

0.15

0.05

0.15

0.09

0q

0.20 0.27

3.5q

0.5

0.20

8q

L_p

L₁

T

e

x

y

L_p

L₁

Detail F

0.08

0.75

0.45

0.6

1.0

Figure 1.3

64-pin LQFP

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 86 of 92

RA6M1 Group

Appendix 1. Package Dimensions

JEITA Package code

RENESAS code

Previous code

MASS(TYP.)[g]

P-HWQFN64-8x8-0.40

PWQN0064LA-A

P64K8-40-9B5-3

0.16

D

33

48

32

49

DETAIL OF A PART

E

A

A₁

c₂

64

17

16

1

INDEX AREA

A

S

y

S

Dimension in Millimeters

Referance

Symbol

Nom

8.00

Max

8.05

0.80

Min

7.95

D

E

D₂

A

EXPOSED DIE PAD

Lp

A

16

1

A₁

b

0.00

0.17

0.23

0.20

0.40

64

17

e

0.30

0.15

0.50

0.05

Lp

x

B

E₂

y

Z_D

Z_E

c₂

1.00

0.20

6.50

Z_E

32

49

0.25

48

33

D₂

E₂

Z_D

e

M

b

x

S A B

Figure 1.4

64-pin QFN

R01DS0356EJ0100 Rev.1.00

Oct 8, 2019

Page 87 of 92

Revision History

RA6M1 Group Datasheet

Rev.

1.00

Date

Summary

Oct 8, 2019

First release

Proprietary Notice

All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in

this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and

trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no

part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated,

transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior

written consent from Renesas.

®

Arm and Cortex are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.

®

CoreMark is a registered trademark of the Embedded Microprocessor Benchmark Consortium.

Magic Packet™ is a trademark of Advanced Micro Devices, Inc.

®

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States

and Japan.

Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective

holders.

Colophon

RA6M1 Group Datasheet

Publication Date:

Published by:

Rev.1.00

Oct 8, 2019

Renesas Electronics Corporation

Address List

General Precautions

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately

degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and

quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.

This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be

stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit

boards with mounted semiconductor devices.

2. Processing at power-on

The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are

indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished

product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time

when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset

by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches

the level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results

from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in

the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-

off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins

of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,

extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,

and malfunctions occur due to the false recognition of the pin state as an input signal become possible.

5. Clock signals

After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the

clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated

with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full

stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or

by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device

stays in the area between V (Max.) and V (Min.) due to noise, for example, the device may malfunction. Take care to

IL

IH

prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the

input level passes through the area between V (Max.) and V (Min.).

IL

IH

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of

functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the

change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the

same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and

other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,

immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a

system-evaluation test for the given product.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

equipment; industrial robots; etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

not intended or authorized for use in products or systems that may pose

a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause

serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all

liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	R7FA6M1AD3CFP
厂家：	RENESAS TECHNOLOGY CORP
描述：	Armv7E-M architecture with DSP instruction set Maximum operating frequency: 120 MHz
文件：	总92页 (文件大小：1270K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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