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Renesas RA6M3 Group

32

Datasheet

32-Bit MCU

Renesas Advanced (RA) Family

Renesas RA6 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

Rev.1.10 Dec 2020

RA6M3 Group

Datasheet

Leading performance 120-MHz Arm^®Cortex^®-M4 core, up to 2-MB code flash memory, 640-KB SRAM, Graphics LCD

Controller, 2D Drawing Engine, Capacitive Touch Sensing Unit, Ethernet MAC Controller with IEEE 1588 PTP, USB 2.0

High-Speed, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog.

Features

■ Arm Cortex-M4 Core with Floating Point Unit (FPU)

 Armv7E-M architecture with DSP instruction set

 Maximum operating frequency: 120 MHz

■ System and Power Management

 Low power modes

 Realtime Clock (RTC) with calendar and VBATT support

 Event Link Controller (ELC)

 DMA Controller (DMAC) × 8

 Support for 4-GB address space

 On-chip debugging system: JTAG, SWD, and ETM

 Boundary scan and Arm Memory Protection Unit (Arm MPU)

 Data Transfer Controller (DTC)

 Key Interrupt Function (KINT)

 Power-on reset

■ Memory

 Up to 2-MB code flash memory (40 MHz zero wait states)

 64-KB data flash memory (125,000 erase/write cycles)

 Up to 640-KB SRAM

 Low Voltage Detection (LVD) with voltage settings

■ Security and Encryption

 AES128/192/256

 3DES/ARC4

 SHA1/SHA224/SHA256/MD5

 GHASH

 RSA/DSA/ECC

 True Random Number Generator (TRNG)

 Flash Cache (FCACHE)

 Memory Protection Units (MPU)

 Memory Mirror Function (MMF)

 128-bit unique ID

■ Connectivity

 Ethernet MAC Controller (ETHERC)

 Ethernet DMA Controller (EDMAC)

 Ethernet PTP Controller (EPTPC)

 USB 2.0 High-Speed (USBHS) module

- On-chip transceiver with voltage regulator

- Compliant with USB Battery Charging Specification 1.2

 USB 2.0 Full-Speed (USBFS) module

- On-chip transceiver with voltage regulator

 Serial Communications Interface (SCI) with FIFO × 10

 Serial Peripheral Interface (SPI) × 2

 I²C bus interface (IIC) × 3

 Controller Area Network (CAN) × 2

 Serial Sound Interface Enhanced (SSIE) × 2

 SD/MMC Host Interface (SDHI) × 2

 Quad Serial Peripheral Interface (QSPI)

 IrDA interface

■ Human Machine Interface (HMI)

 Graphics LCD Controller (GLCDC)

 JPEG codec

 2D Drawing Engine (DRW)

 Capacitive Touch Sensing Unit (CTSU)

 Parallel Data Capture Unit (PDC)

■ Multiple Clock Sources

 Main clock oscillator (MOSC) (8 to 24 MHz)

 Sub-clock oscillator (SOSC) (32.768 kHz)

 High-speed on-chip oscillator (HOCO) (16/18/20 MHz)

 Middle-speed on-chip oscillator (MOCO) (8 MHz)

 Low-speed on-chip oscillator (LOCO) (32.768 kHz)

 IWDT-dedicated on-chip oscillator (15 kHz)

 Clock trim function for HOCO/MOCO/LOCO

 Clock out support

 Sampling Rate Converter (SRC)

 External address space

- 8-bit or 16-bit bus space is selectable per area

- SDRAM support

■ General-Purpose I/O Ports

 Up to 133 input/output pins

- Up to 9 CMOS input

- Up to 124 CMOS input/output

- Up to 21 input/output 5 V tolerant

- Up to 18 high current (20 mA)

■ Analog

 12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits

each × 2

■ Operating Voltage

 VCC: 2.7 to 3.6 V

 12-bit D/A Converter (DAC12) × 2

 High-Speed Analog Comparator (ACMPHS) × 6

 Programmable Gain Amplifier (PGA) × 6

 Temperature Sensor (TSN)

■ Operating Temperature and Packages

 Ta = -40°C to +85°C

- 176-pin BGA (13 mm × 13 mm, 0.8 mm pitch)

- 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch)

 Ta = -40°C to +105°C

■ Timers

 General PWM Timer 32-bit Enhanced High Resolution

(GPT32EH) × 4

 General PWM Timer 32-bit Enhanced (GPT32E) × 4

 General PWM Timer 32-bit (GPT32) × 6

 Asynchronous General-Purpose Timer (AGT) × 2

 Watchdog Timer (WDT)

- 176-pin LQFP (24 mm × 24 mm, 0.5 mm pitch)

- 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)

- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)

■ Safety

 Error Correction Code (ECC) in SRAM

 SRAM parity error check

 Flash area protection

 ADC self-diagnosis function

 Clock Frequency Accuracy Measurement Circuit (CAC)

 Cyclic Redundancy Check (CRC) calculator

 Data Operation Circuit (DOC)

 Port Output Enable for GPT (POEG)

 Independent Watchdog Timer (IWDT)

 GPIO readback level detection

 Register write protection

 Main oscillator stop detection

 Illegal memory access

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1. Overview

1.

Overview

®

The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share the same set of

Renesas peripherals to facilitate design scalability and efficient platform-based product development.

®

The MCU in this series incorporates a high-performance Arm Cortex -M4 core running up to 120 MHz, with the

following features:



Up to 2-MB code flash memory

640-KB SRAM

Graphics LCD Controller (GLCDC)

2D Drawing Engine (DRW)

Capacitive Touch Sensing Unit (CTSU)

Ethernet MAC Controller (ETHERC) with IEEE 1588 PTP, USBFS, USBHS, SD/MMC Host Interface

Quad Serial Peripheral Interface (QSPI)

Security and safety features

Analog peripherals.

1.1

Function Outline

Table 1.1

Feature

Arm core

Functional description

Arm Cortex-M4 core

 Maximum operating frequency: up to 120 MHz

 Arm Cortex-M4 core:

- Revision: r0p1-01rel0

- ARMv7E-M architecture profile

- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.

 Arm Memory Protection Unit (Arm MPU):

- ARMv7 Protected Memory System Architecture

- 8 protect regions.

 SysTick timer:

- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2

Memory

Feature

Functional description

Code flash memory

Data flash memory

Memory Mirror Function (MMF)

Maximum 2-MB code flash memory. See section 55, Flash Memory in User’s Manual.

64-KB data flash memory. See section 55, Flash Memory in User’s Manual.

The Memory Mirror Function (MMF) can be configured to mirror the target application image

load address in code flash memory to the application image link address in the 23-bit unused

memory space (memory mirror space addresses). Your application code is developed and

linked to run from this MMF destination address. The application code does not need to know

the load location where it is stored in code flash memory. See section 5, Memory Mirror

Function (MMF) in User’s Manual.

Option-setting memory

SRAM

The option-setting memory determines the state of the MCU after a reset. See section 7,

Option-Setting Memory in User’s Manual.

On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). The first

32 KB in SRAM0 provides error correction capability using ECC. Parity check is performed for

other areas. See section 53, SRAM in User’s Manual.

Standby SRAM

On-chip SRAM that can retain data in Deep Software Standby mode. See section 54, Standby

SRAM in User’s Manual.

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1. Overview

Table 1.3

Feature

System (1 of 2)

Functional description

Operating modes

Two operating modes:

- Single-chip mode

- SCI or USB boot mode.

See section 3, Operating Modes in User’s Manual.

Resets

14 resets:

 RES pin reset

 Power-on reset

 Voltage monitor 0 reset

 Voltage monitor 1 reset

 Voltage monitor 2 reset

 Independent watchdog timer reset

 Watchdog timer reset

 Deep software standby reset

 SRAM parity error reset

 SRAM ECC error reset

 Bus master MPU error reset

 Bus slave MPU error reset

 Stack pointer error reset

 Software reset.

See section 6, Resets in User’s Manual.

Low Voltage Detection (LVD)

Clocks

The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and

the detection level can be selected using a software program. See section 8, Low Voltage

Detection (LVD) in User’s Manual.

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 PLL frequency synthesizer

 IWDT-dedicated on-chip oscillator

 Clock out support.

See section 9, Clock Generation Circuit in User’s Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock to be used as a

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.

When measurement is complete or the number of pulses within the time generated by the

measurement reference clock is not within the allowable range, an interrupt request is

generated.

See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual.

Interrupt Controller Unit (ICU)

Key Interrupt Function (KINT)

Low power modes

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt

Controller Unit (ICU) in User’s Manual.

A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting

a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function

(KINT) in User’s Manual.

Power consumption can be reduced in multiple ways, such as by setting clock dividers,

controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power

control mode in normal operation, and transitioning to low power modes. See section 11, Low

Power Modes in User’s Manual.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery-powered

area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See

section 12, Battery Backup Function in User’s Manual.

Register write protection

The register write protection function protects important registers from being overwritten

because of software errors. See section 13, Register Write Protection in User’s Manual.

Memory Protection Unit (MPU)

Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided

for memory protection. See section 16, Memory Protection Unit (MPU) in User’s Manual.

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1. Overview

Table 1.3

Feature

System (2 of 2)

Functional description

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow.

A refresh-permitted period can be set to refresh the counter and be used as the condition for

detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in

User’s Manual.

Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. It can be used to reset the MCU or to

generate a non-maskable interrupt or interrupt for a timer underflow. Because the timer

operates with an independent, dedicated clock source, it is particularly useful in returning the

MCU to a known state as a fail safe mechanism when the system runs out of control. The

IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the

count value in the registers. See section 28, Independent Watchdog Timer (IWDT) in User’s

Manual.

Table 1.4

Feature

Event link

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 19, Event Link Controller (ELC)

in User’s Manual.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request. See section 18, Data Transfer Controller (DTC) in User’s Manual.

DMA Controller (DMAC)

An 8-channel DMA Controller (DMAC) module is provided for transferring data without the

CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the

transfer source address to the transfer destination address. See section 17, DMA Controller

(DMAC) in User’s Manual.

Table 1.6

External bus interface

Feature

Functional description

External buses

 CS area (EXBIU): Connected to the external devices (external memory interface)

 SDRAM area (EXBIU): Connected to the SDRAM (external memory interface)

 QSPI area (EXBIUT2): Connected to the QSPI (external device interface).

Table 1.7

Feature

Timers (1 of 2)

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with 14 channels. PWM waveforms can be

generated by controlling the up-counter, down-counter, or the up- and down-counter. In

addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT

can also be used as a general-purpose timer. See section 23, General PWM Timer (GPT) in

User’s Manual.

Port Output Enable for GPT (POEG)

Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in

User’s Manual.

Asynchronous General-Purpose

Timer (AGT)

The Asynchronous General-Purpose Timer (AGT) is a 16-bit timer that can be used for pulse

output, external pulse width or period measurement, and counting of external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and can be accessed with the AGT register.

See section 25, Asynchronous General-Purpose Timer (AGT). in User’s Manual.

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1. Overview

Table 1.7

Feature

Timers (2 of 2)

Functional description

Realtime Clock (RTC)

The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count

mode, that are controlled by the register settings.

For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and

automatically adjusts dates for leap years.

For binary count mode, the RTC counts seconds and retains the information as a serial value.

Binary count mode can be used for calendars other than the Gregorian (Western) calendar.

See section 26, Realtime Clock (RTC) in User’s Manual.

Table 1.8

Feature

Communication interfaces (1 of 2)

Functional description

Serial Communications Interface

(SCI)

The Serial Communications Interface (SCI) is configurable to five asynchronous and

synchronous serial interfaces:

 Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter

(ACIA))

 8-bit clock synchronous interface

 Simple IIC (master-only)

 Simple SPI

 Smart card interface.

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol.

Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data

transfer speed can be configured independently using an on-chip baud rate generator.

See section 34, Serial Communications Interface (SCI) in User’s Manual.

IrDA interface

The IrDA interface sends and receives IrDA data communication waveforms in cooperation

with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 35,

IrDA Interface in User’s Manual.

I²C bus interface (IIC)

Serial Peripheral Interface (SPI)

The 3-channel I²C bus interface (IIC) conforms with and provides a subset of the NXP I²C

(Inter-Integrated Circuit) bus interface functions. See section 36, I2C Bus Interface (IIC) in

User’s Manual.

Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-

duplex synchronous serial communications with multiple processors and peripheral devices.

See section 38, Serial Peripheral Interface (SPI) in User’s Manual.

Serial Sound Interface Enhanced

(SSIE)

The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with

digital audio devices for transmitting I²S 2ch, 4ch, 6ch, 8ch, WS Continue/Monaural/TDM

audio data over a serial bus. The SSIE supports an audio clock frequency of up to 50 MHz,

and can be operated as a slave or master receiver, transmitter, or transceiver to suit various

applications. The SSIE includes 32-stage FIFO buffers in the receiver and transmitter, and

supports interrupts and DMA-driven data reception and transmission. See section 41, Serial

Sound Interface Enhanced (SSIE) in User’s Manual.

Quad Serial Peripheral Interface

(QSPI)

The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial

ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM)

that has an SPI-compatible interface. See section 39, Quad Serial Peripheral Interface (QSPI)

in User’s Manual.

Controller Area Network (CAN)

module

The Controller Area Network (CAN) module provides functionality to receive and transmit data

using a message-based protocol between multiple slaves and masters in electromagnetically-

noisy applications.

The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports

up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox

and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are

supported. See section 37, Controller Area Network (CAN) Module in User’s Manual.

USB 2.0 Full-Speed (USBFS) module The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller.

The module supports full-speed and low-speed (host controller only) transfer as defined in

Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and

supports all of the transfer types defined in the Universal Serial Bus Specification 2.0.

The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9

can be assigned any endpoint number based on the peripheral devices used for

communication or based on your system. See section 32, USB 2.0 Full-Speed Module

(USBFS) in User’s Manual.

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1. Overview

Table 1.8

Feature

Communication interfaces (2 of 2)

Functional description

USB 2.0 High-Speed (USBHS)

module

The USB 2.0 High-Speed (USBHS) module can operate as a host controller or a device

controller. As a host controller, the USBHS supports high-speed transfer, full-speed transfer,

and low-speed transfer as defined in the Universal Serial Bus Specification 2.0. As a device

controller, the USBHS supports high-speed transfer and full-speed transfer as defined in the

Universal Serial Bus Specification 2.0. The USBHS has an internal USB transceiver and

supports all of the transfer types defined in the Universal Serial Bus Specification 2.0.

The USBHS has FIFO buffers for data transfer, providing a maximum of 10 pipes. Any

endpoint number can be assigned to pipes 1 to 9, based on the peripheral devices or your

system for communication. See section 33, USB 2.0 High-Speed Module (USBHS) in User’s

Manual.

Ethernet MAC with IEEE 1588 PTP

(ETHERC)

One-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3

Media Access Control (MAC) layer protocol. An ETHERC channel provides one channel of the

MAC layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows

transmission and reception of frames compliant with the Ethernet and IEEE802.3 standards.

The ETHERC is connected to the Ethernet DMA Controller (EDMAC) so data can be

transferred without using the CPU.

To handle timing and synchronization between devices, an on-chip Precision Time Protocol

(PTP) module for the Ethernet PTP Controller (EPTPC) applies the PTP defined in the IEEE

1588-2008 version 2.0 standard.

The EPTPC is composed of:

 Synchronization Frame Processing unit (SYNFP0)

 A Statistical Time Correction Algorithm unit (STCA).

Use the EPTPC in combination with the on-chip Ethernet MAC Controller (ETHERC) and the

DMA Controller for the PTP Ethernet Controller (PTPEDMAC). See section 29, Ethernet MAC

Controller (ETHERC) in User’s Manual.

SD/MMC Host Interface (SDHI)

The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to

connect a variety of external memory cards to the MCU. The SDHI supports both 1-bit and 4-

bit buses for connecting memory cards that support SD, SDHC, and SDXC formats. When

developing host devices that are compliant with the SD Specifications, you must comply with

the SD Host/Ancillary Product License Agreement (SD HALA).

The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51

(JEDEC Standard JESD 84-B451) device access. This interface also provides backward

compatibility and supports high-speed SDR transfer modes. See section 43, SD/MMC Host

Interface (SDHI) in User’s Manual.

Table 1.9

Feature

Analog

Functional description

12-bit A/D Converter (ADC12)

Up to two successive approximation 12-bit A/D Converters (ADC12) are provided. In unit 0, up

to 13 analog input channels are selectable. In unit 1, up to 11 analog input channels, the

temperature sensor output, and an internal reference voltage are selectable for conversion.

The A/D conversion accuracy is selectable from 12-bit, 10-bit, and 8-bit conversion, making it

possible to optimize the tradeoff between speed and resolution in generating a digital value.

See section 47, 12-Bit A/D Converter (ADC12) in User’s Manual.

12-bit D/A Converter (DAC12)

Temperature Sensor (TSN)

The 12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section

48, 12-Bit D/A Converter (DAC12) in User’s Manual.

The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for

reliable operation of the device. The sensor outputs a voltage directly proportional to the die

temperature, and the relationship between the die temperature and the output voltage is linear.

The output voltage is provided to the ADC12 for conversion and can also be used by the end

application. See section 49, Temperature Sensor (TSN) in User’s Manual.

High-Speed Analog Comparator

(ACMPHS)

The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference

voltage and provides a digital output based on the conversion result.

Both the test and reference voltages can be provided to the comparator from internal sources

such as the DAC12 output and internal reference voltage, and an external source with or

without an internal PGA.

Such flexibility is useful in applications that require go/no-go comparisons to be performed

between analog signals without necessarily requiring A/D conversion. See section 50, High-

Speed Analog Comparator (ACMPHS) in User’s Manual.

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1. Overview

Table 1.10

Feature

Human machine interfaces

Functional description

Capacitive Touch Sensing Unit

(CTSU)

The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the

touch sensor. Changes in the electrostatic capacitance are determined by software, which

enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode

surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do

not come into direct contact with the electrodes. See section 51, Capacitive Touch Sensing

Unit (CTSU) in User’s Manual.

Table 1.11

Feature

Graphics

Functional description

Graphics LCD Controller (GLCDC)

The Graphics LCD Controller (GLCDC) provides multiple functions and supports various data

formats and panels. Key GLCDC features include:

 GPX bus master function for accessing graphics data

 Superimposition of three planes (single-color background plane, graphic 1-plane, and

graphic 2-plane)

 Support for many types of 32-bit or 16-bit per pixel graphics data and 8-bit, 4-bit, or 1-bit LUT

data format

 Digital interface signal output supporting a video image size of WVGA or greater.

See section 58, Graphics LCD Controller (GLCDC) in User’s Manual.

2D Drawing Engine (DRW)

The 2D Drawing Engine (DRW) provides flexible functions that can support almost any object

geometry rather than being bound to only a few specific geometries such as lines, triangles, or

circles. The edges of every object can be independently blurred or antialiased.

Rasterization is executed at one pixel per clock on the bounding box of the object from left to

right and top to bottom. The DRW can also raster from bottom to top to optimize the

performance in certain cases. In addition, optimization methods are available to avoid

rasterization of many empty pixels of the bounding box.

The distances to the edges of the object are calculated by a set of edge equations for every

pixel of the bounding box. These edge equations can be combined to describe the entire

object.

If a pixel is inside the object, it is selected for rendering. If it is outside, it is discarded. If it is on

the edge, an alpha value can be chosen proportional to the distance of the pixel to the nearest

edge for antialiasing.

Every pixel that is selected for rendering can be textured. The resulting aRGB quadruple can

be modified by a general raster operation approach independently for each of the four

channels. The aRGB quadruples can then be blended with one of the multiple blend modes of

the DRW.

The DRW provides two inputs (texture read and framebuffer read), and one output

(framebuffer write).

The internal color format is always aRGB (8888). The color formats from the inputs are

converted to the internal format on read and a conversion back is made on write.

See section 56, 2D Drawing Engine (DRW) in User’s Manual.

JPEG codec

The JPEG incorporates a JPEG codec that conforms to the JPEG baseline compression and

decompression standard. This provides high-speed compression of image data and high-

speed decoding of JPEG data. See section 57, JPEG Codec (JPEG) in User’s Manual.

Parallel Data Capture (PDC) unit

One Parallel Data Capture (PDC) unit is provided for communicating with external I/O devices,

including image sensors, and transferring parallel data, such as an image output from the

external I/O device through the DTC or DMAC to the on-chip SRAM and external address

spaces (the CS and SDRAM areas). See section 44, Parallel Data Capture Unit (PDC) in

User’s Manual.

Table 1.12

Feature

Data processing (1 of 2)

Functional description

Cyclic Redundancy Check (CRC)

calculator

The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the

data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first

communication. Additionally, various CRC-generating polynomials are available. The snoop

function allows monitoring reads from and writes to specific addresses. This function is useful

in applications that require CRC code to be generated automatically in certain events, such as

monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See

section 40, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.

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1. Overview

Table 1.12

Feature

Data processing (2 of 2)

Functional description

Data Operation Circuit (DOC)

The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 52,

Data Operation Circuit (DOC) in User’s Manual.

Sampling Rate Converter (SRC)

The Sampling Rate Converter (SRC) converts the sampling rate of data produced by various

audio decoders, such as the WMA, MP3, and AAC. Both 16-bit stereo and monaural data are

supported. See section 42, Sampling Rate Converter (SRC) in User’s Manual.

Table 1.13

Feature

Security

Functional description

Secure Crypto Engine 7 (SCE7)

 Security algorithms:

- Symmetric algorithms: AES, 3DES, and ARC4

- Asymmetric algorithms: RSA, DSA, and ECC.

 Other support features:

- TRNG (True Random Number Generator)

- Hash-value generation: SHA1, SHA224, SHA256, GHASH, and MD5

- 128-bit unique ID.

See section 46, Secure Cryptographic Engine (SCE7) in User’s Manual.

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Page 9 of 116

RA6M3 Group

1. Overview

1.2

Block Diagram

Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the

features.

Memory

Bus

Arm Cortex-M4

System

Clocks

2 MB code flash

DSP

FPU

POR/LVD

Reset

External

CSC

MOSC/SOSC

(H/M/L) OCO

PLL/USBPLL

64 KB data flash

640 KB SRAM

MPU

NVIC

SDRAM

MPU

Mode control

8 KB Standby

SRAM

System timer

Test and DBG interface

Power control

ICU

CAC

DMA

DTC

Battery backup

Register write

protection

KINT

DMAC × 8

Timers

Communication interfaces

Human machine interfaces

Graphics

CTSU

SCI × 10

QSPI

USBHS

GPT32EH x 4

GPT32E x 4

GPT32 x 6

IrDA × 1

GLCDC

ETHERC

with IEEE 1588

IIC × 3

SDHI × 2

CAN × 2

DRW

SPI × 2

JPEG codec

PDC

AGT × 2

RTC

SSIE × 2

USBFS

WDT/IWDT

Event link

ELC

Data processing

Analog

TSN

ADC12 with

PGA × 2

CRC

SRC

DOC

DAC12

ACMPHS × 6

Security

SCE7

Figure 1.1

Block diagram

R01DS0358EJ0110 Rev.1.10

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Page 10 of 116

RA6M3 Group

1. Overview

1.3

Part Numbering

# A

R 7 F A 6 M 3 A H 2 C B G

C 0

Production identification code

Terminal material (Pb-free)

A: Sn (Tin) only

C: Others

Packaging

#A: Tray/Individual resale

#B: Tray/Full carton

#H: Tape and reel

Please check the www.renesas.com website for

detailed orderable part number.

Package type

BG: BGA 176 pins

FC: LQFP 176 pins

FB: LQFP 144 pins

FP: LQFP 100 pins

LK: LGA 145 pins

Quality Grade

Operating temperature

2: -40^°C to 85^°C

3: -40^°C to 105^°C

Code flash memory size

F: 1 MB

H: 2 MB

Feature set

Group number

Series name

RA family

Flash memory

Renesas microcontroller

Figure 1.2

Table 1.14

Part numbering scheme

Product list

Operating

Product part number

R7FA6M3AH2CBG

R7FA6M3AH3CFC

R7FA6M3AH2CLK

R7FA6M3AH3CFB

R7FA6M3AH3CFP

R7FA6M3AF2CBG

R7FA6M3AF3CFC

R7FA6M3AF2CLK

R7FA6M3AF3CFB

R7FA6M3AF3CFP

Package code

PLBG0176GE-A

PLQP0176KB-A

PTLG0145KA-A

PLQP0144KA-B

PLQP0100KB-B

PLBG0176GE-A

PLQP0176KB-A

PTLG0145KA-A

PLQP0144KA-B

PLQP0100KB-B

Code flash Data flash SRAM

2 MB 64 KB 640 KB

temperature

-40 to +85°C

-40 to +105°C

-40 to +85°C

-40 to +105°C

-40 to +85°C

-40 to +105°C

-40 to +85°C

-40 to +105°C

1 MB

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Page 11 of 116

RA6M3 Group

1. Overview

1.4

Function Comparison

Table 1.15

Functional comparison

Part numbers

R7FA6M3AH2CBG/

R7FA6M3AF2CBG

R7FA6M3AH3CFC/

R7FA6M3AF3CFC

R7FA6M3AH2CLK/

R7FA6M3AF2CLK

R7FA6M3AH3CFB/

R7FA6M3AF3CFB

R7FA6M3AH3CFP/

R7FA6M3AF3CFP

Function

Pin count

176

145

LGA

144

100

Package

BGA

LQFP

Code flash memory

Data flash memory

SRAM

2/1 MB

64 KB

640 KB

608 KB

32 KB

8 KB

Parity

ECC

Standby SRAM

System

CPU clock

120 MHz

512 B

Backup

registers

ICU

Yes

8

KINT

Event link

DMA

ELC

Yes

8

DTC

DMAC

External bus

SDRAM

BUS

16-bit bus

8-bit bus

Yes

No

4

Timers

GPT32EH

GPT32E

GPT32

AGT

4

6

2

4

6

2

4

6

2

4

6

5

2

RTC

Yes

10

WDT/IWDT

SCI

Communication

IIC

3

2

1

SPI

2

SSIE

QSPI

1

2

SDHI

CAN

2

USBFS

USBHS

ETHERC

ADC12

DAC12

ACMPHS

TSN

Yes

No

1

Analog

HMI

24

22

19

12

2

6

Yes

CTSU

13

18

Graphics GLCDC

RGB888

Yes

DRW

JPEG

PDC

CRC

DOC

SRC

Yes

Data processing

Security

Yes

SCE7

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RA6M3 Group

1. Overview

1.5

Pin Functions

Table 1.16

Pin functions (1 of 5)

Function

Signal

I/O

Description

Power supply

VCC

Input

Digital voltage supply pin. This is used as the digital power supply for the

respective modules and internal voltage regulator, and used to monitor the

voltage of the POR/LVD. Connect to the system power supply. Connect to

VSS through a 0.1-μF smoothing capacitor close to each VCC pin.

VCL0

-

Connect to VSS through a 0.1-μF smoothing capacitor close to each VCL

pin. Stabilize the internal power supply.

VCL

-

VSS

Input

Output

Input

Output

Input

Ground pin. Connect to the system power supply (0 V).

Backup power pin

VBATT

XTAL

Clock

Pins for a crystal resonator. An external clock signal can be input through the

EXTAL pin.

EXTAL

XCIN

Input/output pins for the sub-clock oscillator. Connect a crystal resonator

between XCOUT and XCIN.

XCOUT

EBCLK

SDCLK

CLKOUT

MD

Outputs the external bus clock for external devices

Outputs the SDRAM-dedicated clock

Clock output pin

Operating mode

control

Pin for setting the operating mode. The signal level on this pin must not be

changed during operation mode transition on release from the reset state.

System control

RES

Input

Reset signal input pin. The MCU enters the reset state when this signal goes

low.

CAC

CACREF

Input

Measurement reference clock input pin

Non-maskable interrupt request pin

Maskable interrupt request pins

Interrupt

NMI

IRQ0 to IRQ15

KR00 to KR07

KINT

A key interrupt can be generated by inputting a falling edge to the key

interrupt input pins

On-chip emulator

TMS

I/O

On-chip emulator or boundary scan pins

TDI

Input

Output

I/O

TCK

TDO

TCLK

This pin outputs the clock for synchronization with the trace data

Trace data output

TDATA0 to TDATA3

SWDIO

SWCLK

SWO

Serial wire debug data input/output pin

Serial wire clock pin

Input

Output

Serial wire trace output pin

External bus

interface

RD

Strobe signal indicating that reading from the external bus interface space is

in progress, active low

WR

Output

Strobe signal indicating that writing to the external bus interface space is in

progress, in 1-write strobe mode, active low

WR0 to WR1

Strobe signals indicating that either group of data bus pins (D07 to D00 or

D15 to D08) is valid in writing to the external bus interface space, in byte

strobe mode, active low

BC0 to BC1

Output

Strobe signals indicating that either group of data bus pins (D07 to D00 or

D15 to D08) is valid in access to the external bus interface space, in 1-write

strobe mode, active low

ALE

Output

Input

Address latch signal when address/data multiplexed bus is selected

WAIT

Input pin for wait request signals in access to the external space, active low

CS0 to CS7

A00 to A23

D00 to D15

Output

I/O

Select signals for CS areas, active low

Address bus

Data bus

A00/D00 to A15/D15 I/O

Address/data multiplexed bus

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RA6M3 Group

1. Overview

Table 1.16

Function

Pin functions (2 of 5)

Signal

I/O

Description

SDRAM interface CKE

SDCS

Output

I/O

SDRAM clock enable signal

SDRAM chip select signal, active low

SDRAM low address strobe signal, active low

SDRAM column address strobe signal, active low

SDRAM write enable signal, active low

SDRAM I/O data mask enable signal for DQ07 to DQ00

SDRAM I/O data mask enable signal for DQ15 to DQ08

Address bus

RAS

CAS

WE

DQM0

DQM1

A00 to A15

DQ00 to DQ15

Data bus

GPT

GTETRGA,

GTETRGB,

GTETRGC,

GTETRGD

Input

External trigger input pins

GTIOC0A to

GTIOC13A,

GTIOC0B to

GTIOC13B

I/O

Input capture, output compare, or PWM output pins

GTIU

Input

Hall sensor input pin U

GTIV

Input

Hall sensor input pin V

GTIW

Input

Hall sensor input pin W

GTOUUP

Output

Input

3-phase PWM output for BLDC motor control (positive U phase)

3-phase PWM output for BLDC motor control (negative U phase)

3-phase PWM output for BLDC motor control (positive V phase)

3-phase PWM output for BLDC motor control (negative V phase)

3-phase PWM output for BLDC motor control (positive W phase)

3-phase PWM output for BLDC motor control (negative W phase)

External event input enable signals

GTOULO

GTOVUP

GTOVLO

GTOWUP

GTOWLO

AGT

AGTEE0, AGTEE1

AGTIO0, AGTIO1

AGTO0, AGTO1

AGTOA0, AGTOA1

AGTOB0, AGTOB1

RTCOUT

I/O

External event input and pulse output pins

Pulse output pins

Output

Input

Output compare match A output pins

Output compare match B output pins

RTC

SCI

Output pin for 1-Hz or 64-Hz clock

RTCIC0 to RTCIC2

SCK0 to SCK9

RXD0 to RXD9

TXD0 to TXD9

Time capture event input pins

I/O

Input/output pins for the clock (clock synchronous mode)

Input

Input pins for received data (asynchronous mode/clock synchronous mode)

Output

Output pins for transmitted data (asynchronous mode/clock synchronous

mode)

CTS0_RTS0 to

CTS9_RTS9

I/O

Input/output pins for controlling the start of transmission and reception

(asynchronous mode/clock synchronous mode), active low

SCL0 to SCL9

SDA0 to SDA9

SCK0 to SCK9

MISO0 to MISO9

MOSI0 to MOSI9

SS0 to SS9

I/O

Input

I/O

Input/output pins for the I²C clock (simple IIC mode)

Input/output pins for the I²C data (simple IIC mode)

Input/output pins for the clock (simple SPI mode)

Input/output pins for slave transmission of data (simple SPI mode)

Input/output pins for master transmission of data (simple SPI mode)

Chip-select input pins (simple SPI mode), active low

Input/output pins for the clock

IIC

SCL0 to SCL2

SDA0 to SDA2

SSIBCK0

Input/output pins for data

SSIE

SSIE serial bit clock pins

SSIBCK1

SSILRCK0/SSIFS0

SSILRCK1/SSIFS1

SSITXD0

I/O

LR clock/frame synchronization pins

Output

Input

I/O

Serial data output pins

SSIRXD0

Serial data input pins

SSIDATA1

Serial data input/output pins

AUDIO_CLK

Input

External clock pin for audio (input oversampling clock)

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RA6M3 Group

1. Overview

Table 1.16

Pin functions (3 of 5)

Function

Signal

I/O

Description

SPI

RSPCKA, RSPCKB

MOSIA, MOSIB

MISOA, MISOB

SSLA0, SSLB0

I/O

Clock input/output pin

I/O

Input or output pins for data output from the master

Input or output pins for data output from the slave

Input or output pin for slave selection

Output pins for slave selection

I/O

SSLA1 to SSLA3,

SSLB1 to SSLB3

Output

QSPI

QSPCLK

Output

I/O

QSPI clock output pin

QSPI slave output pin

Data0 to Data3

Receive data

QSSL

QIO0 to QIO3

CRX0, CRX1

CTX0, CTX1

VCC_USB

VSS_USB

USB_DP

CAN

Input

Output

Input

I/O

Transmit data

USBFS

Power supply pins

Ground pins

D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of

the USB bus

USB_DM

I/O

D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of

the USB bus

USB_VBUS

Input

USB cable connection monitor pin. Connect this pin to VBUS of the USB

bus. The VBUS pin status (connected or disconnected) can be detected

when the USB module is operating as a function controller.

USB_EXICEN

USB_VBUSEN

Output

Input

Low-power control signal for external power supply (OTG) chip

VBUS (5 V) supply enable signal for external power supply chip

USB_OVRCURA,

USB_OVRCURB

Connect the external overcurrent detection signals to these pins. Connect

the VBUS comparator signals to these pins when the OTG power supply

chip is connected.

USB_ID

Input

Connect the MicroAB connector ID input signal to this pin during operation in

OTG mode

USBHS

VCC_USBHS

VSS1_USBHS

VSS2_USBHS

AVCC_USBHS

AVSS_USBHS

Input

Power supply pin

Ground pin

Analog power supply pin for the USBHS

Analog ground pin for the USBHS. Must be shorted to the PVSS_USBHS

PVSS_USBHS

USBHS_RREF

Input

I/O

PLL circuit ground pin for the USBHS. Must be shorted to the AVSS_USBHS

USBHS reference current source pin. Connect this pin to the AVSS_USBHS

pin through a 2.2-kΩ resistor (1%)

USBHS_DP

I/O

USB bus D+ data pin

USBHS_DM

I/O

USB bus D- data pin

USBHS_EXICEN

USBHS_ID

Output

Input

Output

Connect this pin to the OTG power supply IC

VBUS power enable signal for USB

Overcurrent pin for USB

USBHS_VBUSEN

USBHS_OVRCURA, Input

USBHS_OVRCURB

USBHS_VBUS

Input

USB cable connection monitor input pin

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RA6M3 Group

1. Overview

Table 1.16

Pin functions (4 of 5)

Function

Signal

I/O

Description

ETHERC

REF50CK0

Input

50-MHz reference clock. This pin inputs reference signal for

transmission/reception timing in RMII mode.

RMII0_CRS_DV

Input

Indicates carrier detection signals and valid receive data on RMII0_RXD1

and RMII0_RXD0 in RMII mode

RMII0_TXD0,

RMII0_TXD1

Output

Input

2-bit transmit data in RMII mode

RMII0_RXD0,

RMII0_RXD1

2-bit receive data in RMII mode

RMII0_TXD_EN

RMII0_RX_ER

ET0_CRS

Output

Input

Output pin for data transmit enable signal in RMII mode

Indicates an error occurred during reception of data in RMII mode

Carrier detection/data reception enable signal

Indicates valid receive data on ET0_ERXD3 to ET0_ERXD0

General-purpose external output pin

Input

ET0_RX_DV

ET0_EXOUT

ET0_LINKSTA

Input

Output

Input

Input link status from the PHY-LSI

ET0_ETXD0 to

ET0_ETXD3

Output

4 bits of MII transmit data

ET0_ERXD0 to

ET0_ERXD3

Input

4 bits of MII receive data

ET0_TX_EN

Output

Transmit enable signal. Functions as signal indicating that transmit data is

ready on ET0_ETXD3 to ET0_ETXD0

ET0_TX_ER

Transmit error pin. Functions as signal notifying the PHY_LSI of an error

during transmission

ET0_RX_ER

ET0_TX_CLK

Input

Receive error pin. Functions as signal to recognize an error during reception

Transmit clock pin. This pin inputs reference signal for output timing from

ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0, and ET0_TX_ER

ET0_RX_CLK

Input

Receive clock pin. This pin inputs reference signal for input timing to

ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and ET0_RX_ER

ET0_COL

ET0_WOL

ET0_MDC

ET0_MDIO

Input

Output

I/O

Input collision detection signal

Receive Magic packets

Output reference clock signal for information transfer through ET0_MDIO.

Input or output bidirectional signal for exchange of management data with

PHY-LSI

SDHI

SD0CLK, SD1CLK

SD0CMD, SD1CMD

Output

I/O

SD clock output pins

Command output pin and response input signal pins

SD and MMC data bus pins

SD0DAT0 to

SD0DAT7,

SD1DAT0 to

SD1DAT7

I/O

SD0CD, SD1CD

SD0WP, SD1WP

AVCC0

Input

SD card detection pins

SD write-protect signals

Analog power

supply

Analog voltage supply pin. This is used as the analog power supply for the

respective modules. Supply this pin with the same voltage as the VCC pin.

AVSS0

Input

Analog ground pin. This is used as the analog ground for the respective

modules. Supply this pin with the same voltage as the VSS pin.

VREFH0

Analog reference voltage supply pin for the ADC12 (unit 0). Connect this pin

to VCC when not using the ADC12 (unit 0) and sample-and-hold circuit for

AN000 to AN002.

VREFL0

VREFH

VREFL

Input

Analog reference ground pin for the ADC12. Connect this pin to VSS when

not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to

AN002

Analog reference voltage supply pin for the ADC12 (unit 1) and D/A

Converter. Connect this pin to VCC when not using the ADC12 (unit 1),

sample-and-hold circuit for AN100 to AN102, and D/A Converter.

Analog reference ground pin for the ADC12 and D/A Converter. Connect this

pin to VSS when not using the ADC12 (unit 1), sample-and-hold circuit for

AN100 to AN102, and D/A Converter.

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RA6M3 Group

1. Overview

Table 1.16

Pin functions (5 of 5)

Signal

Function

I/O

Description

ADC12

AN000 to AN007,

AN016 to AN020

Input

Input pins for the analog signals to be processed by the ADC12

AN100 to AN103,

AN105 to AN107,

AN116 to AN119

Input

ADTRG0

ADTRG1

Input

Input pins for the external trigger signals that start the A/D conversion

Differential input pins

PGAVSS000/PGAVS Input

S100

DAC12

DA0, DA1

Output

Output pins for the analog signals processed by the D/A converter

Comparator output pin

ACMPHS

VCOUT

Output

Input

-

IVREF0 to IVREF3

IVCMP0 to IVCMP2

TS00 to TS17

TSCAP

Reference voltage input pins for comparator

Analog voltage input pins for comparator

Capacitive touch detection pins (touch pins)

Secondary power supply pin for the touch driver

General-purpose input pins

CTSU

I/O ports

P000 to P007

Input

I/O

P008 to P010,

P014, P015

General-purpose input/output pins

P100 to P115

P200

I/O

General-purpose input/output pins

General-purpose input pin

Input

I/O

P201 to P214

P300 to P315

P400 to P415

General-purpose input/output pins

I/O

P500 to P508,

P511 to P513

I/O

P600 to P615

P700 to P713

P800 to P806

I/O

General-purpose input/output pins

P900, P901,

P905 to P908

PA00, PA01,

PA08 to PA10

I/O

General-purpose input/output pins

PB00, PB01

I/O

General-purpose input/output pins

Data output pins for panel

GLCDC

LCD_DATA23 to

LCD_DATA00

Output

LCD_TCON3 to

LCD_TCON0

Output

Output pins for panel timing adjustment

LCD_CLK

LCD_EXTCLK

PIXCLK

Output

Input

Panel clock output pin

Panel clock source input pin

Image transfer clock pin

PDC

Input

VSYNC

Input

Vertical synchronization signal pin

Horizontal synchronization signal pin

8-bit image data pins

HSYNC

PIXD0 to PIXD7

PCKO

Input

Output

Output pin for dot clock

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RA6M3 Group

1. Overview

1.6

Pin Assignments

Figure 1.3 to Figure 1.7 show the pin assignments.

R7FA6M3XX2CBG

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

USBHS_ PVSS_

DM USBHS

P212

/EXTAL

15

P407

P409

P411

P414

P708

XCIN

VCL0

P707

P703

P700

P405

P401

P512

P805

P000

P002

P005

15

14

13

12

11

10

9

USBHS_ AVSS_

P213

/XTAL

14 USB_DP USB_DM

VCC_

P410

P412

P408

P206

P203

VSS

P415

P413

P205

XCOUT

VSS

VBATT

PB01

P705

P706

P704

P702

P701

P404

P403

VCC

VSS

P406

P400

P513

P001

P006

AVSS0

AVCC0

VSS

P402

P511

P806

P004

P008

DP

USBHS

VSS_

USB

VCC_

USBHS_ AVCC_

13

12

11

10

9

P204

P313

P900

P214

P210

P208

P906

P310

P308

P306

P303

P301

USB

USBHS

RREF

USBHS

VSS1_

USBHS

VSS2_

USBHS

P202

P207

P314

P901

RES

P200

P312

P307

VSS

VCC

PB00

P315

P211

P209

VCC

P009

P010

VCC

P007

P003

VSS

VREFL0 VREFH0

8

P201/MD

P905

P908

P907

P311

VCC

VREFL

P015

P505

P504

P501

P804

P802

VREFH

P014

P508

P506

P502

P500

P803

8

7

6

P309

P507

P503

VCC

6

5

P305

5

P300/TCK

/SWCLK

4

P304

P111

P110/TDI

P608

VSS

VCC

P611

P613

P610

P614

PA09

VCC

PA00

VSS

P607

P604

P605

VCC

P603

P601

VSS

P105

P107

4

P108/TMS

SWDIO

3

P302

P102

P104

P800

P101

3

2

P112

P114

PA10

PA01

2

1

P109/TDO

A

P113

B

P115

C

P609

D

P612

E

P615

F

PA08

G

VCL

H

P606

J

P602

K

P600

L

P106

M

P103

N

P100

P

P801

R

1

Figure 1.3

Pin assignment for 176-pin BGA (top view)

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RA6M3 Group

1. Overview

133

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

P800

P801

P802

P803

P804

VCC

P300/TCK/SWCLK

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

P301

P302

P303

VCC

VSS

P304

P305

P306

P307

P308

P309

P310

P311

P312

P905

P906

P907

P908

P200

P201/MD

RES

P500

P501

P502

P503

P504

P505

P506

P507

P508

VCC

VSS

P015

P014

VREFL

VREFH

AVCC0

AVSS0

VREFL0

VREFH0

P010

P009

P008

P007

P006

P005

P004

P003

P002

P001

P000

VSS

R7FA6M3XX3CFC

P208

P209

P210

P211

P214

VCC

VSS

P901

P900

P315

P314

P313

P202

P203

P204

P205

P206

P207

VCC_USB

USB_DP

USB_DM

VSS_USB

VCC

P806

P805

P513

P512

P511

Figure 1.4

Pin assignment for 176-pin LQFP (top view)

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 19 of 116

RA6M3 Group

1. Overview

R7FA6M3XX2CLK

A

B

C

D

E

F

G

H

J

K

L

M

N

P212

/EXTAL

13

P407

P409

P412

P708

P711

VCC

XCIN

VCL0

P702

P405

P402

P400

13

12

11

10

9

P213

/XTAL

12 USB_DM USB_DP

P410

P207

P204

P202

P200

RES

P414

P411

P710

P415

P413

VSS

P712

P709

XCOUT

P704

VBATT

P703

P701

P403

P003

P004

P005

P007

P505

P503

P500

P106

VCC

P404

P401

P000

P006

AVSS0

AVCC0

P506

P504

P502

P104

P800

P511

P512

P002

P009

VCC

VSS

VCC_

USB

VSS_

USB

11

10

9

P705

P713

P205

P203

P214

P210

P208

P309

P307

VSS

P206

P313

P408

P700

P406

P001

P008

VSS

8

P211

VCC

VREFL0 VREFH0

8

7

P209

P310

VREFL

P015

VSS

VREFH

P014

VCC

7

6

P201/MD

P311

P312

P308

P304

P301

P111

P305

6

5

P303

NC

5

4

P306

P109/TDO

P112

P114

P115

P609

P608

P610

P612

P604

P614

VSS

P600

P603

P605

P105

P107

P601

P501

VSS

P508

VCC

4

3

VCC

3

P300/TCK

/SWCLK

2

P302

VCC

P101

P801

2

P108/TMS

/SWDIO

1

P110/TDI

B

P113

C

VSS

D

P611

E

P613

F

VCC

G

VCL

H

P602

J

VSS

K

P103

L

P102

M

P100

N

1

A

Figure 1.5

Pin assignment for 145-pin LGA (top view)

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 20 of 116

RA6M3 Group

1. Overview

109

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

P800

P300/TCK/SWCLK

110

P801

P301

P302

P303

VCC

VSS

111

VCC

112

VSS

113

P500

114

P501

115

P304

P305

P502

116

P503

117

P306

P307

P308

P309

P310

P504

118

P505

119

P506

120

P508

121

VCC

122

VSS

P311

P312

123

P015

124

P014

P200

125

P201/MD

RES

VREFL

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

VREFH

R7FA6M3XX3CFB

P208

AVCC0

AVSS0

P209

P210

VREFL0

VREFH0

P211

P214

VCC

VSS

P009

P008

P007

P006

P005

P004

P003

P002

P001

P000

P313

P202

P203

P204

P205

P206

P207

VSS

VCC

P512

VCC_USB

USB_DP

USB_DM

VSS_USB

P511

Figure 1.6

Pin assignment for 144-pin LQFP (top view)

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 21 of 116

RA6M3 Group

1. Overview

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P500

P501

P300/TCK/SWCLK

P301

P502

P302

P503

P303

P504

VCC

P508

VSS

VCC

P304

VSS

P305

P015

P306

P014

P307

VREFL

VREFH

AVCC0

AVSS0

VREFL0

VREFH0

P008

P200

P201/MD

RES

R7FA6M3XX3CFP

P208

P209

P210

P211

P007

P214

P006

P205

P005

P206

P004

P207

P003

VCC_USB

USB_DP

USB_DM

VSS_USB

P002

P001

P000

Figure 1.7

Pin assignment for 100-pin LQFP (top view)

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 22 of 116

RA6M3 Group

1. Overview

1.7

Pin Lists

Pin number

Extbus

Timers

Communication interfaces

Analog

HMI

N13

R15

1

2

N13

L11

1

2

1

2

-

IRQ0 P400

-

AGTIO1

-

GTIOC

6A

-

SCK4 SCK7 SCL0

_A

-

AUDIO ET0_W ET0_

_CLK OL WOL

ET0_M ET0_M -

DC DC

-

ADTRG

1

-

IRQ5- P401

DS

GTETRGA GTIOC

6B

CTX0 CTS4_ TXD7/ SDA0 -

RTS4/ MOSI7 _A

-

SS4

/SDA7

P14

3

M13 3

3

4

5

CACREF IRQ4- P402

DS

-

AGTIO0/

AGTIO1

-

RTC CRX0

IC0

-

RXD7/

MISO7

/SCL7

-

AUDIO ET0_M ET0_M -

_CLK DIO DIO

-

VSYNC

PIXD7

PIXD6

M12 4

M13 5

K11

L12

4

5

-

P403

P404

AGTIO0/

AGTIO1

GTIOC RTC

3A IC1

-

CTS7_ -

RTS7/

SS7

SSIBC ET0_LI ET0_LI -

K0_A NKSTA NKST

A

SD1

DAT7

_B

-

GTIOC RTC

3B

-

SSILR ET0_EX ET0_E

-

SD1

DAT6

_B

IC2

CK0/S OUT

SIFS0_

A

XOUT

P15

N14

N15

6

7

8

L13

J10

H10

K12

6

7

8

9

6

7

-

P405

P406

P700

P701

P702

P703

P704

P705

-

GTIOC

1A

-

SSITX ET0_TX RMII0_ -

SD1

DAT5

_B

-

PIXD5

PIXD4

PIXD3

PIXD2

PIXD1

PIXD0

HSYNC

PIXCLK

-

D0_A _EN

TXD_E

N_B

-

GTIOC

1B

-

SSLB3 SSIRX ET0_RX RMII0_ -

_C

SD1

DAT4

_B

-

D0_A _ER

TXD1_

B

-

GTIOC

5A

-

MISOB -

_C

ET0_ET RMII0_ -

SD1

DAT3

_B

-

XD1

TXD0_

B

M14 9

-

GTIOC

5B

-

MOSIB -

_C

ET0_ET REF50

XD0 CK0_B

-

SD1

DAT2

_B

-

L12 10 K13 10

M15 11 J11 11

L13 12 H11 12

K12 13 G11 13

-

GTIOC

6A

-

RSPC

KB_C

-

ET0_ER RMII0_ -

SD1

DAT1

_B

-

XD1

RXD0_

B

-

GTIOC

6B

-

SSLB0

_C

ET0_ER RMII0_ -

SD1

DAT0

_B

VCOUT

XD0

RXD1_

B

-

AGTO0

AGTIO0

-

CTX0

CRX0

-

SSLB1

_C

ET0_RX RMII0_ -

SD1

CLK_

B

-

_CLK

RX_E

R_B

-

SSLB2

_C

ET0_C RMII0_ -

SD1

CMD

_B

RS

CRS_

DV_B

L14 14

L15 15

-

IRQ7 P706

IRQ8 P707

RXD3/

MISO3

/SCL3

-

USB SD1

HS_ CD_

OVR

CUR

B

-

TXD3/

MOSI3

/SDA3

-

USB SD1

HS_ WP_

-

OVR

CUR

A

B

J12 16

K13 17

-

PB00 -

PB01 -

-

SCK3

-

USB

HS_

VBU

SEN

-

CTS3_ -

RTS3/

SS3

USB

HS_

VBU

S

-

K14 18 J12 14

K15 19 J13 15

8

9

VBATT

VCL0

-

J15 20 H13 16 10 XCIN

J14 21 H12 17 11 XCOUT

J13 22 F12 18 12 VSS

H14 23 G12 19 13 XTAL

IRQ2 P213

GTETRGC GTIOC

0A

TXD1/

MOSI1

/SDA1

ADTRG

1

H15 24 G13 20 14 EXTAL IRQ3 P212

-

AGTEE1 GTETRGD GTIOC

0B

-

RXD1/

MISO1

/SCL1

-

H12 25 F13 21 15 VCC

-

H13 26

G13 27

G14 28

G15 29

G12 30

F15 31

-

AVCC_U

SBHS

USBHS_

RREF

-

AVSS_U

SBHS

PVSS_U

SBHS

VSS2_U

SBHS

-

USB

HS_

DM

F14 32

-

USB

HS_

DP

-

F12 33

F13 34

-

VSS1_U

SBHS

-

VCC_US

BHS

-

G10 22

-

P713

AGTOA0 -

GTIOC

2A

TS17

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 23 of 116

RA6M3 Group

1. Overview

Pin number

Extbus

Timers

Communication interfaces

Analog

HMI

-

F11 23

E13 24

-

P712

P711

-

AGTOB0 -

GTIOC

2B

-

TS16

TS15

-

AGTEE0

-

CTS1_ -

RTS1/

SS1

ET0_TX

_CLK

-

E12 25

F10 26

-

P710

-

SCK1

-

ET0_TX

_ER

-

TS14

TS13

-

IRQ10 P709

TXD1/

MOSI1

/SDA1

-

ET0_ET

XD2

E15 35 D13 27 16 CACREF IRQ11 P708

-

RXD1/

MISO1

/SCL1

-

SSLA3 AUDIO ET0_ET

-

TS12 PCKO

TS11 PIXD5

TS10 PIXD4

TS09 PIXD3

TS08 PIX02

TS07 PIX01

TS06 PIXD0

TS05 HSYNC

_B

_CLK XD3

E14 36 E11 28 17

D15 37 D12 29 18

E13 38 E10 30 19

D14 39 C13 31 20

C15 40 D11 32 21

C14 41 C12 33 22

B15 42 B13 34 23

-

IRQ8 P415

IRQ9 P414

-

GTIOC

0A

USB_

VBUS

EN

-

SSLA2

_B

-

ET0_TX RMII0_ -

_EN

SD0

CD_

A

TXD_E

N_A

-

GTIOC

0B

-

SSLA1

_B

ET0_RX RMII0_ -

_ER

SD0

WP_

A

TXD1_

A

-

P413

P412

GTOUUP

-

CTS0_

RTS0/

SS0

SSLA0

_B

ET0_ET RMII0_ -

XD1

SD0

CLK_

A

TXD0_

A

AGTEE1 GTOULO

SCK0

RSPC

KA_B

ET0_ET REF50

XD0 CK0_A

-

SD0

CMD

_A

IRQ4 P411

IRQ5 P410

IRQ6 P409

AGTOA1 GTOVUP GTIOC

9A

TXD0/ CTS3_ -

MOSI0 RTS3/

/SDA0 SS3

MOSIA -

_B

ET0_ER RMII0_ -

XD1

SD0

DAT0

_A

RXD0_

A

AGTOB1 GTOVLO GTIOC

9B

RXD0/ SCK3

MISO0

/SCL0

-

MISOA -

_B

ET0_ER RMII0_ -

XD0

SD0

DAT1

_A

RXD1_

A

-

GTOWUP GTIOC

10A

USB_

EXIC

EN

-

TXD3/

MOSI3

/SDA3

-

ET0_RX RMII0_ USB

_CLK RX_E HS_

-

R_A

EXIC

EN

D13 43 D10 35 24

A15 44 A13 36 25

-

IRQ7 P408

-

GTOWLO GTIOC

10B

-

USB_

ID

-

RXD3/ SCL0

MISO3 _B

/SCL3

-

ET0_C RMII0_ USB

RS CRS_ HS_I

-

TS04 PIXCLK

DV_A

D

-

P407

AGTIO0

-

RTC USB_ CTS4_ -

OUT VBUS RTS4/

SS4

SDA0 SSLB3

_B

ET0_EX ET0_E

-

ADTRG

0

TS03

-

_A

OUT

XOUT

C13 45 B11 37 26 VSS_US

B

-

B14 46 A12 38 27

-

USB_

DM

A14 47 B12 39 28

-

USB_

DP

B13 48 A11 40 29 VCC_US

B

-

C12 49 C11 41 30

-

P207 A17

-

SSLB2

_A/QS

SL

TS02 LCD_DATA

23_B

D12 50 B10 42 31

-

IRQ0- P206 WAIT

DS

-

GTIU

-

USB_ RXD4/

VBUS MISO4

-

SDA1 SSLB1 SSIDA ET0_LI ET0_LI -

SD0

DAT2

_A

-

TS01

-

_A

TA1_A NKSTA NKST

A

EN

/SCL4

E12 51 A10 43 32 CLKOUT IRQ1- P205 A16

DS

AGTO1 GTIV

AGTIO1 GTIW

GTIOC

4A

USB_ TXD4/ CTS9_ SCL1 SSLB0 SSILR ET0_W ET0_

-

SD0

DAT3

_A

TSCA

P

OVR MOSI4 RTS9/ _A

CUR /SDA4 SS9

A-DS

_A

CK1/S OL

SIFS1_

A

WOL

A13 52 C10 44

-

CACREF -

P204 A18

-

GTIOC

4B

-

USB_ SCK4 SCK9 SCL0 RSPC SSIBC ET0_RX -

SD0

DAT4

_A

-

TS00

-

OVR

CUR

B-DS

_B

KB_A K1_A _DV

D11 53 A9 45

B12 54 C9 46

A12 55 B9 47

-

IRQ2- P203 A19

DS

-

GTIOC

5A

-

CTX0 CTS2_ TXD9/

RTS2/ MOSI9

-

MOSIB -

_A

ET0_C

OL

-

SD0

DAT5

_A

-

TSCA

P

SS2

/SDA9

IRQ3- P202 WR1/ -

GTIOC

5B

CRX0 SCK2 RXD9/

MISO9

MISOB

_A

ET0_ER -

XD2

SD0

DAT6

_A

-

LCD_TCO

N3_B

DS

BC1

/SCL9

-

P313 A20

-

ET0_ER -

XD3

SD0

DAT7

_A

LCD_TCO

N2_B

C11 56

B11 57

A11 58

C10 59

-

P314 A21

P315 A22

P900 A23

-

ADTRG

0

-

LCD_TCO

N1_B

-

RXD4

TXD4

SCK4

-

LCD_TCO

N0_B

-

LCD_CLK_

B

P901

-

AGTIO1

LCD_DATA

15_B

D10 60 D9 48

D9 61 D8 49

-

VSS

VCC

-

A10 62 A8 50 33 TRCLK

P214

GTIU

QSPC

LK

ET0_M ET0_M -

DC DC

SD0

CLK_

B

LCD_DATA

22_B

B10 63 B8 51 34 TRDATA

0

-

P211

P210

P209

-

GTIV

-

QIO0

QIO1

QIO2

-

ET0_M ET0_M -

DIO DIO

SD0

CMD

_B

-

LCD_DATA

21_B

A9 64 A7 52 35 TRDATA

1

GTIW

ET0_W ET0_

OL WOL

-

SD0

CD_

B

LCD_DATA

20_B

B9 65 B7 53 36 TRDATA

2

GTOVUP

ET0_EX ET0_E

OUT XOUT

SD0

WP_

B

LCD_DATA

19_B

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 24 of 116

RA6M3 Group

1. Overview

Pin number

Extbus

Timers

Communication interfaces

Analog

HMI

A8 66 A6 54 37 TRDATA

3

-

P208

-

GTOVLO

-

QIO3

-

ET0_LI ET0_LI -

NKSTA NKST

A

SD0

DAT0

_B

-

LCD_DATA

18_B

C9 67 C7 55 38 RES

B8 68 B6 56 39 MD

-

P201

P200

C8 69 C8 57 40

-

NMI

-

D8 70

D7 71

A7 72

B7 73

-

P908 CS7

P907 CS6

P906 CS5

P905 CS4

GTIOC

2A

LCD_DATA

14_B

-

GTIOC

2B

-

LCD_DATA

13_B

GTIOC

3A

LCD_DATA

12_B

GTIOC

3B

LCD_DATA

11_B

C7 74 C6 58

P312 CS3 CAS AGTOA1 -

P311 CS2 RAS AGTOB1 -

-

CTS3_ -

RTS3/

SS3

-

D6 75 B5 59

A6 76 D7 60

B6 77 A5 61

A5 78 C5 62

-

SCK3

-

LCD_DATA

23_A

P310 A15 A15

P309 A14 A14

P308 A13 A13

P307 A12 A12

P306 A11 A11

AGTEE1

-

TXD3

QIO3

QIO2

QIO1

QIO0

QSSL

LCD_DATA

22_A

-

RXD3

LCD_DATA

21_A

-

LCD_DATA

20_A

C6 79 A4 63 41

A4 80 B4 64 42

B5 81 D6 65 43

GTOUUP

GTOULO

GTOWUP

CTS6

SCK6

LCD_DATA

19_A

LCD_DATA

18_A

IRQ8 P305 A10 A10

IRQ9 P304 A09 A09

TXD6/

MOSI6

/SDA6

QSPC

LK

LCD_DATA

17_A

B4 82 C4 66 44

-

GTOWLO GTIOC

7A

-

RXD6/

MISO6

/SCL6

-

LCD_DATA

16_A

C5 83 A3 67 45 VSS

D5 84 B3 68 46 VCC

-

A3 85 D5 69 47

-

P303 A08 A08

GTIOC

7B

LCD_DATA

15_A

B3 86 A2 70 48

-

IRQ5 P302 A07 A07

IRQ6 P301 A06 A06

-

GTOUUP GTIOC

4A

-

TXD2/

MOSI2

/SDA2

-

SSLB3

_B

-

LCD_DATA

14_A

A2 87 C3 71 49

-

AGTIO0 GTOULO GTIOC

4B

RXD2/ CTS9_ -

MISO2 RTS9/

/SCL2 SS9

SSLB2

_B

LCD_DATA

13_A

C4 88 B2 72 50 TCK/SW

CLK

-

P300

P108

-

GTOUUP GTIOC

0A_A

-

SSLB1

_B

-

C3 89 A1 73 51 TMS/SW

DIO

GTOULO GTIOC

0B_A

-

CTS9_ -

RTS9/

SS9

SSLB0

_B

A1 90 D4 74 52 CLKOUT

-

P109

-

GTOVUP GTIOC

1A_A

-

CTX1

-

TXD9/

MOSI9

/SDA9

-

MOSIB -

_B

-

/TDO/S

WO

D3 91 B1 75 53 TDI

IRQ3 P110

GTOVLO GTIOC

1B_A

CRX1 CTS2_ RXD9/

RTS2/ MISO9

-

MISOB -

_B

VCOUT

SS2

/SCL9

D4 92 C2 76 54

B2 93 D3 77 55

-

IRQ4 P111 A05 A05

-

GTIOC

3A_A

-

SCK2 SCK9

-

RSPC

KB_B

-

LCD_DATA

12_A

-

P112 A04 A04

P113 A03 A03

GTIOC

3B_A

TXD2/ SCK1

MOSI2

/SDA2

SSLB0 SSIBC

LCD_DATA

11_A

_B

-

K0_B

B1 94 C1 78 56

-

GTIOC

2A

-

RXD2/

MISO2

/SCL2

-

SSILR

CK0/S

SIFS0_

B

-

LCD_DATA

10_A

C2 95 E4 79 57

C1 96 E3 80 58

-

P114 A02 A02

P115 A01 A01

-

GTIOC

2B

-

SSIRX

D0_B

-

LCD_DATA

09_A

GTIOC

4A

SSITX

D0_B

LCD_DATA

08_A

E3 97 D2 81

E4 98 D1 82

-

VCC

VSS

-

D2 99 F4 83 59

D1 100 E2 84 60

F3 101 F3 85 61

P608 A00/ A00/D

BC0 QM1

GTIOC

4B

LCD_DATA

07_A

-

P609 CS1 CKE

-

GTIOC

5A

-

CTX1

CRX1

-

LCD_DATA

06_A

P610 CS0 WE

GTIOC

5B

LCD_DATA

05_A

E2 102 E1 86

E1 103 F2 87

F4 104 F1 88

F2 105 G3 89

-

CLKOUT

/CACRE

F

P611

-

SDCS

-

CTS7_ -

RTS7/

SS7

-

P612 D08[ DQ08

-

SCK7

TXD7

RXD7

-

A08/

D08]

P613 D09[ DQ09

A09/

D09]

P614 D10[ DQ10

A10/

D10]

F1 106

G1 107

-

P615

-

LCD_DATA

10_B

PA08 -

LCD_DATA

09_B

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 25 of 116

RA6M3 Group

1. Overview

Pin number

Extbus

Timers

Communication interfaces

Analog

HMI

G4 108

G2 109

-

PA09 -

PA10 -

-

LCD_DATA

08_B

LCD_DATA

07_B

G3 110 G1 90 62 VCC

H3 111 G2 91 63 VSS

H1 112 H1 92 64 VCL

-

H2 113

H4 114

J4 115

J1 116

-

PA01 -

SCK8

LCD_DATA

06_B

-

PA00 -

-

TXD8

RXD8

-

LCD_DATA

05_B

P607

P606

-

LCD_DATA

04_B

RTC

OUT

CTS8_ -

RTS8/

SS8

LCD_DATA

03_B

J2 117 H2 93

J3 118 G4 94

K3 119 H3 95

-

P605 D11[ DQ11

-

GTIOC

8A

-

A11/

D11]

P604 D12[ DQ12

GTIOC

8B

-

A12/

D12]

P603 D13[ DQ13

GTIOC

7A

CTS9_ -

RTS9/

SS9

A13/

D13]

K1 120 J1 96 65

K2 121 J2 97 66

-

P602 EBC SDCL

-

GTIOC

7B

-

TXD9

RXD9

SCK9

-

LCD_DATA

04_A

LK

K

P601 WR/ DQM0

WR0

GTIOC

6A

LCD_DATA

03_A

L1 122 H4 98 67 CLKOUT

P600 RD

-

GTIOC

6B

LCD_DATA

02_A

/CACRE

F

K4 123 K2 99

-

VCC

VSS

-

L4 124 K1 100 -

L2 125 J3 101 68

KR07 P107 D07[ DQ07 AGTOA0 -

GTIOC

8A

CTS8_ -

RTS8/

SS8

LCD_DATA

01_A

A07/

D07]

M1 126 K3 102 69

L3 127 J4 103 70

M2 128 L3 104 71

N1 129 L1 105 72

M3 130 M1 106 73

N2 131 M2 107 74

P1 132 N1 108 75

N3 133 L2 109 -

-

KR06 P106 D06[ DQ06 AGTOB0 -

GTIOC

8B

-

SCK8

-

SSLA3

_A

-

LCD_DATA

00_A

A06/

D06]

IRQ0/ P105 D05[ DQ05

-

GTETRGA GTIOC

1A

TXD8/

MOSI8

/SDA8

SSLA2

_A

LCD_TCO

N3_A

KR05

A05/

D05]

IRQ1/ P104 D04[ DQ04

GTETRGB GTIOC

1B

RXD8/

MISO8

/SCL8

SSLA1

_A

LCD_TCO

N2_A

KR04

A04/

D04]

KR03 P103 D03[ DQ03

GTOWUP GTIOC

2A_A

CTX0 CTS0_ -

RTS0/

SSLA0

_A

LCD_TCO

N1_A

A03/

D03]

SS0

KR02 P102 D02[ DQ02 AGTO0 GTOWLO GTIOC

CRX0 SCK0

-

RSPC

KA_A

ADTRG

0

LCD_TCO

N0_A

A02/

D02]

2B_A

IRQ1/ P101 D01[ DQ01 AGTEE0 GTETRGB GTIOC

-

TXD0/ CTS1_ SDA1 MOSIA -

MOSI0 RTS1/ _B

/SDA0 SS1

-

LCD_CLK_

A

KR01

A01/

D01]

5A

_A

IRQ2/ P100 D00[ DQ00 AGTIO0 GTETRGA GTIOC

RXD0/ SCK1 SCL1 MISOA -

MISO0

/SCL0

LCD_EXT

CLK_A

KR00

A00/

D00]

5B

_B

_A

-

P800 D14[ DQ14

-

A14/

D14]

R1 134 N2 110

-

P801 D15[ DQ15

-

SD1

DAT4

_A

A15/

D15]

P2 135

R2 136

P3 137

-

P802

P803

P804

-

SD1

DAT5

_A

LCD_DATA

02_B

SD1

DAT6

_A

LCD_DATA

01_B

SD1

DAT7

_A

LCD_DATA

00_B

N4 138 N3 111

M4 139 M3 112

-

VCC

VSS

-

R3 140 K4 113 76

P500

AGTOA0 GTIU

GTIOC

11A

USB_

VBUS

EN

QSPC

LK

SD1 AN016 IVREF0

CLK_

A

P4 141 M4 114 77

-

IRQ11 P501

IRQ12 P502

-

AGTOB0 GTIV

GTIOC

11B

-

USB_

OVR

CUR

A

-

TXD5/

MOSI5

/SDA5

-

QSSL

-

SD1 AN116 IVREF1

CMD

_A

-

R4 142 L4 115 78

-

GTIW

GTIOC

12A

USB_

OVR

CUR

B

RXD5/

MISO5

/SCL5

QIO0

SD1 AN017 IVCMP0 -

DAT0

_A

N5 143 K5 116 79

P5 144 L5 117 80

-

P503

-

GTETRGC GTIOC

12B

-

USB_ CTS6_ SCK5

EXIC RTS6/

EN

QIO1

QIO2

QIO3

-

SD1 AN117

DAT1

_A

-

SS6

P504 ALE

GTETRGD GTIOC

13A

USB_ SCK6 CTS5_ -

SD1 AN018

DAT2

_A

ID

-

RTS5/

SS5

P6 145 K6 118

-

IRQ14 P505

-

GTIOC

13B

RXD6/

MISO6

/SCL6

-

SD1 AN118

DAT3

_A

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Dec 25, 2020

Page 26 of 116

RA6M3 Group

1. Overview

Pin number

Extbus

Timers

Communication interfaces

Analog

HMI

R5 146 L6 119

-

IRQ15 P506

-

TXD6/

MOSI6

/SDA6

-

SD1 AN019

CD_

A

-

N6 147

-

P507

-

CTS5_ -

RTS5/

SS5

SD1 AN119

WP_

A

R6 148 N4 120 81

-

P508

-

SCK6 SCK5

-

AN020

-

M7 149 N5 121 82 VCC

N7 150 M5 122 83 VSS

-

P7 151 M6 123 84

-

IRQ13 P015

AN006/ DA1/

AN106 IVCMP1

R7 152 N6 124 85

-

P014

-

AN005/ DA0/

-

AN105 IVREF3

P8 153 M7 125 86 VREFL

R8 154 N7 126 87 VREFH

N8 155 L7 127 88 AVCC0

N9 156 L8 128 89 AVSS0

P9 157 M8 129 90 VREFL0

R9 158 N8 130 91 VREFH0

-

M8 159

-

IRQ14 P010

-DS

AN103

M9 160 M9 131 -

P10 161 N9 132 92

M6 162 K7 133 93

IRQ13 P009

-DS

-

AN004

AN003

-

IRQ12 P008

-DS

-

P007

PGAVS

S100/A

N107

N10 163 L9 134 94

R10 164 K8 135 95

P11 165 K9 136 96

M5 166 K10 137 97

-

IRQ11- P006

DS

-

AN102 IVCMP2 -

AN101 IVCMP2 -

AN100 IVCMP2 -

-

IRQ10 P005

-DS

IRQ9- P004

DS

-

P003

PGAVS

S000/A

N007

-

R11 167 M10 138 98

N11 168 N10 139 99

-

IRQ8- P002

DS

-

AN002 IVCMP2 -

AN001 IVCMP2 -

AN000 IVCMP2 -

-

IRQ7- P001

DS

R12 169 L10 140 100 -

IRQ6- P000

DS

M10 170 N11 141 -

M11 171 N12 142 -

VSS

-

VCC

-

P12 172

R13 173

N12 174

-

P806

LCD_EXT

CLK_B

-

P805

P513

-

TXD5

RXD5

-

LCD_DATA

17_B

-

LCD_DATA

16_B

R14 175 M11 143 -

P13 176 M12 144 -

IRQ14 P512

IRQ15 P511

GTIOC

0A

CTX1 TXD4/

MOSI4

SCL2

VSYNC

/SDA4

-

GTIOC

0B

-

CRX1 RXD4/

MISO4

-

SDA2 -

-

PCKO

/SCL4

Note:

Some pin names have the added suffix of _A, _B, and _C. When assigning the GPT, IIC, SPI, SSIE, ETHERC (RMII), SDHI,

and GLCDC functionality, select the functional pins with the same suffix.

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Page 27 of 116

RA6M3 Group

2. Electrical Characteristics

2.

Electrical Characteristics

Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:

VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS =

AVCC_USBHS = 3.0 to 3.6 V, VSS = AVSS0 = VREFL0/VREFL = VSS_USB = VSS1_USBHS = VSS2_USBHS =

PVSS_USBHS = AVSS_USBHS = 0 V, Ta = Topr.

Figure 2.1 shows the timing conditions.

For example P100

C

V_OH= VCC × 0.7, V_OL= VCC × 0.3

V_IH= VCC × 0.7, V_IL= VCC × 0.3

Load capacitance C = 30pF

Figure 2.1

Input or output timing measurement conditions

The measurement conditions of timing specification in each peripherals are recommended for the best peripheral

operation, however make sure to adjust driving abilities of each pins to meet your conditions.

2.1

Absolute Maximum Ratings

Table 2.1

Absolute maximum ratings

Parameter

Symbol

Value

Unit

V

Power supply voltage

VCC, VCC_USB *²

VBATT

-0.3 to +4.0

VBATT power supply voltage

Input voltage (except for 5V-tolerant ports*¹)

Input voltage (5V-tolerant ports*¹)

Reference power supply voltage

Analog power supply voltage

USBHS power supply voltage

USBHS analog power supply voltage

Analog input voltage (except for P000 to P007)

-0.3 to +4.0

V

V_in

-0.3 to VCC + 0.3

-0.3 to + VCC + 4.0 (max 5.8)

-0.3 to AVCC0 + 0.3

-0.3 to +4.0

V

V_in

V

VREFH/VREFH0

AVCC0 *²

VCC_USBHS

AVCC_USBHS

V_AN

V

-0.3 to +4.0

V

-0.3 to +4.0

V

-0.3 to AVCC0 + 0.3

V

Analog input voltage (P000 to P007) when PGA

differential input is disabled

V_AN

V

Analog input voltage (P000 to P002, P004 to P006)

when PGA differential input is enabled

V_AN

T_opr

T_stg

-1.3 to AVCC0 + 0.3

-0.8 to AVCC0 + 0.3

V

Analog input voltage (P003, P007) when PGA

differential input is enabled

V

Operating temperature*^3,*^4,*⁵

-40 to +85

-40 to +105

°C

Storage temperature

-55 to +125

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Dec 25, 2020

Page 28 of 116

RA6M3 Group

2. Electrical Characteristics

Caution:

Permanent damage to the MCU might result if absolute maximum ratings are exceeded.

Note 1. Ports P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, and PB01 are 5V-tolerant.

Note 2. Connect AVCC0 and VCC_USB to VCC.

Note 3. See section 2.2.1, T_j/T_aDefinition.

Note 4. Contact a Renesas Electronics sales office for information on derating operation when T_a= +85°C to +105°C. Derating is the

systematic reduction of load for improved reliability.

Note 5. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part

Numbering.

Table 2.2

Recommended operating conditions

Parameter

Symbol

Value

Min

Typ

Max

3.6

-

Unit

V

Power supply voltages

VCC

When USB/SDRAM is not used 2.7

-

When USB/SDRAM is used

3.0

-

V

VSS

-

0

V

USB power supply voltages

VCC_USB,

VCC

-

V

VCC_USBHS

VSS_USB,

-

0

-

V

AVSS_USBHS,

PVSS_USBHS,

VSS1_USBHS,

VSS2_USBHS

VBATT power supply voltage

Analog power supply voltages

VBATT

AVCC0*¹

AVSS0

1.8

-

3.6

V

-

VCC

0

-

Note 1. Connect AVCC0 to VCC. When neither the A/D converter nor the D/A converter nor the comparator is in use, do not leave the

AVCC0, VREFH/VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC,

and the AVSS0 and VREFL/VREFL0 pins to VSS, respectively.

2.2

DC Characteristics

T /T Definition

2.2.1

j

a

Table 2.3

DC characteristics

Conditions: Products with operating temperature (T_a) -40 to +105°C

Parameter

Symbol

Typ

Max

125

Unit

Test conditions

Permissible junction temperature

T_j

-

°C

High-speed mode

Low-speed mode

Subosc-speed mode

105*¹

Note:

Make sure that T_j= T_a+ θja × total power consumption (W), where total power consumption = (VCC - V_OH) × ΣI_OH+ V_OL× ΣI_OL

+ I_CCmax × VCC.

Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part

Numbering. If the part number shows the operation temperature to 85°C, then Tj max is 105°C, otherwise, 125°C.

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Dec 25, 2020

Page 29 of 116

RA6M3 Group

2. Electrical Characteristics

2.2.2

I/O V , V

IH

IL

Table 2.4

Parameter

I/O V_IH, V_IL

Symbol Min

Typ Max

Unit

Input voltage

(except for

Schmitt trigger pin

input pins)

Peripheral EXTAL(external clock input), WAIT, SPI (except V_IH

VCC × 0.8

-

V

function

RSPCK)

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

-

VCC × 0.2

D00 to D15,

DQ00 to DQ15

VCC × 0.7

-

VCC × 0.3

ETHERC

2.3

-

VCC × 0.2

IIC (SMBus)*¹

IIC (SMBus)*²

2.1

-

0.8

2.1

VCC + 3.6

(max 5.8)

V_IL

-

0.8

Schmitt trigger

input voltage

IIC (except for SMBus)*¹

IIC (except for SMBus)*²

V_IH

V_IL

VCC × 0.7

-

VCC × 0.3

-

ΔV_T

V_IH

VCC × 0.05

VCC × 0.7

VCC + 3.6

(max 5.8)

V_IL

-

VCC × 0.3

-

ΔV_T

V_IH

VCC × 0.05

VCC × 0.8

7

5V-tolerant ports*^3,

*

VCC + 3.6

(max 5.8)

V_IL

-

VCC × 0.2

ΔV_T

V_IH

V_IL

VCC × 0.05

V_BATT× 0.8

-

RTCIC0, When using the

RTCIC1, Battery Backup

RTCIC2 Function

When VBATT

power supply is

selected

V_BATT+ 0.3

V_BATT× 0.2

-

ΔV_T

V_IH

V_BATT× 0.05

VCC × 0.8

When VCC

power supply is

selected

Higher

voltage either

VCC + 0.3 V

or

V_BATT+ 0.3 V

V_IL

-

VCC × 0.2

ΔV_T

VCC × 0.05

VCC × 0.8

-

When not using the Battery Backup V_IH

VCC + 0.3

Function

V_IL

VCC × 0.2

ΔV_T

VCC × 0.05

VCC × 0.8

-

Other input pins*⁴

V_IH

V_IL

-

VCC × 0.2

-

ΔV_T

V_IH

VCC × 0.05

VCC × 0.8

7

Ports

5V-tolerant ports*^5,

Other input pins*⁶

*

VCC + 3.6

(max 5.8)

V_IL

V_IH

V_IL

-

VCC × 0.2

-

VCC × 0.8

-

VCC × 0.2

Note 1. SCL0_B (P204), SCL1_B, SDA1_B (total 3 pins).

Note 2. SCL0_A, SDA0_A, SCL0_B (P408), SDA0_B, SCL1_A, SDA1_A, SCL2, SDA2 (total 8 pins).

Note 3. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, PB01

(total 23 pins).

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RA6M3 Group

2. Electrical Characteristics

Note 4. All input pins except for the peripheral function pins already described in the table.

Note 5. P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, PB01 (total 22 pins).

Note 6. All input pins except for the ports already described in the table.

Note 7. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown might

occur because the 5 V-tolerant ports are electrically controlled to not violate the breakdown voltage.

2.2.3

I/O I , I

OH OL

Table 2.5

Parameter

I/O I_OH, I_OL

Symbol

Min

Typ

Max

-2.0

2.0

-4.0

4.0

-2.0

2.0

-4.0

4.0

-20

20

Unit

mA

Permissible output current

(average value per pin)

Ports P008 to P010, P201

Ports P014, P015

-

I

-

--

-

OH

I

OL

I

OH

I

OL

Ports P205, P206, P407 to P415, Low drive*¹

P602, P708 to P713, PB01 (total

19 pins)

I

OH

I

OL

Middle drive*²

I

OH

I

OL

High drive*³

I

OH

I

OL

Other output pins*⁴

Low drive*¹

I

-2.0

2.0

-4.0

4.0

-16

16

OH

I

OL

Middle drive*²

I

OH

I

OL

High drive*³

I

OH

I

OL

Permissible output current

(max value per pin)

Ports P008 to P010, P201

Ports P014, P015

-

I

-4.0

4.0

-8.0

8.0

-4.0

4.0

-8.0

8.0

-40

40

OH

I

OL

I

OH

I

OL

Ports P205, P206, P407 to P415, Low drive*¹

P602, P708 to P713, PB01

(total 19 pins)

I

OH

I

OL

Middle drive*²

High drive*³

I

OH

I

OL

I

OH

I

OL

Other output pins*⁴

Low drive*¹

Middle drive*²

High drive*³

I

-4.0

4.0

-8.0

8.0

-32

32

OH

I

OL

I

OH

I

OL

I

OH

I

OL

Permissible output current

(max value total pins)

Maximum of all output pins

ΣI

-80

80

OH (max)

ΣI

OL (max)

Caution:

To protect the reliability of the MCU, the output current values should not exceed the values in this

table. The average output current indicates the average value of current measured during 100 μs.

Note 1. This is the value when low driving ability is selected in the port drive capability bit in the PmnPFS register. The selected driving

ability is retained in Deep Software Standby mode.

Note 2. This is the value when middle driving ability is selected in the port drive capability bit in the PmnPFS register. The selected

driving ability is retained in Deep Software Standby mode.

Note 3. This is the value when high driving ability is selected in the port drive capability bit in the PmnPFS register. The selected driving

ability is retained in Deep Software Standby mode.

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Page 31 of 116

RA6M3 Group

2. Electrical Characteristics

Note 4. Except for P000 to P007, P200, which are input ports.

2.2.4

I/O V , V , and Other Characteristics

OH OL

Table 2.6

I/O V_OH, V_OL, and other characteristics

Parameter

Symbol

Min

Typ

Max

0.4

Unit

Test conditions

Output voltage

IIC

V

-

V

I

= 3.0 mA

= 6.0 mA

= 15.0 mA

OL

V

0.6

IIC*¹

0.4

(ICFER.FMPE = 1)

V

-

0.4

-

I = 20.0 mA

OL

(ICFER.FMPE = 1)

ETHERC

V

VCC - 0.5

-

I

= -1.0 mA

= 1.0 mA

= -20 mA

OH

OL

OH

OL

OH

0.4

-

Ports P205, P206, P407 to P415,

P602, P708 to P713, PB01 (total 19

pins)*²

VCC - 1.0

VCC = 3.3 V

V

-

1.0

I

= 20 mA

OL

VCC = 3.3 V

Other output pins

RES

V

|I

VCC - 0.5

-

I

= -1.0 mA

= 1.0 mA

OH

OL

-

0.5

5.0

I

OL

|

Input leakage current

μA

V

= 0 V

= 5.5 V

in

Ports P000 to P002, P004 to P006,

P200

-

1.0

45.0

1.0

5.0

1.0

-10

16

V

= 0 V

= VCC

in

Ports P003, P007 Before

-

V

= 0 V

= VCC

in

3

initialization*

After

initialization*

-

V

= 0 V

= VCC

in

4

Three-state leakage

current (off state)

5V-tolerant ports

|I

I

|

-

μA

V

= 0 V

= 5.5 V

TSI

in

Other ports (except for ports P000

to P007, P200)

-

V

= 0 V

= VCC

in

Input pull-up MOS current

Input capacitance

Ports P0 to PB (except for ports

P000 to P007)

-300

-

μA

VCC = 2.7 to 3.6 V

= 0 V

p

V

in

USB_DP, USB_DM, and ports

P003, P007, P014, P015, P400,

P401, P511, P512

C

pF

Vbias = 0V

Vamp = 20mV

f = 1 MHz

in

T

= 25°C

a

Other input pins

-

8

Note 1. SCL0_A, SDA0_A (total 2 pins).

Note 2. This is the value when high driving ability is selected in the port drive capability bit in the PmnPFS register.

The selected driving ability is retained in Deep Software Standby mode.

Note 3. P0nPFS.ASEL (n = 3 or 7) = 1.

Note 4. P0nPFS.ASEL (n = 3 or 7) = 0.

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RA6M3 Group

2. Electrical Characteristics

2.2.5

Operating and Standby Current

Table 2.7

Operating and standby current (1 of 2)

Parameter

Symbol

Min

Typ

-

Max

Unit

Test conditions

3

Supply

Maximum*²

I

CC

*

-

mA

ICLK = 120 MHz

PCLKA = 120 MHz*

PCLKB = 60 MHz

PCLKC = 60 MHz

PCLKD = 120 MHz

FCLK = 60 MHz

137*²

current*¹

7

CoreMark®*⁵

21

34

-

Normal mode

All peripheral clocks enabled,

while (1) code executing from

flash*⁴

BCLK = 120 MHz

All peripheral clocks disabled,

-

14

-

while (1) code executing from

6

flash*^5,

*

6

Sleep mode*^5,

*

-

12

6

46

-

Increase during BGO

operation

Data flash P/E

Code flash P/E

8

-

Low-speed mode*⁵

2.4

2

-

ICLK = 1 MHz

ICLK = 32.768 kHz

Ta ≤ 85°C

Ta ≤ 105°C

Ta ≤ 85°C

Ta ≤ 105°C

Ta ≤ 85°C

Ta ≤ 105°C

Ta ≤ 85°C

Ta ≤ 105°C

-

Subosc-speed mode*⁵

Software Standby mode

-

1.8

30

13

6.3

5

18

28

79

113

33

40

28

34

-

Power supplied to Standby SRAM and USB resume

detecting unit

μA

Power not supplied to

SRAM or USB resume

detecting unit

Power-on reset circuit low-

power function disabled

Power-on reset circuit low-

power function enabled

Increase when the RTC

and AGT are operating

When the low-speed on-chip

oscillator (LOCO) is in use

When a crystal oscillator for

low clock loads is in use

-

1.0

1.5

0.9

1.3

1.1

1.8

-

When a crystal oscillator for

standard clock loads is in use

RTC operating while VCC is off (with When a crystal

the battery backup function, only the oscillator for low clock

V

= 1.8 V,

BATT

VCC = 0 V

RTC and sub-clock oscillator

operate)

loads is in use

V

= 3.3 V,

BATT

VCC = 0 V

When a crystal

oscillator for standard

clock loads is in use

V

BATT

VCC = 0 V

= 1.8 V,

V

= 3.3 V,

BATT

VCC = 0 V

Analog

power

supply

current

During 12-bit A/D conversion

AI

-

0.8

2.3

1

1.1

3.3

3

mA

µA

-

CC

During 12-bit A/D conversion with S/H amp

PGA (1ch)

ACMPHS (1unit)

100

0.1

0.6

0.9

2

150

0.2

1.1

1.6

8

Temperature sensor

mA

µA

During D/A conversion (per unit)

Without AMP output

With AMP output

Waiting for A/D, D/A conversion (all units)

ADC12, DAC12 in standby modes (all units)*

During 12-bit A/D conversion (unit 0)

Waiting for 12-bit A/D conversion (unit 0)

ADC12 in standby modes (unit 0)

8

Reference

power

supply

current

(VREFH0)

AI

70

120

0.5

μA

REFH0

0.07

μA

µA

Reference

power

supply

current

(VREFH)

During 12-bit A/D conversion (unit 1)

-

70

120

0.4

0.8

µA

mA

µA

-

REFH

During D/A conversion

(per unit)

Without AMP output

With AMP ouput

0.1

Waiting for 12-bit A/D (unit 1), D/A (all units) conversion

ADC12 unit 1 in standby modes

0.07

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RA6M3 Group

2. Electrical Characteristics

Table 2.7

Operating and standby current (2 of 2)

Parameter

Symbol

Min

Typ

3.5

Max

6.5

Unit

mA

Test conditions

USB

operating

current

Low speed

USB

I

-

VCC_USB

CCUSBLS

USBHS

10.5

13.5

VCC_USBHS =

AVCC_USBHS

(PHYSET.HSEB = 0)

USBHS

-

2.8

3.6

mA

VCC_USBHS =

AVCC_USBHS

(PHYSET.HSEB = 1)

Full speed

USB

I

-

4.0

14

10.0

22

mA

VCC_USB

CCUSBFS

USBHS

VCC_USBHS =

AVCC_USBHS

(PHYSET.HSEB = 0)

USBHS

-

6.5

13.0

mA

VCC_USBHS =

AVCC_USBHS

(PHYSET.HSEB = 1)

High speed

USBHS

I

-

50

65

mA

VCC_USBHS =

AVCC_USBHS

CCUSBHS

Standby mode (direct power down)

I

0.5

4.5

μA

VCC_USBHS =

AVCC_USBHS

CCUSBSBY

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOS transistors in the off state.

Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.

Note 3. ICC depends on f (ICLK) as follows. (ICLK:PCLKA:PCLKB:PCLKC:PCLKD:BCK:EBCLK = 2:2:1:1:2:1:1)

ICC Max. = 0.84 × f + 37 (max. operation in High-speed mode)

ICC Typ. = 0.09 × f + 3.7 (normal operation in High-speed mode)

ICC Typ. = 0.6 × f + 1.8 (Low-speed mode 1)

ICC Max. = 0.08 × f + 37 (Sleep mode).

Note 4. This does not include the BGO operation.

Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 6. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.75 MHz).

Note 7. When using ETHERC, GLCDC, DRW, and JPEG, PCLKA frequency is such that PCLKA = ICLK.

Note 8. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC120 Module Stop bit) and

MSTPCRD.MSTPD15 (ADC121 Module Stop bit) are in the module-stop state. See section 47.6.8, Available Functions and

Register Settings of AN000 to AN002, AN007, AN100 to AN102, and AN107 in User’s Manual.

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RA6M3 Group

2. Electrical Characteristics

100

10

1

-40

-20

0

20

40

60

80

100

Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.2

Temperature dependency in Software Standby mode (reference data)

1000

100

10

1

-40

-20

0

20

40

60

80

100

Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.3

Temperature dependency in Deep Software Standby mode, power supplied to standby SRAM and

USB resume detecting unit (reference data)

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RA6M3 Group

2. Electrical Characteristics

100

10

1

-40

-20

0

20

40

60

80

100

Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.4

Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB

resume detecting unit, power-on reset circuit low-power function disabled (reference data)

100

10

1

-40

-20

0

20

40

60

80

100

Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.5

Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB

resume detecting unit, power-on reset circuit low-power function enabled (reference data)

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RA6M3 Group

2. Electrical Characteristics

2.2.6

VCC Rise and Fall Gradient and Ripple Frequency

Table 2.8

Parameter

Rise and fall gradient characteristics

Symbol Min

Typ

Max

20

-

Unit

Test conditions

VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.0084

-

ms/V

-

Voltage monitor 0 reset enabled at startup

SCI/USB boot mode*¹

0.0084

20

-

VCC falling gradient*²

SfVCC

ms/V

Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.

Note 2. This applies when VBATT is used.

Table 2.9

Rise and fall gradient and ripple frequency characteristics

The ripple voltage must meet the allowable ripple frequency f_r(VCC)within the range between the VCC upper limit (3.6 V) and lower limit

(2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Allowable ripple frequency

f_{r (VCC)}

-

10

kHz

Figure 2.6

V_{r (VCC)}≤ VCC × 0.2

-

1

MHz

ms/V

Figure 2.6

V_{r (VCC)}≤ VCC × 0.08

-

10

-

Figure 2.6

V_{r (VCC)}≤ VCC × 0.06

Allowable voltage change rising

and falling gradient

dt/dVCC

1.0

When VCC change exceeds VCC ±10%

1/f_r(VCC)

VCC

V_r(VCC)

Figure 2.6

Ripple waveform

2.3

AC Characteristics

Frequency

2.3.1

Table 2.10

Parameter

Operation frequency value in high-speed mode

Symbol

Min

Typ

Max

120

60

Unit

Operation frequency

System clock (ICLK*²)

f

-

MHz

Peripheral module clock (PCLKA)*²

Peripheral module clock (PCLKB)*²

Peripheral module clock (PCLKC)*²

Peripheral module clock (PCLKD)*²

Flash interface clock (FCLK)*²

External bus clock (BCLK)*²

EBCLK pin output

-

-*³

-

60

120

60

-*¹

-

120

60

-

SDCLK pin output

VCC ≥ 3.0 V

-

120

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RA6M3 Group

2. Electrical Characteristics

Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

Table 2.11

Parameter

Operation frequency value in low-speed mode

Symbol

Min

Typ

Max

1

Unit

Operation frequency

System clock (ICLK)*²

f

-

MHz

Peripheral module clock (PCLKA)*²

Peripheral module clock (PCLKB)*²

Peripheral module clock (PCLKC)*²,*³

-

1

-

1

-*³

-

1

Peripheral module clock (PCLKD)*²

1

2

Flash interface clock (FCLK)*^1,

External bus clock (BCLK)

EBCLK pin output

*

-

1

-

1

-

1

Note 1. Programming or erasing the flash memory is disabled in low-speed mode.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

Table 2.12

Parameter

Operation frequency value in Subosc-speed mode

Symbol

Min

Typ

Max

37.7

Unit

Operation frequency

System clock (ICLK)*²

f

27.8

-

kHz

Peripheral module clock (PCLKA)*²

Peripheral module clock (PCLKB)*²

Peripheral module clock (PCLKC)*²,*³

-

Peripheral module clock (PCLKD)*²

-

2

Flash interface clock (FCLK)*^1,

External bus clock (BCLK)*²

EBCLK pin output

*

27.8

-

Note 1. Programming or erasing the flash memory is disable in Subosc-speed mode.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3. The ADC12 cannot be used.

2.3.2

Clock Timing

Table 2.13

Clock timing except for sub-clock oscillator (1 of 2)

Parameter

Symbol

t_Bcyc

t_CH

Min

16.6

3.3

-

Typ

Max

Unit

ns

Test conditions

EBCLK pin output cycle time

EBCLK pin output high pulse width

EBCLK pin output low pulse width

EBCLK pin output rise time

EBCLK pin output fall time

SDCLK pin output cycle time

SDCLK pin output high pulse width

SDCLK pin output low pulse width

SDCLK pin output rise time

SDCLK pin output fall time

-

Figure 2.7

-

t_CL

-

t_Cr

5.0

-

t_Cf

-

t_SDcyc

t_CH

8.33

1.0

-

t_CL

-

t_Cr

3.0

t_Cf

-

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RA6M3 Group

2. Electrical Characteristics

Table 2.13

Clock timing except for sub-clock oscillator (2 of 2)

Parameter

Symbol

t_EXcyc

t_EXH

Min

Typ

Max

-

Unit

ns

Test conditions

EXTAL external clock input cycle time

EXTAL external clock input high pulse width

EXTAL external clock input low pulse width

EXTAL external clock rise time

EXTAL external clock fall time

Main clock oscillator frequency

41.66

-

Figure 2.8

15.83

-

ns

t_EXL

15.83

-

ns

t_EXr

-

5.0

24

-*¹

ns

t_EXf

-

ns

f_MAIN

8

-

MHz

ms

-

Main clock oscillation stabilization wait time

(crystal) *¹

t_MAINOSCWT

Figure 2.9

LOCO clock oscillation frequency

f_LOCO

27.8528

-

32.768

-

37.6832

60.4

kHz

μs

-

LOCO clock oscillation stabilization wait time

ILOCO clock oscillation frequency

t_LOCOWT

f_ILOCO

Figure 2.10

12.75

6.8

15

8

17.25

9.2

kHz

MHz

μs

-

MOCO clock oscillation frequency

F_MOCO

-

MOCO clock oscillation stabilization wait time

t_MOCOWT

f_HOCO16

f_HOCO18

f_HOCO20

f_HOCO16

f_HOCO18

f_HOCO20

f_HOCO16

f_HOCO18

f_HOCO20

-

15.0

-

HOCO clock oscillator

oscillation frequency

Without FLL

15.78

17.75

19.72

15.71

17.68

19.64

15.955

17.949

19.944

16

18

20

16

18

20

16

18

20

16.22

18.25

20.28

16.29

18.32

20.36

16.045

18.051

20.056

MHz

-20 ≤ Ta ≤ 105°C

-40 ≤ Ta ≤ -20°C

With FLL

-40 ≤ Ta ≤ 105°C

Sub-clock

frequency accuracy

is ±50 ppm.

HOCO clock oscillation stabilization wait time*²

FLL stabilization wait time

t_HOCOWT

t_FLLWT

f_PLL

-

64.7

1.8

μs

-

ms

MHz

μs

-

PLL clock frequency

120

-

240

-

PLL clock oscillation stabilization wait time

t_PLLWT

174.9

Figure 2.11

Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the

recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended

value.

After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm

that it is 1, and then start using the main clock oscillator.

Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed

operation.

Table 2.14

Parameter

Clock timing for the sub-clock oscillator

Symbol

Min

Typ

32.768

-

Max

Unit

kHz

s

Test conditions

Sub-clock frequency

f_SUB

-

1

Sub-clock oscillation stabilization wait time

t_SUBOSCWT

*

Figure 2.12

Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the

recommended oscillation stabilization time.

After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after

the sub-clock oscillation stabilization time elapses with an adequate margin. Two times the value shown is recommended.

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RA6M3 Group

2. Electrical Characteristics

t_Bcyc, t_SDcyc

t_CH

t_Cf

EBCLK pin output, SDCLK pin output

t_Cr

t_CL

Figure 2.7

Figure 2.8

Figure 2.9

EBCLK and SDCLK output timing

t_EXcyc

t_EXH

t_EXL

EXTAL external clock input

VCC × 0.5

t_EXr

t_EXf

EXTAL external clock input timing

MOSCCR.MOSTP

Main clock oscillator output

Main clock

t_MAINOSCWT

Main clock oscillation start timing

LOCOCR.LCSTP

On-chip oscillator output

t_LOCOWT

LOCO clock

Figure 2.10

LOCO clock oscillation start timing

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RA6M3 Group

2. Electrical Characteristics

PLLCR.PLLSTP

PLL circuit output

t_PLLWT

OSCSF.PLLSF

PLL clock

Figure 2.11

PLL clock oscillation start timing

Note:

Only operate the PLL is operated after main clock oscillation has stabilized.

SOSCCR.SOSTP

Sub-clock oscillator output

t_SUBOSCCWT

Sub-clock

Figure 2.12

Sub-clock oscillation start timing

2.3.3

Reset Timing

Table 2.15

Parameter

Reset timing

Test

Symbol

t_RESWP

t_RESWD

t_RESWS

Min

1

Typ

Max

Unit

ms

conditions

Figure 2.13

Figure 2.14

RES pulse width

Power-on

-

Deep Software Standby mode

0.6

0.3

ms

Software Standby mode, Subosc-speed

mode

ms

All other

t_RESW

200

-

μs

Wait time after RES cancellation

t_RESWT

t_RESW2

-

29

320

33

408

Figure 2.13

-

Wait time after internal reset cancellation

(IWDT reset, WDT reset, software reset, SRAM parity error

reset, SRAM ECC error reset, bus master MPU error reset, bus

slave MPU error reset, stack pointer error reset)

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RA6M3 Group

2. Electrical Characteristics

VCC

RES

t_RESWP

Internal reset signal

(low is valid)

t_RESWT

Figure 2.13

Power-on reset timing

t_RESWD, t_RESWS, t_RESW

RES

Internal reset signal

(low is valid)

t_RESWT

Figure 2.14

Reset input timing

2.3.4

Wakeup Timing

Table 2.16

Parameter

Timing of recovery from low power modes

Test

conditions

Symbol

t_SBYMC

Min

Typ

Max

Unit

Recovery time

from Software

Standby mode*¹

Crystal

System clock source is main

clock oscillator*²

-

2.4*⁹

2.8*⁹

ms

Figure 2.15

The division

ratio of all

oscillators is

1.

resonator

connected

to main

clock

System clock source is PLL

with main clock oscillator*³

t_SBYPC

-

2.7*⁹

3.2*⁹

ms

oscillator

External

clock input

to main

clock

System clock source is main

clock oscillator*⁴

t_SBYEX

t_SBYPE

-

230*⁹

570*⁹

280*⁹

700*⁹

μs

System clock source is PLL

with main clock oscillator*⁵

oscillator

System clock source is sub-clock

oscillator*⁸

t_SBYSC

-

1.2*⁹

1.3*⁹

1.4*⁹

ms

System clock source is LOCO*⁸

t_SBYLO

t_SBYHO

-

1.2*⁹

ms

µs

10

System clock source is HOCO clock

oscillator*⁶

240*^9,

*

310

9, 10

*

System clock source is MOCO clock

oscillator*⁷

t_SBYMO

-

220*⁹

300*⁹

µs

Recovery time from Deep Software Standby mode

t_DSBY

t_DSBYWT

t_SNZ

-

0.65

-

1.0

35

ms

t_cyc

μs

Figure 2.16

Figure 2.17

Wait time after cancellation of Deep Software Standby mode

34

-

10

Recovery time

from Software

Standby mode to

Snooze mode

High-speed mode when system clock

source is HOCO (20 MHz)

35*^9,

*

71

9, 10

*

High-speed mode when system clock

source is MOCO (8 MHz)

t_SNZ

-

11*⁹

14*⁹

μs

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RA6M3 Group

2. Electrical Characteristics

Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be

determined with the following equation:

Total recovery time = recovery time for an oscillator as the system clock source + the longest oscillation stabilization time of any

oscillators requiring longer stabilization times than the system clock source + 2 LOCO cycles (when LOCO is operating) + 3

SOSC cycles (when Subosc is oscillating and MSTPC0 = 0 (CAC module stop)).

Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For

other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 05h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

05h))

Note 3. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other

settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 05h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

05h))

Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 01h).

For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 01h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

01h))

Note 5. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 01h). For other

settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:

t_SBYMC(MOSCWTCR = Xh) = t_SBYMC(MOSCWTCR = 01h) + (t_MAINOSCWT(MOSCWTCR = Xh) - t_MAINOSCWT(MOSCWTCR =

01h))

Note 6. The HOCO frequency is 20 MHz.

Note 7. The MOCO frequency is 8 MHz.

Note 8. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.

Note 9. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time:

STCONR.STCON[1:0] = 00b:16 µs (typical), 34 µs (maximum)

STCONR.STCON[1:0] = 11b:16 µs (typical), 104 µs (maximum).

Note 10. When the SNZCR.RXDREQEN bit is set to 0, 16 μs (typical) or 18 μs (maximum) is added as the HOCO wait time.

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RA6M3 Group

2. Electrical Characteristics

Oscillator

(system clock)

t_SBYOSCWT

t_SBYSEQ

Oscillator

(not the system clock)

ICLK

IRQ

Software Standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of the system clock oscillator is slower

Oscillator

(system clock)

t_SBYSEQ

t_SBYOSCWT

Oscillator

(not the system clock)

t_SBYOSCWT

ICLK

IRQ

Software Standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of an oscillator other than the system clock is slower

Figure 2.15

Software Standby mode cancellation timing

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2. Electrical Characteristics

Oscillator

IRQ

Deep Software Standby

reset

(low is valid)

Internal reset

(low is valid)

Deep Software Standby mode

t_DSBY

t_DSBYWT

Reset exception handling start

Figure 2.16

Deep Software Standby mode cancellation timing

Oscillator

ICLK(except DTC, SRAM)

ICLK(to DTC, SRAM)^*1

PCLK

IRQ

Software Standby mode

Snooze mode

t_SNZ

Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.17

Recovery timing from Software Standby mode to Snooze mode

2.3.5

NMI and IRQ Noise Filter

Table 2.17

NMI and IRQ noise filter

Parameter

Symbol Min

t_NMIW200

_Pcyc× 2*

200

_NMICK× 3.5*

200

_Pcyc× 2*

200

_IRQCK× 3.5*

Typ

Max

Unit

Test conditions

NMI pulse width

-

ns

NMI digital filter disabled

t_Pcyc× 2 ≤ 200 ns

t_Pcyc× 2 > 200 ns

t_NMICK× 3 ≤ 200 ns

1

t

NMI digital filter enabled

IRQ digital filter disabled

IRQ digital filter enabled

2

t

t_NMICK× 3 > 200 ns

t_Pcyc× 2 ≤ 200 ns

t_Pcyc× 2 > 200 ns

IRQ pulse width

t_IRQW

ns

1

t

_IRQCK× 3 ≤ 200 ns

3

t

t_IRQCK× 3 > 200 ns

Note:

200 ns minimum in Software Standby mode.

If the clock source is switched, add 4 clock cycles of the switched source.

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Note 1. t_Pcycindicates the PCLKB cycle.

Note 2.

t_NMICKindicates the cycle of the NMI digital filter sampling clock.

Note 3. t_IRQCKindicates the cycle of the IRQi digital filter sampling clock.

NMI

t_NMIW

Figure 2.18

NMI interrupt input timing

IRQ

t_IRQW

Figure 2.19

IRQ interrupt input timing

2.3.6

Bus Timing

Table 2.18

Bus timing (1 of 2)

Condition 1: When using the CS area controller (CSC).

BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz

VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 2: When using the SDRAM area controller (SDRAMC).

BCLK = SDCLK = 8 to 120 MHz

VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

High drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.

BCLK = SDCLK = 8 to 60 MHz

VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

High drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

t_AD

Min

Max

12.5

-

Unit

ns

Test conditions

Address delay

Byte control delay

CS delay

-

Figure 2.20 to

Figure 2.25

t_BCD

t_CSD

t_ALED

t_RSD

t_RDS

t_RDH

t_WRD

t_WDD

t_WDH

t_WTS

t_WTH

-

ALE delay time

RD delay

-

Read data setup time

Read data hold time

WR/WRn delay

Write data delay

Write data hold time

WAIT setup time

WAIT hold time

12.5

0

-

12.5

-

0

12.5

0

-

Figure 2.26

-

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2. Electrical Characteristics

Table 2.18

Bus timing (2 of 2)

Condition 1: When using the CS area controller (CSC).

BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz

VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 2: When using the SDRAM area controller (SDRAMC).

BCLK = SDCLK = 8 to 120 MHz

VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

High drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.

BCLK = SDCLK = 8 to 60 MHz

VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,

VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

High drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

t_AD2

Min

0.8

2.9

1.5

-

Max

6.8

-

Unit

ns

Test conditions

Address delay 2 (SDRAM)

CS delay 2 (SDRAM)

Figure 2.27 to

Figure 2.33

t_CSD2

t_DQMD

t_CKED

t_RDS2

t_RDH2

t_WDD2

t_WDH2

t_WED

DQM delay (SDRAM)

CKE delay (SDRAM)

Read data setup time 2 (SDRAM)

Read data hold time 2 (SDRAM)

Write data delay 2 (SDRAM)

Write data hold time 2 (SDRAM)

WE delay (SDRAM)

-

6.8

-

0.8

6.8

RAS delay (SDRAM)

t_RASD

t_CASD

CAS delay (SDRAM)

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2. Electrical Characteristics

Data cycle

T_end

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_n1

T_n2

T_W5

EBCLK

t_AD

Address bus

t_RDSt_RDH

t_AD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_RSD

Data read

(RD)

t_CSD

Chip select

(CSn)

Figure 2.20

Address/data multiplexed bus read access timing

Address cycle

Data cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_end

T_n1

T_n2

T_n3

T_W5

EBCLK

t_AD

Address bus

t_AD

t_WDD

t_WDH

t_AD

Address bus/

data bus

t_ALED

Address latch

(ALE)

t_WRD

Data write

(WRm)

t_CSD

Chip select

(CSn)

Figure 2.21

Address/data multiplexed bus write access timing

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2. Electrical Characteristics

CSRWAIT: 2

RDON:1

CSON: 0

CSROFF: 2

T_W1

T_W2

T_end

T_n1

T_n2

EBCLK

Byte strobe mode

t_AD

A23 to A00

A23 to A01

BC1, BC0

1-write strobe mode

t_AD

t_BCD

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7 to CS0

t_RSD

RD (read)

t_RDS

t_RDH

D15 to D00 (read)

Figure 2.22

External bus timing for normal read cycle with bus clock synchronized

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2. Electrical Characteristics

CSWWAIT: 2

WRON: 1

WDON: 1*¹

CSWOFF: 2

WDOFF: 1*¹

CSON:0

T_W1

T_W2

T_end

T_n1

T_n2

EBCLK

Byte strobe mode

t_AD

A23 to A00

A23 to A01

BC1, BC0

1-write strobe mode

t_AD

t_BCD

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7 to CS0

t_WRD

WR1, WR0, WR (write)

D15 to D00 (write)

t_WDD

t_WDH

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.23

External bus timing for normal write cycle with bus clock synchronized

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2. Electrical Characteristics

CSRWAIT:2

RDON:1

CSON:0

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSROFF:2

T_W1

T_W2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_pw1

T_pw2

T_end

T_n1

T_n2

EBCLK

Byte strobe mode

t_AD

A23 to A00

A23 to A01

BC1, BC0

1-write strobe mode

t_AD

t_BCD

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7 to CS0

t_RSD

RD (Read)

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

t_RDS

t_RDH

D15 to D00 (Read)

Figure 2.24

External bus timing for page read cycle with bus clock synchronized

CSPWWAIT:2

CSWWAIT:2

WRON:1

WDON:1*¹

CSON:0

CSPWWAIT:2

CSWOFF:2

WRON:1

WDOFF:1*¹

T_dw1

WDOFF:1*¹

T_n1

WDOFF:1*¹

T_dw1

WDON:1*¹

T_pw1

WDON:1*¹

T_pw1

T_W2

T_end

T_pw2

T_W1

T_end

T_n2

EBCLK

Byte strobe mode

t_AD

A23 to A00

A23 to A01

BC1, BC0

1-write strobe mode

t_AD

t_BCD

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7 to CS0

t_WRD

WR1, WR0, WR (write)

D15 to D00 (write)

t_WDD

t_WDH

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.25

External bus timing for page write cycle with bus clock synchronized

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2. Electrical Characteristics

CSRWAIT:3

CSWWAIT:3

T_W1

T_W2

T_W3

(T_end

)

T_end

T_n1

T_n2

EBCLK

A23 to A00

CS7 to CS0

RD (read)

WR (write)

External wait

t_WTSt_WTHt_WTSt_WTH

WAIT

Figure 2.26

External bus timing for external wait control

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2. Electrical Characteristics

SDRAM command

ACT

RD

PRA

SDCLK

t_AD2

Row

address

A15 to A00

AP*¹

Column address

t_AD2

PRA

command

t_CSD2

SDCS

RAS

t_RASD

t_CASD

CAS

t_WED

WE

(High)

CKE

t_DQMD

DQMn

t_RDS2t_RDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.27

SDRAM single read timing

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2. Electrical Characteristics

SDRAM command

ACT

WR

PRA

SDCLK

t_AD2

Row

address

A15 to A00

AP*¹

Column address

t_AD2

PRA

command

t_CSD2

SDCS

RAS

t_RASD

t_CASD

CAS

t_WED

WE

(High)

CKE

t_DQMD

DQMn

t_WDD2

t_WDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.28

SDRAM single write timing

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2. Electrical Characteristics

ACT

RD RD RD RD PRA

SDCLK

t_AD2

t_AD2t_AD2

t_AD2t_AD2t_AD2t_AD2

t_AD2

Row

address

C0

(column address)

C1

C2

C3

A15 to A00

AP*¹

t_AD2t_AD2

t_AD2

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2

SDCS

t_RASDt_RASD

t_RASD

RAS

CAS

WE

t_CASD

t_WED

(High)

CKE

t_DQMD

DQMn

t_RDS2t_RDH2

t_RDS2

t_RDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.29

SDRAM multiple read timing

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2. Electrical Characteristics

ACT

WR WR WR PRA

WR

SDCLK

t_AD2t_AD2t_AD2

t_AD2t_AD2

C0

Row

address

C1

C2

C3

A15 to A00

AP*¹

(column address)

t_AD2

t_AD2t_AD2

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2t_CSD2

SDCS

t_RASDt_RASD

t_RASDt_RASDt_RASD

RAS

CAS

t_CASD

t_WED

WE

(High)

CKE

t_DQMD

DQMn

t_WDD2t_WDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.30

SDRAM multiple write timing

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2. Electrical Characteristics

ACT

RD

PRA

ACT

RD

PRA

SDRAM command

SDCLK

A15 to A00

AP*¹

t_AD2

t_AD2t_AD2t_AD2

t_AD2t_AD2t_AD2t_AD2

t_AD2t_AD2t_AD2t_AD2t_AD2

Row

address

C0

(column address 0)

C1

C2

C3

R1

C4

C5

C6

C7

t_AD2

t_AD2t_AD2

t_AD2

PRA

command

PRA

command

t_CSD2t_CSD2t_CSD2

t_CSD2t_CSD2t_CSD2t_CSD2

t_CSD2

SDCS

RAS

CAS

WE

t_RASDt_RASD

t_RASDt_RASDt_RASDt_RASD

t_RASDt_RASD

t_CASD

t _WEDt _WED

(High)

CKE

t_DQMD

DQMn

t_RDS2t_RDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.31 SDRAM multiple read line stride timing

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2. Electrical Characteristics

MRS

SDRAM command

SDCLK

t_AD2

A15 to A00

AP*¹

t_AD2

t_CSD2

SDCS

RAS

t_RASD

t_CASD

CAS

t _WED

WE

(High)

CKE

DQMn

(Hi-Z)

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.32

SDRAM mode register set timing

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2. Electrical Characteristics

SDRAM command

SDCLK

Ts (RFA)

(RFS)

(RFX)

(RFA)

t_AD2

A15 to A00

AP*¹

t_AD2

t_CSD2t_CSD2

t_CSD2

t_RASD

t_CASD

t_CSD2

t_RASD

t_CASD

t_CSD2t_CSD2t_CSD2

t_RASDt_RASDt_RASD

t_CASDt_CASDt_CASD

SDCS

RAS

t_RASDt_RASD

t_CASDt_CASD

CAS

(High)

WE

t_CKED

CKE

t_DQMD

DQMn

(Hi-Z)

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.33

SDRAM self-refresh timing

2.3.7

I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing

Table 2.19 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (1 of 2)

GPT32 Conditions:

High drive output is selected in the port drive capability bit in the PmnPFS register.

AGT Conditions:

Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Test

Parameter

I/O ports

POEG

Symbol Min

Max

Unit

t_Pcyc

conditions

Input data pulse width

t_PRW

1.5

3

-

Figure 2.34

Figure 2.35

POEG input trigger pulse width

t_POEW

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2. Electrical Characteristics

Table 2.19 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (2 of 2)

GPT32 Conditions:

High drive output is selected in the port drive capability bit in the PmnPFS register.

AGT Conditions:

Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Test

Parameter

Symbol Min

Max

Unit

conditions

GPT32

Input capture pulse width

Single edge

t_GTICW

1.5

-

t_PDcyc

Figure 2.36

Dual edge

2.5

-

1

GTIOCxY output skew

(x = 0 to 7, Y= A or B)

Middle drive buffer

High drive buffer

Middle drive buffer

High drive buffer

Middle drive buffer

High drive buffer

t_GTISK

*

-

4

6

5

ns

Figure 2.37

GTIOCxY output skew

(x = 8 to 13, Y = A or B)

GTIOCxY output skew

(x = 0 to 13, Y = A or B)

OPS output skew

GTOUUP, GTOULO, GTOVUP,

GTOVLO, GTOWUP, GTOWLO

t_GTOSK

ns

Figure 2.38

Figure 2.39

2

GPT(PWM

Delay

GTIOCxY_Z output skew

t_HRSK

*

-

2.0

(x = 0 to 3, Y = A or B, Z = A)

Generation

Circuit)

3

AGT

AGTIO, AGTEE input cycle

t_ACYC

*

100

40

-

ns

Figure 2.40

AGTIO, AGTEE input high width, low width

t_ACKWH

t_ACKWL

,

AGTIO, AGTO, AGTOA, AGTOB output cycle

ADC12 trigger input pulse width

t_ACYC2

t_TRGW

62.5

1.5

-

ns

ADC12

KINT

t_Pcyc

Figure 2.41

Figure 2.42

KRn (n = 00 to 07) pulse width

t_KR

250

-

ns

Note:

t_Pcyc: PCLKB cycle, t_PDcyc: PCLKD cycle.

Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not

guaranteed.

Note 2. The load is 30 pF.

Note 3. Constraints on input cycle:

When not switching the source clock: t_Pcyc× 2 < t_ACYCshould be satisfied.

When switching the source clock: t_Pcyc× 6 < t_ACYCshould be satisfied.

Port

t_PRW

Figure 2.34

I/O ports input timing

POEG input trigger

t_POEW

Figure 2.35

POEG input trigger timing

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2. Electrical Characteristics

Input capture

t_GTICW

Figure 2.36

GPT32 input capture timing

PCLKD

Output delay

GPT32 output

t_GTISK

Figure 2.37

Figure 2.38

Figure 2.39

GPT32 output delay skew

PCLKD

Output delay

GPT32 output

t_GTOSK

GPT32 output delay skew for OPS

PCLKD

Output delay

GPT32 output

(PWM delay

generation circuit)

t_HRSK

GPT32 (PWM Delay Generation Circuit) output delay skew

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2. Electrical Characteristics

t_ACYC

t_ACKWL

t_ACKWH

AGTIO, AGTEE

(input)

t_ACYC2

AGTIO, AGTO,

AGTOA, AGTOB

(output)

Figure 2.40

AGT input/output timing

ADTRG0,

ADTRG1

t_TRGW

Figure 2.41

ADC12 trigger input timing

KR00 to KR07

t_KR

Figure 2.42

Key interrupt input timing

2.3.8

PWM Delay Generation Circuit Timing

Table 2.20

PWM Delay Generation Circuit timing

Parameter

Operation frequency

Resolution

Min

Typ

-

Max

Unit

Test conditions

80

-

120

MHz

ps

-

260

±2.0

-

PCLKD = 120 MHz

-

DNL*¹

-

LSB

Note 1. This value normalizes the differences between lines in 1-LSB resolution.

2.3.9

CAC Timing

Table 2.21

CAC timing

Test

Parameter

Symbol Min

Typ

Max

Unit

ns

conditions

CAC

CACREF input pulse width

t_PBcyc≤ tcac*²

_PBcyc> tcac*²

t_CACREF4.5 × t_cac+ 3 × t_PBcyc

5 × t_cac+ 6.5 × t_PBcyc

-

t

ns

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2. Electrical Characteristics

Note 1. t_PBcyc: PCLKB cycle.

Note 2. t_cac: CAC count clock source cycle.

2.3.10

SCI Timing

Table 2.22

SCI timing (1)

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9.

For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.

Test

conditions

Parameter

Symbol Min

Max

Unit^*1

SCI

Input clock cycle

Asynchronous

t_Scyc

4

6

-

t_Pcyc

Figure 2.43

Clock

synchronous

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t_SCKW

t_SCKr

t_SCKf

t_Scyc

0.4

-

0.6

5

t_Scyc

ns

-

5

ns

Asynchronous

6

-

t_Pcyc

Clock

4

-

synchronous

Output clock pulse width

Output clock rise time

Output clock fall time

Transmit data delay

t_SCKW

t_SCKr

t_SCKf

t_TXD

0.4

0.6

5

t_Scyc

ns

-

5

ns

Clock

25

ns

Figure 2.44

synchronous

Receive data setup time

Receive data hold time

Clock

synchronous

t_RXS

t_RXH

15

5

-

ns

Clock

synchronous

Note 1. t_Pcyc: PCLKA cycle.

t_SCKW

t_SCKr

t_SCKf

SCKn

(n = 0 to 9)

t_Scyc

Figure 2.43

SCK clock input/output timing

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2. Electrical Characteristics

SCKn

TxDn

t_TXD

t_RXSt_RXH

RxDn

n = 0 to 9

Figure 2.44

Table 2.23

SCI input/output timing in clock synchronous mode

SCI timing (2)

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9.

For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.

Test

Parameter

Symbol

Min

Max

Unit

conditions

Simple SCK clock cycle output

t_SPcyc

4 (PCLKA ≤ 60 MHz)

65536

t_Pcyc

Figure 2.45

SPI

(master)

8 (PCLKA > 60 MHz)

SCK clock cycle input (slave)

-

6 (PCLKA ≤ 60 MHz)

65536

12 (PCLKA > 60 MHz)

SCK clock high pulse width

SCK clock low pulse width

SCK clock rise and fall time

Data input setup time

Data input hold time

t_SPCKWH

t_SPCKWL

t_SPCKr, t_SPCKf

t_SU

0.4

0.6

t_SPcyc

ns

0.4

0.6

-

20

33.3

-

ns

Figure 2.46 to

Figure 2.49

t_H

33.3

-

ns

SS input setup time

t_LEAD

t_LAG

1

-

t_SPcyc

ns

SS input hold time

1

-

Data output delay

t_OD

-

33.3

-

Data output hold time

Data rise and fall time

SS input rise and fall time

Slave access time

t_OH

-10

ns

t_Dr, t_Df

-

16.6

ns

t_SSLr, t_SSLf

ns

t_SA

4 (PCLKA ≤ 60 MHz)

t_Pcyc

Figure 2.49

8 (PCLKA > 60 MHz)

Slave output release time

t_REL

-

5 (PCLKA ≤ 60 MHz)

t_Pcyc

10 (PCLKA > 60 MHz)

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2. Electrical Characteristics

t_SPCKr

t_SPCKf

t_SPCKWH

V_OH

V_OL

V_OH

SCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

SCKn

slave select input

V_IL

t_SPCKWL

V_IL

(n = 0 to 9)

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Figure 2.45

SCI simple SPI mode clock timing

SCKn

CKPOL = 0

output

SCKn

CKPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 9)

Figure 2.46

SCI simple SPI mode timing for master when CKPH = 1

SCKn

CKPOL = 1

output

SCKn

CKPOL = 0

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

(n = 0 to 9)

Figure 2.47

SCI simple SPI mode timing for master when CKPH = 0

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2. Electrical Characteristics

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 0

input

SCKn

CKPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

(n = 0 to 9)

Figure 2.48

SCI simple SPI mode timing for slave when CKPH = 1

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(Last data)

MSB OUT

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

LSB IN

(n = 0 to 9)

Figure 2.49

SCI simple SPI mode timing for slave when CKPH = 0

SCI timing (3) (1 of 2)

Table 2.24

Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

t_Sr

Min

Max

1000

300

Unit

ns

Test conditions

Simple IIC

(Standard mode)

SDA input rise time

-

Figure 2.50

SDA input fall time

t_Sf

-

ns

SDA input spike pulse removal time

Data input setup time

t_SP

0

4 × t_IICcyc

ns

t_SDAS

t_SDAH

250

-

ns

Data input hold time

0

-

ns

1

SCL, SDA capacitive load

C_b*

400

pF

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2. Electrical Characteristics

Table 2.24

SCI timing (3) (2 of 2)

Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

t_Sr

Min

Max

Unit

ns

Test conditions

Simple IIC

SDA input rise time

-

300

Figure 2.50

(Fast mode)

SDA input fall time

t_Sf

-

300

ns

SDA input spike pulse removal time

Data input setup time

t_SP

0

4 × t_IICcyc

ns

t_SDAS

t_SDAH

100

-

ns

Data input hold time

0

-

ns

1

SCL, SDA capacitive load

C_b*

400

pF

Note:

t_IICcyc: IIC internal reference clock (IICφ) cycle.

Note 1. Cb indicates the total capacity of the bus line.

V_IH

V_IL

SDAn

t_Sr

t_Sf

t_SP

SCLn

P*¹

S*¹

Sr*¹

(n = 0 to 9)

t_SDAH

t_SDAS

Note 1. S, P, and Sr indicate the following:

S: Start condition

Test conditions:

V_IH= VCC × 0.7, V_IL= VCC × 0.3

_OL= 0.6 V, I_OL= 6 mA

P: Stop condition

V

Sr: Restart condition

Figure 2.50

SCI simple IIC mode timing

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2. Electrical Characteristics

2.3.11

SPI Timing

Table 2.25

Conditions:

SPI timing

For RSPCKA and RSPCKB pins, high drive output is selected with the port drive capability bit in the PmnPFS register.

For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

SPI RSPCK clock cycle

Symbol Min

t_SPcyc2 (PCLKA  60 MHz)

Max

Unit*¹Test conditions*²

Master

4096

t_Pcyc

Figure 2.51

C = 30 pF

4 (PCLKA > 60 MHz)

Slave

4

4096

-

RSPCK clock high

pulse width

Master

t_SPCKWH(t_SPcyc- t_SPCKr

_SPCKf) / 2 - 3

-

ns

t

Slave

2 × t_Pcyc

-

RSPCK clock low pulse Master

width

t_SPCKWL(t_SPcyc- t_SPCKr

ns

t

_SPCKf) / 2 - 3

Slave

2 × t_Pcyc

-

RSPCK clock rise and Master

t_SPCKr,

t_SPCKf

-

5

1

-

ns

µs

ns

fall time

Slave

-

Data input setup time

Data input hold time

Master

Slave

t_SU

4

5

0

Figure 2.52 to

Figure 2.57

C = 30 pF

-

Master

t_HF

-

ns

(PCLKA division ratio

set to 1/2)

Master

t_H

t_Pcyc

-

(PCLKA division ratio

set to a value other

than 1/2)

Slave

t_H

20

-

SSL setup time

SSL hold time

Master

t_LEAD

N × t_SPcyc- 10*³

N ×

t_SPcyc

100*³

ns

+

Slave

6 x t_Pcyc

-

ns

Master

t_LAG

N × t_SPcyc- 10 *⁴

N ×

t_SPcyc

100*⁴

Slave

6 x t_Pcyc

-

ns

Data output delay

Master

Slave

t_OD

t_OH

t_TD

-

6.3

20

-

Data output hold time

Master

Slave

0

ns

0

-

Successive

Master

t_SPcyc+ 2 × t_Pcyc

8 ×

transmission delay

t_SPcyc

+

2 × t_Pcyc

Slave

Output

Input

6 × t_Pcyc

MOSI and MISO rise

and fall time

t_Dr,t_Df

-

5

1

5

1

ns

μs

ns

μs

SSL rise and fall time

Output

Input

t_SSLr,

t_SSLf

Slave access time

t_SA

2 x t_Pcycns

+ 28

Figure 2.56 and

Figure 2.57

C = 30_PF

Slave output release time

t_REL

-

2 x t_Pcyc

+ 28

Note 1. t_Pcyc: PCLKA cycle.

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2. Electrical Characteristics

Note 2. Must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as groups. For the SPI

interface, the AC portion of the electrical characteristics is measured for each group.

Note 3. N is set to an integer from 1 to 8 by the SPCKD register.

Note 4. N is set to an integer from 1 to 8 by the SSLND register.

t_SPCKr

t_SPCKf

t_SPCKWH

SPI

V_OH

V_OL

V_OH

RSPCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

RSPCKn

slave select input

V_IL

t_SPCKWL

V_IL

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

n = A or B

Figure 2.51

SPI clock timing

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.52

SPI timing for master when CPHA = 0

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2. Electrical Characteristics

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_HF

MISOn

input

LSB IN

MSB IN

DATA

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

DATA

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.53

SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.54

SPI timing for master when CPHA = 1

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2. Electrical Characteristics

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_HF

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

n = A or B

Figure 2.55

RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2

SPI

t_TD

SSLn0

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

n = A or B

Figure 2.56

SPI timing for slave when CPHA = 0

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2. Electrical Characteristics

SPI

t_TD

SSLn0

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(Last data)

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

LSB IN

n = A or B

Figure 2.57

SPI timing for slave when CPHA = 1

2.3.12

QSPI Timing

Table 2.26

QSPI timing

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

QSPI QSPCK clock cycle

Symbol

t_QScyc

t_QSWH

t_QSWL

t_Su

Min

Max

Unit*¹

t_Pcyc

ns

Test conditions

2

48

-

Figure 2.58

QSPCK clock high pulse width

QSPCK clock low pulse width

Data input setup time

t_QScyc× 0.4

-

ns

8

-

ns

Figure 2.59

Data input hold time

t_IH

0

-

ns

QSSL setup time

t_LEAD

(N+0.5) x

t

(N+0.5) x

t

_Qscyc+100 *²

ns

_Qscyc- 5 *²

QSSL hold time

t_LAG

(N+0.5) x

_Qscyc- 5 *³

(N+0.5) x

t

_Qscyc+100 *³

ns

t

Data output delay

t_OD

t_OH

t_TD

-

4

ns

Data output hold time

Successive transmission delay

-3.3

1

-

ns

16

t_QScyc

Note 1. t_Pcyc: PCLKA cycle.

Note 2. N is set to 0 or 1 in SFMSLD.

Note 3. N is set to 0 or 1 in SFMSHD.

t_QSWH

t_QSWL

QSPCLK output

t_QScyc

Figure 2.58

QSPI clock timing

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2. Electrical Characteristics

t_TD

QSSL

output

t_LEAD

t_LAG

QSPCLK

output

t_SU

t_H

QIO0-3

input

MSB IN

DATA

LSB IN

t_OH

t_OD

QIO0-3

output

MSB OUT

DATA

LSB OUT

IDLE

Figure 2.59

Transmit and receive timing

2.3.13

IIC Timing

Table 2.27

IIC timing (1) (1 of 2)

(1) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.

(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.

(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Test

Parameter

Symbol Min*¹

Max

Unit conditions*³

IIC

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 1300

-

ns

Figure 2.60

(Standard mode,

SMBus)

ICFER.FMPE = 0

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

3 (6) × t_IICcyc+ 300

-

3 (6) × t_IICcyc+ 300

-

1000

t_Sf

-

300

SCL, SDA input spike pulse removal t_SP

time

0

1 (4) × t_IICcyc

SDA input bus free time when

wakeup function is disabled

t_BUF

3 (6) × t_IICcyc+ 300

-

ns

SDA input bus free time when

wakeup function is enabled

t_BUF

3 (6) × t_IICcyc+ 4 × t_Pcyc

+ 300

START condition input hold time

when wakeup function is disabled

t_STAH

t_STAS

t_IICcyc+ 300

START condition input hold time

when wakeup function is enabled

1 (5) × t_IICcyc+ t_Pcyc

300

+

Repeated START condition input

setup time

1000

STOP condition input setup time

Data input setup time

t_STOS

t_SDAS

t_SDAH

C_b

1000

-

ns

pF

t_IICcyc+ 50

-

Data input hold time

0

-

SCL, SDA capacitive load

400

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2. Electrical Characteristics

Table 2.27

IIC timing (1) (2 of 2)

(1) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.

(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.

(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Test

Parameter

Symbol Min*¹

Max

Unit conditions*³

IIC

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 600

-

ns

Figure 2.60

(Fast mode)

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

3 (6) × t_IICcyc+ 300

-

20 × (external pullup

voltage/5.5V)*²

300

SCL, SDA input fall time

t_Sf

20 × (external pullup

voltage/5.5V)*²

300

ns

SCL, SDA input spike pulse removal t_SP

time

0

1 (4) × t_IICcyc

SDA input bus free time when

wakeup function is disabled

t_BUF

3 (6) × t_IICcyc+ 300

-

SDA input bus free time when

wakeup function is enabled

t_BUF

3 (6) × t_IICcyc+ 4 × t_Pcyc

+ 300

START condition input hold time

when wakeup function is disabled

t_STAH

t_STAS

t_IICcyc+ 300

START condition input hold time

when wakeup function is enabled

1 (5) × t_IICcyc+ t_Pcyc

300

+

Repeated START condition input

setup time

300

STOP condition input setup time

Data input setup time

t_STOS

t_SDAS

t_SDAH

C_b

300

-

ns

pF

t_IICcyc+ 50

-

Data input hold time

0

-

SCL, SDA capacitive load

400

Note:

t_IICcyc: IIC internal reference clock (IICφ) cycle, t_Pcyc: PCLKB cycle.

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 2. Only supported for SCL0_A, SDA0_A, SCL2, and SDA2.

Note 3. Must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as groups. For the IIC

interface, the AC portion of the electrical characteristics is measured for each group.

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2. Electrical Characteristics

Table 2.28

IIC timing (2)

Setting of the SCL0_A, SDA0_A pins is not required with the port drive capability bit in the PmnPFS register.

Test

Parameter

Symbol Min*^1,*²

Max

Unit conditions

IIC

SCL input cycle time

t_SCL

t_SCLH

t_SCLL

t_Sr

6 (12) × t_IICcyc+ 240

-

ns

Figure 2.60

(Fast-mode+)

ICFER.FMPE = 1

SCL input high pulse width

SCL input low pulse width

SCL, SDA input rise time

SCL, SDA input fall time

3 (6) × t_IICcyc+ 120

-

3 (6) × t_IICcyc+ 120

-

120

t_Sf

-

120

SCL, SDA input spike pulse removal

time

t_SP

0

1 (4) × t_IICcyc

SDA input bus free time when

wakeup function is disabled

t_BUF

3 (6) × t_IICcyc+ 120

-

ns

SDA input bus free time when

wakeup function is enabled

t_BUF

3 (6) × t_IICcyc+ 4 × t_Pcyc

+ 120

Start condition input hold time when

wakeup function is disabled

t_STAH

t_IICcyc+ 120

START condition input hold time

when wakeup function is enabled

1 (5) × t_IICcyc+ t_Pcyc

120

+

Restart condition input setup time

Stop condition input setup time

Data input setup time

t_STAS

t_STOS

t_SDAS

t_SDAH

C_b

120

-

ns

pF

120

-

t_IICcyc+ 30

-

Data input hold time

0

-

SCL, SDA capacitive load

550

Note:

t_IICcyc: IIC internal reference clock (IICφ) cycle, t_Pcyc: PCLKB cycle.

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 2. Cb indicates the total capacity of the bus line.

V_IH

SDA0 to SDA2

V_IL

t_BUF

t_SCLH

t_STAS

t_STOS

t_STAH

t_SP

SCL0 to SCL2

P*¹

S*¹

Sr*¹

t_SCLL

t_Sr

t_Sf

t_SDAS

t_SCL

t_SDAH

Test conditions:

V_IH= VCC × 0.7, V_IL= VCC × 0.3

V_OL= 0.6 V, I_OL= 6 mA (ICFER.FMPE = 0)

V_OL= 0.4 V, I_OL= 15 mA (ICFER.FMPE = 1)

Note 1. S, P, and Sr indicate the following:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.60

I²C bus interface input/output timing

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2.3.14

2. Electrical Characteristics

SSIE Timing

Table 2.29

SSIE timing

(1) High drive output is selected with the port drive capability bit in the PmnPFS register.

(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface,

the AC portion of the electrical characteristics is measured for each group.

Target specification

Parameter

Symbol

Min.

80

0.35

-

Max.

Unit

ns

Comments

SSIBCK

Cycle

Master

Slave

t_O

t_I

-

Figure 2.61

-

ns

High level/ low level

Master

Slave

t_HC/t_LC

-

t_O

-

t_I

Rising time/falling time Master

Slave

t_RC/t_FC

0.15

t_O/ t_I

ns

-

0.15

SSILRCK/SSIFS,

SSITXD0,SSIRXD0,

SSIDATA1

Input set up time

Master

Slave

t_SR

12

8

-

Figure 2.63,

Figure 2.64

-

ns

Input hold time

Master

Slave

t_HR

-

ns

15

-10

0

-

ns

Output delay time

Master

Slave

t_DTR

5

20

ns

Figure 2.63,

Figure 2.64

Output delay time from Slave

SSILRCK/SSIFS

t_DTRW

-

20

ns

Figure 2.65*¹

change

GTIOC1A,

AUDIO_CLK

Cycle

t_EXcyc

t_EXL

t_EXH

20

-

ns

Figure 2.62

High level/ low level

/

0.4

0.6

t_EXcyc

Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK/SSIFS pin is used to

generate transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA1 pin.

t_HC

t_RC

t_FC

t_LC

SSIBCKn

t_O, t_I

Figure 2.61

SSIE clock input/output timing

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t_EXcyc

t_EXH

t_EXL

GTIOC1A,

AUDIO_CLK

(input)

1/2 VCC

t_EXf

t_EXr

Figure 2.62

Clock input timing

SSIBCKn

(Input or Output)

SSILRCKn/SSIFSn (input),

SSIRXD0,

SSIDATA1 (input)

t_SR

t_HR

SSILRCKn/SSIFSn (output),

SSITXD0,

SSIDATA1 (output)

t_DTR

Figure 2.63

SSIE data transmit and receive timing when SSICR.BCKP = 0

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2. Electrical Characteristics

SSIBCKn

(Input or Output)

SSILRCKn/SSIFSn (input),

SSIRXD0,

SSIDATA1 (input)

t_SR

t_HR

SSILRCKn/SSIFSn (output),

SSITXD0,

SSIDATA1 (output)

t_DTR

Figure 2.64

SSIE data transmit and receive timing when SSICR.BCKP = 1

SSILRCKn/SSIFSn (input)

SSITXD0,

SSIDATA1 (output)

t_DTRW

MSB bit output delay after SSILRCKn/SSIFSn change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.

Figure 2.65

SSIE data output delay after SSILRCKn/SSIFSn change

2.3.15

SD/MMC Host Interface Timing

Table 2.30

SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Parameter

Symbol

T_SDCYC

T_SDWH

T_SDWL

T_SDLH

Min

20

6.5

-

Max

Unit

ns

Test conditions*¹

SDCLK clock cycle

-

Figure 2.66

SDCLK clock high pulse width

SDCLK clock low pulse width

SDCLK clock rise time

-

3

5

-

SDCLK clock fall time

T_SDHL

-

SDCMD/SDDAT output data delay

SDCMD/SDDAT input data setup

SDCMD/SDDAT input data hold

T_SDODLY

T_SDIS

-6

4

T_SDIH

2

-

Note 1. Must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as groups. For

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2. Electrical Characteristics

the SD/MMC Host interface, the AC portion of the electrical characteristics is measured for each group.

T_SDCYC

T_SDWL

T_SDWH

SDnCLK

(output)

T_SDLH

T_SDHL

T_SDODLY(max)

T_SDODLY(min)

SDnCMD/SDnDATm

(output)

T_SDIS

T_SDIH

SDnCMD/SDnDATm

(input)

n = 0, 1; m = 0 to 7

Figure 2.66

SD/MMC Host Interface signal timing

2.3.16

ETHERC Timing

Table 2.31

ETHERC timing

Conditions: ETHERC (RMII): Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins:

ET0_MDC, ET0_MDIO.

For other pins, high drive output is selected in the port drive capability bit in the PmnPFS register.

ETHERC (MII): Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Test

Parameter

Symbol Min

Max

Unit

ns

MHz

%

conditions*³

ETHERC

(RMII)

REF50CK cycle time

T_ck

20

-

Figure 2.67 to

Figure 2.70

REF50CK frequency, typical 50 MHz

REF50CK duty

-

50 + 100 ppm

-

35

0.5

2.5

3

65

REF50CK rise/fall time

T_ckr/ckf

T_co

3.5

ns

RMII0_xxxx*¹output delay

RMII0_xxxx*²setup time

RMII0_xxxx*²hold time

RMII0_xxxx*^1,*²rise/fall time

ET0_WOL output delay

ET0_TX_CLK cycle time

ET0_TX_EN output delay

ET0_ETXD0 to ET0_ETXD3 output delay

ET0_CRS setup time

12.0

T_su

-

T_hd

1

-

T_r/T_f

t_WOLd

t_Tcyc

t_TENd

t_MTDd

t_CRSs

t_CRSh

t_COLs

t_COLh

t_TRcyc

t_RDVs

t_RDVh

t_MRDs

t_MRDh

t_RERs

t_RESh

t_WOLd

0.5

1

4

23.5

Figure 2.71

-

ETHERC

(MII)

40

1

-

20

Figure 2.72

1

20

10

40

10

1

-

ET0_CRS hold time

-

ET0_COL setup time

-

Figure 2.73

ET0_COL hold time

-

ET0_RX_CLK cycle time

ET0_RX_DV setup time

ET0_RX_DV hold time

-

Figure 2.74

-

ET0_ERXD0 to ET0_ERXD3 setup time

ET0_ERXD0 to ET0_ERXD3 hold time

ET0_RX_ER setup time

ET0_RX_ER hold time

-

Figure 2.75

Figure 2.76

-

ET0_WOL output delay

23.5

Note 1. RMII0_TXD_EN, RMII0_TXD1, RMII0_TXD0.

Note 2. RMII0_CRS_DV, RMII0_RXD1, RMII0_RXD0, RMII0_RX_ER.

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Note 3. The following pins, must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as

groups. For the ETHERC (RMII) Host interface, the AC portion of the electrical characteristics is measured for each group.

REF50CK0_A, REF50CK0_B, RMII0_xxxx_A, RMII0_xxxx_B

Tck

90%

Tckr

REF50CK0 50%

Tckf

Tco

10%

Tsu

Thd

Tr

Tf

90%

Change

in signal

level

Change

in signal

level

RMII0_xxxx^*150%

Change in

signal level

Signal

10%

Note 1. RMII0_TXD_EN, RMII0_TXD1, RMII0_TXD0, RMII0_CRS_DV, RMII0_RXD1, RMII0_RXD0,

RMII0_RX_ER

Figure 2.67

REF50CK0 and RMII signal timing

T_CK

REF50CK0

T_CO

RMII0_TXD_EN

T_CO

RMII0_TXD1,

RMII0_TXD0

Preamble

SFD

DATA

CRC

Figure 2.68

RMII transmission timing

REF50CK0

Tsu

Thd

RMII0_CRS_DV

Thd

Tsu

RMII0_RXD1,

RMII0_RXD0

Preamble

DATA

CRC

SFD

RMII0_RX_ER

L

Figure 2.69

RMII reception timing in normal operation

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2. Electrical Characteristics

REF50CK0

RMII0_CRS_DV

RMII0_RXD1,

RMII0_RXD0

Preamble

SFD

DATA

xxxx

Thd

Tsu

RMII0_RX_ER

Figure 2.70

RMII reception timing when an error occurs

REF50CK0

t_WOLd

ET0_WOL

Figure 2.71

WOL output timing for RMII

ET0_TX_CLK

t_TENd

ET0_TX_EN

t_MTDd

Preamble

SFD

DATA

CRC

ET0_ETXD[3:0]

ET0_TX_ER

t_CRSs

t_CRSh

ET0_CRS

ET0_COL

Figure 2.72

MII transmission timing in normal operation

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2. Electrical Characteristics

ET0_TX_CLK

ET0_TX_EN

Preamble

JAM

ET0_ETXD[3:0]

ET0_TX_ER

ET0_CRS

t_COLs

t_COLh

ET0_COL

Figure 2.73

MII transmission timing when a conflict occurs

ET0_RX_CLK

t_RDVs

t_RDVh

ET0_RX_DV

t_MRDh

t_MRDs

Preamble

SFD

DATA

CRC

ET0_ERXD[3:0]

ET0_RX_ER

Figure 2.74

MII reception timing in normal operation

ET0_RX_CLK

ET0_RX_DV

Preamble

SFD

DATA

xxxx

ET0_ERXD[3:0]

t_RERh

t_RERs

ET0_RX_ER

Figure 2.75

MII reception timing when an error occurs

ET0_RX_CLK

ET0_WOL

t_WOLd

Figure 2.76

WOL output timing for MII

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2.3.17

2. Electrical Characteristics

PDC Timing

Table 2.32

PDC timing

Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Output load conditions: V_OH= VCC × 0.5, V_OL= VCC × 0.5, C = 30 pF

Test

Parameter

Symbol

t_PIXcyc

t_PIXH

Min

Max

Unit

ns

conditions

PDC PIXCLK input cycle time

PIXCLK input high pulse width

PIXCLK input low pulse width

PIXCLK rise time

37

-

Figure 2.77

10

-

t_PIXL

10

-

t_PIXr

-

5

-

PIXCLK fall time

t_PIXf

-

PCKO output cycle time

PCKO output high pulse width

PCKO output low pulse width

PCKO rise time

t_PCKcyc

t_PCKH

t_PCKL

t_PCKr

2 × t_PBcyc

Figure 2.78

Figure 2.79

(t_PCKcyc- t_PCKr- t_PCKf)/2 - 3

-

(t_PCKcyc- t_PCKr- t_PCKf)/2 - 3

-

5

-

PCKO fall time

t_PCKf

-

VSYNV/HSYNC input setup time

VSYNV/HSYNC input hold time

PIXD input setup time

PIXD input hold time

t_SYNCS

t_SYNCH

t_PIXDS

t_PIXDH

10

5

-

10

5

-

Note 1. t_PBcyc: PCLKB cycle.

t_PIXcyc

t_PIXH

t_PIXf

PIXCLK input

t_PIXr

t_PIXL

Figure 2.77

PDC input clock timing

t_PCKcyc

t_PCKH

t_PCKf

PCKO pin output

t_PCKr

t_PCKL

Figure 2.78

PDC output clock timing

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PIXCLK

VSYNC

HSYNC

t_SYNCS

t_SYNCH

t_SYNCS

t_SYNCH

t_PIXDS

t_PIXDH

PIXD7 to PIXD0

Figure 2.79

PDC AC timing

2.3.18

GLCDC Timing

Table 2.33

Conditions:

GLCDC timing

LCD_CLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

LCD_DATA: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

t_Ecyc

t_WL

Min

-

Typ

Max

60*¹

0.55

60*¹

0.6

Unit

Test conditions

LCD_EXTCLK input clock frequency

LCD_EXTCLK input clock low pulse width

LCD_EXTCLK input clock high pulse width

LCD_CLK output clock frequency

LCD_CLK output clock low pulse width

LCD_CLK output clock high pulse width

LCD data output delay timing _A or _B combinations*²

_A and _B combinations*³

-

MHz

t_Ecyc

Figure 2.80

0.45

-

t_WH

t_Lcyc

t_LOL

t_LOH

t_DD

MHz

t_Lcyc

ns

Figure 2.81

Figure 2.82

0.4

-3.5

-5.0

0.6

4

5.5

Note 1. Parallel RGB888, 666,565: Maximum 54 MHz

Serial RGB888: Maximum 60 MHz (4x speed)

Note 2. Use pins that have a letter appended to their names, for instance, “_A” or “_B”, to indicate

Note 3. Pins of group “_A” and “_B” combinations are used.

t_Dcyc,t_Ecyc

t_WH

t_WL

V_IHV_IH

1/2 Vcc

V_ILV_IL

LCD_EXTCLK

Figure 2.80

LCD_EXTCLK clock input timing

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2. Electrical Characteristics

t_Lcyc

t_LOL

t_LOH

LCD_CLK

Figure 2.81

LCD_CLK clock output timing

LCD_CLK

t_DD

Output on

falling edge

LCD_DATA23 to

LCD_DATA00,

LCD_TCON3 to

LCD_TCON0

t_DD

Output on

rising edge

Figure 2.82

Display output timing

2.4

USB Characteristics

USBHS Timing

2.4.1

Table 2.34

USBHS low-speed characteristics for host only (USBHS_DP and USBHS_DM pin characteristics)

Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 12/20/24 MHz, UCLK = 48 MHz

Parameter

Symbol

V_IH

Min

2.0

-

Typ

Max

Unit

V

Test conditions

Input

characteristics

Input high voltage

-

Input low voltage

V_IL

0.8

-

V

Differential input sensitivity

V_DI

0.2

V

| USBHS_DP -

USBHS_DM |

Differential common-mode

range

V_CM

0.8

-

2.5

V

-

Output

characteristics

Output high voltage

Output low voltage

Cross-over voltage

Rise time

V_OH

V_OL

V_CRS

t_LR

2.8

0.0

1.3

75

-

3.6

V

I_OH= -200 μA

-

0.3

V

I_OL= 2 mA

2.0

V

-

Figure 2.83,

Figure 2.84

300

125

24.80

ns

%

kΩ

-

Fall time

t_LF

75

-

Rise/fall time ratio

t_LR/ t_LF

80

t_LR/ t_LF

-

Pull-up,

Pull-down

characteristics

USBHS_DP and USBHS_DM R_pd

pull-down resistors (Host)

14.25

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90%

V_CRS

USBHS_DP,

USBHS_DM

10%

t_r

t_f

Figure 2.83

USBHS_DP and USBHS_DM output timing in low-speed mode

Observation

point

USBHS_DP

USBHS_DM

200 pF to

600 pF

3.6 V

1.5 K

200 pF to

600 pF

Figure 2.84

Table 2.35

Test circuit in low-speed mode

USBHS full-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)

Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 12/20/24 MHz, UCLK = 48 MHz

Parameter

Symbol

V_IH

Min

2.0

-

Typ

Max

Unit Test conditions

Input

characteristics

Input high voltage

-

V

-

Input low voltage

V_IL

0.8

-

Differential input sensitivity

V_DI

0.2

| USBHS_DP -

USBHS_DM |

Differential common-mode

range

V_CM

0.8

-

2.5

V

-

Output

characteristics

Output high voltage

Output low voltage

Cross-over voltage

Rise time

V_OH

V_OL

2.8

0.0

1.3

4

-

3.6

V

I_OH= -200 μA

-

0.3

V

I_OL= 2 mA

V_CRS

t_LR

2.0

V

-

Figure 2.85,

Figure 2.86

20

ns

%

Ω

-

Fall time

t_LF

4

20

-

Rise/fall time ratio

Output resistance

t_LR/ t_LF

Z_DRV

90

40.5

111.11

49.5

t_FR/ t_FF

-

Rs Not used

(PHYSET.REPSEL[1:0] = 01b

and PHYSET. HSEB = 0)

DC

USBHS_DM pull-up resistor

(device)

R_pu

0.900

1.425

-

1.575

3.090

kΩ

During idle state

characteristics

During transmission and

reception

USBHS_DP/USBHS_DM

pull-down resistor (host)

R_pd

14.25

-

24.80

kΩ

-

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90%

V_CRS

USBHS_DP,

USBHS_DM

10%

t_FR

10%

t_FF

Figure 2.85

USBHS_DP and USBHS_DM output timing in full-speed mode

Observation

point

USBHS_DP

50 pF

USBHS_DM

50 pF

Figure 2.86

Table 2.36

Test circuit in full-speed mode

USBHS high-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)

Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 12/20/24 MHz

Parameter

Symbol

V_HSSQ

V_HSDSC

V_HSCM

V_HSOI

Min

100

525

-50

Typ

Max

150

625

500

10

Unit

mV

ps

Test conditions

Input

characteristics

Squelch detect sensitivity

Disconnect detect sensitivity

Common-mode voltage

Idle state

-

Figure 2.87

Figure 2.88

-

Output

characteristics

-10.0

360

-10.0

700

-900

500

40.5

Output high voltage

Output low voltage

V_HSOH

V_HSOL

V_CHIRPJ

V_CHIRPK

t_HSR

440

10

Chirp J output voltage (difference)

Chirp K output voltage (difference)

Rise time

1100

-500

-

AC

Figure 2.89

-

characteristics

Fall time

t_HSF

-

ps

Output resistance

Z_HSDRV

49.5

Ω

USBHS_DP,

USBHS_DM

V_HSSQ

Figure 2.87

USBHS_DP and USBHS_DM squelch detect sensitivity in high-speed mode

USBHS_DP,

USBHS_DM

V_HSDSC

Figure 2.88

USBHS_DP and USBHS_DM disconnect detect sensitivity in high-speed mode

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90%

USBHS_DP,

USBHS_DM

10%

t_HSR

10%

t_HSF

Figure 2.89

USBHS_DP and USBHS_DM output timing in high-speed mode

Observation

point

USBHS_DP

USBHS_DM

45 

Figure 2.90

Table 2.37

Test circuit in high-speed mode

USBHS high-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)

Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 12/20/24 MHz

Parameter

Symbol

I_{DP_SINK}

I_{DM_SINK}

I_{DP_SRC}

V_{DAT_REF}

V_{DP_SRC}

V_{DM_SRC}

Min

25

Max

175

13

Unit

μA

V

Test conditions

Battery Charging

Specification

D+ sink current

-

D- sink current

25

-

DCD source current

Data detection voltage

D+ source voltage

D- source voltage

7

-

0.25

0.5

0.4

0.7

-

V

Output current = 250 μA

V

2.4.2

USBFS Timing

Table 2.38

USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics) (1 of 2)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS = AVCC_USBHS = 3.0

to 3.6 V, UCLK = 48 MHz

Parameter

Symbol

V_IH

Min

2.0

-

Typ

Max

-

Unit

V

Test conditions

Input

characteristics

Input high voltage

-

Input low voltage

V_IL

0.8

-

V

-

Differential input sensitivity

V_DI

0.2

0.8

V

| USB_DP - USB_DM |

-

Differential common-mode

range

V_CM

2.5

V

Output

characteristics

Output high voltage

Output low voltage

Cross-over voltage

Rise time

V_OH

V_OL

V_CRS

t_LR

2.8

0.0

1.3

75

-

3.6

0.3

2.0

300

125

V

I_OH= -200 μA

I_OL= 2 mA

V

Figure 2.91

ns

%

Fall time

t_LF

75

Rise/fall time ratio

t_LR/ t_LF

80

t_LR/ t_LF

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2. Electrical Characteristics

Table 2.38

USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics) (2 of 2)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS = AVCC_USBHS = 3.0

to 3.6 V, UCLK = 48 MHz

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Pull-up and pull-

down

characteristics

USB_DP and USB_DM pull-

down resistance in host

controller mode

R_pd

14.25

-

24.80

kΩ

-

90%

V_CRS

USB_DP,

USB_DM

10%

t_LR

10%

t_LF

Figure 2.91

USB_DP and USB_DM output timing in low-speed mode

Observation

point

USB_DP

200 pF to

600 pF

3.6 V

1.5 K

27 

USB_DM

200 pF to

600 pF

Figure 2.92

Table 2.39

Test circuit in low-speed mode

USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS = AVCC_USBHS = 3.0

to 3.6 V, UCLK = 48 MHz

Parameter

Symbol

V_IH

Min

2.0

-

Typ

Max

-

Unit

V

Test conditions

Input

characteristics

Input high voltage

-

Input low voltage

V_IL

0.8

-

V

-

Differential input sensitivity

V_DI

0.2

0.8

V

| USB_DP - USB_DM |

-

Differential common-mode

range

V_CM

2.5

V

Output

characteristics

Output high voltage

Output low voltage

Cross-over voltage

Rise time

V_OH

V_OL

V_CRS

t_LR

2.8

0.0

1.3

4

-

3.6

V

I_OH= -200 μA

I_OL= 2 mA

0.3

V

2.0

V

Figure 2.93

20

ns

%

Ω

Fall time

t_LF

4

20

Rise/fall time ratio

Output resistance

t_LR/ t_LF

90

111.11

44

t_FR/ t_FF

Z_DRV

R_pu

28

USBFS: Rs = 27 Ω included

During idle state

Pull-up and pull- DM pull-up resistance in

down

characteristics

0.900

1.425

1.575

3.090

kΩ

device controller mode

During transmission and

reception

USB_DP and USB_DM pull-

down resistance in host

controller mode

R_pd

14.25

-

24.80

kΩ

-

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2. Electrical Characteristics

90%

V_CRS

USB_DP,

USB_DM

10%

t_FR

10%

t_FF

Figure 2.93

USB_DP and USB_DM output timing in full-speed mode

Observation

point

USB_DP

USB_DM

50 pF

27 

Figure 2.94

Test circuit in full-speed mode

2.5

ADC12 Characteristics

Table 2.40

A/D conversion characteristics for unit 0 (1 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

60

30

-

Unit

MHz

pF

Test conditions

Frequency

1

-

Analog input capacitance

Quantization error

Resolution

-

±0.5

LSB

Bits

μs

-

12

-

Channel-dedicated

sample-and-hold

circuits in use

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

1.06

(0.4 + 0.25)*²

 Sampling of channel-

dedicated sample-and-hold

circuits in 24 states

(AN000 to AN002)

 Sampling in 15 states

Offset error

-

±1.5

±3.5

LSB

AN000 to AN002 = 0.25 V

Full-scale error

AN000 to AN002 =

VREFH0- 0.25 V

Absolute accuracy

-

±2.5

±1.0

±1.5

-

±5.5

±2.0

±3.0

20

LSB

μs

-

DNL differential nonlinearity error

INL integral nonlinearity error

Holding characteristics of sample-and hold

circuits

Dynamic range

0.25

-

VREFH

0 - 0.25

V

-

Channel-dedicated

sample-and-hold

circuits not in use

(AN000 to AN002)

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.48 (0.267)*²

-

μs

Sampling in 16 states

Offset error

-

±1.0

±2.0

±0.5

±1.0

±2.5

±4.5

±1.5

±2.5

LSB

-

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

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2. Electrical Characteristics

Table 2.40

A/D conversion characteristics for unit 0 (2 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

Unit

Test conditions

High-precision

channels

(AN003 to AN007)

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.48 (0.267)*²

-

μs

Sampling in 16 states

Max. = 400 Ω

0.40 (0.183)*²

-

μs

Sampling in 11 states

VCC = AVCC0 = 3.0 to 3.6 V

3.0 V ≤ VREFH0 ≤ AVCC0

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

Normal-precision

channels

Conversion time*¹

(Operation at

Permissible signal

source impedance

0.88 (0.667)*²

Sampling in 40 states

(AN016 to AN020)

PCLKC = 60 MHz)

Max. = 1 kΩ

Offset error

-

±1.0

±2.0

±0.5

±1.0

±5.5

±7.5

±4.5

±5.5

LSB

-

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during

A/D conversion, values might not fall within the indicated ranges.

The use of ports 0 as digital outputs is not allowed when the 12-Bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage is

stable.

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Note 2. Values in parentheses indicate the sampling time.

Table 2.41

A/D conversion characteristics for unit 1 (1 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

60

30

-

Unit

MHz

pF

Test conditions

Frequency

1

-

Analog input capacitance

Quantization error

Resolution

-

±0.5

LSB

Bits

μs

-

12

-

Channel-dedicated

sample-and-hold

circuits in use

Conversion time*¹

(operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

1.06

(0.4 + 0.25)*²

 Sampling of channel-

dedicated sample-and-hold

circuits in 24 states

(AN100 to AN102)

 Sampling in 15 states

Offset error

-

±1.5

±3.5

LSB

AN100 to AN102 = 0.25 V

Full-scale error

AN100 to AN102 =

VREFH - 0.25 V

Absolute accuracy

-

±2.5

±1.0

±1.5

-

±5.5

±2.0

±3.0

20

LSB

μs

-

DNL differential nonlinearity error

INL integral nonlinearity error

Holding characteristics of sample-and hold

circuits

Dynamic range

0.25

-

VREFH -

0.25

V

-

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2. Electrical Characteristics

Table 2.41

A/D conversion characteristics for unit 1 (2 of 2)

Conditions: PCLKC = 1 to 60 MHz

Parameter

Min

Typ

Max

Unit

Test conditions

Channel-dedicated

sample-and-hold

circuits not in use

(AN100 to AN102)

Conversion time*¹

(Operation at

PCLKC = 60 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.48

-

μs

Sampling in 16 states

(0.267)*²

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

High-precision

channels

Conversion time*¹

(Operation at

Permissible signal

source impedance

0.48

(0.267)*²

Sampling in 16 states

(AN103, AN105 to

AN107)

PCLKC = 60 MHz)

Max. = 1 kΩ

Max. = 400 Ω

0.40

(0.183)*²

-

μs

Sampling in 11 states

VCC = AVCC0 = 3.0 to 3.6 V

3.0 V ≤ VREFH ≤ AVCC0

Offset error

-

±1.0

±2.0

±0.5

±1.0

-

±2.5

±4.5

±1.5

±2.5

-

LSB

μs

-

Full-scale error

Absolute accuracy

-

DNL differential nonlinearity error

INL integral nonlinearity error

-

Normal-precision

channels

Conversion time*¹

(Operation at

Permissible signal

source impedance

0.88

(0.667)*²

Sampling in 40 states

(AN116 to AN119)

PCLKC = 60 MHz)

Max. = 1 kΩ

Offset error

-

±1.0

±2.0

±0.5

±1.0

±5.5

±7.5

±4.5

±5.5

LSB

-

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during

A/D conversion, values might not fall within the indicated ranges.

The use of ports 0 as digital outputs is not allowed when the 12-Bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage is

stable.

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Note 2. Values in parentheses indicate the sampling time.

Table 2.42

A/D conversion characteristics for simultaneous using of channel-dedicated sample-and-hold

circuits in unit0 and unit1

Conditions: PCLKC = 30/60 MHz

Parameter

Min

Typ

±1.5

±2.5

±4.0

±1.5

±2.5

±4.0

±1.5

±3.0

±1.5

±3.0

Max

±5.0

±8.0

±5.0

±8.0

±3.5

±5.5

±3.5

±5.5

Test conditions

-

Channel-dedicated sample-and-hold circuits in use

with continious sampling function enabled

(AN000 to AN002)

Offset error

 PCLKC = 60 MHz

 Sampling in 15 states

Full-scale error

Absolute accuracy

Offset error

Channel-dedicated sample-and-hold circuits in use

with continious sampling function enabled

(AN100 to AN102)

Full-scale error

Absolute accuracy

Offset error

Channel-dedicated sample-and-hold circuits in use

with continious sampling function enabled

(AN000 to AN002)

 PCLKC = 30 MHz

 Sampling in 7 states

Full-scale error

Absolute accuracy

Offset error

Channel-dedicated sample-and-hold circuits in use

with continious sampling function enabled

(AN100 to AN102)

Full-scale error

Absolute accuracy

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2. Electrical Characteristics

Note:

When simultaneously using channel-dedicated sample-and-hold circuits in unit0 and unit1, setting the ADSHMSR.SHMD bit to

1 is recommended.

Table 2.43

A/D internal reference voltage characteristics

Parameter

Min

1.13

4.15

Typ

Max

1.23

-

Unit

V

Test conditions

A/D internal reference voltage

Sampling time

1.18

-

μs

FFFh

Full-scale error

Integral nonlinearity

error (INL)

A/D converter

output code

Ideal line of actual A/D

conversion characteristic

Actual A/D conversion

characteristic

Ideal A/D conversion

characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

000h

Offset error

0

Analog input voltage

VREFH0

(full-scale)

Figure 2.95

Illustration of ADC12 characteristic terms

Absolute accuracy

Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the

actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog

input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D

conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference

voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog

input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion

result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D

conversion characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale

errors are zeroed, and the actual output code.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion

characteristics and the width of the actual output code.

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2. Electrical Characteristics

Offset error

Offset error is the difference between the transition point of the ideal first output code and the actual first output code.

Full-scale error

Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.6

DAC12 Characteristics

Table 2.44

D/A conversion characteristics

Parameter

Min

Typ

Max

Unit

Test conditions

Resolution

-

12

Bits

-

Without output amplifier

Absolute accuracy

INL

-

±24

±8.0

±2.0

-

LSB

kΩ

Resistive load 2 MΩ

±2.0

±1.0

8.5

-

Resistive load 2 MΩ

DNL

-

Output impedance

Conversion time

3.0

μs

Resistive load 2 MΩ,

Capacitive load 20 pF

Output voltage range

With output amplifier

INL

0

-

VREFH

V

-

±2.0

±4.0

LSB

μs

-

DNL

-

±1.0

±2.0

Conversion time

Resistive load

Capacitive load

Output voltage range

-

4.0

5

-

kΩ

pF

-

50

0.2

VREFH - 0.2

V

2.7

TSN Characteristics

Table 2.45

Parameter

TSN characteristics

Symbol

Min

Typ

Max

Unit

Test conditions

Relative accuracy

-

±1.0

4.0

1.24

-

°C

-

Temperature slope

-

mV/°C

V

Output voltage (at 25°C)

Temperature sensor start time

Sampling time

-

t_START

-

30

-

μs

4.15

-

μs

2.8

OSC Stop Detect Characteristics

Table 2.46

Oscillation stop detection circuit characteristics

Parameter

Symbol

Min

Typ

Max

Unit

ms

Test conditions

Detection time

t_dr

-

1

Figure 2.96

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2. Electrical Characteristics

Main clock

tdr

OSTDSR.OSTDF

MOCO clock

ICLK

Figure 2.96

Oscillation stop detection timing

2.9

POR and LVD Characteristics

Table 2.47

Parameter

Power-on reset circuit and voltage detection circuit characteristics

Symbol

DPSBYCR.DEEPCUT[1:0] = V_POR

Min

Typ

Max

Unit Test conditions

Voltage detection

level

Power-on reset

(POR)

2.5

2.6

2.7

V

Figure 2.97

00b or 01b

DPSBYCR.DEEPCUT[1:0] =

11b

1.8

2.25

2.7

Voltage detection circuit (LVD0)

Voltage detection circuit (LVD1)

Voltage detection circuit (LVD2)

V_{det0_1}

V_{det0_2}

V_{det0_3}

V_{det1_1}

V_{det1_2}

V_{det1_3}

V_{det2_1}

V_{det2_2}

V_{det2_3}

t_POR

2.84

2.77

2.70

2.89

2.82

2.75

2.89

2.82

2.75

-

2.94

2.87

2.80

2.99

2.92

2.85

2.99

2.92

2.85

4.5

3.04

2.97

2.90

3.09

3.02

2.95

3.09

3.02

2.95

-

Figure 2.98

Figure 2.99

Figure 2.100

Internal reset time Power-on reset time

LVD0 reset time

ms

Figure 2.97

Figure 2.98

Figure 2.99

Figure 2.100

t_LVD0

-

0.51

0.38

-

LVD1 reset time

t_LVD1

-

LVD2 reset time

t_LVD2

-

Minimum VCC down time*¹

t_VOFF

200

-

μs

Figure 2.97,

Figure 2.98

Response delay

t_det

-

200

Figure 2.97 to

Figure 2.100

LVD operation stabilization time (after LVD is enabled)

Hysteresis width (LVD1 and LVD2)

t_d(E-A)

V_LVH

-

10

-

μs

Figure 2.99,

Figure 2.100

70

mV

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR

V_det1, and V_det2for POR and LVD.

,

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2. Electrical Characteristics

t_VOFF

V_POR

VCC

Internal reset signal

(active-low)

t_det

t_POR

t_det

t_dett_POR

Figure 2.97

Power-on reset timing

t_VOFF

VCC

V_det0

Internal reset signal

(active-low)

t_det

t_LVD0

Figure 2.98

Voltage detection circuit timing (V_det0)

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2. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det1

LVCMPCR.LVD1E

t_d(E-A)

LVD1

Comparator output

LVD1CR0.CMPE

LVD1SR.MON

Internal reset signal

(active-low)

When LVD1CR0.RN = 0

t_det

t_LVD1

t_det

When LVD1CR0.RN = 1

t_LVD1

Figure 2.99

Voltage detection circuit timing (V_det1)

t_VOFF

V_LVH

VCC

V_det2

LVCMPCR.LVD2E

t_d(E-A)

LVD2

Comparator output

LVD2CR0.CMPE

LVD2SR.MON

Internal reset signal

(active-low)

When LVD2CR0.RN = 0

t_det

t_LVD2

When LVD2CR0.RN = 1

t_LVD2

Figure 2.100

Voltage detection circuit timing (V_det2)

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2. Electrical Characteristics

2.10 VBATT Characteristics

Table 2.48

Battery backup function characteristics

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.8 to 3.6 V

Parameter

Symbol

V_DETBATT

V_BATTSW

Min

2.50

2.70

Typ

2.60

-

Max

2.70

-

Unit

V

Test conditions

Voltage level for switching to battery backup

Figure 2.101

Lower-limit VBATT voltage for power supply

switching caused by VCC voltage drop

V

VCC-off period for starting power supply switching t_VOFFBATT

200

-

μs

Note:

The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum

value of the voltage level for switching to battery backup (V_DETBATT).

t_VOFFBATT

V_DETBATT

VCC

V_BATT

V_BATTSW

Backup power

area

VCC supply

V_BATTsupply

VCC supply

Figure 2.101

Battery backup function characteristics

2.11 CTSU Characteristics

Table 2.49

Parameter

CTSU characteristics

Symbol

C_tscap

C_base

Σ_IoH

Min

Typ

Max

11

Unit

Test conditions

External capacitance connected to TSCAP pin

TS pin capacitive load

9

-

10

-

nF

pF

mA

-

50

Permissible output high current

-

-40

When the mutual

capacitance method

is applied

2.12 ACMPHS Characteristics

Table 2.50

Parameter

ACMPHS characteristics

Symbol

VREF

VI

Min

Typ

-

Max

Unit

V

Test conditions

Reference voltage range

Input voltage range

Output delay*¹

0

AVCC0

100

-

0

-

V

-

Td

-

50

1.18

ns

V

VI = VREF ± 100 mV

-

Internal reference voltage

Vref

1.13

1.23

Note 1. This value is the internal propagation delay.

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2. Electrical Characteristics

2.13 PGA Characteristics

Table 2.51

PGA characteristics in single mode

Parameter

Symbol

Min

Typ

Max

Unit

PGAVSS input voltage range

PGAVSS

0

-

0

V

AIN0 (G = 2.000)

AIN1 (G = 2.500)

AIN2 (G = 2.667)

AIN3 (G = 2.857)

AIN4 (G = 3.077)

AIN5 (G = 3.333)

AIN6 (G = 3.636)

AIN7 (G = 4.000)

AIN8 (G = 4.444)

AIN9 (G = 5.000)

AIN10 (G = 5.714)

AIN11 (G = 6.667)

AIN12 (G = 8.000)

AIN13 (G = 10.000)

AIN14 (G = 13.333)

Gerr0 (G = 2.000)

Gerr1 (G = 2.500)

Gerr2 (G = 2.667)

Gerr3 (G = 2.857)

Gerr4 (G = 3.077)

Gerr5 (G = 3.333)

Gerr6 (G = 3.636)

Gerr7 (G = 4.000)

Gerr8 (G = 4.444)

Gerr9 (G = 5.000)

Gerr10 (G = 5.714)

Gerr11 (G = 6.667)

Gerr12 (G = 8.000)

Gerr13 (G = 10.000)

Gerr14 (G = 13.333)

Voff

0.050 × AVCC0

0.047 × AVCC0

0.046 × AVCC0

0.045 × AVCC0

0.044 × AVCC0

0.042 × AVCC0

0.040 × AVCC0

0.036 × AVCC0

0.033 × AVCC0

0.031 × AVCC0

0.029 × AVCC0

0.027 × AVCC0

0.025 × AVCC0

0.023 × AVCC0

-1.0

0.45 × AVCC0

V

0.360 × AVCC0

V

0.337 × AVCC0

V

0.32 × AVCC0

V

0.292 × AVCC0

V

0.265 × AVCC0

V

0.247 × AVCC0

V

0.212 × AVCC0

V

0.191 × AVCC0

V

0.17 × AVCC0

V

0.148 × AVCC0

V

0.127 × AVCC0

V

0.09 × AVCC0

V

0.08 × AVCC0

V

0.06 × AVCC0

V

Gain error

1.0

1.5

2.0

8

%

mV

-1.0

-1.5

-2.0

Offset error

-8

Table 2.52

Parameter

PGA characteristics in differential mode (1 of 2)

Symbol

Min

-0.5

-0.4

-0.2

-0.15

Typ

Max

0.3

Unit

V

PGAVSS input voltage range

PGAVSS

-

Differential input

voltage range

G = 1.500

AIN-PGAVSS

0.5

V

G = 2.333

G = 4.000

G = 5.667

0.4

V

0.2

V

0.15

V

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2. Electrical Characteristics

Table 2.52

PGA characteristics in differential mode (2 of 2)

Symbol

Parameter

Min

-1.0

Typ

Max

1.0

Unit

Gain error

G = 1.500

G = 2.333

G = 4.000

G = 5.667

Gerr

-

%

2.14 Flash Memory Characteristics

2.14.1

Code Flash Memory Characteristics

Table 2.53

Code flash memory characteristics

Conditions: Program or erase: FCLK = 4 to 60 MHz

Read: FCLK ≤ 60 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Test

Parameter

Symbol

t_P128

t_P8K

Min

Typ

0.75

49

Max

13.2

Min

Typ

0.34

22

Max

6.0

80

Unit

ms

Times

μs

conditions

Programming time

N_PEC 100 times

128-byte

8-KB

-

176

704

15.8

212

848

216

864

260

1040

-

32-KB

128-byte

8-KB

t_P32K

t_P128

t_P8K

-

194

0.91

60

-

88

320

7.2

96

Programming time

-

0.41

27

N_PEC> 100 times

-

32-KB

8-KB

t_P32K

t_E8K

t_E32K

t_E8K

t_E32K

N_PEC

-

234

78

-

106

43

384

120

480

144

576

-

Erasure time

N_PEC 100 times

-

32-KB

8-KB

-

283

94

-

157

52

Erasure time

-

N_PEC> 100 times

32-KB

-

341

-

189

-

Reprogramming/erasure cycle*^Note:

10000*¹

Suspend delay during programming t_SPD

-

264

216

-

120

First suspend delay during erasure in t_SESD1

suspend priority mode

-

μs

Second suspend delay during

erasure in suspend priority mode

t_SESD2

-

1.7

-

1.7

ms

Suspend delay during erasure in

erasure priority mode

t_SEED

Forced stop command

Data hold time*²

t_FD

-

32

-

20

-

μs

3

t_DRP

10*^2,

30*^2,

*

10*^2,

30*^2,

*

Years

3

*

-

*

-

Ta = +85°C

Note:

The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),

erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different

addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address several times as one erasure is not enabled. (Overwriting is prohibited.)

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1

to the minimum value.

Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 3. This result is obtained from reliability testing.

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RA6M3 Group

2. Electrical Characteristics

• Suspension during programming

FCU command

Program

Ready

Suspend

t_SPD

FSTATR0.FRDY

Not Ready

Ready

Programming pulse

Programming

• Suspension during erasure in suspend priority mode

FCU command

Erase

Suspend

Not Ready

Erasing

Resume

t_SESD1

t_SESD2

FSTATR0.FRDY

Erasure pulse

Ready

Not Ready

Erasing

• Suspension during erasure in erasure priority mode

FCU command

FSTATR0.FRDY

Erasure pulse

Erase

Suspend

Not Ready

Erasing

t_SEED

Ready

• Forced Stop

Forced Stop

Not Ready

FACI command

t_FD

FSTATR.FRDY

Ready

Figure 2.102

Suspension and forced stop timing for flash memory programming and erasure

2.14.2

Data Flash Memory Characteristics

Table 2.54

Data flash memory characteristics (1 of 2)

Conditions: Program or erase: FCLK = 4 to 60 MHz

Read: FCLK ≤ 60 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Test

Parameter

Symbol

t_DP4

Min

Typ

0.36

0.38

0.42

3.1

4.7

8.9

-

Max

Min

Typ

0.16

0.17

0.19

1.7

2.6

4.9

-

Max

1.7

1.8

2.0

10

15

28

30

-

Unit

conditions

Programming time

4-byte

-

3.8

4.0

4.5

18

27

50

84

-

ms

8-byte

t_DP8

-

16-byte

64-byte

128-byte

256-byte

4-byte

t_DP16

-

Erasure time

t_DE64

-

ms

t_DE128

t_DE256

t_DBC4

N_DPEC

-

Blank check time

-

μs

Reprogramming/erasure cycle*¹

125000

-

125000

-

2

*

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Page 101 of 116

RA6M3 Group

2. Electrical Characteristics

Table 2.54

Data flash memory characteristics (2 of 2)

Conditions: Program or erase: FCLK = 4 to 60 MHz

Read: FCLK ≤ 60 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Test

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

120

300

390

570

300

390

570

20

Unit

conditions

Suspend delay during

programming

4-byte

t_DSPD

-

264

216

300

390

570

300

390

570

32

-

μs

8-byte

-

16-byte

64-byte

128-byte

256-byte

-

First suspend delay

during erasure in

suspend priority mode

t_DSESD1

t_DSESD2

t_DSEED

-

μs

-

Second suspend delay 64-byte

during erasure in

suspend priority mode

-

128-byte

-

256-byte

-

Suspend delay during

erasing in erasure

priority mode

64-byte

-

128-byte

256-byte

-

Forced stop command

Data hold time*³

t_FD

-

μs

t_DRP

10*^3,*⁴

30*^3,*⁴

-

10*^3,*⁴

30*^3,*⁴

-

Year

-

Ta = +85°C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),

erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different

addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address several times as one erasure is not enabled. (Overwriting is prohibited.)

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1

to the minimum value.

Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 4. This result is obtained from reliability testing.

2.15 Boundary Scan

Table 2.55

Parameter

Boundary scan characteristics

Symbol

Test

conditions

Min

100

45

-

Typ

Max

Unit

ns

-

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TMS setup time

t_TCKcyc

t_TCKH

t_TCKL

t_TCKr

-

Figure 2.103

Figure 2.104

Figure 2.105

-

5

-

t_TCKf

-

t_TMSS

t_TMSH

t_TDIS

20

-

TMS hold time

-

TDI setup time

-

TDI hold time

t_TDIH

-

TDO data delay

t_TDOD

T_BSSTUP

40

-

Boundary scan circuit startup time*¹

t_RESWP

Note 1. Boundary scan does not function until the power-on reset becomes negative.

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 102 of 116

RA6M3 Group

2. Electrical Characteristics

t_TCKcyc

t_TCKH

t_TCKf

TCK

t_TCKr

t_TCKL

Figure 2.103

Boundary scan TCK timing

TCK

TMS

TDI

t_TMSS

t_TMSH

t_TDIS

t_TDIH

t_TDOD

TDO

Figure 2.104

Boundary scan input/output timing

VCC

RES

t_BSSTUP

₍₌t_RESWP)

Boundary scan

execute

Figure 2.105

Boundary scan circuit startup timing

2.16 Joint Test Action Group (JTAG)

Table 2.56

Parameter

JTAG

Test

conditions

Symbol

t_TCKcyc

t_TCKH

t_TCKL

Min

Typ

Max

Unit

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

40

15

-

ns

Figure 2.103

-

t_TCKr

5

TCK clock fall time

t_TCKf

-

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 103 of 116

RA6M3 Group

2. Electrical Characteristics

Table 2.56

JTAG

Test

Parameter

Symbol

t_TMSS

t_TMSH

t_TDIS

Min

8

Typ

Max

Unit

conditions

TMS setup time

TMS hold time

TDI setup time

TDI hold time

-

ns

Figure 2.104

8

-

8

-

t_TDIH

8

-

TDO data delay time

t_TDOD

-

20

t_TCKcyc

t_TCKH

TCK

t_TCKf

t_TCKr

t_TCKL

Figure 2.106

JTAG TCK timing

TCK

t_TMSS

t_TMSH

TMS

t_TDIS

t_TDIH

TDI

t_TDOD

TDO

Figure 2.107

JTAG input/output timing

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 104 of 116

RA6M3 Group

2. Electrical Characteristics

2.17 Serial Wire Debug (SWD)

Table 2.57

Parameter

SWD

Test

conditions

Symbol

t_SWCKcyc

t_SWCKH

t_SWCKL

t_SWCKr

t_SWCKf

t_SWDS

Min

40

15

-

Typ

Max

Unit

SWCLK clock cycle time

SWCLK clock high pulse width

SWCLK clock low pulse width

SWCLK clock rise time

SWCLK clock fall time

SWDIO setup time

-

ns

Figure 2.108

-

5

-

8

Figure 2.109

SWDIO hold time

t_SWDH

8

-

SWDIO data delay time

t_SWDD

2

28

t_SWCKcyc

t_SWCKH

SWCLK

t_SWCKL

Figure 2.108

SWD SWCLK timing

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 105 of 116

RA6M3 Group

2. Electrical Characteristics

SWCLK

t_SWDS

t_SWDH

SWDIO

(Input)

t_SWDD

SWDIO

(Output)

SWDIO

(Output)

SWDIO

(Output)

Figure 2.109

SWD input/output timing

2.18 Embedded Trace Macro Interface (ETM)

Table 2.58

ETM

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.

Test

Parameter

Symbol

t_TCLKcyc

t_TCLKH

t_TCLKL

t_TCLKr

Min

33.3

13.6

-

Typ

Max

Unit

conditions

TCLK clock cycle time

TCLK clock high pulse width

TCLK clock low pulse width

TCLK clock rise time

-

ns

Figure 2.110

-

3

-

TCLK clock fall time

t_TCLKf

-

TDATA[3:0] output setup time

TDATA[3:0] output hold time

t_TRDS

3.5

2.5

Figure 2.111

t_TRDH

-

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Dec 25, 2020

Page 106 of 116

RA6M3 Group

2. Electrical Characteristics

t_TCLKcyc

t_TCLKH

TCLK

t_TCLKf

t_TCLKr

t_TCLKL

Figure 2.110

ETM TCLK timing

TCLK

t_TRDS

t_TRDH

t_TRDS

t_TRDH

TDATA[3:0]

Figure 2.111

ETM output timing

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 107 of 116

RA6M3 Group

Appendix 1. Package Dimensions

Appendix 1.Package Dimensions

For information on the latest version of the package dimensions or mountings, go to “Packages” on the Renesas

Electronics Corporation website.

JEITA Package Code

RENESAS Code

PLBG0176GE-A

Previous Code

176FHS-A

MASS (TYP.)

0.45 g

P-LFBGA176-13x13-0.80

D

w S A

w S B

x4

v

y₁

S

y

S

Z _D

e

A

Dimension in Millimeters

Reference

Symbol

Min

Nom

13.0

Max

D

E

v

R

P

N

M

L

0.15

0.20

1.40

0.45

w

A

B

K

J

H

G

F

A

e

b

x

0.35

0.45

0.40

0.80

0.50

1

E

D

C

B

A

0.55

0.08

0.10

0.2

y

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

S

D

E

D

E

b

S A B

x M

Z

0.90

Figure 1.1

176-pin BGA

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 108 of 116

RA6M3 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS[Typ.]

1.8g

P-LFQFP176-24x24-0.50

PLQP0176KB-A 176P6Q-A/FP-176E/FP-176EV

H_D

*1

D

132

89

133

88

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

b_p

b₁

Dimension in Millimeters

Reference

Symbol

Terminal cross section

Min Nom Max

D

23.9 24.0 24.1

1.4

E

A₂

H_D

H_E

25.8 26.0 26.2

1.7

176

45

A

A₁

b_p

0.05 0.1 0.15

0.15 0.20 0.25

0.18

1

44

Index mark

F

Z_D

b₁

c

c₁

S

0.09 0.145 0.20

0.125

L

θ

e

0°

8°

L₁

*3

0.5

y

S

b_p

e

x

M

x

0.08

0.10

Detail F

y

Z_D

Z_E

1.25

0.35 0.5 0.65

1.0

L

L₁

Figure 1.2

176-pin LQFP

JEITA Package Code

P-TFLGA145-7x7-0.50

RENESAS Code

PTLG0145KA-A

Previous Code

145F0G

MASS[Typ.]

0.1g

φb₁

φ

M

S AB

φb

φ

M

S AB

D

w

S A

Z_D

e

A

N

M

L

K

J

H

G

F

B

E

D

C

B

A

Dimension in Millimeters

Reference

Symbol

1

2

3

4

5

6

7

8

9

10 11 12 13

y

S

x4

Min

Nom Max

7.0

v

Index mark

D

E

S

(Laser mark)

7.0

v

0.15

w

A

0.20

1.05

e

0.5

b

0.21 0.25 0.29

b₁

x

0.29 0.34 0.39

0.08

y

Z_D

Z_E

0.5

Figure 1.3

145-pin LGA

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 109 of 116

RA6M3 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

1.2

P-LFQFP144-20x20-0.50

PLQP0144KA-B

—

H_D

D

Unit: mm

*1

108

73

109

72

144

37

NOTE 4

1

36

NOTE)

Index area

NOTE 3

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

F

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Dimensions in millimeters

Min Nom Max

Reference

Symbol

*3

b

e

p

M

y

S

D

E

A₂

H_D

H_E

A

A₁

b_p

c

19.9

20.0 20.1

1.4

21.8

22.0 22.2

1.7

0.15

0.05

0.17

0.09

0q

0.20 0.27

3.5q

0.5

0.20

8q

T

L_p

L₁

e

x

y

L_p

L₁

0.08

0.ꢀꢁ

0.75

Detail F

0.45

0.6

1.0

Figure 1.4

144-pin LQFP

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 110 of 116

RA6M3 Group

Appendix 1. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

0.6

P-LFQFP100-14x14-0.50

PLQP0100KB-B

—

H_D

Unit: mm

*1

D

75

51

76

50

100

26

1

25

NOTE 4

NOTE)

Index area

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

NOTE 3

F

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Dimensions in millimeters

Min Nom Max

Reference

Symbol

y

S

*3

b

p

e

M

D

E

A₂

H_D

H_E

A

A₁

b_p

c

13.9

14.0 14.1

1.4

15.8

16.0 16.2

1.7

0.15

0.05

0.15

0.09

0q

0.20 0.27

3.5q

0.5

0.20

8q

L_p

L₁

T

e

x

y

L_p

L₁

Detail F

0.08

0.75

0.45

0.6

1.0

Figure 1.5

100-pin LQFP

R01DS0358EJ0110 Rev.1.10

Dec 25, 2020

Page 111 of 116

Revision History

RA6M3 Group Datasheet

Rev.

1.00

1.10

Date

Summary

Oct 8, 2019

First Edition issued

Dec 25, 2020 Second Edition issued

Proprietary Notice

All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in

this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and

trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no

part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated,

transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior

written consent from Renesas.

Arm^®and Cortex^®are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.

CoreMark^®is a registered trademark of the Embedded Microprocessor Benchmark Consortium.

Magic Packet™ is a trademark of Advanced Micro Devices, Inc.

SuperFlash^®is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States

and Japan.

Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective

holders.

Colophon

RA6M3 Group Datasheet

Publication Date:

Published by:

Rev.1.10

Dec 25, 2020

Renesas Electronics Corporation

Address List

General Precautions in the Handling of Microprocessing Unit and Microcontroller

Unit Products

The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage

notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have

been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps

must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be

adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.

Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be

touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.

2. Processing at power-on

The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of

register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset

pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins

in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the

level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O

pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.

Follow the guideline for input signal during power-off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are

generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of

the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal

become possible.

5. Clock signals

After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program

execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator

during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced

with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V_IL(Max.)

and V_IH(Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level

is fixed, and also in the transition period when the input level passes through the area between V_IL(Max.) and V_IH(Min.).

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these

addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.

The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms

of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,

operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-

evaluation test for the given product.

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products

and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your

product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of

these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or

other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this

document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

others.

4. You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export,

manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required.

5. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any

and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.

6. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for

each Renesas Electronics product depends on the product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home

electronic appliances; machine tools; personal electronic equipment; industrial robots; etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key

financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas

Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to

human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system;

undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims

any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is

inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.

7. No semiconductor product is absolutely secure. Notwithstanding any security measures or features that may be implemented in Renesas Electronics

hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or security breach, including but not

limited to any unauthorized access to or use of a Renesas Electronics product or a system that uses a Renesas Electronics product. RENESAS

ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING

RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE,

HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (“Vulnerability Issues”). RENESAS ELECTRONICS DISCLAIMS ANY AND

ALL RESPONSIBILITY OR LIABILITY ARISING FROM OR RELATED TO ANY VULNERABILITY ISSUES. FURTHERMORE, TO THE EXTENT

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RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE, INCLUDING BUT NOT LIMITED TO

THE IMPLIED WARRANTIES OF MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.

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Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by

Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas

Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such

specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific

characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability

product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products

are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury,

injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety

design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging

degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are

responsible for evaluating the safety of the final products or systems manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas

Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of

controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these

applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance

with applicable laws and regulations.

11. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is

prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations

promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions.

12. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or

transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document.

13. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.

14. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas

Electronics products.

(Note1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled

subsidiaries.

(Note2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(Rev.5.0-1 October 2020)

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Corporation. All trademarks and registered trademarks are the property

of their respective owners.

Back cover

RA6M3 Group

R01DS0358EJ0110


型号：	R7FA6M3AH3CFC
厂家：	RENESAS TECHNOLOGY CORP
描述：	Leading performance 120-MHz Arm Cortex-M4 core, up to 2-MB code flash memory
文件：	总116页 (文件大小：1507K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R7FA6M3AH3CFC [RENESAS]

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