R7FA6M4AE3CFP_技术文档

Datasheet

R01DS0365EJ0110

Rev.1.10

RA6M4 Group

Renesas Microcontrollers

Sep 29, 2020

High-performance 200 MHz Arm Cortex-M33 core, up to 1 MB code flash memory with Dual-bank, background and SWAP

operation, 8 KB Data flash memory, and 256 KB SRAM with Parity/ECC. High-integration with Ethernet MAC controller, USB

2.0 Full-Speed, SDHI, Quad and Octa SPI, and advanced analog. Integrated Secure Crypto Engine with cryptography

accelerators, key management support, tamper detection and power analysis resistance in concert with Arm TrustZone for

integrated secure element functionality.

Features

®

● DMA Controller (DMAC) × 8

● Power-on reset

■

Arm Cortex -M33 Core

● Armv8-M architecture with the main extension

● Maximum operating frequency: 200 MHz

● Arm Memory Protection Unit (Arm MPU)

– Protected Memory System Architecture (PMSAv8)

– Secure MPU (MPU_S): 8 regions

– Non-secure MPU (MPU_NS): 8 regions

● SysTick timer

– Embeds two Systick timers: Secure and Non-secure instance

– Driven by LOCO or system clock

● CoreSight ETM-M33

● Low Voltage Detection (LVD) with voltage settings

● Watchdog Timer (WDT)

● Independent Watchdog Timer (IWDT)

■ Human Machine Interface (HMI)

● Capacitive Touch Sensing Unit (CTSU)

■ Multiple Clock Sources

™

● Main clock oscillator (MOSC) (8 to 24 MHz)

● Sub-clock oscillator (SOSC) (32.768 kHz)

● High-speed on-chip oscillator (HOCO) (16/18/20 MHz)

● Middle-speed on-chip oscillator (MOCO) (8 MHz)

● Low-speed on-chip oscillator (LOCO) (32.768 kHz)

● IWDT-dedicated on-chip oscillator (15 kHz)

● Clock trim function for HOCO/MOCO/LOCO

● PLL/PLL2

■ Memory

● Up to 1-MB code flash memory

● 8-KB data flash memory (100,000 program/erase (P/E) cycles)

● 256-KB SRAM

■ Connectivity

● Clock out support

● Serial Communications Interface (SCI) × 10

– Asynchronous interfaces

– 8-bit clock synchronous interface

– Smart card interface

■ General-Purpose I/O Ports

● 5-V tolerance, open drain, input pull-up, switchable driving ability

– Simple IIC

■ Operating Voltage

● VCC: 2.7 to 3.6 V

– Simple SPI

– Manchester coding (SCI3, SCI4)

2

● I C bus interface (IIC) × 2

■ Operating Temperature and Packages

● Ta = -40℃ to +105℃

● Serial Peripheral Interface (SPI) × 2

● Quad Serial Peripheral Interface (QSPI)

● Octa Serial Peripheral Interface (OSPI)

● USB 2.0 Full-Speed Module (USBFS)

● Control Area Network module (CAN) × 2

● Ethernet MAC/DMA Controller (ETHERC/EDMAC)

● SD/MMC Host Interface (SDHI)

– 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)

– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)

– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)

● Serial Sound Interface Enhanced (SSIE)

■ Analog

● 12-bit A/D Converter (ADC12) × 2

● 12-bit D/A Converter (DAC12) × 2

● Temperature Sensor (TSN)

■ Timers

● General PWM Timer 32-bit (GPT32) × 4

● General PWM Timer 16-bit (GPT16) × 6

● Low Power Asynchronous General Purpose Timer (AGT) × 6

■ Security and Encryption

● Secure Crypto Engine 9

– Symmetric algorithms: AES

– Asymmetric algorithms: RSA, ECC, and DSA

– Hash-value generation: SHA224, SHA256, GHASH

– 128-bit unique ID

®

● Arm TrustZone

– Up to three or six regions for the code flash, depending on the

bank mode

– Up to two regions for the data flash

– Up to three regions for the SRAM

– Individual secure or non-secure security attribution for each

peripheral

● Device lifecyle management

● Pin function

– Up to three tamper pins

– Secure pin multiplexing

■ System and Power Management

● Low power modes

● Battery backup function (VBATT)

● Realtime Clock (RTC) with calendar and VBATT support

● Event Link Controller (ELC)

● Data Transfer Controller (DTC)

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 1 of 109

RA6M4 Datasheet

1. Overview

1.

Overview

®

The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of

Renesas peripherals to facilitate design scalability and efficient platform-based product development.

®

The MCU in this series incorporates a high-performance Arm Cortex -M33 core running up to 200 MHz with the following

features:

● Up to 1 MB code flash memory

● 256 KB SRAM

● Quad Serial Peripheral Interface (QSPI), Octa Serial Peripheral Interface (OSPI)

● Ethernet MAC Controller (ETHERC), USBFS, SD/MMC Host Interface

● Capacitive Touch Sensing Unit (CTSU)

● Analog peripherals

● Security and safety features

1.1

Function Outline

Table 1.1

Feature

Arm core

Functional description

Arm Cortex-M33 core

●

Maximum operating frequency: up to 200 MHz

Arm Cortex-M33 core:

–

Armv8-M architecture with security extension

Revision: r0p4-00rel0

●

Arm Memory Protection Unit (Arm MPU)

–

Protected Memory System Architecture (PMSAv8)

Secure MPU (MPU_S): 8 regions

Non-secure MPU (MPU_NS): 8 regions

●

SysTick timer

–

Embeds two Systick timers: Secure and Non-secure instance

Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)

™

CoreSight ETM-M33

Table 1.2

Memory

Feature

Functional description

Code flash memory

Data flash memory

Option-setting memory

SRAM

Maximum 1 MB of code flash memory.

8 KB of data flash memory.

The option-setting memory determines the state of the MCU after a reset.

On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).

Table 1.3

System (1 of 2)

Functional description

Operating modes

Two operating modes:

●

Single-chip mode

SCI/USB boot mode

Resets

The MCU provides 14 resets.

Low Voltage Detection (LVD)

The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The

detection level can be selected by register settings. The LVD module consists of three separate

voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level

input to the VCC pin. LVD registers allow your application to configure detection of VCC changes

at various voltage thresholds.

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Sep 29, 2020

Page 2 of 109

RA6M4 Datasheet

1. Overview

Table 1.3

System (2 of 2)

Functional description

Clocks

●

Main clock oscillator (MOSC)

Sub-clock oscillator (SOSC)

High-speed on-chip oscillator (HOCO)

Middle-speed on-chip oscillator (MOCO)

Low-speed on-chip oscillator (LOCO)

IWDT-dedicated on-chip oscillator

PLL/PLL2

Clock out support

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock selected as the

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.When measurement is

complete or the number of pulses within the time generated by the measurement reference clock

is not within the allowable range, an interrupt request is generated.

Interrupt Controller Unit (ICU)

Low power modes

The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector

Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)

modules. The ICU also controls non-maskable interrupts.

Power consumption can be reduced in multiple ways, including setting clock dividers, stopping

modules, selecting power control mode in normal operation, and transitioning to low power

modes.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery-powered area

includes the RTC, SOSC, backup memory, and switch between VCC and VBATT.

Register write protection

Memory Protection Unit (MPU)

The register write protection function protects important registers from being overwritten due to

software errors. The registers to be protected are set with the Protect Register (PRCR).

The MCU has one Memory Protection Unit (MPU).

Table 1.4

Feature

Event link

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the event requests generated by various peripheral

modules as source signals to connect them to different modules, allowing direct link between the

modules without CPU intervention.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request.

DMA Controller (DMAC)

The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data

without intervention from the CPU. When a DMA transfer request is generated, the DMAC

transfers data stored at the transfer source address to the transfer destination address.

Table 1.6

Feature

External bus interface

Functional description

External buses

●

CS area (ECBIU): Connected to the external devices (external memory interface)

QSPI area (EQBIU): Connected to the QSPI (external device interface)

OSPI area (EOBIU): Connected to the OSPI (external device interface)

Table 1.7

Feature

Timers (1 of 2)

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with

GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-

counter, or the up- and down-counter. In addition, PWM waveforms can be generated for

controlling brushless DC motors. The GPT can also be used as a general-purpose timer.

Port Output Enable for GPT (POEG)

The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins

in the output disable state

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Sep 29, 2020

Page 3 of 109

RA6M4 Datasheet

1. Overview

Table 1.7

Feature

Timers (2 of 2)

Functional description

Low power Asynchronous General

Purpose Timer (AGT)

The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used

for pulse output, external pulse width or period measurement, and counting external events. This

timer consists of a reload register and a down counter. The reload register and the down counter

are allocated to the same address, and can be accessed with the AGT register.

Realtime Clock (RTC)

The realtime clock (RTC) has two counting modes, calendar count mode and binary count mode,

that are used by switching register settings. For calendar count mode, the RTC has a 100-year

calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count

mode, the RTC counts seconds and retains the information as a serial value. Binary count mode

can be used for calendars other than the Gregorian (Western) calendar.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow

interrupt.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the

MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer

operates with an independent, dedicated clock source, it is particularly useful in returning the

MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT

can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value

in the registers.

Table 1.8

Communication interfaces (1 of 2)

Feature

Functional description

Serial Communications Interface (SCI)

The Serial Communications Interface (SCI) × 10 channels have asynchronous and synchronous

serial interfaces:

●

Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter

(ACIA))

●

8-bit clock synchronous interface

Simple IIC (master-only)

Simple SPI

Smart card interface

Manchester interface

Extended Serial interface

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol. SCIn (n = 0, 3 to 9) has FIFO buffers to enable continuous and full-duplex

communication, and the data transfer speed can be configured independently using an on-chip

baud rate generator.

2

I C bus interface (IIC)

The I C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset

2

of the NXP I C (Inter-Integrated Circuit) bus interface functions.

Serial Peripheral Interface (SPI)

Control Area Network (CAN)

The Serial Peripheral Interface (SPI) provides high-speed full-duplex synchronous serial

communications with multiple processors and peripheral devices.

The Controller Area Network (CAN) module uses a message-based protocol to receive and

transmit data between multiple slaves and masters in electromagnetically noisy applications. The

module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32

mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO

modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN

module requires an additional external CAN transceiver.

USB 2.0 Full-Speed module (USBFS)

The USB 2.0 Full-Speed module (USBFS) can operate as a host controller or device controller.

The module supports full-speed and low-speed (host controller only) transfer as defined in

Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and

supports all of the transfer types defined in Universal Serial Bus Specification 2.0. The USB has

buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned

any endpoint number based on the peripheral devices used for communication or based on your

system.

Quad Serial Peripheral Interface (QSPI) The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM

(nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has

an SPI-compatible interface.

Octa Serial Peripheral Interface (OSPI) The Octa Serial Peripheral Interface (OSPI) module is a memory controller for connecting

OctaFlash and OctaRAM.

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RA6M4 Datasheet

1. Overview

Table 1.8

Feature

Communication interfaces (2 of 2)

Functional description

Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with

2

digital audio devices for transmitting I S/Monaural/TDM audio data over a serial bus. The SSIE

supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master

receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage

FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data

reception and transmission.

SD/MMC Host Interface (SDHI)

The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to

connect a variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit

buses for connecting memory cards that support SD, SDHC, and SDXC formats. When

developing host devices that are compliant with the SD Specifications, you must comply with the

SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports 1-bit, 4-

bit, and 8-bit1-bit, and 4-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-

B451) device access. This interface also provides backward compatibility and supports high-

speed SDR transfer modes.

Ethernet MAC (ETHERC)

One-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3 Media

Access Control (MAC) layer protocol. An ETHERC channel provides one channel of the MAC

layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows transmission

and reception of frames compliant with the Ethernet and IEEE802.3 standards. The ETHERC is

connected to the Ethernet DMA Controller (EDMAC) so data can be transferred without using

the CPU.

Table 1.9

Analog

Functional description

12-bit A/D Converter (ADC12)

A 12-bit successive approximation A/D converter is provided. Up to 22 analog input channels are

selectable. Temperature sensor output and internal reference voltage are selectable for

conversion.

12-bit D/A Converter (DAC12)

Temperature Sensor (TSN)

A 12-bit D/A converter (DAC12) is provided.

The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable

operation of the device. The sensor outputs a voltage directly proportional to the die

temperature, and the relationship between the die temperature and the output voltage is fairly

linear. The output voltage is provided to the ADC12 for conversion and can be further used by

the end application.

Table 1.10

Feature

Human machine interfaces

Functional description

Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch

sensor. Changes in the electrostatic capacitance are determined by software that enables the

CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the

touch sensor is usually enclosed with an electrical conductor so that a finger does not come into

direct contact with the electrode.

Table 1.11

Feature

Data processing

Functional description

Cyclic Redundancy Check (CRC)

calculator

The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the

data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first

communication. Additionally, various CRC-generation polynomials are available.

Data Operation Circuit (DOC)

The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected

condition applies, 16-bit data is compared and an interrupt can be generated.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 5 of 109

RA6M4 Datasheet

1. Overview

1.2

Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the

features.

Memory

Bus

External

CSC

Arm Cortex-M33

System

Clocks

DSP

FPU

1 MB code flash

POR/LVD

Reset

MOSC/SOSC

(H/M/L) OCO

PLL/PLL2

8 KB data flash

256 KB SRAM

IDAU

MPU

Mode control

1 KB Standby

SRAM

NVIC

Power control

ICU

CAC

DMA

DTC

System timer

Battery backup

Test and DBG interface

Register write

protection

DMAC × 8

Timers

Communication interfaces

Human machine interfaces

CTSU

QSPI

OSPI

SCI × 10

GPT32 x 4

GPT16 x 6

ETHERC

IIC × 2

SDHI

AGT × 6

RTC

SPI × 2

CAN × 2

SSIE

USBFS

WDT/IWDT

Event link

ELC

Data processing

Analog

TSN

CRC

ADC12 × 2

DOC

DAC12 × 2

Security

SCE9

Note:

Figure 1.1

1.3

Not available on all parts.

Block diagram

Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a

list of products.

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RA6M4 Datasheet

1. Overview

# A A

R 7 F A 6 M 4 A F 3 C F B

0

Production identification code

Packaging, Terminal material (Pb-free)

#AA: Tray/Sn (Tin) only

#AC: Tray/others

Package type

FB: LQFP 144 pins

FP: LQFP 100 pins

FM: LQFP 64 pins

Quality Grade

Operating temperature

3: -40^°C to 105^°C

Code flash memory size

D: 512 KB

E: 768 KB

F: 1 MB

Feature set

Group number

Series name

RA family

Flash memory

Renesas microcontroller

Figure 1.2

Table 1.12

Part numbering scheme

Product list

Data

flash

Operating

temperature

Product part number

Package code

PLQP0144KA-B

PLQP0100KB-B

PLQP0064KB-C

PLQP0144KA-B

PLQP0100KB-B

PLQP0064KB-C

PLQP0144KA-B

PLQP0100KB-B

PLQP0064KB-C

Code flash

SRAM

R7FA6M4AF3CFB

R7FA6M4AF3CFP

R7FA6M4AF3CFM

R7FA6M4AE3CFB

R7FA6M4AE3CFP

R7FA6M4AE3CFM

R7FA6M4AD3CFB

R7FA6M4AD3CFP

R7FA6M4AD3CFM

1 MB

8 KB

256 KB

-40 to +105°C

768 KB

512 KB

256 KB

-40 to +105°C

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RA6M4 Datasheet

1. Overview

1.4

Function Comparison

Table 1.13

Function Comparison (1 of 2)

R7FA6M4AF3CFB

R7FA6M4AE3CFB

R7FA6M4AD3CFB

R7FA6M4AF3CFP

R7FA6M4AE3CFP

R7FA6M4AD3CFP

R7FA6M4AF3CFM

R7FA6M4AE3CFM

R7FA6M4AD3CFM

Parts number

Pin count

144

100

64

Package

LQFP

Code flash memory

1 MB

768 KB

512 KB

Data flash memory

SRAM

8 KB

256 KB

192 KB

64 KB

Parity

ECC

Standby SRAM

DMA

1 KB

DTC

Yes

DMAC

8

BUS

External bus

CPU clock

CPU clock sources

CAC

16-bit bus

8-bit bus

200 MHz (max.)

No

System

MOSC, SOSC, HOCO, MOCO, LOCO, PLL

Yes

WDT/IWDT

Backup register

SCI

Yes

128 B

Communication

10

8

IIC

2

SPI

2

CAN

2

USBFS

QSPI

Yes

OSPI

Yes

4

No

SSIE

SDHI/MMC

ETHERC

*1

Timers

Analog

GPT32

*1

6

GPT16

*1

AGT

RTC

Yes

ADC12

Unit 0: 12

Unit 1: 10

Unit 0: 11

Unit 1: 9

Unit 0: 7

Unit 1: 4

DAC12

TSN

2

Yes

12

HMI

CTSU

CRC

DOC

ELC

20

7

Data processing

Yes

Event control

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 8 of 109

RA6M4 Datasheet

1. Overview

Table 1.13

Function Comparison (2 of 2)

R7FA6M4AF3CFB

R7FA6M4AE3CFB

R7FA6M4AD3CFB

R7FA6M4AF3CFP

R7FA6M4AE3CFP

R7FA6M4AD3CFP

R7FA6M4AF3CFM

R7FA6M4AE3CFM

R7FA6M4AD3CFM

Parts number

Security

SCE9, TrustZone, and Lifecycle management

Note 1. Available pins depend on the Pin count, about details see section 1.7. Pin Lists.

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Page 9 of 109

RA6M4 Datasheet

1. Overview

1.5

Pin Functions

Table 1.14

Function

Pin functions (1 of 6)

Signal

I/O

Description

Power supply

VCC

Input

Power supply pin. Connect it to the system power supply. Connect

this pin to VSS by a 0.1-µF capacitor. The capacitor should be

placed close to the pin.

VCL/VCL0

I/O

Connect this pin to the VSS pin by the smoothing capacitor used to

stabilize the internal power supply. Place the capacitor close to the

pin.

VSS

Input

Ground pin. Connect it to the system power supply (0 V).

Battery Backup power pin

VBATT

XTAL

Input

Clock

Output

Input

Pins for a crystal resonator. An external clock signal can be input

through the EXTAL pin.

EXTAL

XCIN

Input

Input/output pins for the sub-clock oscillator. Connect a crystal

resonator between XCOUT and XCIN.

XCOUT

CLKOUT

Output

Input

Clock output pin

Operating mode control

System control

MD

Pin for setting the operating mode. The signal level on this pin must

not be changed during operation mode transition on release from

the reset state.

RES

Input

Reset signal input pin. The MCU enters the reset state when this

signal goes low.

CAC

CACREF

TMS

Input

I/O

Measurement reference clock input pin

On-chip emulator or boundary scan pins

On-chip emulator

TDI

Input

Output

I/O

TCK

TDO

TCLK

Output clock for synchronization with the trace data

Trace data output

TDATA0 to TDATA3

SWO

Serial wire trace output pin

SWDIO

SWCLK

NMI

Serial wire debug data input/output pin

Serial wire clock pin

Input

Interrupt

Non-maskable interrupt request pin

Maskable interrupt request pins

IRQn

IRQn-DS

Maskable interrupt request pins that can also be used in Deep

Software Standby mode

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RA6M4 Datasheet

1. Overview

Table 1.14

Pin functions (2 of 6)

Function

Signal

I/O

Description

External bus interface

RD

Output

Strobe signal indicating that reading from the external bus interface

space is in progress, active-low

WR

Output

Strobe signal indicating that writing to the external bus interface

space is in progress, in 1-write strobe mode, active-low

WRn

Strobe signals indicating that either group of data bus pins (D07 to

D00 or D15 to D08) is valid in writing to the external bus interface

space, in byte strobe mode, active-low

BCn

Output

Strobe signals indicating that either group of data bus pins (D07 to

D00 or D15 to D08) is valid in access to the external bus interface

space, in 1-write strobe mode, active-low

ALE

Output

Input

Address latch signal when address/data multiplexed bus is selected

WAIT

Input pin for wait request signals in access to the external space,

active-low

CSn

Output

I/O

Select signals for CS areas, active-low

Address bus

A00 to A20

D00 to D15

A00/D00 to A15/D15

Data bus

I/O

Address/data multiplexed bus

External trigger input pins

GPT

GTETRGA, GTETRGB,

GTETRGC, GTETRGD

Input

GTIOCnA, GTIOCnB

GTIU

I/O

Input capture, output compare, or PWM output pins

Hall sensor input pin U

Input

GTIV

Input

Hall sensor input pin V

GTIW

Input

Hall sensor input pin W

GTOUUP

GTOULO

GTOVUP

GTOVLO

GTOWUP

GTOWLO

AGTEEn

AGTIOn

Output

Input

3-phase PWM output for BLDC motor control (positive U phase)

3-phase PWM output for BLDC motor control (negative U phase)

3-phase PWM output for BLDC motor control (positive V phase)

3-phase PWM output for BLDC motor control (negative V phase)

3-phase PWM output for BLDC motor control (positive W phase)

3-phase PWM output for BLDC motor control (negative W phase)

External event input enable signals

AGT

RTC

I/O

External event input and pulse output pins

Pulse output pins

AGTOn

Output

Input

AGTOAn

AGTOBn

RTCOUT

RTCICn

Output compare match A output pins

Output compare match B output pins

Output pin for 1-Hz or 64-Hz clock

Time capture event input pins

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RA6M4 Datasheet

1. Overview

Table 1.14

Function

SCI

Pin functions (3 of 6)

Signal

SCKn

RXDn

I/O

Description

I/O

Input/output pins for the clock (clock synchronous mode)

Input

Input pins for received data (asynchronous mode/clock synchronous

mode)

TXDn

Output

I/O

Output pins for transmitted data (asynchronous mode/clock

synchronous mode)

CTSn_RTSn

Input/output pins for controlling the start of transmission and

reception (asynchronous mode/clock synchronous mode), active-

low.

CTSn

SCLn

Input

I/O

Input for the start of transmission.

Input/output pins for the IIC clock (simple IIC mode)

Input/output pins for the IIC data (simple IIC mode)

Input/output pins for the clock (simple SPI mode)

Input/output pins for slave transmission of data (simple SPI mode)

Input/output pins for master transmission of data (simple SPI mode)

Chip-select input pins (simple SPI mode), active-low

Input pins for received data (Extended Serial Mode)

Output pins for transmitted data (Extended Serial Mode)

SDAn

SCKn

MISOn

MOSIn

SSn

I/O

Input

Output

I/O

RXDXn

TXDXn

SIOXn

Input/output pins for receivde or tramsmitted data (Extended Serial

Mode)

IIC

SCLn

I/O

Input/output pins for the clock

SDAn

Input/output pins for data

SPI

RSPCKA, RSPCKB

MOSIA, MOSIB

MISOA, MISOB

SSLA0, SSLB0

Clock input/output pin

Input or output pins for data output from the master

Input or output pins for data output from the slave

Input or output pin for slave selection

Output pins for slave selection

SSLA1 to SSLA3, SSLB1 Output

to SSLB3

CAN

CRXn

CTXn

Input

Receive data

Transmit data

Output

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 12 of 109

RA6M4 Datasheet

1. Overview

Table 1.14

Function

USBFS

Pin functions (4 of 6)

Signal

I/O

Description

Power supply pin

Ground pin

VCC_USB

VSS_USB

USB_DP

Input

I/O

D+ pin of the USB on-chip transceiver. Connect this pin to the D+

pin of the USB bus.

USB_DM

I/O

D- pin of the USB on-chip transceiver. Connect this pin to the D- pin

of the USB bus.

USB_VBUS

Input

USB cable connection monitor pin. Connect this pin to VBUS of the

USB bus. The VBUS pin status (connected or disconnected) can be

detected when the USB module is operating as a function controller.

USB_EXICEN

USB_VBUSEN

Output

Input

Low-power control signal for external power supply (OTG) chip

VBUS (5 V) supply enable signal for external power supply chip

USB_OVRCURA,

USB_OVRCURB

Connect the external overcurrent detection signals to these pins.

Connect the VBUS comparator signals to these pins when the OTG

power supply chip is connected.

USB_OVRCURA-DS,

USB_OVRCURB-DS

Input

Overcurrent pins for USBFS that can also be used in Deep Software

Standby mode.

Connect the external overcurrent detection signals to these pins.

Connect the VBUS comparator signals to these pins when the OTG

power supply chip is connected.

USB_ID

Input

Connect the MicroAB connector ID input signal to this pin during

operation in OTG mode

QSPI

OSPI

QSPCLK

Output

I/O

QSPI clock output pin

QSSL

QSPI slave output pin

QIO0 to QIO3

OM_SCLK

OM_CSn

Data0 to Data3

Output

I/O

Clock output (OCTACLK divided by 2)

Chip select signal for an OctaFlash device, active-low

Read data strobe/write data mask signal

Data input/output

OM_DQS

OM_SIOn

OM_RESET

OM_ECS

I/O

Output

Input

I/O

Reset signal for both OctaFlash and OctaRAM devices, active-low

ECC error detection signal from the external memory, active-low

SSIE serial bit clock pins

SSIE

SSIBCK0

SSILRCK0/SSIFS0

SSITXD0

I/O

LR clock/frame synchronization pins

Serial data output pin

Output

Input

I/O

SSIRXD0

Serial data input pin

SSIDATA0

AUDIO_CLK

SD0CLK

Serial data input/output pins

Input

Output

I/O

External clock pin for audio (input oversampling clock)

SD clock output pins

SDHI/MMC

SD0CMD

Command output pin and response input signal pins

SD and MMC data bus pins

SD0DAT0 to SD0DAT73

SD0CD

I/O

Input

SD card detection pins

SD0WP

SD write-protect signals

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 13 of 109

RA6M4 Datasheet

1. Overview

Table 1.14

Function

ETHERC

Pin functions (5 of 6)

Signal

I/O

Description

REF50CK0

Input

50-MHz reference clock. This pin inputs reference signal for

transmission/reception timing in RMII mode.

RMII0_CRS_DV

Input

Indicates carrier detection signals and valid receive data on

RMII0_RXD1 and RMII0_RXD0 in RMII mode

.

RMII0_TXDn

RMII0_RXDn

RMII0_TXD_EN

RMII0_RX_ER

ET0_CRS

Output

Input

2-bit transmit data in RMII mode

2-bit receive data in RMII mode

Output

Input

Output pin for data transmit enable signal in RMII mode

Indicates an error occurred during reception of data in RMII mode

Carrier detection/data reception enable signal

Indicates valid receive data on ET0_ERXD3 to ET0_ERXD0

General-purpose external output pin

Input

ET0_RX_DV

ET0_EXOUT

ET0_LINKSTA

ET0_ETXDn

ET0_ERXDn

ET0_TX_EN

Input

Output

Input

Input link status from the PHY-LSI

Output

Input

4 bits of MII transmit data

4 bits of MII receive data

Output

Transmit enable signal. Functions as signal indicating that transmit

data is ready on ET0_ETXD3 to ET0_ETXD0.

ET0_TX_ER

ET0_RX_ER

ET0_TX_CLK

ET0_RX_CLK

Output

Input

Transmit error pin. Functions as signal notifying the PHY_LSI of an

error during transmission.

Receive error pin. Functions as signal to recognize an error during

reception.

Transmit clock pin. This pin inputs reference signal for output timing

from ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0, and ET0_TX_ER.

Input

Receive clock pin. This pin inputs reference signal for input timing to

ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and ET0_RX_ER.

ET0_COL

ET0_WOL

ET0_MDC

Input

Input collision detection signal

Receive Magic packets

Output

Output reference clock signal for information transfer through

ET0_MDIO

AVCC0

I/O

Input or output bidirectional signal for exchange of management

data with PHY-LSI

Analog power supply

Input

Analog voltage supply pin. This is used as the analog power supply

for the respective modules. Supply this pin with the same voltage as

the VCC pin.

AVSS0

Input

Analog ground pin. This is used as the analog ground for the

respective modules. Supply this pin with the same voltage as the

VSS pin.

VREFH0

VREFL0

VREFH

Input

Analog reference voltage supply pin for the ADC12 (unit 0). Connect

this pin to VCC when not using the ADC12 (unit 0).

Analog reference ground pin for the ADC12. Connect this pin to VSS

when not using the ADC12 (unit 0).

Analog reference voltage supply pin for the ADC12 (unit 1) and D/A

Converter. Connect this pin to VCC when not using the ADC12 (unit

1) and D/A Converter.

VREFL

Input

Analog reference ground pin for the ADC12 and D/A Converter.

Connect this pin to VSS when not using the ADC12 (unit 1) and D/A

Converter.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 14 of 109

RA6M4 Datasheet

1. Overview

Table 1.14

Function

ADC12

Pin functions (6 of 6)

Signal

I/O

Description

ANmn

Input

Input pins for the analog signals to be processed by the A/D

converter.

(m: ADC unit number, n: pin number)

ADTRGm

Input

Input pins for the external trigger signals that start the A/D

conversion, active-low.

DAC12

CTSU

DAn

Output

Input

I/O

Output pins for the analog signals processed by the D/A converter.

Capacitive touch detection pins (touch pins)

TSn

TSCAP

Pmn

Secondary power supply pin for the touch driver

I/O ports

I/O

General-purpose input/output pins

(m: port number, n: pin number)

P200

Input

General-purpose input pin

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 15 of 109

RA6M4 Datasheet

1. Overview

1.6

Pin Assignments

The following figures show the pin assignments from the top view.

109

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

P800

P300/TCK/SWCLK

110

P801

P301

P302

P303

VCC

VSS

111

VCC

112

VSS

113

P500

114

P501

115

P304

P305

P502

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

P503

P504

P505

P306

P307

P308

P309

P310

P506

P507

VCC

VSS

P311

P312

P015

P014

P200

P201/MD

RES

VREFL

VREFH

P208

P209

P210

P211

P214

VCC

AVCC0

AVSS0

VREFL0

VREFH0

P009

P008

VSS

P007

P006

P005

P004

P003

P002

P001

P000

P313

P202

P203

P204

P205

P206

P207

VSS

VCC

P512

P511

VCC_USB

USB_DP

USB_DM

VSS_USB

Figure 1.3

Pin assignment for LQFP 144-pin

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 16 of 109

RA6M4 Datasheet

1. Overview

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P500

P501

P300/TCK/SWCLK

P301

P502

P302

P503

P303

P504

VCC

P505

VSS

VCC

P304

VSS

P305

P015

P306

P014

P307

VREFL

VREFH

AVCC0

AVSS0

VREFL0

VREFH0

P008

P200

P201/MD

RES

P208

P209

P210

P211

P007

P214

P006

P205

P005

P206

P004

P207

P003

VCC_USB

USB_DP

USB_DM

VSS_USB

P002

P001

P000

Figure 1.4

Pin assignment for LQFP 100-pin

49

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P500

P300/TCK/SWCLK

P301

50

VCC

51

VSS

P302

52

P015

P303

53

P014

P304

54

VREFL

P200

55

VREFH

P201/MD

RES

56

AVCC0

57

AVSS0

P208

58

VREFL0

P205

59

VREFH0

P206

60

P004

P207

61

P003

VCC_USB

USB_DP

USB_DM

VSS_USB

62

P002

63

P001

64

P000

Figure 1.5

Pin assignment for LQFP 64-pin

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 17 of 109

RA6M4 Datasheet

1. Overview

1.7

Pin Lists

Table 1.15

Pin list (1 of 4)

Power, System,

Clock, Debug,

CAC

I/O

SCI/IIC/SPI/CAN/USBFS/QSPI/OSPI/SSIE/

ports Ex. Bus Ex. Interrupt SDHI/MMC/EHTERC(MII,RMII)

GPT/AGT/RTC

ADC12/DAC12 CTSU

1

2

3

4

5

1

2

3

4

5

1

—

P400

P401

P402

P403

P404

—

IRQ0

SCK4/SCK7/SCL0_A/AUDIO_CLK/ET0_WOL/

ET0_WOL

GTIOC6A/AGTIO1

ADTRG1

—

2

—

IRQ5-DS

IRQ4-DS

IRQ14-DS

IRQ15-DS

CTS4_RTS4/TXD7/SDA0_A/CTX0/ET0_MDC/

ET0_MDC

GTETRGA/GTIOC6B

—

3

CACREF

CTS4/RXD7/CRX0/AUDIO_CLK/ET0_MDIO/

ET0_MDIO

AGTIO0/AGTIO1/AGTIO2/

AGTIO3/RTCIC0

—

CTS7_RTS7/SSIBCK0_A/ET0_LINKSTA/

ET0_LINKSTA

GTIOC3A/AGTIO0/AGTIO1/

AGTIO2/AGTIO3/RTCIC1

CTS7/SSILRCK0_A/ET0_EXOUT/ET0_EXOUT

GTIOC3B/AGTIO0_G/AGTIO1/

AGTIO2/AGTIO3/RTCIC2

6

—

4

—

P405

P406

P700

P701

P702

P703

P704

P705

—

SSITXD0_A/ET0_TX_EN/RMII0_TXD_EN_B

SSLA3_C/SSIRXD0_A/ET0_RX_ER/RMII0_TXD1_B

MISOA_C/ET0_ETXD1/RMII0_TXD0_B

GTIOC1A

—

7

—

GTIOC1B/AGTO5

GTIOC5A/AGTO4

GTIOC5B/AGTO3

GTIOC6A/AGTO2

GTIOC6B/AGTO1

AGTO0

—

8

—

8

—

9

—

MOSIA_C/ET0_ETXD0/REF50CK0_B

—

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

—

RSPCKA_C/ET0_ERXD1/RMII0_RXD0_B

SSLA0_C/ET0_ERXD0/RMII0_RXD1_B

SSLA1_C/CTX0/ET0_RX_CLK/RMII0_RX_ER_B

—

CTS3/SSLA2_C/CRX0/ET0_CRS/RMII0_CRS_DV_B AGTIO0

—

VBATT

VCL0

XCIN

XCOUT

VSS

XTAL

—

9

5

—

10

11

12

13

14

15

—

16

17

6

—

7

—

8

—

9

P213

P212

—

IRQ2

IRQ3

—

TXD1

GTETRGC/GTIOC0A/AGTEE2

ADTRG1

—

10 EXTAL

RXD1

GTETRGD/GTIOC0B/AGTEE1

—

11

—

VCC

—

P713

P712

P711

P710

P709

P708

P415

—

GTIOC2A/AGTOA0

—

TS17

TS16

TS15

TS14

TS13

TS12

TS11

—

GTIOC2B/AGTOB0

—

CTS1_RTS1/ET0_TX_CLK

SCK1/ET0_TX_ER

AGTEE0

—

IRQ10

IRQ11

IRQ8

TXD1/ET0_ETXD2

—

CACREF

—

RXD1/SSLB3_B/AUDIO_CLK/ET0_ETXD3

—

SSLB2_B/USB_VBUSEN/SD0CD/ET0_TX_EN/

RMII0_TXD_EN_A

GTIOC0A/AGTIO4

—

29

30

31

32

33

18

19

20

21

22

—

12

13

—

P414

P413

P412

P411

P410

—

IRQ9

—

CTS0/SSLB1_B/SD0WP/ET0_RX_ER/

RMII0_TXD1_A

GTIOC0B/AGTIO5

—

TS10

TS09

TS08

TS07

TS06

CTS0_RTS0/SSLB0_B/SD0CLK_A/ET0_ETXD1/

RMII0_TXD0_A

GTOUUP/AGTEE3

—

SCK0/CTS3/RSPCKB_B/SD0CMD_A/ET0_ETXD0/

REF50CK0_A

GTOULO/AGTEE1

IRQ4

IRQ5

TXD0/CTS3_RTS3/MOSIB_B/SD0DAT0_A/

ET0_ERXD1/RMII0_RXD0_A

GTOVUP/GTIOC9A/AGTOA1

GTOVLO/GTIOC9B/AGTOB1

RXD0/SCK3/MISOB_B/SD0DAT1_A/ET0_ERXD0/

RMII0_RXD1_A

34

35

23

24

14

15

—

P409

P408

—

IRQ6

IRQ7

TXD3/USB_EXICEN/ET0_RX_CLK/RMII0_RX_ER_A GTOWUP/AGTOA2

—

TS05

TS04

CTS4/RXD3/SCL0_B/USB_ID/ET0_CRS/

RMII0_CRS_DV_A

GTOWLO/GTIOC6B/AGTOB2

36

25

16

—

P407

—

CTS4_RTS4/SDA0_B/SSLA3_A/USB_VBUS/

ET0_EXOUT/ET0_EXOUT

GTIOC6A/AGTIO0/RTCOUT

ADTRG0

TS03

37

38

39

40

26

27

28

29

17 VSS_USB

18 USB_DM

19 USB_DP

20 VCC_USB

—

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 18 of 109

RA6M4 Datasheet

1. Overview

Table 1.15

Pin list (2 of 4)

Power, System,

Clock, Debug,

CAC

I/O

SCI/IIC/SPI/CAN/USBFS/QSPI/OSPI/SSIE/

ports Ex. Bus Ex. Interrupt SDHI/MMC/EHTERC(MII,RMII)

GPT/AGT/RTC

ADC12/DAC12 CTSU

41

42

30

31

21

22

—

P207

P206

A17

—

TXD4/SSLA2_A/QSSL

—

TSCAP

TS02

WAIT

IRQ0-DS

RXD4/CTS9/SDA1_B/SSLA1_A/USB_VBUSEN/

SSIDATA0_C/SD0DAT2_A/ET0_LINKSTA/

ET0_LINKSTA

GTIU

43

32

23 CLKOUT

P205

A16

IRQ1-DS

TXD4/CTS9_RTS9/SCL1_B/SSLA0_A/

USB_OVRCURA-DS/SSILRCK0_C/SD0DAT3_A/

ET0_WOL/ET0_WOL

GTIV/GTIOC4A/AGTO1

—

TS01

44

45

46

—

CACREF

P204

P203

P202

A18

A19

—

SCK4/SCK9/RSPCKA_A/USB_OVRCURB-DS/

SSIBCK0_C/SD0DAT4_A/ET0_RX_DV

GTIW/GTIOC4B/AGTIO1

GTIOC5A/AGTOA3

GTIOC5B/AGTOB3

—

TS00

TS18

TS19

—

IRQ2-DS

CTS2_RTS2/TXD9/MOSIA_A/CTX0/SD0DAT5_A/

ET0_COL

WR1/BC1 IRQ3-DS

SCK2/RXD9/MISOA_A/CRX0/SD0DAT6_A/

ET0_ERXD2

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

—

33

34

35

36

37

38

39

40

—

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

—

59

60

61

—

P313

—

A20

—

SD0DAT7_A/ET0_ERXD3

—

VSS

—

VCC

—

TCLK

TDATA0

TDATA1

TDATA2

P214

P211

P210

P209

P208

—

QSPCLK/SD0CLK_B/ET0_MDC/ET0_MDC

GTIU/AGTO5

GTIV/AGTOA5

GTIW/AGTOB5

GTOVUP/AGTEE5

GTOVLO

CS7

CS6

CS5

CS4

—

QIO0/SD0CMD_B/ET0_MDIO/ET0_MDIO

—

QIO1/SD0CD/ET0_WOL/ET0_WOL

—

QIO2/SD0WP/ET0_EXOUT/ET0_EXOUT

24 TDATA3

25 RES

26 MD

—

QIO3/SD0DAT0_B/ET0_LINKSTA/ET0_LINKSTA

—

P201

P200

P312

P311

P310

P309

P308

P307

P306

P305

P304

—

27

—

28

—

29

30

31

—

NMI

—

CS3

CS2

A15

A14

A13

A12

A11

A10

A9

CTS3_RTS3

AGTOA1

—

SCK3

AGTOB1

—

TXD3/QIO3

AGTEE1

—

RXD3/QIO2

AGTOA4

—

CTS6/CTS3/QIO1

AGTOB4

—

CTS6_RTS6/QIO0

GTOUUP_D/AGTEE4

GTOULO_D/AGTOA2

GTOWUP/AGTOB2

GTOWLO/GTIOC7A/AGTEE2

—

SCK6/QSSL

—

IRQ8

IRQ9

—

TXD6/QSPCLK

—

RXD6

VSS

VCC

—

P303

P302

P301

P300

P108

A8

—

CTS9

GTIOC7B

—

A7

IRQ5

IRQ6

—

TXD2/SSLA3_B

GTOUUP/GTIOC4A

GTOULO/GTIOC4B/AGTIO0

GTOUUP/GTIOC0A

GTOULO/GTIOC0B/AGTOA3

GTOVUP/GTIOC1A/AGTOB3

GTOVLO/GTIOC1B/AGTEE3

GTIOC3A/AGTOA5

GTIOC3B/AGTOB5

GTIOC2A/AGTEE5

GTIOC2B/AGTIO5

GTIOC4A

—

A6

RXD2/CTS9_RTS9/SSLA2_B

32 TCK/SWCLK

33 TMS/SWDIO

—

SSLA1_B

—

CTS9_RTS9/SSLA0_B

34 TDO/SWO/CLKOUT P109

—

TXD9/MOSIA_B/CTX1

35 TDI

P110

P111

P112

P113

P114

P115

—

IRQ3

IRQ4

—

CTS2_RTS2/RXD9/MISOA_B/CRX1

36

37

38

—

A5

SCK2/SCK9/RSPCKA_B

—

A4

TXD2/SCK1/SSLA0_B/QSSL/OM_CS1/SSISCK0_B

—

A3

—

RXD2/SSILRCK0_B

—

A2

—

CTS9/SSIRXD0_B

—

A1

—

SSITXD0_B

VCC

VSS

—

P608

P609

P610

A0/BC0

CS1

CS0

—

GTIOC4B

—

CTX1/OM_ECS

CTS7/CRX1/OM_CS0

GTIOC5A/AGTO5

GTIOC5B/AGTO4

—

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 19 of 109

RA6M4 Datasheet

1. Overview

Table 1.15

Pin list (3 of 4)

Power, System,

Clock, Debug,

CAC

I/O

SCI/IIC/SPI/CAN/USBFS/QSPI/OSPI/SSIE/

ports Ex. Bus Ex. Interrupt SDHI/MMC/EHTERC(MII,RMII)

GPT/AGT/RTC

ADC12/DAC12 CTSU

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

—

62

63

64

—

65

66

67

—

CACREF/CLKOUT

P611

P612

P613

P614

—

CTS7_RTS7

AGTO3

—

D8

D9

D10

—

SCK7

AGTO2

—

TXD7

AGTO1

—

RXD7

AGTO0

—

39 VCC

40 VSS

41 VCL

—

42

43

44

45

46

47

48

—

P605

P604

P603

P602

P601

P600

—

D11

D12

D13

BCLK

WR/WR0

RD

—

CTS8

GTIOC8A/AGTO4

—

CTS9

GTIOC8B/AGTEE4

—

CTS9_RTS9

GTIOC7A/AGTIO4

—

TXD9/OM_CS1

GTIOC7B/AGTO3

—

RXD9/OM_SIO2

GTIOC6A/AGTEE3

—

CACREF/CLKOUT

—

SCK9/OM_SIO4

GTIOC6B/AGTIO3

—

VCC

VSS

—

101 68

102 69

103 70

104 71

105 72

106 73

107 74

108 75

P107

P106

P105

P104

P103

P102

P101

P100

P800

P801

—

D7

D6

D5

D4

D3

D2

D1

D0

D14

D15

—

CTS8_RTS8/OM_SIO3

GTIOC8A/AGTOA0

—

SCK8/SSLB3_A/OM_SIO0

GTIOC8B/AGTOB0

—

IRQ0

IRQ1

—

TXD8/SSLB2_A/OM_SIO5

GTETRGA/GTIOC1A/AGTO2

—

RXD8/SSLB1_A/QIO2/OM_DQS

GTETRGB/GTIOC1B/AGTEE2

—

CTS0_RTS0/SSLB0_A/CTX0/QIO3/OM_SIO6

GTOWUP/GTIOC2A/AGTIO2

—

SCK0/RSPCKB_A/CRX0/QIO0/OM_SIO1

GTOWLO/GTIOC2B/AGTO0

ADTRG0

—

IRQ1

IRQ2

—

TXD0/CTS1_RTS1/MOSIB_A/QIO1/OM_SIO7

GTETRGB/GTIOC5A/AGTEE0

—

RXD0/SCK1/MISOB_A/QSPCLK/OM_SCLK

GTETRGA/GTIOC5B/AGTIO0

—

109

110

111

112

—

CTS0

AGTOA4

—

CTS8

AGTOB4

—

VCC

VSS

—

113 76

114 77

115 78

116 79

117 80

118 81

49 CACREF

P500

P501

P502

P503

P504

P505

P506

P507

—

CTS5/USB_VBUSEN/QSPCLK

GTIU/AGTOA0

AN116

AN117

AN118

AN119

AN120

AN121

AN122

—

IRQ11

IRQ12

—

TXD5/USB_OVRCURA/QSSL

GTIV/AGTOB0

—

CTS6/RXD5/USB_OVRCURB/QIO0

GTIW/AGTOA2

—

CTS6_RTS6/SCK5/USB_EXICEN/QIO1

GTETRGC/AGTOB2

ALE

—

SCK6/CTS5_RTS5/USB_ID/QIO2

GTETRGD/AGTOA3

IRQ14

IRQ15

—

RXD6/QIO3

AGTOB3

—

119

120

—

TXD6

—

SCK6/SCK5

—

121 82

122 83

123 84

124 85

125 86

126 87

127 88

128 89

129 90

130 91

50 VCC

51 VSS

—

52

53

—

P015

P014

—

IRQ13

—

AN013/DA1

AN012/DA0

—

54 VREFL

55 VREFH

56 AVCC0

57 AVSS0

58 VREFL0

59 VREFH0

—

131

—

P009

P008

P007

P006

—

IRQ13-DS

IRQ12-DS

—

AN009

AN008

AN007

AN006

132 92

133 93

134 94

—

IRQ11-DS

—

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 20 of 109

RA6M4 Datasheet

1. Overview

Table 1.15

Pin list (4 of 4)

Power, System,

Clock, Debug,

CAC

I/O

SCI/IIC/SPI/CAN/USBFS/QSPI/OSPI/SSIE/

ports Ex. Bus Ex. Interrupt SDHI/MMC/EHTERC(MII,RMII)

GPT/AGT/RTC

ADC12/DAC12 CTSU

135 95

136 96

137 97

138 98

139 99

—

60

61

62

63

—

P005

P004

P003

P002

P001

P000

—

IRQ10-DS

IRQ9-DS

—

AN005

—

AN004

—

AN003

—

IRQ8-DS

IRQ7-DS

IRQ6-DS

—

AN002/AN102

—

AN001/AN101

140 100 64

—

AN000/AN100

141

142

143

144

—

VSS

VCC

—

P512

P511

IRQ14

IRQ15

TXD4/SCL1_A/CTX1

RXD4/SDA1_A/CRX1

GTIOC0A

GTIOC0B

—

Note:

Several pin names have the added suffix of _A, _B, and _C. The suffix can be ignored when assigning functionality.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 21 of 109

RA6M4 Datasheet

2. Electrical Characteristics

2.

Electrical Characteristics

Supported peripheral functions and pins differ from one product name to another.

Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:

● VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V

● 2.7 ≤ VREFH0/VREFH ≤ AVCC0

● VSS = AVSS0 = VREFL0/VREFL = VSS_USB = 0 V

● T = T

a

opr

Figure 2.1 shows the timing conditions.

For example, P100

C

V_OH= VCC × 0.7, V_OL= VCC × 0.3

V_IH= VCC × 0.7, V_IL= VCC × 0.3

Load capacitance C = 30 pF

Figure 2.1

Input or output timing measurement conditions

The recommended measurement conditions for the timing specification of each peripheral provided are for the best

peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.

2.1

Absolute Maximum Ratings

Table 2.1

Parameter

Absolute maximum ratings

Symbol

Value

Unit

*2

Power supply voltage

–0.3 to +4.0

V

VCC, VCC_USB

VBATT

VBATT power supply voltage

–0.3 to +4.0

V

*1

V

–0.3 to VCC + 0.3

Input voltage (except for 5 V-tolerant ports )

in

*1

V

in

–0.3 to + VCC + 4.0 (max. 5.8)

V

Input voltage (5 V-tolerant ports )

Reference power supply voltage

Analog power supply voltage

VREFH/VREFH0

–0.3 to VCC + 0.3

–0.3 to +4.0

V

*2

AVCC0

Analog input voltage

V

T

–0.3 to AVCC0 + 0.3

–40 to +105

V

AN

*3 *4

°C

Operating temperature

opr

stg

Storage temperature

T

–55 to +125

Note 1. Ports P205, P206, P400, P401, P407 to P415, P511, P512, and P708 to P713 are 5 V tolerant.

Note 2. Connect AVCC0 and VCC_USB to VCC.

Note 3. See section 2.2.1. Tj/Ta Definition.

Note 4. Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the

systematic reduction of load for improved reliability.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 22 of 109

RA6M4 Datasheet

2. Electrical Characteristics

Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.

Table 2.2

Parameter

Recommended operating conditions

Symbol

Value

Min

2.7

3.0

—

Typ

—

Max

3.6

—

Unit

V

Power supply voltages

VCC

When USB is not used

When USB is used

—

V

VSS

0

V

USB power supply voltages

VCC_USB

VSS_USB

VBATT

—

VCC

0

—

V

—

V

VBATT power supply voltage

Analog power supply voltages

1.8

—

3.6

—

V

*1

VCC

V

AVCC0

AVSS0

—

0

—

V

Note 1. Connect AVCC0 to VCC. When the A/D converter and the D/A converter are not in use, do not leave the AVCC0, VREFH/VREFH0,

AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/

VREFL0 pins to VSS, respectively.

2.2

DC Characteristics

2.2.1

Tj/Ta Definition

Table 2.3

DC characteristics

Conditions: Products with operating temperature (T ) -40 to +105°C

a

Parameter

Symbol

Typ

Max

Unit

Test conditions

Permissible junction temperature

T

—

125

°C

High-speed mode

Low-speed mode

Subosc-speed mode

j

Note:

Make sure that T = T + θja × total power consumption (W), where total power consumption = (VCC - V ) × ΣI + V × ΣI

+

OL

j

a

OH

OL

I max × VCC.

CC

2.2.2

I/O V , V

IH

IL

Table 2.4

Parameter

I/O V_IH, V_IL(1 of 2)

Symbol Min

Typ Max

Unit

Input voltage

(except for

Peripheral

function pin

EXTAL (external clock input), WAIT, SPI (except

RSPCK), OSPI (except ECS)

V

VCC ×

0.8

—

V

IH

Schmitt trigger

input pins)

V

—

VCC × 0.2

—

IL

D00 to D15

VCC ×

0.7

IH

V

—

VCC × 0.3

—

IL

IH

IL

IH

ETHERC

2.3

—

VCC × 0.2

IIC (SMBus)

2.1

VCC + 3.6

(max 5.8)

V

—

0.8

IL

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 23 of 109

RA6M4 Datasheet

2. Electrical Characteristics

Table 2.4

Parameter

I/O V_IH, V_IL(2 of 2)

Symbol Min

Typ Max

Unit

Schmitt trigger

input voltage

Peripheral

function pin

IIC (except for SMBus)

V

VCC ×

0.7

—

VCC + 3.6

V

IH

(max 5.8)

VCC × 0.3

—

V

—

IL

ΔV

V

VCC ×

0.05

T

*1 *5

VCC ×

0.8

—

VCC + 3.6

(max 5.8)

5 V-tolerant ports

IH

V

—

VCC × 0.2

—

IL

ΔV

VCC ×

0.05

T

RTCIC0,

RTCIC1,

RTCIC2

When using the

Battery Backup

Function

When VBATT

power supply is

selected

V

0.8

×

—

V

+ 0.3

× 0.2

IH

BATT

V

—

V

IL

BATT

ΔV

V

×

—

T

BATT

0.05

When VCC

power supply is

selected

V

VCC ×

0.8

—

Higher

voltage

either

IH

VCC + 0.3 V

or

V

+ 0.3

BATT

V

—

VCC × 0.2

—

IL

ΔV

VCC ×

0.05

T

When not using the Battery Backup

Function

V

VCC ×

0.8

—

VCC + 0.3

IH

—

VCC × 0.2

—

IL

ΔV

VCC ×

0.05

T

*2

V

VCC ×

0.8

—

Other input pins

IH

V

—

VCC × 0.2

—

IL

ΔV

VCC ×

0.05

T

*3 *5

Ports

V

VCC ×

0.8

—

VCC + 3.6

(max 5.8)

V

5 V-tolerant ports

IH

V

—

VCC × 0.2

—

IL

*4

VCC ×

0.8

Other input pins

IH

V

—

VCC × 0.2

IL

Note 1. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713 (total 22

pins).

Note 2. All input pins except for the peripheral function pins already described in the table.

Note 3. P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713 (total 21 pins).

Note 4. All input pins except for the ports already described in the table.

Note 5. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur

because 5 V-tolerant ports are electrically controlled so as not to violate the break down voltage.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 24 of 109

RA6M4 Datasheet

2. Electrical Characteristics

2.2.3

I/O I , I

OH OL

Table 2.5

Parameter

I/O I_OH, I_OL(1 of 2)

Symbol

Min Typ Max Unit

Permissible output current (average

value per pin)

Ports P000 to P009, P014, P015, P201

—

I

—

–2.0 mA

2.0 mA

–2.0 mA

2.0 mA

–4.0 mA

4.0 mA

–20 mA

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

*1

Ports P205, P206, P407 to P415, P708 to

P713 (total 17 pins)

Low drive

*2

Middle drive

*3

High drive

20

mA

*1

Ports P100 to P107, P208 to P211, P214,

P600, P601 (total 15 pins)

–2.0 mA

2.0 mA

–4.0 mA

4.0 mA

–16 mA

Low drive

*2

Middle drive

*3

High drive

16

–20 mA

20 mA

mA

High spped high

drive

*4

*5

*1

–2.0 mA

2.0 mA

–4.0 mA

4.0 mA

–16 mA

Other output pins

Low drive

*2

Middle drive

*3

High drive

16

mA

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 25 of 109

RA6M4 Datasheet

2. Electrical Characteristics

Table 2.5

Parameter

I/O I_OH, I_OL(2 of 2)

Symbol

Min Typ Max Unit

Permissible output current (max value

per pin)

Ports P000 to P009, P014, P015, P201

—

I

—

–4.0 mA

4.0 mA

–4.0 mA

4.0 mA

–8.0 mA

8.0 mA

–40 mA

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

OH

OL

*1

Ports P205, P206, P407 to P415, P708 to

P713 (total 17 pins)

Low drive

*2

Middle drive

*3

High drive

40

mA

*1

Ports P100 to P107, P208 to P211, P214,

P600, P601 (total 15 pins)

–4.0 mA

4.0 mA

–8.0 mA

8.0 mA

–32 mA

Low drive

*2

Middle drive

*3

High drive

32

–40 mA

40 mA

mA

High spped high

drive

*4

*5

*1

–4.0 mA

4.0 mA

–8.0 mA

8.0 mA

–32 mA

Other output pins

Low drive

*2

Middle drive

*3

High drive

32

–80 mA

80 mA

mA

Permissible output current (maxvalue of Maximum of all output pins

total of all pins)

ΣI

OH (max)

OL (max)

Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving

ability is retained in Deep Software Standby mode.

Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving

ability is retained in Deep Software Standby mode.

Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving

ability is retained in Deep Software Standby mode.

Note 4. This is the value when high speed high driving ability is selected in the Port Drive Capability in the PmnPFS register. The selected

driving ability is retained in Deep Software Standby mode.

Note 5. Except for P200, which is an input port.

Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this table.

The average output current indicates the average value of current measured during 100 µs.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 26 of 109

RA6M4 Datasheet

2. Electrical Characteristics

2.2.4

I/O V , V , and Other Characteristics

OH OL

Table 2.6

I/O V_OH, V_OL, and other characteristics

Parameter

Symbol Min

Typ Max Unit Test conditions

Output voltage

IIC

V

OL

V

OL

V

OL

V

OL

V

OH

V

OL

V

OH

—

0.4

0.6

0.4

—

V

I

= 3.0 mA

OL

OH

OL

OH

= 6.0 mA

*1

= 15.0 mA (ICFER.FMPE = 1)

= 20.0 mA (ICFER.FMPE = 1)

= –1.0 mA

IIC

ETHERC

VCC – 0.5 —

—

0.4

—

= 1.0 mA

Ports P205, P206, P407 to P415,

P708 to P713 (total of 17 pins)

VCC – 1.0 —

= –20 mA

*2

VCC = 3.3 V

V

—

1.0

I

OL

= 20 mA

OL

VCC = 3.3 V

Other output pins

V

VCC – 0.5 —

—

I

= –1.0 mA

= 1.0 mA

OH

—

0.5

OL

Input leakage current

RES

|I |

in

5.0 µA

V

= 0 V

= 5.5 V

in

Port P200

—

1.0

V

= 0 V

= VCC

in

Three-state leakage current 5 V-tolerant ports

(off state)

|I

|

—

5.0 µA

1.0

V

= 0 V

= 5.5 V

TSI

in

Other ports (except for port

P200)

—

V

= 0 V

= VCC

in

Input pull-up MOS current

Input capacitance

Ports P0 to P8

I

p

–300

—

–10 µA VCC = 2.7 to 3.6 V

= 0 V

V

in

USB_DP, USB_DM, and ports

P014, P015, P400, P401, P511,

P512

C

16

pF

Vbias = 0 V

Vamp = 20 mV

f = 1 MHz

in

Ta = 25°C

Other input pins

—

8

Note 1. SCL0_A, SDA0_A (total 2 pins).

Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register.

The selected driving ability is retained in Deep Software Standby mode.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 27 of 109

RA6M4 Datasheet

2. Electrical Characteristics

2.2.5

Operating and Standby Current

Table 2.7

Parameter

Supply

Operating and standby current (1 of 2)

Symbol Min Typ Max Unit Test conditions

*2

*3

High-speed

mode

—

20

30

115 mA ICLK = 200 MHz

PCLKA = 100

Maximum

I

CC

*1

current

®*5 *6

—

CoreMark

,

MHz

PCLKB = 50 MHz

PCLKC = 50 MHz

Normal mode

All peripheral clocks enabled,

while (1) code executing from

flash

—

PCLKD = 100

MHz

*4

FCLK = 50 MHz

BCLK = 100 MHz

All peripheral clocks disabled,

while (1) code executing from

flash ,

—

17

10

—

*5 *6

47

Sleep mode ,

Increase during Data flash P/E

—

6

—

BGO operation

Code flash P/E

8

*5 *9

1.9

—

ICLK = 1 MHz

Low-speed mode

*5 *10

—

1.7

ICLK = 32.768

kHz

Subosc-speed mode

Software Standby mode

SNZCR.RXDREQEN = 1

SNZCR.RXDREQEN = 0

—

34

—

1.6

Deep Software Power supplied to Standby SRAM and USB

Standby mode resume detecting unit

16.9 131 µA

Power not

Power-on reset circuit low

power function disabled

—

11.8 31

—

supplied to

SRAM or USB

resume

Power-on reset circuit low

power function enabled

4.8 21

detecting unit

Increase when

the RTC and

AGT are

When the low-speed on-chip

oscillator (LOCO) is in use

—

4.0

1.2

1.5

0.9

1.3

1.0

1.7

—

When a crystal oscillator for

low clock loads is in use

operating

When a crystal oscillator for

standard clock loads is in use

RTC operating while VCC is off (with the

battery backup function, only the RTC and

sub-clock oscillator operate)

When a crystal

oscillator for low

clock loads is in use

V

= 1.8 V,

BATT

VCC = 0 V

V

= 3.3 V,

BATT

VCC = 0 V

V = 1.8 V,

BATT

When a crystal

oscillator for standard

clock loads is in use

VCC = 0 V

V

= 3.3 V,

BATT

VCC = 0 V

*7

Inrush current on returning from deep

software standby mode

I

—

160

1.0

—

mA

µC

Inrush current

RUSH

Energy of inrush

E

RUSH

*7

current

Analog

power supply

current

During 12-bit A/D conversion

Temperature sensor

AI

CC

—

0.8 1.1 mA

0.1 0.2 mA

0.6 1.1 mA

0.9 1.6 mA

—

During D/A conversion (per unit)

Without AMP output

With AMP output

Waiting for A/D, D/A conversion (all units)

ADC12, DAC12 in standby modes (all units)

*8

2

8

µA

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 28 of 109

RA6M4 Datasheet

2. Electrical Characteristics

Table 2.7

Parameter

Operating and standby current (2 of 2)

Symbol Min Typ Max Unit Test conditions

Reference

power supply

current

During 12-bit A/D conversion (unit 0)

Waiting for 12-bit A/D conversion (unit 0)

ADC12 in standby modes (unit 0)

During 12-bit A/D conversion (unit 1)

During D/A conversion (per unit)

AI

—

70

120 µA

—

REFH0

0.07 0.5 µA

(VREFH0)

Reference

power supply

current

AI

70

120 µA

REFH

Without AMP output

With AMP ouput

0.1 0.4 mA

0.07 0.8 µA

(VREFH)

Waiting for 12-bit A/D (unit 1), D/A (all units) conversion

ADC12 unit 1 in standby modes

USB

operating

current

Low speed

Full speed

USB

I

3.5 6.5 mA VCC_USB

4.0 10.0 mA VCC_USB

CCUSBLS

CCUSBFS

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.

Note 3. I depends on f (ICLK) as follows.

CC

I

Max. = 0.37 × f + 42 (max. operation in high-speed mode)

Typ. = 0.07 × f + 3.6 (normal operation in high-speed mode, all peripheral clocks disabled)

Typ. = 0.2 × f + 1.7 (low-speed mode)

CC

Max. = 0.03 × f + 42 (sleep mode)

Note 4. This does not include the BGO operation.

Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 6. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.125 MHz).

Note 7. Reference value

Note 8. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-Bit A/D Converter 0 Module Stop bit) and

MSTPCRD.MSTPD15 (12-bit A/D converter 1 module stop bit) are in the module-stop state.

Note 9. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz).

Note 10. BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz). FCLK is the same frequency as that of ICLK.

Table 2.8

Coremark and normal mode current

Parameter

Symbol

Typ

99

Unit

Test conditions

*1

Coremark

I

µA/MHz

ICLK = 200MHz

PCLKA =

PCLKB =

PCLKC =

PCLKD =

FCLK =

Supply Current

CC

Normal mode

All peripheral

clocks disabled,

cache on, while

(1) code

95

executing from

BCLK =

3.125MHz

*2

flash

All peripheral

clocks disabled,

cache off, while

(1) code

82

executing from

*2

flash

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

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2. Electrical Characteristics

100.0

10.0

1.0

0.1

-40

-20

0

20

40

Ta (°C)

60

80

100

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.2

Temperature dependency in Software Standby mode (reference data)

1000

100

10

1

-40

-20

0

20

40

Ta (°C)

60

80

100

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.3

Temperature dependency in Deep Software Standby mode, power supplied to standby SRAM

and USB resume detecting unit (reference data)

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RA6M4 Datasheet

2. Electrical Characteristics

100

10

1

-40

-20

0

20

40

Ta (°C)

60

80

100

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.4

Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or

USB resume detecting unit, power-on reset circuit low power function disabled (reference

data)

100

10

1

-40

-20

0

20

40

Ta (°C)

60

80

100

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.5

Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or

USB resume detecting unit, power-on reset circuit low power function enabled (reference data)

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RA6M4 Datasheet

2. Electrical Characteristics

2.2.6

VCC Rise and Fall Gradient and Ripple Frequency

Table 2.9

Rise and fall gradient characteristics

Test

Parameter

Symbol

Min

Typ Max Unit

conditions

VCC rising gradient

VCC falling gradient

Voltage monitor 0 reset disabled at startup

Voltage monitor 0 reset enabled at startup

SrVCC

0.0084

—

20

—

20

ms/V

—

*1

SCI/USB boot mode

*2

SfVCC

0.0084

—

ms/V

—

Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.

Note 2. This applies when VBATT is used.

Table 2.10

Rising and falling gradient and ripple frequency characteristics

The ripple voltage must meet the allowable ripple frequency f

within the range between the VCC upper limit (3.6 V) and lower limit (2.7

r(VCC)

V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Allowable ripple

frequency

f

—

10

kHz

Figure 2.6

r (VCC)

V

≤ VCC × 0.2

r (VCC)

—

1

MHz

ms/V

Figure 2.6

≤ VCC × 0.08

V

r (VCC)

—

10

—

Figure 2.6

≤ VCC × 0.06

V

r (VCC)

Allowable voltage

change rising and

falling gradient

dt/dVCC

1.0

When VCC change

exceeds VCC ±10%

1 / f_r(VCC)

VCC

V_r(VCC)

Figure 2.6

Ripple waveform

2.2.7

Thermal Characteristics

Maximum value of junction temperature (Tj) must not exceed the value of “section 2.2.1. Tj/Ta Definition”.

Tj is calculated by either of the following equations.

● Tj = Ta + θja × Total power consumption

● Tj = Tt + Ψjt × Total power consumption

– Tj : Junction Temperature (°C)

– Ta : Ambient Temperature (°C)

– Tt : Top Center Case Temperature (°C)

– θja : Thermal Resistance of “Junction”-to-“Ambient” (°C/W)

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2. Electrical Characteristics

– Ψjt : Thermal Resistance of “Junction”-to-“Top Center Case” (°C/W)

● Total power consumption = Voltage × (Leakage current + Dynamic current)

● Leakage current of IO = Σ (I × V ) /Voltage + Σ (|I | × |VCC – V |) /Voltage

OL

OH

● Dynamic current of IO = Σ IO (C + C ) × IO switching frequency × Voltage

in

load

– C : Input capacitance

in

– C : Output capacitance

load

Regarding θja and Ψjt, refer to Table 2.11.

Table 2.11

Thermal Resistance

Package

*1

Parameter

Symbol

Value

38.0

35.0

33.0

0.80

0.76

0.63

Unit

Test conditions

Thermal Resistance

64-pin LQFP (PLQP0064KB-C)

100-pin LQFP (PLQP0100KB-B)

144-pin LQFP (PLQP0144KA-B)

64-pin LQFP (PLQP0064KB-C)

100-pin LQFP (PLQP0100KB-B)

144-pin LQFP (PLQP0144KA-B)

θja

°C/W JESD 51-2 and 51-7

compliant

Ψjt

°C/W JESD 51-2 and 51-7

compliant

Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the

board. For details, refer to the JEDEC standards.

2.2.7.1

Calculation guide of I max

CC

Table 2.12 shows the power consumption of each unit.

Table 2.12

Power consumption of each unit (1 of 2)

*1

Dynamic current/

Leakage current

MCU

Domain

Frequency

[MHz]

Current

[uA/MHz]

Current

[mA]

Category

Item

Dynamic current

CPU

Operation with

Coremark

200

86.357

17.27

Flash and SRAM

*4

Peripheral Unit

Timer

100

50

5.300

3.946

1.378

10.095

0.53

0.39

0.07

0.50

GPT16 (6ch)

GPT32 (4ch)

*4

POEG (4 Groups)

*4

50

AGT (6ch)

RTC

50

5.239

0.722

0.267

7.651

8.788

25.595

0.26

0.04

0.01

0.77

0.44

2.56

WDT

50

IWDT

50

Communication

interfaces

ETHERC

USBFS

100

50

*4

100

SCI (10ch)

*4

50

3.014

3.843

6.770

0.15

0.19

0.68

IIC (2ch)

*4

50

CAN (2ch)

*4

100

SPI (2ch)

OSPI

QSPI

SSIE

SDHI

50

32.530

2.587

3.131

7.074

4.697

1.63

0.26

0.16

0.35

0.47

100

50

*4

Analog

100

ADC12 (2 Units)

*4

100

3.543

0.35

DAC12 (2ch)

TSN

50

0.166

0.678

0.01

0.03

Human machine

interfaces

CTSU

Event link

ELC

50

1.016

218.100

0.521

0.358

0.909

4.045

3.720

0.05

21.81

0.05

0.04

0.05

0.81

0.74

Security

SCE9

CRC

DOC

CAC

DMAC

DTC

100

50

Data processing

System

DMA

200

Note 1. The values are guaranteed by design.

Note 2. LDO and Leak are internal voltage regulator’s current and MCU’s leakage current.

It is selected according to the temperature of Ta.

Note 3. Δ(Tj-Ta) = 20 °C is considered to measure the current.

Note 4. To determine the current consumption per channel or unit, divide Current [mA] by the number of channels, groups or units.

Table 2.13 shows the outline of operation for each unit.

Table 2.13

Peripheral

GPT

Outline of operation for each unit (1 of 2)

Outline of operation

Operating modes is set to saw-wave PWM mode.

GPT is operating with PCLKD.

POEG

Only clear module stop bit.

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RA6M4 Datasheet

2. Electrical Characteristics

Table 2.13

Peripheral

AGT

Outline of operation for each unit (2 of 2)

Outline of operation

AGT is operating with PCLKB.

RTC is operating with LOCO.

WDT is operating with PCLKB.

IWDT is operating with IWDTCLK.

RTC

WDT

IWDT

ETHERC

Operation modes is set to full-duplex mode.

ETHERC is operating using Reduced Media Independent Interface (RMII).

USBFS

Transfer types is set to bulk transfer.

USBFS is operating using Full-speed transfer (12 Mbps).

SCI

IIC

SCI is transmitting data in clock synchronous mode.

Communication format is set to I2C-bus format.

IIC is transmitting data in master mode.

CAN

SPI

CAN is transmitting and receiving data in self-test mode 1.

SPI mode is set to SPI operation (4-wire method).

SPI master/slave mode is set to master mode.

SPI is transmitting 8-bit width data.

OSPI

Transfer mode is single continuous write mode.

OSPI is issuing memory write command to OctaRAM.

QSPI

SSIE

QSPI is issuing Fast Read Quad I/O Instruction.

Communication mode is set to Master.

System word length is set to 32 bits.

Data word length is set to 20 bits.

SSIE is transmitting data using I2S format.

SDHI

Transfer bus mode is set to 4-bit wide bus mode.

SDHI is issuing CMD24 (single-block write).

ADC12

Resolution is set to 12-bit accuracy.

Data registers is set to A/D-converted value addition mode.

ADC12 is converting the analog input in continuous scan mode.

DAC12

TSN

DAC12 is outputting the conversion result while updating the value of data register.

TSN is operating.

CTSU

ELC

CTSU is operating in self-capacitance single scan mode.

Only clear module stop bit.

SCE9

CRC

DOC

CAC

SCE9 is executing built-in self test.

CRC is generating CRC code using 32-bit CRC32-C polynomial.

DOC is operating in data addition mode.

Measurement target clocks is set to PCLKB.

Measurement reference clocks is set to PCLKB.

CAC is measuring the clock frequency accuracy.

DMAC

DTC

Bit length of transfer data is set to 32 bits.

Transfer mode is set to block transfer mode.

DMAC is transferring data from SRAM0 to SRAM0.

Bit length of transfer data is set to 32 bits.

Transfer mode is set to block transfer mode.

DTC is transferring data from SRAM0 to SRAM0.

2.2.7.2

Example of T calculation

j

Assumption :

● Package 144-pin LQFP : θja = 33.0 °C/W

● Ta = 100 °C

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RA6M4 Datasheet

2. Electrical Characteristics

● I max = 70 mA

CC

● VCC = 3.5 V (VCC = AVCC = VCC_USB)

● I = 1 mA, V = VCC – 0.5 V, 12 Outputs

OH

● I = 20 mA, V = 1.0 V, 8 Outputs

OL

● I = 1 mA, V = 0.5 V, 12 Outputs

OL

● C = 8 pF, 32 pins, Input frequency = 10 MHz

in

● C

= 30 pF, 32 pins, Output frequency = 10 MHz

load

Leakage current of IO = Σ (V × I ) / Voltage + Σ ((VCC - V ) × I ) / Voltage

OL

OH

= (20 mA × 1 V) × 8 / 3.5 V + (1 mA × 0.5 V) × 12 / 3.5 V + ((VCC - (VCC - 0.5 V)) × 1 mA) × 12 / 3.5 V

= 45.7 mA + 1.71 mA + 1.71 mA

= 49.1 mA

Dynamic current of IO = Σ IO (C + C

) × IO switching frequency × Voltage

in

load

= ((8 pF × 32) × 10 MHz + (30 pF × 32) × 10 MHz) × 3.5 V

= 42.6 mA

Total power consumption = Voltage × (Leakage current + Dynamic current)

= (70 mA × 3.5 V) + (49.1 mA + 42.6 mA) × 3.5 V

= 566 mW (0.566 W)

Tj = Ta + θja × Total power consumption

= 100 °C + 33.0 °C/W × 0.566W

= 118.7 °C

2.3

AC Characteristics

Frequency

2.3.1

Table 2.14

Parameter

Operation frequency value in high-speed mode

Symbol Min

Typ

—

Max

200

100

50

Unit

Operation frequency

System clock (ICLK)

f

—

MHz

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)

—

*2

*1

—

50

—

Peripheral module clock (PCLKD)

Flash interface clock (FCLK)

—

100

50

—

External bus clock (BCLK)

EBCLK pin output

—

100

50

Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.

Note 2. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

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RA6M4 Datasheet

2. Electrical Characteristics

Table 2.15

Operation frequency value in low-speed mode

Parameter

Symbol Min

Typ

—

Max

Unit

Operation frequency

System clock (ICLK)

f

—

1

MHz

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

—

*2

—

Peripheral module clock (PCLKC)

Peripheral module clock (PCLKD)

—

1

*1

Flash interface clock (FCLK)

External bus clock (BCLK)

EBCLK pin output

—

1

Note 1. Programming or erasing the flash memory is disabled in low-speed mode.

Note 2. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

Table 2.16

Parameter

Operation frequency value in Subosc-speed mode

Symbol Min

Typ

—

Max

36.1

Unit

Operation frequency

System clock (ICLK)

f

29.4

—

kHz

Peripheral module clock (PCLKA)

Peripheral module clock (PCLKB)

—

*2

—

Peripheral module clock (PCLKC)

Peripheral module clock (PCLKD)

—

36.1

*1

29.4

Flash interface clock (FCLK)

External bus clock (BCLK)

EBCLK pin output

—

36.1

Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode.

Note 2. The ADC12 cannot be used.

2.3.2

Clock Timing

Table 2.17

Clock timing except for sub-clock oscillator (1 of 2)

Parameter

Symbol

Min

20

Typ

—

Max

Unit Test conditions

EBCLK pin output cycle time

EBCLK pin output high pulse width

EBCLK pin output low pulse width

EBCLK pin output rise time

t

f

t

f

t

—

ns

Figure 2.7

Bcyc

3.3

—

CH

—

CL

5.0

—

Cr

EBCLK pin output fall time

—

Cf

EXTAL external clock input cycle time

EXTAL external clock input high pulse width

EXTAL external clock input low pulse width

EXTAL external clock rise time

EXTAL external clock fall time

Main clock oscillator frequency

41.66

15.83

—

Figure 2.8

EXcyc

EXH

—

EXL

5.0

24

EXr

—

EXf

8

MHz —

MAIN

MAINOSCWT

LOCO

LOCOWT

*1

—

ms Figure 2.9

Main clock oscillation stabilization wait time (crystal)

LOCO clock oscillation frequency

—

29.4912 32.768 36.0448 kHz

60.4 µs

—

LOCO clock oscillation stabilization wait time

—

Figure 2.10

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2. Electrical Characteristics

Table 2.17

Clock timing except for sub-clock oscillator (2 of 2)

Parameter

Symbol

Min

Typ

15

8

Max

Unit Test conditions

kHz

MHz —

µs

ILOCO clock oscillation frequency

MOCO clock oscillation frequency

MOCO clock oscillation stabilization wait time

f

13.5

6.8

16.5

—

ILOCO

F

9.2

MOCO

t

—

15.0

—

MOCOWT

HOCO16

HOCO18

HOCO20

HOCO16

HOCO18

HOCO20

HOCO16

HOCO18

HOCO20

HOCOWT

HOCO clock oscillator oscillation

frequency

Without FLL f

15.78

17.75

19.72

15.71

17.68

19.64

16

18

20

16

18

20

16.22

18.25

20.28

16.29

18.32

20.36

16.040

18.045

20.050

64.7

MHz –20 ≤ Ta ≤ 105°C

f

–40 ≤ Ta ≤ –20°C

With FLL

f

t

15.960 16

17.955 18

19.950 20

–40 ≤ Ta ≤ 105°C

Sub-clock frequency accuracy is

±50 ppm.

*2

—

µs

—

HOCO clock oscillation stabilization wait time

HOCO period jitter

—

±85

—

ps

—

FLL stabilization wait time

PLL clock frequency

t

f

t

—

1.8

200

240

174.9

—

ms

FLLWT

120

—

MHz —

PLL

PLL2 clock frequency

—

PLL2

PLL/PLL2 clock oscillation stabilization wait time

PLL/PLL2 period jitter

—

µs

ps

Figure 2.11

PLLWT

—

±100

±300

—

PLL/PLL2 long term jitter

—

Term: 1µs, 10µs

Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as the

recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended

value.

After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm that

it is 1, and then start using the main clock oscillator.

Note 2. This is the time from release from reset state until the HOCO oscillation frequency (f

) reaches the range for guaranteed

HOCO

operation.

Table 2.18

Parameter

Clock timing for the sub-clock oscillator

Symbol

Min Typ

Max Unit Test conditions

Sub-clock frequency

f

—

32.768

—

kHz

s

—

SUB

*1

Sub-clock oscillation stabilization wait time

t

Figure 2.12

SUBOSCWT

Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the

recommended oscillation stabilization time.

After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after the

sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is recommended.

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RA6M4 Datasheet

2. Electrical Characteristics

t_Bcyc

t_CH

t_Cf

EBCLK pin output

t_Cr

t_CL

Figure 2.7

EBCLK output timing

t_Xcyc

t_XH

t_XL

EXTAL external clock input

VCC × 0.5

t_Xr

t_Xf

Figure 2.8

EXTAL external clock input timing

MOSCCR.MOSTP

Main clock oscillator output

Main clock

t_MAINOSCWT

Figure 2.9

Main clock oscillation start timing

LOCOCR.LCSTP

On-chip oscillator output

t_LOCOWT

LOCO clock

Figure 2.10

LOCO clock oscillation start timing

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RA6M4 Datasheet

2. Electrical Characteristics

PLLCR.PLLSTP

PLL2CR.PLL2STP

PLL/PLL2 circuit output

t_PLLWT

OSCSF.PLLSF

OSCSF.PLL2SF

PLL/PLL2 clock

Figure 2.11

PLL/PLL2 clock oscillation start timing

SOSCCR.SOSTP

Sub-clock oscillator output

t_SUBOSCWT

Sub-clock

Figure 2.12

Sub-clock oscillation start timing

2.3.3

Reset Timing

Table 2.19

Parameter

Reset timing

Symbol Min Typ Max Unit Test conditions

RES pulse width

Power-on

Deep Software Standby mode

t

0.7

0.6

0.3

—

ms Figure 2.13

ms Figure 2.14

ms

RESWP

RESWD

RESWS

Software Standby mode, Subosc-speed

mode

All other

t

200

—

µs

RESW

Wait time after RES cancellation

37.3 41.2 µs

324 397.7 µs

Figure 2.13

—

RESWT

RESW2

Wait time after internal reset cancellation

—

(IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error

reset, bus master MPU error reset, TrustZone error reset, Cache parity error reset)

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RA6M4 Datasheet

2. Electrical Characteristics

VCC

RES

VCCmin

t_RESWP

Internal reset signal

(low is valid)

t_RESWT

Figure 2.13

RES pin input timing under the condition that VCC exceeds V_PORvoltage threshold

t_RESWD, t_RESWS, t_RESW

RES

Internal reset signal

(low is valid)

t_RESWT

Figure 2.14

Reset input timing

2.3.4

Wakeup Timing

Table 2.20

Parameter

Timing of recovery from low power modes (1 of 2)

Symbol

Min Typ Max Unit Test conditions

*13

Recovery time from

Software Standby

mode

Crystal resonator

connected to main clock

oscillator

System clock source is

main clock oscillator

—

2.1

2.4

ms Figure 2.15

The division ratio of all

oscillators is 1.

t

SBYMC

*2

*1

*13

System clock source is

PLL with main clock

—

2.2

2.6

ms

t

SBYPC

*3

oscillator

*13

External clock input to

main clock oscillator

System clock source is

main clock oscillator

—

45

125 μs

t

SBYEX

*4

System clock source is

PLL with main clock

170 255 μs

SBYPE

*5

oscillator

*6 *11

*13

—

0.7

55

0.8

0.9

ms

System clock source is sub-clock oscillator

t

SBYSC

*7 *11

System clock source is LOCO

SBYLO

*8

130 µs

System clock source is HOCO clock oscillator

SBYHO

*9

*13

175 265 µs

35 65 µs

System clock source is PLL with HOCO

SBYPH

*10

*13

System clock source is MOCO clock oscillator

t

SBYMO

DSBY

Recovery time from

Deep Software

Standby mode

DPSBYCR.DEEPCUT[1] = 0 and

DPSWCR.WTSTS[5:0] = 0x0E

0.38 0.54 ms Figure 2.16

0.55 0.73 ms

DPSBYCR.DEEPCUT[1] = 1 and

DPSWCR.WTSTS[5:0] = 0x19

t

—

DSBY

Wait time after cancellation of Deep Software Standby mode

56

—

57

t

cyc

DSBYWT

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RA6M4 Datasheet

2. Electrical Characteristics

Table 2.20

Parameter

Timing of recovery from low power modes (2 of 2)

Symbol

Min Typ Max Unit Test conditions

*12

Recovery time from

Software Standby

mode to Snooze

mode

High-speed mode when system clock source is

HOCO (20 MHz)

t

—

μs

Figure 2.17

35

70

14

SNZ

*12

High-speed mode when system clock source is

MOCO (8 MHz)

t

—

μs

11

SNZ

Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be

determined with the following equation:

Total recovery time = recovery time for an oscillator as the system clock source + the longest tSBYOSCWT in the active oscillators -

tSBYOSCWT for the system clock + 2 LOCO cycles (when LOCO is operating) + Subosc is oscillating and MSTPC0 = 0 (CAC

module stop))

Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the

greatest value of the internal clock division setting is 1.

Note 3. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest

value of the internal clock division setting is 4.

Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and

the greatest value of the internal clock division setting is 1.

Note 5. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest

value of the internal clock division setting is 4.

Note 6. The Sub-clock oscillator frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.

Note 7. The LOCO frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.

Note 8. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1.

Note 9. The PLL frequency is 200 MHz and the greatest value of the internal clock division setting is 4.

Note 10. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1.

Note 11. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.

Note 12. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time: 16 µs (typical), 48 µs

(maximum).

Note 13. The recovery time can be calcurated with the equation of tSBYOSCWT + tSBYSEQ. And they can be determined with the fol-lowing

value and equation. For n, the greatest value is selected from among the internal clock division settings.

Wakeup time TYP

tSBYOSCWT

MAX

Unit

tSBYSEQ

tSBYOSCWT

tSBYSEQ

tSBYMC

(MSTS[7:0]*32 + 3) /

0.262

35 + 18 / fICLK + 4n / fMAIN

(MSTS[7:0]*32 + 14 /

0.236

62 + 18 / fICLK + 4n / fMAIN

µs

tSBYPC

(MSTS[7:0]*32 + 34) /

0.262

35 + 18 / fICLK + 4n / fPLL

(MSTS[7:0]*32 + 45) /

0.236

62 + 18 / fICLK + 4n / fPLL

tSBYEX

tSBYPE

tSBYSC

tSBYLO

tSBYHO

tSBYPH

tSBYMO

10

135

0

35 + 18 / fICLK + 4n / fEXMAIN 62

62 + 18 / fICLK + 4n / fEXMAIN µs

35 + 18 / fICLK + 4n / fPLL

35 + 18 / fICLK + 4n / fSUB

35 + 18 / fICLK + 4n / fLOCO

35 + 18 / fICLK + 4n / fHOCO

35 + 18 / fICLK + 4n / fPLL

35 + 18 / fICLK + 4n / fMOCO

192

62 + 18 / fICLK + 4n / fPLL

62 + 18 / fICLK + 4n / fSUB

62 + 18 / fICLK + 4n / fLOCO

62 + 18 / fICLK + 4n / fHOCO

62 + 18 / fICLK + 4n / fPLL

µs

0

20

140

0

67

202

0

62 + 18 / fICLK + 4n / fMOCO µs

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RA6M4 Datasheet

2. Electrical Characteristics

Oscillator

(system clock)

t_SBYOSCWT

t_SBYSEQ

Oscillator

(not the system clock)

ICLK

IRQ

Software Standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of the system clock oscillator is slower

Oscillator

(system clock)

t_SBYSEQ

t_SBYOSCWT

Oscillator

(not the system clock)

t_SBYOSCWT

ICLK

IRQ

Software Standby mode

t_SBYMC,t_SBYEX,t_SBYPC,t_SBYPE,

t_SBYPH,t_SBYSC,t_SBYHO,t_SBYLO

When stabilization of an oscillator other than the system clock is slower

Figure 2.15

Software Standby mode cancellation timing

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RA6M4 Datasheet

2. Electrical Characteristics

Oscillator

IRQ

Deep Software Standby

reset

(low is valid)

Internal reset

(low is valid)

Deep Software Standby mode

t_DSBY

t_DSBYWT

Reset exception handling start

Figure 2.16

Deep Software Standby mode cancellation timing

Oscillator

ICLK (except DTC, SRAM)

ICLK (to DTC, SRAM)^*1PCLK

IRQ

Software Standby mode

Snooze mode

t_SNZ

Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.17

Recovery timing from Software Standby mode to Snooze mode

2.3.5

NMI and IRQ Noise Filter

Table 2.21

Parameter

NMI and IRQ noise filter

Symbol

Min

Typ

—

Max

—

Unit

Test conditions

NMI pulse

width

t

200

ns

NMI digital filter

disabled

t

× 2 ≤ 200 ns

× 2 > 200 ns

NMIW

Pcyc

*1

—

t

× 2

Pcyc

200

—

NMI digital filter

enabled

t

× 3 ≤ 200 ns

× 3 > 200 ns

NMICK

*2

t

× 3.5

NMICK

IRQ pulse

width

t

200

—

ns

IRQ digital filter

disabled

t

× 2 ≤ 200 ns

× 2 > 200 ns

IRQW

Pcyc

*1

t

× 2

Pcyc

200

—

IRQ digital filter

enabled

t

× 3 ≤ 200 ns

× 3 > 200 ns

IRQCK

*3

t

× 3.5

IRQCK

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RA6M4 Datasheet

2. Electrical Characteristics

Note:

200 ns minimum in Software Standby mode.

If the clock source is switched, add 4 clock cycles of the switched source.

Note 1. t

Note 2. t

Note 3. t

indicates the PCLKB cycle.

Pcyc

indicates the cycle of the NMI digital filter sampling clock.

indicates the cycle of the IRQi digital filter sampling clock.

NMICK

IRQCK

NMI

t_NMIW

Figure 2.18

NMI interrupt input timing

IRQ

t_IRQW

Figure 2.19

IRQ interrupt input timing

Bus Timing

2.3.6

Table 2.22

Bus timing

Condition:

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF.

EBCLK: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Others: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

—

12.5

0

Max

12.5

—

Unit

ns

Test conditions

Address delay

Byte control delay

CS delay

t

Figure 2.22 to Figure

2.25

AD

BCD

CSD

ALED

RSD

RDS

RDH

WRD

WDD

WDH

WTS

WTH

ALE delay time

RD delay

Read data setup time

Read data hold time

WR/WRn delay

Write data delay

Write data hold time

WAIT setup time

WAIT hold time

—

0

12.5

—

12.5

0

—

Figure 2.26

—

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RA6M4 Datasheet

2. Electrical Characteristics

Data cycle

T_end

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_n1

T_n2

T_W5

EBCLK

t_AD

Address bus

t_RDSt^RDH

t_AD

Address bus/

data bus

t_ALED

t^ALED

Address latch

(ALE)

t_RSD

Data read

(RD)

t_CSD

Chip select

(CSn)

Figure 2.20

Address/data multiplexed bus read access timing

Data cycle

Address cycle

T_a1

T_an

T_W1

T_W2

T_W3

T_W4

T_end

T_n1

T_n2

Tⁿ³

T_W5

EBCLK

t_AD

Address bus

t_AD

t^WDD

t^WDH

t_AD

Address bus/

data bus

t_ALED

t^ALED

Address latch

(ALE)

t_WRD

Data write

(WRm)

t_CSD

Chip select

(CSn)

Figure 2.21

Address/data multiplexed bus write access timing

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RA6M4 Datasheet

2. Electrical Characteristics

CSRWAIT: 2

RDON:1

CSON: 0

CSROFF: 2

T_W1

T_W2

T_end

T_n1

T_n2

EBCLK

Byte strobe mode

t_AD

A20 to A00

A20 to A01

BC1, BC0

1-write strobe mode

t_AD

t_BCD

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7 to CS0

t_RSD

RD (read)

t_RDS

t_RDH

D15 to D00 (read)

Figure 2.22

External bus timing for normal read cycle with bus clock synchronized

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RA6M4 Datasheet

2. Electrical Characteristics

CSWWAIT: 2

WRON: 1

WDON: 1*¹

CSWOFF: 2

WDOFF: 1*¹

T_n1

CSON:0

T_W1

T_W2

T_end

T_n2

EBCLK

Byte strobe mode

t_AD

A20 to A00

A20 to A01

BC1, BC0

1-write strobe mode

t_AD

t_BCD

Common to both byte strobe mode

and 1-write strobe mode

t_CSD

CS7 to CS0

t_WRD

WR1, WR0, WR (write)

D15 to D00 (write)

t_WDD

t_WDH

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.23

External bus timing for normal write cycle with bus clock synchronized

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RA6M4 Datasheet

2. Electrical Characteristics

CSRWAIT:2

RDON:1

CSON:0

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSPRWAIT:2

RDON:1

CSROFF:2

T^W1

T^W2

T^end

T^pw1

T^pw2

T^end

T^pw1

T^pw2

T^end

T^pw1

T^pw2

T^end

Tⁿ¹

Tⁿ²

EBCLK

Byte strobe mode

t^AD

A20 to A00

A20 to A01

BC1, BC0

1-write strobe mode

t^AD

t^BCD

Common to both byte strobe mode

and 1-write strobe mode

t^CSD

CS7 to CS0

t^RSD

RD (Read)

t^RDS

t^RDH

t^RDS

t^RDH

t^RDS

t^RDH

t^RDS

t^RDH

D15 to D00 (Read)

Figure 2.24

External bus timing for page read cycle with bus clock synchronized

CSPWWAIT:2

WRON:1

CSWWAIT:2

WRON:1

WDON:1*¹

CSON:0

CSPWWAIT:2

WRON:1

CSWOFF:2

WDOFF:1*¹

T^dw1

WDOFF:1*¹

Tⁿ¹

WDOFF:1*¹

T^dw1

WDON:1*¹

T^W2

T^end

T^pw1

T^pw2

T^pw1

T^pw2

T^W1

T^end

Tⁿ²

EBCLK

Byte strobe mode

t^AD

A20 to A00

A20 to A01

BC1, BC0

1-write strobe mode

t^AD

t^BCD

Common to both byte strobe mode

and 1-write strobe mode

t^CSD

CS7 to CS0

t^WRD

WR1, WR0, WR (write)

D15 to D00 (write)

t^WDD

t^WDH

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.25

External bus timing for page write cycle with bus clock synchronized

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RA6M4 Datasheet

2. Electrical Characteristics

CSRWAIT:3

CSWWAIT:3

T_W1

T_W2

T_W3

(T_end

)

T_end

T_n1

T_n2

EBCLK

A20 to A00

CS7 to CS0

RD (read)

WR (write)

External wait

t_WTSt_WTHt_WTSt_WTH

WAIT

Figure 2.26

External bus timing for external wait control

2.3.7

I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing

Table 2.23

I/O ports, POEG, GPT, AGT, and ADC12 trigger timing (1 of 2)

GPT32 Conditions:

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

AGT Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

I/O ports

POEG

Symbol

Min

1.5

3

Max

Unit

Test conditions

Figure 2.27

Input data pulse width

t

—

4

t

PRW

Pcyc

POEG input trigger pulse width

Input capture pulse width

Figure 2.28

POEW

GTICW

Pcyc

GPT

Single edge

1.5

2.5

—

Figure 2.29

PDcyc

Dual edge

*1

GTIOCxY output skew

(x = 0 to 3, Y = A or B)

Middle drive buffer

High drive buffer

Middle drive buffer

High drive buffer

Middle drive buffer

High drive buffer

ns

Figure 2.30

t

GTISK

—

4

GTIOCxY output skew

(x = 4 to 9, Y = A or B)

—

4

—

4

GTIOCxY output skew

(x = 0 to 9, Y = A or B)

—

6

—

6

OPS output skew

t

—

5

ns

Figure 2.31

GTOSK

GTOUUP, GTOULO, GTOVUP,

GTOVLO, GTOWUP, GTOWLO

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RA6M4 Datasheet

2. Electrical Characteristics

Table 2.23

I/O ports, POEG, GPT, AGT, and ADC12 trigger timing (2 of 2)

GPT32 Conditions:

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

AGT Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

*2

AGT

AGTIO, AGTEE input cycle

100

—

ns

Figure 2.32

t

ACYC

AGTIO, AGTEE input high width, low width

AGTIO, AGTO, AGTOA, AGTOB output cycle

ADC12 trigger input pulse width

, t

40

—

ns

ACKWH ACKWL

62.5

1.5

ACYC2

ADC12

t

Figure 2.33

TRGW

Pcyc

Note:

t

: PCLKB cycle, t

: PCLKD cycle.

Pcyc

PDcyc

Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed.

Note 2. Constraints on input cycle:

When not switching the source clock: t

× 2 < t

should be satisfied.

Pcyc

ACYC

When switching the source clock: t

× 6 < t

should be satisfied.

Pcyc

ACYC

Port

t_PRW

Figure 2.27

I/O ports input timing

POEG input trigger

t_POEW

Figure 2.28

POEG input trigger timing

Input capture

t_GTICW

Figure 2.29

GPT input capture timing

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RA6M4 Datasheet

2. Electrical Characteristics

PCLKD

Output delay

GPT output

t_GTISK

Figure 2.30

GPT output delay skew

PCLKD

Output delay

GPT output

t_GTOSK

Figure 2.31

GPT output delay skew for OPS

t_ACYC

t_ACKWL

t_ACKWH

AGTIO, AGTEE

(input)

t_ACYC2

AGTIO, AGTO,

AGTOA, AGTOB

(output)

Figure 2.32

AGT input/output timing

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RA6M4 Datasheet

2. Electrical Characteristics

ADTRG0,

ADTRG1

t_TRGW

Figure 2.33

ADC12 trigger input timing

2.3.8

CAC Timing

Table 2.24

Parameter

CAC

CAC timing

Symbol Min

4.5 × t

Typ

Max

Unit

Test conditions

*1

CACREF input pulse

width

t

+ 3 × t

—

ns

—

t

≤ t

> t

CACREF

cac

PBcyc

cac

5 × t

+ 6.5 × t

—

ns

cac

PBcyc

cac

Note:

t

: PCLKB cycle.

PBcyc

Note 1. t : CAC count clock source cycle.

cac

2.3.9

SCI Timing

Table 2.25

SCI timing (1)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol Min

Max Unit Test conditions

SCI Input clock cycle

Asynchronous

t

4

—

0.6

5

t

Figure 2.34

Scyc

Pcyc

Clock synchronous

6

Input clock pulse width

Input clock rise time

Input clock fall time

Output clock cycle

t

0.4

—

t

SCKW

SCKr

SCKf

Scyc

ns

5

Asynchronous

6 (other than SCI1,

SCI2)

—

t

Pcyc

8 (SCI1, SCI2)

Clock synchronous

4

—

0.6

5

Output clock pulse width

Output clock rise time

Output clock fall time

Transmit data delay

t

0.4

—

t

SCKW

SCKr

SCKf

TXD

Scyc

ns

5

Clock synchronous master mode (internal

clock)

5

Figure 2.35

Clock synchronous slave mode (external

clock)

t

—

15

5

25

—

ns

TXD

RXS

RXH

Receive data setup time Clock synchronous master mode (internal

clock)

Clock synchronous slave mode (external

clock)

Receive data hold time Clock synchronous

5

Note:

t

: PCLKA cycle.

Pcyc

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2. Electrical Characteristics

t_SCKW

t_SCKr

t_SCKf

SCKn

t_Scyc

Note:

n = 0 to 9

Figure 2.34

SCK clock input/output timing

SCKn

t_TXD

TXDn

RXDn

t_RXSt_RXH

Note:

n = 0 to 9

Figure 2.35

SCI input/output timing in clock synchronous mode

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RA6M4 Datasheet

2. Electrical Characteristics

Table 2.26

SCI timing (2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

4

Max

65536

0.6

5

Unit

Test conditions

Simple SPI

SCK clock cycle output (master)

SCK clock cycle input (slave)

SCK clock high pulse width

SCK clock low pulse width

SCK clock rise and fall time

Data input setup time

t

Figure 2.36

SPcyc

Pcyc

6

t

0.4

—

15

5

t

SPCKWH

SPcyc

SPCKWL

SPcyc

, t

ns

SPCKr SPCKf

master

slave

—

Figure 2.37 to Figure

2.40

SU

—

Data input hold time

SS input setup time

SS input hold time

Data output delay

t

5

—

H

1

—

t

LEAD

LAG

OD

SPcyc

1

—

master

slave

—

-5

—

5

ns

25

ns

Data output hold time

Data rise and fall time

SS input rise and fall time

Slave access time

t

—

OH

, t

Dr Df

5

ns

, t

5

ns

SSLr SSLf

3 × t

+ 25 ns

Figure 2.40

SA

Pcyc

Slave output release time

REL

Pcyc

Note:

t

: PCLKA cycle.

Pcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_OH

SCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

SCKn

slave select input

V_IL

t_SPCKWL

V_IL

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Note:

n = 0 to 9

Figure 2.36

SCI simple SPI mode clock timing

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2. Electrical Characteristics

SCKn

CKPOL = 0

output

SCKn

CKPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Note:

n = 0 to 9

Figure 2.37

SCI simple SPI mode timing for master when CKPH = 1

SCKn

CKPOL = 1

output

SCKn

CKPOL = 0

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Note:

n = 0 to 9

Figure 2.38

SCI simple SPI mode timing for master when CKPH = 0

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2. Electrical Characteristics

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 0

input

SCKn

CKPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

Note:

n = 0 to 9

Figure 2.39

SCI simple SPI mode timing for slave when CKPH = 1

t_TD

SSn

input

t_LEAD

t_LAG

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(Last data)

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

LSB IN

Note:

n = 0 to 9

Figure 2.40

SCI simple SPI mode timing for slave when CKPH = 0

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2. Electrical Characteristics

Table 2.27

SCI timing (3)

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

—

0

Max

1000

300

Unit

ns

Test conditions

Simple IIC

(Standard mode)

SDA input rise time

t

Figure 2.41

Sr

SDA input fall time

ns

Sf

SDA input spike pulse removal time

Data input setup time

Data input hold time

4 × t

—

ns

SP

IICcyc

250

0

ns

SDAS

—

ns

SDAH

*1

SCL, SDA capacitive load

—

400

pF

C

b

Simple IIC

(Fast mode)

SDA input rise time

t

—

0

300

4 × t

—

ns

pF

Figure 2.41

Sr

SDA input fall time

Sf

SDA input spike pulse removal time

Data input setup time

Data input hold time

SP

SDAS

IICcyc

100

0

—

SDAH

*1

SCL, SDA capacitive load

—

400

C

b

Note:

t

: IIC internal reference clock (IICφ) cycle.

IICcyc

Note 1. C indicates the total capacity of the bus line.

b

V_IH

SDAn

V_IL

t_Sr

t_Sf

t_SP

SCLn

P*¹

S*¹

Sr*¹

t_SDAH

t^SDAS

Test conditions:

V_IH= VCC × 0.7, V_IL= VCC × 0.3

V_OL= 0.6 V, I_OL= 6 mA

Note:

n = 0 to 9

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.41

SCI simple IIC mode timing

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2. Electrical Characteristics

2.3.10

SPI Timing

Table 2.28

SPI timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

SPI RSPCK clock cycle

Symbol

Min

2

Max

4096

—

Unit

Test conditions

Master

Slave

t

Figure 2.42

SPcyc

Pcyc

4

RSPCK clock high

pulse width

Master

(t

– t

) /

ns

SPCKWH

SPcyc

SPCKr

SPCKf

2 – 3

Slave

0.4

0.6

—

t

SPcyc

RSPCK clock low

pulse width

Master

t

(t

ns

SPCKWL

SPcyc

SPCKr

SPCKf

2 – 3

0.4

—

4

Slave

0.6

5

t

SPcyc

RSPCK clock rise and Master

fall time

t

, t

ns

µs

ns

SPCKr SPCKf

Slave

1

Data input setup time Master

Slave

—

Figure 2.43 to Figure

2.48

SU

HF

5

Data input hold time

Master

0

ns

(PCLKA

division ratio

set to 1/2)

Master

t

H

t

—

Pcyc

(PCLKA

division ratio

set to a value

other than

1/2)

Slave

t

20

—

H

*1

SSL setup time

SSL hold time

Master

N × t

+

ns

N × t

- 10

LEAD

SPcyc

*1

100

Slave

4 × t

N × t

—

ns

Pcyc

*2

Master

t

N × t

- 10

LAG

SPcyc

*2

100

Slave

4 × t

—

ns

Pcyc

Data output delay

Master

t

6.3

20

OD1

OD2

OD

Slave

—

0

Data output hold time Master

Slave

—

ns

OH

0

—

Successive

Master

t

+ 2 × t

8 × t

+ 2 ns

TD

SPcyc

Pcyc

SPcyc

transmission delay

× t

Pcyc

Slave

4 × t

—

Pcyc

MOSI and MISO rise Output

t

, t

5

ns

µs

ns

µs

ns

Dr Df

and fall time

Input

—

1

SSL rise and fall time Output

Input

, t

—

5

SSLr SSLf

—

1

Slave access time

Slave output release time

t

—

25

Figure 2.47 and

Figure 2.48

SA

—

REL

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2. Electrical Characteristics

Note:

t

: PCLKA cycle.

Pcyc

Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SPI

interface, the AC portion of the electrical characteristics is measured for each group.

Note 1. N is set to an integer from 1 to 8 by the SPCKD register.

Note 2. N is set to an integer from 1 to 8 by the SSLND register.

t_SPCKr

t_SPCKf

t_SPCKWH

V_OH

V_OL

V_OH

RSPCKn

master select

output

V_OL

t_SPCKWL

V_OL

t_SPcyc

t_SPCKr

t_SPCKf

t_SPCKWH

V_IH

V_IL

V_IH

RSPCKn

slave select input

V_IL

t_SPCKWL

V_IL

t_SPcyc

V_OH= 0.7 × VCC, V_OL= 0.3 × VCC, V_IH= 0.7 × VCC, V_IL= 0.3 × VCC

Note:

n = A or B

Figure 2.42

SPI clock timing

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_Dr,t_Df

t_OH

t_OD2

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

t_OD1

Note:

n = A or B

Figure 2.43

SPI timing for master when CPHA = 0

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2. Electrical Characteristics

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_HF

MISOn

input

LSB IN

MSB IN

DATA

MSB IN

t_Dr,t_Df

t_OH

t_OD2

MOSIn

output

MSB OUT

DATA

LSB OUT

IDLE

MSB OUT

t_OD1

Note:

n = A or B

Figure 2.44

SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD2

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Note:

n = A or B

Figure 2.45

SPI timing for master when CPHA = 1

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2. Electrical Characteristics

SPI

t_TD

SSLn0 to

SSLn3

output

t_LEAD

t_LAG

t_SSLr,t_SSLf

RSPCKn

CPOL = 0

output

RSPCKn

CPOL = 1

output

t_SU

t_HF

t_H

MISOn

input

MSB IN

DATA

LSB IN

MSB IN

t_OH

t_OD2

t_Dr,t_Df

MOSIn

output

MSB OUT

LSB OUT

IDLE

MSB OUT

Note:

n = A or B

Figure 2.46

RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2

t_TD

SSLn0

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

MSB OUT

DATA

LSB OUT

LSB IN

MSB IN

MSB OUT

MSB IN

t_SU

t_H

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

Note:

n = A or B

Figure 2.47

SPI timing for slave when CPHA = 0

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2. Electrical Characteristics

t_TD

SSLn0

input

t_LEAD

t_LAG

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

t_SA

t_OH

t_OD

t_REL

MISOn

output

LSB OUT

(Last data)

MSB OUT

t_H

DATA

LSB OUT

MSB OUT

MSB IN

t_SU

t_Dr,t_Df

MOSIn

input

MSB IN

DATA

LSB IN

Note:

n = A or B

Figure 2.48

2.3.11

SPI timing for slave when CPHA = 1

QSPI Timing

Table 2.29

QSPI timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

48

Unit

Test conditions

QSPI

QSPCK clock cycle

t

2

t

Figure 2.49

QScyc

QSWH

Pcyc

QSPCK clock high pulse

width

t

× 0.4

—

ns

QScyc

QSPCK clock low pulse

width

t

—

QSWL

QScyc

Data input setup time

Data input hold time

QSSL setup time

t

10

0

—

ns

Figure 2.50

Su

—

IH

*1

*2

(N + 0.5) × t

+

(N + 0.5) × t

- 5

LEAD

Qscyc

*1

100

QSSL hold time

t

(N + 0.5) × t

ns

(N + 0.5) × t

- 5

LAG

Qscyc

*2

100

Data output delay

t

—

4

ns

OD

OH

TD

Data output hold time

–3.3

1

—

16

Successive transmission

delay

t

QScyc

Note:

t

: PCLKA cycle.

Pcyc

Note 1. N is set to 0 or 1 in SFMSLD.

Note 2. N is set to 0 or 1 in SFMSHD.

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2. Electrical Characteristics

t_QSWH

t_QSWL

QSPCLK output

t_QScyc

Figure 2.49

QSPI clock timing

t_TD

QSSL

output

t_LEAD

t_LAG

QSPCLK

output

t_SU

t_H

QIO0-3

input

MSB IN

DATA

LSB IN

t_OH

t_OD

QIO0-3

output

MSB OUT

DATA

LSB OUT

IDLE

Figure 2.50

2.3.12

Transmit and receive timing

OSPI Timing

Table 2.30

OSPI timing (1 of 2)

(1) Conditions: High speed high drive output is selected in the port drive capability bit in the PmnPFS register for the following pins:

OM_SCLK, OM_DQS, OM_SIO0-7.

(2) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_CS0,

OM_CS1.

Parameter

Symbol

Min

—

Max

50

Unit

MHz

Test conditions

OM_SCLK

clock

frequency

SPI

f

Figure 2.51

OCcyc

SOPI/DOPI

—

100

OM_SCLK high pulse width

OM_SCLK low pulse width

OM_SCLK rise time

t

0.475

—

0.525

1.8

t

OCwh

OCwl

OCr

OCcyc

ns

OM_SCLK fall time

—

1.8

OCf

OM_CS

SPI/SOPI

1.5 × t

– 10.4

2.5 × t + 6.9

OCcyc

Figure 2.52, Figure

2.53

OCLEAD

OCcyc

setup time

(Minimum register settings) (Maximum register settings)

DOPI

t

1.25 × t – 7.9 2.25 × t + 4.4

ns

Figure 2.54

OCLEAD

OCcyc

(Minimum register settings) (Maximum register settings)

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2. Electrical Characteristics

Table 2.30

OSPI timing (2 of 2)

(1) Conditions: High speed high drive output is selected in the port drive capability bit in the PmnPFS register for the following pins:

OM_SCLK, OM_DQS, OM_SIO0-7.

(2) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_CS0,

OM_CS1.

Parameter

Symbol

Min

Max

Unit

Test conditions

OM_CS hold SPI/SOPI

time

t

1 × t

– 6.9

4.5 × t + 10.4

OCcyc

ns

Figure 2.52, Figure

2.53

OCLAG

OCTD

OCcyc

(Minimum register settings) (Maximum register settings)

DOPI read

3.25 × t – 4.4 4.25 × t + 7.9

(Minimum register settings) (Maximum register settings)

ns

Figure 2.54

OCcyc

DOPI write

0.75 × t – 4.4 4.25 × t + 7.9

(Minimum register settings) (Maximum register settings)

OCcyc

Continuous transfer delay

time

1 × t – 1 8.5 × t + 1

Figure 2.52, Figure

2.53, Figure 2.54

OCcyc

(Minimum register settings) (Maximum register settings)

Data input

setup time

SPI SCLK

base point

10.5

—

Figure 2.52

SU

Data input

hold time

0.5

—

H

Data input

setup time

SOPI/DOPI

DQS base

point

-1.3

3.25

—

Figure 2.53, Figure

2.54

SU

*1

Data input

hold time

—

H

Skew of Clock to Data

Strobe

20

2.65

—

CKDS

OD

OH

BOFF

Data output SPI/SOPI

delay time

—

Figure 2.52, Figure

2.53

Data output

hold time

-2.65

2.1

Data output SOPI

buffer off

—

Figure 2.53

time

*1

Data output

delay time

t

—

3.65

—

ns

Figure 2.54, Figure

2.55

DOPI

OD

Data output

hold time

1.1

OH

Data output DOPI

buffer off

time

—

Figure 2.54

Figure 2.56

BOFF

DQS refresh input setup

time

t

20

—

ns

DQSS

DQSH

DQS refresh input hold

time

0.5 × tOCcyc

Note:

t

indicates the OM_SCLK cycle.

OCcyc

Note 1. OM_SCLK frequency: 100 MHz

t_OCwh

t_OCwl

OM_SCLK output

t_OCcyc

Figure 2.51

Clock Timing

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2. Electrical Characteristics

t^OCTD

OM_CS0

OM_CS1

t^OCLAG

t^OCLEAD

OM_SCLK

t^OD

t^OH

OM_SIO0

OM_SIO1

t^SU

t^H

Figure 2.52

SPI Transfer Format Transmission and Reception Timing

t^OCTD

OM_CS0

OM_CS1

t^OCLEAD

t^OCLAG

OM_SCLK

t^CKDS

OM_DQS

t^OH

t^BOFF

t^OD

t^SU

t^H

OM_SIO7 to

OM_SIO0

Figure 2.53

SOPI Transfer Format Transmission and Reception Timing

t_OCTD

OM_CS0

OM_CS1

t_OCLEAD

t^OCLAG

OM_SCLK

OM_DQS

t^CKDS

t^OD

t^OH

t^BOFF

t^SU

Dn

t^H

OM_SIO7 to

OM_SIO0

Dn Dn+1 Dn+1

47:40 39:32 31:24 23:16 15:8 7:0

A

B

A

B

Figure 2.54

DOPI Transfer Format Transmission and Reception Timing

t_OCTD

OM_CS0

OM_CS1

t_OCLEAD

t_OCLAG

OM_SCLK

OM_DQS

t_OD

t_OH

t_OD

t_OH

t_OD

t_OH

OM_SIO7 to

OM_SIO0

Dn

A

Dn Dn+1 Dn+1

47:40 39:32 31:24 23:16 15:8 7:0

B

A

B

Figure 2.55

DOPI Transfer Format Transmission Timing

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2. Electrical Characteristics

OM_CS1

3 × t_OCcyc

OM_SCLK

OM_DQS

t_DQSS

t_DQSH

OM_SIO7 to

OM_SIO0

47:40 39:32 31:24 23:16 15:8 7:0

DQS Refresh input Timing (OctaRAM^™Read/Write)

Figure 2.56

2.3.13

IIC Timing

Table 2.31

IIC timing (1) (1 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B, SDA1_B, SCL1_B.

(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.

(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Test

Parameter

Symbol

Min

Max

—

Unit conditions

IIC

SCL input cycle time

SCL input high pulse width

SCL input low pulse width

SCL, SDA rise time

t

6 (12) × t

+ 1300

IICcyc

ns

Figure 2.57

SCL

SCLH

SCLL

Sr

(Standard mode,

SMBus)

ICFER.FMPE = 0

3 (6) × t

+ 300

—

IICcyc

3 (6) × t

—

0

1000

300

1 (4) × t

SCL, SDA fall time

Sf

SCL, SDA input spike pulse

removal time

SP

IICcyc

SDA input bus free time when

wakeup function is disabled

t

3 (6) × t

+ 300

—

ns

BUF

IICcyc

SDA input bus free time when

wakeup function is enabled

3 (6) × t

300

+ 4 × t

+

IICcyc

Pcyc

START condition input hold time

when wakeup function is disabled

t

+ 300

IICcyc

STAH

STAS

START condition input hold time

when wakeup function is enabled

1 (5) × t

1000

+ t

+ 300

Pcyc

IICcyc

Repeated START condition input

setup time

STOP condition input setup time

Data input setup time

t

1000

—

ns

pF

STOS

SDAS

SDAH

t

+ 50

—

IICcyc

Data input hold time

0

—

SCL, SDA capacitive load

C

—

400

b

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2. Electrical Characteristics

Table 2.31

IIC timing (1) (2 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,

SCL0_B, SDA1_B, SCL1_B.

(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.

(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Test

Parameter

Symbol

Min

Max

—

Unit conditions

IIC

SCL input cycle time

t

6 (12) × t

+ 600

IICcyc

ns

Figure 2.57

SCL

SCLH

SCLL

Sr

(Fast mode)

SCL input high pulse width

SCL input low pulse width

SCL, SDA rise time

3 (6) × t

+ 300

—

IICcyc

—

20 × (external pullup

voltage/5.5V)

300

*1

SCL, SDA fall time

t

20 × (external pullup

voltage/5.5V)

300

ns

Sf

*1

SCL, SDA input spike pulse

removal time

t

0

1 (4) × t

ns

SP

IICcyc

SDA input bus free time when

wakeup function is disabled

3 (6) × t

+ 300

—

BUF

IICcyc

SDA input bus free time when

wakeup function is enabled

3 (6) × t

300

+ 4 × t

+

IICcyc

Pcyc

START condition input hold time

when wakeup function is disabled

t

+ 300

IICcyc

STAH

STAS

START condition input hold time

when wakeup function is enabled

1 (5) × t

300

+ t

+ 300

Pcyc

IICcyc

Repeated START condition input

setup time

STOP condition input setup time

Data input setup time

t

300

—

ns

pF

STOS

SDAS

SDAH

t

+ 50

—

IICcyc

Data input hold time

0

—

SCL, SDA capacitive load

C

—

400

b

Note:

t

: IIC internal reference clock (IICφ) cycle, t

: PCLKB cycle.

Pcyc

IICcyc

Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC

interface, the AC portion of the electrical characteristics is measured for each group.

Note 1. Only supported for SCL0_A, SDA0_A, SCL1_A, and SDA1_A.

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2. Electrical Characteristics

Table 2.32

IIC timing (2)

Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol Min

Max

Unit Test conditions

IIC

SCL input cycle time

t

6 (12) × t

240

+

IICcyc

—

ns

Figure 2.57

SCL

(Fast-mode+)

ICFER.FMPE = 1

SCL input high pulse width

SCL input low pulse width

SCL, SDA rise time

t

3 (6) × t

—

+ 120

—

ns

SCLH

SCLL

Sr

IICcyc

—

IICcyc

120

SCL, SDA fall time

20 × (external

pullup voltage/

5.5V)

Sf

SCL, SDA input spike pulse

removal time

t

0

1 (4) × tIICcyc

ns

SP

SDA input bus free time when

wakeup function is disabled

3 (6) × t

+ 120

+ 4 ×

—

BUF

IICcyc

SDA input bus free time when

wakeup function is enabled

3 (6) × t

t

+ 120

Pcyc

Start condition input hold time

when wakeup function is disabled

t

+ 120

—

ns

STAH

IICcyc

START condition input hold time

when wakeup function is enabled

1 (5) × t

+

IICcyc

t

+ 120

Pcyc

Restart condition input setup time

Stop condition input setup time

Data input setup time

t

120

—

ns

pF

STAS

STOS

SDAS

—

t

+ 30

—

IICcyc

Data input hold time

0

—

SDAH

*1

SCL, SDA capacitive load

—

550

C

b

Note:

t

: IIC internal reference clock (IICφ) cycle, t

: PCLKB cycle.

Pcyc

IICcyc

Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 1. Cb indicates the total capacity of the bus line.

V_IH

SDA0 and SDA1

V_IL

t_BUF

t_SCLH

t_STAS

t_STOS

t_STAH

t_SP

SCL0 and SCL1

P*¹

S*¹

t_Sf

Sr*¹

t_SCLL

t_Sr

t^SDAS

t_SCL

t_SDAH

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

I²C bus interface input/output timing

Figure 2.57

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2. Electrical Characteristics

2.3.14

SSIE Timing

Table 2.33

SSIE timing

(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.

(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the

AC portion of the electrical characteristics is measured for each group.

Target specification

Parameter

Symbol

Min.

80

Max.

—

Unit

ns

Comments

SSIBCK0

Cycle

Master

Slave

t

Figure 2.58

O

80

—

ns

I

High level/ low Master

level

/t

0.35

—

t

HC LC

O

I

Slave

—

Rising time/

falling time

Master

Slave

t

/t

0.15

—

/ t

RC FC

O

I

—

I

SSILRCK0/

SSIFS0,

SSITXD0,

SSIRXD0,

SSIDATA0

Input set up

time

Master

Slave

t

12

ns

Figure 2.60,

Figure 2.61

SR

12

—

Input hold time Master

Slave

8

—

HR

15

—

Output delay

time

Master

Slave

-10

0

5

DTR

20

Figure 2.60,

Figure 2.61

*1

Output delay

time from

Slave

t

—

20

ns

Figure 2.62

DTRW

SSILRCK0/

SSIFS0 change

GTIOC2A,

AUDIO_CLK

Cycle

t

20

—

ns

Figure 2.59

EXcyc

High level/ low level

/t

0.4

0.6

t

EXcyc

EXL EXH

Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate

transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA0 pin.

t_HC

t_RC

t_FC

t_LC

SSIBCK0

t_O, t_I

Figure 2.58

SSIE clock input/output timing

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2. Electrical Characteristics

t_EXcyc

t_EXH

t_EXL

GTIOC2A,

AUDIO_CLK

(input)

1/2 VCC

t_EXf

t_EXr

Figure 2.59

Clock input timing

SSIBCK0

(Input or Output)

SSILRCK0/SSIFS0 (input),

SSIRXD0,

SSIDATA0 (input)

t_SR

t_HR

SSILRCK0/SSIFS0 (output),

SSITXD0,

SSIDATA0 (output)

t_DTR

Figure 2.60

SSIE data transmit and receive timing when SSICR.BCKP = 0

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2. Electrical Characteristics

SSIBCK0

(Input or Output)

SSILRCK0/SSIFS0 (input),

SSIRXD0,

SSIDATA0 (input)

t_SR

t_HR

SSILRCK0/SSIFS0 (output),

SSITXD0,

SSIDATA0 (output)

t_DTR

Figure 2.61

SSIE data transmit and receive timing when SSICR.BCKP = 1

SSILRCK0/SSIFS0 (input)

SSITXD0,

SSIDATA0 (output)

t_DTRW

MSB bit output delay after SSILRCK0/SSIFS0 change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.

Figure 2.62

2.3.15

SSIE data output delay after SSILRCK0/SSIFS0 change

SD/MMC Host Interface Timing

Table 2.34

SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Parameter

Symbol

Min

20

Max

—

3

Unit

ns

Test conditions

SDCLK clock cycle

T

Figure 2.63

SDCYC

SDWH

SDWL

SDLH

SDCLK clock high pulse width

SDCLK clock low pulse width

SDCLK clock rise time

6.5

—

SDCLK clock fall time

—

3

SDHL

SDCMD/SDDAT output data delay

SDCMD/SDDAT input data setup

SDCMD/SDDAT input data hold

–7

4

SDODLY

SDIS

4.5

1.5

—

SDIH

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2. Electrical Characteristics

Note:

Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SD/MMC

Host interface, the AC portion of the electrical characteristics is measured for each group.

T_SDCYC

T_SDWL

T_SDWH

SDnCLK

(output)

T_SDLH

T_SDHL

T_SDODLY(max)

T_SDODLY(min)

SDnCMD/SDnDATm

(output)

T_SDIS

T_SDIH

SDnCMD/SDnDATm

(input)

n = 0, 1, m = 0 to 7

Figure 2.63

2.3.16

SD/MMC Host Interface signal timing

ETHERC Timing

Table 2.35

ETHERC timing (1 of 2)

Conditions: ETHERC (RMII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:

ET0_MDC, ET0_MDIO.

For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

ETHERC (MII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

20

Max

Unit

ns

Test conditions

ETHERC

(RMII)

REF50CK0 cycle time

T

—

Figure 2.64 to

Figure 2.67

ck

REF50CK0 frequency, typical 50 MHz

REF50CK0 duty

—

50 + 100 ppm

MHz

%

35

65

REF50CK0 rise/fall time

T

0.5

2.5

3.5

12.0

ns

ckr/ckf

*1

ns

RMII_xxxx output delay

co

*2

3

—

ns

RMII_xxxx setup time

su

*2

1

—

RMII_xxxx hold time

hd

*1 *2

T /T

r

0.5

1

4

RMII_xxxx , rise/fall time

f

ET0_WOL output delay

t

23.5

Figure 2.68

WOLd

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2. Electrical Characteristics

Table 2.35

ETHERC timing (2 of 2)

Conditions: ETHERC (RMII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:

ET0_MDC, ET0_MDIO.

For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

ETHERC (MII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

40

1

Max

—

Unit

ns

Test conditions

—

ETHERC (MII) ET0_TX_CLK cycle time

ET0_TX_EN output delay

t

Tcyc

20

—

Figure 2.69

TENd

MTDd

CRSs

CRSh

COLs

COLh

TRcyc

RDVs

RDVh

MRDs

MRDh

RERs

RESh

WOLd

ET0_ETXD0 to ET_ETXD3 output delay

1

ET0_CRS setup time

10

40

10

1

ET0_CRS hold time

—

ET0_COL setup time

—

Figure 2.70

ET0_COL hold time

—

ET0_RX_CLK cycle time

ET0_RX_DV setup time

ET0_RX_DV hold time

—

Figure 2.71

—

ET0_ERXD0 to ET_ERXD3 setup time

ET0_ERXD0 to ET_ERXD3 hold time

ET0_RX_ER setup time

ET0_RX_ER hold time

—

Figure 2.72

Figure 2.73

—

ET0_WOL output delay

23.5

Note:

The following pins must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership.

For the ETHERC (RMII) Host interface, the AC portion of the electrical characteristics is measured for each group. REF50CK0_A,

REF50CK0_B, RMII0_xxxx_A, RMII0_xxxx_B.

Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0.

Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER.

Tck

90%

Tckr

REF50CK0 50%

Tckf

Tco

10%

Tsu

Thd

Tr

Tf

90%

Change

in signal

level

Change

in signal

level

RMII_xxxx^*150%

Change in

signal level

Signal

10%

Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0, RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER

Figure 2.64

REF50CK0 and RMII signal timing

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2. Electrical Characteristics

T^CK

REF50CK0

T^CO

RMII_TXD_EN

T^CO

RMII_TXD1,

RMII_TXD0

Preamble

SFD

DATA

CRC

Figure 2.65

RMII transmission timing

REF50CK0

Tsu

Thd

RMII_CRS_DV

Thd

Tsu

RMII_RXD1,

RMII_RXD0

Preamble

DATA

CRC

SFD

RMII_RX_ER

L

Figure 2.66

RMII reception timing in normal operation

REF50CK0

RMII_CRS_DV

RMII_RXD1,

RMII_RXD0

Preamble

SFD

DATA

xxxx

Thd

Tsu

RMII_RX_ER

Figure 2.67

RMII reception timing when an error occurs

REF50CK0

ET0_WOL

t^WOLd

Figure 2.68

WOL output timing for RMII

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2. Electrical Characteristics

ET0_TX_CLK

ET0_TX_EN

t^TENd

t^MTDd

Preamble

SFD

DATA

CRC

ET0_ETXD[3:0]

ET0_TX_ER

t^CRSs

t^CRSh

ET0_CRS

ET0_COL

Figure 2.69

MII transmission timing in normal operation

ET0_TX_CLK

ET0_TX_EN

Preamble

JAM

ET0_ETXD[3:0]

ET0_TX_ER

ET0_CRS

t^COLs

t^COLh

ET0_COL

Figure 2.70

MII transmission timing when a conflict occurs

ET0_RX_CLK

t^RDVs

t^RDVh

ET0_RX_DV

t^MRDh

t^MRDs

Preamble

SFD

DATA

CRC

ET0_ERXD[3:0]

ET0_RX_ER

Figure 2.71

MII reception timing in normal operation

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2. Electrical Characteristics

ET0_RX_CLK

ET0_RX_DV

Preamble

SFD

DATA

xxxx

ET0_ERXD[3:0]

t^RERh

t^RERs

ET0_RX_ER

Figure 2.72

MII reception timing when an error occurs

ET0_RX_CLK

ET0_WOL

t^WOLd

Figure 2.73

WOL output timing for MII

2.4

USB Characteristics

USBFS Timing

2.4.1

Table 2.36

USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz

Parameter

Symbol

Min

2.0

—

Typ

—

Max

—

Unit

V

Test conditions

Input

characteristics

Input high voltage

Input low voltage

V

—

IH

0.8

—

V

—

IL

Differential input sensitivity

Differential common-mode range

Output high voltage

Output low voltage

Cross-over voltage

Rise time

0.2

0.8

2.8

0.0

1.3

75

V

| USB_DP - USB_DM |

—

DI

2.5

3.6

0.3

2.0

300

125

V

CM

OH

OL

CRS

Output

characteristics

V

I

= –200 µA

= 2 mA

OH

OL

V

Figure 2.74

t

ns

%

LR

LF

Fall time

75

Rise/fall time ratio

/ t

80

t / t

LR LF

Pull-up and

pull-down

USB_DP and USB_DM pull-down

resistance in host controller mode

R

14.25

24.80 kΩ

—

pd

characteristics

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2. Electrical Characteristics

90%

V_CRS

USB_DP,

USB_DM

10%

t_LR

10%

t_LF

Figure 2.74

USB_DP and USB_DM output timing in low-speed mode

Observation

point

USB_DP

200 pF to

600 pF

3.6 V

1.5 K

27 

USB_DM

200 pF to

600 pF

Figure 2.75

Table 2.37

Test circuit in low-speed mode

USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz

Parameter

Symbol

Min

2.0

—

Typ

—

Max

—

Unit

V

Test conditions

Input

characteristics

Input high voltage

Input low voltage

V

—

IH

0.8

—

V

—

IL

Differential input sensitivity

Differential common-mode range

Output high voltage

Output low voltage

Cross-over voltage

Rise time

0.2

0.8

2.8

0.0

1.3

4

V

| USB_DP - USB_DM |

—

DI

2.5

3.6

0.3

2.0

20

V

CM

OH

OL

CRS

Output

characteristics

V

I

= –200 µA

= 2 mA

OH

OL

V

Figure 2.76

t

ns

%

Ω

LR

LF

Fall time

4

20

Rise/fall time ratio

Output resistance

/ t

90

111.11

44

t / t

FR FF

LR LF

Z

28

USBFS: Rs = 27 Ω included

During idle state

DRV

Pull-up and

pull-down

characteristics

DM pull-up resistance in device controller

mode

R

0.900

1.425

1.575 kΩ

3.090 kΩ

pu

pd

During transmission and

reception

USB_DP and USB_DM pull-down

resistance in host controller mode

R

14.25

—

24.80 kΩ

—

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2. Electrical Characteristics

90%

V_CRS

USB_DP,

USB_DM

10%

t_FR

10%

t_FF

Figure 2.76

USB_DP and USB_DM output timing in full-speed mode

Observation

point

USB_DP

USB_DM

50 pF

27 

Figure 2.77

Table 2.38

Test circuit in full-speed mode

USBFS characteristics (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz

Parameter

Symbol

Min

25

Typ

—

Max

175

13

Unit

µA

V

Test conditions

Battery Charging D+ sink current

Specification

I

—

DP_SINK

DM_SINK

DP_SRC

D- sink current

25

—

DCD source current

Data detection voltage

D+ source voltage

D- source voltage

7

—

V

0.25

0.5

—

0.4

0.7

—

DAT_REF

DP_SRC

DM_SRC

—

V

Outout current = 250 µA

—

V

2.5

ADC12 Characteristics

Table 2.39

A/D conversion characteristics for unit 0 (1 of 2)

Conditions: PCLKC = 1 to 50 MHz

Parameter

Min

1

Typ Max Unit Test conditions

Frequency

—

50

30

MHz —

Analog input capacitance

Quantization error

Resolution

—

pF

—

±0.5 —

12

LSB

Bits

—

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2. Electrical Characteristics

Table 2.39

A/D conversion characteristics for unit 0 (2 of 2)

Conditions: PCLKC = 1 to 50 MHz

Parameter

Min

Typ Max Unit Test conditions

*1

*2

High-precision high-speed

channels

(AN000 to AN005)

Permissible signal

source impedance

Max. = 1 kΩ

—

μs

Sampling in 13

states

Conversion time

0.52 (0.26)

(operation at PCLKC =

50 MHz)

Max. = 400 Ω

—

μs

Sampling in 7 states

VCC = AVCC0 = 3.0

to 3.6 V

0.40 (0.14)

3.0 V ≤ VREFH0 ≤

AVCC0

Offset error

—

±1.0 ±2.5 LSB

±2.0 ±4.5 LSB

±0.5 ±1.5 LSB

±1.0 ±2.5 LSB

—

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

*1

*2

High-precision normal-speed

channels

(AN006 to AN009, AN012,

AN013)

Permissible signal

source impedance

Max. = 1 kΩ

—

μs

Sampling in 33

states

Conversion time

(Operation at PCLKC =

50 MHz)

0.92 (0.66)

Offset error

—

±1.0 ±2.5 LSB

±2.0 ±4.5 LSB

±0.5 ±1.5 LSB

±1.0 ±2.5 LSB

—

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during

A/D conversion, values might not fall within the indicated ranges.

The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are

stable.

When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave

function. If selected, values might not fall within the indicated ranges.

●

AN100 and AN000 or AN001 or AN002

AN101 and AN000 or AN001 or AN002 or AN003

AN102 and AN000 or AN001 or AN002 or AN003 or AN004

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Note 2. Values in parentheses indicate the sampling time.

Table 2.40

A/D conversion characteristics for unit 1 (1 of 2)

Conditions: PCLKC = 1 to 50 MHz

Parameter

Min

1

Typ Max Unit Test conditions

Frequency

—

50

30

MHz —

Analog input capacitance

Quantization error

Resolution

—

pF

—

±0.5 —

12

LSB

Bits

—

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2. Electrical Characteristics

Table 2.40

A/D conversion characteristics for unit 1 (2 of 2)

Conditions: PCLKC = 1 to 50 MHz

Parameter

Min

Typ Max Unit Test conditions

*1

*2

High-precision high-speed

channels

(AN100 to AN102)

Permissible signal

source impedance

Max. = 1 kΩ

—

μs

Sampling in 13

states

Conversion time

0.52 (0.26)

(Operation at PCLKC =

50 MHz)

Max. = 400 Ω

—

μs

Sampling in 7 states

VCC = AVCC0 = 3.0

to 3.6 V

0.40 (0.14)

3.0 V ≤ VREFH ≤

AVCC0

Offset error

—

±1.0 ±2.5 LSB

±2.0 ±4.5 LSB

±0.5 ±1.5 LSB

±1.0 ±2.5 LSB

—

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

*1

*2

Normal-precision normal-

speed channels

(AN116 to AN122)

Permissible signal

source impedance

Max. = 1 kΩ

—

μs

Sampling in 33

states

Conversion time

(Operation at PCLKC =

50 MHz)

0.92 (0.66)

Offset error

—

±1.0 ±5.5 LSB

±2.0 ±7.5 LSB

±0.5 ±4.5 LSB

±1.0 ±5.5 LSB

—

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during

A/D conversion, values might not fall within the indicated ranges.

The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are

stable.

When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave

function. If selected, values might not fall within the indicated ranges.

●

AN100 and AN000 or AN001 or AN002

AN101 and AN000 or AN001 or AN002 or AN003

AN102 and AN000 or AN001 or AN002 or AN003 or AN004

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Note 2. Values in parentheses indicate the sampling time.

Table 2.41

A/D conversion characteristics for interleaving (1 of 2)

Conditions: PCLKC = 1 to 50 MHz

Parameter

Min Typ Max Unit Test conditions

Frequency

1

—

50

30

MHz —

Analog input capacitance

Quantization error

Resolution

—

pF

—

±0.5 —

12

LSB

Bits

—

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2. Electrical Characteristics

Table 2.41

A/D conversion characteristics for interleaving (2 of 2)

Conditions: PCLKC = 1 to 50 MHz

Parameter

Min Typ Max Unit Test conditions

*1

High-precision high-speed channels

(AN000 & AN100, AN001 & AN101, AN002

& AN102))

Max. = 400 Ω 0.22 —

—

µs

Sampling in 9 states

VCC = AVCC0 = 3.0 to

3.6 V

Conversion time

(operation at PCLKC = 50

MHz)

3.0 V ≤ VREFH0 ≤

AVCC0

Offset error

—

±1.0 ±2.5 LSB

±2.0 ±4.5 LSB

±0.5 ±4.5 LSB

±1.0 ±4.5 LSB

—

Full-scale error

Absolute accuracy

DNL differential nonlinearity error

INL integral nonlinearity error

Note:

These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during

A/D conversion, values might not fall within the indicated ranges.

The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are

stable.

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Table 2.42

A/D internal reference voltage characteristics

Parameter

Min

1.13

4.15

Typ

1.18

—

Max

1.23

—

Unit

V

Test conditions

A/D internal reference voltage

Sampling time

—

µs

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2. Electrical Characteristics

0xFFF

Full-scale error

Integral nonlinearity

error (INL)

A/D converter

output code

Ideal line of actual A/D

conversion characteristic

Actual A/D conversion

characteristic

Ideal A/D conversion

characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

Offset error

0x000

0

Analog input voltage

VREFH0

(full-scale)

Figure 2.78

Illustration of ADC12 characteristic terms

Absolute accuracy

Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the

actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog

input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D

conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference

voltage VREFH0 = 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the

analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D

conversion result is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical

A/D conversion characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors

are zeroed, and the actual output code.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics

and the width of the actual output code.

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2. Electrical Characteristics

Offset error

Offset error is the difference between the transition point of the ideal first output code and the actual first output code.

Full-scale error

Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.6

DAC12 Characteristics

Table 2.43

D/A conversion characteristics

Parameter

Min

Typ

Max

Unit

Test conditions

Resolution

—

12

Bits

—

Without output amplifier

Absolute accuracy

INL

—

0

—

±24

±8.0

±2.0

—

LSB

kΩ

Resistive load 2 MΩ

±2.0

±1.0

8.5

—

Resistive load 2 MΩ

DNL

—

Output impedance

Conversion time

Output voltage range

With output amplifier

INL

—

3

µs

Resistive load 2 MΩ, Capacitive load 20 pF

—

VREFH

V

—

5

±2.0

±1.0

—

±4.0

LSB

µs

—

DNL

±2.0

Conversion time

Resistive load

Capacitive load

Output voltage range

4.0

—

kΩ

pF

—

0.2

—

50

—

VREFH – 0.2

V

2.7

TSN Characteristics

Table 2.44

TSN characteristics

Parameter

Symbol

Min

—

Typ

± 1.0

4.0

Max

Unit

°C

Test conditions

Relative accuracy

Temperature slope

Output voltage (at 25 °C)

Temperature sensor start time

Sampling time

—

30

—

mV/°C

V

—

1.24

—

t

—

µs

START

—

4.15

—

µs

2.8

OSC Stop Detect Characteristics

Table 2.45

Parameter

Oscillation stop detection circuit characteristics

Symbol

Min

Typ

Max

Unit

ms

Test conditions

Detection time

t

—

1

Figure 2.79

dr

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RA6M4 Datasheet

2. Electrical Characteristics

Main clock

tdr

OSTDSR.OSTDF

MOCO clock

ICLK

Figure 2.79

Oscillation stop detection timing

2.9

POR and LVD Characteristics

Table 2.46

Power-on reset circuit and voltage detection circuit characteristics (1)

Un

Parameter

Symbol Min

Typ

2.6

Max it

Test conditions

Voltage detection Power-on reset

level

DPSBYCR.DEEPCUT[1:0] = 00b or

01b.

V

2.5

2.7

V

Figure 2.80

POR

(POR)

DPSBYCR.DEEPCUT[1:0] = 11b.

1.8

2.25 2.7

Voltage detection circuit (LVD0)

Voltage detection circuit (LVD1)

Voltage detection circuit (LVD2)

V

2.84 2.94 3.04

2.77 2.87 2.97

2.70 2.80 2.90

2.89 2.99 3.09

2.82 2.92 3.02

2.75 2.85 2.95

2.89 2.99 3.09

2.82 2.92 3.02

2.75 2.85 2.95

Figure 2.81

Figure 2.82

Figure 2.83

det0_1

det0_2

det0_3

det1_1

det1_2

det1_3

det2_1

det2_2

det2_3

POR

Internal reset time Power-on reset time

LVD0 reset time

t

—

4.5

—

ms Figure 2.80

Figure 2.81

—

0.51

0.38

—

LVD0

LVD1 reset time

—

Figure 2.82

LVD1

LVD2 reset time

—

Figure 2.83

LVD2

*1

200

µs Figure 2.80,

Figure 2.81

Minimum VCC down time

VOFF

Response delay

t

—

200

µs Figure 2.81 to

Figure 2.83

det

LVD operation stabilization time (after LVD is enabled)

Hysteresis width (LVD1 and LVD2)

—

10

—

µs Figure 2.82,

d(E-A)

Figure 2.83

V

70

m

LVH

V

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V

, V

POR

,

det0

V

, and V

det1

for POR and LVD.

det2

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 85 of 109

RA6M4 Datasheet

2. Electrical Characteristics

t_VOFF

V_POR

VCC

Internal reset signal

(active-low)

t_det

t_POR

t_det

t_dett_POR

Figure 2.80

Power-on reset timing

t_VOFF

V_LVH

VCC

V_det0

Internal reset signal

(active-low)

t_det

t_LVD0

Figure 2.81

Voltage detection circuit timing (V_det0)

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 86 of 109

RA6M4 Datasheet

2. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det1

LVCMPCR.LVD1E

T_d(E-A)

LVD1

Comparator output

LVD1CR0.CMPE

LVD1SR.MON

Internal reset signal

(active-low)

When LVD1CR0.RN = 0

t_det

t_LVD1

t_det

When LVD1CR0.RN = 1

t_LVD1

Figure 2.82

Voltage detection circuit timing (V_det1)

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 87 of 109

RA6M4 Datasheet

2. Electrical Characteristics

t_VOFF

V_LVH

VCC

V_det2

LVCMPCR.LVD2E

T_d(E-A)

LVD2

Comparator output

LVD2CR0.CMPE

LVD2SR.MON

Internal reset signal

(active-low)

When LVD2CR0.RN = 0

t_det

t_LVD2

When LVD2CR0.RN = 1

t_LVD2

Figure 2.83

2.10

Voltage detection circuit timing (V_det2)

VBATT Characteristics

Table 2.47

Battery backup function characteristics

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.8 to 3.6 V

Parameter

Symbol

Min

2.50

2.70

Typ

2.60

—

Max

2.70

—

Unit

V

Test conditions

Voltage level for switching to battery backup

V

Figure 2.84

DETBATT

BATTSW

Lower-limit VBATT voltage for power supply

switching caused by VCC voltage drop

V

VCC-off period for starting power supply

switching

t

200

—

µs

VOFFBATT

VBATT low voltage detection level

Minimum VBATT down time

Response delay

V

1.8

200

—

1.9

—

2.0

—

V

Figure 2.85

battldet

BATTOFF

BATTdet

d(E-A)

t

µs

200

20

VBATT monitor operation stabilization time

(after VBATTMNSELR.VBATTMNSEL is

changed to 1)

—

VBATT current increase (when

VBATTMNSELR.VBATTMNSEL is 1 compared

to the case that VBATTMNSELR.VBATTMNSEL

is 0)

I

—

140

350

nA

VBATTSEL

Note:

The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage

level for switching to battery backup (V

).

DETBATT

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 88 of 109

RA6M4 Datasheet

2. Electrical Characteristics

t_VOFFBATT

V_DETBATT

VCC

V_BATT

V_BATTSW

Backup power

area

VCC supply

V_BATTsupply

VCC supply

Figure 2.84

Battery backup function characteristics

t_BATTOFF

V_battldet

VBATT

t_d(E-A)

VBATTMON

t_BATTdet

VBATTMNSEL

Figure 2.85

Battery backup function characteristics

2.11

CTSU Characteristics

Table 2.48

CTSU characteristics

Parameter

Symbol

Min

9

Typ

10

—

Max

11

Unit

nF

Test conditions

External capacitance connected to TSCAP pin

TS pin capacitive load

C

—

tscap

base

IoH

—

50

pF

Permissible output high current

Σ

—

-40

mA

When the mutual capacitance

method is applied

2.12

Flash Memory Characteristics

2.12.1

Code Flash Memory Characteristics

Table 2.49

Code flash memory characteristics (1 of 2)

Conditions: Program or erase: FCLK = 4 to 50 MHz

Read: FCLK ≤ 50 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 50 MHz

Test

conditions

*6

Parameter

Symbol Min

Typ

Max Min

Typ

0.34

22

Max

6.0

80

Unit

ms

Programming time

≤ 100 times

128-byte

8-KB

t

—

0.75 13.2

—

P128

N

PEC

49

176

704

ms

P8K

32-KB

194

88

320

ms

P32K

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 89 of 109

RA6M4 Datasheet

2. Electrical Characteristics

Table 2.49

Code flash memory characteristics (2 of 2)

Conditions: Program or erase: FCLK = 4 to 50 MHz

Read: FCLK ≤ 50 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 50 MHz

Test

conditions

*6

Parameter

Symbol Min

Typ

Max Min

Typ

Max

7.2

96

Unit

ms

Times

µs

Programming time

> 100 times

128-byte

8-KB

t

—

0.91 15.8

—

0.41

27

P128

N

PEC

60

212

848

216

864

260

P8K

32-KB

8-KB

234

78

106

43

384

120

480

144

576

—

P32K

E8K

Erasure time

≤ 100 times

N

PEC

32-KB

8-KB

283

94

157

52

E32K

E8K

Erasure time

> 100 times

N

PEC

32-KB

341

—

1040 —

189

—

E32K

*4

*1

N

—

Reprogramming/erasure cycle

10000

—

10000

—

PEC

Suspend delay during programming

Programming resume time

t

—

264

110

216

—

120

50

SPD

—

µs

PRT

First suspend delay during erasure in suspend

priority mode

—

120

µs

SESD1

Second suspend delay during erasure in suspend

priority mode

t

—

1.7

—

1.7

ms

SESD2

SEED

Suspend delay during erasure in erasure priority

mode

First erasing resume time during erasure in suspend

REST1

*5

priority mode

Second erasing resume time during erasure in

suspend priority mode

t

—

144

—

80

µs

REST2

REET

Erasing resume time during erasure in erasure

priority mode

Forced stop command

t

—

32

—

20

—

µs

FD

*2

*2 *3

Years

Data hold time

10

DRP

Ta = +85°C

30

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to

the minimum value.

Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 3. This result is obtained from reliability testing.

Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),

erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different

addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming

the same address several times as one erasure is not enabled. Overwriting is prohibited.

Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.

Note 6. The reference value at VCC = 3.3V and room temperature.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 90 of 109

RA6M4 Datasheet

2. Electrical Characteristics

• Suspension during programming

FACI command

Program

Ready

Suspend

Resume

t^SPD

FSTATR.FRDY

Not Ready

Ready

t^PRT

Programming pulse

Programming

• Suspension during erasure in suspend priority mode

FACI command

Erase

Suspend

Resume

t^SESD1

t^SESD2

FSTATR.FRDY

Erasure pulse

Not Ready

Ready

Not Ready

Ready

Not Ready

Erasing

Ready

t^REST1

t^REST2

Erasing

• Suspension during erasure in erasure priority mode

FACI command

FSTATR.FRDY

Erasure pulse

Erase

Suspend

Not Ready

Erasing

Resume

t^SEED

Not Ready

Ready

t^REET

Erasing

• Forced Stop

Forced Stop

FACI command

t^FD

FSTATR.FRDY

Not Ready

Ready

Figure 2.86

Suspension and forced stop timing for flash memory programming and erasure

2.12.2

Data Flash Memory Characteristics

Table 2.50

Data flash memory characteristics (1 of 2)

Conditions: Program or erase: FCLK = 4 to 50 MHz

Read: FCLK ≤ 50 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 50 MHz

Test

*6

Parameter

Symbol Min

Typ

Max Min

Typ

0.16

0.17

0.19

1.7

2.6

4.9

—

Max Unit conditions

Programming time

Erasure time

4-byte

t

—

0.36 3.8

0.38 4.0

0.42 4.5

—

1.7

1.8

2.0

10

15

28

30

—

ms

DP4

8-byte

DP8

16-byte

64-byte

128-byte

256-byte

4-byte

DP16

DE64

DE128

DE256

DBC4

3.1

4.7

8.9

—

18

27

50

84

—

ms

Blank check time

µs

—

µs

*1

*2

N

—

Reprogramming/erasure cycle

125000

—

125000

—

DPEC

DSPD

Suspend delay during

programming

4-byte

8-byte

16-byte

t

—

264

110

216

—

120

50

—

Programming resume time

First suspend delay during

t

—

µs

DPRT

64-byte

—

120

DSESD1

erasure in suspend priority mode

128-byte

256-byte

—

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 91 of 109

RA6M4 Datasheet

2. Electrical Characteristics

Table 2.50

Data flash memory characteristics (2 of 2)

Conditions: Program or erase: FCLK = 4 to 50 MHz

Read: FCLK ≤ 50 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 50 MHz

Test

*6

Parameter

Symbol Min

Typ

—

Max Min

Typ

—

Max Unit conditions

Second suspend delay during

64-byte

t

—

300

390

570

300

390

570

300

—

300

390

570

300

390

570

300

µs

DSESD2

erasure in suspend priority mode

128-byte

256-byte

64-byte

Suspend delay during erasing in

erasure priority mode

t

µs

DSEED

128-byte

256-byte

First erasing resume time during erasure in suspend

t

µs

DREST1

DREST2

*5

priority mode

Second erasing resume time during erasure in

suspend priority modeFirst erasing resume time

during erasure in suspend priority mode

—

126

—

70

Erasing resume time during erasure in erasure

priority mode

t

µs

DREET

Forced stop command

t

—

10

30

—

32

—

10

30

—

20

—

µs

FD

*3

*3 *4

Year

Data hold time

DRP

Ta = +85°C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),

erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different

addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address several times as one erasure is not enabled. Overwriting is prohibited.

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to

the minimum value.

Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 4. This result is obtained from reliability testing.

Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.

Note 6. The reference value at VCC = 3.3 V and room temperature.

2.12.3

Option Setting Memory Characteristics

Table 2.51

Option setting memory characteristics

Conditions: Program: FCLK = 4 to 50 MHz

Read: FCLK ≤ 50 MHz

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 50 MHz

*4

Parameter

Symbol Min

Typ

Max

Min

Typ

Max

Unit

Test conditions

Programming time

t

—

83

309

—

45

162

ms

OP

N

OPC

≤ 100 times

Programming time

> 100 times

t

—

100

371

—

55

195

ms

OP

N

OPC

*1

Reprogramming cycle

N

t

—

Times

Years

20000

OPC

*2

*2 *3

Data hold time

10

30

10

30

DRP

*2 *3

Ta = +85°C

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to

the minimum value.

Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 3. This result is obtained from reliability testing.

Note 4. The reference value at VCC = 3.3 V and room temperature.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 92 of 109

RA6M4 Datasheet

2. Electrical Characteristics

2.13

Boundary Scan

Table 2.52

Parameter

Boundary scan characteristics

Symbol

Min

100

45

—

Typ

—

Max

—

5

Unit

ns

—

Test conditions

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TMS setup time

t

Figure 2.87

TCKcyc

TCKH

TCKL

TCKr

—

5

TCKf

20

—

40

—

Figure 2.88

TMSS

TMSH

TDIS

TMS hold time

TDI setup time

TDI hold time

TDIH

TDO data delay

TDOD

*1

T

t

Figure 2.89

Boundary scan circuit startup time

BSSTUP

RESWP

Note 1. Boundary scan does not function until the power-on reset becomes negative.

t_TCKcyc

t_TCKH

t_TCKf

TCK

t_TCKr

t_TCKL

Figure 2.87

Boundary scan TCK timing

TCK

TMS

TDI

t^TMSS

t^TMSH

t^TDIS

t^TDIH

t^TDOD

TDO

Figure 2.88

Boundary scan input/output timing

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 93 of 109

RA6M4 Datasheet

2. Electrical Characteristics

VCC

RES

t_BSSTUP

₍₌t_RESWP)

Boundary scan

execute

Figure 2.89

Boundary scan circuit startup timing

Joint European Test Action Group (JTAG)

JTAG

2.14

Table 2.53

Parameter

Symbol

Min

40

15

—

8

Typ

—

Max

—

5

Unit

Test conditions

TCK clock cycle time

TCK clock high pulse width

TCK clock low pulse width

TCK clock rise time

TCK clock fall time

TMS setup time

t

ns

Figure 2.90

TCKcyc

TCKH

TCKL

TCKr

5

TCKf

—

20

Figure 2.91

TMSS

TMSH

TDIS

TMS hold time

8

TDI setup time

8

TDI hold time

8

TDIH

TDO data delay time

—

TDOD

t_TCKcyc

t_TCKH

TCK

t_TCKf

t_TCKr

t_TCKL

Figure 2.90

JTAG TCK timing

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 94 of 109

RA6M4 Datasheet

2. Electrical Characteristics

TCK

t_TMSS

t_TMSH

TMS

t_TDIS

t_TDIH

TDI

t_TDOD

TDO

Figure 2.91

JTAG input/output timing

2.15

Serial Wire Debug (SWD)

Table 2.54

Parameter

SWD

Symbol

Min

40

15

—

8

Typ

—

Max

—

5

Unit

ns

Test conditions

SWCLK clock cycle time

SWCLK clock high pulse width

SWCLK clock low pulse width

SWCLK clock rise time

SWCLK clock fall time

SWDIO setup time

t

Figure 2.92

SWCKcyc

SWCKH

SWCKL

SWCKr

SWCKf

SWDS

5

—

28

Figure 2.93

SWDIO hold time

8

SWDH

SWDIO data delay time

2

SWDD

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 95 of 109

RA6M4 Datasheet

2. Electrical Characteristics

t_SWCKcyc

t_SWCKH

SWCLK

t_SWCKL

Figure 2.92

SWD SWCLK timing

SWCLK

t_SWDS

t_SWDH

SWDIO

(Input)

t_SWDD

SWDIO

(Output)

SWDIO

(Output)

SWDIO

(Output)

Figure 2.93

SWD input/output timing

2.16

Embedded Trace Macro Interface (ETM)

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 96 of 109

RA6M4 Datasheet

2. Electrical Characteristics

Table 2.55

ETM

Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

20

9

Typ

—

Max

—

1

Unit

ns

Test conditions

TCLK clock cycle time

TCLK clock high pulse width

TCLK clock low pulse width

TCLK clock rise time

t

Figure 2.94

TCLKcyc

TCLKH

TCLKL

TCLKr

TCLKf

TRDS

ns

9

ns

—

2.5

1.5

ns

TCLK clock fall time

1

ns

TDATA[3:0] output setup time

TDATA[3:0] output hold time

—

ns

Figure 2.95

ns

TRDH

t_TCLKcyc

t_TCLKH

TCLK

t_TCLKf

t_TCLKr

t_TCLKL

Figure 2.94

ETM TCLK timing

TCLK

t_TRDS

t_TRDH

t_TRDS

t_TRDH

TDATA[3:0]

Figure 2.95

ETM output timing

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 97 of 109

RA6M4 Datasheet

Appendix 1. Port States in Each Processing Mode

Appendix 1.

Port States in Each Processing Mode

After Deep Software Standby

mode is canceled (return to

startup mode)

Software Standby mode

Deep Software

Standby mode

Function

Mode

Pin function

MD

Reset

Pull-up

output

Hi-Z

OPE=0

Keep-O

OPE=1

IOKEEP = 0

Hi-Z

IOKEEP = 1^*1

Keep

JTAG

TCK/TMS/TDI

TDO

Hi-Z

Keep

TDO output

Hi-Z

Keep

Keep-O^*2

IRQ

IRQx

Keep

Keep^*3

Keep

IRQx-DS

Hi-Z

Keep

AGT

AGTIOn

Keep^*3

Keep

AGTIOn (n=1,3)

RXD0

SCI

IIC

SCLn/SDAn

USB_OVRCURx

Keep

USBFS

Keep^*3

USB_OVRCURx-DS/

USB_VBUS

Keep-O^*4

Keep-O^*2

Keep^*3

USB_DP/USB_DM

RTCICx

Hi-Z

Keep

Keep^*3

Keep

RTC

RTCOUT

Hi-Z

[RTCOUT selected] RTCOUT output

[CLKOUT selected] CLKOUT output

[DAn output (DAOE = 1)] D/A output retained

[EBCLK output] H

Hi-Z

Keep

CLKOUT

DAC

CLKOUT

DAn

External

bus

(CS area)

EBCLK

Dx

[Dx output] Hi-Z

Ax

[Ax output] Hi-Z

[Ax output] Keep-O

BCx/CSx/RD/WRx

[BCx/CSx/RD/WRx

output] Hi-Z

[BCx/CSx/RD/WRx

output] H

ALE

—

Hi-Z

[ALE output] Hi-Z

Keep-O

[ALE output] L

Keep

Hi-Z

Keep

Others

Note:

H: High-level

L: Low-level

Hi-Z: High-impedance

Keep-O: Output pins retain their previous values. Input pins go to high-impedance.

Keep: Pin states are retained during periods in Software Standby mode.

Note 1. Retains the I/O port state until the DPSBYCR.IOKEEP bit is cleared to 0.

Note 2. Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin.

Note 3. Input is enabled if the pin is specified as the Deep Software Standby canceling source.

Note 4. Input is enabled while the pin is used as an input pin.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 98 of 109

RA6M4 Datasheet

Appendix 2. Package Dimensions

Appendix 2.

Package Dimensions

Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas

Electronics Corporation website.

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

1.2

P-LFQFP144-20x20-0.50

PLQP0144KA-B

—

H_D

D

Unit: mm

*1

108

73

109

72

144

37

NOTE 4

1

36

NOTE)

Index area

NOTE 3

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

F

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Dimensions in millimeters

Min Nom Max

Reference

Symbol

*3

b

e

p

M

y

S

D

E

19.9



20.0 20.1

A₂

H_D

H_E

A

1.4



21.8



22.0 22.2



1.7

A₁

b_p

c

0.05

0.17

0.09

0

0.15

0.20 0.27



3.5

0.5



0.20

8



L_p

L₁

e



x



0.08

0.75



Detail F

y



L_p

L₁

0.45



0.6

1.0

Figure 2.1

LQFP 144-pin

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 99 of 109

RA6M4 Datasheet

Appendix 2. Package Dimensions

JEITA Package Code

RENESAS Code

Previous Code

MASS (Typ) [g]

0.6

P-LFQFP100-14x14-0.50

PLQP0100KB-B

—

H_D

Unit: mm

*1

D

75

51

76

50

100

26

1

25

NOTE 4

NOTE)

Index area

NOTE 3

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

F

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Dimensions in millimeters

Min Nom Max

Reference

Symbol

y

S

*3

b

p

e

M

D

E

13.9



14.0 14.1

A₂

H_D

H_E

A

1.4



15.8



16.0 16.2



1.7

A₁

b_p

c

0.05

0.15

0.09

0

0.15

0.20 0.27



3.5

0.5



0.20

8

L_p

L₁



e



Detail F

x



0.08

0.75



y



L_p

L₁

0.45



0.6

1.0

Figure 2.2

LQFP 100-pin

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 100 of 109

RA6M4 Datasheet

Appendix 2. Package Dimensions

JEITA Package Code

P-LFQFP64-10x10-0.50

RENESAS Code

Previous Code

MASS (Typ) [g]

0.3

PLQP0064KB-C

—

Unit: mm

H_D

*1

D

48

33

49

32

64

17

1

16

NOTE 4

Index area

NOTE 3

NOTE)

F

1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.

2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.

3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE

LOCATED WITHIN THE HATCHED AREA.

S

4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

y

S

*3

Dimensions in millimeters

Min Nom Max

Reference

Symbol

b

p

e

M

D

E

9.9



10.0 10.1

A₂

H_D

H_E

A

1.4



11.8



12.0 12.2



1.7

A₁

b_p

c

0.05

0.15

0.09

0

0.15

0.20 0.27



3.5

0.5



0.20

8

L_p

L₁



e



Detail F

x



0.08

0.75



y



L_p

L₁

0.45



0.6

1.0

Figure 2.3

LQFP 64-pin

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 101 of 109

RA6M4 Datasheet

Appendix 3. I/O Registers

Appendix 3.

I/O Registers

This appendix describes I/O register address and access cycles by function.

3.1

Peripheral Base Addresses

This section provides the base addresses for peripherals described in this manual. Table 3.1 shows the name, description,

and the base address of each peripheral.

Table 3.1

Name

RMPU

TZF

Peripheral base address (1 of 3)

Description

Base address

0x4000_0000

0x4000_0E00

0x4000_2000

0x4000_3000

0x4000_5000

0x4000_5040

0x4000_5080

0x4000_50C0

0x4000_5100

0x4000_5140

0x4000_5180

0x4000_51C0

0x4000_5200

0x4000_5400

0x4000_6000

0x4000_7000

0x4000_8000

0x400_1B000

0x400_1C100

0x4001_E000

0x4008_0000

0x4008_0020

0x4008_0040

0x4008_0060

0x4008_0080

0x4008_00A0

0x4008_00C0

0x4008_00E0

0x4008_0100

0x4008_0800

0x4008_2000

0x4008_3000

0x4008_3200

0x4008_3400

0x4008_3600

Renesas Memory Protection Unit

TrustZone Filter

SRAM

BUS

SRAM Control

BUS Control

DMAC0

DMAC1

DMAC2

DMAC3

DMAC4

DMAC5

DMAC6

DMAC7

DMA

Direct memory access controller 0

Direct memory access controller 1

Direct memory access controller 2

Direct memory access controller 3

Direct memory access controller 4

Direct memory access controller 5

Direct memory access controller 6

Direct memory access controller 7

DMAC Module Activation

Data Transfer Controller

Interrupt Controller

DTC

ICU

CACHE

CPSCU

DBG

CACHE

CPU System Security Control Unit

Debug Function

FCACHE

SYSC

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT8

PFS

Flash Cache

System Control

Port 0 Control Registers

Port 1 Control Registers

Port 2 Control Registers

Port 3 Control Registers

Port 4 Control Registers

Port 5 Control Registers

Port 6 Control Registers

Port 7 Control Registers

Port 8 Control Registers

Pmn Pin Function Control Register

Event Link Controller

ELC

RTC

Realtime Clock

IWDT

Independent Watchdog Timer

Watchdog Timer

WDT

CAC

Clock Frequency Accuracy Measurement Circuit

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Sep 29, 2020

Page 102 of 109

RA6M4 Datasheet

Appendix 3. I/O Registers

Table 3.1

Name

MSTP

POEG

USBFS

SDHI0

SSIE0

IIC0

Peripheral base address (2 of 3)

Description

Base address

Module Stop Control A, B, C, D

Port Output Enable Module for GPT

USB 2.0 FS Module

0x4008_4000

0x4008_A000

0x4009_0000

0x4009_2000

0x4009_D000

0x4009_F000

0x4009_F014

0x4009_F100

0x400A_6000

0x400A_8000

0x400A_9000

0x400D_0000

0x400E_0000

0x400E_8000

0x400E_8100

0x400E_8200

0x400E_8300

0x400E_8400

0x400E_8500

0x400F_3000

0x4010_8000

0x4010_9000

0x4011_4000

0x4011_4100

0x4011_8000

0x4011_8100

0x4011_8200

0x4011_8300

0x4011_8400

0x4011_8500

0x4011_8600

0x4011_8700

0x4011_8800

0x4011_8900

0x4011_A000

0x4011_A100

0x4016_1000

0x4016_9000

0x4016_9100

0x4016_9200

0x4016_9300

SD Host Interface 0

Serial Sound Interface Enhanced (SSIE)

Inter-Integrated Circuit 0

IIC0WU

IIC1

Inter-Integrated Circuit 0 Wake-up Unit

Inter-Integrated Circuit 1

OSPI

Octa Serial Peripheral Interface

CAN0 Module

CAN0

CAN1

CTSU

PSCU

AGT0

AGT1

AGT2

AGT3

AGT4

AGT5

TSN

CAN1 Module

Capacitive Touch Sensing Unit

Peripheral Security Control Unit

Low Power Asynchronous General purpose Timer 0

Low Power Asynchronous General purpose Timer 1

Low Power Asynchronous General purpose Timer 2

Low Power Asynchronous General purpose Timer 3

Low Power Asynchronous General purpose Timer 4

Low Power Asynchronous General purpose Timer 5

Temperature Sensor

CRC

CRC Calculator

DOC

Data Operation Circuit

EDMAC0

ETHERC0

SCI0

DMA Controller for the Ethernet Controller Channel 0

Ethernet Controller Channel 0

Serial Communication Interface 0

Serial Communication Interface 1

Serial Communication Interface 2

Serial Communication Interface 3

Serial Communication Interface 4

Serial Communication Interface 5

Serial Communication Interface 6

Serial Communication Interface 7

Serial Communication Interface 8

Serial Communication Interface 9

Serial Peripheral Interface 0

SCI1

SCI2

SCI3

SCI4

SCI5

SCI6

SCI7

SCI8

SCI9

SPI0

SPI1

Serial Peripheral Interface 1

SCE9

GPT320

GPT321

GPT322

GPT323

Secure Cryptographic Engine

General PWM 32-Bit Timer 0

General PWM 32-Bit Timer 1

General PWM 32-Bit Timer 2

General PWM 32-Bit Timer 3

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 103 of 109

RA6M4 Datasheet

Appendix 3. I/O Registers

Table 3.1

Name

Peripheral base address (3 of 3)

Description

Base address

GPT164

GPT165

GPT166

GPT167

GPT168

GPT169

GPT_OPS

ADC120

ADC121

DAC12

FLAD

General PWM 16-Bit Timer 4

General PWM 16-Bit Timer 5

General PWM 16-Bit Timer 6

General PWM 16-Bit Timer 7

General PWM 16-Bit Timer 8

General PWM 16-Bit Timer 9

Output Phase Switching Controller

12bit A/D Converter 0

0x4016_9400

0x4016_9500

0x4016_9600

0x4016_9700

0x4016_9800

0x4016_9900

0x4016_9A00

0x4017_0000

0x4017_0200

0x4017_1000

0x407F_C000

0x407F_E000

0x6400_0000

12bit A/D Converter 1

12-bit D/A converter

Data Flash

FACI

Flash Application Command Interface

Quad-SPI

QSPI

Note:

Name = Peripheral name

Description = Peripheral functionality

Base address = Lowest reserved address or address used by the peripheral

3.2

Access Cycles

This section provides access cycle information for the I/O registers described in this manual.

● Registers are grouped by associated module.

● The number of access cycles indicates the number of cycles based on the specified reference clock.

● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations

cannot be guaranteed.

● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization

cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio

between ICLK and PCLK.

● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always

constant.

● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided

clock synchronization cycles.

● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.

Note:

This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the

external memory or bus access from other bus masters such as DTC or DMAC.

Table 3.2

Access cycles (1 of 4)

Number of access cycles

Address

From

ICLK = PCLK

ICLK > PCLK^*1

Cycle

Unit

Peripherals

To

Read

Write

Read

Write

Related function

RMPU, TZF,

SRAM, BUS,

DMACn, DMA,

DTC, ICU

0x4000_0000

0x4000_6FFF

4

3

4

3

ICLK

Renesas Memory

Protection Unit,

TrustZone Filter,

SRAM Control, BUS

Control, Direct

memory access

controller n, DMAC

Module Activation,

DTC Control Register,

Interrupt Controller

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 104 of 109

RA6M4 Datasheet

Appendix 3. I/O Registers

Table 3.2

Access cycles (2 of 4)

Number of access cycles

ICLK = PCLK

Address

ICLK > PCLK^*1

Cycle

Peripherals

From

To

Read

Write

Read

Write

Unit

ICLK

Related function

CACHE

0x4000_7000

0x4000_8000

0x4000_7FFF

0x4001_CFFF

3

4

5

3

4

5

3

CACHE

CPSCU, DBG,

FCACHE

CPU System Security

Control Unit, Debug

Function, Flash Cache

SYSC

0x4001_E000

0x4001_E400

0x4008_0000

0x4001_E3FF

0x4001_E5FF

0x4008_0FFF

5

9

5

4

8

4

5

4

ICLK

System Control

SYSC

5 to 8

2 to 5

5 to 8

2 to 4

PCLKB System Control

PORTn, PFS

PCLKB Port n Control

Registers, Pmn Pin

Function Control

Register

ELC, RTC, IWDT, 0x4008_2000

WDT, CAC

0x4008_3FFF

5

4

3 to 5

2 to 4

PCLKB Event Link Controller,

Realtime Clock,

Independent

Watchdog Timer,

Clock Frequency

Accuracy

Measurement Circuit

MSTP

POEG

0x4008_4000

0x4008_A000

0x4008_4FFF

0x4008_AFFF

5

4

2 to 5

3 to 5

2 to 4

PCLKB Module Stop Control

PCLKB Port Output Enable

Module for GPT

USBFS

0x4009_0000

0x4009_4000

0x4009_2000

0x4009_3FFF

0x4009_4FFF

0x4009_FFFF

6

4

5

3

4

3 to 6

1 to 4

2 to 5

3 to 5

1 to 3

2 to 4

PCLKB USB 2.0 FS Module

SDHI0, SSIE0,

IICn, IIC0WU

PCLKB SD Host Interface 0,

Serial Sound Interface

Enhanced, Inter-

Integrated Circuit n,

Inter-Integrated Circuit

0 Wake-up Unit

OSPI

0x400A_6000

0x400A_6FFF

15

17

12 to 15

15 to 17

PCLKB Octa Serial Peripheral

Interface

CANn

CTSU

0x400A_8000

0x400D_0000

0x400A_9FFF

0x400D_FFFF

5

4

3

2 to 5

1 to 4

2 to 4

1 to 3

PCLKB CANn Module

PCLKB Capacitive Touch

Sensing Unit

PSCU

AGTn

0x400E_0000

0x400E_8000

0x400E_0FFF

0x400E_8FFF

5

7

4

2 to 5

5 to 7

2 to 4

PCLKB Peripheral Security

Control Unit

PCLKB Low Power

Asynchronous

General purpose

Timer n

TSN

0x400F_3000

0x4010_8000

0x400F_3FFF

0x4010_9FFF

5

4

2 to 5

2 to 4

PCLKB Temperature Sensor

CRC, DOC

PCLKA CRC Calculator, Data

Operation Circuit

EDMAC0

0x4011_4000

0x4011_40FF

6

5

3 to 6

3 to 5

PCLKA DMA Controller for the

Ethernet Controller

Channel 0

ETHERC0

SCIn

0x4011_4100

0x4011_8000

0x4011_A000

0x4016_1000

0x4011_4FFF

0x4011_8FFF

0x4011_AFFF

0x4016_1FFF

15

14

12 to 15

2 to 5^*2

12 to 14

2 to 4^*2

PCLKA Ethernet Controller

Channel 0

5^*2

4^*2

PCLKA Serial Communication

Interface n

5^*3

6

4^*3

4

2 to 5^*3

3 to 6

2 to 4^*3

2 to 4

SPIn

PCLKA Serial Peripheral

Interface n

SCE9

PCLKA Secure Cryptographic

Engine

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 105 of 109

RA6M4 Datasheet

Appendix 3. I/O Registers

Table 3.2

Access cycles (3 of 4)

Number of access cycles

ICLK = PCLK

Address

From

ICLK > PCLK^*1

Read

Cycle

Unit

Peripherals

To

Read

Write

Related function

GPT32n, GPT16n, 0x4016_9000

GPT_OPS

0x4016_9FFF

7

4

4 to 7

2 to 4

PCLKA General PWM 32-Bit

Timer n, General

PWM 16-Bit Timer n,

Output Phase

Switching Controller

ADC12n, DAC12

0x4017_0000

0x4017_2FFF

5

4

2 to 5

2 to 4

PCLKA 12bit A/D Converter n,

12-bit D/A converter

14 to ^*4

6 to ^*4

14 to ^*4

5 to ^*4

QSPI

0x6400_0000

0x6400_0010

0x6400_0014

0x6400_0804

0x6400_000F

0x6400_0013

0x6400_0037

0x6400_0807

PCLKA Quad-SPI

25 to ^*4

5

25 to ^*4

2 to 5

14 to ^*4

3

14 to ^*4

1 to 3

4

1 to 4

Table 3.2

Access cycles (4 of 4)

Number of access cycles

ICLK = FCLK

Address

ICLK > FCLK^*1

Read

Cycle

Unit

Peripherals

From

To

Read

Write

Related function

FLAD, FACI

0x407F_C000

0x407F_EFFF

5

4

2 to 5

2 to 4

FCLK

Data Flash, Flash

Application Command

Interface

Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the

maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.

Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in

Table 3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in

Table 3.2.

Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit

register (SPDR_HA), the access cycles are as shown in Table 3.2.

Note 4. The access cycles depend on the QSPI bus cycles.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 106 of 109

RA6M4 Datasheet

Revision History

Revision 1.00 — April 09, 2020

First edition, issued

Revision 1.10 — September 29, 2020

1. Overview:

●

Added note to Figure 1.1 Block diagram.

2. Electrical Characteristics:

●

Added description that Supported peripheral functions and pins differ from one product name to another.

Appendix:

●

Removed NOTE about USB host operation in Appendix 1.

Added Access cycles for FLAD and FACI to Tables 3.2 in Appendix 3.

Removed NOTE2 about BWAIT in Table 3.2, and along with that,changed the NOTE number in this table in Appendix 3.

R01DS0365EJ0110 Rev.1.10

Sep 29, 2020

Page 107 of 109

General Precautions in the Handling of Microprocessing Unit and Microcontroller

Unit Products

The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the

products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps

must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be

adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.

Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and

measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor

devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.

2. Processing at power-on

The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of

register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset

pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins

in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the

level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O

pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal

elements. Follow the guideline for input signal during power-off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are

generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of

the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal

become possible.

5. Clock signals

After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program

execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator

during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal

produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V_IL

(Max.) and V_IH(Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the

input level is fixed, and also in the transition period when the input level passes through the area between V_IL(Max.) and V_IH(Min.).

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these

addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.

The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms

of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,

operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-

evaluation test for the given product.


型号：	R7FA6M4AE3CFP
厂家：	RENESAS TECHNOLOGY CORP
描述：	Armv8-M architecture with the main extension
文件：	总109页 (文件大小：1314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R7FA6M4AE3CFP [RENESAS]

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