R8C/11 [RENESAS]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER; 单芯片16位CMOS微机
| 型号： | R8C/11 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 文件： | 总30页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R8C/11 Group
REJ03B0034-0160
Rev.1.60
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Jan 27, 2006
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
Rev.1.60 Jan 27, 2006 page 1 of 26
REJ03B0034-0160
R8C/11 Group
1. Overview
1.2 Performance Overview
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item
Performance
CPU
Number of basic instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Operating mode
Address space
Memory capacity
Port
LED drive port
Timer
Single-chip
1M bytes
See Table 1.2.
Input/Output: 22 (including LED drive port), Input: 2
I/O port: 8
Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Timer Z: 8 bits x 1 channel
Peripheral
function
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
(Circuits of input capture and output compare)
•1 channel
Serial Interface
Clock synchronous, UART
•1 channel
UART
A/D converter
Watchdog timer
Interrupt
10-bit A/D converter: 1 circuit, 12 channels
15 bits x 1 (with prescaler)
Internal: 11 factors, External: 5 factors,
Software: 4 factors, Priority level: 7 levels
2 circuits
Clock generation circuit
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•On-chip oscillator (high speed, low speed)
On High-speed on-chip oscillator the frequency adjust-
ment function is usable.
Oscillation stop detection function Main clock oscillation stop detection function
Voltage detection circuit
Power on reset circuit
Supply voltage
Included
Included
Electrical
characteristics
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
Typ. 9 mA (VCC = 5.0 V, (f(XIN) = 20 MHZ)
Typ. 5 mA (VCC = 3.0 V, (f(XIN) = 10 MHZ)
Typ. 35 µA (VCC = 3.0 V, Wait mode, Peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, Stop mode)
Power consumption
Flash memory Program/erase supply voltage VCC = 2.7 to 5.5 V
Program/erase endurance
Operating ambient temperature
100 times
-20 to 85 °C
-40 to 85 °C (D-version)
32-pin plastic mold LQFP
Package
Rev.1.60 Jan 27, 2006 page 2 of 26
REJ03B0034-0160
R8C/11 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
1
2
8
5
8
Port P4
Port P3
I/O port
Port P0
Port P1
Peripheral functions
Timer
A/D converter
(10 bits ✕ 12 channels)
System clock generator
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
UART or Clock synchronous
serial I/O
X
IN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
(8 bits ✕ 1 channel)
UART
(8 bits ✕ 1 channel)
R8C/Tiny Series CPU core
Memory
SB
ROM(1)
R0H
R1H
R0L
R1L
Watchdog timer
(15 bits)
USP
ISP
R2
R3
RAM(2)
INTB
PC
FLG
A0
A1
FB
Multiplier
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.1 Block Diagram
Rev.1.60 Jan 27, 2006 page 3 of 26
REJ03B0034-0160
R8C/11 Group
1. Overview
1.4 Product Information
Table 1.2 lists the product information.
Table 1.2 Product Information
As of January 2006
RAM capacity
512 bytes PLQP0032GB-A
Remarks
Type No.
R5F21112FP
ROM capacity
8K bytes
Package type
Flash memory version
R5F21113FP
R5F21114FP
768 bytes
1K bytes
12K bytes
16K bytes
PLQP0032GB-A
PLQP0032GB-A
R5F21112DFP
R5F21113DFP
R5F21114DFP
512 bytes
768 bytes
1K bytes
D version
8K bytes
12K bytes
16K bytes
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
Type No. R 5 F 21 11 4 D FP
Package type:
FP : PLQP0032GB-A
Classification:
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
R8C/11 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.1.60 Jan 27, 2006 page 4 of 26
REJ03B0034-0160
R8C/11 Group
1. Overview
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
P4
P1
P1
P1
P1
P1
P1
P1
5
0
1
2
3
4
5
6
/INT0
P0
P0
P0
6
/AN
/AN
/AN
1
16
15
14
13
12
11
10
9
/KI
/KI
/KI
/KI
0
1
2
3
/AN
8
9
/CMP0
0
1
5
4
2
3
/AN
/CMP0
MODE
P0 /AN
P0 /AN
P0 /AN
/AN /TxD11
/AN10/CMP0
/AN11
2
R8C/11 Group
3
4
/TxD
0
2
5
/RxD
/CLK
0
0
1
6
P0
0
7
1
2 3 4 5 6 7 8
NOTES:
1. P4 functions only as an input port.
2. When using On-chip debugger, do not use pins P0
and P3 /TxD10/RxD
3. Do not connect IVcc to Vcc.
7
0/AN7/TxD11
7
1.
Package: PLQP0032GB-A (32P6U-A)
Figure 1.3 Pin Assignments (Top View)
Rev.1.60 Jan 27, 2006 page 5 of 26
REJ03B0034-0160
R8C/11 Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name
Power supply
input
Pin name
Vcc,
Vss
I/O type
Function
I
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
IVcc
IVcc
O
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1 µF).
Do not connect to Vcc.
Analog power
supply input
AVcc, AVss
I
Power supply input pins for A/D converter. Connect the
AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a
capacitor between pins AVcc and AVss.
___________
Reset input
CNVss
MODE
RESET
CNVss
MODE
I
I
I
I
Input “L” on this pin resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generat-
ing circuit I/O. Connect a ceramic resonator or a crys-
tal oscillator between the XIN and XOUT pins. To use
an externally derived clock, input it to the XIN pin and
Main clock input XIN
Main clock output XOUT
O
leave the XOUT pin open.
_____
_______
_______
______
INT interrupt input INT0 to INT3
Key input interrupt KI0 to KI3
I
I
INT interrupt input pins.
Key input interrupt pins.
Timer X I/O pin
Timer X output pin
Timer Y I/O pin
Timer Z output pin
Timer C input pin
Timer C output pins
_____
_____
Timer X
CNTR0
I/O
O
I/O
O
I
O
____________
CNTR0
Timer Y
Timer Z
Timer C
CNTR1
TZOUT
TCIN
CMP00 to CMP02,
CMP10 to CMP12
CLK0
Serial interface
I/O
I
O
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
RxD0, RxD1
TxD0, TxD10,
TxD11
Reference voltage VREF
input
I
Reference voltage input pin for A/D converter. Con-
nect the VREF pin to Vcc.
A/D converter
I/O port
AN0 to AN11
I
Analog input pins for A/D converter
P00 to P07,
P10 to P17,
P30 to P33, P37,
P45
I/O
These are 8-bit CMOS I/O ports. Each port has an I/O
select direction register, allowing each pin in that port
to be directed for input or output individually.
Any port set to input can select whether to use a pull-
up resistor or not by program.
P10 to P17 also function as LED drive ports.
Port for input-only
Input port
P46, P47
I
Rev.1.60 Jan 27, 2006 page 6 of 26
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R8C/11 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
b31
b15
b8b7
b0
R0L (low-order of R0)
R1L (low-order of R1)
R2
R3
R0H (high-order of R0)
R1H (high-order of R1)
(1)
Data registers
R2
R3
A0
A1
FB
(1)
Address registers
(1)
Frame base registers
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
b15
b0
b0
FLG
Flag register
b15
b8 b7
IPL
U
I
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTES:
1. A register bank comprises these registers. Two sets of register banks are provided
Figure 2.1 CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
Rev.1.60 Jan 27, 2006 page 7 of 26
REJ03B0034-0160
R8C/11 Group
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be
combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is
set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
Rev.1.60 Jan 27, 2006 page 8 of 26
REJ03B0034-0160
R8C/11 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses
0000016 to FFFFF16.
The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16-Kbyte
internal ROM is allocated addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte
internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing
data, but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function
control registers are located them. All addresses, which have nothing allocated within the SFR, are re-
served area and cannot be accessed by users.
0000016
SFR
(See Chapter 4 for details.)
002FF16
0040016
Internal RAM
0XXXX16
0FFDC16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer,Oscillation stop detection,Voltage detection
0YYYY16
0FFFF16
(Reserved)
(Reserved)
Reset
Internal ROM
0FFFF16
Expansion area
FFFFF16
NOTES :
1. Blank spaces are reserved. No access is allowed.
Internal ROM
Internal RAM
Type name
Address 0YYYY16
Address 0XXXX16
Size
Size
16K bytes
12K bytes
8K bytes
0C00016
0D00016
0E00016
R5F21114FP, R5F21114DFP
R5F21113FP, R5F21113DFP
R5F21112FP, R5F21112DFP
1K bytes
007FF16
768 bytes
512 bytes
006FF16
005FF16
Figure 3.1 Memory Map
Rev.1.60 Jan 27, 2006 page 9 of 26
REJ03B0034-0160
R8C/11 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR
information
(1)
Table 4.1 SFR Information(1)
Address
Register
Symbol
After reset
000016
000116
000216
000316
000416 Processor mode register 0
PM0
PM1
CM0
CM1
HR0
AIER
PRCR
HR1
OCD
0016
0016
01101000
00100000
0016
XXXXXX00
00XXX000
4016
00000100
XX16
XX16
00011111
0016
0016
X016
000516
Processor mode register 1
000616
System clock control register 0
2
2
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
System clock control register 1
High-speed on-chip oscillator control register 0
Address match interrupt enable register
2
Protect register
2
High-speed on-chip oscillator control register 1
Oscillation stop detection register
Watchdog timer reset register
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
2
WDTR
WDTS
WDC
2
RMAD0
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1(2)
Voltage detection register 2(2)
VCR1
VCR2
00001000
0016(3)
2
100000002(4)
001B16
001C16
001D16
001E16
001F16
INT0 input filter select register
INT0F
D4INT
XXXXX000
2
Voltage detection interrupt register(2)
0016(3)
010000012(4)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
X : Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. Software reset or the watchdog timer reset does not affect this register.
3. Owing to Reset input.
4. In the case of RESET pin = H retaining.
Rev.1.60 Jan 27, 2006 page 10 of 26
REJ03B0034-0160
R8C/11 Group
4. Special Function Register (SFR)
(1)
Table 4.2 SFR Information(2)
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Symbol
After reset
Key input interrupt control register
AD conversion interrupt control register
KUPIC
ADIC
XXXXX000
XXXXX000
2
2
Compare 1 interrupt control register
UART0 transmit interrupt control register
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TXIC
TYIC
TZIC
XXXXX000
XXXXX000
XXXXX000
2
2
2
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
INT2 interrupt control register
Timer X interrupt control register
Timer Y interrupt control register
Timer Z interrupt control register
INT1 interrupt control register
INT3 interrupt control register
Timer C interrupt control register
Compare 0 interrupt control register
XXXXX000
2
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
INT1IC
INT3IC
TCIC
CMP0IC
INT0 interrupt control register
INT0IC
XX00X0002
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
X : Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Rev.1.60 Jan 27, 2006 page 11 of 26
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R8C/11 Group
4. Special Function Register (SFR)
(1)
Table 4.3 SFR Information(3)
Address
Register
Symbol
After reset
008016 Timer Y, Z mode register
008116 Prescaler Y register
008216 Timer Y secondary register
TYZMR
PREY
TYSC
TYPR
PUM
PREZ
TZSC
TZPR
0016
FF16
FF16
FF16
0016
FF16
FF16
FF16
Timer Y primary register
Timer Y, Z waveform output control register
Prescaler Z register
Timer Z secondary register
Timer Z primary register
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
Timer Y, Z output control register
Timer X mode register
TYZOC
TXMR
PREX
TX
0016
0016
FF16
FF16
0016
008C16 Prescaler X register
Timer X register
Timer count source set register
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
TCSS
Timer C register
TC
0016
0016
External input enable register
Key input enable register
INTEN
KIEN
0016
0016
Timer C control register 0
TCC0
TCC1
TM0
0016
0016
0016
009B16 Timer C control register 1
009C16 Capture, compare 0 register
009D16
0016(2)
FF16
009E16
Compare 1 register
TM1
009F16
00A016
FF16
0016
XX16
XX16
XX16
00001000
00000010
XX16
XX16
0016
XX16
XX16
XX16
00001000
00000010
UART0 transmit/receive mode register
UART0 bit rate register
UART0 transmit buffer register
U0MR
U0BRG
U0TB
00A116
00A216
00A316
00A416
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
2
2
00A516
00A616
00A716
00A816
UART1 transmit/receive mode register
UART1 bit rate register
UART1 transmit buffer register
U1MR
U1BRG
U1TB
00A916
00AA16
00AB16
00AC16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
U1C0
U1C1
2
2
00AD16
00AE16
UART1 receive buffer register
U1RB
XX16
XX16
0016
00AF16
00B016
UART transmit/receive control register 2
UCON
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
X : Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. When output compare mode (the TCC13 bit in the TCC1 register = 1) is selected, the value after reset is set to “FFFF16”.
Rev.1.60 Jan 27, 2006 page 12 of 26
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R8C/11 Group
4. Special Function Register (SFR)
(1)
Table 4.4 SFR Information(4)
Address
Register
Symbol
AD
After reset
XX16
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
AD register
XX16
AD control register 2
ADCON2
0016
00D616 AD control register 0
ADCON0
ADCON1
00000XXX
0016
2
00D716
AD control register 1
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
P0
P1
PD0
PD1
XX16
XX16
0016
0016
00E116
00E216
00E316
00E416
00E516
Port P3 register
P3
XX16
00E616
00E716
Port P3 direction register
Port P4 register
PD3
P4
0016
XX16
00E816
00E916
00EA16 Port P4 direction register
PD4
0016
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
03FA16
00FB16
00FC16 Pull-up control register 0
PUR0
PUR1
DRR
00XX00002
XXXXXX0X
0016
00FD16
Pull-up control register 1
2
00FE16
Port P1 drive capacity control register
Timer C output control register
00FF16
TCOUT
0016
01B316 Flash memory control register 4
01B416
FMR4
FMR1
FMR0
01000000
0100XX0X
00000001
2
01B516
Flash memory control register 1
2
01B616
01B716
Flash memory control register 0
2
X : Undefined
NOTES:
1. Blank columns, 010016 to 01B216 and 01B816 to 02FF16 are all reserved. No access is allowed.
Rev.1.60 Jan 27, 2006 page 13 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated value
Unit
V
V
CC
Supply voltage
V
CC=AVCC
-0.3 to 6.5
-0.3 to 6.5
V
VCC=AVCC
AVCC
Analog supply voltage
Input voltage
V
I
V
V
-0.3 to VCC+0.3
-0.3 to VCC+0.3
Output voltage
VO
P
d
Power dissipation
C
300
Topr=25
mW
C
T
opr
Operating ambient temperature
Storage temperature
-20 to 85 / -40 to 85 (D version)
T
stg
C
-65 to 150
Table 5.2 Recommended Operating Conditions
Standard
Typ.
Conditions
Symbol
Parameter
Unit
Min.
Max.
V
CC
Supply voltage
2.7
5.5
V
(3)
AVcc
Vss
Analog supply voltage
Supply voltage
V
CC
V
V
V
0
AVss
Analog supply voltage
"H" input voltage
0
0.8VCC
0
V
V
V
IH
IL
VCC
0.2VCC
-60.0
V
"L" input voltage
Sum of all pins' IOH
(peak)
"H" peak all
output currents
IOH (sum)
mA
IOH (peak)
IOH (avg)
IOL (sum)
"H" peak output current
-10.0
-5.0
mA
mA
"H" average output current
Sum of all pins' IOL
"L" peak all
60
mA
(peak)
output currents
"L" peak output
current
Except P10 to P17
10
30
mA
mA
mA
mA
IOL (peak)
P10 to P17
Drive capacity HIGH
Drive capacity LOW
10
5
"L" average
output current
Except P1
P1 to P1
0 to P17
IOL (avg)
Drive capacity HIGH
Drive capacity LOW
3.0V ≤ Vcc ≤ 5.5V
2.7V ≤ Vcc < 3.0V
mA
mA
MHz
MHz
15
0
7
5
20
10
0
0
f (XIN
)
Main clock input oscillation frequency
NOTES:
1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. The typical values when average output current is 100ms.
3. Hold Vcc=AVcc.
Rev.1.60 Jan 27, 2006 page 14 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Table 5.3 A/D Conversion Characteristics
Standard
Unit
Symbol
Parameter
Measuring condition
Min. Typ. Max.
–
–
Resolution
V
ref =VCC
10
Bit
Absolute
accuracy
øAD=10 MHz, Vref=Vcc=5.0V
øAD=10 MHz, Vref=Vcc=5.0V
10 bit mode
LSB
LSB
LSB
±3
±2
8 bit mode
øAD=10 MHz, Vref=Vcc=3.3V(3)
øAD=10 MHz, Vref=Vcc=3.3V(3)
±5
10 bit mode
8 bit mode
±2
40
LSB
kΩ
µs
VREF=VCC
R
LADDER
Ladder resistance
Conversion time
10
t
CONV
øAD=10 MHz, Vref=Vcc=5.0V
øAD=10 MHz, Vref=Vcc=5.0V
3.3
2.8
10 bit mode
8 bit mode
µs
(4)
CC
V
Reference voltage
V
VREF
Analog input voltage
V
IA
0
Vref
V
A/D operating
clock frequency
0.25
1.0
Without sample & hold
With sample & hold
MHz
MHz
10
10
–
(2)
NOTES:
1. VCC=AVCC=2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. If fAD exceeds 10 MHz more, divide the fAD and hold A/D operating clock frequency (ØAD) 10 MHz or below.
3. If the AVcc is less than 4.2V, divide the fAD and hold A/D operating clock frequency (ØAD) fAD/2 or below.
4. Hold Vcc=Vref.
P0
30pF
P1
P2
P3
P4
Figure 5.1 Port P0 to P4 measurement circuit
Rev.1.60 Jan 27, 2006 page 15 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Table 5.4 Flash Memory Version Electrical Characteristics
Standard
Unit
Symbol
Measuring condition
Parameter
Min.
100
Typ.
Max
Program/erase endurance
Byte program time
times
µs
–
–
–
400
9
50
0.4
Block erase time
s
Time delay from suspend request until erase
suspend
td(SR-ES)
–
8
ms
ms
Erase Suspend Request Interval
10
2.7
2.7
0
V
V
5.5
5.5
60
Program, Erase voltage
Read voltage
–
–
–
Program, Erase temperature
°C
Ambient
temperature=55 °C
Data hold time(2)
20
–
year
NOTES:
1. Referenced to VCC1=AVcc=2.7 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.
2. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.5 Voltage Detection Circuit Electrical Characteristics
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
Min.
Max.
Voltage detection level
Vdet
3.3
3.8
4.3
V
(2)
40
µs
nA
µs
Voltage detection interrupt request generating time
Voltage detection circuit self consumption current
VC27=1, VCC=5.0V
600
(3)
td(E-A)
Vccmin
20
Waiting time till voltage detection circuit operation starts
Minimum value of microcomputer operation voltage
V
2.7
NOTES:
1. The measuring condition is Vcc=AVcc=2.7V to 5.5V and Topr= -40°C to 85 °C.
2. This shows the time until the voltage detection interrupt request is generated since the voltage passes Vdet.
3. This shows the required time until the voltage detection circuit operates when setting to "1" again after setting the VC27 bit in
the VCR2 register to “0”.
Erase-suspend request
(interrupt request)
FMR46
t
d(SR-ES)
Figure 5.2 Time delay from Suspend Request until Erase Suspend
Rev.1.60 Jan 27, 2006 page 16 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
(1, 3)
Table 5.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2
)
Standard
Typ.
Symbol
Vpor2
Measuring condition
Parameter
Unit
Min.
Max.
Vdet
Power-on reset valid voltage
–20°C
–20°C
≤
≤
Topr < 85°C
V
t
W
(Vpor2-
Vdet)
(2)
Supply voltage rising time when power-on reset is canceled
(4)
Topr < 85°C, tW(por2) ≥ 0s
ms
100
NOTES:
1. The voltage detection circuit which is embedded in a microcomputer is a factor to generate the hardware reset 2. Refer to 5.1.2 Hardware
Reset 2 of Hardware Manual for details.
2. This condition is not applicable when using with Vcc
≥ 1.0V.
3. When turning power on after the external power has been held below the valid voltage (Vpor1) for greater than 10 seconds, refer to Table 5.7
Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2).
4. tw(por2) is time to hold the external power below effective voltage (Vpor2).
Table 5.7 Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2)
Standard
Typ.
Measuring condition
Symbol
Parameter
Unit
V
Min.
Max.
0.1
Vpor1
Power-on reset valid voltage
–20°C
0°C
≤
Topr < 85°C
tW(Vpor1-
Vdet)
Supply voltage rising time when power-on reset is canceled
Supply voltage rising time when power-on reset is canceled
100
100
ms
≤
Topr ≤ 85°C, tW(por1) ≥ 10s(2)
tW(Vpor1-
Vdet)
30s(2)
10s(2)
ms
–20°C
–20°C
≤
≤
Topr < 0°C, t
Topr < 0°C, t
W
(por1)
(por1)
≥
tW(Vpor1-
Vdet)
Supply voltage rising time when power-on reset is canceled
Supply voltage rising time when power-on reset is canceled
1
ms
ms
W
≥
tW(Vpor1-
Vdet)
0.5
0°C
≤
Topr ≤ 85°C, tW(por1) ≥ 1s(2)
NOTES:
1. When not using hardware reset 2, use with Vcc
≥ 2.7V.
2. tw(por1) is time to hold the external power below effective voltage (Vpor1).
(3)
det
(3)
det
V
V
V
V
cc min
por2
V
por1
(1, 2)
Sampling time
tw(por2)
tw(Vpor2 –Vdet)
tw(por1) tw(Vpor1–Vdet)
Internal reset signal
(“L” effective)
1
1
X 32
X 32
f
RING-S
f
RING-S
NOTES:
1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time.
2. A sampling clock is selectable. Refer to “5.4 Voltage Detection Circuit” of Hardware Manual for details.
3. Vdet shows the voltage detection level of the voltage detection circuit. Refer to “5.4 Voltage Detection Circuit” for details.
4. Refer to “Table 16.6 Reset Circuit Electrical Characteristics” for electrical characteristics.
Figure 5.3 Reset Circuit Electrical Characteristics
Rev.1.60 Jan 27, 2006 page 17 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Table 5.8 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Unit
Symbol
Measuring condition
Parameter
Min.
6
Typ.
8
Max.
10
VCC=5.0V, Topr=25 °C
Set "4016" in the HR1 register
High-speed on-chip oscillator frequency 1 / {td(HRoffset)+td(HR)} when the
reset is released
MHz
ns
td(HRoffset)
td(HR)
VCC=5.0V, Topr=25 °C
Set "0016" in the HR1 register
Settable high-speed on-chip oscillator minimum period
61
Differences when setting "0116" and "0016
in the HR register
"
High-speed on-chip oscillator period adjusted unit
ns
1
±5
Frequency fluctuation in temperature range
of -10 °C to 50 °C
High-speed on-chip oscillator frequency temperature dependence(1)
High-speed on-chip oscillator frequency temperature dependence(2)
%
%
Frequency fluctuation in temperature range
of -40 °C to 85 °C
±10
NOTES:
1. The measuring condition is Vcc=AVcc=5.0 V and Topr=25 °C.
Table 5.9 Power Circuit Timing Characteristics
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
Min.
1
Max.
2000
150
µs
µs
(2)
td(P-R)
td(R-S)
Time for internal power supply stabilization during powering-on
(3)
STOP release time
NOTES:
1. The measuring condition is Vcc=AVcc=2.7 to 5.5 V and Topr=25 °C.
2. This shows the wait time until the internal power supply generating circuit is stabilized during power-on.
3. This shows the time until BCLK starts from the interrupt acknowledgement to cancel stop mode.
Table 5.10 Electrical Characteristics (1) [Vcc=5V]
Standard
Typ.
Measuring condition
Symbol
Parameter
Unit
Min.
CC-2.0
CC-0.3
CC-2.0
Max.
I
OH
=-
5mA
V
V
Except XOUT
V
V
CC
"H" output voltage
"L" output voltage
I
OH
=-200µA
V
V
CC
V
OH
I
I
OH
=
-
-
1 mA
V
V
CC
CC
V
V
Drive ability HIGH
Drive ability LOW
XOUT
OH=
500µA
V
V
CC-2.0
Except P1
0
to P1
7
, XOUT
2.0
I
OL= 5 mA
OL= 200 µA
V
V
I
0.45
V
OL
I
OL= 15 mA
OL= 5 mA
OL= 200 µA
2.0
2.0
P1
0
to P1
7
Drive capacity HIGH
Drive capacity LOW
V
V
I
I
0.45
2.0
2.0
1.0
Drive capacity LOW
V
V
Drive capacity HIGH
Drive capacity LOW
I
OL= 1 mA
XOUT
I
OL=500 µA
V
V
0.2
0.2
Hysteresis
V
T+-
V
T-
INT
KI , KI
RxD , RxD
o
, INT
, CNTR
, P45
1
, INT
2
, INT
3
, KI
0, KI1,
2
3
0
, CNTR
1
, TCIN,
0
1
2.2
5.0
V
RESET
I
IH
"H" input current
"L" input current
Pull-up resistance
V
I
=5V
=0V
µA
µA
kΩ
I
IL
V
I
-5.0
R
PULLUP
fXIN
RING-S
50
1.0
167
V
I=0V
30
X
IN
MΩ
kHz
V
R
Feedback resistance
Low-speed on-chip oscillator frequency
40
f
125
250
At stop mode
RAM retention voltage
2.0
V
RAM
NOTES:
1. Referenced to VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=20MHz unless otherwise specified.
Rev.1.60 Jan 27, 2006 page 18 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Table 5.11 Electrical Characteristics (2) [Vcc=5V]
Standard
Unit
Symbol
Measuring condition
Parameter
Min.
Typ.
9
Max.
15
X
IN=20 MHz (square wave)
High-speed
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
mA
X
IN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
8
5
14
mA
mA
X
IN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
X
IN=20 MHz (square wave)
Medium-speed
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
4
3
2
mA
mA
X
IN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
Power supply current
(VCC=3.3 to 5.5V)
I
CC
X
IN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
mA
In single-chip mode, the output
pins are open and other pins
are VSS
Main clock off
High-speed
on-chip oscillator
mode
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
No division
mA
mA
4
8
Main clock off
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
Division by 8
1.5
Main clock off
Low-speed
on-chip oscillator
mode
High-speed on-chip oscillator off
µA
µA
470
40
900
80
Low-speed on-chip oscillator on=125 kHz
Division by 8
Main clock off
Wait mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed
(1)
Peripheral clock operation
VC27=“0”
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed
Peripheral clock off
VC27=“0”
Wait mode
Stop mode
76
38
µA
µA
(1)
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
0.8
3.0
CM10="1"
Peripheral clock off
VC27="0"
NOTES:
1. Timer Y is operated with timer mode.
2. Referenced to VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=20MHz unless otherwise specified.
Rev.1.60 Jan 27, 2006 page 19 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 °C) [VCC=5V]
Table 5.12 XIN input
Standard
Symbol
Unit
Parameter
Min.
Max.
tC(XIN)
tWH(XIN)
tWL(XIN)
ns
ns
ns
XIN input cycle time
XIN input HIGH pulse width
XIN input LOW pulse width
50
25
25
–
–
–
________
Table 5.13 CNTR0 input, CNTR1 input, INT2 input
Standard
Symbol
Unit
Parameter
Min.
100
40
Max.
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
ns
ns
ns
–
–
–
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
40
________
Table 5.14 TCIN input, INT3 input
Standard
Symbol
Unit
Parameter
Min.
400(1)
200(2)
200(2)
Max.
tC(TCIN)
tWH(TCIN)
tWL(TCIN)
ns
ns
ns
–
–
–
TCIN input cycle time
TCIN input HIGH pulse width
TCIN input LOW pulse width
NOTES:
1. When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source
frequency x 3).
2. When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source
frequency x 1.5).
Table 5.15 Serial Interface
Symbol
Unit
Standard
Parameter
Min.
Max.
–
–
–
80
–
tC(CK)
ns
ns
ns
ns
ns
ns
ns
200
100
100
–
0
35
90
CLKi input cycle time
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
–
–
________
Table 5.16 External interrupt INT0 input
Standard
Symbol
Unit
Parameter
Min.
250(1)
250(2)
Max.
–
–
________
tW(INH)
tW(INL)
ns
ns
INT0 input HIGH pulse width
________
INT0 input LOW pulse width
NOTES:
________
________
1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width
to the greater value,either ( 1/ digital fi_l_t_e__r__c_lock frequency x 3) or the minimum value of standard.
________
2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Rev.1.60 Jan 27, 2006 page 20 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
VCC = 5V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
RxDi
td(C-Q)
tsu(D-C)
th(C-D)
tW(INL)
INTi
tW(INH)
Figure 5.4 Vcc=5V timing diagram
Rev.1.60 Jan 27, 2006 page 21 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Table 5.17 Electrical Characteristics (3) [Vcc=3V]
Standard
Unit
Measuring condition
Symbol
Parameter
Min.
Typ.
Max.
I
OH=-1mA
V
Except XOUT
V
CC
CC
CC
-
0.5
0.5
0.5
V
CC
CC
CC
"H" output voltage
"L" output voltage
V
Drive capacity HIGH
Drive capacity LOW
I
OH
=
-
0.1 mA
V
-
-
V
OH
X
OUT
V
V
V
V
I
OH
=-50 µA
I
OL= 1 mA
Except P1
P1 to P1
0 to P17, XOUT
V
0.5
V
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
I
OL= 2 mA
0.5
0.5
0
7
V
OL
I
OL= 1 mA
V
V
V
I
I
OL= 0.1 mA
OL=50 µA
0.5
0.5
0.8
X
OUT
0.2
0.2
Hysteresis
V
T+-VT-
V
INT
KI , KI
RxD , RxD
o
, INT
, CNTR
, P45
1
, INT
2
, INT
3
, KI
0, KI1,
2
3
0
, CNTR
1
, TCIN,
0
1
1.8
4.0
V
RESET
"H" input current
"L" input current
I
IH
VI=3V
µA
µA
kΩ
V
V
I=0V
-
4.0
I
IL
66
500
160
3.0
RPULLUP
I=0V
Pull-up resistance
Feedback resistance
MΩ
R
fXIN
XIN
kHz
125
250
Low-speed on-chip oscillator frequency
40
f
RING-S
2.0
V
V
RAM
RAM retention voltage
At stop mode
NOTES:
1. Referenced to VCC = AVCC = 2.7 to 3.3V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=10MHz unless otherwise specified.
Rev.1.60 Jan 27, 2006 page 22 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Table 5.18 Electrical Characteristics (4) [Vcc=3V]
Standard
Unit
Symbol
Measuring condition
Parameter
Min.
Typ.
8
Max.
13
X
IN=20 MHz (square wave)
High-speed
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
mA
X
IN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
7
5
12
mA
mA
X
IN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
X
IN=20 MHz (square wave)
Medium-speed
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
3
mA
mA
X
IN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
2.5
1.6
Power supply current
(VCC=2.7 to 3.3V)
I
CC
X
IN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
mA
In single-chip mode, the output
pins are open and other pins
are VSS
Main clock off
High-speed
on-chip oscillator
mode
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
No division
mA
mA
3.5
1.5
7.5
Main clock off
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
Division by 8
Main clock off
Low-speed
on-chip oscillator
mode
High-speed on-chip oscillator off
µA
µA
800
74
420
37
Low-speed on-chip oscillator on=125 kHz
Division by 8
Main clock off
Wait mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed
(1)
Peripheral clock operation
VC27=“0”
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Wait mode
µA
µA
35
70
(1)
When a WAIT instruction is executed
Peripheral clock off
VC27=“0”
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10="1"
Peripheral clock off
Stop mode
0.7
3.0
VC27="0"
NOTES:
1. Timer Y is operated with timer mode.
2. Referenced to VCC = AVCC = 2.7 to 3.3V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=10MHz unless otherwise specified.
Rev.1.60 Jan 27, 2006 page 23 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 °C) [VCC=3V]
Table 5.19 XIN input
Standard
Symbol
Unit
Parameter
Min.
100
40
Max.
tC(XIN)
tWH(XIN)
tWL(XIN)
ns
ns
ns
XIN input cycle time
XIN input HIGH pulse width
XIN input LOW pulse width
–
–
–
40
________
Table 5.20 CNTR0 input, CNTR1 input, INT2 input
Standard
Symbol
Unit
Parameter
Min.
300
120
120
Max.
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
ns
ns
ns
–
–
–
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
________
Table 5.21 TCIN input, INT3 input
Standard
Symbol
Unit
Parameter
Min.
1200(1)
600(2)
600(2)
Max.
tC(TCIN)
tWH(TCIN)
tWL(TCIN)
ns
ns
ns
–
–
–
TCIN input cycle time
TCIN input HIGH pulse width
TCIN input LOW pulse width
NOTES:
1. When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source
frequency x 3).
2. When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source
frequency x 1.5).
Table 5.22 Serial Interface
Symbol
Unit
Standard
Parameter
Min.
Max.
–
–
–
160
–
tC(CK)
ns
ns
ns
ns
ns
ns
ns
300
150
150
–
0
55
90
CLKi input cycle time
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
–
–
________
Table 5.23 External interrupt INT0 input
Standard
Symbol
Unit
Parameter
Min.
380(1)
380(2)
Max.
–
–
________
tW(INH)
tW(INL)
ns
ns
INT0 input HIGH pulse width
________
INT0 input LOW pulse width
NOTES:
________
________
1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width
to the greater value,either ( 1/ digital fi_l_t_e__r__c_lock frequency x 3) or the minimum value of standard.
________
2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Rev.1.60 Jan 27, 2006 page 24 of 26
REJ03B0034-0160
R8C/11 Group
5. Electrical Characteristics
VCC = 3V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
X
IN input
tWL(XIN)
tc(CK)
tW(CKH)
CLK
i
tW(CKL)
th(C-Q)
TxD
i
td(C-Q)
tsu(D-C)
th(C-D)
RxD
i
tW(INL)
INT
i
tW(INH)
Figure 5.5 Vcc=3V timing diagram
Rev.1.60 Jan 27, 2006 page 25 of 26
REJ03B0034-0160
R8C/11 Group
Package Dimensions
Package Dimensions
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
Previous Code
32P6U-A
MASS[Typ.]
0.2g
PLQP0032GB-A
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
6.9 7.0 7.1
6.9 7.0 7.1
1.4
Terminal cross section
32
9
A2
HD
HE
A
8.8 9.0 9.2
8.8 9.0 9.2
1.7
1
8
ZD
Index mark
A1
bp
b1
c
0.1 0.2
0
0.32 0.37 0.42
0.35
F
0.09
0.20
0.145
0.125
c1
L
L1
0°
8°
e
0.8
Detail F
y
x
0.20
0.10
*3
bp
x
e
y
ZD
ZE
L
0.7
0.7
0.3 0.5 0.7
1.0
L1
Rev.1.60 Jan 27, 2006 page 26 of 26
REJ03B0034-0160
REVISION HISTORY
R8C/11 Group Datasheet
Rev.
Date
Description
Summary
Page
1.00 Jun. 19, 2003
1.10 Sep. 08, 2003
First edition issued
2
Table 1.1: Shortest instruction execution time _a__n__d___f_(_X__IN) changed
5
Figure 1.3: Pin name changed from TXOUT to CNTR0
____________
6
Table 1.3: Pin name changed from TXOUT to CNTR0
The value of HR1 register after reset changed
The value of TC register after reset changed
Chapter “5. Electrical Characteristics” added
10
12
14
1.20 Oct. 31, 2003
2
Table 1.1: Power consumption values added
6
11
Table 1.3: Resistor value for CNVss and MODE deleted
Register name of address 005016 modified from CMP2IC to CMP1IC, register name
of address 005C16 modified from CMP1IC to CMP0IC
Table 5.2: Note 3 and Note 4 deleted
tsamp in Table 5.3 deleted
Figure 5.1 added
Table 5.10: Vcc changed from “4.2 to 5.5V” to “3.3V to 5.5V”, low-power on-chip
oscillator changed from “on 100kHz” to “125kHz”, XIN=5MHz deleted and
XIN=10MHz added in high-speed mode and medium-speed mode, VC27=”0” added
in stop mode measuring condition, data added and modified
Table 11 to Table 15 added
14
15
17
19
20
21
22
23
Figure 5.2 added
Table 5.16: Note 1, f(BCLK)=5 MHz changed to 10 MHz
Table 5.17: low-power ring oscillator changed from “on 100kHz” to “125kHz”,
XIN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed
mode, VC27=”0” added in stop mode measuring condition, data added and modi-
fied
24
25
Table 5.18 to Table 5.22 added
Figure 5.3 added
4
15
Table 1.2 : ** deleted
Table 5.4 revised
1.30 Dec 05, 2003
1.40 Sep 30, 2004
all pages Words standardized (on-chip oscillator, serial interface, A/D)
2
5
Table 1.1 revised
Figure 1.3, NOTES 3 added
6
Table 1.3 revised
9
Figure 3.1, NOTES added
10-13
12
14
15
16
17
18
One body sentence in chapter 4 added ; Title of Table 4.1 to 4.4 added
Table 4.3 revised ; Table 4.4 revised
Table 5.2 revised
Table 5.3 revised
Table 5.4 revised ; Table 16.5 revised
Table 5.6, 5.7 adn 5.8 revised ; Figure 5.3 revised
Table 5.9 revised ; Table 5.10 revised
A-1
REVISION HISTORY
R8C/11 Group Datasheet
Rev.
Date
Description
Summary
Table 5.12 revised ; Table 5.16 revised
Table 16.17 revised
Table 16.19 revised
Page
20
22
24
1.40 Sep 30, 2004
1.50 Apr.27.2005
4
5
Table 1.2, Figure 1.2 package name revised
Figure 1.3 package name revised
Table 4.1 revised
Table 4.3 revised
Table 5.3 partly revised
10
12
15
16
17
18
22
26
Table 5.4 partly added
Table 5.6, Table 5.7 revised
Table 5.9, Table 10 partly revised
Table 5.17 partly revised
Package Dimensions revised
1.60 Jan.27.2006
2
3
4
Table 1.1 Performance outline revised
Figure 1.1 Block diagram partly revised
1.4 Product Information, title of Table 1.2 “Product List” →
“Product Informaton” revised
Figure 1.2 Type No., Memory Size, and Package partly revised
Table 1.3 Pin description revised
6
7-8
2 Central Processing Unit (CPU) revised
Figure 2.1 CPU register revised
10
11
12
Table 4.1 SFR Information(1) NOTES:1 revised
Table 4.2 SFR Information(2) NOTES:1 revised
Table 4.3 SFR Information(3);
008116: “Prescaler Y” → “Prescaler Y Register”
008216: “Timer Y Secondary” → “Timer Y Secondary Register”
008316: “Timer Y Primary” → “Timer Y Primary Register”
008516: “Prescaler Z” → “Prescaler Z Register”
008616: “Timer Z Secondary” → “Timer Z Secondary Register”
008716: “Timer Z Primary” → “Timer Z Primary Register”
008C16: “Prescaler X” → “Prescaler X Register” revised
NOTES:1, 2 revised
13
14
15
Table 4.4 SFR Information(4) NOTES:1 revised
Table 5.2 Recommended Operating Conditions; NOTES: 1, 2, 3 revised
Table 5.3 A/D Conversion Characteristics;
“A/D operation clock frequency” → “A/D operating clock frequency” revised
NOTES: 1, 2, 3, 4 revised
16
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics;
“Topr” → “Ambient temperature” revised
Measuring condition of byte program time and block erase time deleted
Table 5.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2)
NOTES: 3 revised
17
18
Table 5.8 High-speed On-Chip Oscillator Circuit Electrical Characteristics;
“High-speed on-chip oscillator temperature dependence”
→
“High-speed on-chip oscillator frequency temperature dependence” revised
Table 5.10 Electrical Characteristics (1) [VCC=5V];
“P10 to P17 Except XOUT” → “Except P10 to P17, XOUT” revised
A-2
REVISION HISTORY
R8C/11 Group Datasheet
Rev.
Date
Description
Page
Summary
1.60 Jan.27.2006
19
Table 5.11 Electrical Characteristics (2) [VCC=5V]
NOTES: 1, 2 revised
Measuring condition Stop mode: “Topr = 25 °C”
22
23
Table 5.17 Electrical Characteristics (3) [VCC=3V]
“P10 to P17 Except XOUT” → “Except P10 to P17, XOUT” revised
Table 5.18 Electrical Characteristics (4) [VCC=3V]
NOTES: 1, 2 revised
Measuring condition Stop mode: “Topr = 25 °C”
A-3
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