R8C-18 [RENESAS]
SINGLE-CHIP 16-BIT CMOS MCU; 单芯片16位CMOS微控制器
| 型号： | R8C-18 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 16-BIT CMOS MCU |
| 文件： | 总41页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R8C/18 Group, R8C/19 Group
SINGLE-CHIP 16-BIT CMOS MCU
REJ03B0124-0140
Rev.1.40
Apr 14, 2006
1. Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the
R8C/Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic
molded-HWQFN. It implements sophisticated instructions for a high level of instruction efficiency. With 1
Mbyte of address space, they are capable of executing instructions at high speed.
Furthermore, the R8C/19 Group has on-chip data flash ROM (1 KB × 2 blocks).
The difference between the R8C/18 Group and R8C/19 Group is only the presence or absence of data
flash ROM. Their peripheral functions are the same.
1.1
Applications
Electric household appliances, office equipment, housing equipment (sensors, security systems), general
industrial equipment, audio equipment, etc.
Rev.1.40 Apr 14, 2006 Page 1 of 38
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1.Overview
1.2
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/18 Group and Table 1.2 outlines the
Functions and Specifications for R8C/19 Group.
Table 1.1
Functions and Specifications for R8C/18 Group
Item
Specification
CPU
Number of fundamental
89 instructions
instructions
Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
time
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Single-chip
1 Mbyte
Operation mode
Address space
Memory capacity
Refer to Table 1.3 Product Information for R8C/18
Group
Peripheral
Functions
Ports
I/O ports: 13 pins (including LED drive port)
Input port: 3 pins
LED drive ports
Timers
I/O ports: 4 pins
Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
1 channel
Serial interfaces
Clock synchronous serial I/O, UART
1 channel
UART
Comparator
Watchdog timer
1-bit comparator: 1 circuit, 4 channels
15 bits × 1 channel (with prescaler)
Reset start selectable, count source protection mode
Internal: 10 sources, External: 4 sources, Software: 4
sources,
Interrupts
Priority levels: 7 levels
Clock generation circuits
2 circuits
• Main clock oscillation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency
adjustment function
Oscillation stop detection
function
Main clock oscillation stop detection function
Voltage detection circuit
Power-on reset circuit
Supply voltage
On-chip
On-chip
Electric
Characteristics
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, comparator stopped)
Typ. 5 mA (VCC = 3.0V, f(XIN) = 10 MHz, comparator stopped)
Current consumption
Typ. 35
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
µA (VCC = 3.0 V, wait mode, peripheral clock off)
Programming and erasure
100 times
endurance
Operating Ambient Temperature
-20 to 85°C
-40 to 85°C (D version)
20-pin molded-plastic LSSOP
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
Package
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1.Overview
Table 1.2
Functions and Specifications for R8C/19 Group
Item
Specification
CPU
Number of fundamental
89 instructions
instructions
Minimum instruction
execution time
Operation mode
Address space
Memory capacity
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Single-chip
1 Mbyte
Refer to Table 1.4 Product Information for R8C/19
Group
Peripheral
Functions
Ports
I/O ports: 13 pins (including LED drive port)
Input port: 3 pins
LED drive ports
Timers
I/O ports: 4 pins
Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
1 channel
Serial interfaces
Clock synchronous serial I/O, UART
1 channel
UART
Comparator
Watchdog timer
1-bit comparator: 1 circuit, 4 channels
15 bits × 1 channel (with prescaler)
Reset start selectable, count source protection mode
Internal: 10 sources, External: 4 sources, Software: 4
sources,
Interrupts
Priority levels: 7 levels
Clock generation circuits
2 circuits
• Main clock generation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency
adjustment function
Oscillation stop detection
function
Main clock oscillation stop detection function
Voltage detection circuit
Power-on reset circuit
Supply voltage
On-chip
On-chip
Electric
Characteristics
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, comparator stopped)
Typ. 5 mA (VCC = 3.0 V, f(XIN) = 10MHz, comparator stopped)
Typ. 35 µA (VCC = 3.0 V, wait mode, peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Current consumption
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
endurance
Operating Ambient Temperature
10,000 times (data flash)
1,000 times (program ROM)
-20 to 85°C
-40 to 85°C (D version)
20-pin molded-plastic LSSOP
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
Package
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1.Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
1
3
4
I/O ports
Port P1
Port P3
Port P4
Peripheral Functions
System clock generator
Comparator
(1 bit × 4 channels)
Timers
XIN-XOUT
High-speed on-chip
oscillator
Low-speed on-chip
oscillator
Timer X (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
UART or
clock synchronous serial I/O
(8 bits × 1 channel)
UART
(8 bits × 1 channel)
Watchdog timer
(15 bits)
Memory
R8C/Tiny Series CPU core
ROM(1)
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
R2
R3
RAM(2)
A0
A1
FB
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.1
Block Diagram
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1.Overview
1.4
Product Information
Table 1.3 lists Product Information for R8C/18 Group and Table 1.4 lists Product Information for R8C/19
Group.
Table 1.3
Product Information for R8C/18 Group
ROM Capacity RAM Capacity Package Type
Current of Apr. 2006
Type No.
Remarks
R5F21181SP
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
384 bytes
512 bytes
768 bytes
1 Kbyte
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
Flash memory version
R5F21182SP
R5F21183SP
R5F21184SP
R5F21181DSP (D)
R5F21182DSP (D)
R5F21183DSP (D)
R5F21184DSP (D)
R5F21181DD
R5F21182DD
R5F21183DD
R5F21184DD
R5F21182NP
384 bytes
512 bytes
768 bytes
1 Kbyte
D version
384 bytes
512 bytes
768 bytes
1 Kbyte
PRDP0020BA-A Flash memory version
PRDP0020BA-A
PRDP0020BA-A
PRDP0020BA-A
512 bytes
768 bytes
1 Kbyte
PWQN0028KA-B Flash memory version
PWQN0028KA-B
R5F21183NP
R5F21184NP
PWQN0028KA-B
(D): Under Development
Type No. R 5 F 21 18 4 D SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Operating ambient temperature -20°C to 85°C
ROM capacity
2: 8 KB
3: 12 KB
4: 16 KB
R8C/18 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductors
Figure 1.2
Type Number, Memory Size, and Package of R8C/18 Group
Rev.1.40 Apr 14, 2006 Page 5 of 38
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1.Overview
Table 1.4
Product Information for R8C/19 Group
Current of Apr. 2006
ROM Capacity
RAM
Capacity
Type No.
Package Type
Remarks
Program ROM Data flash
R5F21191SP
R5F21192SP
R5F21193SP
R5F21194SP
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
1 Kbyte × 2 384 bytes PLSP0020JB-A Flash memory version
1 Kbyte × 2 512 bytes PLSP0020JB-A
1 Kbyte × 2 768 bytes PLSP0020JB-A
1 Kbyte × 2 1 Kbyte
PLSP0020JB-A
R5F21191DSP (D) 4 Kbytes
R5F21192DSP (D) 8 Kbytes
R5F21193DSP (D) 12 Kbytes
R5F21194DSP (D) 16 Kbytes
1 Kbyte × 2 384 bytes PLSP0020JB-A D version
1 Kbyte × 2 512 bytes PLSP0020JB-A
1 Kbyte × 2 768 bytes PLSP0020JB-A
1 Kbyte × 2 1 Kbyte
PLSP0020JB-A
R5F21191DD
R5F21192DD
R5F21193DD
R5F21194DD
R5F21192NP
R5F21193NP
R5F21194NP
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
1 Kbyte × 2 384 bytes PRDP0020BA-A Flash memory version
1 Kbyte × 2 512 bytes PRDP0020BA-A
1 Kbyte × 2 768 bytes PRDP0020BA-A
1 Kbyte × 2 1 Kbyte
PRDP0020BA-A
1 Kbyte × 2 512 bytes PWQN0028KA-B Flash memory version
1 Kbyte × 2 768 bytes PWQN0028KA-B
1 Kbyte × 2 1 Kbyte
PWQN0028KA-B
(D): Under Development
Type No. R 5 F 21 19 4 D SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Operating ambient temperature -20°C to 85°C
ROM capacity
2: 8 KB
3: 12 KB
4: 16 KB
R8C/19 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductors
Figure 1.3
Type Number, Memory Size, and Package of R8C/19 Group
Rev.1.40 Apr 14, 2006 Page 6 of 38
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1.Overview
1.5
Pin Assignments
Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin
Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for
PWQN0028KA-B Package (Top View).
PIN assignments (top view)
P3_5/CMP1_2
20
19
18
17
16
15
14
13
12
11
P3_4/CMP1_1
1
2
3
4
5
6
7
8
9
10
P3_3/TCIN/INT3/CMP1_0
P1_0/KI0/AN8/CMP0_0
P1_1/KI1/AN9/CMP0_1
P4_2/VREF
P3_7/CNTR0/TXD1
RESET
XOUT/P4_7(1)
VSS/AVSS
P1_2/KI2/AN10/CMP0_2
P1_3/KI3/AN11/TZOUT
P1_4/TXD0
XIN/P4_6
VCC/AVCC
MODE
P4_5/INT0/RXD1
P1_5/RXD0/CNTR01/INT11
P1_6/CLK0
P1_7/CNTR00/INT10
NOTE:
1. P4_7 is an input-only port.
Package: PLSP0020JB-A(20P2F-A)
Figure 1.4
Pin Assignments for PLSP0020JB-A Package (Top View)
Rev.1.40 Apr 14, 2006 Page 7 of 38
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1.Overview
PIN assignments (top view)
P3_5/CMP1_2
20
19
18
17
16
15
14
13
12
11
P3_4/CMP1_1
1
P3_3/TCIN/INT3/CMP1_0
P1_0/KI0/AN8/CMP0_0
P1_1/KI1/AN9/CMP0_1
P4_2/VREF
2
P3_7/CNTR0/TXD1
RESET
3
XOUT/P4_7(1)
VSS/AVSS
4
5
P1_2/KI2/AN10/CMP0_2
P1_3/KI3/AN11/TZOUT
P1_4/TXD0
6
XIN/P4_6
7
VCC/AVCC
8
MODE
P1_5/RXD0/CNTR01/INT11
P1_6/CLK0
P4_5/INT0/RXD1
9
10
P1_7/CNTR00/INT10
NOTE:
1. P4_7 is an input-only port.
Package: PRDP0020BA-A(20P4B)
Pin Assignments for PRDP0020BA-A Package (Top View)
Figure 1.5
Rev.1.40 Apr 14, 2006 Page 8 of 38
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1.Overview
PIN Assignment (top view)
21 20 19 18 17 16 15
P1_1/AN9/KI1/CMP0_1
22
23
24
25
26
27
28
14
13
12
11
10
9
P1_4/TXD0
P1_5/RXD0/CNTR01/INT11
P1_6/CLK0
P1_0/AN8/KI0/CMP0_0
P3_3/TCIN/INT3/CMP1_0
P3_4/CMP1_1
R8C/18 Group
R8C/19 Group
P1_7/CNTR00/INT10
P4_5/INT0/RXD1
MODE
P3_5/CMP1_2
P3_7/CNTR0/TXD1
RESET
8
VCC/AVCC
1
2
3
4
5
6
7
NOTES:
1. P4_7 is a port for the input.
Package: PWQN0028KA-B(28PJW-B)
Figure 1.6
Pin Assignments for PWQN0028KA-B Package (Top View)
Rev.1.40 Apr 14, 2006 Page 9 of 38
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1.Overview
1.6
Pin Functions
Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A,
PRDP0020BA-A packages, and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KA-
B package.
Table 1.5
Type
Pin Functions
Symbol
I/O Type
I
Description
Power supply input VCC
VSS
Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to
the VSS pin.
Analog power
supply input
AVCC, AVSS
I
Power supply for the comparator
Connect a capacitor between AVCC and AVSS.
Reset input
MODE
RESET
MODE
XIN
I
I
I
Input “L” on this pin resets the MCU.
Connect this pin to VCC via a resistor.
Main clock input
These pins are provided for main clock generation
circuit I/O. Connect a ceramic resonator or a
crystal oscillator between the XIN and XOUT pins.
To use an external clock, input it to the XIN pin
and leave the XOUT pin open.
Main clock output
INT interrupt
XOUT
O
INT0, INT1, INT3
I
I
INT interrupt input pins
Key input interrupt input pins
Timer X I/O pin
Key input interrupt KI0 to KI3
Timer X
CNTR0
CNTR0
TZOUT
TCIN
I/O
O
O
I
Timer X output pin
Timer Z output pin
Timer C input pin
Timer Z
Timer C
CMP0_0 to CMP0_2,
CMP1_0 to CMP1_2
O
Timer C output pins
Serial interface
CLK0
I/O
Transfer clock I/O pin
RXD0, RXD1
TXD0, TXD1
I
O
I
Serial data input pins
Serial data output pins
Reference voltage VREF
input
Reference voltage input pin to comparator
Comparator
I/O port
AN8 to AN11
I
Analog input pins to comparator
P1_0 to P1_7, P3_3
to P3_5, P3_7, P4_5
I/O
CMOS I/O ports. Each port has an I/O select
direction register, allowing each pin in the port to
be directed for input or output individually.
Any port set to input can be set to use a pull-up
resistor or not by a program.
P1_0 to P1_3 also function as LED drive ports.
Input port
I: Input
P4_2, P4_6, P4_7
I
Input-only ports
O: Output
I/O: Input and output
Rev.1.40 Apr 14, 2006 Page 10 of 38
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1.Overview
Table 1.6
Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A packages
I/O Pin Functions for Peripheral Modules
Pin
Number
Control
Pin
Port
Interrupt
Timer
Serial Interface
Comparator
1
2
P3_5
P3_7
CMP1_2
TXD1
CNTR0
3
RESET
XOUT
4
5
6
7
8
9
P4_7
P4_6
VSS/AVSS
XIN
VCC/AVCC
MODE
P4_5
P1_7
RXD1
INT0
10
CNTR00
CNTR01
INT10
11
12
P1_6
P1_5
CLK0
RXD0
INT11
13
14
P1_4
P1_3
TXD0
TZOUT
AN11
AN10
KI3
KI2
15
P1_2
CMP0_2
16
17
VREF
P4_2
P1_1
CMP0_1
CMP0_0
AN9
AN8
KI1
KI0
18
19
20
P1_0
P3_3
P3_4
TCIN/CMP1_0
CMP1_1
INT3
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1.Overview
Table 1.7
Pin Name Information by Pin Number of PWQN0028KA-B package
I/O Pin of Peripheral Function
Pin
Number
Control
Pin
Port
Interrupt
Timer
Serial Interface
Comparator
1
2
NC
XOUT
P4_7
3
4
5
6
7
8
9
VSS/AVSS
NC
NC
XIN
P4_6
NC
VCC/AVCC
MODE
10
11
12
13
14
15
16
17
18
P4_5
P1_7
P1_6
P1_5
P1_4
RXD1
INT0
CNTR00
CNTR01
INT10
CLK0
RXD0
TXD0
INT11
NC
NC
P1_3
P1_2
TZOUT
AN11
AN10
KI3
KI2
CMP0_2
19
20
21
22
NC
VREF
NC
P4_2
P1_1
P1_0
CMP0_1
CMP0_0
AN9
AN8
KI1
KI0
23
24
25
26
27
P3_3
P3_4
P3_5
P3_7
TCIN/CMP1_0
CMP1_1
INT3
CMP1_2
TXD1
CNTR0
28
RESET
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2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R2
R2
R3
Data registers (1)
R3
A0
Address registers (1)
A1
FB
Frame base register (1)
b19
b15
b0
Interrupt table register
Program counter
INTBH
INTBL
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
b19
b0
PC
b15
b0
User stack pointer
Interrupt stack pointer
Static base register
USP
ISP
SB
b15
b0
b0
Flag register
FLG
b15
b8
b7
IPL
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.1.40 Apr 14, 2006 Page 13 of 38
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2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0
can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data
registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a
32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
It is also used for transfer, arithmetic and logic operations. A1 is analogous to A0. A1 can be combined
with A0 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide, indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch
between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and logic
unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when the operation results in an overflow; otherwise to 0.
Rev.1.40 Apr 14, 2006 Page 14 of 38
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2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is
set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.1.40 Apr 14, 2006 Page 15 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
3.Memory
3. Memory
3.1
R8C/18 Group
Figure 3.1 is a Memory Map of R8C/18 Group. The R8C/18 Group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM area is allocated lower addresses, beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-
Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved for future use and cannot be accessed by users.
00000h
SFR
(See 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer • oscillation stop detection • voltage monitor 2
0YYYYh
Address break
(Reserved)
Reset
Internal ROM
0FFFFh
0FFFFh
FFFFFh
Expanded area
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
0C000h
Size
Address 0XXXXh
007FFh
R5F21184SP, R5F21184DSP, R5F21184DD, R5F21184NP
R5F21183SP, R5F21183DSP, R5F21183DD, R5F21183NP
R5F21182SP, R5F21182DSP, R5F21182DD, R5F21182NP
R5F21181SP, R5F21181DSP, R5F21181DD
16 Kbytes
12 Kbytes
8 Kbytes
4 Kbytes
1 Kbyte
768 bytes
512 bytes
384 bytes
0D000h
006FFh
0E000h
005FFh
0F000h
0057Fh
Figure 3.1
Memory Map of R8C/18 Group
Rev.1.40 Apr 14, 2006 Page 16 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
3.Memory
3.2
R8C/19 Group
Figure 3.2 is a Memory Map of R8C/19 Group. The R8C/19 group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For
example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-
Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved for future use and cannot be accessed by users.
00000h
SFR
(See 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02400h
Internal ROM
0FFDCh
(data flash)(1)
Undefined instruction
02BFFh
Overflow
BRK instruction
Address match
Single step
Watchdog timer • oscillation stop detection • voltage monitor 2
0YYYYh
0FFFFh
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
Expanded area
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
0C000h
Size
Address 0XXXXh
007FFh
R5F21194SP, R5F21194DSP, R5F21194DD, R5F21194NP
R5F21193SP, R5F21193DSP, R5F21193DD, R5F21193NP
R5F21192SP, R5F21192DSP, R5F21192DD, R5F21192NP
R5F21191SP, R5F21191DSP, R5F21191DD
16 Kbytes
12 Kbytes
8 Kbytes
4 Kbytes
1 Kbyte
768 bytes
512 bytes
384 bytes
0D000h
006FFh
0E000h
005FFh
0F000h
0057Fh
Figure 3.2
Memory Map of R8C/19 Group
Rev.1.40 Apr 14, 2006 Page 17 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.4 list the
special function registers.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
00h
00h
01101000b
00100000b
Address Match Interrupt Enable Register
Protect Register
AIER
PRCR
00h
00h
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
00000100b
XXh
WDTR
WDTS
WDC
XXh
00011111b
00h
RMAD0
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Count Source Protection Mode Register
INT0 Input Filter Select Register
CSPR
INT0F
00h
00h
001Fh
0020h
0021h
0022h
0023h
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
HRA0
HRA1
HRA2
00h
When shipping
00h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
(2)
VCA1
VCA2
00001000b
Voltage Detection Register 1
(2)
(3)
Voltage Detection Register 2
00h
(4)
01000000b
0033h
0034h
0035h
0036h
(2)
(3)
VW1C
VW2C
Voltage Monitor 1 Circuit Control Register
0000X000b
(4)
0100X001b
00h
(5)
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Voltage Monitor 2 Circuit Control Register
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register.
3. After hardware reset.
4. After power-on reset or voltage monitor 1 reset.
5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3.
Rev.1.40 Apr 14, 2006 Page 18 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
4. Special Function Registers (SFRs)
(1)
Table 4.2
SFR Information (2)
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
Register
Symbol
After reset
Key Input Interrupt Control Register
KUPIC
ADIC
XXXXX000b
XXXXX000b
Comparator Conversion Interrupt Control Register
Compare 1 Interrupt Control Register
CMP1IC
S0TIC
S0RIC
S1TIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
S1RIC
Timer X Interrupt Control Register
TXIC
XXXXX000b
Timer Z Interrupt Control Register
INT1 Interrupt Control Register
TZIC
XXXXX000b
XXXXX000b
INT1IC
005Ah
INT3IC
XXXXX000b
INT3 Interrupt Control Register
005Bh
005Ch
005Dh
Timer C Interrupt Control Register
Compare 0 Interrupt Control Register
TCIC
CMP0IC
INT0IC
XXXXX000b
XXXXX000b
XX00X000b
INT0 Interrupt Control Register
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.40 Apr 14, 2006 Page 19 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
4. Special Function Registers (SFRs)
(1)
Table 4.3
SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
After reset
Timer Z Mode Register
TZMR
00h
Timer Z Waveform Output Control Register
Prescaler Z Register
PUM
00h
FFh
FFh
FFh
PREZ
TZSC
TZPR
Timer Z Secondary Register
Timer Z Primary Register
Timer Z Output Control Register
Timer X Mode Register
Prescaler X Register
Timer X Register
Timer Count Source Setting Register
TZOC
TXMR
PREX
TX
00h
00h
FFh
FFh
00h
TCSS
Timer C Register
TC
00h
00h
External Input Enable Register
Key Input Enable Register
INTEN
KIEN
00h
00h
Timer C Control Register 0
Timer C Control Register 1
Capture, Compare 0 Register
TCC0
TCC1
TM0
00h
00h
00h
(2)
00h
FFh
FFh
00h
XXh
XXh
XXh
Compare 1 Register
TM1
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
U0BRG
U0TB
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
00001000b
00000010b
XXh
XXh
00h
UART Transmit/Receive Control Register 2
UCON
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. When the output compare mode is selected (the TCC13 bit in the TCC1 register = 1), the value is set to FFFF16.
Rev.1.40 Apr 14, 2006 Page 20 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
4. Special Function Registers (SFRs)
(1)
Table 4.4
SFR Information (4)
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
After reset
A/D Register
AD
XXh
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
00000XXXb
00h
Port P1 Register
P1
XXh
00h
XXh
Port P1 Direction Register
Port P3 Register
PD1
P3
Port P3 Direction Register
Port P4 Register
PD3
P4
00h
XXh
Port P4 Direction Register
PD4
00h
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
DRR
00XX0000b
XXXXXX0Xb
00h
Port P1 Drive Capacity Control Register
Timer C Output Control Register
TCOUT
00h
01B3h
01B4h
01B5h
01B6h
01B7h
Flash Memory Control Register 4
Flash Memory Control Register 1
Flash Memory Control Register 0
Optional Function Select Register
FMR4
FMR1
FMR0
OFS
01000000b
1000000Xb
00000001b
(Note 2)
0FFFFh
X: Undefined
NOTES:
1. The blank regions, 0100h to 01B2h and 01B8h to 02FFh are all reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.1.40 Apr 14, 2006 Page 21 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply voltage
Condition
VCC = AVCC
Rated Value
Unit
V
-0.3 to 6.5
-0.3 to 6.5
AVCC
Analog supply voltage
VCC = AVCC
V
VI
Input voltage
-0.3 to VCC+0.3
-0.3 to VCC+0.3
300
V
V
VO
Pd
Output voltage
Power dissipation
Topr = 25°C
mW
°C
°C
Topr
Tstg
Operating ambient temperature
Storage temperature
-20 to 85 / -40 to 85 (D version)
-65 to 150
Table 5.2
Recommended Operating Conditions
Standard
Symbol
Parameter
Conditions
Unit
Min.
Typ.
−
Max.
5.5
−
VCC
Supply voltage
2.7
V
V
AVCC
VSS
Analog supply voltage
Supply voltage
−
VCC
0
−
−
V
AVSS
VIH
Analog supply voltage
Input “H” voltage
−
0
−
V
0.8VCC
−
VCC
0.2VCC
-60
V
VIL
Input “L” voltage
0
−
V
IOH(sum)
Peak sum output Sum of all
−
−
mA
“H” current
pins IOH (peak)
IOH(peak)
IOH(avg)
IOL(sum)
Peak output “H” current
−
−
−
−
−
−
-10
-5
mA
mA
mA
Average output “H” current
Peak sum output Sum of all
60
“L” currents
pins IOL (peak)
IOL(peak)
Peak output “L”
currents
Except P1_0 to P1_3
P1_0 to P1_3
−
−
−
−
−
−
0
0
−
−
−
−
−
−
−
−
10
30
10
5
mA
mA
Drive capacity HIGH
Drive capacity LOW
mA
IOL(avg)
Average output
“L” current
Except P1_0 to P1_3
P1_0 to P1_3
mA
Drive capacity HIGH
Drive capacity LOW
3.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 3.0 V
15
5
mA
mA
f(XIN)
Main clock input oscillation frequency
20
10
MHz
MHz
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. Typical values when average output current is 100 ms.
Rev.1.40 Apr 14, 2006 Page 22 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.3
Comparator Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min.
−
Typ.
−
Max.
1
−
Resolution
Bit
mV
µs
φAD = 10 MHz(3)
φAD = 10 MHz(3)
−
Absolute accuracy
Conversion time
−
−
±20
−
tconv
Vref
VIA
−
1
−
Reference voltage
0
−
AVCC
AVCC
10
V
Analog input voltage
0
−
V
Comparator conversion operating clock
frequency(2)
1
−
MHz
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. If f1 exceeds 10 MHz, divided f1 and ensure the comparator conversion operating clock frequency (φAD) is 10 MHz or below.
3. If AVcc is less than 4.2 V, divided f1 and ensure the comparator conversion operating clock frequency (φAD) is f1/2 or below.
P1
30pF
P3
P4
Figure 5.1
Port P1, P3, and P4 Measurement Circuit
Rev.1.40 Apr 14, 2006 Page 23 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.4
Flash Memory (Program ROM) Electrical Characteristics
Standard
Unit
Symbol
Parameter
Conditions
R8C/18 Group
Min.
Typ.
−
Max.
−
Program/erase endurance(2)
100(3)
−
times
times
µs
1,000(3)
R8C/19 Group
−
−
−
Byte program time
Block erase time
−
−
−
50
0.4
−
400
9
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
97+CPUclock
× 6 cycles
µs
−
−
−
Interval from erase start/restart until
following suspend request
650
0
−
−
−
−
µs
ns
µs
Interval from program start/restart until
following suspend request
−
Time from suspend until program/erase
restart
−
3+CPU clock
× 4 cycles
−
−
−
−
Program, erase voltage
Read voltage
2.7
2.7
0
−
−
−
−
5.5
5.5
60
−
V
V
Program, erase temperature
Data hold time(8)
°C
Ambient temperature = 55 °C
20
year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting
prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the
normal time delay to Suspend can be applied to the request.However, we recommend that a suspend request with an interval
of less than 650 µs is only used once because, if the suspend state continues, erasure cannot operate and the incidence of
erasure error rises.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the number of erase operations between block A and block B
can further reduce the effective number of rewrites. It is also advisable to retain data on the erase count of each block and
limit the number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support
representative.
8. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.1.40 Apr 14, 2006 Page 24 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.5
Flash Memory (Data flash Block A, Block B) Electrical Characteristics
Standard
Unit
Symbol
Parameter
Conditions
Min.
10,000(3)
−
Typ.
−
Max.
−
Program/erase endurance(2)
−
−
times
Byte program time
50
400
µs
(Program/erase endurance ≤ 1,000 times)
−
Byte program time
(Program/erase endurance > 1,000 times)
−
−
65
0.2
0.3
−
−
9
−
µs
s
−
Block erase time
(Program/erase endurance ≤ 1,000 times)
−
Block erase time
(Program/erase endurance > 1,000 times)
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
97+CPUclock
× 6 cycles
µs
µs
ns
µs
−
−
−
Interval from erase start/restart until
following suspend request
650
0
−
−
Interval from program start/restart until
following suspend request
−
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
−
−
−
−
Program, erase voltage
Read voltage
2.7
2.7
−
−
−
−
5.5
5.5
85
−
V
V
-20(8)
20
Program, erase temperature
°C
Data hold time(9)
Ambient temperature = 55 °C
year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting
prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the
normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an interval
of less than 650 µs is only used once because, if the suspend state continues, erasure cannot operate and the incidence of
erasure error rises.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support
representative.
8. -40 °C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(Maskable interrupt request)
FMR46
Clock-dependent
Fixed time (97 µs)
time
Access restart
td(SR-SUS)
Figure 5.2
Transition Time to Suspend
Rev.1.40 Apr 14, 2006 Page 25 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.6
Voltage Detection 1 Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Voltage detection level(3)
Condition
Min.
2.70
−
Typ.
2.85
600
−
Max.
3.00
−
Vdet1
−
V
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts(2)
VCA26 = 1, VCC = 5.0 V
nA
µs
td(E-A)
−
100
Vccmin
MCU operating voltage minimum value
2.7
−
−
V
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85 °C.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
3. Ensure that Vdet2 > Vdet1.
Table 5.7
Voltage Detection 2 Circuit Electrical Characteristics
Standard
Typ.
3.30
40
Symbol
Parameter
Voltage detection level(4)
Condition
Unit
Min.
3.00
−
Max.
3.60
−
Vdet2
V
Voltage monitor 2 interrupt request generation time(2)
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts(3)
−
µs
nA
µs
−
VCA27 = 1, VCC = 5.0 V
−
600
−
td(E-A)
−
−
100
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85 °C.
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
4. Ensure that Vdet2 > Vdet1.
Rev.1.40 Apr 14, 2006 Page 26 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.8
Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset)
Symbol
Parameter
Condition
Standard
Unit
Min.
−
Typ.
−
Max.
Vdet1
100
Vpor2
Power-on reset valid voltage
-20°C ≤ Topr ≤ 85°C
-20°C ≤ Topr ≤ 85°C,
tw(por2) ≥ 0s(3)
V
tw(Vpor2-Vdet1) Supply voltage rising time when power-on reset is
deasserted(1)
−
−
ms
NOTES:
1. This condition is not applicable when using with Vcc ≥ 1.0 V.
2. When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10 s, refer to Table
5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset).
3. tw(por2) is the time to hold the external power below effective voltage (Vpor2).
Table 5.9
Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset)
Symbol
Parameter
Condition
Standard
Unit
Min.
−
Typ.
−
Max.
0.1
Vpor1
Power-on reset valid voltage
-20°C ≤ Topr ≤ 85°C
0°C ≤ Topr ≤ 85°C,
tw(por1) ≥ 10 s(2)
V
tw(Vpor1-Vdet1)
tw(Vpor1-Vdet1)
tw(Vpor1-Vdet1)
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
−
−
100
ms
Supply voltage rising time when power-on reset is
deasserted
-20°C ≤ Topr < 0°C,
tw(por1) ≥ 30 s(2)
−
−
−
−
−
−
100
1
ms
ms
ms
Supply voltage rising time when power-on reset is
deasserted
-20°C ≤ Topr < 0°C,
tw(por1) ≥ 10 s(2)
Supply voltage rising time when power-on reset is
deasserted
0°C ≤ Topr ≤ 85°C,
tw(por1) ≥ 1 s(2)
0.5
NOTES:
1. When not using voltage monitor 1, use with Vcc ≥ 2.7 V.
2. tw(por1) is the time to hold the external power below effective voltage (Vpor1).
(3)
(3)
Vdet1
Vdet1
Vccmin
Vpor2
Vpor1
Sampling time(1, 2)
tw(Vpor1–Vdet1)
tw(por1)
tw(por2) tw(Vpor2–Vdet1)
Internal
reset signal
(“L” valid)
1
1
× 32
× 32
fRING-S
fRING-S
NOTES:
1. Hold the voltage inside the MCU operation voltage range (Vccmin or above) within the sampling time.
2. The sampling clock can be selected. Refer to 7. Voltage Detection Circuit for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details.
Figure 5.3
Reset Circuit Electrical Characteristics
Rev.1.40 Apr 14, 2006 Page 27 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.10
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Condition
Min.
Typ.
8
Max.
−
High-speed on-chip oscillator frequency when the
reset is deasserted
VCC = 5.0 V, Topr = 25 °C
−
−
MHz
0 to +60 °C/5 V ± 5 %(3)
−
High-speed on-chip oscillator frequency temperature
supply voltage dependence(2)
7.76
7.68
7.44
−
−
−
8.24
8.32
8.32
MHz
MHz
MHz
-20 to +85 °C/2.7 to 5.5 V(3)
-40 to +85 °C/2.7 to 5.5 V(3)
NOTES:
1. The measurement condition is VCC = 5.0 V and Topr = 25 °C.
2. Refer to 10.6.4 High-Speed On-Chip Oscillator Clock for notes on high-speed on-chip oscillator clock.
3. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to
00h.
Table 5.11
Power Supply Circuit Timing Characteristics
Standard
Symbol
Parameter
Condition
Unit
Min.
1
Typ.
Max.
2000
td(P-R)
Time for internal power supply stabilization during
power-on(2)
−
µs
STOP exit time(3)
td(R-S)
−
−
150
µs
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25 °C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.1.40 Apr 14, 2006 Page 28 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.12
Electrical Characteristics (1) [VCC = 5 V]
Standard
Unit
Symbol
Parameter
Output “H” voltage Except XOUT
Condition
Min.
Typ.
Max.
VCC
VCC
VCC
VOH
IOH = -5 mA
VCC − 2.0
VCC − 0.3
VCC − 2.0
−
−
−
V
V
V
IOH = -200 µA
XOUT
Drive capacity
HIGH
IOH = -1 mA
Drive capacity
LOW
IOH = -500 µA VCC − 2.0
−
VCC
V
VOL
Output “L” voltage
Except P1_0 to
P1_3, XOUT
IOL = 5 mA
−
−
−
−
−
2.0
0.45
2.0
V
V
V
IOL = 200 µA
P1_0 to P1_3
Drive capacity
HIGH
IOL = 15 mA
IOL = 5 mA
IOL = 200 µA
IOL = 1 mA
IOL = 500 µA
−
Drive capacity
LOW
−
−
−
−
−
−
2.0
0.45
2.0
V
V
V
V
V
Drive capacity
LOW
−
XOUT
Drive capacity
HIGH
−
Drive capacity
LOW
−
2.0
VT+-VT-
Hysteresis
0.2
1.0
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, CNTR0,
CNTR1, TCIN,
RXD0
0.2
−
2.2
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 5 V
VI = 0 V
VI = 0 V
−
−
−
−
5.0
-5.0
167
−
µA
µA
kΩ
MΩ
kHz
V
RPULLUP Pull-up resistance
30
−
50
1.0
125
−
RfXIN
Feedback resistance XIN
fRING-S
VRAM
Low-speed on-chip oscillator frequency
RAM hold voltage
40
2.0
250
−
During stop mode
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN) = 20 MHz, unless otherwise specified.
Rev.1.40 Apr 14, 2006 Page 29 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.13
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85
°
C, unless otherwise specified.)
Standard
Unit
Symbol
Parameter
Power supply current High-speed
Condition
Min.
Typ.
9
Max.
15
ICC
XIN = 20 MHz (square wave)
−
mA
mA
mA
mA
mA
mA
mA
mA
µA
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS,
comparator is
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
−
−
−
−
−
−
−
8
5
14
−
stopped
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
Medium-
XIN = 20 MHz (square wave)
4
−
speed mode High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
3
−
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
2
−
High-speed
on-chip
oscillator
mode
Main clock off
4
8
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
Main clock off
1.5
110
−
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed
on-chip
oscillator
mode
Main clock off
300
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
Wait mode
Wait mode
Stop mode
Main clock off
−
−
−
40
38
80
76
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = 0
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
0.8
3.0
Peripheral clock off
VCA27 = VCA26 = 0
Rev.1.40 Apr 14, 2006 Page 30 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Ta = 25 °C) [VCC = 5 V]
Table 5.14
XIN Input
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(XIN)
XIN input cycle time
XIN input “H” width
XIN input “L” width
50
25
25
−
−
−
ns
ns
ns
tWH(XIN)
tWL(XIN)
VCC = 5 V
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.4
XIN Input Timing Diagram when VCC = 5 V
Table 5.15
CNTR0 Input, CNTR1 Input, INT1 Input
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(CNTR0)
CNTR0 input cycle time
CNTR0 input “H” width
CNTR0 input “L” width
−
−
−
ns
ns
ns
tWH(CNTR0)
tWL(CNTR0)
40
VCC = 5 V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
Figure 5.5
CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 5 V
TCIN Input, INT3 Input
Table 5.16
Standard
Symbol
Parameter
Unit
Min.
Max.
400(1)
200(2)
200(2)
tc(TCIN)
TCIN input cycle time
TCIN input “H” width
TCIN input “L” width
−
−
−
ns
ns
ns
tWH(TCIN)
tWL(TCIN)
NOTES:
1. When using timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above.
2. When using timer C input capture mode, adjust the pulse width to (1/timer C count source frequency x 1.5) or above.
VCC = 5 V
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
Figure 5.6
TCIN Input, INT3 Input Timing Diagram when VCC = 5 V
Rev.1.40 Apr 14, 2006 Page 31 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.17
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
200
100
100
−
−
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
50
−
0
RXDi input setup time
RXDi input hold time
50
90
−
−
i = 0 or 1
VCC = 5 V
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
RxDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.7
Serial Interface Timing Diagram when VCC = 5 V
Table 5.18
External Interrupt INT0 Input
Standard
Symbol
Parameter
Unit
Min.
Max.
250(1)
250(2)
tW(INH)
tW(INL)
−
−
ns
ns
INT0 input “H” width
INT0 input “L” width
NOTES:
1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INT0 input
tW(INH)
Figure 5.8
External Interrupt INT0 Input Timing Diagram when VCC = 5 V
Rev.1.40 Apr 14, 2006 Page 32 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.19
Electrical Characteristics (3) [VCC = 3V]
Standard
Unit
Symbol
Parameter
Output “H” voltage Except XOUT
Condition
Min.
Typ.
−
Max.
VCC
VCC
VOH
IOH = -1 mA
VCC − 0.5
V
V
XOUT
Drive capacity
HIGH
IOH = -0.1 mA VCC − 0.5
−
Drive capacity
LOW
IOH = -50 µA
VCC − 0.5
−
−
−
−
−
−
−
VCC
0.5
0.5
0.5
0.5
0.5
0.8
V
V
V
V
V
V
V
VOL
Output “L” voltage
Except P1_0 to
P1_3, XOUT
IOL = 1mA
−
−
P1_0 to P1_3
Drive capacity
HIGH
IOL = 2 mA
IOL = 1 mA
IOL = 0.1 mA
IOL = 50 µA
Drive capacity
LOW
−
XOUT
Drive capacity
HIGH
−
Drive capacity
LOW
−
VT+-VT-
Hysteresis
0.2
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, CNTR0,
CNTR1, TCIN,
RXD0
0.2
−
1.8
V
RESET
IIH
IIL
Input “H” current
Input “L” current
VI = 3 V
VI = 0 V
VI = 0 V
−
−
−
−
4.0
-4.0
500
−
µA
µA
kΩ
MΩ
kHz
V
RPULLUP Pull-up resistance
66
−
160
3.0
125
−
RfXIN
Feedback resistance XIN
fRING-S
VRAM
Low-speed on-chip oscillator frequency
RAM hold voltage
40
2.0
250
−
During stop mode
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN) = 10 MHz, unless otherwise specified.
Rev.1.40 Apr 14, 2006 Page 33 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.20
Electrical Characteristics (4) [Vcc = 3V] (Topr = -40 to 85
°C, unless otherwise specified.)
Standard
Unit
Symbol
Parameter
Power supply current High-speed
Condition
Min.
Typ.
8
Max.
13
ICC
XIN = 20 MHz (square wave)
−
mA
mA
mA
mA
mA
mA
mA
mA
µA
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS,
comparator is
mode
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
−
−
−
−
−
−
−
7
5
12
−
stopped
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
Medium-
XIN = 20 MHz (square wave)
3
−
speed mode High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
2.5
1.6
3.5
1.5
100
−
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
High-speed
on-chip
oscillator
mode
Main clock off
7.5
−
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed
on-chip
oscillator
mode
Main clock off
280
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
Wait mode
Wait mode
Stop mode
Main clock off
−
−
−
37
35
74
70
µA
µA
µA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = 0
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
0.7
3.0
Peripheral clock off
VCA27 = VCA26 = 0
Rev.1.40 Apr 14, 2006 Page 34 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Ta = 25 °C) [VCC = 3 V]
Table 5.21
XIN Input
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(XIN)
XIN input cycle time
XIN input “H” width
XIN input “L” width
100
40
−
−
−
ns
ns
ns
tWH(XIN)
tWL(XIN)
40
VCC = 3 V
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.9
XIN Input Timing Diagram when VCC = 3 V
Table 5.22
CNTR0 Input, CNTR1 Input, INT1 Input
Standard
Symbol
Parameter
Unit
Min.
300
120
120
Max.
tc(CNTR0)
CNTR0 input cycle time
CNTR0 input “H” width
CNTR0 input “L” width
−
−
−
ns
ns
ns
tWH(CNTR0)
tWL(CNTR0)
VCC = 3 V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
Figure 5.10
CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 3 V
TCIN Input, INT3 Input
Table 5.23
Standard
Symbol
Parameter
Unit
Min.
1,200(1)
600(2)
600(2)
Max.
tc(TCIN)
TCIN input cycle time
TCIN input “H” width
TCIN input “L” width
−
−
−
ns
ns
ns
tWH(TCIN)
tWL(TCIN)
NOTES:
1. When using the timer C input capture mode, adjust the cycle time to (1/timer C count source frequency × 3) or above.
2. When using the timer C input capture mode, adjust the width to (1/timer C count source frequency × 1.5) or above.
VCC = 3 V
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
Figure 5.11
TCIN Input, INT3 Input Timing Diagram when VCC = 3 V
Rev.1.40 Apr 14, 2006 Page 35 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Table 5.24
Serial Interface
Standard
Unit
Symbol
Parameter
Min.
Max.
tc(CK)
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
300
150
150
−
−
−
ns
ns
ns
ns
ns
ns
ns
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
−
80
−
0
RXDi input setup time
RXDi input hold time
70
90
−
−
i = 0 or 1
VCC = 3 V
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
RxDi
td(C-Q)
tsu(D-C)
th(C-D)
Figure 5.12
Serial Interface Timing Diagram when VCC = 3 V
Table 5.25
External Interrupt INT0 Input
Standard
Symbol
Parameter
Unit
Min.
Max.
380(1)
380(2)
tW(INH)
tW(INL)
−
ns
ns
INT0 input “H” width
INT0 input “L” width
−
NOTES:
1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
Figure 5.13
External Interrupt INT0 Input Timing Diagram when VCC = 3 V
Rev.1.40 Apr 14, 2006 Page 36 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
PackageDimensions
Package Dimensions
JEITA Package Code
RENESAS Code
PLSP0020JB-A
Previous Code
20P2F-A
MASS[Typ.]
0.1g
P-LSSOP20-4.4x6.5-0.65
11
20
NOTE)
F
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
10
Index mark
c
A2
A1
Dimension in Millimeters
Reference
Symbol
*2
D
Min Nom Max
D
E
6.4 6.5 6.6
4.3 4.4 4.5
1.15
A2
A
1.45
0.1 0.2
0
A1
bp
c
*3
bp
e
0.17 0.22 0.32
Detail F
y
0.2
10°
0.13 0.15
0°
HE
e
6.2 6.4 6.6
0.53 0.65 0.77
0.10
y
L
0.3 0.5 0.7
JEITA Package Code
P-SDIP20-6.3x19-1.78
RENESAS Code
PRDP0020BA-A
Previous Code
20P4B
MASS[Typ.]
1.0g
20
11
1
10
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
e1
D
7.32 7.62 7.92
18.8 19.0 19.2
6.15 6.3 6.45
4.5
E
A
A1
A2
bp
b3
c
0.51
*3
b3
bp
e
3.3
SEATING PLANE
0.38 0.48 0.58
0.9 1.0 1.3
0.22 0.27 0.34
0°
15°
e
L
1.528 1.778 2.028
3.0
Rev.1.40 Apr 14, 2006 Page 37 of 38
REJ03B0124-0140
R8C/18 Group, R8C/19 Group
PackageDimensions
JEITA Package Code
P-HWQFN28-5x5-0.50
RENESAS Code
Previous Code
MASS[Typ.]
0.05g
PWQN0028KA-B
28PJW-B
D
15
21
21
15
22
14
14
22
D2
Lp
28
8
28
8
7
1
7
1
e
bp
x
Dimension in Millimeters
Reference
F
Symbol
Min
4.9
4.9
Nom
5.0
Max
5.1
D
E
5.0
5.1
A2
A
0.75
0.8
A1
bp
e
0
0
0.05
0.25
y
0.15
0.2
0.5
0.6
Lp
x
0.5
0.7
0.05
0.05
2.0
Detail F
y
D2
E1
2.0
Rev.1.40 Apr 14, 2006 Page 38 of 38
REJ03B0124-0140
REVISION HISTORY
R8C/18 Group, R8C/19 Group Datasheet
Description
Summary
Rev.
Date
Page
0.10
0.20
0.21
Nov 15, 2004
Jan 11, 2005
Apr 04, 2005
−
First Edition issued
5, 6 Tables 1.3 and 1.4: The date updated
2, 3 Tables 1.1 and 1.2: Partly revised
4
Figure 1.1: Partly revised
5, 6 Tables 1.3 and 1.4: Partly revised
5, 6 Figure 1.2 and 1.3: Partly revised
7, 8 Figure 1.4 and 1.5: Partly revised
10
16
17
18
20
Table 1.6: Partly revised
Table 4.1: Partly revised
Table 4.2: Partly revised
Table 4.3: Partly revised
Package Dimensions are revised
1.00
May 27, 2005
5, 6 Tables 1.3 and 1.4: Partly revised
9
Table 1.5: Partly revised
Table 5.9: Revised
25
26
28
32
26
3
Table 5.10: Partly revised
Table 5.13: Partly revised
Table 5.20: Partly revised
Table 5.10: Partly revised
1.10
1.20
Jun 09, 2005
Nov 01, 2005
Table 1.2 Performance Outline of the R8C/19 Group;
Flash Memory: (Data area) → (Data flash)
(Program area) → (Program ROM) revised
4
6
9
Figure 1.1 Block Diagram;
“Peripheral Function” added,
“System Clock Generation” → “System Clock Generator” revised
Table 1.4 Product Information of R8C/19 Group;
ROM capacity: “Program area” → “Program ROM”,
“Data area” → “Data flash” revised
Table 1.5 Pin Description;
Power Supply Input: “VCC/AVCC” → “VCC”,
“VSS/AVSS” → “VSS” revised
Analog Power Supply Input: added
11
13
15
Figure 2.1 CPU Register;
“Reserved Area” → “Reserved Bit” revised
2.8.10 Reserved Area;
“Reserved Area” → “Reserved Bit” revised
3.2 R8C/19 Group, Figure 3.2 Memory Map of R8C/19 Group;
“Data area” → “Data flash”,
“Program area” → “Program ROM” revised
A - 1
REVISION HISTORY
R8C/18 Group, R8C/19 Group Datasheet
Description
Summary
Rev.
1.20
Date
Page
Nov 01, 2005
16
Table 4.1 SFR Information(1);
0009h: “XXXXXX00b” → “00h”
000Ah: “00XXX000b” → “00h”
001Eh: “XXXXX000b” → “00h” revised
18
Table 4.3 SFR Information(3);
0085h:
0086h:
0087h:
008Ch:
008Dh:
“Prescaler Z” → “Prescaler Z Register”
“Timer Z Secondary” → “Timer Z Secondary Register”
“Timer Z Primary” → “Timer Z Primary Register”
“Prescaler X” → “Prescaler X Register”
“Timer X” → “Timer X Register”
0090h, 0091h:“Timer C” → “Timer C Register” revised
22
23
25
26
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics;
NOTES 3 and 5 revised, NOTE8 deleted
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical
Characteristics; NOTES 1 and 3 revised
Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage
Monitor 1 Reset); NOTE 2 revised
Table 5.10 High-speed On-Chip Oscillator Circuit Electrical
Characteristics;
“High-Speed On-Chip Oscillator ...” →
“High-Speed On-Chip Oscillator Frequency ...” revised
NOTE 2, 3 added
28
32
−
Table 5.13 Electrical Characteristics (2) [Vcc = 5V];
NOTE 1 deleted
Table 5.20 Electrical Characteristics (4) [Vcc = 3V];
NOTE 1 deleted
1.30
Dec 16, 2005
Products of PWQN0028KA-B package included
5, 6 Table 1.3, Table 1.4 revised
24
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics;
Ta → Ambient temperature
25
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical
Characteristics; Ta → Ambient temperature
30, 34 Table 5.13, Table 5.20; The title revised, Condition of Stop Mode added
32, 36 Table 5.17, Table 5.24; td(C-Q) and tsu(D-C) revised
37, 38 Package Dimensions revised
1.40
Apr 14, 2006
2, 3 Table 1.1, Table 1.2;
Interrupts: Internal 8 → 10 sources,
5, 6 Table 1.3, Table 1.4; Type No. added, deleted
16, 17 Figure 3.1, Figure 3.2; Part Number added, deleted
24, 25 Table 5.4, Table 5.5;
Conditions: VCC = 5.0 V at Topr = 25 °C deleted
A - 2
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