R8C2E [RENESAS]

MCU; MCU
R8C2E
型号: R8C2E
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

MCU
MCU

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REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
Hardware Manual  
16  
RENESAS MCU  
R8C FAMILY / R8C/2x SERIES  
All information contained in these materials, including products and product specifications,  
represents information on the product at the time of publication and is subject to change by  
Renesas Technology Corp. without notice. Please review the latest information published  
by Renesas Technology Corp. through various means, including the Renesas Technology  
Corp. website (http://www.renesas.com).  
Rev.1.00  
Revision Date: Dec 14, 2007  
www.renesas.com  
Notes regarding these materials  
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate  
Renesas products for their use. Renesas neither makes warranties or representations with respect to the  
accuracy or completeness of the information contained in this document nor grants any license to any  
intellectual property rights or any other rights of Renesas or any third party with respect to the information in  
this document.  
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising  
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,  
programs, algorithms, and application circuit examples.  
3. You should not use the products or the technology described in this document for the purpose of military  
applications such as the development of weapons of mass destruction or for the purpose of any other military  
use. When exporting the products or technology described herein, you should follow the applicable export  
control laws and regulations, and procedures required by such laws and regulations.  
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and  
application circuit examples, is current as of the date this document is issued. Such information, however, is  
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this  
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular  
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed  
through our website. (http://www.renesas.com )  
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas  
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information  
included in this document.  
6. When using or otherwise relying on the information in this document, you should evaluate the information in  
light of the total system before deciding about the applicability of such information to the intended application.  
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any  
particular application and specifically disclaims any liability arising out of the application and use of the  
information in this document or Renesas products.  
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas  
products are not designed, manufactured or tested for applications or otherwise in systems the failure or  
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require  
especially high quality and reliability such as safety systems, or equipment or systems for transportation and  
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication  
transmission. If you are considering the use of our products for such purposes, please contact a Renesas  
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.  
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:  
(1) artificial life support devices or systems  
(2) surgical implantations  
(3) healthcare intervention (e.g., excision, administration of medication, etc.)  
(4) any other purposes that pose a direct threat to human life  
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who  
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas  
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all  
damages arising out of such applications.  
9. You should use the products described herein within the range specified by Renesas, especially with respect  
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation  
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or  
damages arising out of the use of Renesas products beyond such specified ranges.  
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific  
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use  
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and  
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for  
hardware and software including but not limited to redundancy, fire control and malfunction prevention,  
appropriate treatment for aging degradation or any other applicable measures. Among others, since the  
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or  
system manufactured by you.  
11. In case Renesas products listed in this document are detached from the products to which the Renesas  
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very  
high. You should implement safety measures so that Renesas products may not be easily detached from your  
products. Renesas shall have no liability for damages arising out of such detachment.  
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written  
approval from Renesas.  
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this  
document, Renesas semiconductor products, or if you have any other inquiries.  
General Precautions in the Handling of MPU/MCU Products  
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes  
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under  
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each  
other, the description in the body of the manual takes precedence.  
1. Handling of Unused Pins  
Handle unused pins in accord with the directions given under Handling of Unused Pins in the  
manual.  
The input pins of CMOS products are generally in the high-impedance state. In operation  
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the  
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur  
due to the false recognition of the pin state as an input signal become possible. Unused  
pins should be handled as described under Handling of Unused Pins in the manual.  
2. Processing at Power-on  
The state of the product is undefined at the moment when power is supplied.  
The states of internal circuits in the LSI are indeterminate and the states of register  
settings and pins are undefined at the moment when power is supplied.  
In a finished product where the reset signal is applied to the external reset pin, the states  
of pins are not guaranteed from the moment when power is supplied until the reset  
process is completed.  
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset  
function are not guaranteed from the moment when power is supplied until the power  
reaches the level at which resetting has been specified.  
3. Prohibition of Access to Reserved Addresses  
Access to reserved addresses is prohibited.  
The reserved addresses are provided for the possible future expansion of functions. Do  
not access these addresses; the correct operation of LSI is not guaranteed if they are  
accessed.  
4. Clock Signals  
After applying a reset, only release the reset line after the operating clock signal has become  
stable. When switching the clock signal during program execution, wait until the target clock  
signal has stabilized.  
When the clock signal is generated with an external resonator (or from an external  
oscillator) during a reset, ensure that the reset line is only released after full stabilization of  
the clock signal. Moreover, when switching to a clock signal produced with an external  
resonator (or by an external oscillator) while program execution is in progress, wait until  
the target clock signal is stable.  
5. Differences between Products  
Before changing from one product to another, i.e. to one with a different part number, confirm  
that the change will not lead to problems.  
The characteristics of MPU/MCU in the same group but having different part numbers may  
differ because of the differences in internal memory capacity and layout pattern. When  
changing to products of different part numbers, implement a system-evaluation test for  
each of the products.  
How to Use This Manual  
1. Purpose and Target Readers  
This manual is designed to provide the user with an understanding of the hardware functions and electrical  
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic  
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.  
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral  
functions, and electrical characteristics; and usage notes.  
Particular attention should be paid to the precautionary notes when using the manual. These notes occur  
within the body of the text, at the end of each section, and in the Usage Notes section.  
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer  
to the text of the manual for details.  
The following documents apply to the R8C/2E Group, R8C/2F Group. Make sure to refer to the latest versions of  
these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web  
site.  
Document Type  
Datasheet  
Description  
Document Title  
Document No.  
REJ03B0222  
Hardware overview and electrical characteristics R8C/2E, R8C/2F  
Group Datasheet  
Hardware manual Hardware specifications (pin assignments,  
memory maps, peripheral function  
R8C/2E Group,  
R8C/2F Group  
Hardware Manual  
This hardware  
manual  
specifications, electrical characteristics, timing  
charts) and operation description  
Note: Refer to the application notes for details on  
using peripheral functions.  
Software manual Description of CPU instruction set  
R8C/Tiny Series  
Software Manual  
REJ09B0001  
Application note Information on using peripheral functions and  
application examples  
Available from Renesas  
Technology Web site.  
Sample programs  
Information on writing programs in assembly  
language and C  
Renesas  
Product specifications, updates on documents,  
technical update etc.  
2. Notation of Numbers and Symbols  
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described  
below.  
(1) Register Names, Bit Names, and Pin Names  
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word  
“register,” “bit,” or “pin” to distinguish the three categories.  
Examples the PM03 bit in the PM0 register  
P3_5 pin, VCC pin  
(2) Notation of Numbers  
The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the  
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing  
is appended to numeric values given in decimal format.  
Examples Binary: 11b  
Hexadecimal: EFA0h  
Decimal: 1234  
3. Register Notation  
The symbols and terms used in register diagrams are described below.  
*1  
XXX Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
XXX  
Address  
XXX  
After Reset  
00h  
0
RW  
RW  
Bit Symbol  
XXX0  
Bit Name  
XXX bits  
Function  
*2  
b1 b0  
1 0: XXX  
0 1: XXX  
1 0: Do not set.  
1 1: XXX  
XXX1  
(b2)  
RW  
Nothing is assigned. If necessary, set to 0.  
When read, the content is undefined.  
*3  
Reserved bits  
XXX bits  
Set to 0.  
RW  
(b3)  
XXX4  
XXX5  
*4  
Function varies according to the operating  
mode.  
RW  
WO  
RW  
RO  
XXX6  
XXX7  
0: XXX  
1: XXX  
XXX bit  
*1  
*2  
Blank: Set to 0 or 1 according to the application.  
0: Set to 0.  
1: Set to 1.  
X: Nothing is assigned.  
RW: Read and write.  
RO: Read only.  
WO: Write only.  
: Nothing is assigned.  
*3  
*4  
• Reserved bit  
Reserved bit. Set to specified value.  
• Nothing is assigned  
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.  
• Do not set to a value  
Operation is not guaranteed when a value is set.  
• Function varies according to the operating mode.  
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information  
on the individual modes.  
4. List of Abbreviations and Acronyms  
Abbreviation  
Full Form  
ACIA  
bps  
Asynchronous Communication Interface Adapter  
bits per second  
CRC  
DMA  
DMAC  
GSM  
Hi-Z  
Cyclic Redundancy Check  
Direct Memory Access  
Direct Memory Access Controller  
Global System for Mobile Communications  
High Impedance  
IEBus  
I/O  
Inter Equipment Bus  
Input / Output  
IrDA  
LSB  
Infrared Data Association  
Least Significant Bit  
MSB  
NC  
Most Significant Bit  
Non-Connect  
PLL  
Phase Locked Loop  
PWM  
SFR  
SIM  
Pulse Width Modulation  
Special Function Registers  
Subscriber Identity Module  
Universal Asynchronous Receiver / Transmitter  
Voltage Controlled Oscillator  
UART  
VCO  
All trademarks and registered trademarks are the property of their respective owners.  
Table of Contents  
SFR Page Reference ........................................................................................................................... B - 1  
1.  
Overview ......................................................................................................................................... 1  
1.1  
1.1.1  
1.1.2  
Features ..................................................................................................................................................... 1  
Applications .......................................................................................................................................... 1  
Specifications ........................................................................................................................................ 2  
Product List ............................................................................................................................................... 6  
Block Diagram ......................................................................................................................................... 8  
Pin Assignment .......................................................................................................................................... 9  
Pin Functions ........................................................................................................................................... 11  
1.2  
1.3  
1.4  
1.5  
2.  
Central Processing Unit (CPU) ..................................................................................................... 12  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
Data Registers (R0, R1, R2, and R3) ...................................................................................................... 13  
Address Registers (A0 and A1) ............................................................................................................... 13  
Frame Base Register (FB) ....................................................................................................................... 13  
Interrupt Table Register (INTB) .............................................................................................................. 13  
Program Counter (PC) ............................................................................................................................. 13  
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. 13  
Static Base Register (SB) ........................................................................................................................ 13  
Flag Register (FLG) ................................................................................................................................ 13  
2.8.1  
2.8.2  
Carry Flag (C) ..................................................................................................................................... 13  
Debug Flag (D) ................................................................................................................................... 13  
Zero Flag (Z) ....................................................................................................................................... 13  
Sign Flag (S) ....................................................................................................................................... 13  
Register Bank Select Flag (B) ............................................................................................................ 13  
Overflow Flag (O) .............................................................................................................................. 13  
Interrupt Enable Flag (I) ..................................................................................................................... 14  
Stack Pointer Select Flag (U) .............................................................................................................. 14  
Processor Interrupt Priority Level (IPL) ............................................................................................. 14  
2.8.3  
2.8.4  
2.8.5  
2.8.6  
2.8.7  
2.8.8  
2.8.9  
2.8.10 Reserved Bit ........................................................................................................................................ 14  
3.  
Memory ......................................................................................................................................... 15  
3.1  
R8C/2E Group ......................................................................................................................................... 15  
R8C/2F Group ......................................................................................................................................... 16  
3.2  
4.  
5.  
Special Function Registers (SFRs) ............................................................................................... 17  
Resets ........................................................................................................................................... 24  
5.1  
Hardware Reset ....................................................................................................................................... 27  
5.1.1  
5.1.2  
When Power Supply is Stable ............................................................................................................. 27  
Power On ............................................................................................................................................ 27  
Power-On Reset Function ....................................................................................................................... 29  
Voltage Monitor 1 Reset ......................................................................................................................... 30  
Voltage Monitor 2 Reset ......................................................................................................................... 30  
Watchdog Timer Reset ............................................................................................................................ 30  
Software Reset ......................................................................................................................................... 30  
5.2  
5.3  
5.4  
5.5  
5.6  
6.  
Voltage Detection Circuit .............................................................................................................. 31  
6.1  
VCC Input Voltage .................................................................................................................................. 36  
A - 1  
6.1.1  
6.1.2  
Monitoring Vdet1 ............................................................................................................................... 36  
Monitoring Vdet2 ............................................................................................................................... 36  
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset ..................................................................... 37  
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 39  
6.2  
6.3  
7.  
Programmable I/O Ports ............................................................................................................... 41  
7.1  
7.2  
7.3  
7.4  
7.5  
Functions of Programmable I/O Ports ..................................................................................................... 41  
Effect on Peripheral Functions ................................................................................................................ 42  
Pins Other than Programmable I/O Ports ................................................................................................ 42  
Port Setting .............................................................................................................................................. 52  
Unassigned Pin Handling ........................................................................................................................ 62  
8.  
9.  
Processor Mode ............................................................................................................................ 63  
8.1  
Processor Modes ...................................................................................................................................... 63  
Bus ................................................................................................................................................ 64  
10. Clock Generation Circuit ............................................................................................................... 65  
10.1  
10.2  
XIN Clock ............................................................................................................................................... 73  
On-Chip Oscillator Clocks ...................................................................................................................... 74  
10.2.1 Low-Speed On-Chip Oscillator Clock ................................................................................................ 74  
10.2.2 High-Speed On-Chip Oscillator Clock ............................................................................................... 74  
10.3  
CPU Clock and Peripheral Function Clock ............................................................................................. 75  
10.3.1 System Clock ...................................................................................................................................... 75  
10.3.2 CPU Clock .......................................................................................................................................... 75  
10.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. 75  
10.3.4 fOCO ................................................................................................................................................... 75  
10.3.5 fOCO40M ........................................................................................................................................... 75  
10.3.6 fOCO-F ............................................................................................................................................... 75  
10.3.7 fOCO-S ............................................................................................................................................... 75  
10.3.8 fOCO128 ............................................................................................................................................. 75  
10.4  
Power Control .......................................................................................................................................... 76  
10.4.1 Standard Operating Mode ................................................................................................................... 76  
10.4.2 Wait Mode .......................................................................................................................................... 78  
10.4.3 Stop Mode ........................................................................................................................................... 82  
10.5 Oscillation Stop Detection Function ....................................................................................................... 85  
10.5.1 How to Use Oscillation Stop Detection Function ............................................................................... 85  
10.6  
Notes on Clock Generation Circuit ......................................................................................................... 88  
10.6.1 Stop Mode ........................................................................................................................................... 88  
10.6.2 Wait Mode .......................................................................................................................................... 88  
10.6.3 Oscillation Stop Detection Function ................................................................................................... 88  
10.6.4 Oscillation Circuit Constants .............................................................................................................. 88  
11.  
Protection ...................................................................................................................................... 89  
12. Interrupts ....................................................................................................................................... 90  
12.1 Interrupt Overview .................................................................................................................................. 90  
12.1.1 Types of Interrupts .............................................................................................................................. 90  
12.1.2 Software Interrupts ............................................................................................................................. 91  
A - 2  
12.1.3 Special Interrupts ................................................................................................................................ 92  
12.1.4 Peripheral Function Interrupt .............................................................................................................. 92  
12.1.5 Interrupts and Interrupt Vectors .......................................................................................................... 93  
12.1.6 Interrupt Control ................................................................................................................................. 95  
12.2  
INT Interrupt ......................................................................................................................................... 104  
12.2.1 INTi Interrupt (i = 0, 1, 3) ................................................................................................................. 104  
12.2.2 INTi Input Filter (i = 0, 1, 3) ............................................................................................................. 106  
12.3  
Key Input Interrupt ................................................................................................................................ 107  
Address Match Interrupt ........................................................................................................................ 109  
Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt ........................................... 111  
Notes on Interrupts ................................................................................................................................ 112  
12.4  
12.5  
12.6  
12.6.1 Reading Address 00000h .................................................................................................................. 112  
12.6.2 SP Setting .......................................................................................................................................... 112  
12.6.3 External Interrupt and Key Input Interrupt ....................................................................................... 112  
12.6.4 Changing Interrupt Sources .............................................................................................................. 113  
12.6.5 Changing Interrupt Control Register Contents ................................................................................. 114  
13. Watchdog Timer ........................................................................................................................... 115  
13.1  
13.2  
Count Source Protection Mode Disabled .............................................................................................. 118  
Count Source Protection Mode Enabled ............................................................................................... 119  
14. Timers ......................................................................................................................................... 120  
14.1 Timer RA ............................................................................................................................................... 122  
14.1.1 Timer Mode ...................................................................................................................................... 125  
14.1.2 Pulse Output Mode ........................................................................................................................... 127  
14.1.3 Event Counter Mode ......................................................................................................................... 129  
14.1.4 Pulse Width Measurement Mode ...................................................................................................... 131  
14.1.5 Pulse Period Measurement Mode ..................................................................................................... 134  
14.1.6 Notes on Timer RA ........................................................................................................................... 137  
14.2  
Timer RB ............................................................................................................................................... 138  
14.2.1 Timer Mode ...................................................................................................................................... 142  
14.2.2 Programmable Waveform Generation Mode .................................................................................... 145  
14.2.3 Programmable One-shot Generation Mode ...................................................................................... 148  
14.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 152  
14.2.5 Notes on Timer RB ........................................................................................................................... 155  
14.3  
Timer RC ............................................................................................................................................... 159  
14.3.1 Overview ........................................................................................................................................... 159  
14.3.2 Registers Associated with Timer RC ................................................................................................ 161  
14.3.3 Common Items for Multiple Modes ................................................................................................. 171  
14.3.4 Timer Mode (Input Capture Function) ............................................................................................. 177  
14.3.5 Timer Mode (Output Compare Function) ......................................................................................... 182  
14.3.6 PWM Mode ....................................................................................................................................... 188  
14.3.7 PWM2 Mode ..................................................................................................................................... 193  
14.3.8 Timer RC Interrupt ........................................................................................................................... 199  
14.3.9 Notes on Timer RC ........................................................................................................................... 200  
14.4  
Timer RE ............................................................................................................................................... 201  
14.4.1 Output Compare Mode ..................................................................................................................... 202  
14.4.2 Notes on Timer RE ........................................................................................................................... 206  
A - 3  
15. Serial Interface ............................................................................................................................ 207  
15.1 Clock Synchronous Serial I/O Mode ..................................................................................................... 213  
15.1.1 Polarity Select Function .................................................................................................................... 216  
15.1.2 LSB First/MSB First Select Function ............................................................................................... 216  
15.1.3 Continuous Receive Mode ................................................................................................................ 217  
15.2 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 218  
15.2.1 Bit Rate ............................................................................................................................................. 222  
15.3  
Notes on Serial Interface ....................................................................................................................... 223  
16. Hardware LIN .............................................................................................................................. 224  
16.1  
16.2  
16.3  
16.4  
Features ................................................................................................................................................. 224  
Input/Output Pins .................................................................................................................................. 225  
Register Configuration .......................................................................................................................... 226  
Functional Description .......................................................................................................................... 228  
16.4.1 Master Mode ..................................................................................................................................... 228  
16.4.2 Slave Mode ....................................................................................................................................... 231  
16.4.3 Bus Collision Detection Function ..................................................................................................... 235  
16.4.4 Hardware LIN End Processing ......................................................................................................... 236  
16.5  
16.6  
Interrupt Requests .................................................................................................................................. 237  
Notes on Hardware LIN ........................................................................................................................ 238  
17. A/D Converter ............................................................................................................................. 239  
17.1  
17.2  
17.3  
17.4  
17.5  
17.6  
17.7  
One-Shot Mode ..................................................................................................................................... 243  
Repeat Mode .......................................................................................................................................... 246  
Sample and Hold ................................................................................................................................... 249  
A/D Conversion Cycles ......................................................................................................................... 249  
Internal Equivalent Circuit of Analog Input .......................................................................................... 250  
Output Impedance of Sensor under A/D Conversion ............................................................................ 251  
Notes on A/D Converter ........................................................................................................................ 252  
18. D/A Converter ............................................................................................................................. 253  
19. Comparator ................................................................................................................................. 256  
19.1  
19.2  
19.3  
Overview ............................................................................................................................................... 256  
Register Functions ................................................................................................................................. 258  
Functional Description .......................................................................................................................... 260  
19.3.1 Comparison Result Output ................................................................................................................ 261  
19.3.2 Digital Filter ...................................................................................................................................... 262  
19.4  
Comparator 0 Interrupt and Comparator 1 Interrupt ............................................................................. 263  
20. Flash Memory Version ................................................................................................................ 264  
20.1  
20.2  
20.3  
Overview ............................................................................................................................................... 264  
Memory Map ......................................................................................................................................... 265  
Functions to Prevent Rewriting of Flash Memory ................................................................................ 267  
20.3.1 ID Code Check Function .................................................................................................................. 267  
20.3.2 ROM Code Protect Function ............................................................................................................ 268  
20.4  
CPU Rewrite Mode ............................................................................................................................... 269  
20.4.1 EW0 Mode ........................................................................................................................................ 270  
20.4.2 EW1 Mode ........................................................................................................................................ 270  
A - 4  
20.4.3 Software Commands ......................................................................................................................... 279  
20.4.4 Status Registers ................................................................................................................................. 284  
20.4.5 Full Status Check .............................................................................................................................. 285  
20.5  
20.6  
20.7  
Standard Serial I/O Mode ...................................................................................................................... 287  
20.5.1 ID Code Check Function .................................................................................................................. 287  
Parallel I/O Mode .................................................................................................................................. 290  
20.6.1 ROM Code Protect Function ............................................................................................................ 290  
Notes on Flash Memory Version ........................................................................................................... 291  
20.7.1 CPU Rewrite Mode ........................................................................................................................... 291  
21. Electrical Characteristics ............................................................................................................ 294  
22. Usage Notes ............................................................................................................................... 309  
22.1  
Notes on Clock Generation Circuit ....................................................................................................... 309  
22.1.1 Stop Mode ......................................................................................................................................... 309  
22.1.2 Wait Mode ........................................................................................................................................ 309  
22.1.3 Oscillation Stop Detection Function ................................................................................................. 309  
22.1.4 Oscillation Circuit Constants ............................................................................................................ 309  
22.2  
Notes on Interrupts ................................................................................................................................ 310  
22.2.1 Reading Address 00000h .................................................................................................................. 310  
22.2.2 SP Setting .......................................................................................................................................... 310  
22.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 310  
22.2.4 Changing Interrupt Sources .............................................................................................................. 311  
22.2.5 Changing Interrupt Control Register Contents ................................................................................. 312  
22.3  
Notes on Timers .................................................................................................................................... 313  
22.3.1 Notes on Timer RA ........................................................................................................................... 313  
22.3.2 Notes on Timer RB ........................................................................................................................... 314  
22.3.3 Notes on Timer RC ........................................................................................................................... 318  
22.3.4 Notes on Timer RE ........................................................................................................................... 319  
22.4  
Notes on Serial Interface ....................................................................................................................... 320  
Notes on Hardware LIN ........................................................................................................................ 321  
Notes on A/D Converter ........................................................................................................................ 322  
Notes on Flash Memory Version ........................................................................................................... 323  
22.5  
22.6  
22.7  
22.7.1 CPU Rewrite Mode ........................................................................................................................... 323  
22.8  
Notes on Noise ...................................................................................................................................... 326  
22.8.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and  
Latch-up ............................................................................................................................................ 326  
22.8.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 326  
23. Notes for On-Chip Debugger ...................................................................................................... 327  
Appendix 1. Package Dimensions ........................................................................................................ 328  
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 329  
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 330  
Index ..................................................................................................................................................... 331  
A - 5  
SFR Page Reference  
Address  
0000h  
0001h  
0002h  
0003h  
Register  
Symbol  
Page  
Address  
0040h  
0041h  
0042h  
0043h  
0044h  
0045h  
0046h  
Register  
Symbol  
Page  
0004h Processor Mode Register 0  
PM0  
63  
63  
67  
68  
0005h Processor Mode Register 1  
PM1  
CM0  
CM1  
0006h System Clock Control Register 0  
0007h System Clock Control Register 1  
0047h Timer RC Interrupt Control Register  
TRCIC  
96  
95  
0008h  
0048h  
0009h  
0049h  
000Ah Protect Register  
PRCR  
89  
004Ah Timer RE Interrupt Control Register  
TREIC  
KUPIC  
000Bh  
004Bh  
000Ch Oscillation Stop Detection Register  
OCD  
69  
004Ch  
000Dh Watchdog Timer Reset Register  
WDTR  
WDTS  
WDC  
116  
116  
116  
110  
004Dh Key Input Interrupt Control Register  
95  
95  
000Eh Watchdog Timer Start Register  
004Eh A/D Conversion Interrupt Control Register ADIC  
000Fh Watchdog Timer Control Register  
004Fh  
0010h Address Match Interrupt Register 0  
RMAD0  
0050h  
0011h  
0051h UART0 Transmit Interrupt Control Register S0TIC  
95  
95  
0012h  
0052h UART0 Receive Interrupt Control Register S0RIC  
0013h Address Match Interrupt Enable Register  
AIER  
110  
110  
0053h  
0054h  
0055h  
0014h Address Match Interrupt Register 1  
RMAD1  
0015h  
0016h  
0056h Timer RA Interrupt Control Register  
TRAIC  
95  
0017h  
0057h  
0018h  
0058h Timer RB Interrupt Control Register  
TRBIC  
INT1IC  
INT3IC  
CM0IC  
CM1IC  
INT0IC  
95  
97  
97  
96  
96  
97  
0019h  
0059h INT1 Interrupt Control Register  
001Ah  
005Ah INT3 Interrupt Control Register  
001Bh  
005Bh Comparator 0 Interrupt Control Register  
001Ch Count Source Protection Mode Register  
CSPR  
117  
005Ch Comparator 1 Interrupt Control Register  
001Dh  
001Eh  
001Fh  
0020h  
0021h  
0022h  
005Dh INT0 Interrupt Control Register  
005Eh  
005Fh  
0060h  
0061h  
0062h  
0063h  
0064h  
0065h  
0066h  
0067h  
0068h  
0069h  
006Ah  
006Bh  
006Ch  
006Dh  
006Eh  
006Fh  
0070h  
0071h  
0072h  
0073h  
0074h  
0075h  
0076h  
0077h  
0078h  
0079h  
007Ah  
007Bh  
007Ch  
007Dh  
007Eh  
007Fh  
0023h High-Speed On-Chip Oscillator Control  
Register 0  
FRA0  
FRA1  
FRA2  
70  
70  
70  
0024h High-Speed On-Chip Oscillator Control  
Register 1  
0025h High-Speed On-Chip Oscillator Control  
Register 2  
0026h  
0027h  
0028h  
0029h  
002Ah  
002Bh  
002Ch High-Speed On-Chip Oscillator Control  
Register 7  
FRA7  
71  
0030h  
0031h Voltage Detection Register 1  
VCA1  
VCA2  
33  
0032h Voltage Detection Register 2  
33, 71  
0033h  
0034h  
0035h  
0036h Voltage Monitor 1 Circuit Control Register  
VW1C  
VW2C  
34  
35  
0037h Voltage Monitor 2 Circuit Control Register  
0038h  
0039h  
003Ah  
003Bh  
003Ch  
003Dh  
003Eh  
003Fh  
NOTE:  
1. The blank regions are reserved. Do not access locations in these  
regions.  
B - 1  
Address  
0080h  
0081h  
0082h  
0083h  
0084h  
0085h  
0086h  
0087h  
0088h  
0089h  
008Ah  
008Bh  
008Ch  
008Dh  
008Eh  
008Fh  
0090h  
0091h  
0092h  
0093h  
0094h  
0095h  
0096h  
0097h  
0098h  
0099h  
009Ah  
009Bh  
009Ch  
009Dh  
009Eh  
009Fh  
Register  
Symbol  
Page  
Address  
00C0h A/D Register  
00C1h  
Register  
Symbol  
AD  
Page  
242  
00C2h  
00C3h  
00C4h  
00C5h  
00C6h  
00C7h  
00C8h  
00C9h  
00CAh  
00CBh  
00CCh  
00CDh  
00CEh  
00CFh  
00D0h  
00D1h  
00D2h  
00D3h  
00D4h A/D Control Register 2  
00D5h  
ADCON2  
242  
00D6h A/D Control Register 0  
00D7h A/D Control Register 1  
00D8h D/A Register 0  
00D9h  
ADCON0  
ADCON1  
DA0  
241  
242  
254  
00DAh D/A Register 1  
00DBh  
DA1  
254  
254  
00DCh D/A Control Register  
00DDh  
DACON  
00DEh  
00DFh  
00A0h UART0 Transmit/Receive Mode Register  
00A1h UART0 Bit Rate Register  
00A2h UART0 Transmit Buffer Register  
00A3h  
U0MR  
210  
210  
209  
00E0h Port P0 Register  
00E1h Port P1 Register  
00E2h Port P0 Direction Register  
00E3h Port P1 Direction Register  
00E4h  
P0  
49  
49  
48  
48  
U0BRG  
U0TB  
P1  
PD0  
PD1  
00A4h UART0 Transmit / Receive Control Register 0 U0C0  
00A5h UART0 Transmit / Receive Control Register 1 U0C1  
211  
212  
209  
00E5h Port P3 Register  
00E6h  
P3  
49  
00A6h UART0 Receive Buffer Register  
U0RB  
00A7h  
00A8h  
00A9h  
00AAh  
00ABh  
00ACh  
00ADh  
00AEh  
00AFh  
00B0h  
00B1h  
00B2h  
00B3h  
00B4h  
00B5h  
00B6h  
00B7h  
00B8h  
00B9h  
00BAh  
00BBh  
00BCh  
00BDh  
00BEh  
00BFh  
00E7h Port P3 Direction Register  
00E8h Port P4 Register  
00E9h Port P5 Register  
00EAh Port P4 Direction Register  
00EBh Port P5 Direction Register  
00ECh  
PD3  
P4  
48  
49  
49  
48  
48  
P5  
PD4  
PD5  
00EDh  
00EEh  
00EFh  
00F0h  
00F1h  
00F2h  
00F3h  
00F4h  
00F5h  
00F6h Pin Select Register 2  
00F7h Pin Select Register 3  
00F8h Port Mode Register  
00F9h External Input Enable Register  
00FAh INT Input Filter Select Register  
00FBh Key Input Enable Register  
00FCh Pull-Up Control Register 0  
00FDh Pull-Up Control Register 1  
00FEh Port P1 Drive Capacity Control Register  
00FFh  
PINSR2  
PINSR3  
PMR  
50  
50  
50, 212  
104  
105  
108  
51  
INTEN  
INTF  
KIEN  
PUR0  
PUR1  
P1DRR  
51  
51  
NOTE:  
1. The blank regions are reserved. Do not access locations in these  
regions.  
B - 2  
Address  
Register  
Symbol  
TRACR  
Page  
123  
Address  
Register  
Symbol  
TRCCR2  
TRCDF  
Page  
167  
0100h Timer RA Control Register  
0130h Timer RC Control Register 2  
0101h Timer RA I/O Control Register  
TRAIOC  
123, 125, 128,  
130, 132, 135  
0131h Timer RC Digital Filter Function Select  
Register  
168  
0102h Timer RA Mode Register  
0103h Timer RA Prescaler Register  
0104h Timer RA Register  
TRAMR  
TRAPRE  
TRA  
124  
124  
124  
0132h Timer RC Output Master Enable Register TRCOER  
169  
0133h  
0134h  
0135h  
0136h  
0137h  
0138h  
0139h  
013Ah  
013Bh  
013Ch  
013Dh  
013Eh  
013Fh  
0140h  
0141h  
0142h  
0143h  
0144h  
0145h  
0146h  
0147h  
0148h  
0149h  
014Ah  
014Bh  
014Ch  
014Dh  
014Eh  
014Fh  
0150h  
0151h  
0152h  
0153h  
0154h  
0155h  
0156h  
0157h  
0158h  
0159h  
015Ah  
015Bh  
015Ch  
015Dh  
015Eh  
015Fh  
0160h  
0161h  
0162h  
0163h  
0164h  
0165h  
0166h  
0167h  
0168h  
0169h  
016Ah  
016Bh  
016Ch  
016Dh  
016Eh  
016Fh  
0105h  
0106h LIN Control Register  
0107h LIN Status Register  
LINCR  
226  
227  
139  
139  
LINST  
0108h Timer RB Control Register  
0109h Timer RB One-Shot Control Register  
010Ah Timer RB I/O Control Register  
TRBCR  
TRBOCR  
TRBIOC  
140, 142, 146,  
149, 153  
010Bh Timer RB Mode Register  
TRBMR  
TRBPRE  
TRBSC  
TRBPR  
140  
141  
141  
141  
010Ch Timer RB Prescaler Register  
010Dh Timer RB Secondary Register  
010Eh Timer RB Primary Register  
010Fh  
0110h  
0111h  
0112h  
0113h  
0114h  
0115h  
0116h  
0117h  
0118h Timer RE Counter Data Register  
0119h Timer RE Compare Data Register  
011Ah  
TRESEC  
TREMIN  
203  
203  
011Bh  
011Ch Timer RE Control Register 1  
011Dh Timer RE Control Register 2  
011Eh Timer RE Clock Source Select Register  
011Fh  
TRECR1  
TRECR2  
TRECSR  
203  
204  
204  
0120h Timer RC Mode Register  
0121h Timer RC Control Register 1  
TRCMR  
162  
TRCCR1  
163, 186, 190,  
195  
0122h Timer RC Interrupt Enable Register  
0123h Timer RC Status Register  
0124h Timer RC I/O Control Register 0  
0125h Timer RC I/O Control Register 1  
0126h Timer RC Counter  
0127h  
TRCIER  
TRCSR  
TRCIOR0  
TRCIOR1  
TRC  
164  
165  
170, 179, 184  
170, 180, 185  
166  
0128h Timer RC General Register A  
0129h  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
166  
166  
166  
166  
012Ah Timer RC General Register B  
012Bh  
012Ch Timer RC General Register C  
012Dh  
012Eh Timer RC General Register D  
012Fh  
NOTE:  
1. The blank regions are reserved. Do not access locations in these  
regions.  
B - 3  
Address  
0170h  
0171h  
0172h  
0173h  
Register  
Symbol  
Page  
Address  
01B0h  
01B1h  
01B2h  
Register  
Symbol  
Page  
01B3h Flash Memory Control Register 4  
FMR4  
275  
274  
273  
0174h Comparator 0 Control Register  
ACCR0  
255, 258  
255, 258  
01B4h  
0175h Comparator 1 Control Register  
ACCR1  
01B5h Flash Memory Control Register 1  
FMR1  
FMR0  
0176h  
0177h Comparator Mode Register  
0178h  
01B6h  
ACMR  
259  
01B7h Flash Memory Control Register 0  
01B8h  
01B9h  
01BAh  
01BBh  
01BCh  
01BDh  
01BEh  
0179h  
017Ah  
017Bh  
017Ch  
017Dh  
017Eh  
017Fh  
0180h  
FFFFh Option Function Select Register  
OFS  
26, 117, 268  
0181h  
0182h  
0183h  
0184h  
0185h  
0186h  
0187h  
0188h  
0189h  
018Ah  
018Bh  
018Ch  
018Dh  
018Eh  
018Fh  
0190h  
0191h  
0192h  
0193h  
0194h  
0195h  
0196h  
0197h  
0198h  
0199h  
019Ah  
019Bh  
019Ch  
019Dh  
019Eh  
019Fh  
01A0h  
01A1h  
01A2h  
01A3h  
01A4h  
01A5h  
01A6h  
01A7h  
01A8h  
01A9h  
01AAh  
01ABh  
01ACh  
01ADh  
01AEh  
01AFh  
NOTE:  
1. The blank regions are reserved. Do not access locations in these  
regions.  
B - 4  
R8C/2E Group, R8C/2F Group  
RENESAS MCU  
REJ09B0349-0100  
Rev.1.00  
Dec 14, 2007  
1. Overview  
1.1  
Features  
The R8C/2E Group and R8C/2F Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,  
employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable  
of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation  
processing.  
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also  
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.  
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of  
system components.  
Furthermore, the R8C/2F Group has on-chip data flash (1 KB × 2 blocks).  
The difference between the R8C/2E Group and R8C/2F Group is only the presence or absence of data flash. Their  
peripheral functions are the same.  
1.1.1  
Applications  
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.  
Rev.1.00 Dec 14, 2007 Page 1 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
1.1.2  
Specifications  
Tables 1.1 and 1.2 outlines the Specifications for R8C/2E Group and Tables 1.3 and 1.4 outlines the  
Specifications for R8C/2F Group.  
Table 1.1  
Item  
Specifications for R8C/2E Group (1)  
Function  
Specification  
CPU  
Central  
R8C/Tiny series core  
processing unit  
• Number of fundamental instructions: 89  
• Minimum instruction execution time:  
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)  
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)  
• Multiplier: 16 bits × 16 bits 32 bits  
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits  
• Operation mode: Single-chip mode (address space: 1 Mbyte)  
Refer to Table 1.5 Product List for R8C/2E Group.  
• Power-on reset  
Memory  
PowerSupply Voltage  
ROM, RAM  
Voltage  
detection circuit • Voltage detection 2  
Detection  
I/O Ports  
Programmable  
I/O ports  
• Input-only: 3 pins  
• CMOS I/O ports: 25, selectable pull-up resistor  
• High current drive ports: 8  
Clock  
Clock generation 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),  
circuits  
On-chip oscillator (high-speed, low-speed)  
(high-speed on-chip oscillator has a frequency adjustment  
function)  
• Oscillation stop detection: XIN clock oscillation stop detection  
function  
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16  
• Low power consumption modes:  
Standard operating mode (high-speed clock, high-speed on-chip  
oscillator, low-speed on-chip oscillator), wait mode, stop mode  
• External: 4 sources, Internal: 13 sources, Software: 4 sources  
• Priority levels: 7 levels  
Interrupts  
Watchdog Timer  
15 bits × 1 (with prescaler), reset start selectable  
Timer  
Timer RA  
8 bits × 1 (with 8-bit prescaler)  
Timer mode (period timer), pulse output mode (output level inverted  
every period), event counter mode, pulse width measurement mode,  
pulse period measurement mode  
Timer RB  
Timer RC  
8 bits × 1 (with 8-bit prescaler)  
Timer mode (period timer), programmable waveform generation  
mode (PWM output), programmable one-shot generation mode,  
programmable wait one-shot generation mode  
16 bits × 1 (with 4 capture/compare registers)  
Timer mode (input capture function, output compare function), PWM  
mode (output 3 pins), PWM2 mode (PWM output pin)  
Timer RE  
UART0  
8 bits × 1  
Output compare mode  
Serial  
Clock synchronous serial I/O/UART × 1  
Interface  
LIN Module  
A/D Converter  
D/A Converter  
Comparator  
Hardware LIN: 1 (timer RA, UART0)  
10-bit resolution × 12 channels, includes sample and hold function  
8-bit resolution × 2 circuits  
2 circuits  
Rev.1.00 Dec 14, 2007 Page 2 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
Table 1.2  
Specifications for R8C/2E Group (2)  
Item  
Specification  
Flash Memory  
• Programming and erasure voltage: VCC = 2.7 to 5.5 V  
• Programming and erasure endurance: 100 times  
• Program security: ROM code protect, ID code check  
• Debug functions: On-chip debug, on-board flash rewrite function  
Operating Frequency/Supply  
Voltage  
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V),  
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)  
Current consumption  
Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)  
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)  
Typ. 23 µA (VCC = 3.0 V, wait mode (peripheral clock off))  
Typ. 0.7 µA (VCC = 3.0 V, stop mode)  
Operating Ambient Temperature -20 to 85°C (N version)  
-40 to 85°C (D version)  
(1)  
Package  
32-pin LQFP  
Package code: PLQP0032GB-A (previous code: 32P6U-A)  
NOTE:  
1. Specify the D version if D version functions are to be used.  
Rev.1.00 Dec 14, 2007 Page 3 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
Table 1.3  
Item  
CPU  
Specifications for R8C/2F Group (1)  
Function  
Central  
processing unit  
Specification  
R8C/Tiny series core  
• Number of fundamental instructions: 89  
• Minimum instruction execution time:  
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)  
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)  
• Multiplier: 16 bits × 16 bits 32 bits  
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits  
• Operation mode: Single-chip mode (address space: 1 Mbyte)  
Refer to Table 1.6 Product List for R8C/2F Group.  
Memory  
ROM, RAM  
PowerSupply Voltage detection • Power-on reset  
Voltage  
circuit  
• Voltage detection 2  
Detection  
I/O Ports  
Programmable  
I/O ports  
• Input-only: 3 pins  
• CMOS I/O ports: 25, selectable pull-up resistor  
• High current drive ports: 8  
Clock  
Clock generation 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),  
circuits  
On-chip oscillator (high-speed, low-speed)  
(high-speed on-chip oscillator has a frequency adjustment  
function)  
• Oscillation stop detection: XIN clock oscillation stop detection  
function  
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16  
• Low power consumption modes:  
Standard operating mode (high-speed clock, high-speed on-chip  
oscillator, low-speed on-chip oscillator), wait mode, stop mode  
• External: 4 sources, Internal: 13 sources, Software: 4 sources  
• Priority levels: 7 levels  
Interrupts  
Watchdog Timer  
15 bits × 1 (with prescaler), reset start selectable  
Timer  
Timer RA  
8 bits × 1 (with 8-bit prescaler)  
Timer mode (period timer), pulse output mode (output level inverted  
every period), event counter mode, pulse width measurement mode,  
pulse period measurement mode  
Timer RB  
Timer RC  
8 bits × 1 (with 8-bit prescaler)  
Timer mode (period timer), programmable waveform generation  
mode (PWM output), programmable one-shot generation mode,  
programmable wait one-shot generation mode  
16 bits × 1 (with 4 capture/compare registers)  
Timer mode (input capture function, output compare function), PWM  
mode (output 3 pins), PWM2 mode (PWM output pin)  
Timer RE  
UART0  
8 bits × 1  
Output compare mode  
Serial  
Clock synchronous serial I/O/UART × 1  
Interface  
LIN Module  
A/D Converter  
D/A Converter  
Comparator  
Hardware LIN: 1 (timer RA, UART0)  
10-bit resolution × 12 channels, includes sample and hold function  
8-bit resolution × 2 circuits  
2 circuits  
Rev.1.00 Dec 14, 2007 Page 4 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
Table 1.4  
Specifications for R8C/2F Group (2)  
Item  
Specification  
Flash Memory  
• Programming and erasure voltage: VCC = 2.7 to 5.5 V  
• Programming and erasure endurance: 10,000 times (data flash)  
1,000 times (program ROM)  
• Program security: ROM code protect, ID code check  
• Debug functions: On-chip debug, on-board flash rewrite function  
Operating Frequency/Supply  
Voltage  
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V),  
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)  
Current consumption  
Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)  
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)  
Typ. 23 µA (VCC = 3.0 V, wait mode (peripheral clock off))  
Typ. 0.7 µA (VCC = 3.0 V, stop mode)  
Operating Ambient Temperature -20 to 85°C (N version)  
-40 to 85°C (D version)  
(1)  
Package  
32-pin LQFP  
Package code: PLQP0032GB-A (previous code: 32P6U-A)  
NOTE:  
1. Specify the D version if D version functions are to be used.  
Rev.1.00 Dec 14, 2007 Page 5 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
1.2  
Product List  
Table 1.5 lists Product List for R8C/2E Group, Figure 1.1 shows a Part Number, Memory Size, and Package of  
R8C/2E Group, Table 1.6 lists Product List for R8C/2F Group, and Figure 1.2 shows a Part Number, Memory Size,  
and Package of R8C/2F Group.  
Table 1.5  
Product List for R8C/2E Group  
ROM Capacity RAM Capacity  
Current of Dec. 2007  
Part No.  
Package Type  
PLQP0032GB-A  
PLQP0032GB-A  
PLQP0032GB-A  
PLQP0032GB-A  
PLQP0032GB-A  
PLQP0032GB-A  
Remarks  
N version  
R5F212E2NFP  
R5F212E4NFP  
R5F212E2DFP  
R5F212E4DFP  
R5F212E2NXXXFP  
R5F212E4NXXXFP  
8 Kbytes  
512 bytes  
1 Kbyte  
16 Kbytes  
8 Kbytes  
16 Kbytes  
8 Kbytes  
16 Kbytes  
512 bytes  
1 Kbyte  
D version  
512 bytes  
1 Kbyte  
N version  
Factory programming  
(1)  
product  
R5F212E2DXXXFP  
R5F212E4DXXXFP  
8 Kbytes  
512 bytes  
1 Kbyte  
PLQP0032GB-A  
PLQP0032GB-A  
D version  
Factory programming  
16 Kbytes  
(1)  
product  
NOTE:  
1. The user ROM is programmed before shipment.  
Part No. R 5 F 21 2E 2 N XXX FP  
Package type:  
FP: PLQP0032GB-A  
ROM number (only factory programming product)  
Classification  
N: Operating ambient temperature -20°C to 85°C  
D: Operating ambient temperature -40°C to 85°C  
ROM capacity  
2: 8 KB  
4: 16 KB  
R8C/2E Group  
R8C/Tiny Series  
Memory type  
F: Flash memory version  
Renesas MCU  
Renesas semiconductor  
Figure 1.1  
Part Number, Memory Size, and Package of R8C/2E Group  
Rev.1.00 Dec 14, 2007 Page 6 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
Table 1.6  
Product List for R8C/2F Group  
Current of Dec. 2007  
ROM Capacity  
RAM  
Capacity  
Part No.  
Package Type  
Remarks  
Program ROM Data flash  
R5F212F2NFP  
R5F212F4NFP  
R5F212F2DFP  
R5F212F4DFP  
R5F212F2NXXXFP  
R5F212F4NXXXFP  
8 Kbytes  
16 Kbytes  
8 Kbytes  
16 Kbytes  
8 Kbytes  
16 Kbytes  
1 Kbyte × 2 512 bytes PLQP0032GB-A N version  
1 Kbyte × 2 1 Kbyte PLQP0032GB-A  
1 Kbyte × 2 512 bytes PLQP0032GB-A D version  
1 Kbyte × 2 1 Kbyte PLQP0032GB-A  
1 Kbyte × 2 512 bytes PLQP0032GB-A N version  
Factoryprogramming  
PLQP0032GB-A  
1 Kbyte × 2 1 Kbyte  
(1)  
product  
R5F212F2DXXXFP  
R5F212F4DXXXFP  
8 Kbytes  
1 Kbyte × 2 512 bytes PLQP0032GB-A D version  
Factoryprogramming  
PLQP0032GB-A  
16 Kbytes  
1 Kbyte × 2 1 Kbyte  
(1)  
product  
NOTE:  
1. The user ROM is programmed before shipment.  
Part No. R 5 F 21 2F 2 N XXX FP  
Package type:  
FP: PLQP0032GB-A  
ROM number (only factory programming product)  
Classification  
N: Operating ambient temperature -20°C to 85°C  
D: Operating ambient temperature -40°C to 85°C  
ROM capacity  
2: 8 KB  
4: 16 KB  
R8C/2F Group  
R8C/Tiny Series  
Memory type  
F: Flash memory version  
Renesas MCU  
Renesas semiconductor  
Figure 1.2  
Part Number, Memory Size, and Package of R8C/2F Group  
Rev.1.00 Dec 14, 2007 Page 7 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
1.3  
Block Diagram  
Figure 1.3 shows a Block Diagram.  
8
8
1
3
6
2
Port P0  
Port P1  
I/O ports  
Port P3  
Port P4  
Port P5  
Peripheral functions  
System clock  
generation circuit  
A/D converter  
(10 bits × 12 channels)  
Timers  
Timer RA (8 bits × 1)  
Timer RB (8 bits × 1)  
Timer RC (16 bits × 1)  
Timer RE (8 bits × 1)  
XIN-XOUT  
High-speed on-chip oscillator  
Low-Speed on-chip oscillator  
D/A converter  
(8 bits × 2)  
Comparator  
UART or  
clock synchronous serial I/O  
(8 bits × 1)  
(× 2)  
LIN module  
Watchdog timer  
(15 bits)  
Memory  
R8C/Tiny Series CPU core  
ROM(1)  
R0H  
R1H  
R0L  
R1L  
SB  
USP  
ISP  
INTB  
PC  
FLG  
R2  
R3  
RAM(2)  
A0  
A1  
FB  
Multiplier  
NOTES:  
1. ROM size varies with MCU type.  
2. RAM size varies with MCU type.  
Figure 1.3  
Block Diagram  
Rev.1.00 Dec 14, 2007 Page 8 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
1.4  
Pin Assignment  
Figure 1.4 shows Pin Assignments (Top View). Table 1.7 outlines the Pin Name Information by Pin Number.  
24 23 22 21 20 19 18 17  
P1_5/RXD0/(TRAIO)/(INT1)(2)  
25  
26  
27  
28  
29  
30  
31  
32  
16  
15  
14  
13  
12  
11  
10  
9
P0_7/AN0/DA1  
P1_6/CLK0  
P0_6/AN1/DA0  
P0_5/AN2/AVREF0  
P0_4/AN3/TREO/ACMP0  
P0_3/AN4/AVREF1  
P0_2/AN5/ACMP1  
P0_1/AN6  
R8C/2E Group,  
R8C/2F Group  
P5_3/TRCIOC/ACOUT0  
P5_4/TRCIOD/ACOUT1  
P3_1/TRBO  
PLQP0032GB-A  
(32P6U-A)  
P3_6/(INT1)(2)  
(top view)  
P1_7/TRAIO/INT1  
P4_5/INT0  
P0_0/AN7  
1
2
3
4
5
6
7
8
NOTES:  
1. P4_7 is an input-only port.  
2. Can be assigned to the pin in parentheses by a program.  
3. Confirm the pin 1 position on the package by referring to the package dimensions.  
Figure 1.4  
Pin Assignments (Top View)  
Rev.1.00 Dec 14, 2007 Page 9 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
Table 1.7  
Pin Name Information by Pin Number  
I/O Pin Functions for of Peripheral Modules  
Pin  
Number  
Control Pin  
Port  
Serial  
A/D  
D/A  
Interrupt  
Timer  
Comparator  
Interface  
Converter  
Converter  
(TRCIOD)(1)  
TRAO  
1
2
3
4
5
6
7
8
9
P3_5  
P3_7  
RESET  
XOUT  
P4_7  
P4_6  
VSS/AVSS  
XIN  
VCC/AVCC  
MODE  
P4_5  
P1_7  
P3_6  
INT0  
INT1  
10  
11  
TRAIO  
(INT1)(1)  
12  
13  
14  
15  
P3_1  
P5_4  
P5_3  
P1_6  
TRBO  
TRCIOD  
TRCIOC  
ACOUT1  
ACOUT0  
CLK0  
RXD0  
TXD0  
(TRAIO)(1)  
(INT1)(1)  
16  
17  
18  
P1_5  
P1_4  
P1_3  
(TRBO)(1)  
TRCIOB  
AN11  
AN10  
KI3  
KI2  
19  
20  
21  
P1_2  
P4_2  
P1_1  
VREF  
TRCIOA/  
TRCTRG  
AN9  
AN8  
KI1  
22  
23  
P1_0  
P3_3  
KI0  
TRCCLK  
INT3  
(TRCIOC)(1)  
24  
25  
26  
27  
28  
29  
30  
31  
32  
P3_4  
P0_7  
P0_6  
P0_5  
P0_4  
P0_3  
P0_2  
P0_1  
P0_0  
AN0  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
DA1  
DA0  
AVREF0  
ACMP0  
AVREF1  
ACMP1  
TREO  
NOTE:  
1. Can be assigned to the pin in parentheses by a program.  
Rev.1.00 Dec 14, 2007 Page 10 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
1.Overview  
1.5  
Pin Functions  
Table 1.8 list Pin Functions.  
Table 1.8  
Type  
Power supply input VCC, VSS  
Pin Functions  
Symbol  
I/O Type  
Description  
I
I
Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.  
Analog power  
supply input  
AVCC, AVSS  
Power supply for the A/D converter.  
Connect a capacitor between AVCC and AVSS.  
Reset input  
MODE  
RESET  
MODE  
XIN  
I
I
I
Input “L” on this pin resets the MCU.  
Connect this pin to VCC via a resistor.  
XIN clock input  
These pins are provided for XIN clock generation circuit I/O.  
Connect a ceramic resonator or a crystal oscillator between  
the XIN and XOUT pins.(1) To use an external clock, input it to  
the XIN pin and leave the XOUT pin open.  
XIN clock output  
XOUT  
O
INT interrupt input INT0, INT1, INT3  
I
I
INT interrupt input pins  
Key input interrupt  
Timer RA  
Key input interrupt input pins  
KI0 to KI3  
TRAO  
O
I/O  
O
I
Timer RA output pin  
Timer RA I/O pin  
TRAIO  
Timer RB  
Timer RC  
TRBO  
Timer RB output pin  
External clock input pin  
External trigger input pin  
TRCCLK  
TRCTRG  
I
TRCIOA, TRCIOB,  
TRCIOC, TRCIOD  
I/O  
Sharing output-compare output / input-capture input / PWM /  
PWM2 output pins  
Timer RE  
TREO  
CLK0  
RXD0  
TXD0  
O
I/O  
I
Timer RE output pin  
Serial interface  
Clock I/O pin  
Receive data input pin  
O
I
Transmit data output pin  
Reference voltage input pin to A/D converter  
Reference voltage VREF  
input  
A/D converter  
D/A converter  
Comparator  
AN0 to AN11  
I
O
I
Analog input pins to A/D converter  
DA0 to DA1  
Output pins from D/A converter  
AVREF0 to AVREF1  
ACMP0 to ACMP1  
ACOUT0 to ACOUT1  
Reference voltage input pins to comparator  
Analog voltage input pins to comparator  
Comparison result output pins of comparator  
I
O
I/O  
I/O port  
P0_0 to P0_7,  
P1_0 to P1_7,  
P3_1, P3_3 to P3_7,  
P4_5,  
CMOS I/O ports. Each port has an I/O select direction  
register, allowing each pin in the port to be directed for input  
or output individually.  
Any port set to input can be set to use a pull-up resistor or not  
by a program.  
P5_3, P5_4  
P1_0 to P1_7 also function as LED drive ports.  
Input port  
P4_2, P4_6, P4_7  
I
Input-only ports  
I: Input  
NOTE:  
O: Output  
I/O: Input and output  
1. Refer to the oscillator manufacturer for oscillation characteristics.  
Rev.1.00 Dec 14, 2007 Page 11 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
2. Central Processing Unit (CPU)  
2. Central Processing Unit (CPU)  
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a  
register bank. There are two sets of register bank.  
b31  
b15  
b8b7  
b0  
R0H (high-order of R0) R0L (low-order of R0)  
R1H (high-order of R1) R1L (low-order of R1)  
R2  
R2  
R3  
Data registers(1)  
R3  
A0  
Address registers(1)  
A1  
FB  
Frame base register(1)  
b19  
b15  
b0  
b0  
Interrupt table register  
Program counter  
INTBH  
INTBL  
The 4 high order bits of INTB are INTBH and  
the 16 low order bits of INTB are INTBL.  
b19  
PC  
b15  
b0  
User stack pointer  
Interrupt stack pointer  
Static base register  
USP  
ISP  
SB  
b15  
b0  
b0  
Flag register  
FLG  
b15  
b8  
b7  
IPL  
U I O B S Z D C  
Carry flag  
Debug flag  
Zero flag  
Sign flag  
Register bank select flag  
Overflow flag  
Interrupt enable flag  
Stack pointer select flag  
Reserved bit  
Processor interrupt priority level  
Reserved bit  
NOTE:  
1. These registers comprise a register bank. There are two register banks.  
Figure 2.1  
CPU Registers  
Rev.1.00 Dec 14, 2007 Page 12 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
2. Central Processing Unit (CPU)  
2.1  
Data Registers (R0, R1, R2, and R3)  
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split  
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are  
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is  
analogous to R2R0.  
2.2  
Address Registers (A0 and A1)  
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also  
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used  
as a 32-bit address register (A1A0).  
2.3  
Frame Base Register (FB)  
FB is a 16-bit register for FB relative addressing.  
2.4  
Interrupt Table Register (INTB)  
INTB is a 20-bit register that indicates the start address of an interrupt vector table.  
2.5  
Program Counter (PC)  
PC is 20 bits wide and indicates the address of the next instruction to be executed.  
2.6  
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)  
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between  
USP and ISP.  
2.7  
Static Base Register (SB)  
SB is a 16-bit register for SB relative addressing.  
2.8  
Flag Register (FLG)  
FLG is an 11-bit register indicating the CPU state.  
2.8.1  
Carry Flag (C)  
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.  
2.8.2  
Debug Flag (D)  
The D flag is for debugging only. Set it to 0.  
2.8.3  
Zero Flag (Z)  
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.  
2.8.4  
Sign Flag (S)  
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.  
2.8.5  
Register Bank Select Flag (B)  
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.  
2.8.6  
Overflow Flag (O)  
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.  
Rev.1.00 Dec 14, 2007 Page 13 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
2. Central Processing Unit (CPU)  
2.8.7  
Interrupt Enable Flag (I)  
The I flag enables maskable interrupts.  
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0  
when an interrupt request is acknowledged.  
2.8.8  
Stack Pointer Select Flag (U)  
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.  
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software  
interrupt numbers 0 to 31 is executed.  
2.8.9  
Processor Interrupt Priority Level (IPL)  
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.  
If a requested interrupt has higher priority than IPL, the interrupt is enabled.  
2.8.10 Reserved Bit  
If necessary, set to 0. When read, the content is undefined.  
Rev.1.00 Dec 14, 2007 Page 14 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
3.Memory  
3. Memory  
3.1  
R8C/2E Group  
Figure 3.1 is a Memory Map of R8C/2E Group. The R8C/2E group has 1 Mbyte of address space from addresses  
00000h to FFFFFh.  
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal  
ROM area is allocated addresses 0C000h to 0FFFFh.  
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each  
interrupt routine.  
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal  
RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for  
calling subroutines and as stacks when interrupt requests are acknowledged.  
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control  
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use  
and cannot be accessed by users.  
00000h  
SFR  
(Refer to 4. Special  
Function Registers  
(SFRs))  
002FFh  
00400h  
Internal RAM  
0XXXh  
0FFDCh  
Undefined instruction  
Overflow  
BRK instruction  
Address match  
Single step  
Watchdog timer/oscillation stop detection/voltage monitor 2  
0YYYYh  
(Reserved)  
(Reserved)  
Internal ROM  
(program ROM)  
Reset  
0FFFFh  
0FFFFh  
FFFFFh  
NOTE:  
1. The blank regions are reserved. Do not access locations in these regions.  
Internal ROM  
Part Number  
Internal RAM  
Size  
Address 0YYYYh  
Size  
Address 0XXXXh  
005FFh  
R5F212E2NFP, R5F212E2DFP,  
512 bytes  
8 Kbytes  
0E000h  
R5F212E2NXXXFP, R5F212E2DXXXFP  
R5F212E4NFP, R5F212E4DFP,  
1 Kbyte  
16 Kbytes  
0C000h  
007FFh  
R5F212E4NXXXFP, R5F212E4DXXXFP  
Figure 3.1  
Memory Map of R8C/2E Group  
Rev.1.00 Dec 14, 2007 Page 15 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
3.Memory  
3.2  
R8C/2F Group  
Figure 3.2 is a Memory Map of R8C/2F Group. The R8C/2F group has 1 Mbyte of address space from addresses  
00000h to FFFFFh.  
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a  
16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.  
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each  
interrupt routine.  
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.  
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte  
internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also  
for calling subroutines and as stacks when interrupt requests are acknowledged.  
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control  
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use  
and cannot be accessed by users.  
00000h  
SFR  
(Refer to 4. Special  
Function Registers  
(SFRs))  
002FFh  
00400h  
Internal RAM  
0XXXXh  
02400h  
0FFDCh  
Internal ROM  
(data flash)(1)  
Undefined instruction  
Overflow  
02BFFh  
0YYYYh  
BRK instruction  
Address match  
Single step  
Watchdog timer/oscillation stop detection/voltage monitor 2  
(Reserved)  
Internal ROM  
(program ROM)  
(Reserved)  
Reset  
0FFFFh  
0FFFFh  
FFFFFh  
NOTES:  
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.  
2. The blank regions are reserved. Do not access locations in these regions.  
Internal ROM  
Part Number  
Internal RAM  
Size  
Address 0YYYYh  
Size  
Address 0XXXXh  
005FFh  
R5F212F2NFP, R5F212F2DFP,  
512 bytes  
8 Kbytes  
0E000h  
R5F212F2NXXXFP, R5F212F2DXXXFP  
R5F212F4NFP, R5F212F4DFP,  
1 Kbyte  
16 Kbytes  
0C000h  
007FFh  
R5F212F4NXXXFP, R5F212F4DXXXFP  
Figure 3.2  
Memory Map of R8C/2F Group  
Rev.1.00 Dec 14, 2007 Page 16 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
4. Special Function Registers (SFRs)  
4. Special Function Registers (SFRs)  
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special  
function registers.  
(1)  
Table 4.1  
SFR Information (1)  
Address  
0000h  
0001h  
0002h  
0003h  
0004h  
0005h  
0006h  
0007h  
0008h  
0009h  
000Ah  
000Bh  
000Ch  
000Dh  
000Eh  
000Fh  
0010h  
0011h  
0012h  
0013h  
0014h  
0015h  
0016h  
0017h  
0018h  
0019h  
001Ah  
001Bh  
001Ch  
Register  
Symbol  
After reset  
Processor Mode Register 0  
Processor Mode Register 1  
System Clock Control Register 0  
System Clock Control Register 1  
PM0  
PM1  
CM0  
CM1  
00h  
00h  
01101000b  
00100000b  
Protect Register  
PRCR  
00h  
Oscillation Stop Detection Register  
Watchdog Timer Reset Register  
Watchdog Timer Start Register  
Watchdog Timer Control Register  
Address Match Interrupt Register 0  
OCD  
00000100b  
XXh  
WDTR  
WDTS  
WDC  
XXh  
00X11111b  
00h  
RMAD0  
00h  
00h  
00h  
00h  
00h  
00h  
Address Match Interrupt Enable Register  
Address Match Interrupt Register 1  
AIER  
RMAD1  
Count Source Protection Mode Register  
CSPR  
00h  
10000000b(4)  
001Dh  
001Eh  
001Fh  
0020h  
0021h  
0022h  
0023h  
0024h  
0025h  
0026h  
0027h  
0028h  
0029h  
002Ah  
002Bh  
002Ch  
High-Speed On-Chip Oscillator Control Register 0  
High-Speed On-Chip Oscillator Control Register 1  
High-Speed On-Chip Oscillator Control Register 2  
FRA0  
FRA1  
FRA2  
00h  
When shipping  
00h  
High-Speed On-Chip Oscillator Control Register 7  
FRA7  
When Shipping  
0030h  
0031h  
0032h  
0033h  
0034h  
0035h  
0036h  
0037h  
0038h  
0039h  
003Ah  
003Bh  
003Ch  
003Dh  
003Eh  
003Fh  
Voltage Detection Register 1 (2)  
Voltage Detection Register 2 (2)  
VCA1  
VCA2  
00001000b  
00100000b  
Voltage Monitor 1 Circuit Control Register(3)  
Voltage Monitor 2 Circuit Control Register(3)  
VW1C  
VW2C  
00001000b  
00h  
X: Undefined  
NOTES:  
1. The blank regions are reserved. Do not access locations in these regions.  
2. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register.  
3. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3.  
4. The CSPROINI bit in the OFS register is set to 0.  
Rev.1.00 Dec 14, 2007 Page 17 of 332  
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R8C/2E Group, R8C/2F Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.2  
SFR Information (2)  
Address  
0040h  
0041h  
0042h  
0043h  
0044h  
0045h  
0046h  
0047h  
0048h  
0049h  
004Ah  
004Bh  
004Ch  
004Dh  
004Eh  
004Fh  
0050h  
0051h  
0052h  
0053h  
0054h  
0055h  
0056h  
0057h  
0058h  
0059h  
005Ah  
005Bh  
005Ch  
005Dh  
005Eh  
005Fh  
0060h  
0061h  
0062h  
0063h  
0064h  
0065h  
0066h  
0067h  
0068h  
0069h  
006Ah  
006Bh  
006Ch  
006Dh  
006Eh  
006Fh  
0070h  
0071h  
0072h  
0073h  
0074h  
0075h  
0076h  
0077h  
0078h  
0079h  
007Ah  
007Bh  
007Ch  
007Dh  
007Eh  
007Fh  
Register  
Symbol  
After reset  
Timer RC Interrupt Control Register  
TRCIC  
TREIC  
XXXXX000b  
Timer RE Interrupt Control Register  
XXXXX000b  
Key Input Interrupt Control Register  
KUPIC  
ADIC  
XXXXX000b  
XXXXX000b  
A/D Conversion Interrupt Control Register  
UART0 Transmit Interrupt Control Register  
UART0 Receive Interrupt Control Register  
S0TIC  
S0RIC  
XXXXX000b  
XXXXX000b  
Timer RA Interrupt Control Register  
TRAIC  
TRBIC  
INT1IC  
INT3IC  
CM0IC  
CM1IC  
INT0IC  
XXXXX000b  
Timer RB Interrupt Control Register  
INT1 Interrupt Control Register  
INT3 Interrupt Control Register  
XXXXX000b  
XX00X000b  
XX00X000b  
XXXXX000b  
XXXXX000b  
XX00X000b  
Comparator 0 Interrupt Control Register  
Comparator 1 Interrupt Control Register  
INT0 Interrupt Control Register  
X: Undefined  
NOTE:  
1. The blank regions are reserved. Do not access locations in these regions.  
Rev.1.00 Dec 14, 2007 Page 18 of 332  
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R8C/2E Group, R8C/2F Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.3  
SFR Information (3)  
Address  
0080h  
0081h  
0082h  
0083h  
0084h  
0085h  
0086h  
0087h  
0088h  
0089h  
008Ah  
008Bh  
008Ch  
008Dh  
008Eh  
008Fh  
0090h  
0091h  
0092h  
0093h  
0094h  
0095h  
0096h  
0097h  
0098h  
0099h  
009Ah  
009Bh  
009Ch  
009Dh  
009Eh  
009Fh  
00A0h  
00A1h  
00A2h  
00A3h  
00A4h  
00A5h  
00A6h  
00A7h  
00A8h  
00A9h  
00AAh  
00ABh  
00ACh  
00ADh  
00AEh  
00AFh  
00B0h  
00B1h  
00B2h  
00B3h  
00B4h  
00B5h  
00B6h  
00B7h  
00B8h  
00B9h  
00BAh  
00BBh  
00BCh  
00BDh  
00BEh  
00BFh  
Register  
Symbol  
After reset  
UART0 Transmit/Receive Mode Register  
UART0 Bit Rate Register  
U0MR  
00h  
XXh  
XXh  
XXh  
U0BRG  
U0TB  
UART0 Transmit Buffer Register  
UART0 Transmit/Receive Control Register 0  
UART0 Transmit/Receive Control Register 1  
UART0 Receive Buffer Register  
U0C0  
U0C1  
U0RB  
00001000b  
00000010b  
XXh  
XXh  
X: Undefined  
NOTE:  
1. The blank regions are reserved. Do not access locations in these regions.  
Rev.1.00 Dec 14, 2007 Page 19 of 332  
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R8C/2E Group, R8C/2F Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.4  
SFR Information (4)  
Address  
00C0h  
00C1h  
00C2h  
00C3h  
00C4h  
00C5h  
00C6h  
00C7h  
00C8h  
00C9h  
00CAh  
00CBh  
00CCh  
00CDh  
00CEh  
00CFh  
00D0h  
00D1h  
00D2h  
00D3h  
00D4h  
00D5h  
00D6h  
00D7h  
00D8h  
00D9h  
00DAh  
00DBh  
00DCh  
00DDh  
00DEh  
00DFh  
00E0h  
00E1h  
00E2h  
00E3h  
00E4h  
00E5h  
00E6h  
00E7h  
00E8h  
00E9h  
00EAh  
00EBh  
00ECh  
00EDh  
00EEh  
00EFh  
00F0h  
00F1h  
00F2h  
00F3h  
00F4h  
00F5h  
00F6h  
00F7h  
00F8h  
00F9h  
00FAh  
00FBh  
00FCh  
00FDh  
00FEh  
00FFh  
Register  
Symbol  
After reset  
A/D Register  
AD  
XXh  
XXh  
A/D Control Register 2  
ADCON2  
00h  
A/D Control Register 0  
A/D Control Register 1  
D/A Register 0  
ADCON0  
ADCON1  
DA0  
00h  
00h  
00h  
D/A Register 1  
DA1  
00h  
00h  
D/A Control Register  
DACON  
Port P0 Register  
Port P1 Register  
Port P0 Direction Register  
Port P1 Direction Register  
P0  
P1  
PD0  
PD1  
00h  
00h  
00h  
00h  
Port P3 Register  
P3  
00h  
Port P3 Direction Register  
Port P4 Register  
Port P5 Register  
Port P4 Direction Register  
Port P5 Direction Register  
PD3  
P4  
P5  
PD4  
PD5  
00h  
00h  
00h  
00h  
00h  
Pin Select Register 2  
Pin Select Register 3  
Port Mode Register  
External Input Enable Register  
INT Input Filter Select Register  
Key Input Enable Register  
Pull-Up Control Register 0  
Pull-Up Control Register 1  
PINSR2  
PINSR3  
PMR  
INTEN  
INTF  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
KIEN  
PUR0  
PUR1  
P1DRR  
Port P1 Drive Capacity Control Register  
X: Undefined  
NOTE:  
1. The blank regions are reserved. Do not access locations in these regions.  
Rev.1.00 Dec 14, 2007 Page 20 of 332  
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R8C/2E Group, R8C/2F Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.5  
SFR Information (5)  
Address  
0100h  
0101h  
0102h  
0103h  
0104h  
0105h  
0106h  
0107h  
0108h  
0109h  
010Ah  
010Bh  
010Ch  
010Dh  
010Eh  
010Fh  
0110h  
0111h  
0112h  
0113h  
0114h  
0115h  
0116h  
0117h  
0118h  
0119h  
011Ah  
011Bh  
011Ch  
011Dh  
011Eh  
011Fh  
0120h  
0121h  
0122h  
0123h  
0124h  
0125h  
0126h  
0127h  
0128h  
0129h  
012Ah  
012Bh  
012Ch  
012Dh  
012Eh  
012Fh  
0130h  
0131h  
0132h  
0133h  
0134h  
0135h  
0136h  
0137h  
0138h  
0139h  
013Ah  
013Bh  
013Ch  
013Dh  
013Eh  
013Fh  
Register  
Symbol  
TRACR  
TRAIOC  
TRAMR  
TRAPRE  
TRA  
After reset  
Timer RA Control Register  
Timer RA I/O Control Register  
Timer RA Mode Register  
Timer RA Prescaler Register  
Timer RA Register  
00h  
00h  
00h  
FFh  
FFh  
LIN Control Register  
LIN Status Register  
Timer RB Control Register  
Timer RB One-Shot Control Register  
Timer RB I/O Control Register  
Timer RB Mode Register  
Timer RB Prescaler Register  
Timer RB Secondary Register  
Timer RB Primary Register  
LINCR  
LINST  
00h  
00h  
00h  
00h  
00h  
00h  
FFh  
FFh  
FFh  
TRBCR  
TRBOCR  
TRBIOC  
TRBMR  
TRBPRE  
TRBSC  
TRBPR  
Timer RE Counter Data Register  
Timer RE Compare Data Register  
TRESEC  
TREMIN  
00h  
00h  
Timer RE Control Register 1  
Timer RE Control Register 2  
TRECR1  
TRECR2  
TRECSR  
00h  
00h  
Timer RE Clock Source Select Register  
00001000b  
Timer RC Mode Register  
TRCMR  
TRCCR1  
TRCIER  
TRCSR  
TRCIOR0  
TRCIOR1  
TRC  
01001000b  
00h  
Timer RC Control Register 1  
Timer RC Interrupt Enable Register  
Timer RC Status Register  
Timer RC I/O Control Register 0  
Timer RC I/O Control Register 1  
Timer RC Counter  
01110000b  
01110000b  
10001000b  
10001000b  
00h  
00h  
FFh  
FFh  
FFh  
FFh  
FFh  
FFh  
FFh  
Timer RC General Register A  
Timer RC General Register B  
Timer RC General Register C  
Timer RC General Register D  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
FFh  
Timer RC Control Register 2  
TRCCR2  
TRCDF  
TRCOER  
00011111b  
00h  
01111111b  
Timer RC Digital Filter Function Select Register  
Timer RC Output Master Enable Register  
X: Undefined  
NOTE:  
1. The blank regions are reserved. Do not access locations in these regions.  
Rev.1.00 Dec 14, 2007 Page 21 of 332  
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R8C/2E Group, R8C/2F Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.6  
SFR Information (6)  
Address  
0140h  
0141h  
0142h  
0143h  
0144h  
0145h  
0146h  
0147h  
0148h  
0149h  
014Ah  
014Bh  
014Ch  
014Dh  
014Eh  
014Fh  
0150h  
0151h  
0152h  
0153h  
0154h  
0155h  
0156h  
0157h  
0158h  
0159h  
015Ah  
015Bh  
015Ch  
015Dh  
015Eh  
015Fh  
0160h  
0161h  
0162h  
0163h  
0164h  
0165h  
0166h  
0167h  
0168h  
0169h  
016Ah  
016Bh  
016Ch  
016Dh  
016Eh  
016Fh  
0170h  
0171h  
0172h  
0173h  
0174h  
0175h  
0176h  
0177h  
0178h  
0179h  
017Ah  
017Bh  
017Ch  
017Dh  
017Eh  
017Fh  
Register  
Symbol  
After reset  
Comparator 0 Control Register  
Comparator 1 Control Register  
ACCR0  
ACCR1  
00001000b  
00001000b  
Comparator Mode Register  
ACMR  
00h  
X: Undefined  
NOTE:  
1. The blank regions are reserved. Do not access locations in these regions.  
Rev.1.00 Dec 14, 2007 Page 22 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
4. Special Function Registers (SFRs)  
(1)  
Table 4.7  
SFR Information (7)  
Address  
0180h  
0181h  
0182h  
0183h  
0184h  
0185h  
0186h  
0187h  
0188h  
0189h  
018Ah  
018Bh  
018Ch  
018Dh  
018Eh  
018Fh  
0190h  
0191h  
0192h  
0193h  
0194h  
0195h  
0196h  
0197h  
0198h  
0199h  
019Ah  
019Bh  
019Ch  
019Dh  
019Eh  
019Fh  
01A0h  
01A1h  
01A2h  
01A3h  
01A4h  
01A5h  
01A6h  
01A7h  
01A8h  
01A9h  
01AAh  
01ABh  
01ACh  
01ADh  
01AEh  
01AFh  
01B0h  
01B1h  
01B2h  
01B3h  
01B4h  
01B5h  
01B6h  
01B7h  
01B8h  
01B9h  
01BAh  
01BBh  
01BCh  
01BDh  
01BEh  
01BFh  
Register  
Symbol  
After reset  
Flash Memory Control Register 4  
Flash Memory Control Register1  
Flash Memory Control Register 0  
FMR4  
FMR1  
FMR0  
01000000b  
1000000Xb  
00000001b  
FFFFh  
Option Function Select Register  
OFS  
(Note 2)  
X: Undefined  
NOTES:  
1. The blank regions are reserved. Do not access locations in these regions.  
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.  
Rev.1.00 Dec 14, 2007 Page 23 of 332  
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R8C/2E Group, R8C/2F Group  
5.Resets  
5. Resets  
The following resets are implemented: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset,  
watchdog timer reset, and software reset.  
Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows the Block Diagram of Reset Circuit.  
Table 5.1  
Reset Names and Sources  
Reset Name  
Source  
Hardware reset  
Input voltage of RESET pin is held “L”  
VCC rises  
Power-on reset  
Voltage monitor 1 reset  
Voltage monitor 2 reset  
Watchdog timer reset  
Software reset  
VCC falls (monitor voltage: Vdet1)  
VCC falls (monitor voltage: Vdet2)  
Underflow of watchdog timer  
Write 1 to PM03 bit in PM0 register  
Hardware reset  
RESET  
SFRs  
b5 bit in VCA2  
register  
Power-on reset  
Power-on reset  
VCC  
circuit  
Voltage monitor 1 reset  
SFRs  
Voltage  
detection  
circuit  
Bits VCA13, VCA26, VCA27,  
VW1C2, VW1C3,  
VW2C2, VW2C3  
Voltage monitor 2  
reset  
Watchdog timer  
reset  
Watchdog  
timer  
Pin, CPU, and  
SFR bits other than  
those listed above  
CPU  
Software reset  
VCA13: Bit in VCA1 register  
VCA26, VCA27: Bits in VCA2 register  
VW1C2, VW1C3: Bits in VW1C register  
VW2C2, VW2C3: Bits in VW2C register  
Figure 5.1  
Block Diagram of Reset Circuit  
Rev.1.00 Dec 14, 2007 Page 24 of 332  
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5.Resets  
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after  
Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.  
Table 5.2  
Pin Functions while RESET Pin Level is “L”  
Pin Name Pin Functions  
P0, P1  
Input port  
Input port  
Input port  
Input port  
P3_1, P3_3 to P3_7  
P4_2, P4_5 to P4_7  
P5_3, P5_4  
b15  
b0  
0000h  
0000h  
0000h  
Data register(R0)  
Data register(R1)  
Data register(R2)  
Data register(R3)  
0000h  
0000h  
0000h  
0000h  
Address register(A0)  
Address register(A1)  
Frame base register(FB)  
b19  
b0  
00000h  
Content of addresses 0FFFEh to 0FFFCh  
Interrupt table register(INTB)  
Program counter(PC)  
b15  
b0  
User stack pointer(USP)  
Interrupt stack pointer(ISP)  
Static base register(SB)  
0000h  
0000h  
0000h  
b15  
b0  
b0  
Flag register(FLG)  
0000h  
b15  
b8  
b7  
IPL  
U
I O B S Z D C  
Figure 5.2  
CPU Register Status after Reset  
fOCO-S  
RESET pin  
10 cycles or more are needed(1)  
fOCO-S clock × 32 cycles(2)  
Internal reset  
signal  
Start time of flash memory  
(CPU clock × 14 cycles)  
CPU clock × 28 cycles  
CPU clock  
0FFFCh  
0FFFEh  
Address  
(internal address  
signal)  
Content of reset vector  
0FFFDh  
NOTES:  
1. Hardware reset.  
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal  
reset signal to “H” at the same.  
Figure 5.3  
Reset Sequence  
Rev.1.00 Dec 14, 2007 Page 25 of 332  
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5.Resets  
Option Function Select Register(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
1 0 1  
1
Symbol  
OFS  
Address  
0FFFFh  
When Shipping  
FFh(2)  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Watchdog timer start  
select bit  
0 : Starts w atchdog timer automatically after reset  
1 : Watchdog timer is inactive after reset  
WDTON  
(b1)  
Reserved bit  
Set to 1.  
RW  
RW  
RW  
RW  
RW  
RW  
ROM code protect  
disabled bit  
0 : ROM code protect disabled  
1 : ROMCP1 enabled  
ROMCR  
ROM code protect bit  
0 : ROM code protect enabled  
1 : ROM code protect disabled  
ROMCP1  
(b4)  
Reserved bit  
Set to 1.  
(b5)  
Reserved bit  
Set to 0.  
(b6)  
Reserved bit  
Set to 1.  
Count source protect  
0 : Count source protect mode enabled after reset  
mode after reset select 1 : Count source protect mode disabled after reset  
bit  
CSPROINI  
RW  
NOTES:  
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not  
w rite additions to the OFS register.  
2. If the block including the OFS register is erased, FFh is set to the OFS register.  
Figure 5.4  
OFS Register  
Rev.1.00 Dec 14, 2007 Page 26 of 332  
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R8C/2E Group, R8C/2F Group  
5.Resets  
5.1  
Hardware Reset  
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage  
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions  
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a  
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip  
oscillator clock divided by 8 is automatically selected as the CPU clock.  
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.  
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the  
contents of internal RAM will be undefined.  
Figure 5.5 shows an Example of Hardware Reset Circuit and Operation and Figure 5.6 shows an Example of  
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.  
5.1.1  
When Power Supply is Stable  
(1) Apply “L” to the RESET pin.  
(2) Wait for 10 µs or more.  
(3) Apply “H” to the RESET pin.  
5.1.2  
Power On  
(1) Apply “L” to the RESET pin.  
(2) Let the supply voltage increase until it meets the recommended operating conditions.  
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 21. Electrical  
Characteristics).  
(4) Wait for 10 µs or more.  
(5) Apply “H” to the RESET pin.  
Rev.1.00 Dec 14, 2007 Page 27 of 332  
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R8C/2E Group, R8C/2F Group  
5.Resets  
VCC  
2.2 V  
VCC  
0 V  
RESET  
RESET  
0 V  
0.2 VCC or below  
td(P-R) + 10 µs or more  
NOTE:  
1. Refer to 21. Electrical Characteristics.  
Figure 5.5  
Example of Hardware Reset Circuit and Operation  
5 V  
Supply voltage  
detection circuit  
VCC  
2.2 V  
RESET  
VCC  
0 V  
5 V  
RESET  
0 V  
td(P-R) + 10 µs or more  
Example when  
VCC = 5 V  
NOTE:  
1. Refer to 21. Electrical Characteristics.  
Figure 5.6  
Example of Hardware Reset Circuit (Usage Example of External Supply Voltage  
Detection Circuit) and Operation  
Rev.1.00 Dec 14, 2007 Page 28 of 332  
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5.Resets  
5.2  
Power-On Reset Function  
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while  
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.  
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.  
When the input voltage to the VCC pin reaches the maximum 2.6 V or above, the low-speed on-chip oscillator  
clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held  
“H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by  
8 is automatically selected as the CPU clock after reset.  
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.  
Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.  
VCC  
4.7 kΩ  
(reference)  
RESET  
max. 2.6 V  
max. 2.6 V  
2.2 V  
trth  
trth  
External  
Power VCC  
Vpor2  
Vpor1  
Sampling time(1, 2)  
tw(por1)  
Internal  
reset signal  
(“L” valid)  
1
1
× 32  
× 32  
fOCO-S  
fOCO-S  
NOTES:  
1. Ensure that the voltage is 2.2 V or above during the sampling time.  
2. The sampling time is fOCO-S divided by 1 × 4 cycles.  
3. Refer to 21. Electrical Characteristics.  
Figure 5.7  
Example of Power-On Reset Circuit and Operation  
Rev.1.00 Dec 14, 2007 Page 29 of 332  
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R8C/2E Group, R8C/2F Group  
5.Resets  
5.3  
Voltage Monitor 1 Reset  
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input  
voltage to the VCC pin. The voltage to monitor is Vdet1.  
When the input voltage to the VCC pin drops the Vdet1 level or below, the pins, CPU, and SFR are reset and a program  
is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator  
clock divided by 8 is automatically selected as the CPU clock.  
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for  
details.  
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while  
writing to the internal RAM is in progress, the contents of internal RAM are undefined.  
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.  
5.4  
Voltage Monitor 2 Reset  
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input  
voltage to the VCC pin. The voltage monitored is Vdet2.  
When the input voltage to the VCC pin drops the Vdet2 level or below, the pins, CPU, and SFR are reset and the  
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip  
oscillator clock divided by 8 is automatically selected as the CPU clock.  
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.  
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while  
writing to the internal RAM is in progress, the contents of internal RAM are undefined.  
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.  
5.5  
Watchdog Timer Reset  
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,  
CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the  
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as  
the CPU clock.  
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.  
The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.  
Refer to 13. Watchdog Timer for details of the watchdog timer.  
5.6  
Software Reset  
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The  
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip  
oscillator clock divided by 8 is automatically selected for the CPU clock.  
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.  
The internal RAM is not reset.  
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6. Voltage Detection Circuit  
6. Voltage Detection Circuit  
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC  
input voltage by a program. Alternately, voltage monitor 1 interrupt, voltage monitor 1 reset, voltage monitor 2  
interrupt, and voltage monitor 2 reset can also be used.  
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.3 show the Block Diagrams. Figures  
6.4 to 6.6 show the Associated Registers.  
Table 6.1  
Specifications of Voltage Detection Circuit  
Item Voltage Detection 1  
VCC Monitor Voltage to monitor Vdet1  
Voltage Detection 2  
Vdet2  
Detection target  
Passing through Vdet1 by rising or  
falling  
Passing through Vdet2 by rising or  
falling  
Monitor  
VW1C3 bit in VW1C register  
VCA13 bit in VCA1 register  
Whether VCC is higher or lower than  
Vdet1  
Whether VCC is higher or lower than  
Vdet2  
Process  
Reset  
Voltage monitor 1 reset  
Voltage monitor 2 reset  
When Voltage  
is Detected  
Reset at Vdet1 > VCC; restart CPU  
operation after a specified time  
Reset at Vdet2 > VCC; restart CPU  
operation after a specified time  
Interrupt  
Voltage monitor 1 interrupt  
Voltage monitor 2 interrupt  
Interrupt request at Vdet1 > VCC and Interrupt request at Vdet2 > VCC and  
VCC > Vdet1 when digital filter is  
enabled;  
VCC > Vdet2 when digital filter is  
enabled;  
interrupt request at Vdet1 > VCC or  
VCC > Vdet1 when digital filter is  
disabled  
interrupt request at Vdet2 > VCC or  
VCC > Vdet2 when digital filter is  
disabled  
Digital Filter  
Switch  
Available  
Available  
enabled/disabled  
Sampling time  
(Divide-by-n of fOCO-S) × 4  
n: 1, 2, 4, and 8  
(Divide-by-n of fOCO-S) × 4  
n: 1, 2, 4, and 8  
VCA27  
VCC  
Voltage detection 2  
signal  
Noise  
filter  
+
Internal  
reference  
voltage  
-
Vdet2  
VCA1 register  
b3  
VCA26  
VCA13 bit  
Voltage detection 1  
signal  
Noise  
+
filter  
-
Vdet1  
VW1C register  
b3  
VW1C3 bit  
Figure 6.1  
Block Diagram of Voltage Detection Circuit  
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6. Voltage Detection Circuit  
Voltage monitor 1 interrupt/reset generation circuit  
VW1F1 to VW1F0  
= 00b  
= 01b  
Voltage detection 1 circuit  
VW1C2 bit is set to 0 (not detected) by  
writing 0 by a program.  
When VCA26 bit is set to 0 (voltage  
detection 1 circuit disabled), VW1C2  
bit is set to 0  
= 10b  
= 11b  
fOCO-S  
1/2  
1/2  
1/2  
VCA26  
VW1C1  
VW1C3  
Watchdog  
timer interrupt  
signal  
VCC  
+
-
Digital  
filter  
Noise filter  
(Filter width: 200 ns)  
Voltage  
detection  
1 signal  
Internal  
reference  
voltage  
VW1C2  
Voltage detection 1 signal  
is held “H” when VCA26 bit  
is set to 0 (disabled)  
Voltage monitor 1  
interrupt signal  
Non-maskable  
interrupt signal  
VW1C1  
Oscillation stop  
detection  
interrupt signal  
VW1C7  
VW1C0  
VW1C6  
Voltage monitor 1  
reset signal  
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register  
VCA26: Bit in VCA2 register  
Figure 6.2  
Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit  
Voltage monitor 2 interrupt/reset generation circuit  
VW2F1 to VW2F0  
= 00b  
= 01b  
Voltage detection 2 circuit  
VCA27  
= 10b  
VW2C2 bit is set to 0 (not detected) by  
writing 0 by a program.  
When VCA27 bit is set to 0 (voltage  
detection 2 circuit disabled), VW2C2  
bit is set to 0  
= 11b  
fOCO-S  
VCA13  
1/2  
1/2  
1/2  
VW2C1  
Watchdog  
timer interrupt  
signal  
VCC  
+
-
Digital  
filter  
Noise filter  
Voltage  
detection  
2 signal  
Internal  
reference  
voltage  
VW2C2  
(Filter width: 200 ns)  
Voltage detection 2 signal  
is held “H” when VCA27 bit  
is set to 0 (disabled)  
Voltage monitor 2  
interrupt signal  
Non-maskable  
interrupt signal  
VW2C1  
Oscillation stop  
detection  
interrupt signal  
Watchdog timer block  
VW2C3  
VW2C7  
Watchdog timer  
underflow signal  
VW2C0  
VW2C6  
This bit is set to 0 (not detected) by writing  
by a program.  
0
Voltage monitor 2  
reset signal  
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register  
VCA13: Bit in VCA1 register  
VCA27: Bit in VCA2 register  
Figure 6.3  
Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit  
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6. Voltage Detection Circuit  
Voltage Detection Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0 0  
0 0 0  
Symbol  
Address  
0031h  
After Reset(2)  
00001000b  
Function  
VCA1  
Bit Symbol  
Bit Name  
RW  
RW  
Reserved bits  
Set to 0.  
(b2-b0)  
Voltage detection 2 signal monitor  
flag(1)  
0 : VCC < Vdet2  
1 : VCC Vdet2 or voltage detection 2  
VCA13  
RO  
circuit disabled  
(b7-b4)  
Reserved bits  
Set to 0.  
RW  
NOTES:  
1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).  
The VCA13 bit is set to 1 (VCC Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2  
circuit disabled).  
2. The softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this  
register.  
Voltage Detection Register 2(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
1 0 0 0 0  
Symbol  
VCA2  
Bit Symbol  
Address  
0032h  
Bit Name  
After Reset(4)  
Pow er-on reset or hardw are reset : 00100000b  
Function  
RW  
RW  
Internal pow er low  
consumption enable bit(5)  
0 : Disables low consumption  
1 : Enables low consumption  
VCA20  
(b4-b1)  
Reserved bits  
Set to 0.  
RW  
RW  
RW  
RW  
(b5)  
Reserved bit  
Set to 1.  
Voltage detection 1 enable 0 : Voltage detection 1 circuit disabled  
bit(2)  
1 : Voltage detection 1 circuit enabled  
Voltage detection 2 enable 0 : Voltage detection 2 circuit disabled  
bit(3)  
1 : Voltage detection 2 circuit enabled  
VCA26  
VCA27  
NOTES:  
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.  
2. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.  
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting  
operation.  
3. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.  
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting  
operation.  
4. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this  
register.  
5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in  
Figure  
.
10.8 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit  
Figure 6.4  
Registers VCA1 and VCA2  
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6. Voltage Detection Circuit  
Voltage Monitor 1 Circuit Control Register (1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
VW1C  
Address  
After Reset(8)  
0036h  
00001000b  
Function  
Bit Symbol  
Bit Name  
RW  
RW  
Voltage monitor 1 interrupt/reset 0 : Disable  
VW1C0  
VW1C1  
enable bit(6)  
1 : Enable  
Voltage monitor 1 digital filter  
disable mode select bit(2)  
0 : Digital filter enabled mode  
(digital filter circuit enabled)  
1 : Digital filter disabled mode  
(digital filter circuit disabled)  
RW  
Voltage change detection  
flag(3, 4, 8)  
0 : Not detected  
1 : Vdet1 pass detected  
VW1C2  
VW1C3  
RW  
RO  
Voltage detection 1 signal  
monitor flag(3, 8)  
0 : VCC < Vdet1  
1 : VCC Vdet1 or voltage detection 1  
circuit disabled  
Sampling clock select bits  
b5 b4  
VW1F0  
RW  
0 0 : fOCO-S divided by 1  
0 1 : fOCO-S divided by 2  
1 0 : fOCO-S divided by 4  
1 1 : fOCO-S divided by 8  
VW1F1  
VW1C6  
RW  
RW  
Voltage monitor 1 circuit mode 0 : Voltage monitor 1 interrupt mode  
select bit(5)  
1 : Voltage monitor 1 reset mode  
Voltage monitor 1 interrupt/reset 0 : When VCC reaches Vdet1 or above  
generation condition select  
bit(7,9)  
1 : When VCC reaches Vdet1 or below  
VW1C7  
RW  
NOTES:  
1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.  
2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting  
1.  
3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit  
enabled).  
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is  
w ritten to it).  
5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset).  
6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).  
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).  
7. The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).  
8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or  
voltage monitor 2 reset.  
9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or  
below ). (Do not set to 0.)  
Figure 6.5  
VW1C Register  
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6. Voltage Detection Circuit  
Voltage Monitor 2 Circuit Control Register (1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
VW2C  
Address  
0037h  
After Reset(8)  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Voltage monitor 2 interrupt/reset 0 : Disable  
VW2C0  
VW2C1  
enable bit(6)  
1 : Enable  
Voltage monitor 2 digital filter  
disable mode select bit(2)  
0 : Digital filter enabled mode  
(digital filter circuit enabled)  
1 : Digital filter disabled mode  
(digital filter circuit disabled)  
RW  
Voltage change detection  
flag(3,4,8)  
WDT detection flag(4,8)  
0 : Not detected  
1 : VCC has crossed Vdet2  
VW2C2  
VW2C3  
RW  
RW  
0 : Not detected  
1 : Detected  
Sampling clock select bits  
b5 b4  
VW2F0  
RW  
0 0 : fOCO-S divided by 1  
0 1 : fOCO-S divided by 2  
1 0 : fOCO-S divided by 4  
1 1 : fOCO-S divided by 8  
VW2F1  
VW2C6  
RW  
RW  
Voltage monitor 2 circuit mode 0 : Voltage monitor 2 interrupt mode  
select bit(5)  
1 : Voltage monitor 2 reset mode  
Voltage monitor 2 interrupt/reset 0 : When VCC reaches Vdet2 or above  
generation condition select  
bit(7,9)  
1 : When VCC reaches Vdet2 or below  
VW2C7  
RW  
NOTES:  
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW2C register.  
2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1  
bit before w riting 1.  
3. The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit  
enabled).  
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is  
w ritten to it).  
5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset).  
6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit  
enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).  
7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).  
8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or  
voltage monitor 2 reset.  
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or  
below ). (Do not set to 0.)  
Figure 6.6  
VW2C Register  
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6. Voltage Detection Circuit  
6.1  
6.1.1  
VCC Input Voltage  
Monitoring Vdet1  
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed  
(refer to 21. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register.  
6.1.2  
Monitoring Vdet2  
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed  
(refer to 21. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.  
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6. Voltage Detection Circuit  
6.2  
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset  
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.7  
shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation. To use the voltage  
monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1  
(digital filter disabled).  
Table 6.2  
Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset  
When Using Digital Filter When Not Using Digital Filter  
Voltage Monitor 1 Voltage Monitor 1  
Interrupt Reset  
Step  
Voltage Monitor 1  
Interrupt  
Voltage Monitor 1  
Reset  
1
2
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)  
Wait for td(E-A)  
Select the sampling clock of the digital filter Select the timing of the interrupt and reset  
by the VW1F0 to VW1F1 bits in the VW1C  
register  
request by the VW1C7 bit in the VW1C  
3
(1)  
register  
Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1  
(digital filter enabled) (digital filter disabled)  
(2)  
4
(2)  
Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in  
the VW1C register to the VW1C register to the VW1C register to the VW1C register to  
0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1  
5
interrupt mode)  
reset mode)  
interrupt mode)  
reset mode)  
6
7
Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected)  
Set the CM14 bit in the CM1 register to 0  
(low-speed on-chip oscillator on)  
8
Wait for 4 cycles of the sampling clock of the (No wait time required)  
digital filter  
9
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)  
NOTES:  
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.  
2. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1  
instruction).  
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6. Voltage Detection Circuit  
VCC  
Vdet1  
1
0
VW1C3 bit  
4 cycles of sampling clock of  
digital filter  
4 cycles of sampling clock of  
digital filter  
1
0
VW1C2 bit  
Set to 0 by a program  
When VW1C1 bit is set to 0  
(digital filter enabled)  
Set to 0 by interrupt request  
acknowledgement  
Voltage monitor 1  
interrupt request  
(VW1C6 = 0)  
Internal reset signal  
(VW1C6 = 1)  
Set to 0 by a program  
1
0
VW1C2 bit  
When VW1C1 bit is set to 1  
(digital filter disabled) and  
VW1C7 bit is set to 0  
(Vdet1 or above)  
Set to 0 by interrupt  
request  
acknowledgement  
Voltage monitor 1  
interrupt request  
(VW1C6 = 0)  
Set to 0 by a program  
1
0
VW1C2 bit  
Set to 0 by interrupt  
When VW1C1 bit is set to 1  
(digital filter disabled) and  
VW1C7 bit is set to 1  
(Vdet1 or below)  
request acknowledgement  
Voltage monitor 1  
interrupt request  
(VW1C6 = 0)  
Internal reset signal  
(VW1C6 = 1)  
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register  
The above applies under the following conditions.  
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)  
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)  
Figure 6.7  
Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation  
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6. Voltage Detection Circuit  
6.3  
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset  
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.8  
shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage  
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1  
(digital filter disabled).  
Table 6.3  
Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset  
When Using Digital Filter When Not Using Digital Filter  
Voltage Monitor 2 Voltage Monitor 2  
Interrupt Reset  
Step  
Voltage Monitor 2  
Interrupt  
Voltage Monitor 2  
Reset  
1
2
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)  
Wait for td(E-A)  
Select the sampling clock of the digital filter Select the timing of the interrupt and reset  
by the VW2F0 to VW2F1 bits in the VW2C  
register  
request by the VW2C7 bit in the VW2C  
3
(1)  
register  
Set the VW2C1 bit in the VW2C register to 0 Set the VW2C1 bit in the VW2C register to 1  
(digital filter enabled) (digital filter disabled)  
4
(2)  
Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in  
the VW2C register to the VW2C register to the VW2C register to the VW2C register to  
0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2  
5
interrupt mode)  
reset mode)  
interrupt mode)  
reset mode)  
6
7
Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)  
Set the CM14 bit in the CM1 register to 0  
(low-speed on-chip oscillator on)  
8
Wait for 4 cycles of the sampling clock of the (No wait time required)  
digital filter  
9
Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)  
NOTES:  
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.  
2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1  
instruction).  
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6. Voltage Detection Circuit  
VCC  
Vdet2  
1
0
VCA13 bit  
VW2C2 bit  
4 cycles of sampling clock of  
digital filter  
4 cycles of sampling clock of  
digital filter  
1
0
Set to 0 by a program  
When VW2C1 bit is set to 0  
(digital filter enabled)  
Set to 0 by interrupt request  
acknowledgement  
Voltage monitor 2  
interrupt request  
(VW2C6 = 0)  
Internal reset signal  
(VW2C6 = 1)  
Set to 0 by a program  
1
0
VW2C2 bit  
When VW2C1 bit is set to 1  
(digital filter disabled) and  
VW2C7 bit is set to 0  
(Vdet2 or above)  
Set to 0 by interrupt  
request  
acknowledgement  
Voltage monitor 2  
interrupt request  
(VW2C6 = 0)  
Set to 0 by a program  
1
0
VW2C2 bit  
Set to 0 by interrupt  
When VW2C1 bit is set to 1  
(digital filter disabled) and  
VW2C7 bit is set to 1  
(Vdet2 or below)  
request acknowledgement  
Voltage monitor 2  
interrupt request  
(VW2C6 = 0)  
Internal reset signal  
(VW2C6 = 1)  
VCA13: Bit in VCA1 register  
VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register  
The above applies under the following conditions.  
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)  
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)  
Figure 6.8  
Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation  
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7. Programmable I/O Ports  
7. Programmable I/O Ports  
There are 25 programmable Input/Output ports (I/O ports) P0, P1, P3_1, P3_3 to P3_7, P4_5, P5_3, and P5_4. Also,  
P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the P4_2 can be used  
as an input-only port if the A/D converter is not used.  
Table 7.1 lists an Overview of Programmable I/O Ports.  
Table 7.1  
Overview of Programmable I/O Ports  
I/O Type of Output  
I/O CMOS3 State  
P3_1, P3_3 to P3_7 I/O CMOS3 State  
Ports  
I/O Setting  
Set per bit  
Internal Pull-Up Resister  
(1)  
P0, P1  
Set every 4 bits  
(1)  
Set per bit  
Set per bit  
Set per bit  
Set every 2 bits, 4 bits  
(1)  
P4_5  
I/O CMOS3 State  
I/O CMOS3 State  
Set every bit  
(1)  
P5_3, P5_4  
Set every bit  
(2)  
P4_2  
I
(No output function)  
None  
None  
(3)  
P4_6, P4_7  
NOTES:  
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers  
PUR0 and PUR1.  
2. When the A/D converter is not used, this port can be used as the input-only port.  
3. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports.  
7.1  
Functions of Programmable I/O Ports  
The PDi_j (j = 0 to 7) bit in the PDi (i = 0, 1, 3 to 5) register controls I/O of the ports P0, P1, P3_1, P3_3 to P3_7,  
P4_5, P5_3, and P5_4. The Pi register consists of a port latch to hold output data and a circuit to read pin states.  
Figures 7.1 to 7.5 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of  
Programmable I/O Ports. Also, Figure 7.7 shows the PDi (i = 0, 1, and 3 to 5) Register. Figure 7.8 shows the Pi (i =  
0, 1, and 3 to 5) Register, Figure 7.9 shows Registers PINSR2 and PINSR3, Figure 7.10 shows the PMR Register,  
Figure 7.11 shows Registers PUR0 and PUR1, and Figure 7.12 shows the P1DRR Register.  
Table 7.2  
Functions of Programmable I/O Ports  
(1)  
Operation When  
Accessing  
Pi Register  
Reading  
Value of PDi_j Bit in PDi Register  
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)  
Read pin input level  
Write to the port latch  
Read the port latch  
Write to the port latch. The value written to  
the port latch is output from the pin.  
Writing  
i = 0, 1, 3 to 5 j = 0 to 7  
NOTE:  
1. Nothing is assigned to bits PD3_0, PD3_2, PD4_0 to PD4_4, PD4_6, and PD4_7.  
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7. Programmable I/O Ports  
7.2  
Effect on Peripheral Functions  
Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.7 Pin Name Information  
by Pin Number).  
Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0, 1, 3 to 5 j = 0  
to 7). Refer to the description of each function for information on how to set peripheral functions.  
Table 7.3  
Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0, 1, 3 to 5 j = 0 to 7)  
I/O of Peripheral Functions  
PDi_j Bit Settings for Shared Pin Functions  
Set this bit to 0 (input mode).  
This bit can be set to either 0 or 1 (output regardless of the port setting)  
Input  
Output  
7.3  
Pins Other than Programmable I/O Ports  
Figure 7.6 shows the Configuration of I/O Pins.  
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7. Programmable I/O Ports  
P0  
Pull-up selection  
Direction  
register  
(Note 1)  
(Note 1)  
Data bus  
Port latch  
Analog input  
Pull-up selection  
1
Drive capacity select  
P1_0 to P1_3  
Direction  
register  
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Input to individual peripheral function  
Analog input  
Drive capacity select  
Drive capacity select  
P1_4  
Pull-up selection  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Drive capacity select  
NOTE:  
1.  
symbolizes a parasitic diode.  
Ensure the input voltage to each port does not exceed VCC.  
Figure 7.1  
Configuration of Programmable I/O Ports (1)  
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7. Programmable I/O Ports  
Drive capacity select  
P1_5 and P1_7  
Pull-up selection  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Digital  
filter  
Input to external interrupt  
Input to individual peripheral function  
Drive capacity select  
Drive capacity select  
P1_6  
Pull-up selection  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Input to individual peripheral function  
Drive capacity select  
NOTE:  
1.  
symbolizes a parasitic diode.  
Ensure the input voltage to each port does not exceed VCC.  
Figure 7.2  
Configuration of Programmable I/O Ports (2)  
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7. Programmable I/O Ports  
P3_1  
Pull-up selection  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Pull-up selection  
P3_3 and P3_6  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Input to individual peripheral function  
Input to external interrupt  
Digital  
filter  
P3_4, P3_5, and P3_7  
Pull-up selection  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Input to individual peripheral function  
NOTE:  
1.  
symbolizes a parasitic diode.  
Ensure the input voltage to each port does not exceed VCC.  
Figure 7.3  
Configuration of Programmable I/O Ports (3)  
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7. Programmable I/O Ports  
(Note 1)  
P4_2/VREF  
Data bus  
(Note 1)  
Pull-up selection  
P4_5  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Input to individual peripheral function  
Input to external interrupt  
Digital  
filter  
P4_6/XIN  
(Note 1)  
(Note 1)  
Data bus  
CM13  
XIN  
oscillation  
circuit  
CM05  
CM11  
RfXIN  
P4_7/XOUT  
(Note 2)  
(Note 1)  
(Note 1)  
Data bus  
NOTES:  
1.  
symbolizes a parasitic diode.  
Ensure the input voltage to each port does not exceed VCC.  
2. This pin is pulled up in one of the following conditions:  
• CM05 = CM13 = 1  
• CM10 = CM13 = 1  
• CM10 = 1  
CM05: Bit in CM0 register  
CM10, CM13: Bits in CM1 register  
Figure 7.4  
Configuration of Programmable I/O Ports (4)  
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7. Programmable I/O Ports  
P5_3 and P5_4  
Pull-up selection  
Direction  
register  
1
(Note 1)  
(Note 1)  
Output from individual peripheral function  
Port latch  
Data bus  
Input to individual peripheral function  
NOTE:  
1.  
symbolizes a parasitic diode.  
Ensure the input voltage to each port does not exceed VCC.  
Figure 7.5  
Configuration of Programmable I/O Ports (5)  
MODE  
MODE signal input  
(Note 1)  
RESET  
RESET signal input  
(Note 1)  
NOTE:  
1.  
symbolizes a parasitic diode.  
Ensure the input voltage to each port does not exceed VCC.  
Figure 7.6  
Configuration of I/O Pins  
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7. Programmable I/O Ports  
Port Pi Direction Register (i = 0, 1, 3 to 5)(1, 2, 3, 4)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
PD0  
Address  
00E2h  
After Reset  
00h  
00h  
00E3h  
PD1  
00E7h  
00h  
PD3  
00EAh  
00EBh  
Bit Name  
00h  
PD4  
00h  
PD5  
Bit Symbol  
PDi_0  
PDi_1  
PDi_2  
PDi_3  
PDi_4  
PDi_5  
PDi_6  
PDi_7  
Function  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Port Pi_0 direc tion bit  
0 : Input mode  
(functions as an input port)  
1 : Output mode  
(functions as an output port)  
Port Pi_1 direc tion bit  
Port Pi_2 direc tion bit  
Port Pi_3 direction bit  
Port Pi_4 direc tion bit  
Port Pi_5 direc tion bit  
Port Pi_6 direc tion bit  
Port Pi_7 direction bit  
NOTES:  
1. Set the PD0 register by using the next instruction after setting the PRC2 bit in the PRCR register to 1 (w rite enable).  
2. Bits PD3_0 and PD3_2 in the PD3 register are unavailable on this MCU.  
If it is necessary to set bits PD3_0 and PD3_2, set to 0 (input mode). When read, the content is 0.  
3. Bits PD4_0, PD4_1, PD4_3, PD4_4, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.  
If it is necessary to set bits D4_0, PD4_1, PD4_3, PD4_4, PD4_6, and PD4_7, set to 0 (input mode). When read, the  
content is 0.  
4. Bits PD5_0 to PD5_2 and PD5_5 to PD5_7 in the PD5 register are unavailable on this MCU.  
If it is necessary to set bits PD5_0 to PD5_2 and PD5_5 to PD5_7, set to 0 (input mode). When read, the content is 0.  
Figure 7.7  
PDi (i = 0, 1, and 3 to 5) Register  
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7. Programmable I/O Ports  
Port Pi Register (i = 0, 1, 3 to 5)(1, 2, 3)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
Address  
00E0h  
After Reset  
00h  
00h  
P0  
00E1h  
P1  
P3  
00E5h  
00h  
00E8h  
00h  
P4  
00E9h  
00h  
P5  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Pi_0  
Pi_1  
Pi_2  
Pi_3  
Pi_4  
Pi_5  
Pi_6  
Port Pi_0 bit  
The pin level of any I/O port w hich is set  
to input mode can be read by reading the  
corresponding bit in this register. The pin  
level of any I/O port w hich is set to output  
mode can be controlled by w riting to the  
corresponding bit in this register.  
0 : “L” level  
Port Pi_1 bit  
Port Pi_2 bit  
Port Pi_3 bit  
Port Pi_4 bit  
Port Pi_5 bit  
Port Pi_6 bit  
Port Pi_7 bit  
1 : “H” level  
Pi_7  
RW  
NOTES:  
1. Bits P3_0 and P3_2 in the P3 register are unavailable on this MCU.  
If it is necessary to set bits P3_0 and P3_2, set to 0 (“L” level). When read, the content is 0.  
2. Bits P4_0 to P4_4, P4_6, and P4_7 in the P4 register are unavailable on this MCU.  
If it is necessary to set bits P4_0 to P4_4, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0.  
3. Bits P5_0 to P5_2, P5_5 to P5_7 in the P5 register are unavailable on this MCU.  
If it is necessary to set bits P5_0 to P5_2, P5_5 to P5_7, set to 0 (“L” level). When read, the content is 0.  
Figure 7.8  
Pi (i = 0, 1, and 3 to 5) Register  
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7. Programmable I/O Ports  
Pin Select Register 2  
b7 b6 b5 b4 b3 b2 b1 b0  
0
0 0 0 0 0 0  
Symbol  
Address  
00F6h  
After Reset  
00h  
Function  
PINSR2  
Bit Symbol  
Bit Name  
RW  
RW  
Reserved bits  
Set to 0. When read, the content is 0.  
(b5-b0)  
TRBO pin select bit  
Reserved bit  
0 : P3_1  
1 : P1_3  
TRBOSEL  
RW  
RW  
(b7)  
Set to 0. When read, the content is 0.  
Pin Select Register 3  
b7 b6 b5 b4 b3 b2 b1 b0  
1
1 1 1  
Symbol  
Address  
00F7h  
After Reset  
00h  
Function  
PINSR3  
Bit Symbol  
Bit Name  
Reserved bits  
RW  
RW  
Set to 1. When read, the content is 0.  
(b2-b0)  
TRCIOC pin select bit  
TRCIOD pin select bit  
Reserved bit  
0 : P5_3  
1 : P3_4  
TRCIOCSEL  
TRCIODSEL  
RW  
RW  
RW  
0 : P5_4  
1 : P3_5  
(b5)  
Set to 1. When read, the content is 0.  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 7.9  
Registers PINSR2 and PINSR3  
Port Mode Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0  
Symbol  
PMR  
Address  
00F8h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
___  
0 : P1_5, P1_7  
1 : P3_6  
INT1 pin select bit  
INT1SEL  
(b3-b1)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
RW  
(b6-b4)  
Reserved bits  
Set to 0.  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 7.10  
PMR Register  
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Pull-Up Control Register 0  
7. Programmable I/O Ports  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
00FCh  
After Reset  
00h  
PUR0  
Bit Symbol  
PU00  
Bit Name  
Function  
RW  
RW  
RW  
RW  
RW  
P0_0 to P0_3 pull-up(1)  
P0_4 to P0_7 pull-up(1)  
P1_0 to P1_3 pull-up(1)  
P1_4 to P1_7 pull-up(1)  
Reserved bits  
0 : Not pulled up  
1 : Pulled up  
PU01  
PU02  
PU03  
Set to 0. When read, the content is 0.  
RW  
(b5-b4)  
PU06  
PU07  
P3_1 and P3_3 pull-up(1)  
P3_4 to P3_7 pull-up(1)  
0 : Not pulled up  
1 : Pulled up  
RW  
RW  
NOTE:  
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.  
Pull-Up Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
0
Symbol  
PUR1  
Bit Symbol  
Address  
00FDh  
After Reset  
00h  
Function  
Bit Name  
RW  
RW  
(b0)  
Reserved bit  
Set to 0. When read, the content is 0.  
PU11  
PU12  
PU13  
P4_5 pull-up(1)  
P5_3 pull-up(1)  
P5_4 pull-up(1)  
Reserved bits  
0 : Not pulled up  
1 : Pulled up  
RW  
RW  
RW  
(b5-b4)  
Set to 0. When read, the content is 0.  
RW  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.  
Figure 7.11  
Registers PUR0 and PUR1  
Port P1 Drive Capacity Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
P1DRR  
Address  
00FEh  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
P1DRR0 P1_0 drive capacity  
P1DRR1 P1_1 drive capacity  
P1DRR2 P1_2 drive capacity  
P1DRR3 P1_3 drive capacity  
P1DRR4 P1_4 drive capacity  
P1DRR5 P1_5 drive capacity  
P1DRR6 P1_6 drive capacity  
P1DRR7 P1_7 drive capacity  
Set P1 output transistor drive capacity  
0 : Low  
1 : High(1)  
NOTE:  
1. Both “H” and “L” output are set to high drive capacity.  
Figure 7.12  
P1DRR Register  
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7. Programmable I/O Ports  
7.4  
Port Setting  
Table 7.4 to Table 7.39 list the port setting.  
Table 7.4  
Port P0_0/AN7  
Register  
Bit  
PD0  
ADCON0  
CH1 CH0  
Function  
PD0_0  
CH2  
ADGSEL0  
0
Input port(1)  
Output port  
0
1
0
Other than 1110b  
Other than 1110b  
Setting  
value  
1
1
1
A/D converter input (AN7)  
NOTE:  
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.  
Table 7.5  
Port P0_1/AN6  
Register  
Bit  
PD0  
ADCON0  
Function  
PD0_1  
CH2  
X
CH1  
X
CH0  
X
ADGSEL0  
Input port(1)  
0
1
0
X
X
0
Setting  
value  
X
X
X
Output port  
1
1
0
A/D converter input (AN6)  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.  
Table 7.6  
Port P0_2/AN5/ACMP1  
Register  
Bit  
PD0  
ADCON0  
ACCR1  
CM1E  
Function  
PD0_2  
CH2  
X
CH1  
X
CH0  
X
ADGSEL0  
Input port(1)  
Output port  
0
1
0
0
X
X
0
0
0
0
1
X
X
X
Setting  
value  
1
0
1
A/D converter input (AN5)  
ACMP1 input  
X
X
X
X
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.  
Table 7.7  
Port P0_3/AN4/AVREF1  
Register  
Bit  
PD0  
ADCON0  
ACCR1  
Function  
PD0_3  
CH2  
X
CH1  
X
CH0  
X
ADGSEL0  
CM1E  
VR1SEL  
Input port(1)  
Output port  
0
1
X
X
0
0
0
1
1
X
X
X
1
X
X
X
Setting  
value  
0
0
1
0
0
0
A/D converter input (AN4)  
AVREF1 input  
X
X
X
X
0
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.  
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7. Programmable I/O Ports  
Table 7.8  
Port P0_4/AN3/TREO/ACMP0  
Register  
Bit  
PD0  
TRECR1  
ADCON0  
CH1  
ACCR0  
Function  
PD0_4  
TOENA  
CH2  
X
CH0  
X
ADGSEL0  
CM0E  
Input port(1)  
0
1
0
X
0
0
0
0
1
0
X
X
1
X
X
0
0
0
0
0
1
X
X
Output port  
Setting  
value  
0
1
A/D converter input (AN3)  
TREO output  
X
X
X
X
X
X
X
X
ACMP0 input  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.  
Table 7.9  
Port P0_5/AN2/AVREF0  
Register  
Bit  
PD0  
ADCON0  
ACCR0  
Function  
PD0_5  
CH2  
X
CH1  
X
CH0  
X
ADGSEL0  
CM0E  
VR0SEL  
X
X
X
0
0
0
0
1
1
X
X
X
X
1
Input port(1)  
0
1
0
0
X
X
X
X
X
X
Output port  
Setting  
value  
0
1
0
0
A/D converter input (AN2)  
AVREF0 input  
X
X
X
X
0
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.  
Table 7.10  
Port P0_6/AN1/DA0  
Register  
Bit  
PD0  
ADCON0  
CH1  
DACON  
ACCR0  
Function  
Input port(1)  
PD0_6  
CH2  
X
CH0  
X
ADGSEL0  
X
DA0E  
VR0SEL  
0
1
0
1
0
1
1
X
1
X
1
X
1
0
0
X
X
1
X
X
X
Output port  
Setting  
value  
0
0
0
0
1
0
A/D converter input (AN1)  
DA0 output  
X
X
X
X
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.  
Table 7.11  
Port P0_7/AN0/DA1  
Register  
Bit  
PD0  
ADCON0  
CH1  
DACON  
ACCR1  
Function  
Input port(1)  
PD0_7  
CH2  
X
CH0  
X
ADGSEL0  
X
DA1E  
VR1SEL  
0
1
0
1
0
1
1
X
1
X
1
X
1
0
0
X
X
1
X
X
X
Output port  
Setting  
value  
0
0
0
0
0
0
A/D converter input (AN0)  
DA1 output  
X
X
X
X
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.  
Rev.1.00 Dec 14, 2007 Page 53 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.12  
Port P1_0/KI0/AN8  
Register  
Bit  
PD1  
KIEN  
ADCON0  
Function  
PD1_0  
KI0EN  
CH2  
X
CH1  
CH0  
X
ADGSEL0  
Input port(1)  
Output port  
0
1
0
0
X
X
X
0
X
X
X
1
X
X
Setting  
value  
KI0 input(1)  
0
0
1
0
X
X
1
0
A/D converter input (AN8)  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.  
Table 7.13  
Port P1_1/KI1/AN9/TRCIOA/TRCTRG  
Register  
Bit  
PD1  
KIEN  
Timer RC Setting  
ADCON0  
CH2 CH1 CH0 ADGSEL0  
Function  
Input port(1)  
PD1_1 KI1EN  
0
1
0
0
0
0
Other than TRCIOA usage conditions  
Other than TRCIOA usage conditions  
Other than TRCIOA usage conditions  
X
X
1
X
X
0
X
X
1
X
X
1
Output port  
A/D converter input (AN9)  
Setting  
value  
KI1 input(1)  
0
1
Other than TRCIOA usage conditions  
X
X
X
X
Refer to Table 7.14 TRCIOA Pin  
X
0
X
X
X
X
TRCIOA output  
Setting  
Refer to Table 7.14 TRCIOA Pin  
TRCIOA input(1)  
0
0
X
X
X
X
Setting  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.  
Table 7.14  
TRCIOA Pin Setting  
Register  
Bit  
TRCOER TRCMR  
TRCIOR0  
TRCCR2  
Function  
EA  
PWM2  
IOA2  
IOA1  
IOA0  
TCEG1  
TCEG2  
0
0
0
1
1
X
X
X
X
0
X
X
X
X
1
Timer waveform output  
(output compare function)  
0
1
X
0
1
0
1
1
0
1
X
X
X
Timer mode (input capture function)  
Setting  
value  
X
X
PWM2 mode TRCTRG input  
1
X
Other than above  
Other than TRCIOA usage conditions  
X: 0 or 1  
Rev.1.00 Dec 14, 2007 Page 54 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.15  
Port P1_2/KI2/AN10/TRCIOB  
Register  
Bit  
PD1  
KIEN  
Timer RC Setting  
ADCON0  
Function  
PD1_2 KI2EN  
CH2 CH1 CH0 ADGSEL0  
Input port(1)  
0
1
0
0
0
0
Other than TRCIOB usage conditions  
Other than TRCIOB usage conditions  
Other than TRCIOB usage conditions  
X
X
1
X
X
1
X
X
0
X
X
1
Output port  
A/D converter input (AN10)  
Setting  
value  
KI2 input(1)  
0
1
Other than TRCIOB usage conditions  
X
X
X
X
Refer to Table 7.16 TRCIOB Pin  
X
0
X
X
X
X
TRCIOB output  
Setting  
Refer to Table 7.16 TRCIOB Pin  
TRCIOB input(1)  
0
0
X
X
X
X
Setting  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.  
Table 7.16  
TRCIOB Pin Setting  
Register  
Bit  
TRCOER  
TRCMR  
TRCIOR0  
Function  
EB  
0
PWM2  
PWMB  
IOB2  
IOB1  
IOB0  
0
1
X
1
X
X
0
X
X
0
X
X
1
PWM2 mode waveform output  
PWM mode waveform output  
0
Timer waveform output (output compare  
function)  
0
1
1
0
0
Setting  
value  
0
1
X
0
1
1
X
X
Timer mode (input capture function)  
Other than TRCIOB usage conditions  
Other than above  
X: 0 or 1  
Table 7.17  
Port P1_3/KI3/AN11/(TRBO)  
Register  
Bit  
PD1  
KIEN  
Timer RB Setting  
ADCON0  
CH2 CH1 CH0 ADGSEL0  
Function  
PD1_3 KI3EN  
Input port(1)  
Output port  
0
1
0
0
0
0
Other than TRBO usage conditions  
Other than TRBO usage conditions  
Other than TRBO usage conditions  
X
X
1
X
X
1
X
X
1
X
X
1
Setting  
value  
A/D converter input (AN11)  
KI3 input  
0
1
0
Other than TRBO usage conditions  
X
X
X
X
X
X
X
X
Refer to Table 7.18 TRBO Pin  
X
TRBO output  
Setting  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.  
Table 7.18  
TRBO Pin Setting  
Register  
Bit  
PINSR2  
TRBIOC  
TRBMR  
Function  
TOCNT(1)  
TRBOSEL  
TMOD1  
TMOD0  
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
1
Programmable waveform generation mode  
Programmable one-shot generation mode  
Programmable wait one-shot generation mode  
Setting  
value  
P1_3 output port  
Other than above  
Other than TRBO usage conditions  
NOTE:  
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.  
Rev.1.00 Dec 14, 2007 Page 55 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.19  
Port P1_4/TXD0  
Register  
Bit  
PD1  
U0MR  
Function  
PD1_4  
SMD2  
SMD1  
SMD0  
Input port(1)  
Output port  
0
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
1
0
Setting  
value  
TXD0 output(2)  
X
X: 0 or 1  
NOTES:  
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.  
2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1.  
Table 7.20  
Port P1_5/RXD0/(TRAIO)/(INT1)  
Register  
Bit  
PD1  
TRAIOC  
TRAMR  
INTEN  
INT1EN  
X
Function  
TOPCR(3)  
PD1_5  
0
TIOSEL  
TMOD2  
TMOD1  
TMOD0  
0
1
1
0
1
0
1
1
1
1
X
1
0
X
0
X
0
0
0
1
X
0
0
X
0
X
X
X
1
0
X
0
X
Input port(1)  
0
0
0
X
X
X
0
0
1
1
0
X
1
Output port  
0
X
Setting  
value  
RXD0 input(1)  
TRAIO input(1)  
INT1(2)  
Other than 001b  
Other than 000b, 001b  
0
0
0
0
0
0
1
TRAIO input/INT1(1, 2)  
TRAIO pulse output  
1
1
0
0
Other than 000b, 001b  
1
X
0
0
1
X
X: 0 or 1  
NOTES:  
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.  
2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7).  
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.  
Table 7.21  
Port P1_6/CLK0  
Register  
Bit  
PD1  
U0MR  
Function  
PD1_6  
CKDIR  
SMD2  
X
SMD1  
X
SMD0  
X
Input port(1)  
0
1
X
0
X
X
0
1
Other than 001b  
Output port  
CLK0 output  
CLK0 input(1)  
Setting  
value  
0
0
1
X
X
X
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.  
Rev.1.00 Dec 14, 2007 Page 56 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.22  
Port P1_7/TRAIO/INT1  
Register  
Bit  
PD1  
TRAIOC  
TRAMR  
INTEN  
Function  
TOPCR(3)  
PD1_7  
TIOSEL  
TMOD2  
TMOD1  
TMOD0  
INT1EN  
1
0
0
1
0
0
0
0
X
1
0
X
0
0
0
1
X
0
0
X
0
X
0
0
X
0
X
1
0
X
0
X
0
0
X
X
0
1
1
Input port(1)  
0
1
Output port  
TRAIO input(1)  
INT1(2)  
Setting  
value  
Other than 000b, 001b  
0
0
0
0
0
0
1
TRAIO input/INT1(1, 2)  
TRAIO pulse output  
0
0
0
0
Other than 000b, 001b  
1
X
0
0
1
X
X: 0 or 1  
NOTES:  
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.  
2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7).  
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.  
Table 7.23  
Port P3_1/TRBO  
Register  
Bit  
PD3  
Timer RB Setting  
Function  
PD3_1  
Input port(1)  
Output port  
TRBO output  
0
1
X
Other than TRBO usage conditions  
Other than TRBO usage conditions  
Refer to Table 7.24 TRBO Pin Setting  
Setting  
value  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.  
Table 7.24  
TRBO Pin Setting  
Register  
Bit  
PINSR2  
TRBIOC  
TOCNT(1)  
TRBMR  
Function  
TRBOSEL  
TMOD1  
TMOD0  
0
0
0
0
0
0
0
1
0
1
1
1
1
0
1
0
Programmable waveform generation mode  
Programmable one-shot generation mode  
Programmable wait one-shot generation mode  
Setting  
value  
P3_1 output port  
Other than above  
Other than TRBO usage conditions  
NOTE:  
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.  
Rev.1.00 Dec 14, 2007 Page 57 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.25  
Port P3_3/INT3/TRCCLK  
Register  
Bit  
PD3  
TRCCR1  
TCK1  
INTEN  
Function  
PD3_3  
TCK2  
TCK0  
INT3EN  
Input port(1)  
0
1
Other than 101b  
Other than 101b  
0
0
Output port  
Setting  
value  
INT3 input(1)  
0
0
Other than 101b  
0
1
0
TRCCLK input(1)  
1
1
NOTE:  
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.  
Table 7.26  
Port P3_4/(TRCIOC)  
Register  
Bit  
PD3  
Timer RC setting  
Function  
PD3_4  
Other than TRCIOC usage conditions  
Other than TRCIOC usage conditions  
Other than TRCIOC usage conditions  
Other than TRCIOC usage conditions  
Refer to Table 7.27 TRCIOC Pin Setting  
Refer to Table 7.27 TRCIOC Pin Setting  
Input port(1)  
0
1
Setting  
value  
Output port  
X
0
TRCIOC output  
TRCIOC input(1)  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.  
Table 7.27  
TRCIOC Pin Setting  
Register  
Bit  
PINSR3  
TRCOER  
TRCMR  
TRCIOR1  
Function  
TRCIOCSEL  
EC  
0
PWM2 PWMC  
IOC2  
IOC1  
IOC0  
1
1
1
1
1
1
1
X
0
0
X
0
1
X
1
PWM mode waveform output  
Timer waveform output (output compare  
function)  
0
1
0
X
Setting  
value  
0
1
1
0
1
X
X
Timer mode (input capture function)  
Other than TRCIOC usage conditions  
Other than above  
X: 0 or 1  
Rev.1.00 Dec 14, 2007 Page 58 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.28  
Port P3_5/(TRCIOD)  
Register  
Bit  
PD3  
Timer RC setting  
Function  
PD3_5  
Input port(1)  
Output port  
0
1
X
0
Other than TRCIOD usage conditions  
Other than TRCIOD usage conditions  
Refer to Table 7.29 TRCIOD Pin Setting  
Refer to Table 7.29 TRCIOD Pin Setting  
Setting  
value  
TRCIOD output  
TRCIOD input(1)  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.  
Table 7.29  
TRCIOD Pin Setting  
Register  
Bit  
PINSR3  
TRCOER  
TRCMR  
TRCIOR1  
Function  
TRCIODSEL  
EC  
0
PWM2  
PWMD  
1
IOD2  
IOD1  
IOD0  
1
1
1
1
1
1
X
0
0
X
0
1
X
1
PWM mode waveform output  
Timer waveform output (output  
compare function)  
0
1
0
0
X
Setting  
value  
0
1
1
1
X
X
Timer mode (input capture function)  
Other than TRCIOD usage conditions  
Other than above  
X: 0 or 1  
Table 7.30  
Port P3_6/(INT1)  
Register  
Bit  
PD3  
INTEN  
Function  
PD3_6  
INT1EN  
Input port(1)  
0
1
0
0
0
1
Setting  
value  
Output port  
INT1 input(1, 2)  
NOTES:  
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.  
2. Set the INT1SEL bit in the PMR register to 1 (P3_6).  
Table 7.31  
Port P3_7/TRAO  
Register  
Bit  
PD3  
TRAMR  
Function  
PD3_7  
TOENA  
Input port(1)  
Output port  
TRAO output  
0
1
X
0
0
1
Setting  
value  
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.  
Rev.1.00 Dec 14, 2007 Page 59 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.32  
Port P4_2/VREF  
Register  
Bit  
ADCON1  
Function  
VCUT  
0
1
Input port  
Input port/VREF input  
Setting  
value  
Table 7.33  
Port P4_5/INT0  
Register  
Bit  
PD4  
INTEN  
Function  
PD4_5  
INT0EN  
Input port(1)  
Output port  
0
1
0
0
1
Setting  
value  
INT0 input(1)  
0
NOTE:  
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.  
Table 7.34  
Port P4_6/XIN  
Register  
Bit  
CM0  
CM1  
CM11  
X
Circuit specifications  
Function  
Oscillation  
buffer  
Feedback  
resistor  
CM05  
1
CM13  
0
CM10  
0
OFF  
Input port  
XIN clock oscillation (on-chip  
feedback resistor enabled)  
0
ON  
ON  
0
XIN clock oscillation (on-chip  
feedback resistor disabled)  
1
0
0
ON  
OFF  
OFF  
OFF  
ON  
Setting  
value  
0
1
External clock input  
1
XIN clock oscillation stop (on-chip  
feedback resistor enabled)  
ON  
1
XIN clock oscillation stop (on-chip  
feedback resistor disabled)  
1
1
OFF  
OFF  
OFF  
OFF  
XIN clock oscillation stop (stop  
mode)  
X: 0 or 1  
Table 7.35  
Register  
Bit  
Port P4_7/XOUT  
CM0  
CM1  
CM11  
X
Circuit specifications  
Function  
Oscillation  
buffer  
Feedback  
resistor  
CM05  
1
CM13  
0
CM10  
0
OFF  
Input port  
XIN clock oscillation (on-chip  
feedback resistor enabled)  
0
ON  
ON  
0
XIN clock oscillation (on-chip  
feedback resistor disabled)  
1
0
0
ON  
OFF  
OFF  
OFF  
ON  
Setting  
value  
0
1
External clock input  
1
XIN clock oscillation stop (on-chip  
feedback resistor enabled)  
ON  
1
XIN clock oscillation stop (on-chip  
feedback resistor disabled)  
1
1
OFF  
OFF  
OFF  
OFF  
XOUT pulled up  
X: 0 or 1  
Rev.1.00 Dec 14, 2007 Page 60 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
Table 7.36  
Port P5_3/TRCIOC/ACOUT0  
Register  
Bit  
PD5  
Timer RC setting  
ACCR0  
Function  
PD5_3  
CM0OE  
Input port(1)  
0
1
Other than TRCIOC usage conditions  
Other than TRCIOC usage conditions  
Refer to Table 7.37 TRCIOC Pin Setting  
Refer to Table 7.37 TRCIOC Pin Setting  
Other than TRCIOC usage conditions  
0
0
0
0
1
Output port  
Setting  
value  
X
0
TRCIOC output  
TRCIOC input(1)  
ACOUT0 output  
X
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.  
Table 7.37  
TRCIOC Pin Setting  
Register  
Bit  
PINSR3  
TRCOER  
TRCMR  
TRCIOR1  
Function  
TRCIOCSEL  
EC  
0
PWM2  
PWMC  
1
IOC2  
IOC1  
IOC0  
0
0
0
0
0
1
X
0
0
X
0
1
X
1
PWM mode waveform output  
Timer waveform output (output  
compare function)  
0
1
0
0
X
Setting  
value  
0
1
1
1
X
X
Timer mode (input capture function)  
Other than TRCIOC usage conditions  
Other than above  
X: 0 or 1  
Table 7.38  
Port P5_4/TRCIOD/ACOUT1  
Register  
Bit  
PD5  
Timer RC setting  
ACCR1  
Function  
PD5_4  
CM1OE  
Input port(1)  
0
1
Other than TRCIOD usage conditions  
Other than TRCIOD usage conditions  
Refer to Table 7.39 TRCIOD Pin Setting  
Refer to Table 7.39 TRCIOD Pin Setting  
Other than TRCIOD usage conditions  
0
0
0
0
1
Output port  
Setting  
value  
X
0
TRCIOD output  
TRCIOD input(1)  
ACOUT1 output  
X
X: 0 or 1  
NOTE:  
1. Pulled up by setting the PU13 bit in the PUR1 register to 1.  
Table 7.39  
TRCIOD Pin Setting  
Register  
Bit  
PINSR3  
TRCOER  
TRCMR  
TRCIOR1  
Function  
TRCIODSEL  
ED  
0
PWM2  
PWMD  
1
IOD2  
IOD1  
IOD0  
0
0
0
0
0
1
X
0
0
X
0
1
X
1
PWM mode waveform output  
Timer waveform output (output  
compare function)  
0
1
0
0
X
Setting  
value  
0
1
1
1
X
X
Timer mode (input capture function)  
Other than TRCIOD usage conditions  
Other than above  
X: 0 or 1  
Rev.1.00 Dec 14, 2007 Page 61 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
7. Programmable I/O Ports  
7.5  
Unassigned Pin Handling  
Table 7.40 lists Unassigned Pin Handling.  
Table 7.40  
Unassigned Pin Handling  
Pin Name  
Connection  
Ports P0, P1, P3_1, P3_3 to P3_7, • After setting to input mode, connect each pin to VSS via a resistor  
(2)  
P4_3 to P4_5, P5_3, P5_4  
(pull-down) or connect each pin to VCC via a resistor (pull-up).  
(1, 2)  
• After setting to output mode, leave these pins open.  
(2)  
Ports P4_6, P4_7  
Port P4_2, VREF  
Connect to VCC via a pull-up resistor  
Connect to VCC  
(2)  
(3)  
Connect to VCC via a pull-up resistor  
RESET  
NOTES:  
1. If these ports are set to output mode and left open, they remain in input mode until they are switched  
to output mode by a program. The voltage level of these pins may be undefined and the power  
current may increase while the ports remain in input mode.  
The content of the direction registers may change due to noise or program runaway caused by  
noise. In order to enhance program reliability, the program should periodically repeat the setting of  
the direction registers.  
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.  
3. When the power-on reset function is in use.  
MCU  
Port P0, P1,  
P3_1, P3_3 to P3_7,  
P4_3 to P4_5,  
(Input mode )  
:
:
:
:
(Input mode)  
P5_3, P5_4  
(Output mode)  
Open  
Port P4_6, P4_7  
RESET(1)  
Port P4_2/VREF  
NOTE:  
1. When the power-on reset function is in use.  
Figure 7.13  
Unassigned Pin Handling  
Rev.1.00 Dec 14, 2007 Page 62 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
8. Processor Mode  
8. Processor Mode  
8.1  
Processor Modes  
Single-chip mode can be selected as the processor mode.  
Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1  
Register.  
Table 8.1  
Features of Processor Mode  
Accessible Areas  
Processor Mode  
Pins Assignable as I/O Port Pins  
Single-chip mode  
SFR, internal RAM, internal ROM All pins are I/O ports or peripheral  
function I/O pins  
Processor Mode Register 0(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0  
Symbol  
PM0  
Address  
0004h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
(b2-b0)  
Reserved bits  
Set to 0.  
Softw are reset bit  
The MCU is reset w hen this bit is set to 1.  
When read, the content is 0.  
PM03  
RW  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.  
Figure 8.1  
PM0 Register  
Processor Mode Register 1(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0
0 0  
Symbol  
PM1  
Address  
0005h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
(b1-b0)  
Reserved bits  
WDT interrupt/reset sw itch bit  
Set to 0.  
0 : Watchdog timer interrupt  
1 : Watchdog timer reset(2)  
PM12  
RW  
(b6-b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
(b7)  
Reserved bit  
Set to 0.  
RW  
NOTES:  
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.  
2. The PM12 bit is set to 1 by a program (It remains unchanged even if 0 is w ritten to it).  
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is  
automatically set to 1.  
Figure 8.2  
PM1 Register  
Rev.1.00 Dec 14, 2007 Page 63 of 332  
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R8C/2E Group, R8C/2F Group  
9.Bus  
9. Bus  
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.  
Table 9.1 lists Bus Cycles by Access Space of the R8C/2E Group and Table 9.2 lists Bus Cycles by Access Space of  
the R8C/2F Group.  
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are  
accessed twice in 8-bit units.  
Table 9.3 lists Access Units and Bus Operations.  
Table 9.1  
Bus Cycles by Access Space of the R8C/2E Group  
Access Area  
Bus Cycle  
2 cycles of CPU clock  
1 cycle of CPU clock  
SFR  
ROM/RAM  
Table 9.2  
Bus Cycles by Access Space of the R8C/2F Group  
Access Area  
Bus Cycle  
2 cycles of CPU clock  
1 cycle of CPU clock  
SFR/Data flash  
Program ROM/RAM  
Table 9.3  
Access Units and Bus Operations  
SFR, data flash  
Area  
ROM (program ROM), RAM  
CPU clock  
Even address  
Byte access  
CPU clock  
Even  
Data  
Even  
Odd  
Address  
Data  
Address  
Data  
Data  
Odd address  
Byte access  
CPU clock  
CPU clock  
Address  
Data  
Odd  
Data  
Address  
Data  
Data  
Even address  
Word access  
CPU clock  
CPU clock  
Address  
Data  
Address  
Data  
Even  
Data  
Even+1  
Data  
Even  
Data  
Even+1  
Data  
Odd address  
Word access  
CPU clock  
CPU clock  
Address  
Data  
Odd  
Odd+1  
Data  
Odd+1  
Data  
Odd  
Address  
Data  
Data  
Data  
However, only following SFRs are connected with the 16-bit bus:  
Timer RC: registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD  
Therefore, when accessing in word (16-bit) unit, 16-bit data is accessed at a time. The bus operation is the same as  
“Area: SFR, data flash, even address byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is  
accessed at a time.  
Rev.1.00 Dec 14, 2007 Page 64 of 332  
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R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
10. Clock Generation Circuit  
The clock generation circuit has:  
• XIN clock oscillation circuit  
• Low-speed on-chip oscillator  
• High-speed on-chip oscillator  
Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures  
10.2 to 10.7 show clock associated registers.  
Table 10.1  
Specifications of Clock Generation Circuit  
On-Chip Oscillator  
High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator  
Item  
XIN Clock Oscillation Circuit  
Applications  
• CPU clock source  
• Peripheral function clock  
source  
• CPU clock source  
• Peripheral function clock  
source  
• CPU clock source  
• Peripheral function clock  
source  
• CPU and peripheral function  
clock sources when XIN clock  
stops oscillating  
• CPU and peripheral function  
clock sources when XIN clock  
stops oscillating  
Approx. 40 MHz(3)  
Clock frequency 0 to 20 MHz  
Approx. 125 kHz  
Connectable  
oscillator  
• Ceramic resonator  
• Crystal oscillator  
XIN, XOUT(1)  
(1)  
(1)  
Oscillator  
connect pins  
Oscillation stop, Usable  
restart function  
Usable  
Stop  
Usable  
Oscillate  
Oscillator status Stop  
after reset  
Others  
• Externally generated clock  
can be input(2)  
• On-chip feedback resistor  
RfXIN (connected/ not  
connected, selectable)  
NOTES:  
1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the  
XIN clock oscillation circuit is not used.  
2. Set the CM05 bit in the CM0 register to 1 (XIN clock stopped) and the CM13 bit in the CM1 register to 1 (XIN-  
XOUT pin) when an external clock is input.  
3. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip  
oscillator as the CPU clock source.  
Rev.1.00 Dec 14, 2007 Page 65 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
FRA1 register  
Frequency adjustable  
High-speed  
on-chip  
oscillator  
FRA00  
fOCO40M  
FRA2 register  
Divider  
fOCO128  
Divider  
(1/128)  
Watchdog  
timer  
fOCO-F  
On-chip oscillator  
clock  
FRA01 = 1  
FRA01 = 0  
A/D  
converter  
INT0  
Timer RA Timer RB Timer RC Timer RE  
UART0  
fOCO  
Stop signal  
Low-speed  
on-chip  
oscillator  
Power-on  
reset circuit  
CM14  
fOCO-S  
Voltage  
detection  
circuit  
XOUT  
XIN  
f1  
b
CM13  
CM05  
f2  
f4  
f8  
c
Oscillation  
stop  
detection  
d
e
g
OCD2 = 1  
OCD2 = 0  
f32  
XIN  
clock  
a
CPU clock  
Divider  
D/A  
converter  
Comparator  
System clock  
CM02  
CM10 = 1 (stop mode)  
Q
S
R
RESET  
Power-on reset  
Software reset  
Interrupt request  
g
e
d
c
b
Q
S
R
1/2  
1/2  
a
1/2  
1/2  
1/2  
WAIT instruction  
CM06 = 0  
CM17 to CM16 = 11b  
CM06 = 1  
h
CM06 = 0  
CM17 to CM16 = 10b  
CM02, CM05, CM06: Bits in CM0 register  
CM06 = 0  
CM17 to CM16 = 01b  
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register  
OCD0, OCD1, OCD2: Bits in OCD register  
FRA00, FRA01: Bits in FRA0 register  
CM06 = 0  
CM17 to CM16 = 00b  
Detail of divider  
Oscillation Stop Detection Circuit  
Forcible discharge when OCD0 = 0  
Pulse generation  
circuit for clock  
Charge,  
discharge  
circuit  
Oscillation stop detection  
interrupt generation  
circuit detection  
XIN clock  
edge detection and  
charge, discharge  
control circuit  
Oscillation stop detection,  
Watchdog timer,  
Voltage monitor 1 interrupt,  
Voltage monitor 2 interrupt  
Watchdog timer  
OCD1  
interrupt  
Voltage monitor 1  
interrupt  
Voltage monitor 2  
interrupt  
OCD2 bit switch signal  
CM14 bit switch signal  
Figure 10.1  
Clock Generation Circuit  
Rev.1.00 Dec 14, 2007 Page 66 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
System Clock Control Register 0(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0
0 1  
0 0  
Symbol  
CM0  
Bit Symbol  
Address  
0006h  
After Reset  
01101000b  
Function  
Bit Name  
RW  
RW  
(b1-b0)  
Reserved bits  
Set to 0.  
WAIT peripheral function clock 0 : Peripheral function clock does not stop  
stop bit  
in w ait mode  
1 : Peripheral function clock stops in w ait  
mode  
CM02  
RW  
(b3)  
Reserved bit  
Reserved bit  
Set to 1.  
RW  
RW  
RW  
RW  
RW  
(b4)  
Set to 0.  
XIN clock (XIN-XOUT)  
stop bit(2, 3)  
0 : XIN clock oscillates  
1 : XIN clock stops(4)  
CM05  
CM06  
System clock division select bit 0 : CM16, CM17 enabled  
0(5)  
1 : Divide-by-8 mode  
(b7)  
Reserved bit  
Set to 0.  
NOTES:  
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.  
2. P4_6 and P4_7 can be used as input ports w hen the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the  
CM1 register is set to 0 (P4_6, P4_7).  
3. The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode or low -speed on-chip oscillator mode  
is selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the  
follow ing order:  
(a) Set bits OCD1 to OCD0 in the OCD register to 00b.  
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).  
4. During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged.  
5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).  
Figure 10.2  
CM0 Register  
Rev.1.00 Dec 14, 2007 Page 67 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
System Clock Control Register 1(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
Address  
0007h  
After Reset  
00100000b  
Function  
CM1  
Bit Symbol  
Bit Name  
RW  
RW  
3, 4)  
All clock stop control bit(2,  
0 : Clock operates  
1 : Stops all clocks (stop mode)  
XIN-XOUT on-chip feedback resistor 0 : On-chip feedback resistor enabled  
CM10  
CM11  
RW  
RW  
RW  
RW  
RW  
select bit  
1 : On-chip feedback resistor disabled  
(b2)  
Reserved bit  
Set to 0.  
Port XIN-XOUT sw itch bit(3, 5)  
0 : Input ports P4_6, P4_7  
1 : XIN-XOUT pin  
CM13  
CM14  
CM15  
Low -speed on-chip oscillation stop 0 : Low -speed on-chip oscillator on  
bit(4, 6, 7)  
1 : Low -speed on-chip oscillator off  
XIN-XOUT drive capacity select bit(8) 0 : Low  
1 : High  
System clock division select bits 1(9)  
b7 b6  
0 0 : No division mode  
CM16  
CM17  
RW  
RW  
0 1 : Divide-by-2 mode  
1 0 : Divide-by-4 mode  
1 1 : Divide-by-16 mode  
NOTES:  
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.  
2. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.  
3. When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes “H”.  
When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode.  
4. In count source protect mode (Refer to  
), the value remains  
13.2 Count Source Protect Mode Enabled  
unchanged even if bits CM10 and CM14 are set.  
5. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.  
6. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped).  
When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip  
oscillator on). It remains unchanged even if 1 is w ritten to it.  
7. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14  
bit to 0 (low -speed on-chip oscillator on).  
8. When entering stop mode, the CM15 bit is set to 1 (drive capacity high).  
9. When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.  
Figure 10.3  
CM1 Register  
Rev.1.00 Dec 14, 2007 Page 68 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
Oscillation Stop Detection Register(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0 0  
Symbol  
Address  
000Ch  
After Reset  
00000100b  
Function  
OCD  
Bit Symbol  
Bit Name  
RW  
RW  
Oscillation stop detection enable 0 : Oscillation stop detection function  
bit(7)  
disabled(2)  
OCD0  
1 : Oscillation stop detection function  
enabled  
Oscillation stop detection  
interrupt enable bit  
Systemclock select bit(4)  
0 : Disabled(2)  
1 : Enabled  
0 : Selects XIN clock(7)  
1 : Selects on-chip oscillator clock(3)  
OCD1  
OCD2  
OCD3  
RW  
RW  
RO  
RW  
Clock monitor bit(5, 6)  
Reserved bits  
0 : XIN clock oscillates  
1 : XIN clock stops  
(b7-b4)  
Set to 0.  
NOTES:  
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.  
2. Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip  
oscillator mode (XIN clock stops).  
3. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock  
selected).  
4. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected  
w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains  
unchanged even w hen set to 0 (XIN clock selected).  
5. The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled).  
6. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.  
7. Ref er to  
Figure 10.14 Procedure for Switching Clock Source from Low-speed On-Chip Oscillator to XIN  
for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.  
Clock  
Figure 10.4  
OCD Register  
Rev.1.00 Dec 14, 2007 Page 69 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
High-Speed On-Chip Oscillator Control Register 0(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0 0 0 0  
Symbol  
FRA0  
Address  
0023h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
High-speed on-chip oscillator  
enable bit  
0 : High-speed on-chip oscillator off  
1 : High-speed on-chip oscillator on  
0 : Selects low -speed on-chip oscillator(3)  
1 : Selects high-speed on-chip oscillator  
FRA00  
FRA01  
High-speed on-chip oscillator  
select bit(2)  
RW  
RW  
(b7-b2)  
Reserved bits  
Set to 0.  
NOTES:  
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA0 register.  
1.  
2. Change the FRA01 bit under the follow ing conditions.  
• FRA00 = 1 (high-speed on-chip oscillation)  
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)  
3. When setting the FRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-speed  
on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0.  
High-Speed On-Chip Oscillator Control Register 1(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
FRA1  
Address  
0024h  
After Reset  
When Shipping  
Function  
RW  
RW  
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.  
High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value w hen shipping)  
Setting the FRA1 register to a low er value results in a higher frequency.  
Setting the FRA1 register to a higher value results in a low er frequency.(2)  
NOTES:  
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA1 register.  
2. When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed  
on-chip oscillator clock w ill be 40 MHz or less.  
High-Speed On-Chip Oscillator Control Register 2(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0 0 0  
Symbol  
FRA2  
Address  
0025h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
High-speed on-chip oscillator  
frequency sw itching bits  
Selects the dividing ratio for the high-  
speed on-chip oscillator clock.  
b2 b1 b0  
FRA20  
FRA21  
FRA22  
0 0 0: Divide-by-2 mode  
0 0 1: Divide-by-3 mode  
0 1 0: Divide-by-4 mode  
0 1 1: Divide-by-5 mode  
1 0 0: Divide-by-6 mode  
1 0 1: Divide-by-7 mode  
1 1 0: Divide-by-8 mode  
1 1 1: Divide-by-9 mode  
RW  
RW  
RW  
(b7-b3)  
Reserved bits  
Set to 0.  
NOTE:  
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA2 register.  
Figure 10.5  
Registers FRA0 and FRA1, FRA2  
Rev.1.00 Dec 14, 2007 Page 70 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
High-Speed On-Chip Oscillator Control Register 7  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
FRA7  
Address  
002Ch  
After Reset  
When Shipping  
Function  
36.864 MHz frequency correction data is stored.  
The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz  
by transferring this value to the FRA1 register.  
RW  
RO  
Figure 10.6  
FRA7 Register  
Voltage Detection Register 2(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
1 0 0 0 0  
Symbol  
Address  
0032h  
Bit Name  
After Reset(4)  
Pow er-on reset or hardw are reset : 00100000b  
Function  
VCA2  
Bit Symbol  
RW  
RW  
Internal pow er low  
consumption enable bit(5)  
0 : Disables low consumption  
1 : Enables low consumption  
VCA20  
(b4-b1)  
Reserved bits  
Set to 0.  
RW  
RW  
RW  
RW  
(b5)  
Reserved bit  
Set to 1.  
Voltage detection 1 enable 0 : Voltage detection 1 circuit disabled  
bit(2)  
1 : Voltage detection 1 circuit enabled  
Voltage detection 2 enable 0 : Voltage detection 2 circuit disabled  
bit(3)  
1 : Voltage detection 2 circuit enabled  
VCA26  
VCA27  
NOTES:  
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.  
2. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.  
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting  
operation.  
3. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.  
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting  
operation.  
4. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this  
register.  
5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in  
Figure  
.
10.8 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit  
Figure 10.7  
VCA2 Register  
Rev.1.00 Dec 14, 2007 Page 71 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
10. Clock Generation Circuit  
Exit wait mode by interrupt  
(Note 1)  
Handling procedure of internal power  
low consumption enabled by VCA20 bit  
In interrupt routine  
VCA20 0 (internal power low consumption  
Step (1)  
Step (2)  
Step (3)  
Step (4)  
Enter low-speed on-chip oscillator mode  
Step (5)  
Step (6)  
Step (7)  
Step (8)  
disabled)(2)  
If it is necessary to start  
the high-speed clock or  
the high-speed on-chip  
oscillator in the interrupt  
routine, execute steps (5)  
to (7) in the interrupt  
routine.  
Stop XIN clock and high-speed on-chip  
oscillator clock  
Start XIN clock or high-speed on-chip  
oscillator clock  
VCA20 1 (internal power low consumption  
(Wait until XIN clock oscillation stabilizes)  
enabled)(2, 3)  
Enter high-speed clock mode or  
high-speed on-chip oscillator mode  
Enter wait mode(4)  
Interrupt handling  
VCA20 0 (internal power low consumption  
Step (5)  
Step (6)  
Step (7)  
Step (8)  
disabled)(2)  
Step (1)  
Step (2)  
Step (3)  
Enter low-speed on-chip oscillator mode  
Start XIN clock or high-speed on-chip  
oscillator clock  
If the high-speed clock or  
high-speed on-chip  
oscillator is started in the  
interrupt routine, execute  
steps (1) to (3) at the last of  
the interrupt routine.  
Stop XIN clock and high-speed on-chip  
oscillator clock  
(Wait until XIN clock oscillation stabilizes)  
VCA20 1 (internal power low consumption  
enabled)(2, 3)  
Enter high-speed clock mode or  
high-speed on-chip oscillator mode  
Interrupt handling completed  
NOTES:  
1. Execute this routine to handle all interrupts generated in wait mode.  
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.  
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.  
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).  
4. When entering wait mode, follow 10.6.2 Wait Mode.  
VCA20: Bit in VCA2 register  
Figure 10.8  
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit  
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10. Clock Generation Circuit  
The clocks generated by the clock generation circuits are described below.  
10.1 XIN Clock  
This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and  
peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the  
XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is  
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the  
chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN  
pin.  
Figure 10.9 shows Examples of XIN Clock Connection Circuit.  
In reset and after reset, the XIN clock stops.  
The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates) after  
setting the CM13 bit in the CM1 register to 1 (XIN- XOUT pin). To use the XIN clock for the CPU clock source,  
set the OCD2 bit in the OCD register to 0 (select XIN clock) after the XIN clock is oscillating stably.  
The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the  
OCD2 bit is set to 1 (select on-chip oscillator clock).  
When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 bit is set to 1. If  
necessary, use an external circuit to stop the clock.  
This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM11  
bit in the CM1 register.  
In stop mode, all clocks including the XIN clock stop. Refer to 10.4 Power Control for details.  
MCU  
MCU  
(on-chip feedback resistor)  
(on-chip feedback resistor)  
XIN  
XIN  
XOUT  
XOUT  
Open  
Rf(1)  
Rd(1)  
Externally derived clock  
CIN  
COUT  
VCC  
VSS  
External clock input circuit  
Ceramic resonator external circuit  
NOTE:  
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive  
capacity setting. Use the value recommended by the manufacturer of the oscillator.  
Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after  
oscillation stabilizes.  
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's  
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN  
and XOUT following the instructions.  
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register  
to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor  
to the chip externally.  
Figure 10.9  
Examples of XIN Clock Connection Circuit  
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10. Clock Generation Circuit  
10.2 On-Chip Oscillator Clocks  
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip  
oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.  
10.2.1 Low-Speed On-Chip Oscillator Clock  
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,  
peripheral function clock, fOCO, and fOCO-S.  
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as  
the CPU clock.  
If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed  
on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.  
The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating  
ambient temperature. Application products must be designed with sufficient margin to allow for frequency  
changes.  
10.2.2 High-Speed On-Chip Oscillator Clock  
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,  
peripheral function clock, fOCO, fOCO-F, and fOCO40M.  
After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is  
started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can  
be adjusted by registers FRA1 and FRA2.  
The frequency correction data of 36.864 MHz is stored in the FRA7 register. To set the frequency of the high-  
speed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7 register to the FRA1 register  
before use.  
Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make  
adjustments by changing the settings of individual bits. Adjust the FRA1 register so that the frequency of the  
high-speed on-chip oscillator clock will be 40 MHz or less.  
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10. Clock Generation Circuit  
10.3 CPU Clock and Peripheral Function Clock  
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer  
to Figure 10.1 Clock Generation Circuit.  
10.3.1 System Clock  
The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock or the  
on-chip oscillator clock can be selected.  
10.3.2 CPU Clock  
The CPU clock is an operating clock for the CPU and watchdog timer.  
The system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit  
in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division.  
After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock.  
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).  
10.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)  
The peripheral function clock is the operating clock for the peripheral functions.  
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers  
RA, RB, RC, and RE, the serial interface and the A/D converter.  
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function  
clock stops in wait mode), the clock fi stop.  
10.3.4 fOCO  
fOCO is an operating clock for the peripheral functions.  
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.  
When the WAIT instruction is executed, the clocks fOCO does not stop.  
10.3.5 fOCO40M  
fOCO40M is used as the count source for timer RC. fOCO40M is generated by the high-speed on-chip  
oscillator and supplied by setting the FRA00 bit to 1.  
When the WAIT instruction is executed, the clock fOCO40M does not stop.  
fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V.  
10.3.6 fOCO-F  
fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip  
oscillator and supplied by setting the FRA00 bit to 1.  
When the WAIT instruction is executed, the clock fOCO-F does not stop.  
10.3.7 fOCO-S  
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by  
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on-  
chip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer,  
fOCO-S does not stop.  
10.3.8 fOCO128  
fOCO128 is generated by fOCO divided by 128.  
The clock fOCO128 is used for capture signal of the timer RC’s TRCGRA register.  
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10. Clock Generation Circuit  
10.4 Power Control  
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard  
operating mode.  
10.4.1 Standard Operating Mode  
Standard operating mode is further separated into four modes.  
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU  
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock  
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU  
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power  
consumption is further reduced.  
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating  
and stable. If the new clock source is the XIN clock, allow sufficient wait time in a program until oscillation is  
stabilized before exiting.  
Table 10.2  
Modes  
High-speed No division  
Settings and Modes of Clock Associated Bits  
OCD Register  
CM1 Register  
CM0 Register  
FRA0 Register  
OCD2  
CM17, CM16 CM14 CM13 CM06 CM05 FRA01 FRA00  
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
00b  
01b  
10b  
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
clock mode  
Divide-by-2  
Divide-by-4  
Divide-by-8  
Divide-by-16  
11b  
00b  
01b  
10b  
High-speed No division  
on-chip  
oscillator  
mode  
Divide-by-2  
Divide-by-4  
Divide-by-8  
Divide-by-16  
11b  
00b  
01b  
10b  
Low-speed No division  
on-chip  
oscillator  
mode  
Divide-by-2  
Divide-by-4  
Divide-by-8  
Divide-by-16  
11b  
: can be 0 or 1, no change in outcome  
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10. Clock Generation Circuit  
10.4.1.1 High-Speed Clock Mode  
The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide-  
by-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the  
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-  
speed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be  
used as timer RC.  
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer  
and voltage detection circuit.  
10.4.1.2 High-Speed On-Chip Oscillator Mode  
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0  
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The on-  
chip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide-  
by-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as  
timer RC.  
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer  
and voltage detection circuit.  
10.4.1.3 Low-Speed On-Chip Oscillator Mode  
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0  
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.  
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip  
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8  
mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as  
timer RC.  
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer  
and voltage detection circuit.  
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4  
register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.  
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1  
(internal power low consumption enabled) enables lower consumption current in wait mode.  
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.11 Procedure for  
Enabling Reduced Internal Power Consumption Using VCA20 bit.  
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10. Clock Generation Circuit  
10.4.2 Wait Mode  
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog  
timer, when count source protection mode is disabled, stop. The XIN clock and on-chip oscillator clock do not  
stop and the peripheral functions using these clocks continue operating.  
10.4.2.1 Peripheral Function Clock Stop Function  
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop  
in wait mode. This reduces power consumption.  
10.4.2.2 Entering Wait Mode  
The MCU enters wait mode when the WAIT instruction is executed.  
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1  
bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT  
instruction.  
If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled),  
current consumption is not reduced because the CPU clock does not stop.  
10.4.2.3 Pin Status in Wait Mode  
The I/O port is the status before wait mode was entered is maintained.  
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10. Clock Generation Circuit  
10.4.2.4 Exiting Wait Mode  
The MCU exits wait mode by a reset or a peripheral function interrupt.  
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral  
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.  
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the  
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip  
oscillator clock can be used to exit wait mode.  
Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions.  
Table 10.3  
Interrupts to Exit Wait Mode and Usage Conditions  
Interrupt  
CM02 = 0  
Usable when operating with  
internal or external clock  
Usable  
CM02 = 1  
Usable when operating with external  
clock  
Serial interface interrupt  
Key input interrupt  
Usable  
A/D conversion interrupt  
Comparator 0 interrupt  
Comparator 1 interrupt  
Timer RA interrupt  
Usable in one-shot mode  
Usable  
(Do not use)  
Can be used if there is no filter  
Can be used if there is no filter  
Can be used if there is no filter in  
event counter mode.  
Usable by selecting fOCO as count  
source.  
Usable  
Usable in all modes  
Timer RB interrupt  
Timer RC interrupt  
Timer RE interrupt  
Usable in all modes  
Usable in all modes  
Usable in all modes  
Usable  
(Do not use)  
(Do not use)  
(Do not use)  
INT interrupt  
Usable (INT0, INT1, INT3 can be used  
if there is no filter.)  
Usable  
Voltage monitor 1 interrupt  
Voltage monitor 2 interrupt  
Oscillation stop detection  
interrupt  
Usable  
Usable  
Usable  
Usable  
(Do not use)  
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10. Clock Generation Circuit  
Figure 10.10 shows Time from Wait Mode to Interrupt Routine Execution.  
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT  
instruction.  
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral  
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function  
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).  
(2) Set the I flag to 1.  
(3) Operate the peripheral function to be used for exiting wait mode.  
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request  
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register,  
as described in Figure 10.10.  
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock  
when the WAIT instruction is executed.  
FMR0 Register  
FMSTP Bit  
Time until Flash Memory Time until CPU Clock Time for Interrupt  
Remarks  
is Activated (T1)  
is Supplied (T2)  
Sequence (T3)  
0
Period of XIN clock  
× 12 cycles + 30 µs (max.)  
Period of CPU clock Period of CPU clock  
Following total time is  
the time from wait  
× 6 cycles  
× 20 cycles  
(flash memory operates)  
mode until an interrupt  
routine is executed.  
1
Period of XIN clock  
Same as above  
Same as above  
× 12 cycles  
(flash memory stops)  
T1  
T2  
T3  
Flash memory  
activation sequence  
Wait mode  
CPU clock restart sequence  
Interrupt sequence  
Interrupt request generated  
Figure 10.10 Time from Wait Mode to Interrupt Routine Execution  
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10. Clock Generation Circuit  
10.4.2.5 Reducing Internal Power Consumption  
Internal power consumption can be reduced by using low-speed on-chip oscillator mode. Figure 10.11 shows  
the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.  
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.11 Procedure for  
Enabling Reduced Internal Power Consumption Using VCA20 bit.  
Exit wait mode by interrupt  
(Note 1)  
Handling procedure of internal power  
In interrupt routine  
low consumption enabled by VCA20 bit  
VCA20 0 (internal power low consumption  
Step (1)  
Step (2)  
Step (3)  
Step (4)  
Enter low-speed on-chip oscillator mode  
Step (5)  
Step (6)  
Step (7)  
Step (8)  
disabled)(2)  
If it is necessary to start  
the high-speed clock or  
the high-speed on-chip  
oscillator in the interrupt  
routine, execute steps (5)  
to (7) in the interrupt  
routine.  
Stop XIN clock and high-speed on-chip  
oscillator clock  
Start XIN clock or high-speed on-chip  
oscillator clock  
VCA20 1 (internal power low consumption  
(Wait until XIN clock oscillation stabilizes)  
enabled)(2, 3)  
Enter high-speed clock mode or  
high-speed on-chip oscillator mode  
Enter wait mode(4)  
Interrupt handling  
VCA20 0 (internal power low consumption  
Step (5)  
Step (6)  
Step (7)  
Step (8)  
disabled)(2)  
Step (1)  
Step (2)  
Step (3)  
Enter low-speed on-chip oscillator mode  
Start XIN clock or high-speed on-chip  
oscillator clock  
If the high-speed clock or  
high-speed on-chip  
oscillator is started in the  
interrupt routine, execute  
steps (1) to (3) at the last of  
the interrupt routine.  
Stop XIN clock and high-speed on-chip  
oscillator clock  
(Wait until XIN clock oscillation stabilizes)  
VCA20 1 (internal power low consumption  
enabled)(2, 3)  
Enter high-speed clock mode or  
high-speed on-chip oscillator mode  
Interrupt handling completed  
NOTES:  
1. Execute this routine to handle all interrupts generated in wait mode.  
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.  
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.  
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).  
4. When entering wait mode, follow 10.6.2 Wait Mode.  
VCA20: Bit in VCA2 register  
Figure 10.11 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit  
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10. Clock Generation Circuit  
10.4.3 Stop Mode  
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU  
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in  
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is  
maintained.  
The peripheral functions clocked by external signals continue operating.  
Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.  
Table 10.4  
Interrupts to Exit Stop Mode and Usage Conditions  
Interrupt Usage Conditions  
Key input interrupt  
INT0, INT1, INT3 interrupt  
Timer RA interrupt  
Can be used if there is no filter  
When there is no filter and external pulse is counted in event counter  
mode  
Serial interface interrupt  
When external clock is selected  
Voltage monitor 1 interrupt  
Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set  
to 1)  
Voltage monitor 2 interrupt  
Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set  
to 1)  
Comparator 0 interrupt,  
Comparator 1 interrupt  
Can be used if there is no filter  
10.4.3.1 Entering Stop Mode  
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same  
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is  
set to 1 (XIN clock oscillator circuit drive capacity high).  
When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode.  
10.4.3.2 Pin Status in Stop Mode  
The status before wait mode was entered is maintained.  
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held  
“H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in input status.  
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10. Clock Generation Circuit  
10.4.3.3 Exiting Stop Mode  
The MCU exits stop mode by a reset or peripheral function interrupt.  
Figure 10.12 shows the Time from Stop Mode to Interrupt Routine Execution.  
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit  
to 1.  
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for  
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used  
for exiting stop mode to 000b (interrupt disabled).  
(2) Set the I flag to 1.  
(3) Operates the peripheral function to be used for exiting stop mode.  
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is  
generated and the CPU clock supply is started.  
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral  
function interrupt, the CPU clock becomes the previous system clock divided by 8.  
FMR0 Register  
FMSTP Bit  
Time until Flash Memory Time until CPU Clock  
Time for Interrupt  
Sequence (T4)  
Remarks  
is Activated (T2)  
is Supplied (T3)  
0
Following total  
time of T0 to T4  
is the time from  
stop mode until  
an interrupt  
Period of XIN clock  
Period of CPU clock Period of CPU clock  
(flash memory  
operates)  
× 12 cycles + 30 µs (max.)  
× 6 cycles  
× 20 cycles  
1
Period of XIN clock  
Same as above  
Same as above  
handling is  
(flash memory stops)  
× 12 cycles  
executed.  
T0  
T1  
T2  
T3  
T4  
Oscillation time of  
CPU clock source  
used immediately  
Internal  
power  
stability time  
Stop  
mode  
Flash memory  
activation sequence  
CPU clock restart  
sequence  
Interrupt sequence  
before stop mode  
150 µs  
(max.)  
Interrupt  
request  
generated  
Figure 10.12 Time from Stop Mode to Interrupt Routine Execution  
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10. Clock Generation Circuit  
Figure 10.13 shows the State Transitions in Power Control Mode.  
State Transitions in Power Control Mode  
Standard operating mode  
Reset  
Low-speed on-chip oscillator mode  
CM14 = 0  
OCD2 = 1  
FRA01 = 0  
CM14 = 0  
OCD2 = 1  
FRA01 = 0  
CM05 = 0  
CM13 = 1  
OCD2 = 0  
High-speed clock mode  
CM05 = 0  
FRA00 = 1  
FRA01 = 1  
CM14 = 0  
FRA01 = 0  
CM13 = 1  
OCD2 = 0  
OCD2 = 1  
FRA00 = 1  
FRA01 = 1  
CM05 = 0  
CM13 = 1  
OCD2 = 0  
High-speed on-chip oscillator mode  
OCD2 = 1  
FRA00 = 1  
FRA01 = 1  
Interrupt  
WAIT instruction  
Interrupt  
CM10 = 1  
Wait mode  
Stop mode  
All oscillators stop  
CPU operation stops  
CM05: Bit in CM0 register  
CM13, CM14: Bits in CM1 register  
OCD2: Bit in OCD register  
FRA00, FRA01: Bits in FRA0 register  
Figure 10.13 State Transitions in Power Control Mode  
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10. Clock Generation Circuit  
10.5 Oscillation Stop Detection Function  
The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop  
detection function can be enabled and disabled by the OCD0 bit in the OCD register.  
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.  
When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the  
following state if the XIN clock stops.  
OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)  
OCD3 bit in OCD register = 1 (XIN clock stops)  
CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)  
Oscillation stop detection interrupt request is generated.  
Table 10.5  
Specifications of Oscillation Stop Detection Function  
Item Specification  
Oscillation stop detection clock and  
frequency bandwidth  
f(XIN) 2 MHz  
Enabled condition for oscillation stop  
detection function  
Set bits OCD1 to OCD0 to 11b  
Oscillation stop detection interrupt is generated  
Operation at oscillation stop detection  
10.5.1 How to Use Oscillation Stop Detection Function  
The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage  
monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt  
and watchdog timer interrupt, the interrupt source needs to be determined.  
Table 10.6 lists Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage  
Monitor 1, and Voltage Monitor 2 Interrupts. Figure 10.15 shows the Example of Determining Interrupt  
Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt.  
When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU  
clock and peripheral functions by a program.  
Figure 10.14 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to  
XIN Clock.  
To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral  
function clock does not stop in wait mode).  
Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an  
external cause, set bits OCD1 to OCD0 to 00b when the XIN clock stops or is started by a program, (stop  
mode is selected or the CM05 bit is changed).  
This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1  
to OCD0 to 00b.  
To use the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions  
after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip  
oscillator selected) and bits OCD1 to OCD0 to 11b.  
To use the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions  
after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01  
bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b.  
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10. Clock Generation Circuit  
Table 10.6  
Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer,  
Voltage Monitor 1, and Voltage Monitor 2 Interrupts  
Generated Interrupt Source  
Oscillation stop detection  
((a) or (b))  
Bit Showing Interrupt Cause  
(a) OCD3 bit in OCD register = 1  
(b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1  
VW2C3 bit in VW2C register = 1  
Watchdog timer  
Voltage monitor 1  
Voltage monitor 2  
VW1C2 bit in VW1C register = 1  
VW2C2 bit in VW2C register = 1  
Switch to XIN clock  
Multiple confirmations  
that OCD3 bit is set to 0 (XIN  
clock oscillates) ?  
NO  
YES  
Set OCD1 to OCD0 bits to 00b  
Set OCD2 bit to 0  
(select XIN clock)  
End  
OCD3 to OCD0: Bits in OCD register  
Figure 10.14 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN  
Clock  
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10. Clock Generation Circuit  
Interrupt sources judgment  
NO  
OCD3 = 1 ?  
(XIN clock stopped)  
YES  
OCD1 = 1  
(oscillation stop detection  
NO  
interrupt enabled) and OCD2 = 1  
(on-chip oscillator clock selected  
as system clock) ?  
YES  
VW2C3 = 1 ?  
(Watchdog timer  
underflow)  
NO  
YES  
NO  
VW2C2 = 1 ?  
(passing Vdet2)  
YES  
Set OCD1 bit to 0 (oscillation stop  
detection interrupt disabled).(1)  
To oscillation stop detection  
interrupt routine  
To watchdog timer  
interrupt routine  
To voltage monitor 2  
interrupt routine  
To voltage monitor 1  
interrupt routine  
NOTE:  
1. This disables multiple oscillation stop detection interrupts.  
OCD1 to OCD3: Bits in OCD register  
VW2C2, VW2C3: Bits in VW2C register  
Figure 10.15 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog  
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt  
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10. Clock Generation Circuit  
10.6 Notes on Clock Generation Circuit  
10.6.1 Stop Mode  
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the  
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction  
which sets the CM10 bit to 1 (stop mode) and the program stops.  
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit  
to 1.  
Program example to enter stop mode  
BCLR  
BSET  
FSET  
BSET  
JMP.B  
1,FMR0  
0,PRCR  
I
0,CM1  
LABEL_001  
; CPU rewrite mode disabled  
; Protect disabled  
; Enable interrupt  
; Stop mode  
LABEL_001 :  
NOP  
NOP  
NOP  
NOP  
10.6.2 Wait Mode  
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and  
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the  
program stops. Insert at least 4 NOP instructions after the WAIT instruction.  
Program example to execute the WAIT instruction  
BCLR  
FSET  
WAIT  
NOP  
1,FMR0  
I
; CPU rewrite mode disabled  
; Enable interrupt  
; Wait mode  
NOP  
NOP  
NOP  
10.6.3 Oscillation Stop Detection Function  
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set  
bits OCD1 to OCD0 to 00b.  
10.6.4 Oscillation Circuit Constants  
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.  
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1  
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the  
feedback resistor to the chip externally.  
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11.Protection  
11. Protection  
The protection function protects important registers from being easily overwritten when a program runs out of control.  
Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.  
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2  
• Registers protected by PRC1 bit: Registers PM0 and PM1  
• Registers protected by PRC2 bit: PD0 register  
• Registers protected by PRC3 bit: Registers VCA2, VW1C, and VW2C  
Protect Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
PRCR  
Address  
000Ah  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Protect bit 0  
Writing to registers CM0, CM1, OCD, FRA0, FRA1,  
and FRA2 is enabled.  
PRC0  
0 : Disables w riting  
1 : Enables w riting  
Protect bit 1  
Protect bit 2  
Protect bit 3  
Writing to registers PM0 and PM1 is enabled.  
0 : Disables w riting  
1 : Enables w riting  
PRC1  
PRC2  
RW  
RW  
Writing to the PD0 register is enabled.  
0 : Disables w riting  
1 : Enables w riting(1)  
Writing to registers VCA2, VW1C, and VW2C is  
enabled.  
0 : Disables w riting  
PRC3  
RW  
1 : Enables w riting  
(b5-b4)  
Reserved bits  
Reserved bits  
Set to 0.  
RW  
RO  
(b7-b6)  
When read, the content is 0.  
NOTE:  
1. This bit is set to 0 after w riting 1 to the PRC2 bit and executing a w rite to any address. Since the other bits are not  
set to 0, set them to 0 by a program.  
Figure 11.1  
PRCR Register  
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12.Interrupts  
12. Interrupts  
12.1 Interrupt Overview  
12.1.1 Types of Interrupts  
Figure 12.1 shows the types of Interrupts.  
Undefined instruction (UND instruction)  
Overflow (INTO instruction)  
BRK instruction  
INT instruction  
Software  
(non-maskable interrupts)  
Watchdog timer  
Oscillation stop detection  
Voltage monitor 1  
Voltage monitor 2  
Single step(2)  
Interrupts  
Special  
(non-maskable interrupts)  
Address break(2)  
Address match  
Hardware  
Peripheral functions(1)  
(maskable interrupts)  
NOTES:  
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.  
2. Do not use this interrupt. This is for use with development tools only.  
Figure 12.1  
Interrupts  
Maskable Interrupts:  
The interrupt enable flag (I flag) enables or disables these interrupts. The  
interrupt priority order can be changed based on the interrupt priority level.  
Non-Maskable Interrupts:  
The interrupt enable flag (I flag) does not enable or disable these interrupts.  
The interrupt priority order cannot be changed based on interrupt priority  
level.  
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12.Interrupts  
12.1.2 Software Interrupts  
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.  
12.1.2.1 Undefined Instruction Interrupt  
The undefined instruction interrupt is generated when the UND instruction is executed.  
12.1.2.2 Overflow Interrupt  
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO  
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,  
NEG, RMPA, SBB, SHA, and SUB.  
12.1.2.3 BRK Interrupt  
A BRK interrupt is generated when the BRK instruction is executed.  
12.1.2.4 INT Instruction Interrupt  
An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select  
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function  
interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as  
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to  
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is  
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt  
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.  
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12.Interrupts  
12.1.3 Special Interrupts  
Special interrupts are non-maskable.  
12.1.3.1 Watchdog Timer Interrupt  
The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer.  
12.1.3.2 Oscillation Stop Detection Interrupt  
The oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the  
oscillation stop detection function, refer to 10. Clock Generation Circuit.  
12.1.3.3 Voltage Monitor 1 Interrupt  
The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection  
circuit, refer to 6. Voltage Detection Circuit.  
12.1.3.4 Voltage Monitor 2 Interrupt  
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection  
circuit, refer to 6. Voltage Detection Circuit.  
12.1.3.5 Single-Step Interrupt, and Address Break Interrupt  
Do not use these interrupts. They are for use by development tools only.  
12.1.3.6 Address Match Interrupt  
The address match interrupt is generated immediately before executing an instruction that is stored at an  
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to  
1 (address match interrupt enable). For details of the address match interrupt, refer to 12.4 Address Match  
Interrupt.  
12.1.4 Peripheral Function Interrupt  
The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable  
interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For  
details of peripheral functions, refer to the descriptions of individual peripheral functions.  
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12.Interrupts  
12.1.5 Interrupts and Interrupt Vectors  
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When  
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.  
Figure 12.2 shows an Interrupt Vector.  
MSB  
LSB  
Vector address (L)  
Low address  
Mid address  
0 0 0 0  
0 0 0 0  
High address  
0 0 0 0  
Vector address (H)  
Figure 12.2  
Interrupt Vector  
12.1.5.1 Fixed Vector Tables  
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.  
Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code  
check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory.  
Table 12.1  
Fixed Vector Tables  
Vector Addresses  
Address (L) to (H)  
Interrupt Source  
Remarks  
Reference  
Undefined instruction  
0FFDCh to 0FFDFh Interrupt on UND  
instruction  
R8C/Tiny Series Software  
Manual  
Overflow  
0FFE0h to 0FFE3h Interrupt on INTO  
instruction  
BRK instruction  
0FFE4h to 0FFE7h If the content of address  
0FFE7h is FFh,  
program execution  
starts from the address  
shown by the vector in  
the relocatable vector  
table.  
Address match  
0FFE8h to 0FFEBh  
12.4 Address Match  
Interrupt  
(1)  
0FFECh to 0FFEFh  
0FFF0h to 0FFF3h  
Single step  
Watchdog timer,  
13. Watchdog Timer  
Oscillation stop detection,  
Voltage monitor 1,  
Voltage monitor 2  
10. Clock Generation Circuit  
6. Voltage Detection Circuit  
(1)  
0FFF4h to 0FFF7h  
0FFF8h to 0FFFBh  
0FFFCh to 0FFFFh  
Address break  
(Reserved)  
Reset  
5. Resets  
NOTE:  
1. Do not use these interrupts. They are for use by development tools only.  
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12.Interrupts  
12.1.5.2 Relocatable Vector Tables  
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.  
Table 12.2 lists the Relocatable Vector Tables.  
Table 12.2  
Relocatable Vector Tables  
Software  
Interrupt  
Number  
Vector Addresses(1)  
Address (L) to Address (H)  
Interrupt Control  
Register  
Interrupt Source  
Reference  
BRK instruction(2)  
+0 to +3 (0000h to 0003h)  
0
R8C/Tiny Series Software  
Manual  
(Reserved)  
(Reserved)  
Timer RC  
1 to 2  
3 to 6  
7
+28 to +31 (001Ch to 001Fh)  
+40 to +43 (0028h to 002Bh)  
TRCIC  
14.3 Timer RC  
(Reserved)  
Timer RE  
8 to 9  
10  
TREIC  
14.4 Timer RE  
(Reserved)  
Key input  
11 to 12  
13  
+52 to +55 (0034h to 0037h)  
+56 to +59 (0038h to 003Bh)  
KUPIC  
ADIC  
12.3 Key Input Interrupt  
17. A/D Converter  
A/D  
14  
(Reserved)  
UART0 transmit  
UART0 receive  
(Reserved)  
Timer RA  
15 to 16  
17  
+68 to +71 (0044h to 0047h)  
+72 to +75 (0048h to 004Bh)  
S0TIC  
S0RIC  
15. Serial Interface  
18  
19 to 21  
22  
+88 to +91 (0058h to 005Bh)  
TRAIC  
14.1 Timer RA  
(Reserved)  
Timer RB  
23  
+96 to +99 (0060h to 0063h)  
+100 to +103 (0064h to 0067h)  
24  
TRBIC  
INT1IC  
14.2 Timer RB  
25  
INT1  
12.2 INT Interrupt  
+104 to +107 (0068h to 006Bh)  
26  
INT3IC  
INT3  
Comparator 0  
Comparator 1  
+108 to +111 (006Ch to 006Fh)  
+112 to +115 (0070h to 0073h)  
+116 to +119 (0074h to 0077h)  
27  
28  
29  
CM0IC  
CM1IC  
INT0IC  
19. Comparator  
INT0  
12.2 INT Interrupt  
(Reserved)  
(Reserved)  
Software interrupt(2)  
30  
31  
+128 to +131 (0080h to 0083h) to 32 to 63  
+252 to +255 (00FCh to 00FFh)  
R8C/Tiny Series Software  
Manual  
NOTES:  
1. These addresses are relative to those in the INTB register.  
2. The I flag does not disable these interrupts.  
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12.Interrupts  
12.1.6 Interrupt Control  
The following describes enabling and disabling the maskable interrupts and setting the priority for  
acknowledgement. The explanation does not apply to nonmaskable interrupts.  
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or  
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control  
register.  
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, CM0IC, and CM1IC  
and Figure 12.5 shows the INTiIC Register (i=0, 1, 3).  
Interrupt Control Register(2)  
Symbol  
TREIC  
Address  
004Ah  
004Dh  
004Eh  
0051h  
0052h  
0056h  
0058h  
After Reset  
XXXXX000b  
XXXXX000b  
XXXXX000b  
XXXXX000b  
XXXXX000b  
XXXXX000b  
XXXXX000b  
KUPIC  
ADIC  
S0TIC  
S0RIC  
TRAIC  
TRBIC  
b7 b6 b5 b4 b3 b2 b1 b0  
Bit Symbol  
ILVL0  
Bit Name  
Interrupt priority level select bits  
Function  
RW  
RW  
b2 b1 b0  
0 0 0 : Level 0 (interrupt disable)  
0 0 1 : Level 1  
0 1 0 : Level 2  
0 1 1 : Level 3  
1 0 0 : Level 4  
1 0 1 : Level 5  
1 1 0 : Level 6  
ILVL1  
RW  
RW  
ILVL2  
IR  
1 1 1 : Level 7  
Interrupt request bit  
0 : Requests no interrupt  
1 : Requests interrupt  
RW(1)  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is undefined.  
NOTES:  
1. Only 0 can be w ritten to the IR bit. Do not w rite 1.  
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for its register is not generated.  
Ref er to  
.
12.6.5 Changing Interrupt Control Register Contents  
Figure 12.3  
Interrupt Control Register  
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12.Interrupts  
Interrupt Control Register(1)  
Symbol  
TRCIC  
Address  
0047h  
After Reset  
XXXXX000b  
b7 b6 b5 b4 b3 b2 b1 b0  
CM0IC  
CM1IC  
005Bh  
005Ch  
XXXXX000b  
XXXXX000b  
Function  
Bit Symbol  
Bit Name  
Interrupt priority level select bits  
RW  
RW  
b2 b1 b0  
0 0 0 : Level 0 (interrupt disable)  
0 0 1 : Level 1  
0 1 0 : Level 2  
0 1 1 : Level 3  
1 0 0 : Level 4  
1 0 1 : Level 5  
1 1 0 : Level 6  
1 1 1 : Level 7  
ILVL0  
ILVL1  
RW  
RW  
ILVL2  
IR  
Interrupt request bit  
0 : Requests no interrupt  
1 : Requests interrupt  
RO  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is undefined.  
NOTE:  
1. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.  
Ref er to  
.
12.6.5 Changing Interrupt Control Register Contents  
Figure 12.4  
Registers TRCIC, CM0IC, and CM1IC  
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12.Interrupts  
INTi Interrupt Control Register (i=0, 1, 3)(2)  
Symbol  
Address  
0059h  
After Reset  
XX00X000b  
INT1IC  
b7 b6 b5 b4 b3 b2 b1 b0  
0
INT3IC  
005Ah  
XX00X000b  
INT0IC  
005Dh  
Bit Name  
XX00X000b  
Function  
Bit Symbol  
RW  
RW  
b2 b1 b0  
Interrupt priority level select bits  
0 0 0 : Level 0 (interrupt disable)  
0 0 1 : Level 1  
0 1 0 : Level 2  
0 1 1 : Level 3  
1 0 0 : Level 4  
1 0 1 : Level 5  
1 1 0 : Level 6  
1 1 1 : Level 7  
ILVL0  
ILVL1  
ILVL2  
RW  
RW  
Interrupt request bit  
Polarity sw itch bit(4)  
Reserved bit  
0 : Requests no interrupt  
1 : Requests interrupt  
IR  
RW(1)  
RW  
RW  
0 : Selects falling edge  
1 : Selects rising edge(3)  
POL  
(b5)  
Set to 0.  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is undefined.  
NOTES:  
1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.)  
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.  
Ref er to  
.
12.6.5 Changing Interrupt Control Register Contents  
3. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).  
4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to  
12.6.4 Changing Interrupt  
Sources.  
Figure 12.5  
INTiIC Register (i=0, 1, 3)  
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12.Interrupts  
12.1.6.1 I Flag  
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.  
Setting the I flag to 0 (disabled) disables all maskable interrupts.  
12.1.6.2 IR Bit  
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt  
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=  
interrupt not requested).  
The IR bit can be set to 0 by a program. Do not write 1 to this bit.  
However, the IR bit operations of the timer RC interrupt, comparator 0 interrupt, and comparator 1 interrupt are  
different. Refer to 12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt.  
12.1.6.3 ILVL2 to ILVL0 Bits and IPL  
Interrupt priority levels can be set using bits ILVL2 to ILVL0.  
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels  
Enabled by IPL.  
The following are conditions under which an interrupt is acknowledged:  
I flag = 1  
IR bit = 1  
Interrupt priority level > IPL  
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.  
Table 12.3  
Settings of Interrupt Priority  
Levels  
Table 12.4  
Interrupt Priority Levels Enabled by  
IPL  
ILVL2 to ILVL0 Bits  
Interrupt Priority Level  
Priority Order  
IPL  
000b  
Enabled Interrupt Priority Levels  
Interrupt level 1 and above  
Interrupt level 2 and above  
Interrupt level 3 and above  
Interrupt level 4 and above  
Interrupt level 5 and above  
Interrupt level 6 and above  
Interrupt level 7 and above  
All maskable interrupts are disabled  
000b  
001b  
010b  
011b  
100b  
101b  
110b  
111b  
Level 0 (interrupt disabled)  
Level 1  
Level 2  
Level 3  
Level 4  
Level 5  
Level 6  
Level 7  
Low  
001b  
010b  
011b  
100b  
101b  
110b  
High  
111b  
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12.Interrupts  
12.1.6.4 Interrupt Sequence  
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine  
execution.  
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt  
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.  
However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the  
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt  
sequence is performed as indicated below.  
Figure 12.6 shows the Time Required for Executing Interrupt Sequence.  
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address  
(2)  
00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).  
(1)  
(2) The FLG register is saved to a temporary register in the CPU immediately before entering the  
interrupt sequence.  
(3) The I, D and U flags in the FLG register are set as follows:  
The I flag is set to 0 (interrupts disabled).  
The D flag is set to 0 (single-step interrupt disabled).  
The U flag is set to 0 (ISP selected).  
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63  
is executed.  
(1)  
(4) The CPU’s internal temporary register is saved to the stack.  
(5) The PC is saved to the stack.  
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.  
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.  
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt  
routine.  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
CPU Clock  
Address Bus  
Data Bus  
RD  
Address  
0000h  
Undefined  
SP-2 SP-1 SP-4  
SP-3  
VEC  
VEC+1  
VEC+2  
PC  
Interrupt  
information  
SP-3  
contents  
VEC+1  
contents  
VEC+2  
contents  
SP-2  
SP-1  
SP-4  
VEC  
contents  
Undefined  
Undefined  
contents contents contents  
WR  
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is  
ready to acknowledge instructions.  
Figure 12.6  
Time Required for Executing Interrupt Sequence  
NOTES:  
1. This register cannot be used by user.  
2. Refer to 12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt for the  
IR bit operations of the timer RC interrupt, comparator 0 interrupt, and comparator 1 interrupt.  
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12.Interrupts  
12.1.6.5 Interrupt Response Time  
Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt  
request generation and the execution of the first instruction in the interrupt routine. The interrupt response time  
includes the period between interrupt request generation and the completion of execution of the instruction  
(refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in  
Figure 12.7).  
Interrupt request is generated. Interrupt request is acknowledged.  
Time  
Instruction in  
interrupt routine  
Instruction  
Interrupt sequence  
(a)  
20 cycles (b)  
Interrupt response time  
(a) Period between interrupt request generation and the completion of execution of an  
instruction. The length of time varies depending on the instruction being executed. The  
DIVX instruction requires the longest time, 30 cycles (no wait and when the register is set  
as the divisor)  
(b) 21 cycles for address match and single-step interrupts.  
Figure 12.7  
Interrupt Response Time  
12.1.6.6 IPL Change when Interrupt Request is Acknowledged  
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the  
acknowledged interrupt is set in the IPL.  
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the  
IPL.  
Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.  
Table 12.5  
IPL Value When Software or Special Interrupt Is Acknowledged  
Interrupt Source Value Set in IPL  
Watchdog timer, oscillation stop detection, voltage monitor 1,  
voltage monitor 2, address break  
7
Software, address match, single-step  
Not changed  
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12.Interrupts  
12.1.6.7 Saving a Register  
In the interrupt sequence, the FLG register and PC are saved to the stack.  
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG  
register, are saved to the stack, the 16 low-order bits in the PC are saved.  
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.  
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM  
(1)  
instruction can save several registers in the register bank being currently used with a single instruction.  
NOTE:  
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.  
Stack  
Stack  
Address  
Address  
MSB  
LSB  
MSB  
LSB  
[SP]  
New SP value  
m4  
m3  
m4  
m3  
PCL  
PCM  
m2  
m1  
m
m2  
FLGL  
m1  
FLGH  
PCH  
[SP]  
m
SP value before  
interrupt is generated  
Previous stack contents  
Previous stack contents  
Previous stack contents  
Previous stack contents  
PCH  
PCM  
PCL  
: 4 High-order bits of PC  
: 8 Middle-order bits of PC  
: 8 Low-order bits of PC  
m+1  
m+1  
FLGH : 4 High-order bits of FLG  
FLGL : 8 Low-order bits of FLG  
Stack state before interrupt request  
is acknowledged  
Stack state after interrupt request  
is acknowledged  
NOTE:  
1.When executing software number 32 to 63 INT instructions,  
this SP is specified by the U flag. Otherwise it is ISP.  
Figure 12.8  
Stack State Before and After Acknowledgement of Interrupt Request  
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in  
four steps.  
Figure 12.9 shows the Register Saving Operation.  
Stack  
Address  
Sequence in which  
order registers are  
saved  
[SP]5  
[SP]4  
[SP]3  
(3)  
(4)  
PCL  
PCM  
Saved, 8 bits at a time  
[SP]2  
[SP]1  
(1)  
(2)  
FLGL  
FLGH  
PCH  
PCH  
PCM  
PCL  
: 4 High-order bits of PC  
: 8 Middle-order bits of PC  
: 8 Low-order bits of PC  
[SP]  
FLGH : 4 High-order bits of FLG  
FLGL : 8 Low-order bits of FLG  
Completed saving  
registers in four  
operations.  
NOTE:  
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.  
After registers are saved, the SP content is [SP] minus 4. When executing  
software number 32 to 63 INT instructions, this SP is specified by the U  
flag. Otherwise it is ISP.  
Figure 12.9  
Register Saving Operation  
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12.Interrupts  
12.1.6.8 Returning from an Interrupt Routine  
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have  
been saved to the stack, are automatically restored. The program, that was running before the interrupt request  
was acknowledged, starts running again.  
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before  
executing the REIT instruction.  
12.1.6.9 Interrupt Priority  
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with  
the higher priority is acknowledged.  
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).  
However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by  
hardware, and the higher priority interrupts acknowledged.  
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set  
by hardware.  
Figure 12.10 shows the Priority Levels of Hardware Interrupts.  
The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the  
instruction is executed.  
High  
Reset  
Address break  
Watchdog timer  
Oscillation stop detection  
Voltage monitor 1  
Voltage monitor 2  
Peripheral function  
Single step  
Address match  
Low  
Figure 12.10 Priority Levels of Hardware Interrupts  
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12.Interrupts  
12.1.6.10 Interrupt Priority Judgement Circuit  
The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11.  
Priority level of interrupt  
Highest  
Level 0 (default value)  
Comparator 0  
INT3  
Timer RB  
Timer RA  
INT0  
Comparator 1  
Priority of peripheral function interrupts  
(if priority levels are same)  
INT1  
Timer RC  
UART0 receive  
A/D conversion  
Timer RE  
UART0 transmit  
Key input  
Lowest  
IPL  
Interrupt request level  
judgment output signal  
Interrupt request  
acknowledged  
I flag  
Address match  
Watchdog timer  
Oscillation stop detection  
Voltage monitor 1  
Voltage monitor 2  
Figure 12.11 Interrupt Priority Level Judgement Circuit  
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12.Interrupts  
12.2 INT Interrupt  
12.2.1 INTi Interrupt (i = 0, 1, 3)  
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN  
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the  
POL bit in the INTiIC register.  
Inputs can be passed through a digital filter with three different sampling clocks.  
The INT0 pin is shared with the pulse output forced cutoff of timer RC and is shared with the external trigger  
input of timer RB.  
Figure 12.12 shows the INTEN Register. Figure 12.13 shows the INTF Register.  
External Input Enable Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
INTEN  
Address  
00F9h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
____  
0 : Disable  
1 : Enable  
INT0 input enable bit  
INT0EN  
INT0PL  
INT1EN  
INT1PL  
____  
INT0 input polarity select bit(1,2)  
0 : One edge  
1 : Both edges  
RW  
RW  
RW  
RW  
RW  
RW  
____  
0 : Disable  
1 : Enable  
INT1 input enable bit  
____  
INT1 input polarity select bit(1,2)  
0 : One edge  
1 : Both edges  
(b5-b4)  
Reserved bits  
Set to 0.  
____  
0 : Disable  
1 : Enable  
INT3 input enable bit  
INT3EN  
INT3PL  
____  
INT3 input polarity select bit(1,2)  
0 : One edge  
1 : Both edges  
NOTES:  
1. When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling  
edge).  
2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to  
12.6.4  
Changing Interrupt Sources.  
Figure 12.12 INTEN Register  
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12.Interrupts  
_______  
INT0 Input Filter Select Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
00FAh  
After Reset  
00h  
INTF  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
_____  
b1 b0  
INT0 input filter select bits  
0 0 : No filter  
INT0F0  
INT0F1  
INT1F0  
INT1F1  
0 1 : Filter w ith f1 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
RW  
RW  
_____  
b3 b2  
INT1 input filter select bits  
0 0 : No filter  
0 1 : Filter w ith f1 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
RW  
RW  
RW  
(b5-b4)  
Reserved bits  
Set to 0.  
_____  
b7 b6  
INT3 input filter select bits  
0 0 : No filter  
INT3F0  
INT3F1  
0 1 : Filter w ith f1 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
RW  
Figure 12.13 INTF Register  
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12.Interrupts  
12.2.2 INTi Input Filter (i = 0, 1, 3)  
The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF  
register. The IR bit in the INTiIC register is set to 1 (interrupt requested) when the INTi level is sampled for  
every sampling clock and the sampled input level matches three times.  
Figure 12.14 shows the Configuration of INTi Input Filter. Figure 12.15 shows an Operating Example of INTi  
Input Filter.  
INTiF1 to INTiF0  
= 01b  
f1  
Sampling clock  
= 10b  
f8  
= 11b  
INTiEN  
f32  
Other than  
INTiF1 to INTiF0  
= 00b  
INTi  
INTi interrupt  
Digital filter  
(input level  
matches 3x)  
Port direction  
register(1)  
= 00b  
INTiPL = 0  
INTiPL = 1  
Both edges  
detection  
circuit  
INTiF0, INTiF1: Bits in INTF register  
INTiEN, INTiPL: Bits in INTEN register  
i = 0, 1, 3  
NOTE:  
1. INT0: Port P4_5 direction register  
INT1: Port P1_5 direction register when using the P1_5 pin  
Port P1_7 direction register when using the P1_7 pin  
INT3: Port P3_3 direction register  
Figure 12.14 Configuration of INTi Input Filter  
INTi input  
Sampling  
timing  
IR bit in  
INTiIC register  
Set to 0 in program  
This is an operation example when bits INTiF1 to INTiF0 in the  
INTiF register are set to 01b, 10b, or 11b (passing digital filter).  
i = 0, 1, 3  
Figure 12.15 Operating Example of INTi Input Filter  
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12.Interrupts  
12.3 Key Input Interrupt  
A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt  
can be used as a key-on wake-up function to exit wait or stop mode.  
The KIiEN (i = 0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in  
the KIEN register can select the input polarity.  
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to  
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising  
edge), the input of the other pins K10 to K13 is not detected as interrupts.  
Figure 12.16 shows a Block Diagram of Key Input Interrupt.  
PU02 bit in PUR0 register  
KUPIC register  
Pull-up  
transistor  
PD1_3 bit in PD1 register  
KI3EN bit  
PD1_3 bit  
KI3PL = 0  
KI3  
KI3PL = 1  
KI2EN bit  
Pull-up  
transistor  
PD1_2 bit  
KI2PL = 0  
Interrupt control  
circuit  
Key input interrupt  
request  
KI2  
KI1  
KI0  
KI2PL = 1  
KI1EN bit  
PD1_1 bit  
Pull-up  
transistor  
KI1PL = 0  
KI1PL = 1  
KI0EN, KI1EN, KI2EN, KI3EN,  
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register  
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register  
KI0EN bit  
PD1_0 bit  
Pull-up  
transistor  
KI0PL = 0  
KI0PL = 1  
Figure 12.16 Block Diagram of Key Input Interrupt  
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12.Interrupts  
Key Input Enable Register(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
KIEN  
Address  
00FBh  
After Reset  
00h  
Bit Symbol  
Bit Name  
KI0 input enable bit  
Function  
RW  
RW  
0 : Disable  
1 : Enable  
KI0EN  
KI0PL  
KI1EN  
KI1PL  
KI2EN  
KI2PL  
KI3EN  
KI0 input polarity select bit  
KI1 input enable bit  
0 : Falling edge  
1 : Rising edge  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0 : Disable  
1 : Enable  
KI1 input polarity select bit  
KI2 input enable bit  
0 : Falling edge  
1 : Rising edge  
0 : Disable  
1 : Enable  
KI2 input polarity select bit  
KI3 input enable bit  
0 : Falling edge  
1 : Rising edge  
0 : Disable  
1 : Enable  
KI3 input polarity select bit  
0 : Falling edge  
1 : Rising edge  
KI3PL  
NOTE:  
1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten.  
Ref er to  
12.6.4 Changing Interrupt Sources.  
Figure 12.17 KIEN Register  
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12.Interrupts  
12.4 Address Match Interrupt  
An address match interrupt request is generated immediately before execution of the instruction at the address  
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When  
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and  
fixed vector tables) in a user system.  
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can  
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.  
The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when  
an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the  
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match  
interrupt, return by one of the following means:  
Change the content of the stack and use the REIT instruction.  
Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged.  
Then use a jump instruction.  
Table 12.6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged, Table 12.7 lists  
the Correspondence Between Address Match Interrupt Sources and Associated Registers.  
Figure 12.18 shows Registers AIER and RMAD0 to RMAD1.  
Table 12.6  
Values of PC Saved to Stack when Address Match Interrupt is Acknowledged  
(1)  
Address Indicated by RMADi Register (i = 0 or 1)  
PC Value Saved  
(2)  
Address indicated by  
RMADi register + 2  
• Instruction with 2-byte operation code  
• Instruction with 1-byte operation code  
(2)  
ADD.B:S  
OR.B:S  
STNZ  
CMP.B:S  
JMPS  
#IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest  
#IMM8,dest MOV.B:S #IMM8,dest STZ  
#IMM8,dest STZX #IMM81,#IMM82,dest  
#IMM8,dest PUSHM src POPM  
#IMM8 JSRS #IMM8  
#IMM,dest (however, dest = A0 or A1)  
#IMM8,dest  
dest  
MOV.B:S  
• Instructions other than the above  
Address indicated by  
RMADi register + 1  
NOTES:  
1. Refer to the 12.1.6.7 Saving a Register for the PC value saved.  
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).  
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing  
operation code below each syntax. Operation code is shown in the bold frame in  
the diagrams.  
Table 12.7  
Correspondence Between Address Match Interrupt Sources and Associated Registers  
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register  
Address match interrupt 0  
Address match interrupt 1  
AIER0  
AIER1  
RMAD0  
RMAD1  
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12.Interrupts  
Address Match Interrupt Enable Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
AIER  
Address  
0013h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Address match interrupt 0 enable bit 0 : Disable  
1 : Enable  
AIER0  
AIER1  
Address match interrupt 1 enable bit 0 : Disable  
1 : Enable  
RW  
(b7-b2)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Address Match Interrupt Register i(i = 0 or 1)  
(b23)  
b7  
(b19)  
b3  
(b16) (b15)  
b0 b7  
(b8)  
b0 b7  
b0  
Symbol  
RMAD0  
RMAD1  
Address  
0012h-0010h  
0016h-0014h  
After Reset  
000000h  
000000h  
Function  
Setting Range  
RW  
Address setting register for address match interrupt  
00000h to FFFFFh  
RW  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
(b7-b4)  
Figure 12.18 Registers AIER and RMAD0 to RMAD1  
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12.Interrupts  
12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt  
As with other maskable interrupts, the timer RC interrupt, comparator 0 interrupt, and comparator 1 interrupt are  
controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, some differences from  
other maskable interrupts apply.  
Refer to chapters of the individual peripheral functions (14.3 Timer RC and 19.4 Comparator 0 Interrupt and  
Comparator 1 Interrupt) for the status register and enable register.  
Refer to 12.1.6 Interrupt Control for the interrupt control register.  
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12.Interrupts  
12.6 Notes on Interrupts  
12.6.1 Reading Address 00000h  
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads  
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At  
this time, the acknowledged interrupt IR bit is set to 0.  
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the  
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be  
generated.  
12.6.2 SP Setting  
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an  
interrupt is acknowledged before setting a value in the SP, the program may run out of control.  
12.6.3 External Interrupt and Key Input Interrupt  
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input  
to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.  
For details, refer to Table 21.19 (VCC = 5V), Table 21.25 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3)  
Input.  
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12.Interrupts  
12.6.4 Changing Interrupt Sources  
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source  
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.  
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to  
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral  
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after  
the change. Refer to the individual peripheral function for its related interrupts.  
Figure 12.19 shows an Example of Procedure for Changing Interrupt Sources.  
Interrupt source change  
Disable interrupts(2, 3)  
Change interrupt source (including mode  
of peripheral function)  
Set the IR bit to 0 (interrupt not requested)  
using the MOV instruction(3)  
Enable interrupts(2, 3)  
Change completed  
IR bit:  
The interrupt control register bit of an  
interrupt whose source is changed.  
NOTES:  
1. Execute the above settings individually. Do not execute two  
or more settings at once (by one instruction).  
2. To prevent interrupt requests from being generated, disable  
the peripheral function before changing the interrupt  
source. In this case, use the I flag if all maskable interrupts  
can be disabled. If all maskable interrupts cannot be  
disabled, use bits ILVL0 to ILVL2 of the interrupt whose  
source is changed.  
3. Refer to 12.6.5 Changing Interrupt Control Register  
Contents for the instructions to be used and usage notes.  
Figure 12.19 Example of Procedure for Changing Interrupt Sources  
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12.Interrupts  
12.6.5 Changing Interrupt Control Register Contents  
(a) The contents of an interrupt control register can only be changed while no interrupt requests  
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts  
before changing the interrupt control register contents.  
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to  
choose appropriate instructions.  
Changing any bit other than IR bit  
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit  
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a  
problem, use the following instructions to change the register: AND, OR, BCLR, BSET  
Changing IR bit  
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.  
Therefore, use the MOV instruction to set the IR bit to 0.  
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer  
to (b) regarding changing the contents of interrupt control registers by the sample programs.  
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt  
control register is changed for reasons of the internal bus or the instruction queue buffer.  
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register  
is changed  
INT_SWITCH1:  
FCLR  
I
; Disable interrupts  
AND.B #00H,0056H  
NOP  
NOP  
; Set TRAIC register to 00h  
;
FSET  
I
; Enable interrupts  
Example 2: Use dummy read to delay FSET instruction  
INT_SWITCH2:  
FCLR  
AND.B #00H,0056H  
MOV.W MEM,R0  
I
; Disable interrupts  
; Set TRAIC register to 00h  
; Dummy read  
FSET  
I
; Enable interrupts  
Example 3: Use POPC instruction to change I flag  
INT_SWITCH3:  
PUSHC FLG  
FCLR  
AND.B #00H,0056H  
POPC FLG  
I
; Disable interrupts  
; Set TRAIC register to 00h  
; Enable interrupts  
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13. Watchdog Timer  
13. Watchdog Timer  
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is  
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows  
selection of count source protection mode enable or disable.  
Table 13.1 lists the Specifications for Watchdog Timer.  
Refer to 5.5 Watchdog Timer Reset for details on the watchdog timer.  
Figure 13.1 shows the Block Diagram of Watchdog Timer, Figure 13.2 shows the Registers WDTR, WDTS, and WDC  
and Figure 13.3 shows the Registers CSPR and OFS.  
Table 13.1  
Item  
Specifications for Watchdog Timer  
Count Source Protection Mode Disabled Count Source Protection Mode Enabled  
Count source  
CPU clock  
Decrement  
Low-speed on-chip oscillator clock  
Count operation  
Count start condition Either of the following can be selected  
• After reset, count starts automatically  
• Count starts by writing to WDTS register  
Count stop condition Stop mode, wait mode  
None  
Reset condition of  
watchdog timer  
• Reset  
• Write 00h to the WDTR register before writing FFh  
• Underflow  
Operation at the time Watchdog timer interrupt or watchdog  
Watchdog timer reset  
of underflow  
timer reset  
Select functions  
• Division ratio of prescaler  
Selected by the WDC7 bit in the WDC register  
• Count source protection mode  
Whether count source protection mode is enabled or disabled after a reset can  
be selected by the CSPROINI bit in the OFS register (flash memory). If count  
source protection mode is disabled after a reset, it can be enabled or disabled  
by the CSPRO bit in the CSPR register (program).  
• Starts or stops of the watchdog timer after a reset  
Selected by the WDTON bit in the OFS register (flash memory).  
Prescaler  
WDC7 = 0  
1/16  
CSPRO = 0  
PM12 = 0  
Watchdog timer  
interrupt request  
CPU clock  
1/128  
Watchdog timer  
WDC7 = 1  
PM12 = 1  
Watchdog  
timer reset  
fOCO-S  
CSPRO = 1  
Set to  
7FFFh(1)  
Write to WDTR register  
Internal reset signal  
CSPRO: Bit in CSPR register  
WDC7: Bit in WDC register  
PM12: Bit in PM1 register  
NOTE:  
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.  
Figure 13.1  
Block Diagram of Watchdog Timer  
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Watchdog Timer Reset Register  
13. Watchdog Timer  
b7  
b0  
Symbol  
WDTR  
Address  
000Dh  
After Reset  
Undefined  
Function  
RW  
WO  
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)  
The default value of the w atchdog timer is 7FFFh w hen count source protection  
mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)  
NOTES:  
1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten.  
2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),  
0FFFh is set in the w atchdog timer.  
Watchdog Timer Start Register  
b7  
b0  
Symbol  
WDTS  
Address  
000Eh  
After Reset  
Undefined  
Function  
The w atchdog timer starts counting after a w rite instruction to this register.  
RW  
WO  
Watchdog Timer Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
000Fh  
After Reset  
00X11111b  
Function  
WDC  
Bit Symbol  
Bit Name  
RW  
RO  
(b4-b0)  
High-order bits of w atchdog timer  
(b5)  
Reserved bit  
Set to 0. When read, the content is undefined.  
Set to 0.  
RW  
RW  
RW  
(b6)  
Reserved bit  
Prescaler select bit  
0 : Divide-by-16  
1 : Divide-by-128  
WDC7  
Figure 13.2  
Registers WDTR, WDTS, and WDC  
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13. Watchdog Timer  
Count Source Protection Mode Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0 0 0 0 0  
Symbol  
CSPR  
Address  
001Ch  
After Reset(1)  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
(b6-b0)  
Reserved Bits  
Set to 0.  
Count Source Protection Mode 0 : Count source protection mode disabled  
Select Bit(2)  
1 : Count source protection mode enabled  
CSPRO  
RW  
NOTES:  
1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.  
2. Write 0 before w riting 1 to set the CSPRO bit to 1.  
0 cannot be set by a program.  
Option Function Select Register(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
1 0 1  
1
Symbol  
OFS  
Address  
0FFFFh  
When Shipping  
FFh(2)  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Watchdog timer start  
select bit  
0 : Starts w atchdog timer automatically after reset  
1 : Watchdog timer is inactive after reset  
WDTON  
(b1)  
Reserved bit  
Set to 1.  
RW  
RW  
RW  
RW  
RW  
RW  
ROM code protect  
disabled bit  
0 : ROM code protect disabled  
1 : ROMCP1 enabled  
ROMCR  
ROM code protect bit  
0 : ROM code protect enabled  
1 : ROM code protect disabled  
ROMCP1  
(b4)  
Reserved bit  
Set to 1.  
(b5)  
Reserved bit  
Set to 0.  
(b6)  
Reserved bit  
Set to 1.  
Count source protect  
0 : Count source protect mode enabled after reset  
mode after reset select 1 : Count source protect mode disabled after reset  
bit  
CSPROINI  
RW  
NOTES:  
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not  
w rite additions to the OFS register.  
2. If the block including the OFS register is erased, FFh is set to the OFS register.  
Figure 13.3  
Registers CSPR and OFS  
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13. Watchdog Timer  
13.1 Count Source Protection Mode Disabled  
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.  
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).  
Table 13.2  
Watchdog Timer Specifications (with Count Source Protection Mode Disabled)  
Item Specification  
Count source  
CPU clock  
Decrement  
Count operation  
Period  
(1)  
Division ratio of prescaler (n) × count value of watchdog timer (32768)  
CPU clock  
n: 16 or 128 (selected by WDC7 bit in WDC register)  
Example: When the CPU clock frequency is 16 MHz and prescaler  
divides by 16, the period is approximately 32.8 ms  
Reset condition of watchdog  
timer  
• Reset  
• Write 00h to the WDTR register before writing FFh  
• Underflow  
(2)  
Count start condition  
The WDTON bit in the OFS register (0FFFFh) selects the operation  
of the watchdog timer after a reset  
• When the WDTON bit is set to 1 (watchdog timer is in stop state after  
reset)  
The watchdog timer and prescaler stop after a reset and the count  
starts when the WDTS register is written to  
• When the WDTON bit is set to 0 (watchdog timer starts automatically  
after exiting)  
• The watchdog timer and prescaler start counting automatically after a  
reset  
Count stop condition  
Stop and wait modes (inherit the count from the held value after exiting  
modes)  
Operation at time of underflow • When the PM12 bit in the PM1 register is set to 0  
Watchdog timer interrupt  
• When the PM12 bit in the PM1 register is set to 1  
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)  
NOTES:  
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is  
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the  
prescaler.  
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address  
0FFFFh with a flash programmer.  
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13. Watchdog Timer  
13.2 Count Source Protection Mode Enabled  
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection  
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the  
watchdog timer.  
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).  
Table 13.3  
Watchdog Timer Specifications (with Count Source Protection Mode Enabled)  
Item Specification  
Low-speed on-chip oscillator clock  
Count source  
Count operation  
Period  
Decrement  
Count value of watchdog timer (4096)  
Low-speed on-chip oscillator clock  
Example: Period is approximately 32.8 ms when the low-speed on-  
chip oscillator clock frequency is 125 kHz  
Reset condition of watchdog  
timer  
• Reset  
• Write 00h to the WDTR register before writing FFh  
• Underflow  
(1)  
Count start condition  
The WDTON bit in the OFS register (0FFFFh) selects the operation  
of the watchdog timer after a reset.  
• When the WDTON bit is set to 1 (watchdog timer is in stop state  
after reset)  
The watchdog timer and prescaler stop after a reset and the count  
starts when the WDTS register is written to  
• When the WDTON bit is set to 0 (watchdog timer starts  
automatically after reset)  
The watchdog timer and prescaler start counting automatically after  
a reset  
Count stop condition  
None (The count does not stop in wait mode after the count starts.  
The MCU does not enter stop mode.)  
Operation at time of underflow  
Registers, bits  
Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.)  
• When setting the CSPPRO bit in the CSPR register to 1 (count  
(2)  
source protection mode is enabled) , the following are set  
automatically  
- Set 0FFFh to the watchdog timer  
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip  
oscillator on)  
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is  
reset when watchdog timer underflows)  
• The following conditions apply in count source protection mode  
- Writing to the CM10 bit in the CM1 register is disabled (It remains  
unchanged even if it is set to 1. The MCU does not enter stop  
mode.)  
- Writing to the CM14 bit in the CM1 register is disabled (It remains  
unchanged even if it is set to 1. The low-speed on-chip oscillator  
does not stop.)  
NOTES:  
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address  
0FFFFh with a flash programmer.  
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The  
CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address  
0FFFFh with a flash programmer.  
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14.Timers  
14. Timers  
The MCU has two 8-bit timers with 8-bit prescalers, a 16-bit timer, and a timer with a 4-bit counter and an 8-bit  
counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to  
store the default value of the counter. The 16-bit timer is timer RC, and has input capture and output compare  
functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function. All the timers operate  
independently.  
Table 14.1 lists Functional Comparison of Timers.  
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14.Timers  
Table 14.1  
Functional Comparison of Timers  
Item Timer RA  
8-bit timer with 8- 8-bit timer with 8- 16-bit free-run timer (with 4-bit counter  
Timer RB  
Timer RC  
Timer RE  
Configuration  
bit prescaler (with bit prescaler (with input capture and output  
8-bit counter  
reload register)  
reload register)  
compare)  
Count  
Decrement  
Decrement  
Increment  
Increment  
Count source  
• f1  
• f2  
• f1  
• f2  
• f1  
• f2  
• f4  
• f8  
• f8  
• fOCO  
• f8  
• Timer RA  
underflow  
• f4  
• f8  
• f32  
• f32  
• fOCO40M  
• TRCCLK  
Function Timer Mode  
provided  
provided  
provided  
(input capture function,  
output compare function)  
not provided  
Pulse Output Mode provided  
not provided  
not provided  
not provided  
not provided  
not provided  
not provided  
Event Counter  
Mode  
provided  
Pulse Width  
Measurement Mode  
provided  
not provided  
not provided  
provided  
not provided  
not provided  
not provided  
not provided  
not provided  
not provided  
Pulse Period  
Measurement Mode  
provided  
Programmable  
Waveform  
not provided  
Generation Mode  
Programmable  
One-Shot  
generation Mode  
not provided  
provided  
provided  
not provided  
not provided  
not provided  
not provided  
Programmable Wait not provided  
One-Shot  
Generation Mode  
Input Capture Mode not provided  
not provided  
not provided  
provided  
provided  
not provided  
provided  
Output Compare  
Mode  
not provided  
PWM Mode  
not provided  
not provided  
TRAIO  
not provided  
not provided  
provided  
provided  
not provided  
not provided  
PWM2 Mode  
Input Pin  
INT0  
INT0, TRCCLK, TRCTRG  
TRCIOA, TRCIOB,  
TRCIOC, TRCIOD  
Output Pin  
TRAO  
TRAIO  
TRBO  
TRCIOA, TRCIOB,  
TRCIOC, TRCIOD  
TREO  
Related Interrupt  
Timer RA interrupt Timer RB interrupt Compare Match / Input  
Timer RE  
interrupt  
INT1 interrupt  
INT0 interrupt  
Capture A to D interrupt  
Overflow interrupt  
INT0 interrupt  
Timer Stop  
provided  
provided  
provided  
provided  
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14.Timers  
14.1 Timer RA  
Timer RA is an 8-bit timer with an 8-bit prescaler.  
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated  
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.2 to 14.6  
the Specification of Each Modes).  
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting  
and reloading.  
Figure 14.1 shows a Block Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associated with Timer  
RA.  
Timer RA contains the following five operating modes:  
Timer mode:  
The timer counts the internal count source.  
Pulse output mode:  
The timer counts the internal count source and outputs pulses which  
invert the polarity by underflow of the timer.  
Event counter mode:  
The timer counts external pulses.  
Pulse width measurement mode:  
Pulse period measurement mode:  
The timer measures the pulse width of an external pulse.  
The timer measures the pulse period of an external pulse.  
Data bus  
TCK2 to TCK0 bit  
Reload  
register  
Reload  
register  
TCKCUT bit  
TMOD2 to TMOD0  
= other than 010b  
= 000b  
= 001b  
= 010b  
= 011b  
f1  
f8  
fOCO  
f2  
TCSTF bit  
Underflow signal  
Timer RA interrupt  
Counter  
TRAPRE register  
(prescaler)  
Counter  
TRA register  
(timer)  
TMOD2 to TMOD0  
= 010b  
TIPF1 to TIPF0 bits  
= 01b  
f1  
= 10b  
= 11b  
f8  
TMOD2 to TMOD0  
= 011b or 100b  
f32  
TIPF1 to TIPF0 bits  
= other than  
000b  
TIOSEL = 0  
Digital  
filter  
Polarity  
switching  
Count control  
circle  
INT1/TRAIO (P1_7) pin  
INT1/TRAIO (P1_5) pin  
Measurement completion  
signal  
= 00b  
TIOSEL = 1  
TMOD2 to TMOD0 = 001b  
TEDGSEL = 1  
TOPCR bit  
Toggle  
flip-flop  
Q
Q
CK  
CLR  
TOENA bit  
TEDGSEL = 0  
Write to TRAMR register  
Write 1 to TSTOP bit  
TRAO pin  
TCSTF, TSTOP: TRACR register  
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: TRAIOC register  
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: TRAMR register  
Figure 14.1  
Block Diagram of Timer RA  
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14.Timers  
Timer RA Control Register(4)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRACR  
Address  
0100h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Timer RA count start bit(1)  
Function  
RW  
RW  
0 : Count stops  
1 : Count starts  
TSTART  
TCSTF  
TSTOP  
Timer RA count status flag(1) 0 : Count stops  
1 : During count  
RO  
RW  
Timer RA count forcible stop When this bit is set to 1, the count is forcibly  
bit(2)  
stopped. When read, its content is 0.  
(b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Active edge judgment  
flag(3, 5)  
0 : Active edge not received  
1 : Active edge received  
TEDGF  
TUNDF  
RW  
(end of measurement period)  
Timer RA underflow flag(3, 5) 0 : No underflow  
1 : Underflow  
RW  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTES:  
1. Ref er to  
for precautions regarding bits TSTART and TCSTF.  
14.1.6 Notes on Timer RA  
2. When the TSTOPbit is set to 1, bits TSTART and TCSTF and registers TPRAPREand TRA are set to the values after  
a reset.  
3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains  
unchanged w hen 1 is w ritten.  
4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR  
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.  
5. Set to 0 in timer mode, pulse output mode, and event counter mode.  
Timer RA I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRAIOC  
Bit Symbol  
Address  
0101h  
After Reset  
00h  
Function  
Bit Name  
RW  
RW  
TRAIO polarity sw itch bit  
Function varies depending on operating mode.  
TEDGSEL  
TOPCR  
TOENA  
TIOSEL  
TRAIO output control bit  
TRAO output enable bit  
RW  
RW  
RW  
RW  
____  
INT1/TRAIO select bit  
TIPF0  
TIPF1  
TRAIO input filter select bits  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 14.2  
Registers TRACR and TRAIOC  
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14.Timers  
Timer RA Mode Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
Address  
0102h  
After Reset  
00h  
TRAMR  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Timer RA operating mode  
select bits(1)  
b2 b1 b0  
0 0 0 : Timer mode  
TMOD0  
TMOD1  
TMOD2  
0 0 1 : Pulse output mode  
0 1 0 : Event counter mode  
0 1 1 : Pulse w idth measurement mode  
1 0 0 : Pulse period measurement mode  
1 0 1 :  
RW  
1 1 0 : Do not set.  
1 1 1 :  
RW  
(b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Timer RA count source  
b6 b5 b4  
select bits  
0 0 0 : f1  
0 0 1 : f8  
0 1 0 : fOCO  
0 1 1 : f2  
1 0 0 :  
TCK0  
TCK1  
RW  
RW  
1 0 1 : Do not set.  
1 1 0 :  
1 1 1 :  
TCK2  
RW  
RW  
Timer RA count source  
cutoff bit  
0 : Provides count source  
1 : Cuts off count source  
TCKCUT  
NOTE:  
1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.  
Timer RA Prescaler Register  
b7  
b0  
Symbol  
TRAPRE  
Mode  
Address  
0103h  
After Reset  
FFh(1)  
Function  
Counts an internal count source  
Setting Range  
00h to FFh  
00h to FFh  
00h to FFh  
RW  
RW  
RW  
RW  
Timer mode  
Pulse output mode  
Event counter mode  
Counts an external count source  
Pulse w idth  
measurement mode  
Measure pulse w idth of input pulses from  
external (counts internal count source)  
00h to FFh  
00h to FFh  
RW  
RW  
Pulse period  
measurement mode  
Measure pulse period of input pulses from  
external (counts internal count source)  
NOTE:  
1. When the TSTOPbit in the TRACR register is set to 1, the TRAPREregister is set to FFh.  
Timer RA Register  
b7  
b0  
Symbol  
TRA  
Address  
0104h  
After Reset  
FFh(1)  
Mode  
Function  
Counts on underflow of timer RA prescaler  
register  
Setting Range  
RW  
RW  
All modes  
00h to FFh  
NOTE:  
1. When the TSTOPbit in the TRACR register is set to 1, the TRA register is set to FFh.  
Figure 14.3  
Registers TRAMR, TRAPRE, and TRA  
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14.Timers  
14.1.1 Timer Mode  
In this mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode  
Specifications).  
Figure 14.4 shows TRAIOC Register in Timer Mode.  
Table 14.2  
Timer Mode Specifications  
Item  
Specification  
Count sources  
f1, f2, f8, fOCO  
Count operations  
• Decrement  
• When the timer underflows, the contents of the reload register are reloaded  
and the count is continued.  
Divide ratio  
1/(n+1)(m+1)  
n: Value set in TRAPRE register, m: Value set in TRA register  
1 (count starts) is written to the TSTART bit in the TRACR register.  
Count start condition  
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.  
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.  
Interrupt request  
generation timing  
When timer RA underflows [timer RA interrupt].  
INT1/TRAIO pin  
function  
Programmable I/O port, or INT1 interrupt input  
Programmable I/O port  
TRAO pin function  
Read from timer  
Write to timer  
The count value can be read by reading registers TRA and TRAPRE.  
• When registers TRAPRE and TRA are written while the count is stopped,  
values are written to both the reload register and counter.  
• When registers TRAPRE and TRA are written during the count, values are  
written to the reload register and counter (refer to 14.1.1.1 Timer Write  
Control during Count Operation).  
Timer RA I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
0 0 0  
Symbol  
TRAIOC  
Address  
0101h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
TRAIO polarity sw itch bit  
Set to 0 in timer mode.  
TEDGSEL  
TOPCR  
TOENA  
TIOSEL  
TRAIO output control bit  
TRAO output enable bit  
RW  
RW  
RW  
RW  
____  
____  
INT1/TRAIO select bit  
0 : INT1/TRAIO pin (P1_7)  
____  
1 : INT1/TRAIO pin (P1_5)  
TIPF0  
TIPF1  
TRAIO input filter select bits Set to 0 in timer mode.  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 14.4  
TRAIOC Register in Timer Mode  
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14.Timers  
14.1.1.1 Timer Write Control during Count Operation  
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each  
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the  
reload register and counter.  
However, values are transferred from the reload register to the counter of the prescaler in synchronization with  
the count source. In addition, values are transferred from the reload register to the counter of the timer in  
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count  
operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed.  
Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count  
Operation.  
Set 01h to the TRAPRE register and 25h to  
the TRA register by a program.  
Count source  
After writing, the reload register is  
written to at the first count source.  
Reloads register of  
timer RA prescaler  
Previous value  
New value (01h)  
Reload at  
second count  
source  
Reload at  
underflow  
Counter of  
timer RA prescaler  
06h  
05h  
04h  
01h  
00h  
01h  
00h  
01h  
00h  
01h  
00h  
After writing, the reload register is  
written to at the first underflow.  
Reloads register of  
timer RA  
Previous value  
New value (25h)  
Reload at the second underflow  
25h 24h  
Counter of timer RA  
03h  
02h  
IR bit in TRAIC  
register  
0
The IR bit remains unchanged until underflow is  
generated by a new value.  
The above applies under the following conditions.  
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).  
Figure 14.5  
Operating Example of Timer RA when Counter Value is Rewritten during Count  
Operation  
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14.Timers  
14.1.2 Pulse Output Mode  
In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is  
output from the TRAIO pin each time the timer underflows (refer to Table 14.3 Pulse Output Mode  
Specifications).  
Figure 14.6 shows TRAIOC Register in Pulse Output Mode.  
Table 14.3  
Pulse Output Mode Specifications  
Item  
Specification  
Count sources  
f1, f2, f8, fOCO  
Count operations  
• Decrement  
• When the timer underflows, the contents in the reload register is reloaded and  
the count is continued.  
Divide ratio  
1/(n+1)(m+1)  
n: Value set in TRAPRE register, m: Value set in TRA register  
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.  
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.  
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.  
Interrupt request  
generation timing  
When timer RA underflows [timer RA interrupt].  
(1)  
INT1/TRAIO pin  
function  
Pulse output, programmable output port, or INT1 interrupt  
(1)  
Programmable I/O port or inverted output of TRAIO  
TRAO pin function  
The count value can be read by reading registers TRA and TRAPRE.  
Read from timer  
Write to timer  
• When registers TRAPRE and TRA are written while the count is stopped, values  
are written to both the reload register and counter.  
• When registers TRAPRE and TRA are written during the count, values are  
written to the reload register and counter (refer to 14.1.1.1 Timer Write Control  
during Count Operation).  
Select functions  
• TRAIO signal polarity switch function  
The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse  
(1)  
output.  
• TRAO output function  
Pulses inverted from the TRAIO output polarity can be output from the TRAO  
pin (selectable by the TOENA bit in the TRAIOC register).  
• Pulse output stop function  
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.  
• INT1/TRAIO pin select function  
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.  
NOTE:  
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR  
register is written to.  
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14.Timers  
Timer RA I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
0101h  
After Reset  
00h  
TRAIOC  
Bit Symbol  
Bit Name  
TRAIO polarity sw itch bit  
Function  
0 : TRAIO output starts at “H”  
1 : TRAIO output starts at “L”  
RW  
RW  
TEDGSEL  
TOPCR  
TOENA  
TIOSEL  
TRAIO output control bit  
TRAO output enable bit  
0 : TRAIO output  
1 : Port P1_7 or P1_5  
RW  
RW  
RW  
0 : Port P3_7  
1 : TRAO output (inverted TRAIO output from P3_7)  
____  
____  
INT1/TRAIO select bit  
0 : INT1/TRAIO pin (P1_7)  
____  
1 : INT1/TRAIO pin (P1_5)  
TIPF0  
TIPF1  
TRAIO input filter select bits Set to 0 in pulse output mode.  
RW  
RW  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 14.6  
TRAIOC Register in Pulse Output Mode  
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14.Timers  
14.1.3 Event Counter Mode  
In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.4 Event  
Counter Mode Specifications).  
Figure 14.7 shows TRAIOC Register in Event Counter Mode.  
Table 14.4  
Event Counter Mode Specifications  
Item  
Specification  
Count source  
Count operations  
External signal which is input to TRAIO pin (active edge selectable by a program)  
• Decrement  
• When the timer underflows, the contents of the reload register are reloaded and  
the count is continued.  
Divide ratio  
1/(n+1)(m+1)  
n: setting value of TRAPRE register, m: setting value of TRA register  
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.  
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.  
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.  
Interrupt request  
generation timing  
• When timer RA underflows [timer RA interrupt].  
INT1/TRAIO pin  
function  
Count source input  
interrupt input)  
(INT1  
(1)  
Programmable I/O port or pulse output  
TRAO pin function  
Read from timer  
Write to timer  
The count value can be read by reading registers TRA and TRAPRE.  
• When registers TRAPRE and TRA are written while the count is stopped, values  
are written to both the reload register and counter.  
• When registers TRAPRE and TRA are written during the count, values are  
written to the reload register and counter (refer to 14.1.1.1 Timer Write Control  
during Count Operation).  
Select functions  
• INT1 input polarity switch function  
The TEDGSEL bit in the TRAIOC register selects the active edge of the count  
source.  
• Count source input pin select function  
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.  
• Pulse output function  
Pulses of inverted polarity can be output from the TRAO pin each time the timer  
(1)  
underflows (selectable by the TOENA bit in the TRAIOC register).  
• Digital filter function  
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter  
and select the sampling frequency.  
NOTE:  
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR  
register is written to.  
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14.Timers  
Timer RA I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
Address  
0101h  
After Reset  
00h  
TRAIOC  
Bit Symbol  
Bit Name  
TRAIO polarity sw itch bit  
Function  
RW  
RW  
0 : Starts counting at rising edge of the TRAIO  
input or TRAIO starts output at “L”  
1 : Starts counting at falling edge of the TRAIO  
input or TRAIO starts output at “H”  
TEDGSEL  
TRAIO output control bit  
TRAO output enable bit  
Set to 0 in event counter mode.  
TOPCR  
TOENA  
TIOSEL  
RW  
RW  
RW  
0 : Port P3_0  
1 : TRAO output  
____  
____  
INT1/TRAIO select bit  
0 : INT1/TRAIO pin (P1_7)  
____  
1 : INT1/TRAIO pin (P1_5)  
TRAIO input filter select  
bits(1)  
b5 b4  
0 0 : No filter  
TIPF0  
TIPF1  
0 1 : Filter w ith f1 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
RW  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.  
Figure 14.7  
TRAIOC Register in Event Counter Mode  
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14.Timers  
14.1.4 Pulse Width Measurement Mode  
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is  
measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications).  
Figure 14.8 shows TRAIOC Register in Pulse Width Measurement Mode and Figure 14.9 shows an Operating  
Example of Pulse Width Measurement Mode.  
Table 14.5  
Pulse Width Measurement Mode Specifications  
Item Specification  
Count sources  
f1, f2, f8, fOCO  
Count operations  
• Decrement  
• Continuously counts the selected signal only when measurement pulse is “H”  
level, or conversely only “L” level.  
• When the timer underflows, the contents of the reload register are reloaded  
and the count is continued.  
Count start condition  
Count stop conditions  
1 (count starts) is written to the TSTART bit in the TRACR register.  
• 0 (count stops) is written to the TSTART bit in the TRACR register.  
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.  
Interrupt request  
generation timing  
• When timer RA underflows [timer RA interrupt].  
• Rising or falling of the TRAIO input (end of measurement period) [timer RA  
interrupt]  
INT1/TRAIO pin function Measured pulse input  
(INT1 interrupt input)  
Programmable I/O port  
TRAO pin function  
Read from timer  
Write to timer  
The count value can be read by reading registers TRA and TRAPRE.  
• When registers TRAPRE and TRA are written while the count is stopped,  
values are written to both the reload register and counter.  
• When registers TRAPRE and TRA are written during the count, values are  
written to the reload register and counter (refer to 14.1.1.1 Timer Write  
Control during Count Operation).  
Select functions  
• Measurement level select  
The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.  
• Measured pulse input pin select function  
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.  
• Digital filter function  
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital  
filter and select the sampling frequency.  
Rev.1.00 Dec 14, 2007 Page 131 of 332  
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14.Timers  
Timer RA I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
0101h  
After Reset  
00h  
TRAIOC  
Bit Symbol  
Bit Name  
TRAIO polarity sw itch bit  
Function  
0 : TRAIO input starts at “L”  
1 : TRAIO input starts at “H”  
RW  
RW  
TEDGSEL  
TOPCR  
TOENA  
TIOSEL  
TRAIO output control bit  
TRAO output enable bit  
Set to 0 in pulse w idth measurement mode.  
RW  
RW  
RW  
____  
____  
INT1/TRAIO select bit  
0 : INT1/TRAIO pin (P1_7)  
____  
1 : INT1/TRAIO pin (P1_5)  
TRAIO input filter select  
bits(1)  
b5 b4  
0 0 : No filter  
TIPF0  
TIPF1  
0 1 : Filter w ith f1 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
RW  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.  
Figure 14.8  
TRAIOC Register in Pulse Width Measurement Mode  
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14.Timers  
n = high level: the contents of TRA register, low level: the contents of TRAPRE register  
FFFFh  
n
Count start  
Underflow  
Count stop  
Count stop  
Count start  
Count start  
Period  
0000h  
Set to 1 by a program  
1
0
TSTART bit in  
TRACR register  
1
0
Measured pulse  
(TRAIO pin input)  
Set to 0 when interrupt request is acknowledged, or set by a program  
1
0
IR bit in  
TRAIC register  
Set to 0 by a program  
1
0
TEDGF bit in  
TRACR register  
Set to 0 by a program  
1
0
TUNDF bit in  
TRACR register  
The above applies under the following conditions.  
“H” level width of measured pulse is measured. (TEDGSEL = 1)  
TRAPRE = FFh  
Figure 14.9  
Operating Example of Pulse Width Measurement Mode  
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14.Timers  
14.1.5 Pulse Period Measurement Mode  
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is  
measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications).  
Figure 14.10 shows TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an  
Operating Example of Pulse Period Measurement Mode.  
Table 14.6  
Pulse Period Measurement Mode Specifications  
Item Specification  
Count sources  
f1, f2, f8, fOCO  
Count operations  
• Decrement  
• After the active edge of the measured pulse is input, the contents of the read-  
out buffer are retained at the first underflow of timer RA prescaler. Then timer  
RA reloads the contents in the reload register at the second underflow of  
timer RA prescaler and continues counting.  
Count start condition  
Count stop conditions  
1 (count start) is written to the TSTART bit in the TRACR register.  
• 0 (count stop) is written to TSTART bit in the TRACR register.  
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.  
Interrupt request  
generation timing  
• When timer RA underflows or reloads [timer RA interrupt].  
• Rising or falling of the TRAIO input (end of measurement period) [timer RA  
interrupt]  
(1)  
INT1/TRAIO pin function  
Measured pulse input (INT1 interrupt input)  
Programmable I/O port  
TRAO pin function  
Read from timer  
Write to timer  
The count value can be read by reading registers TRA and TRAPRE.  
• When registers TRAPRE and TRA are written while the count is stopped,  
values are written to both the reload register and counter.  
• When registers TRAPRE and TRA are written during the count, values are  
written to the reload register and counter (refer to 14.1.1.1 Timer Write  
Control during Count Operation).  
Select functions  
• Measurement period select  
The TEDGSEL bit in the TRAIOC register selects the measurement period of  
the input pulse.  
• Measured pulse input pin select function  
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.  
• Digital filter function  
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital  
filter and select the sampling frequency.  
NOTE:  
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a  
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to  
the TRAIO pin, the input may be ignored.  
Rev.1.00 Dec 14, 2007 Page 134 of 332  
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14.Timers  
Timer RA I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
0101h  
After Reset  
00h  
TRAIOC  
Bit Symbol  
Bit Name  
TRAIO polarity sw itch bit  
Function  
RW  
RW  
0 : Measures measurement pulse from one  
rising edge to next rising edge  
1 : Measures measurement pulse from one  
falling edge to next falling edge  
TEDGSEL  
TRAIO output control bit  
TRAO output enable bit  
Set to 0 in pulse period measurement mode.  
TOPCR  
TOENA  
TIOSEL  
RW  
RW  
RW  
____  
____  
INT1/TRAIO select bit  
0 : INT1/TRAIO pin (P1_7)  
____  
1 : INT1/TRAIO pin (P1_5)  
TRAIO input filter select  
bits(1)  
b5 b4  
0 0 : No filter  
TIPF0  
TIPF1  
0 1 : Filter w ith f1 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
RW  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.  
Figure 14.10 TRAIOC Register in Pulse Period Measurement Mode  
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14.Timers  
Underflow signal of  
timer RA prescaler  
Set to 1 by a program  
1
TSTART bit in  
TRACR register  
0
Starts counting  
1
0
Measurement pulse  
(TRAIO pin input)  
TRA reloads  
TRA reloads  
Contents of TRA  
0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh  
01h 00h 0Fh 0Eh  
Underflow  
Retained  
0Dh  
Retained  
09h  
Contents of read-out  
buffer(1)  
0Fh 0Eh  
0Bh 0Ah  
0Dh  
01h 00h 0Fh 0Eh  
TRA read(3)  
(Note 2)  
(Note 2)  
(Note 4)  
1
0
TEDGF bit in  
TRACR register  
Set to 0 by a program  
(Note 6)  
1
0
TUNDF bit in  
TRACR register  
Set to 0 by a program  
(Note 5)  
1
0
IR bit in TRAIC  
register  
Set to 0 when interrupt request is acknowledged, or set by a program  
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with  
the default value of the TRA register as 0Fh.  
NOTES:  
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.  
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer  
RA prescaler underflows for the second time.  
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).  
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge  
is input, the measured result of the previous period is retained.  
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the  
TUNDF bit in the TRACR register.  
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.  
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.  
Figure 14.11 Operating Example of Pulse Period Measurement Mode  
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14.Timers  
14.1.6 Notes on Timer RA  
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the  
count starts.  
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by  
the MCU. Consequently, the timer value may be updated during the period when these two registers are  
being read.  
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by  
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the  
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0  
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or  
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.  
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and  
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.  
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.  
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler  
immediately after the count starts, then set the TEDGF bit to 0.  
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1  
(count starts) while the count is stopped.  
During this time, do not access registers associated with timer RA other than the TCSTF bit. Timer RA  
(1)  
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).  
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count  
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.  
(1)  
During this time, do not access registers associated with timer RA other than the TCSTF bit.  
NOTE:  
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.  
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow  
three or more cycles of the count source clock for each write interval.  
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three  
or more cycles of the prescaler underflow for each write interval.  
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14.Timers  
14.2 Timer RB  
Timer RB is an 8-bit timer with an 8-bit prescaler.  
The prescaler and timer each consist of a reload register and counter (refer to Tables 14.7 to 14.10 the  
Specifications of Each Mode).  
Timer RB has timer RB primary and timer RB secondary as reload registers.  
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting  
and reloading.  
Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 and 14.15 show the registers associated with  
timer RB.  
Timer RB has four operation modes listed as follows:  
Timer mode:  
The timer counts an internal count source (peripheral  
function clock or timer RA underflows).  
Programmable waveform generation mode:  
Programmable one-shot generation mode:  
Programmable wait one-shot generation mode:  
The timer outputs pulses of a given width successively.  
The timer outputs a one-shot pulse.  
The timer outputs a delayed one-shot pulse.  
Data bus  
TRBSC  
register  
TRBPR  
register  
Reload  
register  
Reload  
register  
Reload  
register  
TCK1 to TCK0 bits  
TCKCUT bit  
= 00b  
f1  
Timer RB interrupt  
= 01b  
f8  
Timer RA underflow  
f2  
Counter  
Counter (timer RB)  
(Timer)  
= 10b  
= 11b  
TRBPRE register  
(prescaler)  
TMOD1 to TMOD0 bits  
= 10b or 11b  
TSTRAT bit  
TOSSTF bit  
INT0 interrupt  
Input polarity  
selected to be one  
edge or both edges  
INT0 pin  
Digital filter  
Polarity  
select  
INT0PL bit  
INT0EN bit  
INOSEG bit  
INOSTG bit  
TMOD1 to TMOD0 bits  
= 01b, 10b, 11b  
TOPL = 1  
Toggle  
flip-flop  
Q
Q
TOCNT = 0  
CK  
TRBO pin  
CLR  
P3_1 bit in P3 register  
TOPL = 0  
TOCNT = 1  
TCSTF bit  
TMOD1 to TMOD0 bits  
= 01b, 10b, 11b  
TSTART, TCSTF: Bits in TRBCR register  
TOSSTF: Bit in TRBOCR register  
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register  
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register  
Figure 14.12 Block Diagram of Timer RB  
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14.Timers  
Timer RB Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
Address  
0108h  
After Reset  
00h  
TRBCR  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Timer RB count start bit(1)  
0 : Count stops  
1 : Count starts  
TSTART  
TCSTF  
TSTOP  
Timer RB count status flag(1) 0 : Count stops  
1 : During count(3)  
RO  
RW  
Timer RB count forcible stop When this bit is set to 1, the count is forcibly  
bit(1, 2)  
stopped. When read, its content is 0.  
(b7-b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTES:  
1. Ref er to  
for precautions regarding bits TSTART, TCSTF and TSTOP.  
14.2.5 Notes on Timer RB  
2. When the TSTOPbit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit  
in the TRBOCR register are set to values after a reset.  
3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable one-  
shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has  
been acknow ledged.  
Timer RB One-Shot Control Register(2)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRBOCR  
Bit Symbol  
Address  
0109h  
After Reset  
00h  
Bit Name  
Function  
RW  
RW  
Timer RB one-shot start bit When this bit is set to 1, one-shot trigger  
generated. When read, its content is 0.  
TOSST  
TOSSP  
TOSSTF  
Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot  
pulses (including programmable w ait one-shot  
RW  
pulses) stops. When read, its content is 0.  
Timer RB one-shot status  
flag(1)  
0 : One-shot stopped  
1 : One-shot operating (Including w ait period)  
RO  
(b7-b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTES:  
1. When 1 is set to the TSTOPbit in the TRBCR register, the TOSSTF bit is set to 0.  
2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot  
generation mode) or 11b (programmable w ait one-shot generation mode).  
Figure 14.13 Registers TRBCR and TRBOCR  
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14.Timers  
Timer RB I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRBIOC  
Address  
010Ah  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Timer RB output level select Function varies depending on operating mode.  
bit  
TOPL  
Timer RB output sw itch bit  
TOCNT  
INOSTG  
INOSEG  
RW  
RW  
RW  
One-shot trigger control bit  
One-shot trigger polarity  
select bit  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Timer RB Mode Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRBMR  
Address  
010Bh  
After Reset  
00h  
Bit Symbol  
Bit Name  
Timer RB operating mode  
select bits(1)  
Function  
RW  
RW  
b1 b0  
0 0 : Timer mode  
TMOD0  
TMOD1  
0 1 : Programmable w aveform generation mode  
1 0 : Programmable one-shot generation mode  
1 1 : Programmable w ait one-shot generation mode  
RW  
(b2)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Timer RB w rite control bit(2) 0 : Write to reload register and counter  
1 : Write to reload register only  
TWRC  
RW  
Timer RB count source  
select bits(1)  
b5 b4  
0 0 : f1  
TCK0  
RW  
RW  
0 1 : f8  
1 0 : Timer RA underflow  
1 1 : f2  
TCK1  
(b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Timer RB count source  
cutoff bit(1)  
0 : Provides count source  
1 : Cuts off count source  
TCKCUT  
RW  
NOTES:  
1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR  
register set to 0 (count stops).  
2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable  
one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to  
reload register only).  
Figure 14.14 Registers TRBIOC and TRBMR  
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Timer RB Prescaler Register(1)  
14.Timers  
b7  
b0  
Symbol  
TRBPRE  
Mode  
Address  
010Ch  
After Reset  
FFh  
Function  
Counts an internal count source or timer RA  
underflow s  
Setting Range  
00h to FFh  
RW  
RW  
Timer mode  
Programmable w aveform  
generation mode  
00h to FFh  
00h to FFh  
00h to FFh  
RW  
RW  
RW  
Programmable one-shot  
generation mode  
Programmable w ait one-shot  
generation mode  
NOTE:  
1. When the TSTOPbit in the TRBCR register is set to 1, the TRBPREregister is set to FFh.  
Timer RB Secondary Register(3, 4)  
b7  
b0  
Symbol  
TRBSC  
Mode  
Address  
010Dh  
After Reset  
FFh  
Function  
Setting Range  
00h to FFh  
RW  
Disabled  
Timer mode  
Programmable w aveform  
generation mode  
Counts timer RB prescaler underflow s(1)  
Disabled  
00h to FFh  
00h to FFh  
00h to FFh  
WO(2)  
Programmable one-shot  
generation mode  
Programmable w ait one-shot Counts timer RB prescaler underflow s  
generation mode (one-shot w idth is counted)  
WO(2)  
NOTES:  
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.  
2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted.  
3. When the TSTOPbit in the TRBCR register is set to 1, the TRBSC register is set to FFh.  
4. To w rite to the TRBSC register, perform the follow ing steps.  
(1) Write the value to the TRBSC register.  
(2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)  
Timer RB Primary Register(2)  
b7  
b0  
Symbol  
TRBPR  
Mode  
Address  
010Eh  
Function  
After Reset  
FFh  
Setting Range  
00h to FFh  
RW  
RW  
Counts timer RB prescaler underflow s  
Timer mode  
Programmable w aveform  
generation mode  
Counts timer RB prescaler underflow s(1)  
00h to FFh  
00h to FFh  
00h to FFh  
RW  
RW  
RW  
Programmable one-shot  
generation mode  
Counts timer RB prescaler underflow s  
(one-shot w idth is counted)  
Programmable w ait one-shot Counts timer RB prescaler underflow s  
generation mode (w ait period w idth is counted)  
NOTES:  
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.  
2. When the TSTOPbit in the TRBCR register is set to 1, the TRBPR register is set to FFh.  
Figure 14.15 Registers TRBPRE, TRBSC, and TRBPR  
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14.Timers  
14.2.1 Timer Mode  
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table  
14.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.  
Figure 14.16 shows TRBIOC Register in Timer Mode.  
Table 14.7  
Timer Mode Specifications  
Item  
Count sources  
Count operations  
Specification  
f1, f2, f8, timer RA underflow  
• Decrement  
• When the timer underflows, it reloads the reload register contents before the  
count continues (when timer RB underflows, the contents of timer RB primary  
reload register is reloaded).  
Divide ratio  
1/(n+1)(m+1)  
n: setting value in TRBPRE register, m: setting value in TRBPR register  
1 (count starts) is written to the TSTART bit in the TRBCR register.  
Count start condition  
Count stop conditions  
• 0 (count stops) is written to the TSTART bit in the TRBCR register.  
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.  
Interrupt request  
generation timing  
TRBO pin function  
When timer RB underflows [timer RB interrupt].  
Programmable I/O port  
INT0 pin function  
Read from timer  
Write to timer  
Programmable I/O port or INT0 interrupt input  
The count value can be read out by reading registers TRBPR and TRBPRE.  
• When registers TRBPRE and TRBPR are written while the count is stopped,  
values are written to both the reload register and counter.  
• When registers TRBPRE and TRBPR are written to while count operation is in  
progress:  
If the TWRC bit in the TRBMR register is set to 0, the value is written to both  
the reload register and the counter.  
If the TWRC bit is set to 1, the value is written to the reload register only.  
(Refer to 14.2.1.1 Timer Write Control during Count Operation.)  
Timer RB I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0 0  
Symbol  
Address  
010Ah  
After Reset  
00h  
TRBIOC  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Timer RB output level select Set to 0 in timer mode.  
bit  
TOPL  
Timer RB output sw itch bit  
TOCNT  
INOSTG  
INOSEG  
RW  
RW  
RW  
One-shot trigger control bit  
One-shot trigger polarity  
select bit  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 14.16 TRBIOC Register in Timer Mode  
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14.Timers  
14.2.1.1 Timer Write Control during Count Operation  
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each  
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to  
select whether writing to the prescaler or timer during count operation is performed to both the reload register  
and counter or only to the reload register.  
However, values are transferred from the reload register to the counter of the prescaler in synchronization with  
the count source. In addition, values are transferred from the reload register to the counter of the timer in  
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload  
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In  
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be  
shifted if the prescaler value changes. Figure 14.17 shows an Operating Example of Timer RB when Counter  
Value is Rewritten during Count Operation.  
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14.Timers  
When the TWRC bit is set to 0 (write to reload register and counter)  
Set 01h to the TRBPRE register and 25h to  
the TRBPR register by a program.  
Count source  
After writing, the reload register is  
written with the first count source.  
Reloads register of  
Previous value  
New value (01h)  
timer RB prescaler  
Reload with  
the second  
count source  
Reload on  
underflow  
Counter of  
timer RB prescaler  
06h  
05h  
04h  
01h  
00h  
01h  
00h  
01h  
00h  
01h  
00h  
After writing, the reload register is  
written on the first underflow.  
Reloads register of  
timer RB  
Previous value  
New value (25h)  
Reload on the second  
underflow  
Counter of timer RB  
03h  
02h  
25h  
24h  
IR bit in TRBIC  
register  
0
The IR bit remains unchanged until underflow  
is generated by a new value.  
When the TWRC bit is set to 1 (write to reload register only)  
Set 01h to the TRBPRE register and 25h to  
the TRBPR register by a program.  
Count source  
After writing, the reload register is  
written with the first count source.  
Reloads register of  
timer RB prescaler  
Previous value  
New value (01h)  
Reload on  
underflow  
Counter of  
timer RB prescaler  
06h  
05h  
04h  
03h  
02h  
01h  
00h  
01h  
00h  
01h  
00h  
01h  
00h  
01h  
After writing, the reload register is  
written on the first underflow.  
Reloads register of  
timer RB  
Previous value  
New value (25h)  
Reload on  
underflow  
Counter of timer RB  
03h  
02h  
01h  
00h  
25h  
IR bit in TRBIC  
register  
0
Only the prescaler values are updated,  
extending the duration until timer RB underflow.  
The above applies under the following conditions.  
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).  
Figure 14.17 Operating Example of Timer RB when Counter Value is Rewritten during Count  
Operation  
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14.Timers  
14.2.2 Programmable Waveform Generation Mode  
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the  
counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table  
14.8 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting value  
in the TRBPR register. The TRBOCR register is unused in this mode.  
Figure 14.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows an  
Operating Example of Timer RB in Programmable Waveform Generation Mode.  
Table 14.8  
Programmable Waveform Generation Mode Specifications  
Item  
Specification  
Count sources  
f1, f2, f8, timer RA underflow  
Count operations  
• Decrement  
• When the timer underflows, it reloads the contents of the primary reload and  
secondary reload registers alternately before the count continues.  
Width and period of  
output waveform  
Primary period: (n+1)(m+1)/fi  
Secondary period: (n+1)(p+1)/fi  
Period: (n+1){(m+1)+(p+1)}/fi  
fi: Count source frequency  
n: Value set in TRBPRE register  
m: Value set in TRBPR register  
p: Value set in TRBSC register  
Count start condition 1 (count start) is written to the TSTART bit in the TRBCR register.  
Count stop conditions • 0 (count stop) is written to the TSTART bit in the TRBCR register.  
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.  
Interrupt request  
generation timing  
In half a cycle of the count source, after timer RB underflows during the  
secondary period (at the same time as the TRBO output change) [timer RB  
interrupt]  
TRBO pin function  
Programmable output port or pulse output  
INT0 pin function  
Read from timer  
Write to timer  
Programmable I/O port or INT0 interrupt input  
(1)  
The count value can be read out by reading registers TRBPR and TRBPRE  
.
• When registers TRBPRE, TRBSC, and TRBPR are written while the count is  
stopped, values are written to both the reload register and counter.  
• When registers TRBPRE, TRBSC, and TRBPR are written to during count  
(2)  
operation, values are written to the reload registers only.  
Select functions  
• Output level select function  
The TOPL bit in the TRBIOC register selects the output level during primary and  
secondary periods.  
• TRBO pin output switch function  
Timer RB pulse output or P3_1 latch output is selected by the TOCNT bit in the  
(3)  
TRBIOC register.  
NOTES:  
1. Even when counting the secondary period, the TRBPR register may be read.  
2. The set values are reflected in the waveform output beginning with the following primary period after  
writing to the TRBPR register.  
3. The value written to the TOCNT bit is enabled by the following.  
When counting starts.  
When a timer RB interrupt request is generated.  
The contents after the TOCNT bit is changed are reflected from the output of the following  
primary period.  
Rev.1.00 Dec 14, 2007 Page 145 of 332  
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14.Timers  
Timer RB I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
010Ah  
After Reset  
00h  
TRBIOC  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Timer RB output level select 0 : Outputs “H” for primary period  
bit  
Outputs “L” for secondary period  
Outputs “L” w hen the timer is stopped  
1 : Outputs “L” for primary period  
Outputs “H” for secondary period  
Outputs “H” w hen the timer is stopped  
TOPL  
Timer RB output sw itch bit  
0 : Outputs timer RB w aveform  
1 : Outputs value in P3_1 (P1_3) port register  
TOCNT  
INOSTG  
INOSEG  
RW  
RW  
RW  
One-shot trigger control bit Set to 0 in programmable w aveform generation  
mode.  
One-shot trigger polarity  
select bit  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode  
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14.Timers  
Set to 1 by a program  
1
0
TSTART bit in TRBCR  
register  
Count source  
Timer RB prescaler  
underflow signal  
Timer RB secondary reloads  
Timer RB primary reloads  
Counter of timer RB  
01h  
00h  
02h  
01h  
00h  
01h  
00h  
02h  
Set to 0 when interrupt  
request is acknowledged,  
or set by a program.  
1
0
IR bit in TRBIC  
register  
Set to 0 by a program  
1
0
TOPL bit in TRBIO  
register  
Waveform  
output starts  
Waveform output inverted  
Waveform output starts  
1
0
TRBO pin output  
Primary period  
Secondary period  
Primary period  
Initial output is the same level  
as during secondary period.  
The above applies under the following conditions.  
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h  
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)  
Figure 14.19 Operating Example of Timer RB in Programmable Waveform Generation Mode  
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14.Timers  
14.2.3 Programmable One-shot Generation Mode  
In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an  
external trigger input (input to the INT0 pin) (refer to Table 14.9 Programmable One-Shot Generation Mode  
Specifications). When a trigger is generated, the timer starts operating from the point only once for a given  
period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.  
Figure 14.20 shows TRBIOC Register in Programmable One-Shot Generation Mode. Figure 14.21 shows an  
Operating Example of Programmable One-Shot Generation Mode.  
Table 14.9  
Programmable One-Shot Generation Mode Specifications  
Item  
Specification  
Count sources  
f1, f2, f8, timer RA underflow  
Count operations  
• Decrement the setting value in the TRBPR register  
• When the timer underflows, it reloads the contents of the reload register before  
the count completes and the TOSSTF bit is set to 0 (one-shot stops).  
• When the count stops, the timer reloads the contents of the reload register  
before it stops.  
One-shot pulse  
output time  
(n+1)(m+1)/fi  
fi: Count source frequency,  
(2)  
n: Setting value in TRBPRE register, m: Setting value in TRBPR register  
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next  
trigger is generated  
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)  
• Input trigger to the INT0 pin  
Count stop conditions • When reloading completes after timer RB underflows during primary period  
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)  
• When the TSTART bit in the TRBCR register is set to 0 (stops counting)  
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting)  
Interrupt request  
generation timing  
TRBP pin function  
In half a cycle of the count source, after the timer underflows (at the same time as  
the TRBO output ends) [timer RB interrupt]  
Pulse output  
INT0 pin functions  
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger  
disabled): programmable I/O port or INT0 interrupt input  
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger  
enabled): external trigger (INT0 interrupt input)  
Read from timer  
Write to timer  
The count value can be read out by reading registers TRBPR and TRBPRE.  
• When registers TRBPRE and TRBPR are written while the count is stopped,  
values are written to both the reload register and counter.  
• When registers TRBPRE and TRBPR are written during the count, values are  
written to the reload register only (the data is transferred to the counter at the  
(1)  
following reload)  
.
Select functions  
• Output level select function  
The TOPL bit in the TRBIOC register selects the output level of the one-shot  
pulse waveform.  
• One-shot trigger select function  
Refer to 14.2.3.1 One-Shot Trigger Selection.  
NOTES:  
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.  
2. Do not set both the TRBPRE and TRBPR registers to 00h.  
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14.Timers  
Timer RB I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
Address  
010Ah  
After Reset  
00h  
TRBIOC  
Bit Symbol  
Bit Name  
Timer RB Output Level  
Select Bit  
Function  
0 : Outputs one-shot pulse “H”  
Outputs “L” w hen the timer is stopped  
1 : Outputs one-shot pulse “L”  
RW  
RW  
TOPL  
Outputs “H” w hen the timer is stopped  
Timer RB Output Sw itch Bit Set to 0 in programmable one-shot generation  
TOCNT  
INOSTG  
INOSEG  
RW  
RW  
RW  
mode.  
____  
One-Shot Trigger Control  
Bit(1)  
0 : INT0 pin one-shot trigger disabled  
____  
1 : INT0 pin one-shot trigger enabled  
One-Shot Trigger Polarity  
Select Bit(1)  
0 : Falling edge trigger  
1 : Rising edge trigger  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, its content is 0.  
NOTE:  
1. Refer to  
.
14.2.3.1 One-Shot Trigger Selection  
Figure 14.20 TRBIOC Register in Programmable One-Shot Generation Mode  
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14.Timers  
Set to 1 by a program  
1
0
TSTART bit in TRBCR  
register  
Set to 0 when  
counting ends  
Set to 1 by INT0 pin  
input trigger  
Set to 1 by a program  
1
0
TOSSTF bit in TRBOCR  
register  
INT0 pin input  
Count source  
Timer RB prescaler  
underflow signal  
Timer RB primary reloads  
Timer RB primary reloads  
Count starts  
Count starts  
Counter of timer RB  
01h  
00h  
01h  
00h  
01h  
Set to 0 when interrupt request is  
acknowledged, or set by a program  
1
0
IR bit in TRBIC  
register  
Set to 0 by a program  
1
0
TOPL bit in  
TRBIOC register  
Waveform output starts Waveform output ends  
Waveform output starts Waveform output ends  
1
0
TRBIO pin output  
The above applies under the following conditions.  
TRBPRE = 01h, TRBPR = 01h  
TRBIOC register TOPL = 0, TOCNT = 0  
INOSTG = 1 (INT0 one-shot trigger enabled)  
INOSEG = 1 (edge trigger at rising edge)  
Figure 14.21 Operating Example of Programmable One-Shot Generation Mode  
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14.Timers  
14.2.3.1 One-Shot Trigger Selection  
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts  
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).  
A one-shot trigger can be generated by either of the following causes:  
1 is written to the TOSST bit in the TRBOCR register by a program.  
Trigger input from the INT0 pin.  
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in  
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation  
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation  
mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1,  
no retriggering occurs.  
To use trigger input from the INT0 pin, input the trigger after making the following settings:  
Set the PD4_5 bit in the PD4 register to 0 (input port).  
Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.  
Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select  
falling or rising edge with the INOSEG bit in TRBIOC register.  
Set the INT0EN bit in the INTEN register to 0 (enabled).  
After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger  
enabled).  
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.  
Processing to handle the interrupts is required. Refer to 12. Interrupts, for details.  
If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The  
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).  
If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the  
value of the IR bit in the INT0IC register changes.  
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14.Timers  
14.2.4 Programmable Wait One-Shot Generation Mode  
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program  
or an external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable Wait One-Shot  
Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only  
once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length  
of time equal to the setting value in the TRBPR register.  
Figure 14.22 shows TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 14.23 shows  
an Operating Example of Programmable Wait One-Shot Generation Mode.  
Table 14.10 Programmable Wait One-Shot Generation Mode Specifications  
Item  
Count sources  
Specification  
f1, f2, f8, timer RA underflow  
Count operations  
• Decrement the timer RB primary setting value.  
• When a count of the timer RB primary underflows, the timer reloads the contents of  
timer RB secondary before the count continues.  
• When a count of the timer RB secondary underflows, the timer reloads the contents  
of timer RB primary before the count completes and the TOSSTF bit is set to 0  
(one-shot stops).  
• When the count stops, the timer reloads the contents of the reload register before it  
stops.  
Wait time  
(n+1)(m+1)/fi  
fi: Count source frequency  
n: Value set in the TRBPRE register, m Value set in the TRBPR register  
(2)  
One-shot pulse output time  
Count start conditions  
(n+1)(p+1)/fi  
fi: Count source frequency  
n: Value set in the TRBPRE register, p: Value set in the TRBSC register  
• The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger  
is generated.  
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).  
• Input trigger to the INT0 pin  
Count stop conditions  
• When reloading completes after timer RB underflows during secondary period.  
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).  
• When the TSTART bit in the TRBCR register is set to 0 (starts counting).  
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting).  
Interrupt request generation  
timing  
In half a cycle of the count source after timer RB underflows during secondary period  
(complete at the same time as waveform output from the TRBO pin) [timer RB  
interrupt].  
TRBO pin function  
INT0 pin functions  
Pulse output  
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger  
disabled): programmable I/O port or INT0 interrupt input  
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger  
enabled): external trigger (INT0 interrupt input)  
Read from timer  
Write to timer  
The count value can be read out by reading registers TRBPR and TRBPRE.  
• When registers TRBPRE, TRBSC, and TRBPR are written while the count stops,  
values are written to both the reload register and counter.  
• When registers TRBPRE, TRBSC, and TRBPR are written to during count  
operation, values are written to the reload registers only.(1)  
Select functions  
• Output level select function  
The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse  
waveform.  
• One-shot trigger select function  
Refer to 14.2.3.1 One-Shot Trigger Selection.  
NOTES:  
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR.  
2. Do not set both the TRBPRE and TRBPR registers to 00h.  
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14.Timers  
Timer RB I/O Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
Address  
010Ah  
After Reset  
00h  
TRBIOC  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Timer RB output level select 0 : Outputs one-shot pulse “H”.  
bit  
Outputs “L” w hen the timer stops or during  
w ait.  
TOPL  
1 : Outputs one-shot pulse “L”.  
Outputs “H” w hen the timer stops or during  
w ait.  
Timer RB output sw itch bit  
One-shot trigger control bit(1)  
Set to 0 in programmable w ait one-shot generation  
TOCNT  
INOSTG  
INOSEG  
RW  
RW  
RW  
mode.  
____  
0 : INT0 pin one-shot trigger disabled  
____  
1 : INT0 pin one-shot trigger enabled  
0 : Falling edge trigger  
1 : Rising edge trigger  
One-shot trigger polarity  
select bit(1)  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. Ref er to  
.
14.2.3.1 One-Shot Trigger Selection  
Figure 14.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode  
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14.Timers  
Set to 1 by a program  
1
0
TSTART bit in TRBCR  
register  
Set to 1 by setting 1 to TOSST bit in TRBOCR  
register, or INT0 pin input trigger.  
Set to 0 when  
counting ends  
1
0
TOSSTF bit in TRBOCR  
register  
INT0 pin input  
Count source  
Timer RB prescaler  
underflow signal  
Timer RB secondary reloads  
Timer RB primary reloads  
Count starts  
Counter of timer RB  
01h  
00h  
04h  
03h  
02h  
01h  
00h  
01h  
Set to 0 when interrupt request is  
acknowledged, or set by a program.  
1
0
IR bit in TRBIC  
register  
Set to 0 by a program  
1
0
TOPL bit in  
TRBIOC register  
Wait starts  
Waveform output starts  
Waveform output ends  
1
0
TRBIO pin output  
Wait  
(primary period)  
One-shot pulse  
(secondary period)  
The above applies under the following conditions.  
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h  
INOSTG = 1 (INT0 one-shot trigger enabled)  
INOSEG = 1 (edge trigger at rising edge)  
Figure 14.23 Operating Example of Programmable Wait One-Shot Generation Mode  
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14.Timers  
14.2.5 Notes on Timer RB  
Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the  
count starts.  
Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the  
MCU. Consequently, the timer value may be updated during the period when these two registers are being  
read.  
In programmable one-shot generation mode and programmable wait one-shot generation mode, when  
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the  
TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore,  
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the  
timer count value before the timer stops.  
The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to  
1 (count starts) while the count is stopped.  
(1)  
During this time, do not access registers associated with timer RB other than the TCSTF bit. Timer RB  
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).  
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count  
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.  
(1)  
During this time, do not access registers associated with timer RB other than the TCSTF bit.  
NOTE:  
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and  
TRBPR.  
If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.  
If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes  
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period  
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be  
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the  
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit  
may be set to either 0 or 1.  
14.2.5.1 Timer mode  
The following workaround should be performed in timer mode.  
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following  
points:  
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each  
write interval.  
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow  
for each write interval.  
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14.Timers  
14.2.5.2 Programmable waveform generation mode  
The following three workarounds should be performed in programmable waveform generation mode.  
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the  
following points:  
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each  
write interval.  
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow  
for each write interval.  
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize  
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in  
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period  
A shown in Figures 14.24 and 14.25.  
The following shows the detailed workaround examples.  
Workaround example (a):  
As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These  
write operations must be completed by the beginning of period A.  
Period A  
Count source/  
prescaler  
underflow signal  
Primary period  
Secondary period  
TRBO pin output  
IR bit in  
TRBIC register  
Interrupt request is  
acknowledged  
(a)  
Ensure sufficient time  
(b)  
Interrupt  
Instruction in  
Set the secondary and then  
the primary register immediately  
Interrupt request  
is generated  
sequence interrupt routine  
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time  
varies depending on the instruction being executed.  
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as  
the divisor).  
(b) 20 cycles. 21 cycles for address match and single-step interrupts.  
Figure 14.24 Workaround Example (a) When Timer RB interrupt is Used  
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14.Timers  
Workaround example (b):  
As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to  
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.  
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is  
set to 0 (input mode), the read value indicates the TRBO pin output value.  
Period A  
Count source/  
prescaler  
underflow signal  
Primary period  
Secondary period  
TRBO pin output  
Read value of the port register’s  
bit corresponding to the TRBO pin  
(when the bit in the port direction  
register is set to 0)  
(i) (ii) (iii)  
Ensure sufficient time  
The TRBO output inversion  
is detected at the end of the  
secondary period.  
Upon detecting (i), set the secondary and  
then the primary register immediately.  
Figure 14.25 Workaround Example (b) When TRBO Pin Output Value is Read  
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,  
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.  
14.2.5.3 Programmable one-shot generation mode  
The following two workarounds should be performed in programmable one-shot generation mode.  
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the  
following points:  
When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow  
three or more cycles of the count source for each write interval.  
When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow  
three or more cycles of the prescaler underflow for each write interval.  
(2) Do not set both the TRBPRE and TRBPR registers to 00h.  
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14.Timers  
14.2.5.4 Programmable wait one-shot generation mode  
The following three workarounds should be performed in programmable wait one-shot generation mode.  
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the  
following points:  
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each  
write interval.  
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow  
for each write interval.  
(2) Do not set both the TRBPRE and TRBPR registers to 00h.  
(3) Set registers TRBSC and TRBPR using the following procedure.  
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition  
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR  
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the  
INT0 pin.  
(b) To use “writing 1 to TOSST bit” as the start condition  
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the  
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the  
TOSST bit.  
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14.Timers  
14.3 Timer RC  
14.3.1 Overview  
Timer RC is a 16-bit timer with four I/O pins.  
Timer RC uses either f1 or fOCO40M as its operation clock. Table 14.11 lists the Timer RC Operation Clock.  
Table 14.11 Timer RC Operation Clock  
Condition  
Timer RC Operation Clock  
Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in f1  
TRCCR1 register are set to a value from 000b to 101b)  
Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set fOCO40M  
to 110b)  
Table 14.12 lists the Timer RC I/O Pins, and Figure 14.26 shows a Block Diagram of Timer RC.  
Timer RC has three modes.  
Timer mode  
- Input capture function  
The counter value is captured to a register, using an external signal as the trigger.  
- Output compare function Matches between the counter and register values are detected. (Pin output state  
changes when a match is detected.)  
The following two modes use the output compare function.  
PWM mode  
PWM2 mode  
Pulses of a given width are output continuously.  
A one-shot waveform or PWM waveform is output following the trigger after  
the wait time has elapsed.  
Input capture function, output compare function, and PWM mode settings may be specified independently for  
each pin.  
In PWM2 mode waveforms are output based on a combination of the counter or the register.  
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14.Timers  
f1, f2, f4, f8, f32,  
fOCO40M  
TRCMR register  
TRCCR1 register  
TRCIER register  
TRCSR register  
TRCIOR0 register  
TRCIOR1 register  
TRC register  
INT0  
Count source  
select circuit  
TRCCLK  
TRCIOA/TRCTRG  
TRCIOB  
Timer RC control circuit  
TRCIOC  
TRCGRA register  
TRCGRB register  
TRCGRC register  
TRCGRD register  
TRCCR2 register  
TRCIOD  
TRCDF register  
Timer RC interrupt  
request  
TRCOER register  
Figure 14.26 Block Diagram of Timer RC  
Table 14.12 Timer RC I/O Pins  
Pin Name  
TRCIOA(P1_1)  
TRCIOB(P1_2)  
I/O  
Function  
I/O  
Function differs according to the mode. Refer to descriptions  
of individual modes for details  
(1)  
(1)  
TRCIOC(P5_3 or P3_4)  
TRCIOD(P5_4 or P3_5)  
TRCCLK(P3_3)  
Input  
Input  
External clock input  
TRCTRG(P1_1)  
PWM2 mode external trigger input  
NOTE:  
1. The pins used for TRCIOC and TRCIOD are selectable. Refer to the description of the bits  
TRCIOCSEL and TRCIODSEL in the PINSR3 register in Figure 7.9 Registers PINSR2 and  
PINSR3 for details.  
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14.Timers  
14.3.2 Registers Associated with Timer RC  
Table 14.13 lists the Registers Associated with Timer RC. Figures 14.27 to 14.36 show details of the registers  
associated with timer RC.  
Table 14.13 Registers Associated with Timer RC  
Mode  
Timer  
Address Symbol  
Related Information  
Input  
Capture Compare  
Function Function  
Output  
PWM  
PWM2  
0120h  
0121h  
TRCMR  
Valid  
Valid  
Valid  
Valid  
Valid  
Timer RC mode register  
Figure 14.27 TRCMR Register  
TRCCR1 Valid  
Valid  
Valid  
Timer RC control register 1  
Figure 14.28 TRCCR1 Register  
Figure 14.49 TRCCR1 Register in Output  
Compare Function  
Figure 14.52 TRCCR1 Register in PWM Mode  
Figure 14.56 TRCCR1 Register in PWM2 Mode  
0122h  
0123h  
0124h  
TRCIER  
TRCSR  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Timer RC interrupt enable register  
Figure 14.29 TRCIER Register  
Timer RC status register  
Figure 14.30 TRCSR Register  
TRCIOR0 Valid  
Timer RC I/O control register 0, timer RC I/O  
control register 1  
Figure 14.36 Registers TRCIOR0 and TRCIOR1  
Figure 14.43 TRCIOR0 Register in Input Capture  
Function  
Figure 14.44 TRCIOR1 Register in Input Capture  
Function  
0125h  
TRCIOR1  
Figure 14.47 TRCIOR0 Register in Output  
Compare Function  
Figure 14.48 TRCIOR1 Register in Output  
Compare Function  
0126h  
0127h  
TRC  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Timer RC counter  
Figure 14.31 TRC Register  
0128h  
0129h  
TRCGRA Valid  
TRCGRB  
Timer RC general registers A, B, C, and D  
Figure 14.32 Registers TRCGRA, TRCGRB,  
TRCGRC, and TRCGRD  
012Ah  
012Bh  
012Ch TRCGRC  
012Dh  
012Eh  
012Fh  
TRCGRD  
TRCCR2  
TRCDF  
0130h  
0131h  
0132h  
Valid  
Valid  
Valid  
Timer RC control register 2  
Figure 14.33 TRCCR2 Register  
Valid  
Timer RC digital filter function select register  
Figure 14.34 TRCDF Register  
TRCOER  
Valid  
Valid  
Timer RC output mask enable register  
Figure 14.35 TRCOER Register  
: Invalid  
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14.Timers  
Timer RC Mode Register(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
Address  
0120h  
After Reset  
01001000b  
Function  
TRCMR  
Bit Symbol  
Bit Name  
RW  
RW  
PWM mode of TRCIOB select bit(2) 0 : Timer mode  
PWMB  
PWMC  
PWMD  
PWM2  
BFC  
1 : PWM mode  
PWM mode of TRCIOC select bit(2) 0 : Timer mode  
1 : PWM mode  
PWM mode of TRCIOD select bit(2) 0 : Timer mode  
1 : PWM mode  
RW  
RW  
RW  
RW  
RW  
PWM2 mode select bit  
0 : PWM 2 mode  
1 : Timer mode or PWM mode  
TRCGRC register function select  
bit(3)  
0 : General register  
1 : Buffer register of TRCGRA register  
TRCGRD register function select  
bit  
0 : General register  
1 : Buffer register of TRCGRB register  
BFD  
(b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
TRC count start bit  
0 : Count stops  
1 : Count starts  
TSTART  
RW  
NOTES:  
1. For notes on PWM2 mode, refer to  
.
14.3.9.5 TRCMR Register in PWM2 Mode  
2. These bits are enabled w hen the PWM2 bit is set to 1 (timer mode or PWM mode).  
3. Set the BFC bit to 0 (general register) in PWM2 mode.  
Figure 14.27 TRCMR Register  
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14.Timers  
Timer RC Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCCR1  
Address  
0121h  
After Reset  
00h  
Bit Symbol  
Bit Name  
TRCIOA output level select bit(1)  
Function  
RW  
RW  
Function varies according to the  
operating mode (function).(2)  
TOA  
TOB  
TOC  
TOD  
TRCIOB output level select bit(1)  
TRCIOC output level select bit(1)  
TRCIOD output level select bit(1)  
Count source select bits(1)  
RW  
RW  
RW  
b6 b5 b4  
0 0 0 : f1  
0 0 1 : f2  
0 1 0 : f4  
0 1 1 : f8  
TCK0  
TCK1  
TCK2  
RW  
RW  
RW  
1 0 0 : f32  
1 0 1 : TRCCLK input rising edge  
1 1 0 : fOCO40M  
1 1 1 : Do not set.  
TRC counter clear select bit(2, 3)  
0 : Disable clear (free-running  
operation)  
CCLR  
RW  
1 : Clear by compare match in the  
TRCGRA register  
NOTES:  
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).  
2. Bits CCLR, TOA, TOB, TOC and TOD are disabled for the input capture function of the timer mode.  
3. The TRC counter performs free-running operation for the input capture function of the timer mode independent of the  
CCLR bit setting.  
Figure 14.28 TRCCR1 Register  
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14.Timers  
Timer RC Interrupt Enable Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCIER  
Address  
0122h  
After Reset  
01110000b  
Bit Symbol  
Bit Name  
Input capture / compare match  
interrupt enable bit A  
Function  
0 : Disable interrupt (IMIA) by the  
IMFA bit  
1 : Enable interrupt (IMIA) by the  
IMFA bit  
RW  
RW  
IMIEA  
IMIEB  
IMIEC  
IMIED  
Input capture / compare match  
interrupt enable bit B  
0 : Disable interrupt (IMIB) by the  
IMFB bit  
1 : Enable interrupt (IMIB) by the  
IMFB bit  
RW  
RW  
Input capture / compare match  
interrupt enable bit C  
0 : Disable interrupt (IMIC) by the  
IMFC bit  
1 : Enable interrupt (IMIC) by the  
IMFC bit  
Input capture / compare match  
interrupt enable bit D  
0 : Disable interrupt (IMID) by the  
IMFD bit  
1 : Enable interrupt (IMID) by the  
IMFD bit  
RW  
(b6-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
Overflow interrupt enable bit  
0 : Disable interrupt (OVI) by the  
OVF bit  
OVIE  
RW  
1 : Enable interrupt (OVI) by the  
OVF bit  
Figure 14.29 TRCIER Register  
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14.Timers  
Timer RC Status Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCSR  
Bit Symbol  
Address  
0123h  
Bit Name  
After Reset  
01110000b  
Function  
RW  
RW  
Input capture / compare match flag [Source for setting this bit to 0]  
A
IMFA  
IMFB  
IMFC  
IMFD  
Write 0 after read(1).  
[Source for setting this bit to 1]  
Refer to the table below .  
Input capture / compare match flag  
B
RW  
RW  
RW  
Input capture / compare match flag  
C
Input capture / compare match flag  
D
(b6-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
Overflow flag  
[Source for setting this bit to 0]  
Write 0 after read(1).  
OVF  
RW  
[Source for setting this bit to 1]  
Refer to the table below .  
NOTE:  
1. The w riting results are as follow s:  
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.  
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1  
even if it is set to 1 from 0 after reading, and w riting 0.)  
• This bit remains unchanged if 1 is w ritten to it.  
Timer Mode  
Bit Symbol  
PWM Mode  
PWM2 Mode  
Input capture Function  
TRCIOA pin input edge(1)  
TRCIOB pin input edge(1)  
TRCIOC pin input edge(1)  
TRCIOD pin input edge(1)  
Output Compare Function  
IMFA  
IMFB  
IMFC  
IMFD  
OVF  
When the values of the registers TRC and TRCGRA match.  
When the values of the registers TRC and TRCGRB match.  
When the values of the registers TRC and TRCGRC match.(2)  
When the values of the registers TRC and TRCGRD match.(2)  
When the TRC register overflow s.  
NOTES:  
1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).  
2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and  
TRCGRB).  
Figure 14.30 TRCSR Register  
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Timer RC Counter(1)  
14.Timers  
(b15)  
b7  
(b8)  
b0  
b7  
b0  
Symbol  
TRC  
Address  
0127h-0126h  
After Reset  
0000h  
Function  
Setting Range  
0000h to FFFFh  
RW  
RW  
Count a count source. Count operation is incremented.  
When an overflow occurs, the OVF bit in the TRCSR register is set to 1.  
NOTE:  
1. Access the TRC register in 16-bit units. Do not access it in 8-bit units.  
Figure 14.31 TRC Register  
Timer RC General Register A, B, C and D(1)  
(b15)  
b7  
(b8)  
b0  
b7  
b0  
Symbol  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
Address  
After Reset  
FFFFh  
FFFFh  
FFFFh  
FFFFh  
0129h-0128h  
012Bh-012Ah  
012Dh-012Ch  
012Fh-012Eh  
Function  
Function varies according to the operating mode.  
RW  
RW  
NOTE:  
1. Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units.  
Figure 14.32 Registers TRCGRA, TRCGRB, TRCGRC, and TRCGRD  
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14.Timers  
Timer RC Control Register 2  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCCR2  
Address  
0130h  
After Reset  
00011111b  
Function  
Bit Symbol  
(b4-b0)  
Bit Name  
RW  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
TRC count operation select  
bit(1, 2)  
0 : Count continues at compare match w ith  
the TRCGRA register  
1 : Count stops at compare match w ith  
the TRCGRA register  
CSEL  
RW  
TRCTRG input edge select bits(3)  
b7 b6  
0 0 : Disable the trigger input from the  
TRCTRG pin  
0 1 : Rising edge selected  
1 0 : Falling edge selected  
1 1 : Both edges selected  
TCEG0  
RW  
RW  
TCEG1  
NOTES:  
1. For notes on PWM2 mode, refer to  
.
14.3.9.5 TRCMR Register in PWM2 Mode  
2. In timer mode and PWM mode this bit is disabled (the count operation continues independent of the CSEL bit setting).  
3. In timer mode and PWM mode these bits are disabled.  
Figure 14.33 TRCCR2 Register  
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14.Timers  
Timer RC Digital Filter Function Select Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCDF  
Address  
0131h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
TRCIOA pin digital filter function  
select bit(1)  
0 : Function is not used  
1 : Function is used  
DFA  
DFB  
TRCIOB pin digital filter function  
select bit(1)  
RW  
RW  
RW  
RW  
TRCIOC pin digital filter function  
select bit(1)  
DFC  
TRCIOD pin digital filter function  
select bit(1)  
DFD  
TRCTRG pin digital filter function  
select bit(2)  
DFTRG  
(b5)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
b7 b6  
Clock select bits for digital filter  
function(1, 2)  
0 0 : f32  
DFCK0  
DFCK1  
RW  
RW  
0 1 : f8  
1 0 : f1  
1 1 : Count source (clock selected by  
bits TCK2 to TCK0 in the  
TRCCR1 register)  
NOTES:  
1. These bits are enabled for the input capture function.  
2. These bits are enabled w hen in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or  
11b (TRCTRG trigger input enabled).  
Figure 14.34 TRCDF Register  
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14.Timers  
Timer RC Output Master Enable Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCOER  
Bit Symbol  
Address  
0132h  
After Reset  
01111111b  
Function  
Bit Name  
TRCIOA output disable bit(1)  
RW  
RW  
0 : Enable output  
1 : Disable output (The TRCIOA pin is  
used as a programmable I/O port.)  
EA  
EB  
EC  
ED  
TRCIOB output disable bit(1)  
TRCIOC output disable bit(1)  
TRCIOD output disable bit(1)  
0 : Enable output  
1 : Disable output (The TRCIOB pin is  
used as a programmable I/O port.)  
RW  
RW  
0 : Enable output  
1 : Disable output (The TRCIOC pin is  
used as a programmable I/O port.)  
0 : Enable output  
1 : Disable output (The TRCIOD pin is  
used as a programmable I/O port.)  
RW  
(b6-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
____  
INT0 of pulse output forced  
cutoff signal input enabled  
bit  
0 : Pulse output forced cutoff input disabled  
1 : Pulse output forced cutoff input enabled  
(Bits EA, EB, EC, and ED are set to 1  
PTO  
RW  
(_d_i_s_able output) w hen “L” is applied to the  
INT0 pin)  
NOTE:  
1. These bits are disabled for input pins set to the input capture function.  
Figure 14.35 TRCOER Register  
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14.Timers  
Timer RC I/O Control Register 0(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCIOR0  
Bit Symbol  
Address  
0124h  
After Reset  
10001000b  
Function  
Bit Name  
RW  
IOA0  
IOA1  
TRCGRA control bits  
Function varies according to the operating mode RW  
(function).  
RW  
TRCGRA mode select bit(2)  
0 : Output compare function  
1 : Input capture function  
IOA2  
IOA3  
RW  
TRCGRA input capture input  
sw itch bit(4)  
0 : fOCO128 signal  
1 : TRCIOA pin input  
RW  
IOB0  
IOB1  
TRCGRB control bits  
Function varies according to the operating mode RW  
(function).  
RW  
TRCGRB mode select bit(3)  
0 : Output compare function  
1 : Input capture function  
IOB2  
RW  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
NOTES:  
1. The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2.  
2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the  
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.  
3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the  
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.  
4. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).  
Timer RC I/O Control Register 1(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCIOR1  
Bit Symbol  
IOC0  
Address  
0125h  
After Reset  
10001000b  
Function  
Bit Name  
RW  
TRCGRC control bits  
Function varies according to the operating mode RW  
(function).  
IOC1  
RW  
TRCGRC mode select bit(2)  
0 : Output compare function  
1 : Input capture function  
IOC2  
RW  
(b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
IOD0  
IOD1  
TRCGRD control bits  
Function varies according to the operating mode RW  
(function).  
RW  
TRCGRD mode select bit(3)  
0 : Output compare function  
1 : Input capture function  
IOD2  
RW  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
NOTES:  
1. The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2.  
2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the  
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.  
3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the  
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.  
Figure 14.36 Registers TRCIOR0 and TRCIOR1  
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14.Timers  
14.3.3 Common Items for Multiple Modes  
14.3.3.1 Count Source  
The method of selecting the count source is common to all modes.  
Table 14.14 lists the Count Source Selection, and Figure 14.37 shows a Count Source Block Diagram.  
Table 14.14 Count Source Selection  
Count Source  
f1, f2, f4, f8, f32  
fOCO40M  
Selection Method  
Count source selected using bits TCK2 to TCK0 in TRCCR1 register  
FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on) and bits  
TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M)  
External signal input Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge  
to TRCCLK pin  
of external clock) and PD3_3 bit in PD3 register is set to 0 (input mode)  
TCK2 to TCK0  
= 000b  
f1  
= 001b  
f2  
= 010b  
f4  
f8  
Count source  
= 011b  
= 100b  
TRC register  
f32  
= 101b  
TRCCLK  
= 110b  
fOCO40M  
TCK2 to TCK0: Bits in TRCCR1 register  
Figure 14.37 Count Source Block Diagram  
The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC  
operation clock (see Table 14.11 Timer RC Operation Clock).  
To select fOCO40M as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip  
oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M).  
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14.Timers  
14.3.3.2 Buffer Operation  
Bits BFC and BFD in the TRCMR register are used to select the TRCGRC or TRCGRD register as the buffer  
register for the TRCGRA or TRCGRB register.  
Buffer register for TRCGRA register: TRCGRC register  
Buffer register for TRCGRB register: TRCGRD register  
Buffer operation differs depending on the mode.  
Table 14.15 lists the Buffer Operation in Each Mode, Figure 14.38 shows the Buffer Operation for Input  
Capture Function, and Figure 14.39 shows the Buffer Operation for Output Compare Function.  
Table 14.15 Buffer Operation in Each Mode  
Function, Mode  
Transfer Timing  
Transfer Destination Register  
Contents of TRCGRA (TRCGRB)  
register are transferred to buffer register  
Contents of buffer register are  
transferred to TRCGRA (TRCGRB)  
register  
Input capture function  
Input capture signal input  
Output compare function Compare match between TRC  
register and TRCGRA (TRCGRB)  
PWM mode  
register  
PWM2 mode  
• Compare match between TRC  
register and TRCGRA register  
• TRCTRG pin trigger input  
Contents of buffer register (TRCGRD)  
are transferred to TRCGRB register  
TRCIOA input  
(input capture signal)  
TRCGRC  
register  
TRCGRA  
register  
TRC  
TRCIOA input  
TRC register  
n
n-1  
n+1  
Transfer  
Transfer  
TRCGRA register  
m
n
TRCGRC register  
(buffer)  
m
The above applies under the following conditions:  
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).  
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge).  
Figure 14.38 Buffer Operation for Input Capture Function  
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14.Timers  
Compare match signal  
TRCGRA  
TRCGRC  
register  
Comparator  
TRC  
register  
m
TRC register  
m-1  
m+1  
n
TRCGRA register  
m
Transfer  
TRCGRC register  
(buffer)  
n
TRCIOA output  
The above applies under the following conditions:  
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).  
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).  
Figure 14.39 Buffer Operation for Output Compare Function  
Make the following settings in timer mode.  
To use the TRCGRC register as the buffer register for the TRCGRA register:  
Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.  
To use the TRCGRD register as the buffer register for the TRCGRB register:  
Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.  
The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is  
functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare  
match with the TRC register occurs.  
The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,  
the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin  
or TRCIOD pin.  
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14.Timers  
14.3.3.3 Digital Filter  
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined  
when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.  
Figure 14.40 shows a Block Diagram of Digital Filter.  
TCK2 to TCK0  
DFCK1 to DFCK0  
f1  
= 000b  
= 00b  
f32  
= 001b  
f2  
= 01b  
f8  
= 010b  
= 10b  
= 11b  
f4  
f8  
f1  
= 011b  
= 100b  
Count source  
f32  
IOA2 to IOA0  
IOB2 to IOB0  
IOC2 to IOC0  
IOD2 to IOD0  
(or TCEG1 to TCEG0)  
= 101b  
= 110b  
TRCCLK  
fOCO40M  
Sampling clock  
DFj (or DFTRG)  
1
C
C
C
C
Match detect  
circuit  
Edge detect  
circuit  
TRCIOj input signal  
(or TRCTRG input  
signal)  
D
Q
D
Q
D
Q
D
Q
Latch  
Latch  
Latch  
Latch  
0
Timer RC operation clock  
f1 or fOCO40M  
C
D
Q
Latch  
Clock cycle selected by  
TCK2 to TCK0  
(or DFCK1 to DFCK0)  
Sampling clock  
TRCIOj input signal  
(or TRCTRG input signal)  
Three matches occur and a  
signal change is confirmed.  
Input signal after passing  
through digital filter  
Maximum signal transmission  
delay is five sampling clock  
pulses.  
If fewer than three matches occur,  
the matches are treated as noise  
and no transmission is performed.  
j = A, B, C, or D  
TCK0 to TCK2: Bits in TRCCR1 register  
DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register  
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register  
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register  
TCEG1 to TCEG0: Bits in TRCCR2 register  
Figure 14.40 Block Diagram of Digital Filter  
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14.Timers  
14.3.3.4 Forced Cutoff of Pulse Output  
When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from  
the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a  
programmable I/O port by means of input to the INT0 pin.  
A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be  
set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output  
enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output  
forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1  
(timer RC output disabled, TRCIOj output pin functions as the programmable I/O port). When one or two  
cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 14.11 Timer RC  
Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port.  
Make the following settings to use this function.  
Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H”  
output). (Refer to 7. Programmable I/O Ports.)  
Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.  
Set the PD4_5 bit in the PD4 register to 0 (input mode).  
Select the INT0 digital filter by means of bits INT0F1 to INT0F0 in the INTF register.  
Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled).  
The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and  
a change in the INT0 pin input (refer to 12.6 Notes on Interrupts).  
For details on interrupts, refer to 12. Interrupts.  
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14.Timers  
EA bit  
Q
EA bit  
write value  
D
S
Timer RC  
output data  
INT0 input  
TRCIOA  
Port P1_1  
output data  
PTO bit  
Port P1_1  
input data  
EB bit  
EB bit  
write value  
Q
D
S
Timer RC  
output data  
TRCIOB  
Port P1_2  
output data  
Port P1_2  
input data  
EC bit  
Q
EC bit  
write value  
D
S
Timer RC  
output data  
TRCIOC  
Port P5_3 (P3_4)(1)  
output data  
Port P5_3 (P3_4)(1)  
input data  
ED bit  
ED bit  
write value  
Q
D
S
Timer RC  
output data  
TRCIOD  
Port P5_4 (P3_5)(1)  
output data  
Port P5_4 (P3_5)(1)  
input data  
EA, EB, EC, ED, PTO: Bits in TRCOER register  
NOTE:  
1. The pin in parentheses ( ) can be assigned by a program.  
Figure 14.41 Forced Cutoff of Pulse Output  
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14.Timers  
14.3.4 Timer Mode (Input Capture Function)  
This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A,  
B, C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj  
register (input capture). The input capture function, or any other mode or function, can be selected for each  
individual pin.  
The TRCGRA register can also select fOCO128 signal as input-capture trigger input.  
Table 14.16 lists the Specifications of Input Capture Function, Figure 14.42 shows a Block Diagram of Input  
Capture Function, Figures 14.43 and 14.44 show registers associated with the input capture function, Table  
14.17 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 14.45 shows an  
Operating Example of Input Capture Function.  
Table 14.16 Specifications of Input Capture Function  
Item  
Count source  
Specification  
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to  
TRCCLK pin  
Count operation  
Count period  
Increment  
1/fk × 65,536 fk: Count source frequency  
1 (count starts) is written to the TSTART bit in the TRCMR register.  
0 (count stops) is written to the TSTART bit in the TRCMR register.  
The TRC register retains a value before count stops.  
Count start condition  
Count stop condition  
Interrupt request generation  
timing  
• Input capture (valid edge of TRCIOj input or fOCO128 signal edge)  
• The TRC register overflows.  
TRCIOA, TRCIOB, TRCIOC, Programmable I/O port or input capture input (selectable individually by  
and TRCIOD pin functions  
pin)  
INT0 pin function  
Read from timer  
Write to timer  
Programmable I/O port or INT0 interrupt input  
The count value can be read by reading TRC register.  
The TRC register can be written to.  
Select functions  
• Input capture input pin select  
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD  
• Input capture input valid edge selected  
Rising edge, falling edge, or both rising and falling edges  
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)  
• Digital filter (Refer to 14.3.3.3 Digital Filter.)  
• Input-capture trigger selected  
fOCO128 can be selected for input-capture trigger input of the  
TRCGRA register.  
j = A, B, C, or D  
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14.Timers  
fOCO128  
IOA3 = 0  
Divided  
fOCO  
by 128  
Input capture signal(3)  
TRCIOA  
IOA3 = 1  
TRCGRA  
register  
TRC register  
(Note 1)  
TRCGRC  
register  
TRCIOC  
TRCIOB  
Input capture signal  
Input capture signal  
TRCGRB  
register  
(Note 2)  
TRCGRD  
register  
TRCIOD  
Input capture signal  
IOA3: Bit in TRCIOR0 register  
NOTES:  
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)  
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)  
3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal.  
Figure 14.42 Block Diagram of Input Capture Function  
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14.Timers  
Timer RC I/O Control Register 0  
b7 b6 b5 b4 b3 b2 b1 b0  
1
1
Symbol  
TRCIOR0  
Bit Symbol  
Address  
0124h  
After Reset  
10001000b  
Function  
Bit Name  
RW  
RW  
b1 b0  
TRCGRA control bits  
0 0 : Input capture to the TRCGRA register  
at the rising edge  
0 1 : Input capture to the TRCGRA register  
at the falling edge  
IOA0  
IOA1  
1 0 : Input capture to the TRCGRA register  
at both edges  
RW  
1 1 : Do not set.  
TRCGRA mode select bit(1)  
Set to 1 (input capture) in the input capture  
function.  
IOA2  
IOA3  
RW  
RW  
TRCGRA input capture input  
sw itch bit(3)  
0 : fOCO128 signal  
1 : TRCIOA pin input  
b5 b4  
TRCGRB control bits  
0 0 : Input capture to the TRCGRB register  
at the rising edge  
0 1 : Input capture to the TRCGRB register  
at the falling edge  
IOB0  
RW  
RW  
1 0 : Input capture to the TRCGRB register  
at both edges  
1 1 : Do not set.  
IOB1  
IOB2  
TRCGRB mode select bit(2)  
Set to 1 (input capture) in the input capture  
function.  
RW  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
NOTES:  
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the  
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.  
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the  
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.  
3. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).  
Figure 14.43 TRCIOR0 Register in Input Capture Function  
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14.Timers  
Timer RC I/O Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
1
1
Symbol  
TRCIOR1  
Bit Symbol  
Address  
0125h  
After Reset  
10001000b  
Function  
Bit Name  
RW  
RW  
b1 b0  
TRCGRC control bits  
0 0 : Input capture to the TRCGRC register  
at the rising edge  
IOC0  
0 1 : Input capture to the TRCGRC register  
at the falling edge  
1 0 : Input capture to the TRCGRC register  
at both edges  
1 1 : Do not set.  
IOC1  
IOC2  
RW  
TRCGRC mode select bit(1)  
Set to 1 (input capture) in the input capture  
function.  
RW  
(b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
b5 b4  
TRCGRD control bits  
0 0 : Input capture to the TRCGRD register  
IOD0  
RW  
RW  
at the rising edge  
0 1 : Input capture to the TRCGRD register  
at the falling edge  
1 0 : Input capture to the TRCGRD register  
at both edges  
1 1 : Do not set.  
IOD1  
IOD2  
TRCGRD mode select bit(2)  
Set to 1 (input capture) in the input capture  
function.  
RW  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
NOTES:  
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the  
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.  
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the  
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.  
Figure 14.44 TRCIOR1 Register in Input Capture Function  
Table 14.17 Functions of TRCGRj Register when Using Input Capture Function  
Input Capture  
Input Pin  
General register. Can be used to read the TRC register value TRCIOA  
at input capture.  
General register. Can be used to read the TRC register value TRCIOC  
at input capture.  
Buffer registers. Can be used to hold transferred value from TRCIOA  
the general register. (Refer to 14.3.3.2 Buffer Operation.)  
Register  
Setting  
Register Function  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
TRCGRC  
TRCGRD  
TRCIOB  
TRCIOD  
TRCIOB  
BFC = 0  
BFD = 0  
BFC = 1  
BFD = 1  
j = A, B, C, or D  
BFC, BFD: Bits in TRCMR register  
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14.Timers  
TRCCLK input  
count source  
TRC register  
count value  
FFFFh  
0006h  
0003h  
0000h  
1
0
TSTART bit in  
TRCMR register  
65536  
TRCIOA input  
TRCGRA register  
TRCGRC register  
0006h  
0003h  
Transfer  
0006h  
Transfer  
1
0
IMFA bit in  
TRCSR register  
Set to 0 by a program  
1
0
OVF bit in  
TRCSR register  
The above applies under the following conditions:  
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).  
• Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input).  
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).  
Figure 14.45 Operating Example of Input Capture Function  
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14.Timers  
14.3.5 Timer Mode (Output Compare Function)  
This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or  
D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The  
output compare function, or other mode or function, can be selected for each individual pin.  
Table 14.18 lists the Specifications of Output Compare Function, Figure 14.46 shows a Block Diagram of  
Output Compare Function, Figures 14.47 to 14.49 show registers associated with the output compare function,  
Table 14.19 lists the Functions of TRCGRj Register when Using Output Compare Function, and Figure 14.50  
shows an Operating Example of Output Compare Function.  
Table 14.18 Specifications of Output Compare Function  
Item  
Count source  
Specification  
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to  
TRCCLK pin  
Increment  
Count operation  
Count period  
• The CCLR bit in the TRCCR1 register is set to 0 (free running  
operation): 1/fk × 65,536  
fk: Count source frequency  
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to  
0000h at TRCGRA compare match):  
1/fk × (n + 1)  
n: TRCGRA register setting value  
Waveform output timing  
Count start condition  
Count stop condition  
Compare match  
1 (count starts) is written to the TSTART bit in the TRCMR register.  
0 (count stops) is written to the TSTART bit in the TRCMR register.  
The output compare output pin retains output level before count stops,  
the TRC register retains a value before count stops.  
Interrupt request generation  
timing  
• Compare match (contents of registers TRC and TRCGRj match)  
• The TRC register overflows.  
TRCIOA, TRCIOB, TRCIOC, Programmable I/O port or output compare output (selectable individually  
and TRCIOD pin functions  
by pin)  
INT0 pin function  
Programmable I/O port, pulse output forced cutoff signal input, or INT0  
interrupt input  
Read from timer  
Write to timer  
The count value can be read by reading the TRC register.  
The TRC register can be written to.  
Select functions  
• Output compare output pin selected  
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD  
• Compare match output level select  
“L” output, “H” output, or output level inverted  
• Initial output level select  
Sets output level for period from count start to compare match  
• Timing for clearing the TRC register to 0000h  
Overflow or compare match with the TRCGRA register  
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)  
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff  
of Pulse Output.)  
• Can be used as an internal timer by disabling timer RC output  
j = A, B, C, or D  
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14.Timers  
TRC  
Compare match signal  
Compare match signal  
Compare match signal  
Compare match signal  
Output  
TRCIOA  
control  
Comparator  
Comparator  
Comparator  
Comparator  
TRCGRA  
TRCGRC  
TRCGRB  
TRCGRD  
Output  
TRCIOC  
control  
Output  
TRCIOB  
control  
Output  
TRCIOD  
control  
Figure 14.46 Block Diagram of Output Compare Function  
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14.Timers  
Timer RC I/O Control Register 0  
b7 b6 b5 b4 b3 b2 b1 b0  
0
1 0  
Symbol  
TRCIOR0  
Bit Symbol  
Address  
0124h  
After Reset  
10001000b  
Function  
Bit Name  
RW  
RW  
b1 b0  
TRCGRA control bits  
0 0 : Disable pin output by compare  
match (TRCIOA pin functions as the  
programmable I/O port)  
IOA0  
IOA1  
0 1 : “L” output by compare match in  
the TRCGRA register  
1 0 : “H” output by compare match in  
the TRCGRA register  
1 1 : Toggle output by compare match  
in the TRCGRA register  
RW  
TRCGRA mode select bit(1)  
Set to 0 (output compare) in the output compare  
function.  
IOA2  
IOA3  
RW  
RW  
TRCGRA input capture input  
sw itch bit  
Set to 1.  
b5 b4  
TRCGRB control bits  
0 0 : Disable pin output by compare  
match (TRCIOB pin functions as the  
programmable I/O port)  
0 1 : “L” output by compare match in  
the TRCGRB register  
1 0 : “H” output by compare match in  
the TRCGRB register  
1 1 : Toggle output by compare match  
in the TRCGRB register  
IOB0  
RW  
RW  
IOB1  
IOB2  
TRCGRB mode select bit(2)  
Set to 0 (output compare) in the output compare  
function.  
RW  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
NOTES:  
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the  
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.  
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the  
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.  
Figure 14.47 TRCIOR0 Register in Output Compare Function  
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14.Timers  
Timer RC I/O Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
0
0
Symbol  
TRCIOR1  
Bit Symbol  
Address  
0125h  
After Reset  
10001000b  
Function  
Bit Name  
RW  
RW  
b1 b0  
TRCGRC control bits  
0 0 : Disable pin output by compare  
match  
0 1 : “L” output by compare match in  
the TRCGRC register  
IOC0  
1 0 : “H” output by compare match in  
the TRCGRC register  
1 1 : Toggle output by compare match  
in the TRCGRC register  
IOC1  
IOC2  
RW  
TRCGRC mode select bit(1)  
Set to 0 (output compare) in the output compare  
function.  
RW  
(b3)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
b5 b4  
TRCGRD control bits  
0 0 : Disable pin output by compare  
match  
IOD0  
RW  
RW  
0 1 : “L” output by compare match in  
the TRCGRD register  
1 0 : “H” output by compare match in  
the TRCGRD register  
1 1 : Toggle output by compare match  
in the TRCGRD register  
IOD1  
IOD2  
TRCGRD mode select bit(2)  
Set to 0 (output compare) in the output compare  
function.  
RW  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 1.  
NOTES:  
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the  
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.  
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the  
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.  
Figure 14.48 TRCIOR1 Register in Output Compare Function  
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14.Timers  
Timer RC Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCCR1  
Address  
0121h  
After Reset  
00h  
Bit Symbol  
Bit Name  
TRCIOA output level select bit(1, 2)  
Function  
RW  
RW  
0 : Initial output “L”  
1 : Initial output “H”  
TOA  
TOB  
TOC  
TOD  
TRCIOB output level select bit(1, 2)  
TRCIOC output level select bit(1, 2)  
TRCIOD output level select bit(1, 2)  
Count source select bits(1)  
RW  
RW  
RW  
b6 b5 b4  
0 0 0 : f1  
0 0 1 : f2  
0 1 0 : f4  
0 1 1 : f8  
1 0 0 : f32  
1 0 1 : TRCCLK input rising edge  
TCK0  
TCK1  
TCK2  
RW  
RW  
RW  
1 1 0 : fOCO40M  
1 1 1 : Do not set.  
TRC counter clear select bit  
0 : Disable clear (free-running  
operation)  
CCLR  
RW  
1 : Clear by compare match in the  
TRCGRA register  
NOTES:  
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).  
2. If the pin function is set for w aveform output (refer to Tables 7.13 to 7.16, Tables 7.26 to 7.29, and Tables 7.36 to  
7.39), the initial output level is output w hen the TRCCR1 register is set.  
Figure 14.49 TRCCR1 Register in Output Compare Function  
Table 14.19 Functions of TRCGRj Register when Using Output Compare Function  
Output Compare  
Register  
Setting  
Register Function  
Output Pin  
General register. Write a compare value to one of these TRCIOA  
registers.  
General register. Write a compare value to one of these TRCIOC  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
TRCGRC  
TRCGRD  
TRCIOB  
BFC = 0  
BFD = 0  
BFC = 1  
BFD = 1  
registers.  
TRCIOD  
TRCIOA  
TRCIOB  
Buffer register. Write the next compare value to one of  
these registers. (Refer to 14.3.3.2 Buffer Operation.)  
j = A, B, C, or D  
BFC, BFD: Bits in TRCMR register  
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14.Timers  
Count source  
TRC register value  
m
n
p
Count  
restarts  
Count  
stops  
1
0
TSTART bit in  
TRCMR register  
m+1  
m+1  
Output level held  
TRCIOA output  
Output inverted at  
compare match  
Initial output “L”  
1
0
IMFA bit in  
TRCSR register  
Output level held  
Set to 0 by a program  
n+1  
TRCIOB output  
“H” output at  
compare match  
Initial output “L”  
1
0
IMFB bit in  
TRCSR register  
Set to 0 by a program  
P+1  
Output level held  
“L” output at compare match  
TRCIOC output  
Initial output “H”  
1
0
IMFC bit in  
TRCSR register  
Set to 0 by a program  
m: TRCGRA register setting value  
n: TRCGRB register setting value  
p: TRCGRC register setting value  
The above applies under the following conditions:  
• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).  
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).  
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).  
• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until  
compare match).  
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).  
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).  
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).  
Figure 14.50 Operating Example of Output Compare Function  
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14.Timers  
14.3.6 PWM Mode  
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.  
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA  
register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer  
mode.)  
Table 14.20 lists the Specifications of PWM Mode, Figure 14.51 shows a Block Diagram of PWM Mode,  
Figure 14.52 shows the registers associated with the PWM mode, Table 14.21 lists the Functions of TRCGRj  
Register in PWM Mode, and Figures 14.53 and 14.54 show Operating Examples of PWM Mode.  
Table 14.20 Specifications of PWM Mode  
Item  
Specification  
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to  
TRCCLK pin  
Count source  
Count operation  
PWM waveform  
Increment  
PWM period: 1/fk × (m + 1)  
Active level width: 1/fk × (m - n)  
Inactive width: 1/fk × (n + 1)  
fk: Count source frequency  
m: TRCGRA register setting value  
n: TRCGRj register setting value  
m+1  
(“L” is active level)  
n+1  
m-n  
Count start condition  
Count stop condition  
1 (count starts) is written to the TSTART bit in the TRCMR register.  
0 (count stops) is written to the TSTART bit in the TRCMR register.  
PWM output pin retains output level before count stops, TRC register  
retains value before count stops.  
Interrupt request generation  
timing  
• Compare match (contents of registers TRC and TRCGRj match)  
• The TRC register overflows.  
TRCIOA pin function  
TRCIOB, TRCIOC, and  
TRCIOD pin functions  
Programmable I/O port  
Programmable I/O port or PWM output (selectable individually by pin)  
INT0 pin function  
Programmable I/O port, pulse output forced cutoff signal input, or INT0  
interrupt input  
Read from timer  
Write to timer  
The count value can be read by reading the TRC register.  
The TRC register can be written to.  
Select functions  
• One to three pins selectable as PWM output pins per channel  
One or more of pins TRCIOB, TRCIOC, and TRCIOD  
• Active level selectable by individual pin  
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)  
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced  
Cutoff of Pulse Output.)  
j = B, C, or D  
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14.Timers  
TRC  
Compare match signal  
Compare match signal  
Compare match signal  
Compare match signal  
Comparator  
Comparator  
Comparator  
Comparator  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
TRCIOB  
(Note 1)  
Output  
control  
TRCIOC  
TRCIOD  
(Note 2)  
NOTES:  
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)  
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)  
Figure 14.51 Block Diagram of PWM Mode  
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14.Timers  
Timer RC Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCCR1  
Address  
0121h  
After Reset  
00h  
Bit Symbol  
Bit Name  
TRCIOA output level select bit(1)  
Function  
RW  
RW  
Disabled in PWM mode  
TOA  
TOB  
TRCIOB output level select bit(1, 2)  
TRCIOC output level select bit(1, 2)  
TRCIOD output level select bit(1, 2)  
Count source select bits(1)  
0 : Active level “H”  
(Initial output “L”  
RW  
RW  
RW  
H” output by compare match in  
the TRCGRj register  
“L” output by compare match in  
the TRCGRA register  
1 : Active level “L”  
(Initial output “H”  
“L” output by compare match in  
the TRCGRj register  
TOC  
TOD  
H” output by compare match in  
the TRCGRA register  
b6 b5 b4  
0 0 0 : f1  
0 0 1 : f2  
0 1 0 : f4  
0 1 1 : f8  
TCK0  
TCK1  
TCK2  
CCLR  
RW  
RW  
RW  
RW  
1 0 0 : f32  
1 0 1 : TRCCLK input rising edge  
1 1 0 : fOCO40M  
1 1 1 : Do not set.  
TRC counter clear select bit  
0 : Disable clear (free-running operation)  
1 : Clear by compare match in the  
TRCGRA register  
j = B, C or D  
NOTES:  
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).  
2. If the pin function is set for w aveform output (refer to Table 7.15, Table 7.16, Tables 7.26 to 7.29, and Tables 7.36 to  
7.39), the initial output level is output w hen the TRCCR1 register is set.  
Figure 14.52 TRCCR1 Register in PWM Mode  
Table 14.21 Functions of TRCGRj Register in PWM Mode  
Register  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
TRCGRC  
Setting  
Register Function  
PWM Output Pin  
General register. Set the PWM period.  
General register. Set the PWM output change point.  
General register. Set the PWM output change point.  
TRCIOB  
TRCIOC  
TRCIOD  
BFC = 0  
BFD = 0  
BFC = 1  
Buffer register. Set the next PWM period. (Refer to 14.3.3.2  
Buffer Operation.)  
TRCGRD  
BFD = 1  
Buffer register. Set the next PWM output change point. (Refer to TRCIOB  
14.3.3.2 Buffer Operation.)  
j = A, B, C, or D  
BFC, BFD: Bits in TRCMR register  
NOTE:  
1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM  
period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.  
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14.Timers  
Count source  
TRC register value  
m
n
p
q
m+1  
n+1  
m-n  
Active level is “H”  
Inactive level is “L”  
p+1  
TRCIOB output  
TRCIOC output  
TRCIOD output  
m-p  
“L” initial output until  
compare match  
q+1  
m-q  
Active level is “L”  
“H” initial output until  
compare match  
1
0
IMFA bit in  
TRCSR register  
Set to 0 by a program  
Set to 0 by a program  
1
0
IMFB bit in  
TRCSR register  
1
0
IMFC bit in  
TRCSR register  
Set to 0 by a program  
Set to 0 by a program  
1
0
IMFD bit in  
TRCSR register  
m: TRCGRA register setting value  
n: TRCGRB register setting value  
p: TRCGRC register setting value  
q: TRCGRD register setting value  
The above applies under the following conditions:  
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).  
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).  
• In the TRCCR1 register, bits TOB and TOC are set to 0 (active level is “H”) and the TOD bit is set to 1 (active level is “L”).  
Figure 14.53 Operating Example of PWM Mode  
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14.Timers  
TRC register value  
p
m
q
n
0000h  
1
0
TSTART bit in  
TRCMR register  
TRCIOB output does not switch to “L” because  
no compare match with the TRCGRB register  
has occurred  
Duty 0%  
TRCIOB output  
TRCGRB register  
n
p (p>m)  
Rewritten by a program  
q
1
0
IMFA bit in  
TRCSR register  
Set to 0 by a program  
Set to 0 by a program  
1
0
IMFB bit in  
TRCSR register  
TRC register value  
m
p
n
0000h  
1
0
TSTART bit in  
TRCMR register  
If compare matches occur simultaneously with registers TRCGRA and  
TRCGRB, the compare match with the TRCGRB register has priority.  
TRCIOB output switches to “L”. (In other words, no change).  
Duty 100%  
TRCIOB output  
TRCIOB output switches to “L” at compare match with the  
TRCGRB register. (In other words, no change).  
TRCGRB register  
n
m
p
Rewritten by  
a program  
1
0
IMFA bit in  
TRCSR register  
Set to 0 by a program  
Set to 0 by a program  
1
0
IMFB bit in  
TRCSR register  
m: TRCGRA register setting value  
The above applies under the following conditions:  
• The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled).  
• The TOB bit in the TRCCR1 register is set to 1 (active level is “L”).  
Figure 14.54 Operating Example of PWM Mode (Duty 0% and Duty 100%)  
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14.Timers  
14.3.7 PWM2 Mode  
This mode outputs a single PWM waveform. After a given wait duration has elapsed following the trigger, the  
pin output switches to active level. Then, after a given duration, the output switches back to inactive level.  
Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use  
PWM2 mode to output a programmable wait one-shot waveform.  
Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with  
it.  
Figure 14.55 shows a Block Diagram of PWM2 Mode, Table 14.22 lists the Specifications of PWM2 Mode,  
Figure 14.56 shows the register associated with PWM2 mode, Table 14.23 lists the Functions of TRCGRj  
Register in PWM2 Mode, and Figures 14.57 to 14.59 show Operating Examples of PWM2 Mode.  
Trigger signal  
Compare match signal  
Count clear signal  
(Note 1)  
Input  
control  
TRCTRG  
TRCIOB  
TRC  
Comparator  
Comparator  
Comparator  
TRCGRA  
TRCGRB  
TRCGRC  
TRCGRD  
register  
Output  
control  
NOTE:  
1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB register).  
Figure 14.55 Block Diagram of PWM2 Mode  
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14.Timers  
Table 14.22 Specifications of PWM2 Mode  
Item  
Specification  
Count source  
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin  
Increment TRC register  
Count operation  
PWM waveform  
PWM period: 1/fk × (m + 1) (no TRCTRG input)  
Active level width: 1/fk × (n - p)  
Wait time from count start or trigger: 1/fk × (p + 1)  
fk: Count source frequency  
m: TRCGRA register setting value  
n: TRCGRB register setting value  
p: TRCGRC register setting value  
TRCTRG input  
m+1  
n+1  
p+1  
n+1  
p+1  
TRCIOB output  
n-p  
n-p  
(TRCTRG: Rising edge, active level is “H”)  
Count start conditions  
Count stop conditions  
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger  
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).  
1 (count starts) is written to the TSTART bit in the TRCMR register.  
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG  
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).  
A trigger is input to the TRCTRG pin  
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in  
the TRCCR2 register is set to 0 or 1.  
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in  
the TRCCR1 register. The TRC register retains the value before count stops.  
• The count stops due to a compare match with TRCGRA while the CSEL bit in the  
TRCCR2 register is set to 1  
The TRCIOB pin outputs the initial level. The TRC register retains the value before  
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set  
to 0000h if the CCLR bit in the TRCCR1 register is set to 1.  
Interrupt request  
generation timing  
• Compare match (contents of TRC and TRCGRj registers match)  
• The TRC register overflows  
TRCIOA/TRCTRG pin  
function  
Programmable I/O port or TRCTRG input  
TRCIOB pin function  
PWM output  
TRCIOC and TRCIOD pin Programmable I/O port  
functions  
INT0 pin function  
Read from timer  
Write to timer  
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input  
The count value can be read by reading the TRC register.  
The TRC register can be written to.  
Select functions  
• External trigger and valid edge selected  
The edge or edges of the signal input to the TRCTRG pin can be used as the PWM  
output trigger: rising edge, falling edge, or both rising and falling edges  
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)  
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse  
Output.)  
• Digital filter (Refer to 14.3.3.3 Digital Filter.)  
j = A, B, C, or D  
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14.Timers  
Timer RC Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TRCCR1  
Address  
0121h  
After Reset  
00h  
Bit Symbol  
Bit Name  
TRCIOA output level select bit(1)  
Function  
RW  
RW  
Disabled in the PWM2 mode  
TOA  
TRCIOB output level select bit(1, 2)  
0 : Active level “H”  
(Initial output “L”  
H” output by compare match in the  
TRCGRC register  
“L” output by compare match in the  
TRCGRB register)  
1 : Active level “L”  
TOB  
RW  
(Initial output “H”  
“L” output by compare match in the  
TRCGRC register  
H” output by compare match in the  
TRCGRB register)  
TRCIOC output level select bit(1)  
TRCIOD output level select bit(1)  
Count source select bits(1)  
Disabled in the PWM2 mode  
TOC  
TOD  
RW  
RW  
b6 b5 b4  
0 0 0 : f1  
0 0 1 : f2  
TCK0  
TCK1  
TCK2  
RW  
RW  
RW  
RW  
0 1 0 : f4  
0 1 1 : f8  
1 0 0 : f32  
1 0 1 : TRCCLK input rising edge  
1 1 0 : fOCO40M  
1 1 1 : Do not set.  
TRC counter clear select bit  
0 : Disable clear (free-running operation)  
1 : Clear by compare match in the  
TRCGRA register  
CCLR  
NOTES:  
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).  
2. If the pin function is set for w aveform output (refer to Table 7.15 and Table 7.16), the initial output level is output  
w hen the TRCCR1 register is set.  
Figure 14.56 TRCCR1 Register in PWM2 Mode  
Table 14.23 Functions of TRCGRj Register in PWM2 Mode  
Register  
TRCGRA  
TRCGRB  
TRCGRC  
Setting  
Register Function  
General register. Set the PWM period.  
PWM2 Output Pin  
TRCIOB pin  
General register. Set the PWM output change point.  
BFC = 0  
General register. Set the PWM output change point (wait time  
after trigger).  
TRCGRD  
TRCGRD  
BFD = 0  
BFD = 1  
(Not used in PWM2 mode)  
Buffer register. Set the next PWM output change point. (Refer to TRCIOB pin  
14.3.3.2 Buffer Operation.)  
j = A, B, C, or D  
BFC, BFD: Bits in TRCMR register  
NOTE:  
1. Do not set the TRCGRB and TRCGRC registers to the same value.  
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14.Timers  
Count source  
TRC register value  
FFFFh  
m
TRC register cleared  
at TRCGRA register  
compare match  
n
Previous value held if the  
TSTRAT bit is set to 0  
Set to 0000h  
by a program  
p
0000h  
Count stops  
because the  
CSEL bit is  
set to 1  
1
0
TSTART bit in  
TRCMR register  
Set to 1 by  
a program  
TSTART bit  
is set to 0  
1
0
CSEL bit in  
TRCCR2 register  
m+1  
n+1  
p+1  
p+1  
Return to initial output  
if the TSTART bit is  
set to 0  
“H” output at TRCGRC  
register compare match  
“L” output at TRCGRB  
register compare match  
No change  
“L” initial output  
No change  
TRCIOB output  
“H” output at TRCGRC register  
compare match  
1
0
IMFA bit in  
TRCSR register  
Set to 0 by a program  
1
0
IMFB bit in  
TRCSR register  
Set to 0 by a program  
Set to 0 by a program  
1
0
IMFC bit in  
TRCSR register  
TRCGRB register  
TRCGRD register  
n
Transfer  
Transfer  
n
Next data  
Transfer from buffer register to general register  
m: TRCGRA register setting value  
n: TRCGRB register setting value  
p: TRCGRC register setting value  
The above applies under the following conditions:  
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare  
match with the TRCGRB register).  
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).  
Figure 14.57 Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)  
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14.Timers  
Count source  
TRC register value  
TRC register cleared  
at TRCGRA register  
compare match  
FFFFh  
m
TRC register (counter)  
cleared at TRCTRG pin  
trigger input  
Previous value  
held if the  
TSTART bit is  
set to 0  
n
Set to 0000h  
by a program  
p
0000h  
Count stops  
because the  
CSEL bit is  
set to 1  
Count starts at  
TRCTRG pin  
trigger input  
TRCTRG input  
Count starts  
TSTART bit  
is set to 1  
Changed by a program  
The TSTART  
bit is set to 0  
1
0
TSTART bit in  
TRCMR register  
1
0
CSEL bit in  
TRCCR2 register  
Set to 1 by  
a program  
m+1  
n+1  
p+1  
n+1  
p+1  
p+1  
“L” output at  
TRCGRB register  
compare match  
“H” output at  
TRCGRC register  
compare match  
“L” initial output  
TRCIOB output  
Active level so TRCTRG  
input is disabled  
Inactive level so  
TRCTRG input is  
enabled  
Return to initial value if the  
TSTART bit is set to 0  
1
0
IMFA bit in  
TRCSR register  
Set to 0 by  
a program  
1
0
IMFB bit in  
TRCSR register  
Set to 0 by  
a program  
Set to 0 by  
a program  
Set to 0 by  
a program  
1
0
IMFC bit in  
TRCSR register  
TRCGRB register  
TRCGRD register  
n
n
n
n
Transfer  
Transfer  
Transfer  
Transfer  
n
Next data  
Transfer from buffer register to general register  
Transfer from buffer register to general register  
m: TRCGRA register setting value  
n: TRCGRB register setting value  
p: TRCGRC register setting value  
The above applies under the following conditions:  
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the  
TRCGRB register).  
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).  
Figure 14.58 Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)  
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14.Timers  
• TRCGRB register setting value greater than TRCGRA  
register setting value  
• TRCGRC register setting value greater than TRCGRA  
register setting value  
TRC register value  
TRC register value  
n
p
m
m
n
p
0000h  
0000h  
1
0
1
0
TSTART bit in  
TRCMR register  
TSTART bit in  
TRCMR register  
p+1  
n+1  
m+1  
m+1  
No compare match with  
TRCGRB register, so  
“H” output continues  
“L” output at  
No compare match  
with TRCGRC register,  
so “L” output continues  
TRCGRB register  
compare match  
with no change.  
TRCIOB output  
TRCIOB output  
“H” output at TRCGRC register  
compare match  
“L” initial  
output  
“L” initial  
output  
1
0
1
IMFA bit in  
TRCSR register  
IMFA bit in  
TRCSR register  
0
1
0
1
0
IMFB bit in  
TRCSR register  
IMFB bit in  
TRCSR register  
Set to 0 by a  
program  
1
0
1
0
IMFC bit in  
TRCSR register  
IMFC bit in  
TRCSR register  
m: TRCGRA register setting value  
n: TRCGRB register setting value  
p: TRCGRC register setting value  
The above applies under the following conditions:  
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare  
match with the TRCGRB register).  
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).  
Figure 14.59 Operating Example of PWM2 Mode (Duty 0% and Duty 100%)  
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14.Timers  
14.3.8 Timer RC Interrupt  
Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single  
TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector.  
Table 14.24 lists the Registers Associated with Timer RC Interrupt, and Figure 14.60 is a Timer RC Interrupt  
Block Diagram.  
Table 14.24 Registers Associated with Timer RC Interrupt  
Timer RC Status Register Timer RC Interrupt Enable Register Timer RC Interrupt Control Register  
TRCSR  
TRCIER  
TRCIC  
IMFA bit  
IMIEA bit  
Timer RC interrupt request  
(IR bit in TRCIC register)  
IMFB bit  
IMIEB bit  
IMFC bit  
IMIEC bit  
IMFD bit  
IMIED bit  
OVF bit  
OVIE bit  
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register  
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register  
Figure 14.60 Timer RC Interrupt Block Diagram  
Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits  
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because  
a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.  
The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to  
1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).  
The IR bit is set to 0 (no interrupt request) when the bit in the TRCSR register or the corresponding bit in  
the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained  
if the IR bit is once set to 1 but the interrupt is not acknowledged.  
If after the IR bit is set to 1 another interrupt source is triggered, the IR bit remains set to 1 and does not  
change.  
If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the  
interrupt request.  
The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them  
to 0 within the interrupt routine. Refer to Figure 14.30 TRCSR Register, for the procedure for setting  
these bits to 0.  
Refer to Figure 14.29 TRCIER Register, for details of the TRCIER register.  
Refer to 12.1.6 Interrupt Control, for details of the TRCIC register and 12.1.5.2 Relocatable Vector Tables,  
for information on interrupt vectors.  
Rev.1.00 Dec 14, 2007 Page 199 of 332  
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14.Timers  
14.3.9 Notes on Timer RC  
14.3.9.1 TRC Register  
The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at  
compare match with TRCGRA register).  
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is  
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is  
set to 0000h.  
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the  
write value will not be written to the TRC register and the TRC register will be set to 0000h.  
Reading from the TRC register immediately after writing to it can result in the value previous to the write  
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.  
Program Example  
MOV.W  
JMP.B  
MOV.W  
#XXXXh, TRC  
L1  
TRC,DATA  
;Write  
;JMP.B instruction  
;Read  
L1:  
14.3.9.2 TRCSR Register  
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write  
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.  
Program Example  
MOV.B  
JMP.B  
MOV.B  
#XXh, TRCSR  
L1  
TRCSR,DATA  
;Write  
;JMP.B instruction  
;Read  
L1:  
14.3.9.3 Count Source Switching  
Stop the count before switching the count source.  
Switching procedure  
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).  
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.  
After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to  
elapse after changing the clock setting before stopping fOCO40M.  
Switching procedure  
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).  
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.  
(3) Wait for a minimum of two cycles of f1.  
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).  
14.3.9.4 Input Capture Function  
The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock  
(refer to Table 14.11 Timer RC Operation Clock).  
The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC  
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the  
digital filter function is not used).  
14.3.9.5 TRCMR Register in PWM2 Mode  
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA  
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.  
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14.Timers  
14.4 Timer RE  
Timer RE has the 4-bit counter and 8-bit counter.  
Timer RE has the following modes:  
Output compare mode  
Count a count source and detect compare matches.  
The count source for timer RE is the operating clock that regulates the timing of timer operations.  
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14.Timers  
14.4.1 Output Compare Mode  
In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and  
compare value match is detected with the 8-bit counter. Figure 14.61 shows a Block Diagram of Output  
Compare Mode and Table 14.25 lists the Output Compare Mode Specifications. Figures 14.62 to 14.66 show  
the Registers Associated with Output Compare Mode, and Figure 14.67 shows the Operating Example in  
Output Compare Mode.  
f4  
f8  
RCS6 to RCS5  
= 00b  
TOENA  
f2  
= 01b  
= 10b  
= 11b  
RCS1 to RCS0  
= 00b  
TREO pin  
RCS2 = 1  
RCS2 = 0  
= 01b  
= 10b  
4-bit  
counter  
1/2  
8-bit  
counter  
T Q  
f32  
R
Reset  
TRERST  
Match  
signal  
Comparison  
circuit  
Timer RE interrupt  
COMIE  
TRERST, TOENA: Bits in TRECR1 register  
COMIE: Bit in TRECR2 register  
TRESEC  
TREMIN  
RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register  
Data bus  
Figure 14.61 Block Diagram of Output Compare Mode  
Table 14.25 Output Compare Mode Specifications  
Item  
Specification  
Count sources  
f4, f8, f32  
Count operations  
• Increment  
• When the 8-bit counter content matches with the TREMIN register content, the  
value returns to 00h and count continues.  
The count value is held while count stops.  
Count period  
• When RCS2 = 0 (4-bit counter is not used)  
1/fi x 2 x (n+1)  
• When RCS2 = 1 (4-bit counter is used)  
1/fi x 32 x (n+1)  
fi: Frequency of count source  
n: Setting value of TREMIN register  
Count start condition  
Count stop condition  
1 (count starts) is written to the TSTART bit in the TRECR1 register  
0 (count stops) is written to the TSTART bit in the TRECR1 register  
Interrupt request generation timing When the 8-bit counter content matches with the TREMIN register content  
TREO pin function  
Select any one of the following:  
• Programmable I/O ports  
• Output f2, f4, or f8  
• Compare output  
Read from timer  
Write to timer  
When reading the TRESEC register, the 8-bit counter value can be read.  
When reading the TREMIN register, the compare value can be read.  
Writing to the TRESEC register is disabled.  
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer  
stops), writing to the TREMIN register is enabled.  
Select functions  
• Select use of 4-bit counter  
• Compare output function  
Every time the 8-bit counter value matches the TREMIN register value, TREO  
output polarity is reversed. The TREO pin outputs “L” after reset is deasserted  
and the timer RE is reset by the TRERST bit in the TRECR1 register. Output  
level is held by setting the TSTART bit to 0 (count stops).  
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14.Timers  
Timer RE Counter Data Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
Address  
0118h  
After Reset  
00h  
TRESEC  
Function  
RW  
RO  
8-bit counter data can be read.  
Although Timer RE stops counting, the count value is held.  
The TRESEC register is set to 00h at the compare match.  
Figure 14.62 TRESEC Register in Output Compare Mode  
Timer RE Compare Data Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TREMIN  
Address  
0119h  
After Reset  
00h  
Function  
RW  
RW  
8-bit compare data is stored.  
Figure 14.63 TREMIN Register in Output Compare Mode  
Timer RE Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
0
Symbol  
Address  
011Ch  
After Reset  
00h  
TRECR1  
Bit Symbol  
Bit Name  
Function  
RW  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
(b0)  
Timer REcount status flag  
TREO pin output enable bit  
Interrupt request timing bit  
Timer REreset bit  
0 : Count stopped  
1 : Counting  
TCSTF  
TOENA  
INT  
RO  
RW  
RW  
0 : Disable clock output  
1 : Enable clock output  
Set to 0 in output compare mode.  
When setting this bit to 0, after setting it to 1, the  
follow ing w ill occur.  
• Registers TRESEC, TREMIN, and TRECR2  
are set to 00h.  
• Bits TCSTF, INT, and TSTART in the  
TRECR1 register are set to 0.  
TRERST  
RW  
• The 8-bit counter is set to 00h and the 4-bit  
counter is set to 0h.  
(b6-b5)  
Reserved bits  
Set to 0.  
RW  
RW  
Timer REcount start bit  
0 : Count stops  
1 : Count starts  
TSTART  
Figure 14.64 TRECR1 Register in Output Compare Mode  
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14.Timers  
Timer RE Control Register 2  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0 0 0  
Symbol  
Address  
011Dh  
After Reset  
00h  
TRECR2  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Reserved bits  
Compare match interrupt enable bit  
Set to 0.  
(b4-b0)  
0 : Disable compare match interrupt  
1 : Enable compare match interrupt  
COMIE  
RW  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
(b7-b6)  
Figure 14.65 TRECR2 Register in Output Compare Mode  
Timer RE Count Source Select Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
TRECSR  
Bit Symbol  
Address  
011Eh  
After Reset  
00001000b  
Function  
Bit Name  
RW  
RW  
b1 b0  
Count source select bits  
0 0 : f4  
0 1 : f8  
RCS0  
1 0 : f32  
1 1 : Do not set.  
RCS1  
RCS2  
RW  
4-bit counter select bit  
Reserved bit  
0 : Not used  
1 : Used  
RW  
RW  
(b3)  
Set to 0.  
(b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Clock output select bits(1)  
b6 b5  
0 0 : f2  
RCS5  
RCS6  
RW  
0 1 : f4  
1 0 : f8  
1 1 : Compare output  
RW  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).  
Figure 14.66 TRECSR Register in Output Compare Mode  
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14.Timers  
Count starts  
Matched  
Matched  
Matched  
TREMIN register  
setting value  
00h  
Time  
Set to 1 by a program  
1
0
TSTART bit in  
TRECR1 register  
2 cycles of maximum count source  
1
0
TCSTF bit in  
TRECR1 register  
Set to 0 by acknowledgement of interrupt request  
or a program  
1
0
IR bit in  
TREIC register  
1
0
TREO output  
Output polarity is inverted  
when the compare matches  
The above applies under the following conditions.  
TOENA bit in TRECR1 register = 1 (enable clock output)  
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)  
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)  
Figure 14.67 Operating Example in Output Compare Mode  
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14.Timers  
14.4.2 Notes on Timer RE  
14.4.2.1 Starting and Stopping Count  
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates  
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.  
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count  
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to  
(1)  
1. During this time, do not access registers associated with timer RE other than the TCSTF bit.  
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0  
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting  
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF  
bit.  
NOTE:  
1. Registers associated with timer RE: TRESEC, TREMIN, TRECR1, TRECR2, and TRECSR.  
14.4.2.2 Register Setting  
Write to the following registers or bits when timer RE is stopped.  
Registers TRESEC, TREMIN, and TRECR2  
INT bit in TRECR1 register  
Bits RCS0 to RCS2 and b3 in TRECSR register  
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).  
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the  
TRECR2 register.  
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15. Serial Interface  
15. Serial Interface  
The serial interface consists of one channel (UART0). UART0 has an exclusive timer to generate the transfer clock and  
operates.  
Figure 15.1 shows a UART0 Block Diagram. Figure 15.2 shows a UART0 Transmit/Receive Unit.  
UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).  
Figures 15.3 to 15.7 show the Registers Associated with UART0.  
(UART0)  
RXD0  
TXD0  
UART reception  
Receive  
clock  
1/16  
Reception control  
circuit  
CLK1 to CLK0 = 00b  
CKDIR = 0  
Internal  
Clock  
Transmit/  
receive  
unit  
synchronous type  
f1  
f8  
= 01b  
= 10b  
U0BRG register  
1/(n0+1)  
UART transmission  
Transmit  
clock  
1/16  
1/2  
f32  
Transmission  
control circuit  
Clock  
synchronous type  
External  
CKDIR = 1  
CKDIR = 0  
CKDIR = 1  
Clock synchronous type  
(when internal clock is selected)  
Clock synchronous type  
(when external clock is selected)  
Clock synchronous type  
(when internal clock is selected)  
CLK  
polarity  
switch  
circuit  
CLK0  
CLK1 to CLK0: Bits in U0C0 register  
CKDIR: Bit in U0MR register  
Figure 15.1  
UART0 Block Diagram  
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15. Serial Interface  
Clock  
synchronous  
type  
PRYE = 0  
PAR  
disabled  
Clock  
synchronous  
type  
UART (7 bits)  
UART (8 bits)  
1SP  
UART (7 bits)  
UART0 receive register  
SP  
PAR  
RXD0  
SP  
PAR  
Clock  
synchronous  
type  
UART  
2SP  
UART (9 bits)  
enabled  
PRYE = 1  
UART (8 bits)  
UART (9 bits)  
U0RB register  
D7 D6 D5 D4 D3 D2 D1 D0  
0
0
0
0
0
0
0
D8  
MSB/LSB conversion circuit  
Data bus high-order bits  
Data bus low-order bits  
MSB/LSB conversion circuit  
U0TB register  
D8  
D7 D6 D5 D4 D3 D2 D1 D0  
UART (8 bits)  
UART (9 bits)  
Clock  
synchronous  
type  
PRYE = 1  
PAR  
enabled  
UART (9 bits)  
UART  
2SP  
1SP  
SP  
PAR  
TXD0  
SP  
Clock  
synchronous  
type  
PAR  
UART (7 bits)  
UART (8 bits)  
UART0 transmit register  
SP: Stop bit  
PAR: Parity bit  
PRYE: Bit in U0MR register  
UART (7 bits)  
disabled  
PRYE = 0  
Clock  
synchronous  
type  
0
Figure 15.2  
UART0 Transmit/Receive Unit  
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15. Serial Interface  
UART0 Transmit Buffer Register(1, 2)  
(b15)  
b7  
(b8)  
b0  
b7  
b0  
Symbol  
U0TB  
Address  
00A3h-00A2h  
After Reset  
Undefined  
Function  
RW  
WO  
Transmit data  
(b8-b0)  
(b15-b9)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is undefined.  
NOTES:  
1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte.  
2. Use the MOV instruction to w rite to this register.  
UART0 Receive Buffer Register(1)  
(b15)  
(b8)  
b7  
b0  
b7  
b0  
Symbol  
U0RB  
Address  
00A7h-00A6h  
After Reset  
Undefined  
Function  
Bit Symbol  
(b7-b0)  
Bit Name  
RW  
RO  
Receive data (D7 to D0)  
Receive data (D8)  
(b8)  
RO  
(b11-b9)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is undefined.  
Overrun error flag(2)  
Framing error flag(2)  
Parity error flag(2)  
Error sumflag(2)  
0 : No overrun error  
1 : Overrun error  
OER  
FER  
PER  
SUM  
RO  
RO  
RO  
RO  
0 : No framing error  
1 : Framing error  
0 : No parity error  
1 : Parity error  
0 : No error  
1 : Error  
NOTES:  
1. Read out the U0RB register in 16-bit units.  
2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the U0MR register are set to 000b  
(serial interface disabled) or the REbit in the U0C1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no  
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte  
of the U0RB register is read out.  
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the U0RB register.  
Figure 15.3  
Registers U0TB and U0RB  
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UART0 Bit Rate Register(1, 2, 3)  
15. Serial Interface  
b7  
b0  
Symbol  
U0BRG  
Address  
00A1h  
Function  
After Reset  
Undefined  
Setting Range  
00h to FFh  
RW  
WO  
Assuming the set value is n, U0BRG divides the count source by  
n+1  
NOTES:  
1. Write to this register w hile the serial I/O is neither transmitting nor receiving.  
2. Use the MOV instruction to w rite to this register.  
3. After setting the CLK0 to CLK1 bits of the U0C0 register, w rite to the U0BRG register.  
UART0 Transmit/Receive Mode Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
U0MR  
Address  
00A0h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Serial I/O mode select bits  
b2 b1 b0  
SMD0  
SMD1  
SMD2  
0 0 0 : Serial interface disabled  
0 0 1 : Clock synchronous serial I/O mode  
1 0 0 : UART mode transfer data 7 bits long  
1 0 1 : UART mode transfer data 8 bits long  
1 1 0 : UART mode transfer data 9 bits long  
Other than above : Do not set  
RW  
RW  
Internal/external clock select bit 0 : Internal clock  
1 : External clock(1)  
CKDIR  
STPS  
RW  
RW  
Stop bit length select bit  
0 : 1 stop bit  
1 : 2 stop bits  
Odd/even parity select bit  
Enable w hen PRYE= 1  
0 : Odd parity  
PRY  
RW  
1 : Even parity  
Parity enable bit  
Reserved bit  
0 : Parity disabled  
1 : Parity enabled  
PRY E  
RW  
RW  
(b7)  
Set to 0.  
NOTE:  
1. When the CLK0 pin is used, set the PD1_6 bit in the PD1 register to 0 (input).  
Figure 15.4  
Registers U0BRG and U0MR  
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15. Serial Interface  
UART0 Transmit/Receive Control Register 0  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
U0C0  
Bit Symbol  
Address  
00A4h  
After Reset  
00001000b  
Function  
Bit Name  
RW  
RW  
BRG count source select  
bits(1)  
b1 b0  
0 0 : Selects f1  
CLK0  
CLK1  
0 1 : Selects f8  
1 0 : Selects f32  
1 1 : Do not set.  
RW  
RW  
(b2)  
Reserved bit  
Set to 0.  
Transmit register empty  
flag  
0 : Data in transmit register (during transmit)  
1 : No data in transmit register (transmit completed)  
TXEPT  
RO  
(b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Data output select bit  
0 : TXDi pin is for CMOS output  
1 : TXDi pin is for N-channel open drain output  
NCH  
RW  
CLK polarity select bit  
0 : Transmit data is output at falling edge of transfer  
clock and receive data is input at rising edge  
1 : Transmit data is output at rising edge of transfer  
clock and receive data is input at falling edge  
CKPOL  
RW  
RW  
Transfer format select bit 0 : LSB first  
1 : MSB first  
UFORM  
NOTE:  
1. If the BRG count source is sw itched, set the U0BRG register again.  
Figure 15.5  
U0C0 Register  
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15. Serial Interface  
UART0 Transmit/Receive Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
U0C1  
Address  
00A5h  
After Reset  
00000010b  
Function  
Bit Symbol  
Bit Name  
RW  
RW  
Transmit enable bit(1)  
0 : Disables transmission  
1 : Enables transmission  
TE  
TI  
Transmit buffer empty flag  
Receive enable bit  
0 : Data in U0TB register  
1 : No data in U0TB register  
RO  
RW  
RO  
0 : Disables reception  
1 : Enables reception  
RE  
Receive complete flag(1)  
0 : No data in U0RB register  
1 : Data in U0RB register  
RI  
UART0 transmit interrupt cause  
select bit  
0 : Transmission buffer empty (TI=1)  
1 : Transmission completed (TXEPT=1)  
U0IRS  
U0RRM  
RW  
RW  
UART0 continuous receive mode 0 : Disables continuous receive mode  
enable bit(2)  
1 : Enables continuous receive mode  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTES:  
1. The RI bit is set to 0 w hen the higher byte of the U0RB register is read out.  
2. Set the U0RRM bit to 0 (disables continuous receive mode) in UART mode.  
Figure 15.6  
U0C1 Register  
Port Mode Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0  
Symbol  
PMR  
Address  
00F8h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
___  
0 : P1_5, P1_7  
1 : P3_6  
INT1 pin select bit  
INT1SEL  
(b3-b1)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
RW  
(b6-b4)  
Reserved bits  
Set to 0.  
(b7)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 15.7  
PMR Register  
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15. Serial Interface  
15.1 Clock Synchronous Serial I/O Mode  
In the clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.  
Table 15.1 lists the Specifications of Clock Synchronous Serial I/O Mode. Table 15.2 lists the Registers Used and  
Settings in Clock Synchronous Serial I/O Mode.  
Table 15.1  
Specifications of Clock Synchronous Serial I/O Mode  
Item Specification  
Transfer data format  
Transfer clocks  
• Transfer data length: 8 bits  
• CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n+1))  
fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh  
• The CKDIR bit is set to 1 (external clock): input from CLK0 pin  
(1)  
Transmit start conditions  
Receive start conditions  
• Before transmit starts, the following requirements must be met  
- The TE bit in the U0C1 register is set to 1 (transmission enabled)  
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)  
(1)  
• Before receive starts, the following requirements must be met  
- The RE bit in the U0C1 register is set to 1 (reception enabled)  
- The TE bit in the U0C1 register is set to 1 (transmission enabled)  
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)  
Interrupt request  
generation timing  
• When transmitting, one of the following conditions can be selected  
- The U0IRS bit is set to 0 (transmit buffer empty):  
When transferring data from the U0TB register to UART0 transmit  
register (when transmission starts).  
- The U0IRS bit is set to 1 (transmission completes):  
When completing data transmission from UART0 transmit register.  
• When receiving  
When data transfer from the UART0 receive register to the U0RB register  
(when reception completes).  
(2)  
Error detection  
Select functions  
• Overrun error  
This error occurs if the serial interface starts receiving the next data item  
before reading the U0RB register and receives the 7th bit of the next data.  
• CLK polarity selection  
Transfer data input/output can be selected to occur synchronously with the  
rising or the falling edge of the transfer clock.  
• LSB first, MSB first selection  
Whether transmitting or receiving data begins with bit 0 or begins with bit 7  
can be selected.  
• Continuous receive mode selection  
Receive is enabled immediately by reading the U0RB register.  
NOTES:  
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the  
U0C0 register is set to 0 (transmit data output at falling edge and receive data input at rising edge of  
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output  
at rising edge and receive data input at falling edge of transfer clock).  
2. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR  
bit in the S0RIC register remains unchanged.  
Rev.1.00 Dec 14, 2007 Page 213 of 332  
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15. Serial Interface  
(1)  
Table 15.2  
Registers Used and Settings in Clock Synchronous Serial I/O Mode  
Register  
U0TB  
Bit Function  
0 to 7  
0 to 7  
OER  
Set data transmission  
U0RB  
Data reception can be read  
Overrun error flag  
U0BRG  
U0MR  
0 to 7  
Set bit rate  
Set to 001b  
SMD2 to SMD0  
CKDIR  
CLK1 to CLK0  
TXEPT  
NCH  
Select the internal clock or external clock  
Select the count source in the U0BRG register  
Transmit register empty flag  
U0C0  
Select TXD0 pin output mode  
Select the transfer clock polarity  
Select the LSB first or MSB first  
Set this bit to 1 to enable transmission/reception  
Transmit buffer empty flag  
CKPOL  
UFORM  
TE  
U0C1  
TI  
RE  
Set this bit to 1 to enable reception  
Reception complete flag  
RI  
U0IRS  
U0RRM  
Select the UART0 transmit interrupt source  
Set this bit to 1 to use continuous receive mode  
NOTE:  
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous  
serial I/O mode.  
Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs “H” level  
between the operating mode selection of UART0 and transfer start. (If the NCH bit is set to 1 (N-channel open-  
drain output), this pin is in a high-impedance state.)  
Table 15.3  
I/O Pin Functions in Clock Synchronous Serial I/O Mode  
Pin Name  
Function  
Output serial data  
Input serial data  
Selection Method  
TXD0 (P1_4)  
RXD0 (P1_5)  
(Outputs dummy data when performing reception only)  
PD1_5 bit in PD1 register = 0  
(P1_5 can be used as an input port when performing  
transmission only)  
CLK0 (P1_6)  
Output transfer clock CKDIR bit in U0MR register = 0  
Input transfer clock  
CKDIR bit in U0MR register = 1  
PD1_6 bit in PD1 register = 0  
Rev.1.00 Dec 14, 2007 Page 214 of 332  
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15. Serial Interface  
• Example of transmit timing (when internal clock is selected)  
TC  
Transfer clock  
1
0
TE bit in U0C1  
register  
Set data in U0TB register  
TI bit in U0C1  
register  
1
0
Transfer from U0TB register to UART0 transmit register  
TCLK  
Stop pulsing because the TE bit is set to 0  
CLK0  
TXD0  
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7  
D0 D1 D2 D3 D4 D5 D6 D7  
TXEPT bit in  
U0C0 register  
1
0
IR bit in S0TIC  
register  
1
0
Set to 0 when interrupt request is acknowledged, or set by a program  
TC = TCLK = 2(n+1)/fi  
fi: Frequency of U0BRG count source (f1, f8, f32)  
n: Setting value to U0BRG register  
The above applies under the following settings:  
• CKDIR bit in U0MR register = 0 (internal clock)  
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)  
• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when the transmit buffer is empty)  
• Example of receive timing (when external clock is selected)  
RE bit in U0C1  
register  
1
0
TE bit in U0C1  
register  
1
0
Write dummy data to U0TB register  
TI bit in U0C1  
register  
1
0
Transfer from U0TB register to UART0 transmit register  
1/fEXT  
CLK0  
RXD0  
Receive data is taken in  
D0 D1 D2 D3 D4 D5 D6 D7  
D0 D1 D2 D3 D4 D5  
Read out from U0RB register  
Transfer from UART0 receive register to  
U0RB register  
RI bit in U0C1  
register  
1
0
1
0
IR bit in S0RIC  
register  
Set to 0 when interrupt request is acknowledged, or set by a program  
The above applies under the following settings:  
• CKDIR bit in U0MR register = 1 (external clock)  
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)  
The following conditions are met when “H” is applied to the CLK0 pin before receiving data:  
• TE bit in U0C1 register = 1 (enables transmit)  
• RE bit in U0C1 register = 1 (enables receive)  
• Write dummy data to the U0TB register  
fEXT: Frequency of external clock  
Figure 15.8  
Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode  
Rev.1.00 Dec 14, 2007 Page 215 of 332  
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15. Serial Interface  
15.1.1 Polarity Select Function  
Figure 15.9 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer  
clock polarity.  
• When the CKPOL bit in the U0C0 register = 0 (output transmit data at the falling  
edge and input receive data at the rising edge of the transfer clock)  
CLK0(1)  
TXD0  
RXD0  
D0  
D0  
D1  
D1  
D2  
D2  
D3  
D3  
D4  
D4  
D5  
D5  
D6  
D6  
D7  
D7  
• When the CKPOL bit in the U0C0 register = 1 (output transmit data at the rising  
edge and input receive data at the falling edge of the transfer clock)  
CLK0(2)  
TXD0  
RXD0  
D0  
D0  
D1  
D1  
D2  
D2  
D3  
D3  
D4  
D4  
D5  
D5  
D6  
D6  
D7  
D7  
NOTES:  
1. When not transferring, the CLK0 pin level is “H”.  
2. When not transferring, the CLK0 pin level is “L”.  
Figure 15.9  
Transfer Clock Polarity  
15.1.2 LSB First/MSB First Select Function  
Figure 15.10 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format.  
• When UFORM bit in U0C0 register = 0 (LSB first)(1)  
CLK0  
TXD0  
RXD0  
D0  
D0  
D1  
D1  
D2  
D2  
D3  
D3  
D4  
D4  
D5  
D5  
D6  
D6  
D7  
D7  
• When UFORM bit in U0C0 register = 1 (MSB first)(1)  
CLK0  
TXD0  
RXD0  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
NOTE:  
1. The above applies when the CKPOL bit in the U0C0 register is  
set to 0 (output transmit data at the falling edge and input receive  
data at the rising edge of the transfer clock).  
Figure 15.10 Transfer Format  
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15. Serial Interface  
15.1.3 Continuous Receive Mode  
Continuous receive mode is selected by setting the U0RRM bit in the U0C1 register to 1 (enables continuous  
receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to 0 (data in the  
U0TB register). When the U0RRM bit is set to 1, do not write dummy data to the U0TB register by a program.  
Rev.1.00 Dec 14, 2007 Page 217 of 332  
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15. Serial Interface  
15.2 Clock Asynchronous Serial I/O (UART) Mode  
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.  
Table 15.4 lists the Specifications of UART Mode. Table 15.5 lists the Registers Used and Settings for UART  
Mode.  
Table 15.4  
Specifications of UART Mode  
Item  
Specification  
Transfer data formats  
• Character bit (transfer data): Selectable among 7, 8 or 9 bits  
• Start bit: 1 bit  
• Parity bit: Selectable among odd, even, or none  
• Stop bit: Selectable among 1 or 2 bits  
Transfer clocks  
• CKDIR bit in U0MR register is set to 0 (internal clock): fj/(16(n+1))  
fj = f1, f8, f32 n = value set in U0BRG register: 00h to FFh  
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))  
fEXT: Input from CLK0 pin, n = value set in U0BRG register: 00h to FFh  
Transmit start conditions  
Receive start conditions  
• Before transmission starts, the following are required  
- TE bit in U0C1 register is set to 1 (transmission enabled)  
- TI bit in U0C1 register is set to 0 (data in U0TB register)  
• Before reception starts, the following are required  
- RE bit in U0C1 register is set to 1 (reception enabled)  
- Start bit detected  
Interrupt request  
generation timing  
• When transmitting, one of the following conditions can be selected  
- U0IRS bit is set to 0 (transmit buffer empty):  
When transferring data from the U0TB register to UART0 transmit  
register (when transmit starts).  
- U0IRS bit is set to 1 (transfer ends):  
When serial interfac.e completes transmitting data from the UART0  
transmit register  
• When receiving  
When transferring data from the UART0 receive register to U0RB register  
(when receive ends).  
(1)  
Error detection  
• Overrun error  
This error occurs if the serial interface starts receiving the next data item  
before reading the U0RB register and receive the bit preceding the final  
stop bit of the next data item.  
• Framing error  
This error occurs when the set number of stop bits is not detected.  
• Parity error  
This error occurs when parity is enabled, and the number of 1’s in parity  
and character bits do not match the number of 1’s set.  
• Error sum flag  
This flag is set is set to 1 when an overrun, framing, or parity error is  
generated.  
NOTE:  
1. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR  
bit in the S0RIC register remains unchanged.  
Rev.1.00 Dec 14, 2007 Page 218 of 332  
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15. Serial Interface  
Table 15.5  
Registers Used and Settings for UART Mode  
Bit  
Register  
U0TB  
Function  
(1)  
0 to 8  
0 to 8  
Set transmit data  
Receive data can be read  
(1, 2)  
U0RB  
OER,FER,PER,SUM Error flag  
U0BRG  
U0MR  
0 to 7  
Set a bit rate  
SMD2 to SMD0  
Set to 100b when transfer data is 7 bits long.  
Set to 101b when transfer data is 8 bits long.  
Set to 110b when transfer data is 9 bits long.  
CKDIR  
Select the internal clock or external clock  
Select the stop bit  
STPS  
PRY, PRYE  
CLK0, CLK1  
TXEPT  
Select whether parity is included and whether odd or even  
Select the count source for the U0BRG register  
Transmit register empty flag  
U0C0  
U0C1  
NCH  
Select TXD0 pin output mode  
CKPOL  
UFORM  
Set to 0  
LSB first or MSB first can be selected when transfer data is 8 bits  
long. Set to 0 when transfer data is 7 or 9 bits long.  
TE  
Set to 1 to enable transmit  
Transmit buffer empty flag  
Set to 1 to enable receive  
Receive complete flag  
TI  
RE  
RI  
U0IRS  
U0RRM  
Select the factor of UART0 transmit interrupt  
Set to 0  
NOTES:  
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;  
bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.  
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer  
data is 8 bits long.  
Table 15.6 lists the I/O Pin Functions in UART Mode. After the UART0 operating mode is selected, the TXD0 pin  
outputs “H” level (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-impedance state)  
until transfer starts.  
Table 15.6  
I/O Pin Functions in UART Mode  
Pin name  
Function  
Selection Method  
TXD0 (P1_4) Output serial data  
RXD0 (P1_5) Input serial data  
(Cannot be used as a port when performing reception only)  
PD1_5 bit in PD1 register = 0  
(P1_5 can be used as an input port when performing  
transmission only)  
CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0  
Input transfer clock  
CKDIR bit in U0MR register = 1  
PD1_6 bit in PD1 register = 0  
Rev.1.00 Dec 14, 2007 Page 219 of 332  
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15. Serial Interface  
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)  
TC  
Transfer clock  
TE bit in U0C1  
register  
1
0
Write data to U0TB register  
TI bit in U0C1  
register  
1
0
Stop pulsing  
because the TE bit is set to 0  
Transfer from U0TB register to UART0 transmit register  
Start  
bit  
Parity Stop  
bit  
bit  
TXD0  
ST D0 D1 D2 D3 D4 D5 D6 D7  
P
ST D0 D1 D2 D3 D4 D5 D6 D7  
P
SP  
ST D0 D1  
SP  
1
0
TXEPT bit  
U0C0 register  
IR bit in  
S0TIC register  
1
0
Set to 0 when interrupt request is acknowledged, or set by a program  
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT  
The above timing diagram applies under the following conditions:  
• PRYE bit in U0MR register = 1 (parity enabled)  
• STPS bit in U0MR register = 0 (1 stop bit)  
fj: Frequency of U0BRG count source (f1, f8, f32)  
fEXT: Frequency of U0BRG count source (external clock)  
• U0IRS bit in U0C1 register = 1 (an interrupt request is generated when transmit completes)  
n: Setting value to U0BRG register  
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)  
TC  
Transfer clock  
TE bit in U0C1  
register  
1
0
Write data to U0TB register  
1
0
TI bit in U0C1  
register  
Transfer from U0TB register to UART0 transmit register  
Stop Stop  
bit bit  
Start  
bit  
TXD0  
ST D0 D1 D2 D3 D4 D5 D6 D7 D8  
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP  
ST D0 D1  
SP SP  
TXEPT bit in  
U0C0 register  
1
0
IR bit in  
S0TIC register  
1
0
Set to 0 when interrupt request is acknowledged, or set by a program  
The above timing diagram applies under the following conditions:  
• PRYE bit in U0MR register = 0 (parity disabled)  
• STPS bit in U0MR register = 1 (2 stop bits)  
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT  
fj: Frequency of U0BRG count source (f1, f8, f32)  
fEXT: Frequency of U0BRG count source (external clock)  
n: Setting value to U0BRG register  
• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when transmit buffer is empty)  
Figure 15.11 Transmit Timing in UART Mode  
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15. Serial Interface  
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)  
U0BRG output  
1
0
RE bit in  
U0C1 register  
Stop bit  
Start bit  
RXD0  
D0  
D1  
D7  
Determined to be “L”  
Receive data taken in  
Transfer clock  
Reception triggered when transfer clock  
is generated by falling edge of start bit  
Transferred from UART0 receive  
register to U0RB register  
RI bit in  
U0C1 register  
1
0
IR bit in  
S0RIC register  
1
0
Set to 0 when interrupt request is accepted, or set by a program  
The above timing diagram applies when the register bits are set as follows:  
• PRYE bit in U0MR register = 0 (parity disabled)  
• STPS bit in U0MR register = 0 (1 stop bit)  
Figure 15.12 Receive Timing Example in UART Mode  
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15. Serial Interface  
15.2.1 Bit Rate  
In UART mode, the bit rate is the frequency divided by the U0BRG register.  
Figure 15.13 shows a Calculation Formula of U0BRG Register Setting Value. Table 15.7 lists the Bit Rate  
Setting Example in UART Mode (Internal Clock Selected).  
UART mode  
• Internal clock selected  
fj  
U0BRG register setting value =  
- 1  
Bit Rate ×16  
fj: Count source frequency of the U0BRG register (f1, f8, or f32)  
• External clock selected  
U0BRG register setting value =  
fEXT  
Bit Rate ×16  
- 1  
fEXT: Count source frequency of the U0BRG register (external clock)  
Figure 15.13 Calculation Formula of U0BRG Register Setting Value  
Table 15.7  
Bit Rate Setting Example in UART Mode (Internal Clock Selected)  
System Clock = 20 MHz  
System Clock = 8 MHz  
BRG  
Count  
Source  
f8  
Bit Rate  
(bps)  
U0BRG  
Actual Time  
(bps)  
U0BRG  
Setting Value Time (bps)  
Actual  
Error (%)  
Error (%)  
Setting Value  
129 (81h)  
64 (40h)  
32 (20h)  
129 (81h)  
86 (56h)  
64 (40h)  
42 (2Ah)  
39 (27h)  
32 (20h)  
23 (17h)  
1200  
2400  
1201.92  
2403.85  
4734.85  
9615.38  
14367.82  
19230.77  
29069.77  
31250.00  
37878.79  
52083.33  
0.16  
0.16  
-1.36  
0.16  
-0.22  
0.16  
0.94  
0.00  
-1.36  
1.73  
51 (33h)  
25 (19h)  
12 (0Ch)  
51 (33h)  
34 (22h)  
25 (19h)  
16 (10h)  
15 (0Fh)  
12 (0Ch)  
9 (09h)  
1201.92  
2403.85  
0.16  
0.16  
0.16  
0.16  
-0.79  
0.16  
2.12  
0.00  
0.16  
-2.34  
f8  
4800  
f8  
4807.69  
9600  
f1  
9615.38  
14400  
19200  
28800  
31250  
38400  
51200  
f1  
14285.71  
19230.77  
29411.76  
31250.00  
38461.54  
50000.00  
f1  
f1  
f1  
f1  
f1  
Rev.1.00 Dec 14, 2007 Page 222 of 332  
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15. Serial Interface  
15.3 Notes on Serial Interface  
When reading data from the U0RB register either in the clock synchronous serial I/O mode or in the clock  
asynchronous serial I/O mode, ensure the data is read in 16-bit units. When the high-order byte of the U0RB  
register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0.  
The check receive errors, read the U0RB register and then use the read data.  
Example (when reading receive buffer register):  
MOV.W  
00A6H,R0  
; Read the U0RB register  
When writing data to the U0TB register in the clock asynchronous serial I/O mode with 9-bit transfer data  
length, write data to the high-order byte first then the low-order byte, in 8-bit units.  
Example (when reading transmit buffer register):  
MOV.B  
MOV.B  
#XXH,00A3H ; Write the high-order byte of U0TB register  
#XXH,00A2H ; Write the low-order byte of U0TB register  
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16. Hardware LIN  
16. Hardware LIN  
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.  
16.1 Features  
The hardware LIN has the features listed below.  
Figure 16.1 shows a Block Diagram of Hardware LIN.  
Master mode  
Generates Synch Break  
Detects bus collision  
Slave mode  
Detects Synch Break  
Measures Synch Field  
Controls Synch Break and Synch Field signal inputs to UART0  
Detects bus collision  
NOTE:  
1. The WakeUp function is detected by INT1.  
Hardware LIN  
Synch Field  
RXD0 pin  
control  
circuit  
Timer RA  
TIOSEL = 0  
TIOSEL = 1  
RXD data  
Timer RA  
RXD0 input  
control  
LSTART bit  
SBE bit  
underflow signal  
Timer RA  
interrupt  
circuit  
LINE bit  
Interrupt  
control  
circuit  
Bus collision  
detection  
circuit  
UART0  
Bits BCIE,  
SBIE, and SFIE  
UART0 transfer clock  
UART0 TE bit  
Timer RA output pulse  
MST bit  
UART0 TXD data  
TXD0 pin  
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register  
TIOSEL: Bit in TRAIOC register  
TE: Bit in U0C1 register  
Figure 16.1  
Block Diagram of Hardware LIN  
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16. Hardware LIN  
16.2 Input/Output Pins  
The pin configuration of the hardware LIN is listed in Table 16.1.  
Table 16.1  
Pin Configuration  
Abbreviation Input/Output  
Name  
Function  
Receive data input  
RXD0  
TXD0  
Input  
Receive data input pin of the hardware LIN  
Transmit data output pin of the hardware LIN  
Transmit data output  
Output  
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16. Hardware LIN  
16.3 Register Configuration  
The hardware LIN contains the registers listed below.  
These registers are detailed in Figures 16.2 and 16.3.  
LIN Control Register (LINCR)  
LIN Status Register (LINST)  
LIN Control Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
LINCR  
Address  
0106h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Synch Field measurement-  
completed interrupt enable bit  
0 : Disables Synch Field measurement-  
completed interrupt  
1 : Enables Synch Field measurement-  
completed interrupt  
SFIE  
Synch Break detection interrupt 0 : Disables Synch Break detection interrupt  
enable bit 1 : Enables Synch Break detection interrupt  
Bus collision detection interrupt 0 : Disables bus collision detection interrupt  
SBIE  
BCIE  
RW  
RW  
RO  
enable bit  
1 : Enables bus collision detection interrupt  
RXD0 input status flag  
0 : RXD0 input enabled  
1 : RXD0 input disabled  
RXDSF  
Synch Break detection start bit(1) When this bit is set to 1, timer RA input is  
enabled and RXD0 input is disabled.  
LSTART  
SBE  
RW  
RW  
When read, the content is 0.  
RXD0 input unmasking timing  
select bit (effective only in slave 1 : Unmasked after Synch Field measurement  
mode) is completed  
0 : Unmasked after Synch Break is detected  
LIN operation mode setting bit(2) 0 : Slave mode  
(Synch Break detection circuit actuated)  
MST  
LINE  
RW  
RW  
1 : Master mode  
(timer RA output OR’ed w ith TXD0)  
LIN operation start bit  
0 : Causes LIN to stop  
1 : Causes LIN to start operating(3)  
NOTES:  
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.  
2. Before changing LIN operation modes, temporarily stop the LIN operation (LINEbit = 0).  
3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to  
Figure 16.5 Example of  
and  
Header Field Transmission Flowchart (1)  
.)  
Figure 16.9 Example of Header Field Reception Flowchart  
(2)  
Figure 16.2  
LINCR Register  
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16. Hardware LIN  
LIN Status Register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
Address  
0107h  
After Reset  
00h  
LINST  
Bit Symbol  
Bit Name  
Synch Field measurement-  
completed flag  
Function  
RW  
1 show s Synch Field measurement completed.  
SFDCT  
SBDCT  
BCDCT  
B0CLR  
B1CLR  
B2CLR  
RO  
RO  
RO  
RW  
RW  
RW  
Synch Break detection flag 1 show s Synch Break detected or Synch Break  
generation completed.  
Bus collision detection flag  
1 show s Bus collision detected.  
SFDCT bit clear bit  
When this bit is set to 1, the SFDCT bit is set to 0.  
When read, the content is 0.  
SBDCT bit clear bit  
When this bit is set to 1, the SBDCT bit is set to 0.  
When read, the content is 0.  
BCDCT bit clear bit  
When this bit is set to 1, the BCDCT bit is set to 0.  
When read, the content is 0.  
(b7-b6)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 16.3  
LINST Register  
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16. Hardware LIN  
16.4 Functional Description  
16.4.1 Master Mode  
Figure 16.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.  
Figures 16.5 and 16.6 show an Example of Header Field Transmission Flowchart.  
When transmitting a header field, the hardware LIN operates as described below.  
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware  
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for  
timer RA.  
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of  
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the  
LINCR register is set to 1, it generates a timer RA interrupt.  
(3) The hardware LIN transmits 55h via UART0.  
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.  
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.  
Synch Break  
Synch Field  
IDENTIFIER  
1
0
TXD0 pin  
Set by writing 1 to the  
B1CLR bit in the LINST  
register  
SBDCT flag in  
LINST register  
1
0
Cleared to 0 upon  
acceptance of interrupt  
request or by a program  
IR bit in  
TRAIC register  
1
0
(1)  
(2) (3)  
(4)  
(5)  
The above applies under the following conditions.  
LINE = 1, MST = 1, SBIE = 1  
LINE, MST, SBIE: Bits in LINCR register  
Figure 16.4  
Typical Operation when Sending a Header Field  
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Timer RA Set to timer mode  
16. Hardware LIN  
Bits TMOD0 to TMOD2 in TRAMR register 000b  
Timer RA Set the pulse output level from low to start  
TEDGSEL bit in TRAIOC register 1  
For the hardware LIN  
function, set the TIOSEL bit  
in the TRAIOC register to 1.  
Timer RA Set the INT1/TRAIO pin to P1_5  
TIOSEL bit in TRAIOC register 1  
Timer RA Set the count source (f1, f2, f8, fOCO)  
Bits TCK0 to TCK2 in TRAMR register  
Set the count source and  
registers TRA and TRAPRE  
as suitable for the Synch  
Break period.  
Timer RA Set the Synch Break width  
TRAPRE register  
TRA register  
UART0 Set to transmit/receive mode  
(Transfer data length: 8 bits, Internal clock, 1 stop bit,  
Parity disabled)  
U0MR register  
UART0 Set the BRG count source (f1, f8, f32)  
Bits CLK0 to CLK2 in U0C0 register  
Set the BRG count source  
and U0BRG register as  
appropriate for the bit rate.  
UART0 Set the bit rate  
U0BRG register  
Hardware LIN Set the LIN operation to stop  
LINCR register LINE bit 0  
Hardware LIN Set to master mode  
MST bit in LINCR register 1  
Hardware LIN Set the LIN operation to start  
LINE bit in LINCR register 1  
Hardware LIN Set the register to enable interrupts  
(Bus collision detection, Synch Break detection,  
Synch Field measurement)  
Bits BCIE, SBIE, SFIE in LINCR register  
During master mode, the  
Synch Field measurement-  
completed interrupt cannot be  
used.  
Hardware LIN Clear the status flags  
(Bus collision detection, Synch Break detection,  
Synch Field measurement)  
Bits B2CLR, B1CLR, B0CLR in LINST register 1  
A
Figure 16.5  
Example of Header Field Transmission Flowchart (1)  
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16. Hardware LIN  
A
Timer RA generates Synch Break.  
Timer RA Set the timer to start counting  
TSTART bit in TRACR register 1  
If registers TRAPRE and TRA for  
timer RA do not need to be read or  
the register settings do not need to be  
changed after writing 1 to the  
TSTART bit, the procedure for reading  
TCSTF flag = 1 can be omitted.  
Zero to one cycle of the timer RA  
count source is required after timer  
RA starts counting before the TCSTF  
flag is set to 1.  
Timer RA Read the count status flag  
TCSTF flag in TRACR register  
NO  
TCSTF = 1 ?  
YES  
The timer RA interrupt may be used  
to terminate generation of Synch  
Break.  
Hardware LIN Read the Synch Break detection flag  
SBDCT flag in LINST register  
Three to five cycles of the CPU clock  
are required after Synch Break  
generation completes before the  
SBDCT flag is set to 1.  
NO  
SBDCT = 1 ?  
YES  
After timer RA Synch Break is  
generated, the timer should be made  
to stop counting.  
Timer RA Set the timer to stop counting  
TSTART bit in TRACR register 0  
If registers TRAPRE and TRA for timer  
RA do not need to be read or the  
register settings do not need to be  
changed after writing 0 to the TSTART  
bit, the procedure for reading TCSTF  
flag = 0 can be omitted.  
Zero to one cycle of the timer RA count  
source is required after timer RA stops  
counting before the TCSTF flag is set  
to 0.  
Timer RA Read the count status flag  
TCSTF flag in TRACR register  
NO  
TCSTF = 0 ?  
YES  
UART0 Communication via UART0  
TE bit in U0C1 register 1  
U0TB register 0055h  
Transmit the Synch Field.  
UART0 Communication via UART0  
Transmit the ID field.  
U0TB register ID field  
Figure 16.6  
Example of Header Field Transmission Flowchart (2)  
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16. Hardware LIN  
16.4.2 Slave Mode  
Figure 16.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure  
16.8 through Figure 16.10 show an Example of Header Field Transmission Flowchart.  
When receiving a header field, the hardware LIN operates as described below.  
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware  
LIN.  
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware  
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.  
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA  
interrupt. Then it goes to Synch Field measurement.  
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and  
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal  
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.  
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch  
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.  
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA  
and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via  
UART0.  
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.  
Synch Break  
Synch Field  
IDENTIFIER  
1
0
RXD0 pin  
RXD0 input for  
UART0  
1
0
Set by writing 1 to  
the LSTART bit in  
the LINCR register  
Cleared to 0 when Synch  
Field measurement  
finishes  
RXDSF flag in  
LINCR register  
1
0
Set by writing 1 to  
the B1CLR bit in  
the LINST register  
SBDCT flag in  
LINST register  
1
0
Set by writing 1 to the  
B0CLR bit in the LINST  
register  
Measure this period  
SFDCT flag in  
LINST register  
1
0
Cleared to 0 upon  
acceptance of  
interrupt request or  
by a program  
IR bit in  
TRAIC register  
1
0
(1)  
(2) (3)  
(4)  
(5)  
(6)  
The above applies under the following conditions.  
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1  
LINE, MST, SBE, SBIE, SFIE: Bits in LINCR register  
Figure 16.7  
Typical Operation when Receiving a Header Field  
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16. Hardware LIN  
Timer RA Set to pulse width measurement mode  
Bits TMOD0 to TMOD2 in the TRAMR register 011b  
Timer RA Set the pulse width measurement level low  
TEDGSEL bit in the TRAIOC register 0  
For the hardware LIN  
function, set the TIOSEL bit  
in the TRAIOC register to 1.  
Timer RA Set the INT1/TRAIO pin to P1_5  
TIOSEL bit in the TRAIOC register 1  
Timer RA Set the count source (f1, f2, f8, fOCO)  
Bits TCK0 to TCK2 in the TRAMR register  
Set the count source and registers  
TRA and TRAPRE as appropriate  
for the Synch Break period.  
Timer RA Set the Synch Break width  
TRAPRE register  
TRA register  
Hardware LIN Set the LIN operation to stop  
LINE bit in the LINCR register 0  
Hardware LIN Set to slave mode  
MST bit in the LINCR register 0  
Hardware LIN Set the LIN operation to start  
LINE bit in the LINCR register 1  
Select the timing at which to  
unmask the RXD0 input for UART0.  
If the RXD0 input is chosen to be  
unmasked after detection of Synch  
Break, the Synch Field signal is  
also input to UART0.  
Hardware LIN Set the RXD0 input unmasking timing  
(After Synch Break detection, or after Synch  
Field measurement)  
SBE bit in the LINCR register  
Hardware LIN Set the register to enable interrupts  
(Bus collision detection, Synch Break detection,  
Synch Field measurement)  
Bits BCIE, SBIE, SFIE in the LINCR register  
A
Figure 16.8  
Example of Header Field Reception Flowchart (1)  
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16. Hardware LIN  
A
Hardware LIN Clear the status flags  
(Bus collision detection, Synch Break  
detection, Synch Field measurement)  
Bits B2CLR, B1CLR, B0CLR in the LINST  
register 1  
Timer RA waits until the timer starts  
counting.  
Timer RA Set to start a pulse width measurement  
TSTART bit in the TRACR register 1  
Timer RA Read the count status flag  
TCSTF flag in the TRACR register  
Zero to one cycle of the timer RA  
count source is required after timer  
RA starts counting before the TCSTF  
flag is set to 1.  
NO  
TCSTF = 1 ?  
YES  
Hardware LIN waits until the RXD0  
input for UART0 is masked.  
Hardware LIN Set to start Synch Break detection  
LSTART bit in the LINCR register 1  
Do not apply “L” level to the RXD pin  
until the RXDSF flag reads 1 after  
writing 1 to the LSTART bit. This is  
because the signal applied during this  
time is input directly to UART0.  
Three to five cycles of the CPU clock  
are required after the LSTART bit is  
set to 1 before the RXDSF flag is set  
to 1. After this, input to timer RA and  
UART0 is enabled.  
Hardware LIN Read the RXD0 input status flag  
RXDSF flag in the LINCR register  
NO  
RXDSF = 1 ?  
YES  
Hardware LIN detects a Synch Break.  
The interrupt of the timer RA may be  
used.  
Hardware LIN Read the Synch Break detection flag  
SBDCT flag in the LINST register  
When Synch Break is detected, timer  
RA is reloaded with the initially set  
count value.  
Even if the duration of the input “L”  
level is shorter than the set period,  
timer RA is reloaded with the initially  
set count value and waits until the  
next “L” level is input.  
NO  
SBDCT = 1 ?  
YES  
B
Three to five cycles of the CPU clock  
are required after Synch Break  
detection before the SBDCT flag is  
set to 1.  
When the SBE bit in the LINCR  
register is set to 0 (unmasked after  
Synch Break is detected), timer RA  
can be used in timer mode after the  
SBDCT flag in the LINST register is  
set to 1 and the RXDSF flag is set to  
0.  
Figure 16.9  
Example of Header Field Reception Flowchart (2)  
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16. Hardware LIN  
Hardware LIN measures the Synch  
Field.  
B
YES  
The interrupt of timer RA may be  
used (the SBDCT flag is set when  
the timer RA counter underflows  
upon reaching the terminal count).  
When the SBE bit in the LINCR  
register is set to 1 (unmasked after  
Synch Field measurement is  
completed), timer RA may be used  
in timer mode after the SFDCT bit  
in the LINST register is set to 1.  
Hardware LIN Read the Synch Field measurement-  
completed flag  
SFDCT flag in the LINST register  
NO  
SFDCT = 1 ?  
YES  
UART0 Set the UART0 communication rate  
U0BRG register  
Set a communication rate based on  
the Synch Field measurement  
result.  
Timer RA Set the Synch Break width again  
TRAPRE register  
TRA register  
Communication via UART0  
UART0 Communication via UART0  
Clock asynchronous serial interface (UART) mode  
Transmit ID field  
(The SBDCT flag is set when the  
timer RA counter underflows upon  
reaching the terminal count.)  
Figure 16.10 Example of Header Field Reception Flowchart (3)  
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16. Hardware LIN  
16.4.3 Bus Collision Detection Function  
The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1  
register = 1).  
Figure 16.11 shows Typical Operation when a Bus Collision is Detected.  
1
TXD0 pin  
0
1
RXD0 pin  
0
1
Transfer clock  
0
Set to 1 by a program  
LINE bit in the  
LINCR register  
1
0
Set to 1 by a program  
TE bit in the U0C1  
register  
1
0
Set by writing 1 to  
the B2CLR bit in the  
LINST register  
BCDCT flag in the  
LINST register  
1
0
Cleared to 0 upon  
acceptance of interrupt  
request or by a program  
IR bit in the TRAIC  
register  
1
0
Figure 16.11 Typical Operation when a Bus Collision is Detected  
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16. Hardware LIN  
16.4.4 Hardware LIN End Processing  
Figure 16.12 shows an Example of Hardware LIN Communication Completion Flowchart.  
Use the following timing for hardware LIN end processing:  
If the hardware bus collision detection function is used  
Perform hardware LIN end processing after checksum transmission completes.  
If the bus collision detection function is not used  
Perform hardware LIN end processing after header field transmission and reception complete.  
Timer RA Set the timer to stop counting  
TSTART bit in TRACR register 0  
Set the timer to stop counting.  
Timer RA Read the count status flag  
TCSTF flag in TRACR register  
Zero to one cycle of the timer RA  
count source is required after timer  
RA starts counting before the  
TCSTF flag is set to 1.  
NO  
TCSTF = 0 ?  
YES  
When the bus collision detection  
function is not used, end  
UART0 Complete transmission via UART0  
processing for the UART0  
transmission is not required.  
Hardware LIN Clear the status flags  
(Bus collision detection, Synch Break detection, Synch  
Field measurement)  
Bits B2CLR, B1CLR, B0CLR in the LINST register 1  
After clearing hardware LIN  
status flag, stop the hardware  
LIN operation.  
Hardware LIN Set the LIN operation to stop  
LINE bit in the LINCR register 0  
Figure 16.12 Example of Hardware LIN Communication Completion Flowchart  
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16. Hardware LIN  
16.5 Interrupt Requests  
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break  
generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are  
shared with timer RA.  
Table 16.2 lists the Interrupt Requests of Hardware LIN.  
Table 16.2  
Interrupt Requests of Hardware LIN  
Interrupt Request  
Status Flag  
SBDCT  
Cause of Interrupt  
Synch Break detection  
Generated when timer RA has underflowed after measuring  
the “L” level duration of RXD0 input, or when a “L” level is  
input for a duration longer than the Synch Break period during  
communication.  
Synch Break generation  
completed  
Generated when “L” level output to TXD0 for the duration set  
by timer RA completes.  
Synch Field measurement  
completed  
Generated when measurement for 6 bits of the Synch Field by  
timer RA is completed.  
SFDCT  
BCDCT  
Bus collision detection  
Generated when the RXD0 input and TXD0 output values  
differed at data latch timing while UART0 is enabled for  
transmission.  
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16. Hardware LIN  
16.6 Notes on Hardware LIN  
For the time-out processing of the header and response fields, use another timer to measure the duration of time  
with a Synch Break detection interrupt as the starting point.  
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17. A/D Converter  
17. A/D Converter  
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling  
amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that  
the corresponding port direction bits are set to 0 (input mode).  
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no  
current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip.  
The result of A/D conversion is stored in the AD register.  
Table 17.1 lists the Performance of A/D converter. Figure 17.1 shows a Block Diagram of A/D Converter.  
Figures 17.2 and 17.3 show the A/D converter-related registers.  
Table 17.1  
Performance of A/D converter  
Item  
Performance  
Successive approximation (with capacitive coupling amplifier)  
0 V to AVCC  
A/D conversion method  
(1)  
Analog input voltage  
(2)  
4.2 V AVCC 5.5 V f1, f2, f4, fOCO-F  
2.7 V AVCC < 4.2 V f2, f4, fOCO-F  
8 bits or 10 bits selectable  
Operating clock φAD  
Resolution  
Absolute accuracy  
AVCC = Vref = 5 V, φAD = 10 MHz  
• 8-bit resolution ±2 LSB  
• 10-bit resolution ±3 LSB  
AVCC = Vref = 3.3 V, φAD = 10 MHz  
• 8-bit resolution ±2 LSB  
• 10-bit resolution ±5 LSB  
(3)  
Operating mode  
Analog input pin  
One-shot and repeat  
12 pins (AN0 to AN11)  
A/D conversion start condition Software trigger  
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)  
Conversion rate per pin  
• Without sample and hold function  
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles  
• With sample and hold function  
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles  
NOTES:  
1. The analog input voltage does not depend on use of a sample and hold function.  
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh  
in 10-bit mode and FFh in 8-bit mode.  
2. When 2.7 V AVCC 5.5 V, the frequency of φAD must be 10 MHz or below.  
Without a sample and hold function, the φAD frequency should be 250 kHz or above.  
With a sample and hold function, the φAD frequency should be 1 MHz or above.  
3. In repeat mode, only 8-bit mode can be used.  
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17. A/D Converter  
CKS0 = 1  
CKS0 = 0  
fOCO-F  
A/D conversion rate selection  
CKS1 = 1  
f1  
CKS0 = 1  
φAD  
f2  
CKS1 = 0  
f4  
CKS0 = 0  
VCUT = 0  
VCUT = 1  
AVSS  
VREF  
Resistor ladder  
Successive conversion register  
ADCON0  
Vcom  
AD register  
Data bus  
Decoder  
Comparator  
VIN  
CH2 to CH0 = 000b  
CH2 to CH0 = 001b  
P0_7/AN0  
P0_6/AN1  
P0_5/AN2  
P0_4/AN3  
P0_3/AN4  
P0_2/AN5  
P0_1/AN6  
P0_0/AN7  
CH2 to CH0 = 010b  
CH2 to CH0 = 011b  
ADGSEL0 = 0  
CH2 to CH0 = 100b  
CH2 to CH0 = 101b  
CH2 to CH0 = 110b  
CH2 to CH0 = 111b  
ADGSEL0 = 1  
CH2 to CH0 = 100b  
CH2 to CH0 = 101b  
P1_0/AN8  
P1_1/AN9  
P1_2/AN10  
P1_3/AN11  
CH2 to CH0 = 110b  
CH2 to CH0 = 111b  
CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register  
CKS1, VCUT: Bits in ADCON1 register  
Figure 17.1  
Block Diagram of A/D Converter  
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A/D Control Register 0(1)  
17. A/D Converter  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
ADCON0  
Address  
00D6h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Analog input pin select bits (Note 4)  
CH0  
CH1  
RW  
RW  
RW  
RW  
RW  
RW  
CH2  
A/D operating mode select 0 : One-shot mode  
MD  
bit(2)  
1 : Repeat mode  
A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7)  
1 : Selects port P1 group (AN8 to AN11)  
ADGSEL0  
(b5)  
Reserved bit  
Set to 0.  
A/D conversion start flag 0 : Stops A/D conversion  
1 : Starts A/D conversion  
ADST  
Frequency select bit 0  
[When CKS1 in ADCON1 register = 0]  
0 : Select f4  
1 : Select f2  
[When CKS1 in ADCON1 register = 1]  
0 : Select f1(3)  
CKS0  
RW  
1 : Select fOCO-F  
NOTES:  
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.  
2. When changing A/D operation mode, set the analog input pin again.  
3. Set øAD frequency to 10 MHz or below .  
4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit.  
CH2 to CH0 ADGSEL0 = 0  
ADGSEL0 = 1  
Do not set.  
000b  
001b  
010b  
011b  
100b  
101b  
110b  
111b  
AN0  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
AN8  
AN9  
AN10  
AN11  
Figure 17.2  
ADCON0 Register  
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17. A/D Converter  
A/D Control Register 1(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
0 0 0  
Symbol  
ADCON1  
Bit Symbol  
Address  
00D7h  
After Reset  
00h  
Bit Name  
Function  
RW  
RW  
(b2-b0)  
Reserved bits  
Set to 0.  
8/10-bit mode select bit(2)  
Frequency select bit 1  
VREF connect bit(3)  
Reserved bits  
0 : 8-bit mode  
1 : 10-bit mode  
BITS  
CKS1  
VCUT  
RW  
Refer to the description of the CKS0 bit in the  
ADCON0 register function.  
RW  
RW  
RW  
0 : VREF not connected  
1 : VREF connected  
(b6-b7)  
Set to 0.  
NOTES:  
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.  
2. Set the BITS bit to 0 (8-bit mode) in repeat mode.  
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting  
A/D conversion.  
A/D Control Register 2(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0  
Symbol  
ADCON2  
Bit Symbol  
Address  
00D4h  
After Reset  
00h  
Bit Name  
Function  
RW  
RW  
A/D conversion method select bit  
0 : Without sample and hold  
1 : With sample and hold  
SMP  
(b3-b1)  
Reserved bits  
Set to 0.  
RW  
(b7-b4)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result is undefined.  
A/D Register  
(b15)  
b7  
(b8)  
b0  
b7  
b0  
Symbol  
AD  
Address  
00C1h-00C0h  
After Reset  
Undefined  
Function  
When BITS bit in ADCON1 register is  
set to 1 (10-bit mode).  
When BITS bit in ADCON1 register is  
set to 0 (8-bit mode).  
RW  
8 low -order bits in A/D conversion result  
2 high-order bits in A/D conversion result  
A/D conversion result  
When read, the content is undefined.  
RO  
RO  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
Figure 17.3  
Registers ADCON1, ADCON2, and AD  
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17. A/D Converter  
17.1 One-Shot Mode  
In one-shot mode, the input voltage of one selected pin is A/D converted once.  
Table 17.2 lists the Specification of One-Shot Mode. Figure 17.4 shows the ADCON0 Register in One-Shot Mode  
and Figure 17.5 shows the ADCON1 Register in One-Shot Mode.  
Table 17.2  
Specification of One-Shot Mode  
Item  
Specification  
Function  
The input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is  
A/D converted once  
Start condition  
Stop condition  
Set the ADST bit to 1 (A/D conversion starts)  
• A/D conversion completes (ADST bit is set to 0)  
• Set the ADST bit to 0  
Interrupt request generation A/D conversion completes  
timing  
Input pin  
Select one of AN0 to AN11  
Reading of A/D conversion Read AD register  
result  
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17. A/D Converter  
A/D Control Register 0(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0
0
Symbol  
ADCON0  
Bit Symbol  
Address  
00D6h  
After Reset  
00h  
Bit Name  
Function  
RW  
RW  
Analog input pin select bits (Note 4)  
CH0  
CH1  
RW  
RW  
RW  
RW  
RW  
RW  
CH2  
A/D operating mode select 0 : One-shot mode  
bit(2)  
A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7)  
1 : Selects port P1 group (AN8 to AN11)  
MD  
ADGSEL0  
(b5)  
Reserved bit  
Set to 0.  
A/D conversion start flag 0 : Stops A/D conversion  
1 : Starts A/D conversion  
ADST  
CKS0  
Frequency select bit 0  
[When CKS1 in ADCON1 register = 0]  
0 : Select f4  
1 : Select f2  
[When CKS1 in ADCON1 register = 1]  
0 : Select f1(3)  
RW  
1 : Select fOCO-F  
NOTES:  
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.  
2. After changing the A/D operating mode, select the analog input pin again.  
3. Set øAD frequency to 10 MHz or below .  
4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit.  
CH2 to CH0 ADGSEL0 = 0  
ADGSEL0 = 1  
Do not set.  
000b  
001b  
010b  
011b  
100b  
101b  
110b  
111b  
AN0  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
AN8  
AN9  
AN10  
AN11  
Figure 17.4  
ADCON0 Register in One-Shot Mode  
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17. A/D Converter  
A/D Control Register 1(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 1  
0 0 0  
Symbol  
ADCON1  
Bit Symbol  
Address  
00D7h  
After Reset  
00h  
Bit Name  
Function  
RW  
RW  
(b2-b0)  
Reserved bits  
Set to 0.  
8/10-bit mode select bit  
Frequency select bit 1  
VREF connect bit(2)  
Reserved bits  
0 : 8-bit mode  
1 : 10-bit mode  
BITS  
CKS1  
VCUT  
RW  
Refer to the description of the CKS0 bit in the  
ADCON0 register function.  
RW  
RW  
RW  
1 : VREF connected  
(b6-b7)  
Set to 0.  
NOTES:  
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.  
2. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting  
A/D conversion.  
Figure 17.5  
ADCON1 Register in One-Shot Mode  
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17. A/D Converter  
17.2 Repeat Mode  
In repeat mode, the input voltage of one selected pin is A/D converted repeatedly.  
Table 17.3 lists the Repeat Mode Specifications. Figure 17.6 shows the ADCON0 Register in Repeat Mode and  
Figure 17.7 shows ADCON1 Register in Repeat Mode.  
Table 17.3  
Repeat Mode Specifications  
Item  
Specification  
Function  
The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is  
A/D converted repeatedly  
Start conditions  
Stop condition  
Set the ADST bit to 1 (A/D conversion starts)  
Set the ADST bit to 0  
Interrupt request generation Not generated  
timing  
Input pin  
Select one of AN0 to AN11  
Read AD register  
Reading of result of A/D  
converter  
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17. A/D Converter  
A/D Control Register 0(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0
1
Symbol  
ADCON0  
Bit Symbol  
Address  
00D6h  
After Reset  
00h  
Bit Name  
Function  
RW  
RW  
Analog input pin select bits (Note 4)  
CH0  
CH1  
RW  
RW  
RW  
RW  
RW  
RW  
CH2  
A/D operating mode select 1 : Repeat mode  
bit(2)  
A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7)  
1 : Selects port P1 group (AN8 to AN11)  
MD  
ADGSEL0  
(b5)  
Reserved bit  
Set to 0.  
A/D conversion start flag 0 : Stops A/D conversion  
1 : Starts A/D conversion  
ADST  
CKS0  
Frequency select bit 0  
[When CKS1 in ADCON1 register = 0]  
0 : Select f4  
1 : Select f2  
[When CKS1 in ADCON1 register = 1]  
0 : Select f1(3)  
RW  
1 : Do not set.  
NOTES:  
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.  
2. After changing A/D operation mode, select the analog input pin again.  
3. Set øAD frequency to 10 MHz or below .  
4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit.  
CH2 to CH0 ADGSEL0 = 0  
ADGSEL0 = 1  
Do not set.  
000b  
001b  
010b  
011b  
100b  
101b  
110b  
111b  
AN0  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
AN8  
AN9  
AN10  
AN11  
Figure 17.6  
ADCON0 Register in Repeat Mode  
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17. A/D Converter  
A/D Control Register 1(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 1  
0 0 0 0  
Symbol  
ADCON1  
Bit Symbol  
Address  
00D7h  
After Reset  
00h  
Bit Name  
Function  
RW  
RW  
(b2-b0)  
Reserved bits  
Set to 0.  
8/10-bit mode select bit(2)  
Frequency select bit 1  
VREF connect bit(3)  
Reserved bits  
0 : 8-bit mode  
BITS  
CKS1  
VCUT  
RW  
Refer to the description of the CKS0 bit in the  
ADCON0 register function.  
RW  
RW  
RW  
1 : VREF connected  
(b6-b7)  
Set to 0.  
NOTES:  
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.  
2. Set the BITS bit to 0 (8-bit mode) in repeat mode.  
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting  
A/D conversion.  
Figure 17.7  
ADCON1 Register in Repeat Mode  
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17. A/D Converter  
17.3 Sample and Hold  
When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate  
per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after  
selecting whether the sample and hold circuit is to be used or not.  
Figure 17.8 shows a Timing Diagram of A/D Conversion.  
Sample and hold  
disabled  
Conversion time of 1st bit  
2nd bit  
Comparison  
Comparison  
time  
Comparison  
time  
Sampling time  
4ø AD cycles  
Sampling time  
2.5ø AD cycles  
Sampling time  
2.5ø AD cycles  
time  
* Repeat until conversion ends  
Sample and hold  
enabled  
2nd bit  
Conversion time of 1st bit  
Comparison Comparison Comparison Comparison  
time time time time  
Sampling time  
4ø AD cycles  
* Repeat until conversion ends  
Figure 17.8  
Timing Diagram of A/D Conversion  
17.4 A/D Conversion Cycles  
Figure 17.9 shows the A/D Conversion Cycles.  
Conversion time at the 2nd  
bit and the follows  
Conversion time at the 1st bit  
End process  
Conversion Sampling Comparison Sampling Comparison  
End process  
A/D Conversion Mode  
Time  
Time  
4φAD  
4φAD  
4φAD  
4φAD  
Time  
Time  
Time  
Without Sample & Hold  
8 bits  
10 bits  
8 bits  
49φAD  
59φAD  
28φAD  
33φAD  
2.0φAD  
2.0φAD  
2.5φAD  
2.5φAD  
2.5φAD  
2.5φAD  
0.0φAD  
0.0φAD  
2.5φAD  
2.5φAD  
2.5φAD  
2.5φAD  
8.0φAD  
8.0φAD  
4.0φAD  
4.0φAD  
Without Sample & Hold  
With Sample & Hold  
With Sample & Hold  
10 bits  
Figure 17.9  
A/D Conversion Cycles  
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17. A/D Converter  
17.5 Internal Equivalent Circuit of Analog Input  
Figure 17.10 shows the Internal Equivalent Circuit of Analog Input.  
VCC  
VCC VSS  
AVCC  
ON Resistor  
Approx. 0.6kΩ  
ON Resistor  
Approx. 2kΩ  
Parasitic Diode  
AN0  
Wiring Resistor  
Approx. 0.2kΩ  
C = Approx.1.5pF  
AMP  
Analog Input  
Voltage  
VIN  
SW1  
SW2  
ON Resistor  
Approx. 5kΩ  
Parasitic Diode  
Sampling  
Control Signal  
SW3  
SW4  
VSS  
i=12  
i Ladder-type  
Switches  
i Ladder-type  
Wiring Resistors  
Chopper-type  
Amplifier  
AVSS  
ON Resistor  
Wiring Resistor  
Approx. 2kΩ  
Approx. 0.2kΩ  
AN11  
SW1  
A/D Successive  
Conversion Register  
b4 b2 b1b0  
Reference  
Control Signal  
A/D Control Register 0  
Vref  
VREF  
Comparison  
voltage  
Approx. 0.6k f  
SW5  
Resistor  
ladder  
ON Resistor  
A/D Conversion  
Interrupt Request  
AVSS  
Comparison reference voltage  
(Vref) generator  
Sampling  
Connect to  
Comparison  
SW1 conducts only on the ports selected for analog input.  
SW2 and SW3 are open when A/D conversion is not in progress;  
their status varies as shown by the waveforms in the diagrams on the left.  
Control signal  
for SW2  
Connect to  
Connect to  
Connect to  
SW4 conducts only when A/D conversion is not in progress.  
SW5 conducts when compare operation is in progress.  
Control signal  
for SW3  
NOTE:  
1. Use only as a standard for designing this data.  
Mass production may cause some changes in device characteristics.  
Figure 17.10 Internal Equivalent Circuit of Analog Input  
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17. A/D Converter  
17.6 Output Impedance of Sensor under A/D Conversion  
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 17.11 has to be completed  
within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor  
equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X,  
and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).  
1
-------------------------- t  
C(R0 + R)   
VC is generally  
And when t = T,  
e
VC= VIN  
1
X
Y
X
Y
VC = VIN --- VIN = VIN 1 – ---  
1
-------------------------- T  
X
Y
C(R0 + R)  
e
= ---  
1
X
Y
-------------------------- T= ln---  
C(R0 + R)  
T
Hence,  
R0= – ------------------- – R  
X
C ln---  
Y
Figure 17.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN  
and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-  
(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to  
0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision  
added to 0.1LSB.  
When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode without sample and hold. Output impedance R0  
for sufficiently charging capacitor C within time T is determined as follows.  
T = 0.25 µs, R = 2.8 k, C = 6.0 pF, X = 0.1, and Y = 1024. Hence,  
–6  
3
3
0.25 × 10  
R0= –--------------------------------------------------–2.8×10 1.7×10  
0.1  
–12  
6.0 × 10  
ln-----------  
1024  
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less,  
is approximately 1.7 k. maximum.  
MCU  
Sensor equivalent  
circuit  
R0  
R (2.8 k)  
VIN  
C (6.0 pF)  
VC  
NOTE:  
1. The capacity of the terminal is assumed to be 4.5 pF.  
Figure 17.11 Analog Input Pin and External Sensor Equivalent Circuit  
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17. A/D Converter  
17.7 Notes on A/D Converter  
Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit  
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).  
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF  
connected), wait for at least 1 µs before starting the A/D conversion.  
After changing the A/D operating mode, select an analog input pin again.  
When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The  
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D  
conversion is completed.  
When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the  
CPU clock during A/D conversion.  
Do not select the fOCO-F for the φAD.  
If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion  
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be  
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.  
Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.  
Do not enter stop mode during A/D conversion.  
Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in  
wait mode) during A/D conversion.  
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18. D/A Converter  
18. D/A Converter  
The D/A converters are 8-bit R-2R type units. The D/A converter 0 and D/A converter 1 are two independent D/A  
converters.  
D/A conversion is performed by writing to the DAi register (i = 0 or 1). To output the conversion result, set the DAiE  
bit in the DACON register to 1 (output enabled) and set the VRiSEL bit in the ACCRi register to 0 (AVREFi pin  
input). Before using D/A conversion, the corresponding port direction bit must be set to 0 (input mode). Setting the  
DAiE bit to 1 removes the pull-up from the corresponding port.  
The output analog voltage (V) is determined by the setting value n (n: decimal) of the DAi register.  
V = Vref × n/256 (n = 0 to 255)  
Vref: Reference voltage  
Table 18.1 lists the D/A Converter Specifications. Figure 18.1 shows the Block Diagram of D/A Converter. Figures  
18.2 and 18.3 show the D/A converter related registers. Figure 18.4 shows the D/A Converter Equivalent Circuit.  
Table 18.1  
D/A Converter Specifications  
Item  
Performance  
D/A conversion method  
Resolution  
R-2R method  
8 bits  
Analog output pins  
2 (DA0 and DA1)  
DA0 register  
0
1
1
R-2R resistor ladder  
DA0  
0
DA0E bit  
VR0SEL bit  
DA1 register  
0
1
R-2R resistor ladder  
DA1  
1
0
DA1E bit  
VR1SEL bit  
DA0E, DA1E: Bits in DACON register  
VR0SEL: Bit in ACCR0 register  
VR1SEL: Bit in ACCR1 register  
Figure 18.1  
Block Diagram of D/A Converter  
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D/Ai Register (i = 0 or 1)(1)  
18. D/A Converter  
b7  
b0  
Symbol  
DA0  
Address  
00D8h  
After Reset  
00h  
00h  
00DAh  
DA1  
Function  
Setting Range  
RW  
RW  
Output value of D/A conversion  
00h to FFh  
NOTE:  
1. When not using the D/A converter, set the DAiEbit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to  
prevent current from flow ing into the R-2R resistor ladder to reduce unnecessary current consumption.  
D/A Control Register(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
DACON  
Address  
00DCh  
After Reset  
00h  
Bit Name  
Function  
Bit Symbol  
RW  
RW  
D/A0 output enable bit  
0 : Output disabled  
1 : Output enabled  
DA0E  
DA1E  
D/A1 output enable bit  
0 : Output disabled  
1 : Output enabled  
RW  
(b7-b2)  
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
NOTE:  
1. When not using the D/A converter, set the DAiEbit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to  
prevent current from flow ing into the R-2R resistor ladder to reduce unnecessary current consumption.  
Figure 18.2  
Registers DA0 to DA1 and DACON  
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18. D/A Converter  
Comparator i Control Register (i = 0 or 1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
ACCR0  
Address  
0174h  
After Reset  
00001000b  
00001000b  
Function  
0175h  
ACCR1  
Bit Symbol  
Bit Name  
RW  
RW  
Comparator i enable operation bit 0 : Disable operation  
1 : Enable operation  
CMiE  
CMiOE  
VRiSEL  
CMiLV  
ACOUTi output enable bit  
0 : Disable output  
1 : Enable output  
RW  
RW  
RO  
Comparator i reference input  
select bit  
0 : AVREFi pin input  
1 : D/A converter i output(1)  
Comparison result monitor flag  
0 : ACMPi input < reference input  
1 : ACMPi input > reference input  
Comparator i digital filter select  
bits  
b5 b4  
0 0 : No filter  
FLTi0  
RW  
0 1 : Filter w ith f2 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
FLTi1  
CMiIE  
RW  
RW  
Comparator i interrupt enable bit 0 : Disable interrupt by CMiF bit  
1 : Enable interrupt by CMiF bit  
Comparator i interrupt flag  
[Source for setting this bit to 0]  
Write 0 after read(2)  
CMiF  
RW  
[Source for setting this bit to 1]  
When the comparison result is changed  
NOTES:  
1. When setting the VRiSEL bit to 1 (D/A converter i output), set the DAiEbit in the DACON register to 1 (output  
enabled). How ever, at this time, the D/A conversion result is not output from DAi pin.  
2. The w riting results are as follow s:  
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.  
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1  
even if it is set to 1 from 0 after reading, and w riting 0.)  
• This bit remains unchanged if 1 is w ritten to it.  
Figure 18.3  
Registers ACCR0 to ACCR1  
DAiE bit  
0
r
R
R
R
R
R
R
R
2R  
DAi  
1
2R  
MSB  
2R  
2R  
2R  
2R  
2R  
2R  
2R  
LSB  
DAi register  
0
1
AVSS  
VREF(2)  
i = 0 to 1  
NOTES:  
1. The above diagram applies when the value of the DAi register is 2Ah.  
2. VREF is not affected by the setting of the VCUT bit in the ADCON1 register.  
Figure 18.4  
D/A Converter Equivalent Circuit  
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19.Comparator  
19. Comparator  
The comparators compare a reference input voltage and an analog input voltage. Comparator 0 and comparator 1 are  
two independent comparators.  
19.1 Overview  
The comparison result of the reference input voltage and analog input voltage can be read by software. The result  
also can be output from the ACOUTi (i = 0 or 1) pin. An input to the AVREFi pin or output from D/A converter i  
can be selected as the reference input voltage.  
Table 19.1 lists the Specifications for Comparator, Figure 19.1 shows the Block Diagram of Comparator, and Table  
19.2 lists the I/O Pins.  
Table 19.1  
Specifications for Comparator  
Item  
Specification  
Analog input voltage  
Reference input voltage  
Comparison result  
Interrupt request  
Input voltage to ACMPi pin  
Input voltage to AVREFi pin or output voltage of D/A converter i  
Read the CMiLV bit in the ACCRi register  
When the comparison result changes  
generation timing  
Select functions  
• The comparison result can be output from the ACOUTi pin.  
• ACOUTi pin output polarity  
Whether the comparison result output is inverted or not inverted can be  
selected.  
• Digital filter function  
For the CMACOUTi signal (comparison result), whether the digital filter is  
applied or not and the sampling frequency can be selected.  
i = 0 or 1  
FLT01 to FLT00  
CM0POR  
= 01b  
Pin output  
select circuit  
f2  
f8  
Sampling clock  
= 10b  
CM0E  
0
= 11b  
CM0LV  
f32  
CM0OE  
0
ACMP0  
+
-
= other than 00b  
1
0
Digital filter  
ACOUT0  
1
AVREF0  
CMACOUT0  
1
= 00b  
signal  
VR0SEL  
FLT11 to FLT10  
= 01b  
CM1POR  
f2  
Sampling clock  
= 10b  
= 11b  
f8  
CM1E  
0
f32  
CM1OE  
0
ACMP1  
+
-
= other than 00b  
1
0
Digital filter  
ACOUT1  
1
AVREF1  
CMACOUT1  
signal  
1
= 00b  
VR1SEL  
CM1LV  
VR0SEL  
1
DA0E  
Comparator 0  
0
1
D/A Converter 0  
D/A Converter 1  
DA0  
interrupt request  
Interrupt control  
circuit  
0
1
Comparator 1  
interrupt request  
0
1
DA1  
0
DA1E  
VR1SEL  
CM0E, CM0OE, VR0SEL, CM0LV, FLT00 to FLT01: Bits in ACCR0 register  
CM1E, CM1OE, VR1SEL, CM1LV, FLT10 to FLT11: Bits in ACCR1 register  
CM0POR, CM1POR: Bits in ACMR register  
DA0E, DA1E: Bits in DACON register  
CMACOUT0 signal, CMACOUT1 signal: Internal signal  
Figure 19.1  
Block Diagram of Comparator  
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19.Comparator  
Table 19.2  
I/O Pins  
Pin Name  
I/O  
Function  
ACMP0  
AVREF0  
ACOUT0  
ACMP1  
AVREF1  
ACOUT1  
Input  
Comparator 0 analog pin  
Input  
Comparator 0 reference voltage pin  
Comparator 0 comparison result output pin  
Comparator 1 analog pin  
Output  
Input  
Input  
Comparator 1 reference voltage pin  
Comparator 1 comparison result output pin  
Output  
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19.Comparator  
19.2 Register Functions  
Figure 19.2 shows the Registers ACCR0 to ACCR1 and Figure 19.3 shows the ACMR Register.  
Comparator i Control Register (i = 0 or 1)  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
ACCR0  
Address  
0174h  
After Reset  
00001000b  
00001000b  
Function  
0175h  
ACCR1  
Bit Symbol  
Bit Name  
RW  
RW  
Comparator i enable operation bit 0 : Disable operation  
1 : Enable operation  
CMiE  
CMiOE  
VRiSEL  
CMiLV  
ACOUTi output enable bit  
0 : Disable output  
1 : Enable output  
RW  
RW  
RO  
Comparator i reference input  
select bit  
0 : AVREFi pin input  
1 : D/A converter i output(1)  
Comparison result monitor flag  
0 : ACMPi input < reference input  
1 : ACMPi input > reference input  
Comparator i digital filter select  
bits  
b5 b4  
0 0 : No filter  
FLTi0  
RW  
0 1 : Filter w ith f2 sampling  
1 0 : Filter w ith f8 sampling  
1 1 : Filter w ith f32 sampling  
FLTi1  
CMiIE  
RW  
RW  
Comparator i interrupt enable bit 0 : Disable interrupt by CMiF bit  
1 : Enable interrupt by CMiF bit  
Comparator i interrupt flag  
[Source for setting this bit to 0]  
Write 0 after read(2)  
CMiF  
RW  
[Source for setting this bit to 1]  
When the comparison result is changed  
NOTES:  
1. When setting the VRiSEL bit to 1 (D/A converter i output), set the DAiEbit in the DACON register to 1 (output  
enabled). How ever, at this time, the D/A conversion result is not output from DAi pin.  
2. The w riting results are as follow s:  
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.  
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1  
even if it is set to 1 from 0 after reading, and w riting 0.)  
• This bit remains unchanged if 1 is w ritten to it.  
Figure 19.2  
Registers ACCR0 to ACCR1  
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19.Comparator  
Comparator Mode Register  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0 0  
0
Symbol  
ACMR  
Address  
0177h  
After Reset  
00h  
Bit Symbol  
Bit Name  
Function  
RW  
ACOUT0 output polarity select bit 0 : Output the non-inverted comparator 0  
comparison result to ACOUT0  
CM0POR  
CM1POR  
RW  
RW  
1 : Output the inverted comparator 0  
comparison result to ACOUT0  
ACOUT1 output polarity select bit 0 : Output the non-inverted comparator 1  
comparison result to ACOUT1  
1 : Output the inverted comparator 1  
comparison result to ACOUT1  
-
Reserved bit  
Set to 0.  
RW  
(b2)  
-
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
(b3)  
-
Reserved bits  
Set to 0.  
RW  
(b6-b4)  
-
Nothing is assigned. If necessary, set to 0.  
When read, the content is 0.  
(b7)  
Figure 19.3  
ACMR Register  
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19.Comparator  
19.3 Functional Description  
Comparator 0 and comparator 1 operate independently. Their operations are the same.  
Table 19.3 lists the Procedure for Setting Registers Associated with Comparator  
Table 19.3  
Procedure for Setting Registers Associated with Comparator  
Bit Setting Value  
Step Register  
1
Function selection of ACMPi, AVREFi, and ACOUTi pin. Refer to 7.4 Port Setting.  
Set registers and bits other than listed in step 2 and the following steps.  
2
3
ACMR  
ACCRi  
CMiPOR  
When using the ACOUTi output: Select the ACOUTi output polarity.  
Select to enable or disable the filter, and select the sampling clock  
frequency.  
FLTi1 to FLTi0  
VRiSEL  
DAiE  
Select the reference input.  
4
DACON  
ACCRi  
When setting the D/A converter i output voltage to reference  
voltage: 1 (D/A output enabled)  
5
6
7
8
CMiE  
1 (operation enabled)  
Wait until comparator stability time (max. 10 µs)  
ACCRi  
ACCRi  
CMiF  
Read (dummy read to initialize the interrupt flag)  
CMiOE  
CMiIE  
When using the ACOUTi output: 1 (ACOUTi output enabled)  
When using interrupts: 1 (interrupt enabled)  
CMiF  
When using interrupts: 0 (no interrupt requested: Initialization)  
When using interrupts: Select the interrupt priority level.  
When using interrupts: 0 (no interrupt requested: Initialization)  
9
CMiIC  
ILVL2 to ILVL0  
IR  
i = 0 or 1  
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19.Comparator  
Figure 19.4 shows an Operating Example of Comparator i (i = 0 or 1).  
If the analog input voltage is higher than the reference input voltage, the CMiLV bit in the ACCRi register is set  
to 1. If the analog input voltage is lower than the reference input voltage, the CMiLV bit is set to 0. When the  
comparison result changes, the CMiF bit in the ACCRi register is set to 1. If the value of the CMiIE bit in the  
ACCRi register is 1 (interrupt by CMiF bit enabled) at this time, a comparator i interrupt request is generated.  
Refer to 19.4 Comparator 0 Interrupt and Comparator 1 Interrupt for information of interrupts.  
Analog input voltage (V)  
Reference input voltage  
0
1
0
CMiLV bit in  
ACCRi register  
Set to 0 by a program  
1
0
CMiF bit in  
ACCRi register  
ACOUTi output  
(when CMiPOR bit  
in ACMR register  
is set to 0)  
1
0
ACOUTi output  
(when CMiPOR bit  
in ACMR register  
is set to 1)  
1
0
The above applies under the following conditions:  
CMiOE bit in the ACCRi register = 1 (output enabled)  
Bits FLTi1 to FLTi0 in the ACCRi register = 00b (no filter)  
CMiPOR bit in the ACMR register = 0 (non-inverted comparator i compare result output to ACOUTi)  
CMiPOR bit in the ACMR register = 1 (inverted comparator i compare result output to ACOUTi)  
i = 0 or 1  
Figure 19.4  
Operating Example of Comparator i (i = 0 or 1)  
19.3.1 Comparison Result Output  
When the CMiOE bit in the ACCRi register is set to 1 (output enabled), the comparison result can be output  
from the ACOUTi pin. Also, the CMiPOR bit in the ACMR register can be used to select whether the ACOUTi  
pin output polarity is inverted or not inverted.  
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19.Comparator  
19.3.2 Digital Filter  
The digital filter can be applied to the CMACOUTi (i = 0 or1) signal.  
The CMACOUTi signal is sampled, and the level is considered to be determined when two matches occur. The  
digital filter function and sampling frequency are selected using bits FLTi0 to FLTi1 in the ACCRi register.  
Figure 19.5 shows a Block Diagram of Digital Filter.  
FLTi1 to FLTi0  
= 01b  
f2  
= 10b  
f8  
= 11b  
f32  
Sampling clock  
C
C
FLTi1 to FLTi0  
= 01b, 10b, 11b  
C
CMACOUTi  
signal  
Match  
detect  
circuit  
D
Q
D
Q
D
Q
Latch  
Latch  
Latch  
= 00b  
Clock cycle selected by  
FLTi1 to FLTi0  
Sampling clock  
CMACOUTi  
signal  
Two matches  
occur and a  
signal change  
is confirmed.  
Input signal after passing  
through digital filter  
Maximum signal  
transmission  
delay is 2.5  
sampling clock  
pulses.  
If fewer than two matches  
occur, the matches are  
treated as noise and no  
transmission is performed.  
FLTi0 to FLTi1: Bits in ACCRi register  
i = 0 or 1  
Figure 19.5  
Block Diagram of Digital Filter  
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19.Comparator  
19.4 Comparator 0 Interrupt and Comparator 1 Interrupt  
Comparator 0 and Comparator 1 generate interrupt request from two sources. The comparator i (i = 0 or 1)  
interrupt uses the corresponding CMiIC register (bits IR and ILVL0 to ILVL2) and vector. When the  
comparison result changes, the CMiF bit in the ACCRi register is set to 1. If the value of the CMiIE bit in the  
ACCRi register is 1 (interrupt by CMiF bit enabled) at this time, a comparator i interrupt request is generated.  
Table 19.4 lists the Registers and Bits Associated with Comparator Interrupt, and Figure 19.6 is a Block  
Diagram of Comparator Interrupt.  
Table 19.4  
Registers and Bits Associated with Comparator Interrupt  
Comparator i Control Register,  
Comparator i Interrupt Flag  
CMiF bit in ACCRi register  
Comparator i Interrupt Control Register,  
Comparator i Interrupt Enable Bit  
CMiE bit in ACCRi register  
Comparator i Interrupt  
Control Register  
CMiIC  
i = 0 or 1  
CM0F bit  
Comparator 0 interrupt request  
(IR bit in CM0IC register)  
CM0IE bit  
CM1F bit  
CM1IE bit  
Comparator 1 interrupt request  
(IR bit in CM1IC register)  
CM0F, CM0IE: Bits in ACCR0 register  
CM1F, CM1IE: Bits in ACCR1 register  
Figure 19.6  
Block Diagram of Comparator Interrupt  
Like other maskable interrupts, the comparator i interrupt is controlled by the combination of the I flag, IR bit,  
bits ILVL0 to ILVL2, and IPL.  
However, the existence of the bits CMiF and CMiIE results in the following differences from other maskable  
interrupts.  
The IR bit in the CMiIC register is set to 1 (interrupt requested) when the CMiF bit in the ACCRi register  
is set to 1 and the CMiIE bit in the ACCRi register is set to 1 (interrupt enabled).  
The IR bit is set to 0 (no interrupt requested) when the CMiF bit or CMiIE bit is set to 0, or both are set to  
0. In other words, the interrupt request is not maintained if the IR bit is once set to 1 but the interrupt is not  
acknowledged.  
The CMiF bit is not automatically set to 0 when an interrupt is acknowledged. Set it to 0 within the  
interrupt routine. Refer to Figure 19.2 Registers ACCR0 to ACCR1, for the procedure for setting these  
bits to 0.  
Refer to 12.1.6 Interrupt Control, for details of the CMiIC register and 12.1.5.2 Relocatable Vector Tables,  
for information on interrupt vectors.  
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20. Flash Memory Version  
20. Flash Memory Version  
20.1 Overview  
In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite,  
standard serial I/O, and parallel I/O.  
Table 20.1 lists the Flash Memory Performance (refer to Table 1.1, Table 1.2, Table 1.3, and Table 1.4  
Specifications for items not listed in Table 20.1).  
Table 20.1  
Flash Memory Performance  
Item  
Specification  
3 modes (CPU rewrite, standard serial I/O, and parallel I/O)  
Refer to Figure 20.1 and Figure 20.2  
Byte unit  
Flash memory operating mode  
Division of erase block  
Programming method  
Erase method  
Block erase  
(3)  
Program and erase control by software command  
Programming and erasure control method  
Rewrite control method  
Rewrite control for blocks 0 and 1 by FMR02 bit in FMR0  
register  
Rewrite control for block 0 by FMR15 bit and block 1 by  
FMR16 bit in FMR1 register  
Number of commands  
5 commands  
Programming Blocks 0 and 1 (program  
and erasure ROM)  
R8C/2E Group: 100 times; R8C/2F Group: 1,000 times  
(1)  
(2)  
endurance  
10,000 times  
Blocks A and B (data flash)  
ID code check function  
Standard serial I/O mode supported  
Parallel I/O mode supported  
ROM code protect  
NOTES:  
1. Definition of programming and erasure endurance  
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure  
endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are  
performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When  
performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations  
in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular  
blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to  
retain data on the erase count of each block and limit the number of erase operations to a certain number.  
2. Blocks A and B are implemented only in the R8C/2F group.  
3. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform  
programming and erasure at less than 2.7 V.  
Table 20.2  
Flash memory  
Rewrite mode  
Function  
Flash Memory Rewrite Modes  
Standard Serial I/O  
Mode  
CPU Rewrite Mode  
Parallel I/O Mode  
User ROM area is rewritten by executing User ROM area is User ROM area is  
software commands from the CPU.  
EW0 mode: Rewritable in the RAM  
EW1 mode: Rewritable in flash memory programmer.  
rewritten by a  
dedicated serial  
rewritten by a  
dedicated parallel  
programmer.  
Areas which can User ROM area  
be rewritten  
User ROM area  
User ROM area  
Operating mode  
Single chip mode  
Boot mode  
Parallel I/O mode  
ROM Programmer None  
Serial programmer Parallel programmer  
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20. Flash Memory Version  
20.2 Memory Map  
The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 20.1 shows the Flash  
Memory Block Diagram for R8C/2E Group. Figure 20.2 shows a Flash Memory Block Diagram for R8C/2F  
Group.  
The user ROM area of the R8C/2F Group contains an area (program ROM) which stores MCU operating programs  
and blocks A and B (data flash) each 1 Kbyte in size.  
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and  
standard serial I/O and parallel I/O modes.  
When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite  
enabled). When the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the  
FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable.  
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot  
ROM area and the user ROM area share the same address, but have separate memory areas.  
16 Kbyte ROM product  
0C000h  
Block 1: 8 Kbytes(1)  
Program ROM  
8 Kbyte ROM product  
Block 0: 8 Kbytes(1)  
User ROM area  
0DFFFh  
0E000h  
0E000h  
0FFFFh  
0E000h  
0FFFFh  
Block 0: 8 Kbytes(1)  
User ROM area  
8 Kbytes  
0FFFFh  
Boot ROM area  
(reserved area)(2)  
NOTES:  
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0  
(rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for  
CPU rewrite mode).  
2. This area is for storing the boot program provided by Renesas Technology.  
Figure 20.1  
Flash Memory Block Diagram for R8C/2E Group  
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20. Flash Memory Version  
16 Kbytes ROM product  
8 Kbytes ROM product  
Block A: 1 Kbyte  
02400h  
02400h  
02BFFh  
Block A: 1 Kbyte  
Data flash  
Block B: 1 Kbyte  
02BFFh  
Block B: 1 Kbyte  
Block 0: 16 Kbytes(1)  
0C000h  
Block 1: 8 Kbytes(1)  
Program ROM  
0DFFFh  
0E000h  
0E000h  
0FFFFh  
0E000h  
0FFFFh  
Block 0: 8 Kbytes(1)  
Block 0: 8 Kbytes(1)  
User ROM area  
8 Kbytes  
0FFFFh  
User ROM area  
Boot ROM area  
(reserved area)(2)  
NOTES:  
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0  
(rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU  
rewrite mode).  
2. This area is for storing the boot program provided by Renesas Technology.  
Figure 20.2  
Flash Memory Block Diagram for R8C/2F Group  
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20. Flash Memory Version  
20.3 Functions to Prevent Rewriting of Flash Memory  
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to  
prevent the flash memory from being read or rewritten easily.  
20.3.1 ID Code Check Function  
This function is used in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the  
programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do  
not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of  
data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh,  
00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write  
them to the flash memory.  
Address  
00FFDFh to 00FFDCh  
00FFE3h to 00FFE0h  
00FFE7h to 00FFE4h  
00FFEBh to 00FFE8h  
00FFEFh to 00FFECh  
00FFF3h to 00FFF0h  
00FFF7h to 00FFF4h  
00FFFBh to 00FFF8h  
00FFFFh to 00FFFCh  
ID1  
ID2  
Undefined instruction vector  
Overflow vector  
BRK instruction vector  
Address match vector  
Single step vector  
ID3  
ID4  
ID5  
ID6  
ID7  
Oscillation stop detection/watchdog  
timer/voltage monitor 1 and voltage  
monitor 2 vector  
Address break  
(Reserved)  
(Note 1) Reset vector  
4 bytes  
NOTE:  
1. The OFS register is assigned to 00FFFFh.  
Refer to Figure 20.4 OFS Register for OFS register details.  
Figure 20.3  
Address for Stored ID Code  
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20. Flash Memory Version  
20.3.2 ROM Code Protect Function  
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the  
OFS register in parallel I/O mode. Figure 20.4 shows the OFS Register.  
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables  
reading or changing the contents of the on-chip flash memory.  
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O  
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or  
standard serial I/O mode.  
Option Function Select Register(1)  
b7 b6 b5 b4 b3 b2 b1 b0  
1 0 1  
1
Symbol  
OFS  
Address  
0FFFFh  
When Shipping  
FFh(2)  
Bit Symbol  
Bit Name  
Function  
RW  
RW  
Watchdog timer start  
select bit  
0 : Starts w atchdog timer automatically after reset  
1 : Watchdog timer is inactive after reset  
WDTON  
(b1)  
Reserved bit  
Set to 1.  
RW  
RW  
RW  
RW  
RW  
RW  
ROM code protect  
disabled bit  
0 : ROM code protect disabled  
1 : ROMCP1 enabled  
ROMCR  
ROM code protect bit  
0 : ROM code protect enabled  
1 : ROM code protect disabled  
ROMCP1  
(b4)  
Reserved bit  
Set to 1.  
(b5)  
Reserved bit  
Set to 0.  
(b6)  
Reserved bit  
Set to 1.  
Count source protect  
0 : Count source protect mode enabled after reset  
mode after reset select 1 : Count source protect mode disabled after reset  
bit  
CSPROINI  
RW  
NOTES:  
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not  
w rite additions to the OFS register.  
2. If the block including the OFS register is erased, FFh is set to the OFS register.  
Figure 20.4  
OFS Register  
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20. Flash Memory Version  
20.4 CPU Rewrite Mode  
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.  
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a  
ROM programmer. Execute the program and block erase commands only to blocks in the user ROM area.  
The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in  
CPU rewrite mode. It performs an interrupt process after the erase operation is halted temporarily. During erase-  
suspend, the user ROM area can be read by a program.  
In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash module  
contains a program-suspend function which performs the interrupt process after the auto-program operation is  
suspended. During program-suspend, the user ROM area can be read by a program.  
CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 20.3 lists  
the Differences between EW0 Mode and EW1 Mode.  
Table 20.3  
Differences between EW0 Mode and EW1 Mode  
Item EW0 Mode  
Single-chip mode  
EW1 Mode  
Single-chip mode  
Operating mode  
Areas in which a rewrite  
control program can be  
located  
User ROM area  
User ROM area  
Areas in which a rewrite  
control program can be  
executed  
Necessary to transfer to any area other  
than the flash memory (e.g., RAM) before area possible  
executing  
Executing directly in user ROM or RAM  
Areas which can be  
rewritten  
User ROM area  
None  
User ROM area  
However, blocks which contain a rewrite  
control program are excluded(1)  
Software command  
restrictions  
• Program and block erase commands  
Cannot be run on any block which  
contains a rewrite control program  
• Read status register command  
Cannot be executed  
Modes after program or  
erase  
Read status register mode  
Read status register mode  
Operating  
Read array mode  
Modes after read status  
register  
Do not execute this command  
CPU status during auto-  
write and auto-erase  
Hold state (I/O ports hold state before the  
command is executed)  
Flash memory status  
detection  
• Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07 in  
in the FMR0 register by a program  
• Execute the read status register  
command and read bits SR7, SR5, and  
SR4 in the status register.  
the FMR0 register by a program  
Conditions for transition to  
erase-suspend  
Set bits FMR40 and FMR41 in the FMR4 The FMR40 bit in the FMR4 register is set  
register to 1 by a program.  
to 1 and the interrupt request of the  
enabled maskable interrupt is generated  
Conditions for transitions to Set bits FMR40 and FMR42 in the FMR4 The FMR40 bit in the FMR4 register is set  
program-suspend  
register to 1 by a program.  
to 1 and the interrupt request of the  
enabled maskable interrupt is generated  
CPU clock  
5 MHz or below  
No restriction (on clock frequency to be  
used)  
NOTE:  
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled  
by setting the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is  
enabled by setting the FMR16 bit to 0 (rewrite enabled).  
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20. Flash Memory Version  
20.4.1 EW0 Mode  
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in  
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is  
set to 0, EW0 mode is selected.  
Use software commands to control program and erase operations. The FMR0 register or the status register can  
be used to determine when program and erase operations complete.  
During auto-erasure, set the FMR40 bit to 1 (erase-suspend enabled) and the FMR41 bit to 1 (request erase-  
suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the  
user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts).  
To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the  
FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read  
enabled) before accessing the user ROM area. The auto-program operation can be restarted by setting the  
FMR42 bit to 0 (program restarts).  
20.4.2 EW1 Mode  
The MCU is switched to EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to  
1 (CPU rewrite mode enabled).  
The FMR0 register can be used to determine when program and erase operations complete. Do not execute  
commands that use the read status register in EW1 mode.  
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the  
FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled  
status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is  
acknowledged.  
When an interrupt request is generated, the FMR41 bit is automatically set to 1 (requests erase-suspend) and the  
auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt  
process completes, the auto-erase operation restarts by setting the FMR41 bit to 0 (erasure restarts)  
To enable the program-suspend function during auto-programming, execute the program command after setting  
the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled  
status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is  
acknowledged.  
When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program-suspend) and  
the auto-program operation suspends. When the auto-program operation does not complete (FMR00 bit is 0)  
after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0  
(programming restarts).  
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20. Flash Memory Version  
Figure 20.5 shows the FMR0 Register. Figure 20.6 shows the FMR1 Register. Figure 20.7 shows the FMR4  
Register.  
20.4.2.1 FMR00 Bit  
This bit indicates the operating status of the flash memory. The bits value is 0 during programming, erasure  
(including suspend periods), or erase-suspend mode; otherwise, it is 1.  
20.4.2.2 FMR01 Bit  
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).  
20.4.2.3 FMR02 Bit  
Rewriting of blocks 0 and 1 does not accept program or block erase commands if the FMR02 bit is set to 0  
(rewrite disabled).  
Rewriting of blocks 0 and 1 are controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite  
enabled).  
20.4.2.4 FMSTP Bit  
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current  
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.  
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.  
In the following cases, set the FMSTP bit to 1:  
When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit  
not reset to 1 (ready))  
To provide lower consumption in high-speed on-chip oscillator mode and low-speed on-chip oscillator  
mode (XIN clock stops).  
Figure 20.11 shows the handling to provide lower consumption in high-speed on-chip oscillator mode and low-  
speed on-chip oscillator mode (XIN clock stops). Handle according to this flowchart. Note that when going to  
stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because  
the power for the flash memory is automatically turned off and is turned back on again after returning from stop  
or wait mode.  
20.4.2.5 FMR06 Bit  
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program  
error occurs; otherwise, it is cleared to 0. For details, refer to the description in 20.4.5 Full Status Check.  
20.4.2.6 FMR07 Bit  
This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error  
occurs; otherwise, it is set to 0. Refer to 20.4.5 Full Status Check for details.  
20.4.2.7 FMR11 Bit  
Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.  
20.4.2.8 FMR15 Bit  
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0  
accepts program and block erase commands.  
20.4.2.9 FMR16 Bit  
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1  
accepts program and block erase commands.  
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20. Flash Memory Version  
20.4.2.10 FMR40 Bit  
The suspend function is enabled by setting the FMR40 bit to 1 (enable).  
20.4.2.11 FMR41 Bit  
In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41  
bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is  
generated in EW1 mode, and then the MCU enters erase-suspend mode.  
Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts.  
20.4.2.12 FMR42 Bit  
In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The  
FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled  
interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode.  
Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts.  
20.4.2.13 FMR43 Bit  
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit  
remains set to 1 (erase execution in progress) during erase-suspend operation.  
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).  
20.4.2.14 FMR44 Bit  
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44  
bit remains set to 1 (program execution in progress) during program-suspend operation.  
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).  
20.4.2.15 FMR46 Bit  
The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution and set to 1 (reading  
enabled) in suspend mode. Do not access the flash memory while this bit is set to 0.  
20.4.2.16 FMR47 Bit  
Power consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in  
low-speed on-chip oscillator mode (XIN clock stops).  
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20. Flash Memory Version  
Flash Memory Control Register 0  
b7 b6 b5 b4 b3 b2 b1 b0  
0 0  
Symbol  
Address  
01B7h  
After Reset  
00000001b  
Function  
FMR0  
Bit Symbol  
Bit Name  
RW  
RO  
___  
0 : Busy (w riting or erasing in progress)  
1 : Ready  
RY/BY status flag  
FMR00  
FMR01  
FMR02  
CPU rew rite mode select bit(1)  
Blocks 0, 1 rew rite enable bit(2, 6)  
Flash memory stop bit(3, 5)  
0 : CPU rew rite mode disabled  
1 : CPU rew rite mode enabled  
RW  
RW  
0 : Disables rew rite  
1 : Enables rew rite  
0 : Enables flash memory operation  
1 : Stops flash memory  
FMSTP  
RW  
(enters low -pow er consumption state  
and flash memory is reset)  
(b5-b4)  
Reserved bits  
Set to 0.  
RW  
RO  
RO  
Program status flag(4)  
Erase status flag(4)  
0 : Completed successfully  
1 : Terminated by error  
FMR06  
FMR07  
0 : Completed successfully  
1 : Terminated by error  
NOTES:  
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit  
to 0 and setting it to 1. Enter read array mode and set this bit to 0.  
2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1.  
Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.  
3. Set this bit by a program transferred to the RAM.  
4. This bit is set to 0 by executing the clear status command.  
5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0,  
w riting 1 to the FMSTPbit causes the FMSTPbit to be set to 1. The flash memory does not enter low -pow er  
consumption state nor is it reset.  
6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).  
Figure 20.5  
FMR0 Register  
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20. Flash Memory Version  
Flash Memory Control Register 1  
b7 b6 b5 b4 b3 b2 b1 b0  
1
0 0 0  
Symbol  
FMR1  
Bit Symbol  
Address  
01B5h  
After Reset  
1000000Xb  
Function  
Bit Name  
RW  
RO  
(b0)  
Reserved bit  
When read, the content is undefined.  
EW1 mode select bit(1, 2)  
Reserved bits  
0 : EW0 mode  
1 : EW1 mode  
FMR11  
RW  
RW  
RW  
RW  
RW  
(b4-b2)  
Set to 0.  
Block 0 rew rite disable bit(2,3)  
Block 1 rew rite disable bit(2,3)  
Reserved bit  
0 : Enables rew rite  
1 : Disables rew rite  
FMR15  
FMR16  
0 : Enables rew rite  
1 : Disables rew rite  
(b7)  
Set to 1.  
NOTES:  
1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode  
enable) . Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.  
2. This bit is set to 0 by setting the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled).  
3. When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.  
To set this bit to 0, set it to 0 immediately after setting it first to 1.  
To set this bit to 1, set it to 1.  
Figure 20.6  
FMR1 Register  
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20. Flash Memory Version  
Flash Memory Control Register 4  
b7 b6 b5 b4 b3 b2 b1 b0  
0
Symbol  
Address  
01B3h  
After Reset  
01000000b  
Function  
FMR4  
Bit Symbol  
Bit Name  
RW  
RW  
Erase-suspend function  
enable bit(1)  
Erase-suspend request bit(2)  
0 : Disable  
1 : Enable  
FMR40  
FMR41  
FMR42  
FMR43  
FMR44  
0 : Erase restart  
RW  
RW  
RO  
RO  
1 : Erase-suspend request  
Program-suspend request bit(3) 0 : Program restart  
1 : Program-suspend request  
0 : Erase not executed  
Erase command flag  
Program command flag  
Reserved bit  
1 : Erase execution in progress  
0 : Program not executed  
1 : Program execution in progress  
Set to 0.  
(b5)  
RO  
RO  
RW  
Read status flag  
0 : Disables reading  
1 : Enables reading  
FMR46  
FMR47  
Low -pow er consumption read 0 : Disable  
mode enable bit (1, 4, 5)  
1 : Enable  
NOTES:  
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit  
to 0 and setting it to 1.  
2. This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing  
an erase command and completing the erase. (This bit is set to 0 during periods other than the above.)  
In EW0 mode, it can be set to 0 or 1 by a program.  
In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase  
operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten).  
3. The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled  
until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the  
above.)  
In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.  
In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming  
w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program.  
4. In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).  
5. Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er consumption read mode.  
Figure 20.7  
FMR4 Register  
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20. Flash Memory Version  
Figure 20.8 shows the Timing of Suspend Operation.  
Erasure  
starts  
Erasure  
suspends  
Programming Programming Programming Programming Erasure  
Erasure  
ends  
starts  
suspends  
restarts  
ends  
restarts  
During programming  
During programming  
During erasure  
During erasure  
1
0
FMR00 bit in  
FMR0 register  
Remains 0 during suspend  
1
0
FMR46 bit in  
FMR4 register  
1
0
FMR44 bit in  
FMR4 register  
1
0
FMR43 bit in  
FMR4 register  
Remains 1 during suspend  
Check that the  
FMR43 bit is set to 1  
(during erase  
execution), and that  
the erase-operation  
has not ended.  
Check that the  
Check the status,  
and that the  
programming ends  
normally.  
Check the status,  
and that the  
erasure ends  
normally.  
FMR44 bit is set to 1  
(during program  
execution), and that  
the program has not  
ended.  
The above figure shows an example of the use of program-suspend during programming following erase-suspend.  
NOTE:  
1. If program-suspend is entered during erase-suspend, always restart programming.  
Figure 20.8  
Timing of Suspend Operation  
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20. Flash Memory Version  
Figure 20.9 shows How to Set and Exit EW0 Mode. Figure 20.10 shows How to Set and Exit EW1 Mode.  
EW0 Mode Operating Procedure  
Rewrite control program  
Write 0 to the FMR01 bit before writing 1  
(CPU rewrite mode enabled)(2)  
Set registers(1) CM0 and CM1  
Execute software commands  
Transfer a rewrite control program which uses CPU  
rewrite mode to the RAM.  
Execute the read array command(3)  
Write 0 to the FMR01 bit  
Jump to the rewrite control program which has been  
transferred to the RAM.  
(CPU rewrite mode disabled)  
(The subsequent process is executed by the rewrite  
control program in the RAM.)  
Jump to a specified address in the flash memory  
NOTES:  
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.  
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.  
Write to the FMR01 bit in the RAM.  
3. Disable the CPU rewrite mode after executing the read array command.  
Figure 20.9  
How to Set and Exit EW0 Mode  
EW1 Mode Operating Procedure  
Program in ROM  
Write 0 to the FMR01 bit before writing 1 (CPU  
rewrite mode enabled)(1)  
Write 0 to the FMR11 bit before writing 1 (EW1  
mode)  
Execute software commands  
Write 0 to the FMR01 bit  
(CPU rewrite mode disabled)  
NOTE:  
1. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1.  
Do not generate an interrupt between writing 0 and 1.  
Figure 20.10 How to Set and Exit EW1 Mode  
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20. Flash Memory Version  
High-speed on-chip oscillator mode  
and low-speed on-chip oscillator  
mode (XIN clock stops) program  
Transfer a high-speed on-chip oscillator mode and  
low-speed on-chip oscillator mode (XIN clock stops)  
program to the RAM.  
Write 0 to the FMR01 bit before writing 1  
(CPU rewrite mode enabled)  
Jump to the high-speed on-chip oscillator mode and  
low-speed on-chip oscillator mode (XIN clock stops)  
program which has been transferred to the RAM.  
(The subsequent processing is executed by the  
program in the RAM.)  
Write 1 to the FMSTP bit (flash memory stops.  
Low power consumption mode)(1)  
Switch the clock source for the CPU clock.  
Turn XIN off  
Process in high-speed on-chip oscillator  
mode and low-speed on-chip oscillator  
mode (XIN clock stops)  
Turn XIN clock on wait until oscillation  
stabilizes switch the clock source for CPU  
clock(2)  
Write 0 to the FMSTP bit  
(flash memory operation)  
Write 0 to the FMR01 bit  
(CPU rewrite mode disabled)  
NOTES:  
1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the  
FMSTP bit to 1.  
Wait until the flash memory circuit stabilizes  
(30 µs)(3)  
2. Before switching to a different clock source for the CPU, make sure  
the designated clock is stable.  
3. Insert a 30 µs wait time in a program. Do not access to the flash  
memory during this wait time.  
Jump to a specified address in the flash memory  
Figure 20.11 Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode and  
Low-Speed On-Chip Oscillator Mode (XIN Clock Stops)  
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20. Flash Memory Version  
20.4.3 Software Commands  
The software commands are described below. Read or write commands and data in 8-bit units.  
Table 20.4 Software Commands  
Command  
First Bus Cycle  
Address  
Second Bus Cycle  
Mode Address  
Data  
(D7 to D0)  
FFh  
Data  
(D7 to D0)  
Mode  
Read array  
Write  
×
Read status register  
Clear status register  
Program  
Write  
Write  
Write  
Write  
×
70h  
Read  
×
SRD  
×
50h  
WA  
×
40h  
Write  
Write  
WA  
BA  
WD  
Block erase  
20h  
D0h  
SRD: Status register data (D7 to D0)  
WA: Write address (Ensure the address specified in the first bus cycle is the same address as the write  
address specified in the second bus cycle.)  
WD: Write data (8 bits)  
BA: Given block address  
×: Any specified address in the user ROM area  
20.4.3.1 Read Array Command  
The read array command reads the flash memory.  
The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in  
the following bus cycles, the content of the specified address can be read in 8-bit units.  
Since the MCU remains in read array mode until another command is written, the contents of multiple  
addresses can be read continuously.  
In addition, the MCU enters read array mode after a reset.  
20.4.3.2 Read Status Register Command  
The read status register command is used to read the status register.  
When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 20.4.4  
Status Registers). When reading the status register, specify an address in the user ROM area.  
Do not execute this command in EW1 mode.  
The MCU remains in read status register mode until the next read array command is written.  
20.4.3.3 Clear Status Register Command  
The clear status register command sets the status register to 0.  
When 50h is written in the first bus cycle, bits FMR06 to FMR07 in the FMR0 register and SR4 to SR5 in the  
status register are set to 0.  
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20. Flash Memory Version  
20.4.3.4 Program Command  
The program command writes data to the flash memory in 1-byte units.  
By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program  
operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the  
same address as the write address specified in the second bus cycle.  
The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed.  
When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when auto-  
programming completes.  
When suspend function enabled, the FMR44 bit is set to 1 during auto-programming and set to 0 when auto-  
programming completes.  
The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been  
finished (refer to 20.4.5 Full Status Check).  
Do not write additions to the already programmed addresses.  
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), or the FMR02 bit is set to 1 (rewrite  
enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), program commands targeting  
block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), program commands  
targeting block 1 are not acknowledged.  
Figure 20.12 shows Program Command (When Suspend Function Disabled). Figure 20.13 shows Program  
Command (When Suspend Function Enabled).  
In EW1 mode, do not execute this command for any address which a rewrite control program is allocated.  
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the  
status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts  
and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register  
mode until the next read array command is written. The status register can be read to determine the result of  
auto-programming after auto-programming has completed.  
Start  
Write the command code 40h to  
the write address  
Write data to the write address  
No  
FMR00 = 1?  
Yes  
Full status check  
Program completed  
Figure 20.12 Program Command (When Suspend Function Disabled)  
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20. Flash Memory Version  
EW0 Mode  
Start  
Maskable interrupt(1)  
FMR44 = 1 ?  
I = 1 (enable interrupt)(3)  
FMR40 = 1  
No  
Yes  
FMR42 = 1(4)  
Write the command code 40h  
to the write address  
No  
Access flash memory  
FMR46 = 1 ?  
Write data to the write address  
FMR44 = 0 ?  
Yes  
Access flash memory  
No  
FMR42 = 0  
REIT  
Yes  
Full status check  
Program completed  
Start  
Maskable interrupt (2)  
Access flash memory  
REIT  
EW1 Mode  
I = 1 (enable interrupt)  
FMR40 = 1  
Write the command code 40h  
Write data to the write address  
FMR42 = 0  
No  
FMR44 = 0 ?  
Yes  
Full status check  
Program completed  
NOTES:  
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.  
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend  
should be in interrupt enabled status.  
3. When no interrupt is used, the instruction to enable interrupts is not needed.  
4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1.  
Figure 20.13 Program Command (When Suspend Function Enabled)  
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20. Flash Memory Version  
20.4.3.5 Block Erase  
When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus  
cycle, an auto-erase operation (erase and verify) of the specified block starts.  
The FMR00 bit in the FMR0 register can determine whether auto-erasure has completed.  
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.  
The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has  
completed (refer to 20.4.5 Full Status Check).  
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled) or the FMR02 bit is set to 1 (rewriting  
enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), the block erase commands  
targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), block erase  
commands targeting block 1 are not acknowledged.  
Do not use the block erase command during program-suspend.  
Figure 20.14 shows the Block Erase Command (When Erase-Suspend Function Disabled). Figure 20.15 shows  
the Block Erase Command (When Erase-Suspend Function Enabled).  
In EW1 mode, do not execute this command for any address to which a rewrite control program is allocated.  
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status  
register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to  
1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read  
array command is written.  
Start  
Write the command code 20h  
Write D0h to a given block  
address  
No  
FMR00 = 1?  
Yes  
Full status check  
Block erase completed  
Figure 20.14 Block Erase Command (When Erase-Suspend Function Disabled)  
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20. Flash Memory Version  
EW0 Mode  
Start  
Maskable interrupt(1)  
FMR43 = 1 ?  
I = 1 (enable interrupt)(3)  
FMR40 = 1  
No  
Yes  
FMR41 = 1(4)  
Write the command code 20h  
No  
Access flash memory  
FMR46 = 1 ?  
Write D0h to any block  
address  
Yes  
Access flash memory  
No  
FMR00 = 1 ?  
FMR41 = 0  
REIT  
Yes  
Full status check  
Block erase completed  
Maskable interrupt(2)  
Access flash memory  
REIT  
EW1 Mode  
Start  
I = 1 (enable interrupt)  
FMR40 = 1  
Write the command code 20h  
Write D0h to any block  
address  
FMR41 = 0  
No  
FMR00 = 1 ?  
Yes  
Full status check  
Block erase completed  
NOTES:  
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.  
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend  
should be in interrupt enabled status.  
3. When no interrupt is used, the instruction to enable interrupts is not needed.  
4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1.  
Figure 20.15 Block Erase Command (When Erase-Suspend Function Enabled)  
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20. Flash Memory Version  
20.4.4 Status Registers  
The status register indicates the operating status of the flash memory and whether an erase or program operation  
has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and  
FMR07 in the FMR0 register.  
Table 20.5 lists the Status Register Bits.  
In EW0 mode, the status register can be read in the following cases:  
When a given address in the user ROM area is read after writing the read status register command  
When a given address in the user ROM area is read after executing the program or block erase command  
but before executing the read array command.  
20.4.4.1 Sequencer Status (SR7 and FMR00 Bits)  
The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during auto-  
programming and auto-erasure, and is set to 1 (ready) at the same time the operation completes.  
20.4.4.2 Erase Status (SR5 and FMR07 Bits)  
Refer to 20.4.5 Full Status Check.  
20.4.4.3 Program Status (SR4 and FMR06 Bits)  
Refer to 20.4.5 Full Status Check.  
Table 20.5  
Status Register Bits  
Description  
StatusRegister FMR0 Register  
Value after  
Reset  
Status Name  
Bit  
SR0 (D0)  
SR1 (D1)  
SR2 (D2)  
SR3 (D3)  
SR4 (D4)  
SR5 (D5)  
SR6 (D6)  
SR7 (D7)  
Bit  
0
1
Reserved  
Reserved  
Reserved  
Reserved  
0
0
1
FMR06  
FMR07  
Program status Completed normally Error  
Erase status  
Reserved  
Sequencer  
status  
Completed normally Error  
FMR00  
Busy  
Ready  
D0 to D7:Indicate the data bus which is read when the read status register command is executed.  
Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.  
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot  
be accepted.  
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20. Flash Memory Version  
20.4.5 Full Status Check  
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an  
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.  
Table 20.6 lists the Errors and FMR0 Register Status. Figure 20.16 shows the Full Status Check and Handling  
Procedure for Individual Errors.  
Table 20.6  
Errors and FMR0 Register Status  
FRM0 Register (Status  
Register) Status  
Error  
Error Occurrence Condition  
FMR07(SR5) FMR06(SR4)  
1
1
Command  
sequence  
error  
• When a command is not written correctly  
• When invalid data other than that which can be written  
in the second bus cycle of the block erase command is  
written (i.e., other than D0h or FFh)(1)  
• When the program command or block erase command  
is executed while rewriting is disabled by the FMR02 bit  
in the FMR0 register, or the FMR15 or FMR16 bit in the  
FMR1 register.  
• When an address not allocated in flash memory is input  
during erase command input  
• When attempting to erase the block for which rewriting  
is disabled during erase command input.  
• When an address not allocated in flash memory is input  
during write command input.  
• When attempting to write to a block for which rewriting  
is disabled during the write command input.  
1
0
0
1
Erase error  
• When the block erase command is executed but auto-  
erasure does not complete correctly  
Program error • When the program command is executed but not auto-  
programming does not complete.  
NOTE:  
1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.  
At the same time, the command code written in the first bus cycle is disabled.  
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20. Flash Memory Version  
Command sequence error  
Full status check  
Execute the clear status register command  
(set these status flags to 0)  
FMR06 = 1  
Yes  
and  
Command sequence error  
FMR07 = 1?  
Check if command is properly input  
Re-execute the command  
No  
Yes  
Erase error  
FMR07 = 1?  
Erase error  
No  
Execute the clear status register command  
(set these status flags to 0)  
Erase command  
re-execution times 3 times?  
No  
Block targeting for erasure  
cannot be used  
Yes  
Yes  
FMR06 = 1?  
Program error  
Re-execute block erase command  
No  
Program error  
Execute the clear status register  
command  
(set these status flags to 0)  
Full status check completed  
Specify the other address besides the  
write address where the error occurs for  
the program address(1)  
NOTE:  
1. To rewrite to the address where the program error occurs, check if the full  
status check is complete normally and write to the address after the block  
erase command is executed.  
Re-execute program command  
Figure 20.16 Full Status Check and Handling Procedure for Individual Errors  
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20. Flash Memory Version  
20.5 Standard Serial I/O Mode  
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a  
serial programmer which is suitable for the MCU.  
There are three types of Standard serial I/O modes:  
Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer  
Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer  
Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial  
programmer  
This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3.  
Refer to Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator.  
Contact the manufacturer of your serial programmer for details. Refer to the user’s manual of your serial  
programmer for instructions on how to use it.  
Table 20.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 20.8 lists the Pin Functions  
(Flash Memory Standard Serial I/O Mode 3). Figure 20.17 shows Pin Connections for Standard Serial I/O Mode 3.  
After processing the pins shown in Table 20.8 and rewriting the flash memory using the programmer, apply “H” to  
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.  
20.5.1 ID Code Check Function  
The ID code check function determines whether the ID codes sent from the serial programmer and those written  
in the flash memory match (refer to 20.3 Functions to Prevent Rewriting of Flash Memory).  
Table 20.7  
Pin  
Pin Functions (Flash Memory Standard Serial I/O Mode 2)  
Name  
Power input  
I/O  
Description  
VCC,VSS  
Apply the voltage guaranteed for programming and  
erasure to the VCC pin and 0 V to the VSS pin.  
Reset input pin.  
Reset input  
I
I
RESET  
P4_6/XIN  
P4_6 input/clock input  
Connect a ceramic resonator or crystal oscillator  
between the XIN and XOUT pins.  
P4_7/XOUT  
P0_0 to P0_7  
P1_0 to P1_7  
P4_7 input/clock output I/O  
Input port P0  
Input port P1  
I
I
I
Input “H” or “L” level signal or leave the pin open.  
P3_0, P3_1, P3_3 to Input port P3  
P3_6  
P4_2/VREF  
P5_3, P5_4  
MODE  
Input port P4  
Input port P5  
MODE  
I
I
I/O Input “L”.  
P3_7  
TXD output  
RXD input  
O
I
Serial data output pin.  
Serial data input pin.  
P4_5  
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20. Flash Memory Version  
Table 20.8  
Pin  
Pin Functions (Flash Memory Standard Serial I/O Mode 3)  
Name I/O Description  
Power input  
VCC,VSS  
Apply the voltage guaranteed for programming and  
erasure to the VCC pin and 0 V to the VSS pin.  
Reset input pin.  
Reset input  
I
RESET  
P4_6/XIN  
P4_6 input/clock input  
I
Connect a ceramic resonator or crystal oscillator  
between the XIN and XOUT pins when connecting  
external oscillator. Apply “H” and “L” or leave the pin  
open when using as input port.  
P4_7/XOUT  
P4_7 input/clock output I/O  
P0_0 to P0_7  
P1_0 to P1_7  
Input port P0  
Input port P1  
I
I
I
Input “H” or “L” level signal or leave the pin open.  
P3_0, P3_1, P3_3 to Input port P3  
P3_7  
P4_2/VREF, P4_5  
P5_3, P5_4  
MODE  
Input port P4  
Input port P5  
MODE  
I
I
I/O Serial data I/O pin. Connect to the flash  
programmer.  
24 23 22 21 20 19 18 17  
16  
15  
14  
13  
12  
11  
10  
9
25  
26  
27  
28  
29  
30  
31  
32  
R8C/2E Group, R8C/2F Group  
1
2
3
4
5
6
7
8
MODE  
VSS  
VCC  
Connect oscillator circuit(1)  
Value  
Mode setting  
Signal  
Package: PLQP0032GB-A  
Voltage from programmer  
MODE  
NOTE:  
VSS VCC  
RESET  
1. It is not necessary to connect an oscillating circuit  
when operating with the on-chip oscillator clock.  
Figure 20.17 Pin Connections for Standard Serial I/O Mode 3  
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20. Flash Memory Version  
20.5.1.1 Example of Circuit Application in the Standard Serial I/O Mode  
Figure 20.18 shows an example of Pin Processing in Standard Serial I/O Mode 2, Figure 20.19 shows an  
example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the  
programmer, refer to the manual of your serial programmer for details.  
MCU  
Data Output  
Data Input  
TXD  
RXD  
MODE  
NOTES:  
1. In this example, modes are switched between single-chip mode and  
standard serial I/O mode by controlling the MODE input with a switch.  
2. Connecting the oscillation is necessary. Set the main clock frequency 1  
MHz to 20 MHz. Refer to Appendix Figure 2.1 Connecting examples  
with M16C Flash Starter (M3A-0806).  
Figure 20.18 Pin Processing in Standard Serial I/O Mode 2  
MCU  
MODE  
MODE I/O  
Reset input  
RESET  
User reset signal  
NOTES:  
1. Controlled pins and external circuits vary depending on the programmer.  
Refer to the programmer manual for details.  
2. In this example, modes are switched between single-chip mode and  
standard serial I/O mode by connecting a programmer.  
3. When operating with the on-chip oscillator clock, it is not necessary to  
connect an oscillating circuit.  
Figure 20.19 Pin Processing in Standard Serial I/O Mode 3  
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20. Flash Memory Version  
20.6 Parallel I/O Mode  
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,  
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the  
manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel  
programmer for details on how to use it.  
ROM areas shown in Figures 20.1 and 20.2 can be rewritten in parallel I/O mode.  
20.6.1 ROM Code Protect Function  
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to the 20.3  
Functions to Prevent Rewriting of Flash Memory.)  
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20. Flash Memory Version  
20.7 Notes on Flash Memory Version  
20.7.1 CPU Rewrite Mode  
20.7.1.1 Operating Speed  
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit  
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.  
20.7.1.2 Prohibited Instructions  
The following instructions cannot be used in EW0 mode because they reference internal data in flash memory:  
UND, INTO, and BRK.  
20.7.1.3 Interrupts  
Table 20.9 lists the EW0 Mode Interrupts and Table 20.10 lists the EW1 Mode Interrupt.  
Table 20.9  
EW0 Mode Interrupts  
When Maskable  
When Watchdog Timer, Oscillation Stop  
Detection, Voltage Monitor 1, or Voltage Monitor  
2 Interrupt Request is Acknowledged  
Mode  
Status  
Interrupt Request is  
Acknowledged  
EW0 During auto-erasure Any interrupt can be used Once an interrupt request is acknowledged, the  
by allocating a vector in auto-programming or auto-erasure is forcibly  
RAM  
stopped immediately and the flash memory is  
reset. Interrupt handling starts after the fixed  
period and the flash memory restarts. Since the  
block during auto-erasure or the address during  
auto-programming is forcibly stopped, the  
normal value may not be read. Execute auto-  
erasure again and ensure it completes normally.  
Since the watchdog timer does not stop during  
the command operation, interrupt requests may  
be generated. Reset the watchdog timer  
regularly.  
Auto-programming  
NOTES:  
1. Do not use the address match interrupt while a command is being executed because the vector of  
the address match interrupt is allocated in ROM.  
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed  
vector is allocated in block 0.  
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20. Flash Memory Version  
Table 20.10 EW1 Mode Interrupt  
When Watchdog Timer, Oscillation Stop  
Detection, Voltage Monitor 1, or Voltage  
Monitor 2 Interrupt Request is  
Acknowledged  
When Maskable Interrupt  
Request is Acknowledged  
Mode  
Status  
EW1 During auto-erasure Auto-erasure is suspended after Once an interrupt request is  
(erase-suspend  
function enabled)  
td(SR-SUS) and interrupt  
handling is executed. Auto-  
erasure can be restarted by  
setting the FMR41 bit in the  
acknowledged, auto-programming or  
auto-erasure is forcibly stopped  
immediately and the flash memory is  
reset. Interrupt handling starts after the  
FMR4 register to 0 (erase restart) fixed period and the flash memory  
after interrupt handling  
completes.  
restarts. Since the block during auto-  
erasure or the address during auto-  
programming is forcibly stopped, the  
normal value may not be read. Execute  
auto-erasure again and ensure it  
completes normally.  
Since the watchdog timer does not stop  
during the command operation,  
interrupt requests may be generated.  
Reset the watchdog timer regularly  
using the erase-suspend function.  
During auto-erasure Auto-erasure has priority and the  
(erase-suspend  
function disabled)  
interrupt request  
acknowledgement is put on  
standby. Interrupt handling is  
executed after auto-erasure  
completes.  
During auto-  
programming  
(program suspend  
function enabled)  
Auto-programming is suspended  
after td(SR-SUS) and interrupt  
handling is executed.  
Auto-programming can be  
restarted by setting the FMR42 bit  
in the FMR4 register to 0  
(program restart) after interrupt  
handling completes.  
During auto-  
programming  
(program suspend  
function disabled)  
Auto-programming has priority  
and the interrupt request  
acknowledgement is put on  
standby. Interrupt handling is  
executed after auto-programming  
completes.  
NOTES:  
1. Do not use the address match interrupt while a command is executing because the vector of the  
address match interrupt is allocated in ROM.  
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed  
vector is allocated in block 0.  
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20. Flash Memory Version  
20.7.1.4 How to Access  
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt  
between writing 0 and 1.  
20.7.1.5 Rewriting User ROM Area  
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is  
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be  
rewritten correctly. In this case, use standard serial I/O mode.  
20.7.1.6 Program  
Do not write additions to the already programmed address.  
20.7.1.7 Entering Stop Mode or Wait Mode  
Do not enter stop mode or wait mode during erase-suspend.  
20.7.1.8 Program and Erase Voltage for Flash Memory  
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform  
programming and erasure at less than 2.7 V.  
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21. Electrical Characteristics  
21. Electrical Characteristics  
Table 21.1  
Absolute Maximum Ratings  
Symbol  
Parameter  
Supply voltage  
Condition  
Rated Value  
Unit  
V
VCC/AVCC  
0.3 to 6.5  
0.3 to VCC + 0.3  
0.3 to VCC + 0.3  
500  
VI  
Input voltage  
V
VO  
Pd  
Output voltage  
V
Power dissipation  
Topr = 25°C  
mW  
°C  
Topr  
Operating ambient temperature  
20 to 85 (N version) /  
40 to 85 (D version)  
Tstg  
Storage temperature  
65 to 150  
°C  
Table 21.2  
Recommended Operating Conditions  
Standard  
Symbol  
Parameter  
Conditions  
Unit  
Min.  
Typ.  
Max.  
5.5  
VCC/AVCC Supply voltage  
2.7  
V
V
VSS/AVSS  
VIH  
Supply voltage  
Input “H” voltage  
Input “L” voltage  
0
0.8 VCC  
VCC  
V
VIL  
0
0.2 VCC  
160  
V
IOH(sum)  
Peak sum output Sum of all pins IOH(peak)  
“H” current  
mA  
IOH(sum)  
IOH(peak)  
Average sum  
output “H” current  
Sum of all pins IOH(avg)  
80  
mA  
Peak output “H”  
current  
Except P1_0 to P1_7  
P1_0 to P1_7  
10  
20  
5  
mA  
mA  
mA  
mA  
mA  
IOH(avg)  
Average output  
“H” current  
Except P1_0 to P1_7  
P1_0 to P1_7  
10  
160  
IOL(sum)  
IOL(sum)  
IOL(peak)  
Peak sum output Sum of all pins IOL(peak)  
“L” currents  
Average sum  
output “L” currents  
Sum of all pins IOL(avg)  
80  
mA  
Peak output “L”  
currents  
Except P1_0 to P1_7  
P1_0 to P1_7  
0
0
0
0
10  
20  
5
mA  
mA  
IOL(avg)  
f(XIN)  
Average output  
“L” current  
Except P1_0 to P1_7  
P1_0 to P1_7  
mA  
10  
20  
10  
20  
10  
mA  
XIN clock input oscillation frequency  
3.0 V VCC 5.5 V  
2.7 V VCC < 3.0 V  
3.0 V VCC 5.5 V  
2.7 V VCC < 3.0 V  
MHz  
MHz  
MHz  
MHz  
kHz  
System clock  
OCD2 = 0  
XlN clock selected  
OCD2 = 1  
FRA01 = 0  
125  
Low-speed on-chip  
oscillator clock selected  
On-chip oscillator clock  
selected  
FRA01 = 1  
20  
10  
MHz  
MHz  
High-speed on-chip  
oscillator clock selected  
3.0 V VCC 5.5 V  
FRA01 = 1  
High-speed on-chip  
oscillator clock selected  
2.7 V VCC 5.5 V  
NOTES:  
1. VCC = 2.7 to 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. The average output current indicates the average value of current measured during 100 ms.  
Rev.1.00 Dec 14, 2007 Page 294 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
P0  
P1  
P3  
P4  
P5  
30pF  
Figure 21.1  
Ports P0, P1, and P3 to P5 Timing Measurement Circuit  
Table 21.3  
A/D Converter Characteristics  
Standard  
Unit  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
10  
Resolution  
Vref = AVCC  
Bits  
LSB  
LSB  
LSB  
LSB  
k  
Absolute  
accuracy  
10-bit mode  
8-bit mode  
10-bit mode  
8-bit mode  
φAD = 10 MHz, Vref = AVCC = 5.0 V  
φAD = 10 MHz, Vref = AVCC = 5.0 V  
φAD = 10 MHz, Vref = AVCC = 3.3 V  
φAD = 10 MHz, Vref = AVCC = 3.3 V  
Vref = AVCC  
±3  
±2  
±5  
±2  
Rladder  
tconv  
Resistor ladder  
10  
3.3  
2.8  
2.7  
0
40  
Conversion time 10-bit mode  
8-bit mode  
φAD = 10 MHz, Vref = AVCC = 5.0 V  
φAD = 10 MHz, Vref = AVCC = 5.0 V  
µs  
µs  
Vref  
VIA  
Reference voltage  
AVCC  
AVCC  
10  
V
Analog input voltage(2)  
V
A/D operating  
clock frequency  
Without sample and hold Vref = AVCC = 2.7 to 5.5 V  
0.25  
1
MHz  
MHz  
With sample and hold  
Vref = AVCC = 2.7 to 5.5 V  
10  
NOTES:  
1. AVCC = 2.7 to 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in  
8-bit mode.  
Table 21.4  
D/A Converter Characteristics  
Standard  
Symbol  
Parameter  
Conditions  
Unit  
Min.  
Typ.  
Max.  
8
Resolution  
Bit  
%
Absolute accuracy  
Setup time  
1.0  
3
tsu  
µs  
RO  
Output resistor  
4
10  
20  
1.5  
kΩ  
mA  
IVref  
Reference power input current  
(NOTE 2)  
NOTES:  
1. AVCC = 2.7 to 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.  
The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF  
not connected), IVref flows into the D/A converters.  
Rev.1.00 Dec 14, 2007 Page 295 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
(1)  
Table 21.5  
Comparator Characteristics  
Standard  
Unit  
Symbol  
Parameter  
Conditions  
Min.  
0
Typ.  
Max.  
VCC1.2  
VCC+0.3  
±100  
Vcref  
Vcin  
Vofs  
Tcrsp  
Comparator reference voltage  
Comparator input voltage  
Input offset voltage  
V
V
0.3  
mV  
ns  
Response time  
200  
NOTE:  
1. VCC = 2.7 to 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
Table 21.6  
Flash Memory (Program ROM) Electrical Characteristics  
Standard  
Symbol  
Parameter  
Conditions  
R8C/2E Group  
Unit  
Min.  
Typ.  
Max.  
Program/erase endurance(2)  
100(3)  
times  
times  
µs  
1,000(3)  
R8C/2F Group  
Byte program time  
Block erase time  
50  
0.4  
400  
9
s
td(SR-SUS)  
Time delay from suspend request until  
suspend  
97+CPUclock  
× 6 cycles  
µs  
Interval from erase start/restart until  
following suspend request  
650  
0
µs  
ns  
µs  
Interval from program start/restart until  
following suspend request  
Time from suspend until program/erase  
restart  
3+CPU clock  
× 4 cycles  
Program, erase voltage  
Read voltage  
2.7  
2.7  
0
5.5  
5.5  
60  
V
V
Program, erase temperature  
Data hold time(7)  
°C  
Ambient temperature = 55°C  
20  
year  
NOTES:  
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.  
2. Definition of programming/erasure endurance  
The programming and erasure endurance is defined on a per-block basis.  
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024  
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance  
still stands at one.  
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).  
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).  
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential  
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,  
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups  
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the  
number of erase operations to a certain number.  
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase  
command at least three times until the erase error does not occur.  
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.  
7. The data hold time includes time that the power supply is off or the clock is not supplied.  
Rev.1.00 Dec 14, 2007 Page 296 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Table 21.7  
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)  
Standard  
Unit  
Symbol  
Parameter  
Conditions  
Min.  
10,000(3)  
Typ.  
Max.  
Program/erase endurance(2)  
times  
Byte program time  
50  
400  
µs  
(program/erase endurance 1,000 times)  
Byte program time  
(program/erase endurance > 1,000 times)  
65  
0.2  
0.3  
9
µs  
s
Block erase time  
(program/erase endurance 1,000 times)  
Block erase time  
(program/erase endurance > 1,000 times)  
s
td(SR-SUS)  
Time delay from suspend request until  
suspend  
97+CPUclock  
× 6 cycles  
µs  
µs  
ns  
µs  
Interval from erase start/restart until  
following suspend request  
650  
0
Interval from program start/restart until  
following suspend request  
Time from suspend until program/erase  
restart  
3+CPU clock  
× 4 cycles  
Program, erase voltage  
Read voltage  
2.7  
2.7  
20(8)  
20  
5.5  
5.5  
85  
V
V
Program, erase temperature  
°C  
Data hold time(9)  
Ambient temperature = 55 °C  
year  
NOTES:  
1. VCC = 2.7 to 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. Definition of programming/erasure endurance  
The programming and erasure endurance is defined on a per-block basis.  
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024  
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance  
still stands at one.  
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).  
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).  
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times  
is the same as that in program ROM.  
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential  
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,  
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups  
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the  
number of erase operations to a certain number.  
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase  
command at least three times until the erase error does not occur.  
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.  
8. 40°C for D version.  
9. The data hold time includes time that the power supply is off or the clock is not supplied.  
Rev.1.00 Dec 14, 2007 Page 297 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Suspend request  
(maskable interrupt request)  
FMR46  
Clock-dependent  
time  
Fixed time  
Access restart  
td(SR-SUS)  
Figure 21.2  
Time delay until Suspend  
Table 21.8  
Voltage Detection 1 Circuit Electrical Characteristics  
Standard  
Symbol  
Parameter  
Voltage detection level(4)  
Voltage monitor 1 interrupt request generation time(2)  
Voltage detection circuit self power consumption  
Waiting time until voltage detection circuit operation  
starts(3)  
Condition  
Unit  
Min.  
Typ.  
2.85  
40  
Max.  
3.00  
Vdet1  
2.7  
V
µs  
µA  
µs  
VCA26 = 1, VCC = 5.0 V  
0.6  
td(E-A)  
100  
Vccmin  
MCU operating voltage minimum value  
2.7  
V
NOTES:  
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = 20 to 85°C (N version) / 40 to 85°C (D version).  
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.  
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2  
register to 0.  
4. This parameter shows the voltage detection level when the power supply drops.  
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply  
drops by approximately 0.1 V.  
Table 21.9  
Voltage Detection 2 Circuit Electrical Characteristics  
Standard  
Typ.  
3.6  
Symbol  
Parameter  
Condition  
Unit  
Min.  
3.3  
Max.  
3.9  
Vdet2  
V
Voltage detection level  
Voltage monitor 2 interrupt request generation time(2)  
Voltage detection circuit self power consumption  
Waiting time until voltage detection circuit operation  
starts(3)  
40  
µs  
µA  
µs  
VCA27 = 1, VCC = 5.0 V  
0.6  
td(E-A)  
100  
NOTES:  
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = 20 to 85°C (N version) / 40 to 85°C (D version).  
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.  
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2  
register to 0.  
Rev.1.00 Dec 14, 2007 Page 298 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Table 21.10 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics  
Standard  
Symbol  
Parameter  
Condition  
Unit  
Min.  
Typ.  
Max.  
0.1  
2.6  
Power-on reset valid voltage(3)  
Power-on reset valid voltage  
Vpor1  
V
V
Vpor2  
trth  
0
External power VCC rise gradient(2)  
20  
mV/msec  
NOTES:  
1. The measurement condition is Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V.  
3. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on  
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if 20°C Topr 85°C, maintain tw(por1) for  
3,000 s or more if 40°C Topr < 20°C.  
max. 2.6 V  
max. 2.6 V  
2.2 V  
trth  
trth  
External  
Power VCC  
Vpor2  
Vpor1  
Sampling time(1, 2)  
tw(por1)  
Internal  
reset signal  
(“L” valid)  
1
1
× 32  
× 32  
fOCO-S  
fOCO-S  
NOTES:  
1. Ensure that the voltage is 2.2 V or above during the sampling time.  
2. The sampling time is fOCO-S divided by 1 × 4 cycles.  
Figure 21.3  
Reset Circuit Electrical Characteristics  
Rev.1.00 Dec 14, 2007 Page 299 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Table 21.11 High-speed On-Chip Oscillator Circuit Electrical Characteristics  
Standard  
Typ.  
Symbol  
Parameter  
Condition  
Unit  
Min.  
39.2  
Max.  
40.8  
fOCO40M  
High-speed on-chip oscillator frequency  
temperature • supply voltage dependence  
VCC = 4.75 V to 5.25 V  
0°C Topr 60°C(2)  
VCC = 3.0 V to 5.5 V  
20°C Topr 85°C(2)  
VCC = 3.0 V to 5.5 V  
40°C Topr 85°C(2)  
VCC = 2.7 V to 5.5 V  
20°C Topr 85°C(2)  
VCC = 2.7 V to 5.5 V  
40°C Topr 85°C(2)  
VCC = 5.0 V ±10%  
40  
MHz  
38.8  
38.4  
38  
40  
40  
40  
40  
40  
40  
41.2  
41.6  
42  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
37.6  
38.8  
38.4  
42.4  
40.8  
40.8  
20°C Topr 85°C(2)  
VCC = 5.0 V ±10%  
40°C Topr 85°C(2)  
VCC = 5.0 V, Topr = 25°C  
High-speed on-chip oscillator frequency when  
correction value in FRA7 register is written to  
FRA1 register  
36.864  
MHz  
%
VCC = 2.7 V to 5.5 V  
20°C Topr 85°C  
3%  
3%  
Value in FRA1 register after reset  
08h  
F7h  
Oscillation frequency adjustment unit of high-  
speed on-chip oscillator  
Adjust FRA1 register  
(value after reset) to 1  
+0.3  
MHz  
Oscillation stability time  
10  
100  
µs  
Self power consumption at oscillation  
VCC = 5.0 V, Topr = 25°C  
400  
µA  
NOTES:  
1. VCC = 2.7 to 5.5 V, Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
2. These standard values show when the FRA1 register value after reset is assumed.  
Table 21.12 Low-speed On-Chip Oscillator Circuit Electrical Characteristics  
Standard  
Typ.  
125  
Symbol  
fOCO-S  
Parameter  
Condition  
Unit  
Min.  
30  
Max.  
250  
100  
Low-speed on-chip oscillator frequency  
Oscillation stability time  
kHz  
µs  
10  
Self power consumption at oscillation  
VCC = 5.0 V, Topr = 25°C  
15  
µA  
NOTE:  
1. VCC = 2.7 to 5.5 V, Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.  
Table 21.13 Power Supply Circuit Timing Characteristics  
Standard  
Symbol  
Parameter  
Condition  
Unit  
Min.  
1
Typ.  
Max.  
2000  
td(P-R)  
Time for internal power supply stabilization during  
power-on(2)  
µs  
STOP exit time(3)  
td(R-S)  
150  
µs  
NOTES:  
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25°C.  
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.  
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.  
Rev.1.00 Dec 14, 2007 Page 300 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Table 21.14 Electrical Characteristics (1) [VCC = 5 V]  
Standard  
Unit  
Symbol  
VOH  
Parameter  
Condition  
Min.  
Typ.  
Max.  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
2.0  
Output “H” voltage Except P1_0 to P1_7, IOH = 5 mA  
VCC 2.0  
VCC 0.5  
VCC 2.0  
VCC 2.0  
VCC 2.0  
V
V
V
V
V
V
V
V
V
V
V
V
V
XOUT  
IOH = 200 µA  
P1_0 to P1_7  
Drive capacity HIGH IOH = 10 mA  
Drive capacity LOW IOH = 5 mA  
Drive capacity HIGH IOH = 1 mA  
XOUT  
Drive capacity LOW IOH = 500 µA VCC 2.0  
VOL  
Output “L” voltage Except P1_0 to P1_7, IOL = 5 mA  
XOUT  
IOL = 200 µA  
0.45  
2.0  
P1_0 to P1_7  
Drive capacity HIGH IOL = 10 mA  
Drive capacity LOW IOL = 5 mA  
Drive capacity HIGH IOL = 1 mA  
Drive capacity LOW IOL = 500 µA  
2.0  
XOUT  
2.0  
2.0  
VT+-VT-  
Hysteresis  
0.1  
0.5  
INT0, INT1, INT3,  
KI0, KI1, KI2, KI3,  
TRAIO, RXD0, CLK0  
0.1  
1.0  
V
RESET  
IIH  
IIL  
Input “H” current  
Input “L” current  
VI = 5 V, VCC = 5 V  
VI = 0 V, VCC = 5 V  
VI = 0 V, VCC = 5 V  
5.0  
5.0  
167  
µA  
µA  
RPULLUP Pull-up resistance  
30  
50  
1.0  
kΩ  
MΩ  
RfXIN  
Feedback  
resistance  
XIN  
VRAM  
RAM hold voltage  
During stop mode  
1.8  
V
NOTE:  
1. VCC = 4.2 to 5.5 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.  
Rev.1.00 Dec 14, 2007 Page 301 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Table 21.15 Electrical Characteristics (2) [Vcc = 5 V]  
(Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.)  
Standard  
Symbol  
ICC  
Parameter  
Condition  
Unit  
mA  
Min.  
Typ.  
10  
Max.  
17  
XIN = 20 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
Power supply  
current  
High-speed  
clock mode  
(VCC = 3.3 to 5.5 V)  
Single-chip mode,  
output pins are  
open, other pins  
are VSS  
XIN = 16 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
9
6
15  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
µA  
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN = 20 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
5
XIN = 16 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
4
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
2.5  
10  
4
XIN clock off  
High-speed  
on-chip  
oscillator mode  
15  
High-speed on-chip oscillator on fOCO = 20 MHz  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN clock off  
High-speed on-chip oscillator on fOCO = 20 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN clock off  
5.5  
2.5  
130  
25  
10  
High-speed on-chip oscillator on fOCO = 10 MHz  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN clock off  
High-speed on-chip oscillator on fOCO = 10 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
XIN clock off  
Low-speed  
on-chip  
300  
75  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8, FMR47 = 1  
oscillator mode  
XIN clock off  
Wait mode  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock operation  
VCA27 = VCA26 = 0  
VCA20 = 1  
XIN clock off  
23  
60  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock off  
VCA27 = VCA26 = 0  
VCA20 = 1  
XIN clock off, Topr = 25°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = 0  
Stop mode  
0.8  
1.2  
3.0  
µA  
µA  
XIN clock off, Topr = 85°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = 0  
Rev.1.00 Dec 14, 2007 Page 302 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Timing Requirements  
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]  
Table 21.16 XIN Input  
Standard  
Unit  
Symbol  
Parameter  
Min.  
50  
Max.  
tc(XIN)  
XIN input cycle time  
XIN input “H” width  
XIN input “L” width  
ns  
ns  
ns  
tWH(XIN)  
tWL(XIN)  
25  
25  
VCC = 5 V  
tC(XIN)  
tWH(XIN)  
XIN input  
tWL(XIN)  
Figure 21.4  
XIN Input Timing Diagram when VCC = 5 V  
Table 21.17 TRAIO Input  
Standard  
Max.  
Symbol  
Parameter  
Unit  
Min.  
100  
40  
tc(TRAIO)  
TRAIO input cycle time  
TRAIO input “H” width  
TRAIO input “L” width  
ns  
ns  
ns  
tWH(TRAIO)  
tWL(TRAIO)  
40  
tC(TRAIO)  
VCC = 5 V  
tWH(TRAIO)  
TRAIO input  
tWL(TRAIO)  
Figure 21.5  
TRAIO Input Timing Diagram when VCC = 5 V  
Rev.1.00 Dec 14, 2007 Page 303 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F Group  
21. Electrical Characteristics  
Table 21.18 Serial Interface  
Standard  
Unit  
Symbol  
Parameter  
Min.  
200  
100  
100  
Max.  
tc(CK)  
CLK0 input cycle time  
CLK0 input “H” width  
CLK0 input “L” width  
TXD0 output delay time  
TXD0 hold time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tW(CKH)  
tW(CKL)  
td(C-Q)  
th(C-Q)  
tsu(D-C)  
th(C-D)  
50  
0
RXD0 input setup time  
RXD0 input hold time  
50  
90  
VCC = 5 V  
tC(CK)  
tW(CKH)  
CLK0  
tW(CKL)  
th(C-Q)  
TXD0  
RXD0  
td(C-Q)  
tsu(D-C)  
th(C-D)  
Figure 21.6  
Serial Interface Timing Diagram when VCC = 5 V  
Table 21.19 External Interrupt INTi (i = 0, 1, 3) Input  
Standard  
Symbol  
Parameter  
Unit  
Min.  
Max.  
250(1)  
250(2)  
tW(INH)  
ns  
ns  
INTi input “H” width  
INTi input “L” width  
tW(INL)  
NOTES:  
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
VCC = 5 V  
tW(INL)  
INTi input  
tW(INH)  
i = 0, 1, 3  
Figure 21.7  
External Interrupt INTi Input Timing Diagram when VCC = 5 V  
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21. Electrical Characteristics  
Table 21.20 Electrical Characteristics (3) [VCC = 3 V]  
Standard  
Unit  
Symbol  
VOH  
Parameter  
Condition  
Min.  
Typ.  
Max.  
VCC  
Output “H” voltage Except P1_0 to P1_7, IOH = 1 mA  
VCC 0.5  
V
V
V
V
V
V
V
V
V
V
V
XOUT  
P1_0 to P1_7  
Drive capacity  
HIGH  
IOH = 2 mA  
IOH = 1 mA  
VCC 0.5  
VCC 0.5  
VCC  
VCC  
VCC  
VCC  
0.5  
0.5  
0.5  
0.5  
0.5  
Drive capacity  
LOW  
XOUT  
Drive capacity  
HIGH  
IOH = 0.1 mA VCC 0.5  
Drive capacity  
LOW  
IOH = 50 µA  
VCC 0.5  
VOL  
Output “L” voltage  
Except P1_0 to P1_7, IOL = 1 mA  
XOUT  
P1_0 to P1_7  
Drive capacity  
HIGH  
IOL = 2 mA  
IOL = 1 mA  
IOL = 0.1 mA  
IOL = 50 µA  
Drive capacity  
LOW  
XOUT  
Drive capacity  
HIGH  
Drive capacity  
LOW  
VT+-VT-  
Hysteresis  
0.1  
0.3  
INT0, INT1, INT3,  
KI0, KI1, KI2, KI3,  
TRAIO, RXD0, CLK0  
0.1  
0.4  
V
RESET  
IIH  
IIL  
Input “H” current  
Input “L” current  
VI = 3 V, VCC = 3 V  
VI = 0 V, VCC = 3 V  
VI = 0 V, VCC = 3 V  
4.0  
4.0  
500  
µA  
µA  
kΩ  
MΩ  
V
RPULLUP Pull-up resistance  
66  
160  
3.0  
RfXIN  
VRAM  
Feedback resistance XIN  
RAM hold voltage  
During stop mode  
1.8  
NOTE:  
1. VCC =2.7 to 3.3 V at Topr = 20 to 85°C (N version) / 40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.  
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21. Electrical Characteristics  
Table 21.21 Electrical Characteristics (4) [Vcc = 3 V]  
(Topr = 20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.)  
Standard  
Symbol  
ICC  
Parameter  
Condition  
Unit  
mA  
Min.  
Typ.  
6
Max.  
Power supply current High-speed  
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
No division  
(VCC = 2.7 to 3.3 V)  
Single-chip mode,  
output pins are open,  
other pins are VSS  
clock mode  
XIN = 10 MHz (square wave)  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
2
5
9
mA  
mA  
mA  
µA  
High-speed  
on-chip  
oscillator  
mode  
XIN clock off  
High-speed on-chip oscillator on fOCO = 10 MHz  
Low-speed on-chip oscillator on = 125 kHz  
No division  
XIN clock off  
2
High-speed on-chip oscillator on fOCO = 10 MHz  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8  
Low-speed  
on-chip  
oscillator  
mode  
XIN clock off  
130  
300  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
Divide-by-8, FMR47 = 1  
Wait mode  
XIN clock off  
25  
23  
70  
55  
µA  
µA  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock operation  
VCA27 = VCA26 = 0  
VCA20 = 1  
XIN clock off  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator on = 125 kHz  
While a WAIT instruction is executed  
Peripheral clock off  
VCA27 = VCA26 = 0  
VCA20 = 1  
Stop mode  
XIN clock off, Topr = 25°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
0.7  
1.1  
3.0  
µA  
µA  
Peripheral clock off  
VCA27 = VCA26 = 0  
XIN clock off, Topr = 85°C  
High-speed on-chip oscillator off  
Low-speed on-chip oscillator off  
CM10 = 1  
Peripheral clock off  
VCA27 = VCA26 = 0  
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21. Electrical Characteristics  
Timing requirements  
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]  
Table 21.22 XIN Input  
Standard  
Unit  
Symbol  
Parameter  
Min.  
100  
40  
Max.  
tc(XIN)  
XIN input cycle time  
XIN input “H” width  
XIN input “L” width  
ns  
ns  
ns  
tWH(XIN)  
tWL(XIN)  
40  
tC(XIN)  
VCC = 3 V  
tWH(XIN)  
XIN input  
tWL(XIN)  
Figure 21.8  
XIN Input Timing Diagram when VCC = 3 V  
Table 21.23 TRAIO Input  
Standard  
Symbol  
Parameter  
Unit  
Min.  
300  
120  
120  
Max.  
tc(TRAIO)  
TRAIO input cycle time  
TRAIO input “H” width  
TRAIO input “L” width  
ns  
ns  
ns  
tWH(TRAIO)  
tWL(TRAIO)  
VCC = 3 V  
tC(TRAIO)  
tWH(TRAIO)  
TRAIO input  
tWL(TRAIO)  
Figure 21.9  
TRAIO Input Timing Diagram when VCC = 3 V  
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21. Electrical Characteristics  
Table 21.24 Serial Interface  
Standard  
Unit  
Symbol  
Parameter  
Min.  
300  
150  
150  
Max.  
tc(CK)  
CLK0 input cycle time  
CLK0 input “H” width  
CLK0 Input “L” width  
TXD0 output delay time  
TXD0 hold time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tW(CKH)  
tW(CKL)  
td(C-Q)  
th(C-Q)  
tsu(D-C)  
th(C-D)  
80  
0
RXD0 input setup time  
RXD0 input hold time  
70  
90  
tC(CK)  
VCC = 3 V  
tW(CKH)  
CLK0  
tW(CKL)  
th(C-Q)  
TXD0  
RXD0  
td(C-Q)  
tsu(D-C)  
th(C-D)  
Figure 21.10 Serial Interface Timing Diagram when VCC = 3 V  
Table 21.25 External Interrupt INTi (i = 0, 1, 3) Input  
Standard  
Min. Max.  
Symbol  
Parameter  
Unit  
380(1)  
380(2)  
tW(INH)  
ns  
ns  
INTi input “H” width  
INTi input “L” width  
tW(INL)  
NOTES:  
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock  
frequency × 3) or the minimum value of standard, whichever is greater.  
VCC = 3 V  
tW(INL)  
INTi input  
tW(INH)  
i = 0, 1, 3  
Figure 21.11 External Interrupt INTi Input Timing Diagram when VCC = 3 V  
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22. Usage Notes  
22. Usage Notes  
22.1 Notes on Clock Generation Circuit  
22.1.1 Stop Mode  
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the  
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction  
which sets the CM10 bit to 1 (stop mode) and the program stops.  
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit  
to 1.  
Program example to enter stop mode  
BCLR  
BSET  
FSET  
BSET  
JMP.B  
1,FMR0  
0,PRCR  
I
0,CM1  
LABEL_001  
; CPU rewrite mode disabled  
; Protect disabled  
; Enable interrupt  
; Stop mode  
LABEL_001 :  
NOP  
NOP  
NOP  
NOP  
22.1.2 Wait Mode  
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and  
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the  
program stops. Insert at least 4 NOP instructions after the WAIT instruction.  
Program example to execute the WAIT instruction  
BCLR  
FSET  
WAIT  
NOP  
1,FMR0  
I
; CPU rewrite mode disabled  
; Enable interrupt  
; Wait mode  
NOP  
NOP  
NOP  
22.1.3 Oscillation Stop Detection Function  
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set  
bits OCD1 to OCD0 to 00b.  
22.1.4 Oscillation Circuit Constants  
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.  
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1  
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the  
feedback resistor to the chip externally.  
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22. Usage Notes  
22.2 Notes on Interrupts  
22.2.1 Reading Address 00000h  
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads  
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At  
this time, the acknowledged interrupt IR bit is set to 0.  
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the  
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be  
generated.  
22.2.2 SP Setting  
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an  
interrupt is acknowledged before setting a value in the SP, the program may run out of control.  
22.2.3 External Interrupt and Key Input Interrupt  
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input  
to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.  
For details, refer to Table 21.19 (VCC = 5V), Table 21.25 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3)  
Input.  
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22. Usage Notes  
22.2.4 Changing Interrupt Sources  
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source  
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.  
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to  
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral  
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after  
the change. Refer to the individual peripheral function for its related interrupts.  
Figure 22.1 shows an Example of Procedure for Changing Interrupt Sources.  
Interrupt source change  
Disable interrupts(2, 3)  
Change interrupt source (including mode  
of peripheral function)  
Set the IR bit to 0 (interrupt not requested)  
using the MOV instruction(3)  
Enable interrupts(2, 3)  
Change completed  
IR bit:  
The interrupt control register bit of an  
interrupt whose source is changed.  
NOTES:  
1. Execute the above settings individually. Do not execute two  
or more settings at once (by one instruction).  
2. To prevent interrupt requests from being generated, disable  
the peripheral function before changing the interrupt  
source. In this case, use the I flag if all maskable interrupts  
can be disabled. If all maskable interrupts cannot be  
disabled, use bits ILVL0 to ILVL2 of the interrupt whose  
source is changed.  
3. Refer to 12.6.5 Changing Interrupt Control Register for  
the instructions to be used and usage notes.  
Figure 22.1  
Example of Procedure for Changing Interrupt Sources  
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22. Usage Notes  
22.2.5 Changing Interrupt Control Register Contents  
(a) The contents of an interrupt control register can only be changed while no interrupt requests  
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts  
before changing the interrupt control register contents.  
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to  
choose appropriate instructions.  
Changing any bit other than IR bit  
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit  
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a  
problem, use the following instructions to change the register: AND, OR, BCLR, BSET  
Changing IR bit  
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.  
Therefore, use the MOV instruction to set the IR bit to 0.  
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer  
to (b) regarding changing the contents of interrupt control registers by the sample programs.  
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt  
control register is changed for reasons of the internal bus or the instruction queue buffer.  
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register  
is changed  
INT_SWITCH1:  
FCLR  
I
; Disable interrupts  
AND.B #00H,0056H  
NOP  
NOP  
; Set TRAIC register to 00h  
;
FSET  
I
; Enable interrupts  
Example 2: Use dummy read to delay FSET instruction  
INT_SWITCH2:  
FCLR  
AND.B #00H,0056H  
MOV.W MEM,R0  
I
; Disable interrupts  
; Set TRAIC register to 00h  
; Dummy read  
FSET  
I
; Enable interrupts  
Example 3: Use POPC instruction to change I flag  
INT_SWITCH3:  
PUSHC FLG  
FCLR  
AND.B #00H,0056H  
POPC FLG  
I
; Disable interrupts  
; Set TRAIC register to 00h  
; Enable interrupts  
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22. Usage Notes  
22.3 Notes on Timers  
22.3.1 Notes on Timer RA  
Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the  
count starts.  
Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by  
the MCU. Consequently, the timer value may be updated during the period when these two registers are  
being read.  
In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by  
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the  
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0  
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or  
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.  
When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and  
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.  
The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.  
When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler  
immediately after the count starts, then set the TEDGF bit to 0.  
The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1  
(count starts) while the count is stopped.  
(1)  
During this time, do not access registers associated with timer RA other than the TCSTF bit. Timer RA  
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).  
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count  
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.  
(1)  
During this time, do not access registers associated with timer RA other than the TCSTF bit.  
NOTE:  
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.  
When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow  
three or more cycles of the count source clock for each write interval.  
When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three  
or more cycles of the prescaler underflow for each write interval.  
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22. Usage Notes  
22.3.2 Notes on Timer RB  
Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the  
count starts.  
Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the  
MCU. Consequently, the timer value may be updated during the period when these two registers are being  
read.  
In programmable one-shot generation mode and programmable wait one-shot generation mode, when  
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the  
TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore,  
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the  
timer count value before the timer stops.  
The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to  
1 (count starts) while the count is stopped.  
(1)  
During this time, do not access registers associated with timer RB other than the TCSTF bit. Timer RB  
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).  
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count  
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.  
(1)  
During this time, do not access registers associated with timer RB other than the TCSTF bit.  
NOTE:  
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and  
TRBPR.  
If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.  
If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes  
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period  
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be  
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the  
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit  
may be set to either 0 or 1.  
22.3.2.1 Timer mode  
The following workaround should be performed in timer mode.  
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following  
points:  
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each  
write interval.  
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow  
for each write interval.  
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22. Usage Notes  
22.3.2.2 Programmable waveform generation mode  
The following three workarounds should be performed in programmable waveform generation mode.  
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the  
following points:  
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each  
write interval.  
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow  
for each write interval.  
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize  
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in  
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period  
A shown in Figures 22.2 and 22.3.  
The following shows the detailed workaround examples.  
Workaround example (a):  
As shown in Figure 22.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These  
write operations must be completed by the beginning of period A.  
Period A  
Count source/  
prescaler  
underflow signal  
Primary period  
Secondary period  
TRBO pin output  
IR bit in  
TRBIC register  
Interrupt request is  
acknowledged  
(a)  
Ensure sufficient time  
(b)  
Interrupt  
Instruction in  
Set the secondary and then  
the primary register immediately  
Interrupt request  
is generated  
sequence interrupt routine  
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time  
varies depending on the instruction being executed.  
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as  
the divisor).  
(b) 20 cycles. 21 cycles for address match and single-step interrupts.  
Figure 22.2  
Workaround Example (a) When Timer RB interrupt is Used  
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22. Usage Notes  
Workaround example (b):  
As shown in Figure 22.3 detect the start of the primary period by the TRBO pin output level and write to  
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.  
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is  
set to 0 (input mode), the read value indicates the TRBO pin output value.  
Period A  
Count source/  
prescaler  
underflow signal  
Primary period  
Secondary period  
TRBO pin output  
Read value of the port register’s  
bit corresponding to the TRBO pin  
(when the bit in the port direction  
register is set to 0)  
(i) (ii) (iii)  
Ensure sufficient time  
The TRBO output inversion  
is detected at the end of the  
secondary period.  
Upon detecting (i), set the secondary and  
then the primary register immediately.  
Figure 22.3  
Workaround Example (b) When TRBO Pin Output Value is Read  
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,  
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.  
22.3.2.3 Programmable one-shot generation mode  
The following two workarounds should be performed in programmable one-shot generation mode.  
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the  
following points:  
When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow  
three or more cycles of the count source for each write interval.  
When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow  
three or more cycles of the prescaler underflow for each write interval.  
(2) Do not set both the TRBPRE and TRBPR registers to 00h.  
Rev.1.00 Dec 14, 2007 Page 316 of 332  
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R8C/2E Group, R8C/2F Group  
22. Usage Notes  
22.3.2.4 Programmable wait one-shot generation mode  
The following three workarounds should be performed in programmable wait one-shot generation mode.  
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the  
following points:  
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each  
write interval.  
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow  
for each write interval.  
(2) Do not set both the TRBPRE and TRBPR registers to 00h.  
(3) Set registers TRBSC and TRBPR using the following procedure.  
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition  
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR  
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the  
INT0 pin.  
(b) To use “writing 1 to TOSST bit” as the start condition  
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the  
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the  
TOSST bit.  
Rev.1.00 Dec 14, 2007 Page 317 of 332  
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22. Usage Notes  
22.3.3 Notes on Timer RC  
22.3.3.1 TRC Register  
The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at  
compare match with TRCGRA register).  
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is  
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is  
set to 0000h.  
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the  
write value will not be written to the TRC register and the TRC register will be set to 0000h.  
Reading from the TRC register immediately after writing to it can result in the value previous to the write  
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.  
Program Example  
MOV.W  
JMP.B  
MOV.W  
#XXXXh, TRC  
L1  
TRC,DATA  
;Write  
;JMP.B instruction  
;Read  
L1:  
22.3.3.2 TRCSR Register  
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write  
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.  
Program Example  
MOV.B  
JMP.B  
MOV.B  
#XXh, TRCSR  
L1  
TRCSR,DATA  
;Write  
;JMP.B instruction  
;Read  
L1:  
22.3.3.3 Count Source Switching  
Stop the count before switching the count source.  
Switching procedure  
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).  
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.  
After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to  
elapse after changing the clock setting before stopping fOCO40M.  
Switching procedure  
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).  
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.  
(3) Wait for a minimum of two cycles of f1.  
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).  
22.3.3.4 Input Capture Function  
The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock  
(refer to Table 14.11 Timer RC Operation Clock).  
The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC  
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the  
digital filter function is not used).  
22.3.3.5 TRCMR Register in PWM2 Mode  
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA  
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.  
Rev.1.00 Dec 14, 2007 Page 318 of 332  
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R8C/2E Group, R8C/2F Group  
22. Usage Notes  
22.3.4 Notes on Timer RE  
22.3.4.1 Starting and Stopping Count  
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates  
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.  
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count  
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to  
(1)  
1. During this time, do not access registers associated with timer RE other than the TCSTF bit.  
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0  
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting  
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF  
bit.  
NOTE:  
1. Registers associated with timer RE: TRESEC, TREMIN, TRECR1, TRECR2, and TRECSR.  
22.3.4.2 Register Setting  
Write to the following registers or bits when timer RE is stopped.  
Registers TRESEC, TREMIN, and TRECR2  
INT bit in TRECR1 register  
Bits RCS0 to RCS2 and b3 in TRECSR register  
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).  
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the  
TRECR2 register.  
Rev.1.00 Dec 14, 2007 Page 319 of 332  
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22. Usage Notes  
22.4 Notes on Serial Interface  
When reading data from the U0RB register either in the clock synchronous serial I/O mode or in the clock  
asynchronous serial I/O mode, ensure the data is read in 16-bit units. When the high-order byte of the U0RB  
register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0.  
The check receive errors, read the U0RB register and then use the read data.  
Example (when reading receive buffer register):  
MOV.W  
00A6H,R0  
; Read the U0RB register  
When writing data to the U0TB register in the clock asynchronous serial I/O mode with 9-bit transfer data  
length, write data to the high-order byte first then the low-order byte, in 8-bit units.  
Example (when reading transmit buffer register):  
MOV.B  
MOV.B  
#XXH,00A3H ; Write the high-order byte of U0TB register  
#XXH,00A2H ; Write the low-order byte of U0TB register  
Rev.1.00 Dec 14, 2007 Page 320 of 332  
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R8C/2E Group, R8C/2F Group  
22. Usage Notes  
22.5 Notes on Hardware LIN  
For the time-out processing of the header and response fields, use another timer to measure the duration of time  
with a Synch Break detection interrupt as the starting point.  
Rev.1.00 Dec 14, 2007 Page 321 of 332  
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22. Usage Notes  
22.6 Notes on A/D Converter  
Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit  
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).  
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF  
connected), wait for at least 1 µs before starting the A/D conversion.  
After changing the A/D operating mode, select an analog input pin again.  
When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The  
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D  
conversion is completed.  
When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the  
CPU clock during A/D conversion.  
Do not select the fOCO-F for the φAD.  
If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion  
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be  
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.  
Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.  
Do not enter stop mode during A/D conversion.  
Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in  
wait mode) during A/D conversion.  
Rev.1.00 Dec 14, 2007 Page 322 of 332  
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22. Usage Notes  
22.7 Notes on Flash Memory Version  
22.7.1 CPU Rewrite Mode  
22.7.1.1 Operating Speed  
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit  
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.  
22.7.1.2 Prohibited Instructions  
The following instructions cannot be used in EW0 mode because they reference internal data in flash memory:  
UND, INTO, and BRK.  
22.7.1.3 Interrupts  
Table 22.1 lists the EW0 Mode Interrupts and Table 22.2 lists the EW1 Mode Interrupt.  
Table 22.1  
EW0 Mode Interrupts  
When Maskable  
When Watchdog Timer, Oscillation Stop  
Detection, Voltage Monitor 1, or Voltage Monitor  
2 Interrupt Request is Acknowledged  
Mode  
Status  
Interrupt Request is  
Acknowledged  
EW0 During auto-erasure Any interrupt can be used Once an interrupt request is acknowledged, the  
by allocating a vector in auto-programming or auto-erasure is forcibly  
RAM  
stopped immediately and the flash memory is  
reset. Interrupt handling starts after the fixed  
period and the flash memory restarts. Since the  
block during auto-erasure or the address during  
auto-programming is forcibly stopped, the  
normal value may not be read. Execute auto-  
erasure again and ensure it completes normally.  
Since the watchdog timer does not stop during  
the command operation, interrupt requests may  
be generated. Reset the watchdog timer  
regularly.  
Auto-programming  
NOTES:  
1. Do not use the address match interrupt while a command is being executed because the vector of  
the address match interrupt is allocated in ROM.  
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed  
vector is allocated in block 0.  
Rev.1.00 Dec 14, 2007 Page 323 of 332  
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R8C/2E Group, R8C/2F Group  
22. Usage Notes  
Table 22.2  
EW1 Mode Interrupt  
When Watchdog Timer, Oscillation Stop  
Detection, Voltage Monitor 1, or Voltage  
Monitor 2 Interrupt Request is  
Acknowledged  
When Maskable Interrupt  
Request is Acknowledged  
Mode  
Status  
EW1 During auto-erasure Auto-erasure is suspended after Once an interrupt request is  
(erase-suspend  
function enabled)  
td(SR-SUS) and interrupt  
handling is executed. Auto-  
erasure can be restarted by  
setting the FMR41 bit in the  
acknowledged, auto-programming or  
auto-erasure is forcibly stopped  
immediately and the flash memory is  
reset. Interrupt handling starts after the  
FMR4 register to 0 (erase restart) fixed period and the flash memory  
after interrupt handling  
completes.  
restarts. Since the block during auto-  
erasure or the address during auto-  
programming is forcibly stopped, the  
normal value may not be read. Execute  
auto-erasure again and ensure it  
completes normally.  
Since the watchdog timer does not stop  
during the command operation,  
interrupt requests may be generated.  
Reset the watchdog timer regularly  
using the erase-suspend function.  
During auto-erasure Auto-erasure has priority and the  
(erase-suspend  
function disabled)  
interrupt request  
acknowledgement is put on  
standby. Interrupt handling is  
executed after auto-erasure  
completes.  
During auto-  
programming  
(program suspend  
function enabled)  
Auto-programming is suspended  
after td(SR-SUS) and interrupt  
handling is executed.  
Auto-programming can be  
restarted by setting the FMR42 bit  
in the FMR4 register to 0  
(program restart) after interrupt  
handling completes.  
During auto-  
programming  
(program suspend  
function disabled)  
Auto-programming has priority  
and the interrupt request  
acknowledgement is put on  
standby. Interrupt handling is  
executed after auto-programming  
completes.  
NOTES:  
1. Do not use the address match interrupt while a command is executing because the vector of the  
address match interrupt is allocated in ROM.  
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed  
vector is allocated in block 0.  
Rev.1.00 Dec 14, 2007 Page 324 of 332  
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22. Usage Notes  
22.7.1.4 How to Access  
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt  
between writing 0 and 1.  
22.7.1.5 Rewriting User ROM Area  
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is  
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be  
rewritten correctly. In this case, use standard serial I/O mode.  
22.7.1.6 Program  
Do not write additions to the already programmed address.  
22.7.1.7 Entering Stop Mode or Wait Mode  
Do not enter stop mode or wait mode during erase-suspend.  
22.7.1.8 Program and Erase Voltage for Flash Memory  
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform  
programming and erasure at less than 2.7 V.  
Rev.1.00 Dec 14, 2007 Page 325 of 332  
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22. Usage Notes  
22.8 Notes on Noise  
22.8.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure  
against Noise and Latch-up  
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.  
22.8.2 Countermeasures against Noise Error of Port Control Registers  
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the  
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers  
may be changed.  
As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up  
control registers be reset periodically. However, examine the control processing fully before introducing the  
reset routine as conflicts may be created between the reset routine and interrupt routines.  
Rev.1.00 Dec 14, 2007 Page 326 of 332  
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23. Notes for On-Chip Debugger  
23. Notes for On-Chip Debugger  
When using the on-chip debugger to develop and debug programs for the R8C/2E Group and R8C/2F Group take note  
of the following.  
(1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be  
accessed by the user.  
Refer to the on-chip debugger manual for which areas are used.  
(2) Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a  
user system.  
(3) Do not use the BRK instruction in a user system.  
(4) Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip  
debugger under less than 2.7 V is not allowed.  
Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for  
details.  
Rev.1.00 Dec 14, 2007 Page 327 of 332  
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R8C/2E Group, R8C/2F Group  
Appendix 1. Package Dimensions  
Appendix 1. Package Dimensions  
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of  
the Renesas Technology website.  
JEITA Package Code  
P-LQFP32-7x7-0.80  
RENESAS Code  
PLQP0032GB-A  
Previous Code  
32P6U-A  
MASS[Typ.]  
0.2g  
HD  
*1  
D
24  
17  
NOTE)  
1. DIMENSIONS "*1" AND "*2"  
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION "*3" DOES NOT  
INCLUDE TRIM OFFSET.  
16  
25  
bp  
b1  
Dimension in Millimeters  
Reference  
Symbol  
Min Nom Max  
D
E
6.9 7.0 7.1  
6.9 7.0 7.1  
1.4  
Terminal cross section  
32  
9
A2  
HD  
HE  
A
8.8 9.0 9.2  
8.8 9.0 9.2  
1.7  
1
8
ZD  
Index mark  
A1  
bp  
b1  
c
0.1 0.2  
0
0.32 0.37 0.42  
0.35  
F
c
0.09  
0.20  
0.145  
0.125  
c1  
L
L1  
0°  
8°  
e
0.8  
Detail F  
y
x
0.20  
0.10  
*3  
bp  
x
e
y
ZD  
ZE  
L
0.7  
0.7  
0.3 0.5 0.7  
1.0  
L1  
Rev.1.00 Dec 14, 2007 Page 328 of 332  
REJ09B0349-0100  
R8C/2E Group, R8C/2F GroupAppendix 2. Connection Examples between Serial Writer and On-Chip Debugging  
Appendix 2. Connection Examples between Serial Writer and On-Chip  
Debugging Emulator  
Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2  
shows a Connection Example with E8 Emulator (R0E000080KCE00).  
VCC  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
(2)  
TXD  
RESET  
Connect oscillation circuit(1)  
VSS  
MODE  
10  
TXD  
7
1
VSS  
VCC  
RXD  
4
M16C Flash Starter  
(M3A-0806)  
(2)  
RXD  
NOTES:  
1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock.  
2. For development tools only.  
Appendix Figure 2.1  
Connection Example with M16C Flash Starter (M3A-0806)  
VCC  
Open collector buffer  
User logic  
4.7kor more  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Connect oscillation circuit(1)  
VSS  
4.7kΩ ±10%  
13  
14  
12  
10  
8
RESET  
MODE  
7
MODE  
VCC  
6
4
2
VSS  
NOTE:  
1. It is not necessary to connect an oscillation circuit when  
operating with the on-chip oscillator clock.  
E8 emulator  
(R0E000080KCE00)  
Appendix Figure 2.2  
Connection Example with E8 Emulator (R0E000080KCE00)  
Rev.1.00 Dec 14, 2007 Page 329 of 332  
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R8C/2E Group, R8C/2F Group  
Appendix 3. Example of Oscillation Evaluation Circuit  
Appendix 3. Example of Oscillation Evaluation Circuit  
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.  
VCC  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
RESET  
VSS  
3
4
5
6
7
8
Connect  
oscillation  
circuit  
NOTE:  
1. After reset, the XIN clock stops.  
Write a program to oscillate the XIN clock.  
Appendix Figure 3.1  
Example of Oscillation Evaluation Circuit  
Rev.1.00 Dec 14, 2007 Page 330 of 332  
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R8C/2E Group, R8C/2F Group  
Index  
Index  
PUR1 ..................................................................................... 51  
[ A ]  
ACCR0 to ACCR1 ....................................................... 255, 258  
ACMR .................................................................................. 259  
AD ....................................................................................... 242  
ADCON0 ............................................................................. 241  
ADCON1 ............................................................................. 242  
ADCON2 ............................................................................. 242  
ADIC ...................................................................................... 95  
AIER .................................................................................... 110  
[ R ]  
RMAD0 ................................................................................ 110  
RMAD1 ................................................................................ 110  
[ S ]  
S0RIC .................................................................................... 95  
S0TIC .................................................................................... 95  
[ C ]  
CM0 ....................................................................................... 67  
CM0IC ................................................................................... 96  
CM1 ....................................................................................... 68  
CM1IC ................................................................................... 96  
CSPR .................................................................................. 117  
[ T ]  
TRA ..................................................................................... 124  
TRACR ................................................................................ 123  
TRAIC .................................................................................... 95  
TRAIOC ....................................... 123, 125, 128, 130, 132, 135  
TRAMR ................................................................................ 124  
TRAPRE .............................................................................. 124  
TRBCR ................................................................................ 139  
TRBIC .................................................................................... 95  
TRBIOC ............................................... 140, 142, 146, 149, 153  
TRBMR ................................................................................ 140  
TRBOCR ............................................................................. 139  
TRBPR ................................................................................ 141  
TRBPRE .............................................................................. 141  
TRBSC ................................................................................ 141  
TRC ..................................................................................... 166  
TRCCR1 ...................................................... 163, 186, 190, 195  
TRCCR2 .............................................................................. 167  
TRCDF ................................................................................ 168  
TRCGRA ............................................................................. 166  
TRCGRB ............................................................................. 166  
TRCGRC ............................................................................. 166  
TRCGRD ............................................................................. 166  
TRCIC .................................................................................... 96  
TRCIER ............................................................................... 164  
TRCIOR0 ............................................................. 170, 179, 184  
TRCIOR1 ............................................................. 170, 180, 185  
TRCMR ................................................................................ 162  
TRCOER ............................................................................. 169  
TRCSR ................................................................................ 165  
TRECR1 .............................................................................. 203  
TRECR2 .............................................................................. 204  
TRECSR .............................................................................. 204  
TREIC .................................................................................... 95  
TREMIN ............................................................................... 203  
TRESEC .............................................................................. 203  
[ D ]  
DA0 to DA1 ......................................................................... 254  
DACON ............................................................................... 254  
[ F ]  
FMR0 .................................................................................. 273  
FMR1 .................................................................................. 274  
FMR4 .................................................................................. 275  
FRA0 ..................................................................................... 70  
FRA1 ..................................................................................... 70  
FRA2 ..................................................................................... 70  
FRA7 ..................................................................................... 71  
[ I ]  
INT0IC ................................................................................... 97  
INT1IC ................................................................................... 97  
INT3IC ................................................................................... 97  
INTEN ................................................................................. 104  
INTF .................................................................................... 105  
[ K ]  
KIEN .................................................................................... 108  
KUPIC ................................................................................... 95  
[ L ]  
LINCR ................................................................................. 226  
LINST .................................................................................. 227  
[ U ]  
[ O ]  
U0BRG ................................................................................ 210  
U0C0 ................................................................................... 211  
U0C1 ................................................................................... 212  
U0MR .................................................................................. 210  
U0RB ................................................................................... 209  
U0TB ................................................................................... 209  
OCD ...................................................................................... 69  
OFS ....................................................................... 26, 117, 268  
[ P ]  
P1DRR .................................................................................. 51  
PDi (i = 0, 1, and 3 to 5) ........................................................ 48  
Pi (i = 0, 1, and 3 to 5) ........................................................... 49  
PINSR2 ................................................................................. 50  
PINSR3 ................................................................................. 50  
PM0 ....................................................................................... 63  
PM1 ....................................................................................... 63  
PMR .............................................................................. 50, 212  
PRCR .................................................................................... 89  
PUR0 ..................................................................................... 51  
[ V ]  
VCA1 ..................................................................................... 33  
VCA2 ............................................................................... 33, 71  
VW1C .................................................................................... 34  
VW2C .................................................................................... 35  
Rev.1.00 Dec 14, 2007 Page 331 of 332  
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Index  
[ W ]  
WDC .................................................................................... 116  
WDTR ................................................................................. 116  
WDTS .................................................................................. 116  
Rev.1.00 Dec 14, 2007 Page 332 of 332  
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REVISION HISTORY  
R8C/2E Group, R8C/2F Group Hardware Manual  
Description  
Summary  
Rev.  
Date  
Page  
0.01 Nov 17, 2006  
0.03a May 31, 2007  
First Edition issued  
“RENESAS TECHNICAL UPDATE” reflected:  
TN-16C-A164A/E, TN-16C-A167A/E  
25  
26  
Figure 5.3 revised  
Figure 5.4 NOTE1 revised  
5.2 and Figure 5.7 revised  
Figure 6.4; VCA2 register NOTE5 revised  
Table 7.18 revised  
29  
33  
56  
67  
10 revised  
68  
Figure 10.1 revised  
72  
Figure 10.5 FRA1 register revised  
Figure 10.6 NOTE5 revised  
Figure 10.7 added  
73  
74  
79  
10.4.1.3 revised  
83  
10.4.2.5 and Figure 10.10 revised  
Figure 10.11 revised  
85  
87  
10.5.1 revised  
94  
12.1.3.1 revised  
106  
111  
114  
115  
119  
128  
139  
142  
143  
146  
154  
12.2.1 revised  
Table 12.6 revised  
12.6.4 deleted  
Figure 12.19 NOTE2 revised  
Figure 13.3 OFS register NOTE1 revised  
Figure 14.5; “Following conditions” revised  
14.1.6 revised  
Figure 14.14 TRBMR register revised  
Figure 14.15 TRBPR register; NOTE2 revised  
Figure 14.17; “Following conditions” revised  
Table 14.10 revised  
157 to 160 14.2.5.1 to 14.2.5.4 added  
212  
222  
233  
234  
236  
238  
255  
267  
Figure 15.4 U0MR to U1MR Register NOTE2 deleted  
Table 15.5 NOTE2 added  
Figure 16.6 revised  
Figure 16.7; “B0CLR“bit name revised  
Figure 16.9 revised  
Figure 16.11; “BCDCT” flag name revised.  
17.7 revised  
Table 20.2 revised  
C - 1  
REVISION HISTORY  
R8C/2E Group, R8C/2F Group Hardware Manual  
Description  
Summary  
Rev.  
Date  
Page  
271  
272  
274  
275  
276  
278  
280  
281  
283  
284  
286  
288  
303  
313  
314  
316  
0.03a May 31, 2007  
Figure 20.4 NOTE1 revised  
Table 20.3 revised  
20.4.2.4 revised  
20.4.2.15 revised  
Figure 20.5 revised  
Figure 20.7 NOTE5 revised  
Figure 20.9 revised  
Figure 20.11 revised  
20.4.3.4 revised  
Figure 20.13 revised  
Figure 20.15 revised  
Table 20.6; “FRM00 Register” “FRM0 Register” revised  
Table 21.11 revised  
22.2.4 deleted  
Figure 22.1 NOTE2 revised  
22.3.1 revised  
317 to 320 21.3.2.1 to 21.3.2.4 added  
325  
332  
333  
2, 4  
3, 5  
22.6 revised  
Appendix Figure 2.1 NOTE2 deleted  
Appendix Figure 3.1 NOTE1 revised  
Table 1.1 and Table 1.3; “Serial Interface” revised  
0.10 Aug 01, 2007  
Table 1.2 and Table 1.4; revised specifications of “Operating Frequency/  
Supply Voltage” and “Current consumption”  
6
7
Table 1.5 and Figure 1.1; “factory programming product” added  
Table 1.6 and Figure 1.2; “factory programming product” added  
Figure 1.3 “UART or clock synchronous serial I/O (8 bits × 1)” revised  
Figure 1.4 revised  
8
9
10  
11  
15  
16  
18  
Table 1.7 revised  
Table 1.8 revised  
Figure 3.1 revised  
Figure 3.2 revised  
Table 4.2; - 0053h “S1TIC register” deleted,  
- 0054h “S1RIC register” deleted  
19  
Table 4.3; - 00A8h “U1MR register” deleted,  
- 00A9h “U1BRG register” deleted,  
- 00AAh to 00ABh “U1TB register” deleted,  
- 00ACh “U1C0 register” deleted,  
- 00ADh “U1C1 register” deleted,  
- 00AEh to 00AFh “U1RB register” deleted  
20  
Table 4.4; - 00F5h “PINSR1 register” deleted  
C - 2  
REVISION HISTORY  
R8C/2E Group, R8C/2F Group Hardware Manual  
Description  
Summary  
Rev.  
Date  
Page  
29  
43  
44  
50  
52  
53  
59  
60  
65  
66  
77  
0.10 Aug 01, 2007  
Figure 5.7 revised  
Figure 7.1 P1_0 to P1_3 and P1_4 revised  
Figure 7.2 revised  
Figure 7.9 PINSR1 register deleted, Figure 7.10 PMR register revised  
Table 7.4 revised  
Table 7.9 revised  
Table 7.30 and Table 7.31 revised, Table 7.32 revised  
Table 7.33 revised  
Table 10.1 NOTE2 revised  
Figure 10.1 revised  
10.4.1.3 “low-speed clock mode” “low-speed on-chip oscillator mode”  
revised  
94  
95  
Table 12.2 revised  
Figure 12.3 Registers S1TIC and S1RIC deleted  
Figure 12.11 revised  
103  
138  
14.2 “The reload register and counter are allocated at the same  
address.” deleted  
141  
203  
Figure 14.15 “Programmable one-shot generation mode” mode name revised  
Figure 14.64 revised  
207 to 223 15. Serial Interface; “UART1” deleted  
(“UARTi (i = 0 or 1)” “UART0” and “i (i = 0 or 1)” “0” revised)  
Figure 15.1 revised  
207  
208  
209  
210  
Figure 15.2 revised  
Figure 15.3 U1TB register and U1RB register deleted  
Figure 15.4 U1BRG register and U1MR register deleted, U0MR register  
NOTE1 revised  
211  
212  
213  
214  
215  
216  
218  
219  
220  
221  
222  
223  
224  
Figure 15.5 U1C0 register deleted  
Figure 15.6 U1C1 register deleted, Figure 15.7 PMR register revised  
Table 15.1 revised  
Table 15.2 and Table 15.3 revised  
Figure 15.8 revised  
Figure 15.9 and Figure 15.10 revised  
Table 15.4 revised  
Table 15.5 and Table 15.6 revised  
Figure 15.11 revised  
Figure 15.12 revised  
Figure 15.13 revised  
15.3 revised  
Figure 16.1 revised  
C - 3  
REVISION HISTORY  
R8C/2E Group, R8C/2F Group Hardware Manual  
Description  
Summary  
Rev.  
Date  
Page  
229  
230  
233  
236  
294  
296  
297  
298  
299  
301  
304  
305  
308  
320  
327  
329  
0.10 Aug 01, 2007  
Figure 16.5 revised  
Figure 16.6 “Zero to one cycle of” revised  
Figure 16.9 revised  
Figure 16.12 revised  
Table 21.2 revised  
Table 21.5 and Table 21.6 revised  
Table 21.7 revised  
Table 21.8 NOTE4 added  
Table 21.10 and Figure 21.3 revised  
Table 21.14 revised  
Table 21.18 and Figure 21.6 “i (i = 0 or 1)” “0” revised  
Table 21.20 revised  
Table 21.24 and Figure 21.10 “i (i = 0 or 1)” “0” revised  
22.4 “i (i = 0 or 1)” “0” revised  
23 (1) deleted  
Appendix Figure 2.1 NOTE2 added, Appendix Figure 2.2 revised  
1.00 Dec 14, 2007 All pages “Under development” deleted  
2, 4  
6, 7  
Table 1.1 and Table 1.3 “Interrupts” revised  
Table 1.5 and Table 1.6 “(D)” deleted  
15, 16 Figure 3.1 and Figure 3.2 “Expanded area” deleted  
17  
29  
Table 4.1 “002Ch” added  
5.2 “2.5 V” “2.6 V” revised  
Figure 10.1 revised  
66  
71  
Figure 10.6 “FRA7 Register” added  
10.2.2 revised  
74  
75  
10.3.8 added  
79  
Table 10.3 revised  
94  
Table 12.2 revised  
122  
170  
177  
178  
179  
184  
233  
250  
294  
300  
Figure 14.1 “TSTART” “TCSTF” revised  
Figure 14.36 TRCIOR0: b3 revised, NOTE4 added  
14.3.4 and Table 14.16 revised  
Figure 14.42 revised  
Figure 14.43 b3 revised, NOTE3 added  
Figure 14.47 b3 revised  
Figure 16.9 revised  
Figure 17.10 revised  
Table 21.2 IOH(sum) and NOTE2 revised  
Table 21.11 Symbol “fOCO40M”: Parameter added  
C - 4  
R8C/2E Group, R8C/2F Group Hardware Manual  
Publication Date: Rev.0.01 Nov 17, 2006  
Rev.1.00 Dec 14, 2007  
Published by: Sales Strategic Planning Div.  
Renesas Technology Corp.  
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan  
R8C/2E Group, R8C/2F Group  
Hardware Manual  
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan  

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