RD151TS3324ARPH0 [RENESAS]
Spread Spectrum Clock for EMI Solution; 扩频时钟的EMI解决方案
| 型号： | RD151TS3324ARPH0 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Spread Spectrum Clock for EMI Solution |
| 文件： | 总9页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RD151TS3314ARP, RD151TS3324ARP
Spread Spectrum Clock for EMI Solution
REJ03D0795-0100
Rev.1.00
May 11, 2006
Description
RD151TS3314ARP and RD151TS3324ARP is a high-performance Spread Spectrum Clock generator. It is suitable for
EMI solution of electric systems.
Features
•
Supports 20 MHz to 40 MHz operations. Multiple rate (XIN: SSCOUT) = 1: 2
Input frequency 40 MHz to 80 MHz
•
Spread spectrum modulation ; RD151TS3314ARP : ±1.5%, ±0.5% (Central spread modulation)
RD151TS3324ARP : -3.0%, -1.0% (Down spread modulation)
Key Specifications
•
•
•
•
•
Supply voltages: VDD = 3.3 V ±0.3 V
Cycle to cycle jitter = ±100 ps typ.
Clock output duty cycle = 50 ±5%
Output slew rate = 0.7 V/ns typ.
Ordering Information
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
Part Name
Package Type
RD151TS3314ARPH0
RD151TS3324ARPH0
SOP-8 pin
(JEDEC)
PRSP0008DD-C
(FP-8DCV)
RP
H (2,500 pcs / Reel)
Block Diagram
VDD
GND
NC
XIN
1/M
OSC
R = 1 MΩ
Synthesizer
1/N
SSCOUT
XOUT
SSC Modulator
Mode Control
SEL
SSN
R = 350 kΩ
R = 350 kΩ
Rev.1.00 May 11, 2006 page 1 of 8
RD151TS3314ARP, RD151TS3324ARP
Pin Arrangement
1
2
3
4
XIN
XOUT
NC
8
7
6
5
VDD
SEL
SSCOUT
GND
SSN
(Top view)
Pin Descriptions
Pin name
GND
No.
Type
Description
5
8
3
6
1
2
7
Ground
Power
NC
GND pin
Power supply pin.
VDD
NC
Don’t connect any VDD or GND.
Spread spectrum modulated clock output.
Oscillator input.
SSCOUT
XIN
Output
Input
XOUT
SEL
Output
Input
Oscillator output.
SSC% mode select pin. LVCMOS level input.
Pull-down by internal resistor (350 kΩ).
SSN
4
Input
SSC ON/OFF select pin. LVCMOS level input.
Pull–down by internal resistor (350 kΩ).
SSC Function Table
STB
SEL
RD151TS3314ARP(Central spread)
RD151TS3324ARP(Down spread)
0
0
1
1
0
1
0
1
±1.5%*1
–3.0%*1
±0.5%
–1.0%
OFF
OFF
Note: 1. ±1.5%(TS3314ARP) / -3.0%(TS3324ARP) SSC is selected for default by internal pull-down resistors.
Clock Frequency Table
PRODUCT
XIN(MHz)
20 to 40
20 to 40
SSCOUT(MHz)
40 to 80
Multiply rate (XIN: SSCOUT)
RD151TS3314ARP
RD151TS3324ARP
1:2
1:2
40 to 80
Rev.1.00 May 11, 2006 page 2 of 8
RD151TS3314ARP, RD151TS3324ARP
Absolute Maximum Ratings
Item
Supply voltage
Symbol
VDD
VI
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to VDD+0.5
–50
Unit
V
Conditions
Input voltage
Output voltage *1
V
VO
V
Input clamp current
Output clamp current
Continuous output current
Maximum power dissipation
Storage temperature
IIK
mA
mA
mA
W
VI < 0
IOK
–50
VO < 0
IO
±50
VO = 0 to VDD
0.7
Ta = 55°C (in still air)
Tstg
–65 to +150
°C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Symbol
Min
3.0
Typ
3.3
—
Max
3.6
Unit
V
Conditions
Supply voltage
VDD
DC input signal voltage
High level input voltage
Low level input voltage
Input clock duty cycle
Operating temperature
–0.3
0.7×VDD
–0.3
45
VDD+0.3
VDD+0.3
0.3×VDD
55
V
VIH
VIL
—
V
—
V
50
—
%
°C
–20
85
DC Electrical Characteristics
Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V
Item
Input current
Symbol
Min
Typ
Max
Unit
Test Conditions
II
—
—
±20
±100
—
µA
VI = 0 V or 3.6 V, VDD = 3.6 V,
XIN pin
—
—
—
3
VI = 0 V or 3.6 V, VDD = 3.6 V,
SEL, SSN pins
Input capacitance
CI
pF
SEL, SSN pins
DC Electrical Characteristics / SSC Clock Output
Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V
Test Conditions
Item
Symbol
VOH
Min
VDD-0.2
—
Typ
—
Max
—
Unit
Output voltage
V
IOH = –1 mA
VOL
—
200
—
mV IOL = 1 mA
mA VOH = 1.5 V, VDD = 3.3 V
VOL = 1.5 V, VDD = 3.3 V
Ω
Output current
IOH
—
–19
19
IOL
—
—
Output impedance
—
40
—
Notes: Parameters are target of design. Not 100% tested in production.
Rev.1.00 May 11, 2006 page 3 of 8
RD151TS3314ARP, RD151TS3324ARP
AC Electrical Characteristics / SSC Clock Output
Ta = 25°C, VDD = 3.3 V, CL = 15 pF
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Notes
Operating current
IDD
—
16
22
mA
VDD = 3.3 V, CL = 15 pF,
XIN = 40 MHz
Cycle to cycle jitter *1
Slew rate
tCCS
—
—
|100|
0.8
—
ps
SEL = 0, CL = 0 pF
Figure 1
SSC = ±1.5% (TS3314ARP)
SSC = –3.0% (TS3324ARP)
tSL
4.0
V/ns VDD = 3.3 V,
0.2 × VDD to 0.8 × VDD
Clock duty cycle
45
—
50
—
55
2
%
Stabilization time *2
ms
Notes: Parameters are target of design. Not 100% tested in production.
1. Cycle to cycle jitter is included spread spectrum modulation.
2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
SSCOUT
tcycle n
tcycle n+1
tCCS = (tcycle n)
– (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.1.00 May 11, 2006 page 4 of 8
RD151TS3314ARP, RD151TS3324ARP
Application Information
1. Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 2.
VDD decoupling is important to both reduce Jitter and EMI radiation.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
VDD
1
2
3
4
XIN
(Crystal or Reference input)
8
7
6
5
C1 C2
XOUT
(Crystal or Not connection)
SEL
GND GND
R1
NC
SSCOUT
SSN
GND
Notes:
C1 = High frequency supply decoupling capacitor.
(0.1 µF recommended)
C2 = Low frequency supply decoupling capacitor.
(22 µF recommended)
R1 = Match value to line impedance.
Figure 2 Recommended circuit configuration
Rev.1.00 May 11, 2006 page 5 of 8
RD151TS3314ARP, RD151TS3324ARP
2. Example Board Layout Configuration
VDD
(+3.3V Supply)
P
FB
22 µF
G
0.1 µF
Crystal connection
or Reference input
1
2
3
4
G
Crystal connection
or No connection
7
6
5
R1
SSCOUT
G
G
Note:
Via to GND plane
R1 = Match value to line impedance.
FB = Ferrite bead.
Figure 3 Example Board Layout
Rev.1.00 May 11, 2006 page 6 of 8
RD151TS3314ARP, RD151TS3324ARP
3. Example of TS33XX EMI Solution IC’s Application
Spread Spectrum
Modulated Clock
XTAL
Memory
Graphics
XIN
CPU & ASIC
TS33XXA
XOUT
SSCOUT
System Cont.
Ref.
Clock
3.3 V CMOS level ref. Clock
Figure 4 Ref. Clock Input Example
Spread Spectrum
Modulated Clock
Memory
Graphics
XIN
CPU & ASIC
SSCOUT
TS33XXA
XTAL
XOUT
System Cont.
Figure 5 XTAL Ref. Clock Input Example
Rev.1.00 May 11, 2006 page 7 of 8
RD151TS3314ARP, RD151TS3324ARP
Package Dimensions
JEITA Package Code
P-SOP8-3.95x4.9-1.27
RENESAS Code
PRSP0008DD-C
Previous Code
FP-8DCV
MASS[Typ.]
0.085g
*1
F
D
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
8
5
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Reference
Symbol
1
4
*3
Min Nom Max
e
Z
bp
x
M
D
E
4.90 5.30
3.95
L1
A2
A1
A
bp
b1
c
0.10 0.14 0.25
1.75
0.34 0.40 0.46
0.15 0.20 0.25
L
c1
θ
y
0° 8°
5.80 6.10 6.20
Detail F
HE
e
x
1.27
0.25
0.10
y
Z
L
L1
0.75
0.40 0.60 1.27
1.08
Rev.1.00 May 11, 2006 page 8 of 8
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