RJE0615JSP-00-J3 [RENESAS]
Silicon P Channel MOS FET Series Power Switching; 硅P沟道MOS FET系列电源开关
| 型号： | RJE0615JSP-00-J3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Silicon P Channel MOS FET Series Power Switching |
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Datasheet
RJE0615JSP
Silicon P Channel MOS FET Series
Power Switching
R07DS0124EJ0200
(Previous: REJ03G1943-0100)
Rev.2.00
Sep 01, 2010
Description
This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in
over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of
high junction temperature like applying over power consumption, over current etc..
Features
Built-in the over temperature shut-down circuit.
High endurance capability against to the short circuit.
Latch type shut down operation (need 0 voltage recovery).
Built-in the current limitation circuit.
Low on-resistance RDS(on) : 53 m Typ, 65 m Max (VGS = –10 V)
High density mounting
Outline
RENESAS Package code: PRSP0008DD-D
(Package name: SOP-8)
5
6
D
D
D
D
7
8
5
6
7
8
4
3
2
1
1, 2, 3
4
5, 6, 7, 8
Source
Gate
Drain
4
Current
Limitation
Circuit
G
Gate Resistor
Temperature
Sensing
Circuit
Gate
Shut-down
Circuit
Latch
Circuit
1
2
3
S
S
S
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Symbol
VDSS
VGSS
Ratings
–60
–16
Unit
V
V
VGSS
ID
2.5
–10
V
A
Note3
Drain current
Body-drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
Channel temperature
Storage temperature
IDR
–10
A
A
mJ
W
C
C
Note 2
IAP
EAR
–4.7
94.7
2.5
Note 2
Pch Note 1
Tch
150
–55 to +150
Tstg
Notes: 1 1 Drive operation: When using the glass epoxy board (FR4 40 40 1.6 mm), PW 10 s
2. Tch = 25C, Rg 50
3. It provides by the current limitation lower bound value.
R07DS0124EJ0200 Rev.2.00
Sep 01, 2010
Page 1 of 7
RJE0615JSP
Preliminary
Typical Operation Characteristics
(Ta = 25°C)
Item
Symbol
VIH
Min
–3.5
—
Typ
—
Max
—
Unit
V
Test Conditions
Input voltage
Input current
VIL
—
–1.2
–100
–50
–10
—
V
IIH1
—
—
A
A
A
mA
mA
C
Vi = –8 V, VDS = 0
(Gate non shut down)
IIH2
—
—
Vi = –3.5 V, VDS = 0
Vi = –1.2 V, VDS = 0
Vi = –8 V, VDS = 0
Vi = –3.5 V, VDS = 0
IIL
—
—
Input current
IIH(sd)1
IIH(sd)2
Tsd
—
–0.8
–0.35
175
(Gate shut down)
—
—
Shut down temperature
—
—
Channel temperature
(dv/dt VGS 500 V/ms)
Gate operation voltage
Vop
–3.5
–10
—
—
–12
—
V
A
Drain current
ID limt
VGS = –12 V, VDS = –10 V Note 4
(Current limitation value)
Notes; 4. Pulse test
Electrical Characteristics
(Ta = 25°C)
Item
Symbol
ID1
Min
—
Typ
—
Max
–4
Unit
Test Conditions
VGS = –3.5 V, VDS = –10 V
VGS = –1.2 V, VDS = –10 V
VGS = –12 V, VDS = –10 V Note 5
ID = –10 mA, VGS = 0
Drain current
A
mA
A
ID2
—
—
–10
—
ID3
–10
–60
—
Drain to source breakdown
voltage
V(BR)DSS
—
—
V
Gate to source breakdown
voltage
V(BR)GSS
V(BR)GSS
IGSS1
–16
2.5
—
—
—
—
—
V
IG = –800 A, VDS = 0
IG = 100 A, VDS = 0
VGS = –8 V, VDS = 0
VGS = –3.5 V, VDS = 0
VGS = –1.2 V, VDS = 0
VGS = 2.4 V, VDS = 0
VGS = –8 V, VDS = 0
VGS = –3.5 V, VDS = 0
VDS = –60 V, VGS = 0
V
Gate to source leak current
—
–100
–50
–10
100
—
A
A
A
A
mA
mA
A
A
IGSS2
—
—
IGSS3
—
—
IGSS4
—
—
Input current (shut down)
IGS(OP)1
IGS(OP)2
IDSS1
—
–0.8
–0.35
—
—
—
Zero gate voltage drain current
Zero gate voltage drain current
—
–10
–10
IDSS2
—
—
VDS = –48 V, VGS = 0,
Ta = 125C
Gate to source cutoff voltage
VGS(off)
RDS(on)
RDS(on)
Coss
td(on)
tr
–2.2
—
—
70
–3.4
95
65
—
V
m
m
pF
s
s
s
s
V
VDS = –10 V, ID = –1 mA
ID = –5 A, VGS = –6 V Note 5
ID = –5 A, VGS = –10 V Note 5
VDS = –10 V, VGS = 0, f = 1MHz
VGS = –10 V, ID= –5 A,
RL = 6
Static drain to source on state
resistance
—
53
Output capacitance
Turn-on delay time
Rise time
—
356
4.4
4.5
2.0
1.6
–0.87
—
—
—
—
Turn-off delay time
Fall time
td(off)
tf
—
—
—
—
Body-drain diode forward
voltage
VDF
—
—
IF = –10 A, VGS = 0
Body-drain diode reverse
recovery time
trr
—
—
90
—
—
ns
IF = –10 A, VGS = 0
diF/dt = 50 A/s
Over load shut down
operation time Note 6
tos1
2.6
ms
VGS = –6 V, VDD = –16 V
Notes: 5. Pulse test
6. Including the junction temperature rise of the over loaded condition.
R07DS0124EJ0200 Rev.2.00
Sep 01, 2010
Page 2 of 7
RJE0615JSP
Preliminary
Main Characteristics
Power vs. Temperature Derating
Maximum Safe Operation Area
100
10
4.0
3.0
2.0
1.0
0
Ta = 25°C
Thermal shut down operation area
Test condition.
When using the glass epoxy board.
(FR4 40 x 40 x 1.6 mm), (PW ≤ 10s)
1
0.1
Operation
in this area
is limited RDS(on)
0.01
−0.01
0
50
100
150
200
−0.1
−1
−10
−100
Drain to Source Voltage VDS (V)
Case Temperature Tc (°C)
Note 7:
When using the glass epoxy board.
(FR4 40 x 40 x 1.6 mm)
Typical Output Characteristics
Typical Transfer Characteristics
−10
−8
−10
−8
−10 V
−7 V
−40°C
Tc = 150°C
25°C
−6 V
−5.5 V
−4.5 V
−5 V
V
DS = −10 V
Pulse Test
−6
−6
−4
−4
Tc = 150°C
25°C
V
GS = −4 V
−2
−2
−40°C
−6
Pulse Test
−8 −10
0
0
−2
−4
−8
−2
−4
−6
Drain to Source Voltage VDS (V)
Gate to Source Voltage VGS (V)
Drain Source Saturation Voltage vs.
Gate to Source Voltage
Static Drain to Source On State Resistance
vs. Drain Current
1000
−1000
−500
−0
Pulse Test
Pulse Test
500
200
100
50
VGS = −6 V
ID = −5 A
−2 A
−10 V
−1 A
20
10
−2 −4 −6 −8 −10 −12 −14 −16
−0.1 −0.2
−0.5 −1 −2
−5 −10
Gate to Source Voltage VGS (V)
Drain Current ID (A)
R07DS0124EJ0200 Rev.2.00
Sep 01, 2010
Page 3 of 7
RJE0615JSP
Preliminary
Body-Drain Diode Reverse
Recovery Time
Static Drain to Source On State Resistance
vs. Temperature
1000
150
125
100
Pulse Test
I
D = −5 A
−1 A, −2 A
VGS = −6 V
75
50
100
−2 A, −5 A
−1 A
VGS = −10 V
25
0
di / dt = 50 A / μs
V
GS = 0, Ta = 25°C
10
−0.1
−50 −25
0
25 50 75 100 125 150
−1 −10
Case Temperature Tc (°C)
Reverse Drain Current IDR (A)
Reverse Drain Current vs.
Source to Drain Voltage
Switching Characteristics
−10
−8
10
Pulse Test
t
r
t
VGS = −5 V
d(on)
−6
VGS = 0 V, 5 V
t
−4
d(off)
t
f
−2
V
GS = −10 V, VDD = −30 V
PW = 300 μs, duty ≤ 1 %
1
−0.1
0
−0.4
−0.8
−1.2
−1.6
−2.0
−1
Drain Current ID (A)
−10
Source to Drain Voltage VSD (V)
Gate to Source Voltage vs.
Shutdown Time of Load-Short Test
Typical Capacitance vs.
Drain to Source Voltage
10000
1000
100
−16
−14
VGS = 0
f = 1 MHz
−12
−10
−8
VDD = −16 V
−6
−4
−2
0
10
1
10
100
0
−10 −20 −30 −40 −50 −60
Shutdown Time of Load-Short Test Pw (ms)
Drain to Source Voltage VDS (V)
R07DS0124EJ0200 Rev.2.00
Sep 01, 2010
Page 4 of 7
RJE0615JSP
Preliminary
Shutdown Case Temperature vs.
Gate to Source Voltage
200
180
160
140
ID = −1 A
dv / dt
120
100
V
GS ≥ 500 V/ ms
−6 −8
Gate to Source Voltage VGS (V)
0
−2
−4
−10
Normalized Transient Thermal Impedance vs. Pulse Width
10
D = 1
0.5
1
0.1
0.1
θch − f(t) = γs (t) • θch − f
θch − f = 83.3°C/W, Ta = 25°C
When using the glass epoxy board
(FR4 40 × 40 × 1.6 mm)
0.01
PW
T
P
DM
D =
PW
T
0.001
1 m
10 m 100 m
1
10
100
1000
10000
100 μ
Pulse Width PW (S)
Avalanche Test Circuit
Avalanche Waveform
VDSS
VDSS – VDD
1
2
2
L
EAR
=
• L • IAP •
VDS
Monitor
IAP
Monitor
V(BR)DSS
IAP
Rg
VDD
D.U.T
VDS
ID
Vin
–10 V
50 Ω
VDD
0
R07DS0124EJ0200 Rev.2.00
Sep 01, 2010
Page 5 of 7
RJE0615JSP
Preliminary
Switching Time Test Circuit
Switching Time Waveform
10%
Vout
Monitor
Vin
Vin Monitor
D.U.T.
RL
90%
90%
VDD
= –30 V
Vin
–10 V
90%
50 Ω
10%
10%
Vout
t
t
t
f
t
d(off)
d(on)
r
R07DS0124EJ0200 Rev.2.00
Sep 01, 2010
Page 6 of 7
RJE0615JSP
Preliminary
Package Dimensions
Package Name
SOP-8
JEITA Package Code
RENESAS Code
PRSP0008DD-D
Previous Code
FP-8DAV
MASS[Typ.]
0.085g
P-SOP8-3.95 × 4.9-1.27
1
D
*
bp
5
8
1
Index mark
NOTE)
4
Terminal cross section
(Ni/Pd/Au plating)
1. DIMENSIONS "*1(Nom)" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Z
3
bp
*
M
x
e
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
4.90
3.95
5.3
L1
A2
A1
A
0.10
0.14 0.25
1.75
bp
b1
c
0.34 0.40 0.46
0.15 0.20 0.25
c1
L
0°
8°
y
HE
e
5.80 6.10 6.20
Detail F
1.27
x
0.25
y
Z
0.1
0.75
L
L1
0.40 0.60 1.27
1.08
Ordering Information
Part No.
Quantity
Shipping Container
RJE0615JSP-00-J3
2500 pcs
Taping
R07DS0124EJ0200 Rev.2.00
Sep 01, 2010
Page 7 of 7
Notice
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