RMLV0808BGSB-4S2 [RENESAS]
STANDARD SRAM;
| 型号： | RMLV0808BGSB-4S2 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | STANDARD SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RMLV0808BGSB - 4S2
8Mb Advanced LPSRAM (1024k word × 8bit)
R10DS0232EJ0200
Rev.2.00
2015.06.26
Description
The RMLV0808BGSB is a family of 8-Mbit static RAMs organized 1,048,576-word × 8-bit, fabricated by Renesas’s
high-performance Advanced LPSRAM technologies. The RMLV0808BGSB has realized higher density, higher
performance and low power consumption. The RMLV0808BGSB offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 44pin TSOP (II).
Features
Single 3V supply: 2.4V to 3.6V
Access time:
── Power supply voltage from 2.7V to 3.6V: 45ns (max.)
── Power supply voltage from 2.4V to 2.7V: 55ns (max.)
Current consumption:
── Standby: 0.45µA (typ.)
Equal access and cycle times
Common data input and output
── Three state output
Directly TTL compatible
── All inputs and outputs
Battery backup operation
Part Name Information
Temperature
Range
Part Name
Power supply
Access time
Package
2.7V to 3.6V
2.4V to 2.7V
45 ns
55 ns
RMLV0808BGSB-4S2
-40 ~ +85°C 11.76mm×18.41mm 44pin plastic TSOP(II)
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RMLV0808BGSB - 4S2
Pin Arrangement
44pin TSOP(II)
A4
A3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
1
2
A6
A2
A7
3
A1
OE#
CS2
A8
4
A0
5
CS1#
NC
6
NC
7
NC
NC
8
DQ0
DQ1
Vcc
Vss
DQ2
DQ3
NC
DQ7
DQ6
Vss
Vcc
DQ5
DQ4
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
WE#
A19
A18
A17
A16
A15
A9
A10
A11
A12
A13
A14
(Top view)
Pin Description
Pin name
Function
VCC
Power supply
Ground
VSS
A0 to A19
DQ0 to DQ7
CS1#
CS2
Address input
Data input/output
Chip select 1
Chip select 2
Output enable
Write enable
OE#
WE#
NC
No connection
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RMLV0808BGSB - 4S2
Block Diagram
A0
A1
MEMORY ARRAY
1024k-word x8-bit
ROW
ADDRESS
BUFFER
DECODER
A19
DQ0
DQ1
DQ
BUFFER
SENSE / WRITE AMPLIFIER
COLUMN DECODER
DQ7
CLOCK
GENERATOR
Vcc
Vss
WE#
CS1#
CS2
OE#
Operation Table
CS1#
CS2
X
WE#
X
OE#
X
DQ0~7
High-Z
High-Z
Din
Operation
H
X
L
L
L
Stand-by
Stand-by
Write
L
X
X
H
L
X
H
H
L
Dout
Read
H
H
H
High-Z
Output disable
Note 1. H: VIH L:VIL
X: VIH or VIL
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RMLV0808BGSB - 4S2
Absolute Maximum Ratings
Parameter
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
Symbol
VCC
Value
-0.5 to +4.6
-0.5*2 to VCC+0.3*3
0.7
unit
V
VT
V
PT
W
°C
°C
°C
Operation temperature
Topr
Tstg
Tbias
-40 to +85
-65 to +150
-40 to +85
Storage temperature range
Storage temperature range under bias
Note 2. -3.0V for pulse ≤ 30ns (full width at half maximum)
3. Maximum voltage is +4.6V.
DC Operating Conditions
Parameter
Supply voltage
Symbol
VCC
Min.
2.4
0
Typ.
3.0
0
Max.
Unit
V
Test conditions
Note
3.6
0
VSS
V
2.0
2.2
-0.2
-0.2
-40
─
VCC+0.2
VCC+0.2
0.4
V
Vcc=2.4V to 2.7V
Vcc=2.7V to 3.6V
Vcc=2.4V to 2.7V
Vcc=2.7V to 3.6V
Input high voltage
VIH
─
V
─
V
4
4
Input low voltage
VIL
Ta
─
0.6
V
Ambient temperature range
─
+85
°C
Note 4. -3.0V for pulse ≤ 30ns (full width at half maximum)
DC Characteristics
Parameter
Symbol
| ILI |
Min.
Typ.
Max.
1
Unit
Test conditions
Input leakage current
Output leakage current
─
─
A
Vin = VSS to VCC
CS1# = VIH or CS2 = VIL or OE# = VIH
or WE# = VIL , VI/O = VSS to VCC
| ILO
|
─
─
─
─
1
A
Average operating current
Cycle = 55ns, duty =100%, II/O = 0mA,
CS1# = VIL, CS2 = VIH, Others = VIH/VIL
Cycle = 45ns, duty =100%, II/O = 0mA,
CS1# = VIL, CS2 = VIH, Others = VIH/VIL
Cycle = 1s, duty =100%, II/O = 0mA,
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V,
20*5
25*5
25
30
mA
mA
ICC1
ICC2
ISB
─
1.5*5
3
mA
VIH ≥ VCC-0.2V, VIL ≤ 0.2V
Standby current
Standby current
─
─
─
0.3
2
mA
CS2 = VIL, Others = VSS to VCC
0.45*5
A
~+25°C
Vin = VSS to VCC,
~+40°C
─
─
─
0.6*6
─
4
7
A
A
A
(1) CS2 ≤ 0.2V or
ISB1
(2) CS1# ≥ VCC-0.2V,
~+70°C
CS2 ≥ VCC-0.2V
─
10
~+85°C
Output high voltage
Output low voltage
IOH = -1mA
Vcc≥2.7V
VOH
2.4
2.0
─
─
─
─
─
─
─
V
V
V
V
VOH2
VOL
IOH = -0.1mA
I
OL = 2mA
0.4
Vcc≥2.7V
VOL2
─
0.4
IOL = 0.1mA
Note 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
Note 6. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
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RMLV0808BGSB - 4S2
Capacitance
(Ta =25°C, f =1MHz)
Parameter
Input capacitance
Symbol
C in
Min.
─
Typ.
─
Max.
8
Unit
pF
Test conditions
Note
Vin =0V
VI/O =0V
7
7
Input / output capacitance
C I/O
─
─
10
pF
Note 7. This parameter is sampled and not 100% tested.
AC Characteristics
Test Conditions (Vcc = 2.4V ~ 3.6V, Ta = -40 ~ +85°C)
1.4V
Input pulse levels:
VIL = 0.4V, VIH = 2.4V (Vcc=2.7V to 3.6V)
VIL = 0.4V, VIH = 2.2V (Vcc=2.4V to 2.7V)
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
RL = 500 ohm
DQ
CL = 30 pF
Read Cycle
Vcc=2.7V to 3.6V
Vcc=2.4V to 2.7V
Parameter
Symbol
Unit
Note
Min.
45
─
Max.
─
Min.
55
─
Max.
─
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
45
45
45
22
─
55
55
55
30
─
tACS1
tACS2
tOE
─
─
Chip select access time
─
─
Output enable to output valid
─
─
Output hold from address change
tOH
10
10
10
5
10
10
10
5
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
─
─
8,9
8,9
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
─
─
─
─
8,9
0
18
18
18
0
20
20
20
8,9,10
8,9,10
8,9,10
0
0
0
0
Note 8. This parameter is sampled and not 100% tested.
9. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2
min, and tOHZ max is less than tOLZ min, for any device.
10. tCHZ1, tCHZ2 and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not
referred to the DQ levels.
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RMLV0808BGSB - 4S2
Write Cycle
Vcc=2.7V to 3.6V
Vcc=2.4V to 2.7V
Parameter
Symbol
Unit
Note
11
Min.
45
35
35
35
0
Max.
─
Min.
55
50
50
40
0
Max.
─
Write cycle time
tWC
tAW
tCW
tWP
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to write end
Chip select to write end
─
─
─
─
Write pulse width
─
─
Address setup time to write start
Write recovery time from write end
Data to write time overlap
Data hold from write end
Output enable from write end
Output disable to output in high-Z
Write to output in high-Z
─
─
tWR
tDW
tDH
0
─
0
─
25
0
─
25
0
─
─
─
tOW
tOHZ
tWHZ
5
─
5
─
12
0
18
18
0
20
20
12,13
12,13
0
0
Note 11. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (WE#) and (CS2) become active.
A write is performed during the overlap of a low CS1#, a low WE# and a high CS2.
A write ends when any of (CS1#), (WE#) or (CS2) becomes inactive.
12. This parameter is sampled and not 100% tested.
13. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
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RMLV0808BGSB - 4S2
Timing Waveforms
Read Cycle
tRC
A0~19
CS1#
CS2
Valid address
tAA
tACS1
*15,16
*14,15,16
*14,15,16
*14,15,16
tCLZ1
tCHZ1
tACS2
*15,16
tCLZ2
tCHZ2
VIH
WE#
WE# = “H” level
tOHZ
tOE
OE#
*15,16
tOLZ
tOH
High impedance
DQ0~7
Valid Data
Note 14. tCHZ1, tCHZ2 and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not
referred to the DQ levels.
15. This parameter is sampled and not 100% tested
16. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2
min, and tOHZ max is less than tOLZ min, for any device.
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RMLV0808BGSB - 4S2
Write Cycle (1) (WE# CLOCK, OE#=”H” while writing)
tWC
Valid address
A0~19
tCW
CS1#
CS2
tCW
tAW
tWR
*17
tWP
WE#
OE#
tAS
*18,19
tWHZ
*18,19
tOHZ
tDW
tDH
DQ0~7
Valid Data
*20
Note 17. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (WE#) and (CS2) become active.
A write is performed during the overlap of a low CS1#, a low WE# and a high CS2.
A write ends when any of (CS1#), (WE#) or (CS2) becomes inactive.
18. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
19. This parameter is sampled and not 100% tested
20. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
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RMLV0808BGSB - 4S2
Write Cycle (2) (WE# CLOCK, OE# Low Fixed)
tWC
Valid address
A0~19
tCW
CS1#
CS2
tCW
tAW
tWR
*21
tWP
WE#
tAS
OE#
VIL
OE# = “L” level
*22,23
tWHZ
tOW
Valid Data
tDH
*24
*24
DQ0~7
tDW
Note 21. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (WE#) and (CS2) become active.
A write is performed during the overlap of a low CS1#, a low WE# and a high CS2.
A write ends when any of (CS1#), (WE#) or (CS2) becomes inactive.
22. tWHZ is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ
levels.
23. This parameter is sampled and not 100% tested.
24. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
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RMLV0808BGSB - 4S2
Write Cycle (3) (CS1#, CS2 CLOCK)
tWC
Valid address
A0~19
tAW
tAS
tWR
tCW
CS1#
CS2
tAS
tCW
*25
tWP
WE#
OE#
OE# = “H” level
VIH
tDW
tDH
Valid Data
DQ0~7
Note 25. tWP is the interval between write start and write end.
A write starts when all of (CS1#), (WE#) and (CS2) become active.
A write is performed during the overlap of a low CS1#, a low WE# and a high CS2.
A write ends when any of (CS1#), (WE#) or (CS2) becomes inactive.
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RMLV0808BGSB - 4S2
Low VCC Data Retention Characteristics
Parameter
Symbol Min.
Typ.
Max. Unit
Test conditions*28
Vin ≥ 0V,
VCC for data retention
VDR
1.5
─
3.6
V
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V
─
─
─
─
0.45*26
0.6*27
─
2
4
A
A
A
A
~+25°C
V
CC = 3.0V, Vin ≥ 0V,
~+40°C
~+70°C
~+85°C
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V
Data retention current
ICCDR
7
─
10
Chip deselect time to data retention
Operation recovery time
tCDR
tR
0
5
─
─
─
─
ns
See retention waveform.
ms
Note 26. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
27. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
28. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and DQ buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1#
controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V. The other inputs levels (address,
WE#, OE#, DQ) can be in the high-impedance state.
Low Vcc Data Retention Timing Waveforms (CS1# controlled)
CS1# Controlled
VCC
2.4V
2.4V
tCDR
tR
VDR
2.0V
2.0V
CS1# ≥ VCC - 0.2V
CS1#
Low Vcc Data Retention Timing Waveforms (CS2 controlled)
CS2 Controlled
VCC
2.4V
2.4V
tCDR
tR
CS2
VDR
0.4V
0.4V
CS2 ≤ 0.2V
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Revision History
RMLV0808BGSB Data Sheet
Description
Summary
Rev.
1.00
2.00
Date
Page
─
2014.11.28
2015.06.26
First Edition issued
P.1, 4
P.2
Standby current ISB1 : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.)
Modefy Pin Arrangement : Add 1pin Mark
P.4
Average operating current ICC2 : 25°C 2mA ->1.5mA (typ.)
P.11
Data retention current ICCDR : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.)
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Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HALII Stage, Indiranagar, Bangalore, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2015 Renesas Electronics Corporation. All rights reserved.
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