RNA51958APT0 [RENESAS]
Voltage Detecting, System Resetting IC Series; 电压检测,设备重新启动IC系列![RNA51958APT0](http://pdffile.icpdf.com/pdf1/p00143/img/icpdf/RNA51_793509_icpdf.jpg)
型号: | RNA51958APT0 |
厂家: | ![]() |
描述: | Voltage Detecting, System Resetting IC Series |
文件: | 总14页 (文件大小:124K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Preliminary Datasheet
RNA51958A, B
Voltage Detecting, System Resetting IC Series
REJ03D0915-0302
Rev.3.02
Apr 01, 2010
Description
RNA51958A,B are semiconductor integrated circuits for resetting of all types of logic circuits such as CPUs, and has
the feature of setting the detection voltage by adding external resistance.
They include a built-in delay circuit to provide the desired retardation time simply by adding an external capacitor.
They fined extensive applications, including battery checking circuit, level detecting circuit and waveform shaping
circuit.
Features
Few external parts
Large delay time with a capacitor of small capacitance (td 100 ms, at 0.33 F)
Wide supply voltage range: 2 V to 17 V
Wide application range
Ordering Information
Taping Abbreviation
Package
Abbreviation
Surface
Treatment
Part Name
Package Type
Package Code
(Quantity)
RNA51958AFPH0
RNA51958APT0
RNA51958BFPH0
RNA51958BPT0
SOP-8 pin
DIP-8 pin
SOP-8 pin
DIP-8 pin
PRSP0008DE-C
PRDP0008AF-B
PRSP0008DE-C
PRDP0008AF-B
FP
P
H (2,500 pcs / Reel)
T (1,000 pcs / Reel)
H (2,500 pcs / Reel)
T (1,000 pcs / Reel)
0 (Ni/Pd/Au)
0 (Ni/Pd/Au)
0 (Ni/Pd/Au)
0 (Ni/Pd/Au)
FP
P
Application
Reset circuit of Pch, Nch, CMOS, microcomputer, CPU and MCU, Reset of logic circuit, Battery check circuit,
switching circuit back-up voltage, level detecting circuit, waveform shaping circuit, delay waveform generating
circuit, DC/DC converter, over voltage protection circuit
Recommended Operating Condition
Supply voltage range: 2 V to 17 V
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 1 of 13
RNA51958A, B
Preliminary
Outline and Article Indication
• RNA51958A, B
Part No.
Lot No.
R 9 5 8 A
R 9 5 8 B
YMWC
CCC
YMWC
CCC
Y: Year Code
(the last digit of year)
M: Month Code
W: Week Code
C: Control Code
SOP-8
Pin No.1
Trace Code
Part No.
R 5 1 9 5 8 A
R 5 1 9 5 8 B
Y M W
Y M W
DIP-8
W: Week Code
M: Month Code
Y: Year Code
Pin Arrangement
RNA51958A, B
NC
Input
NC
1
2
3
4
8
7
6
5
NC
Power-supply
Output
GND
Delay capacitor
(Top view)
NC: No Connection
Outline: PRSP0008DE-C (SOP-8)
PRDP0008AF-B (DIP-8)
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 2 of 13
RNA51958A, B
Preliminary
Block Diagram
RNA51958A, B
Power-
supply
A: Built-in Load
B: Open Collector
5 μA
Typ
25 μA
Typ
Output
–
+
Input
+
1.25 V
GND
Delay capacitor
Operating Waveform
RNA51958A, B
1.25 V
t
t
H
L
td
td
td ≈ 0.34 × Cd(pF) μs
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 3 of 13
RNA51958A, B
Preliminary
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item
Symbol
VCC
Ratings
Unit
V
Conditions
Supply voltage
Output sink current
18
6
Isink
mA
VCC
Type A (output with constant current load)
Output voltage
VO
Pd
K
V
18
Type B (open collector output)
8-pin SOP (PRSP0008DE-C)
8-pin DIP (PRDP0008AF-B)
8-pin SOP (PRSP0008DE-C)
8-pin DIP (PRDP0008AF-B)
400
Power dissipation
Thermal derating
mW
570
4.4
Refer to the thermal
derating curve.
mW/°C
8.3
Operating temperature Topr
–40 to +85
–55 to +125
–0.3 to VCC
–0.3 to +7
°C
°C
Storage temperature
Tstg
VCC 7 V
Input voltage range
VIN
V
VCC > 7 V
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
“H” reset type
Item
Symbol
VS
Min
Typ
Max
Unit
V
Test Conditions
Detecting voltage
Hysteresis voltage
1.20
9
1.25
15
1.30
23
VS
mV
VCC = 5V
Detecting voltage
VS/T
VCC
Vin
Iin
—
0.01
—
%/°C
V
temperature coefficient
Supply voltage range
Input voltage range
Input current
2
–0.3
–0.3
—
—
—
17
VCC
7.0
500
590
540
7.0
–3
VCC 7V
V
—
VCC > 7V
100
390
360
3.4
–5
nA
A
Vin = 1.25V
Type A, VCC = 5V
Type B, VCC = 5V
Cd = 0.01F *
VCC = 5V
—
Circuit current
ICC
—
Delay time
tpd
1.6
–8
ms
Constant current
Ipd
A
Output saturation
voltage
Vsat
IOH
—
0.2
0.4
30
V
VCC = 5V, Vin < 1.35V, Isink = 4mA
Output leakage
current
—
—
nA
Type B
Output load current
Output high voltage
IOC
–40
–25
–17
—
A
Type A, VCC = 5V, VO = 1/2 VCC
VOH
VCC–0.2 VCC–0.06
V
Type A
Note: Please set the desired delay time by attaching capacitor of the range between 4700 pF and 10 F.
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 4 of 13
RNA51958A, B
Preliminary
Typical Characteristics
Thermal Derating
Detection Voltage vs. Ambient Temperature
600
500
400
300
200
100
0
1.28
1.27
1.26
1.25
1.24
1.23
1.22
8-pin DIP
VSH
(PRDP0008AF-B)
VSL
8-pin SOP
(PRSP0008DE-C)
85
0
25
50
75
100 125
–40 –20
0
20 40 60 80 100
Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C)
Detection Voltage vs. Supply Voltage
1.28
Input Current vs. Supply Voltage
VIN = 1.25 V
250
200
150
100
50
1.27
1.26
1.25
1.24
1.23
1.22
VSH
Ta = –40°C
VSL
Ta = 25°C
Ta = 85°C
0
0
0
4
8
12
16
20
4
8
12
16
20
Supply Voltage VCC (V)
Supply Voltage VCC (V)
Delay Capacitance vs. Delay Time
VCC = 5 V
Delay Time vs. Ambient Temperature
10
7
5
6
CD = 0.01 μF
3
5
4
3
2
1
0
1
7
5
3
VCC = 5 V
0.1
7
5
10 V
VCC = 15 V
3
0.01
7
5
3
0.001
0.1 3 5 7 1
3 5 7 10 3 5 7 100 3 5 7 1000
–40 –20
0
20 40 60 80 100
Delay Time tpd (ms)
Ambient Temperature Ta (°C)
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 5 of 13
RNA51958A, B
Preliminary
Canstant Current at Cd pin vs. Ambient Temperature
Output Saturation Voltage vs. Output Sink Current
0.3
0.2
0.1
0
–12
–10
–8
–6
–4
–2
0
Supply voltage detecting
: VCC = 5 V
VCC = 5 V
VCC = 15 V
0
1
2
3
4
5
6
–40 –20
0
20 40 60 80 100
Output Sink Current Isink (mA)
Ambient Temperature Ta (°C)
Circuit Current vs. Supply Voltage
(RNA51958B)
Output Load Current vs. Output Voltage
(RNA51958A)
800
600
400
200
0
–40
Ta = –40°C
–30
–20
–10
0
VCC = 5 V VCC = 10 V VCC = 15 V
Ta = 25°C
Ta = 85°C
0
4
8
12
16
0
4
8
12
16
Supply Voltage VCC (V)
Output Voltage VO (V)
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 6 of 13
RNA51958A, B
Preliminary
Example of Application Circuit
Reset Circuit of RNA51958
VCC
Power-
supply
Power-
supply
R1
RL
Input
Output
RESET
Logic circuit
RNA51958x
GND
R2
Delay capacitor
Cd
GND
Figure 1 Reset Circuit of RNA51958
Notes: 1. When the detecting supply voltage is 4.25 V, RNA51953 are used. In this case, R1 and R2 are not necessary.
When the voltage is anything except 4.25 V, RNA51957 and RNA51958 are used. In this case, the detecting
supply voltage is 1.25 (R1 +R2)/R2 (V) approximately.
The detecting supply voltage can be set between 2 V and 15 V.
2. If a longer delay time is necessary, RNA51953, RNA51957, RNA51958 are used. In this case, the delay
time is about 0.34 Cd (pF) s.
3. If the RNA51958 and the logic circuit share a common power source, type A (built-in load type) can be used
whether a pull-up resistor is included in the logic circuit or not.
4. The logic circuit preferably should not have a pull-down resistor, but if one is present, add load resistor RL to
overcome the pull-down resistor.
5. When the reset terminal in the logic circuit is of the low reset type, RNA51953 and RNA51957 are used and
when the terminal is of the high reset type, RNA51958 are used.
6. When a negative supply voltage is used, the supply voltage side of RNA51958 and the GND side are
connected to negative supply voltage respectively.
Case of Using Reset Signal except Supply Voltage in the RNA51958
(a) Reset at ON
(b) Reset at transistor ON
Power-
VCC
VCC
Power-
supply
Power-
supply
Power-
supply
supply
R1
RL
R1
RL
Out
put
Out
put
Input
Input
RESET
Logic circuit
RESET
Logic circuit
RNA51958x
RNA51958x
R2
R2
GND
Delay capacitor
Cd
GND
GND
Delay capacitor
Cd
GND
Control
signal
Figure 2 Case of Using Reset Signal except Supply Voltage in the RNA51958
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 7 of 13
RNA51958A, B
Preliminary
Delay Waveform Generating Circuit
When RNA51958 are used, a waveform with a large delay time can generate only by adding a small capacitor.
Power-supply
R1
Input
Output
RNA51958
R2
GND
Delay capacitor
Cd
Figure 3 Delay Waveform Generating Circuit
Operating Waveform
Input
(VCC partial
pressure)
td
Output
td ≈ 0.34 × Cd(pF) μs
Figure 4 Operating Waveform
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 8 of 13
RNA51958A, B
Preliminary
Notice for use
About the Power Supply Line
1. About bypass capacitor
Because the ripple and the spike of the high frequency noise and the low frequency are superimposed to the power
supply line, it is necessary to remove these.
Therefore, please install C1 and C2 for the low frequency and for the high frequency between the power supply line
and the GND line as shown in following figure 5.
VCC
+
C1
C2
Power-supply
Output
R1
Input
Example of ripple
noise measures
Vin
R2
RNA51958
GND
Delay capacitor
Cd
Figure 5 Example of Ripple Noise Measures
2. The sequence of voltage impression
Please do not impress the voltages to the input terminals earlier than the power supply terminal. Moreover, please
do not open the power supply terminal with the voltage impressed to the input terminal.
(The setting of the bias of an internal circuit collapses, and a parasitic element might operate.)
About the Input Terminal
1. Setting range of input voltage
The following voltage is recommended to be input to the input terminal (pin 2).
about 0.8 (V) < Vin < VCC – 0.3 (V) ... at VCC 7 V
about 0.8 (V) < Vin < 6.7 (V) ............. at VCC > 7 V
2. About using input terminal
Please do an enough verification to the transition characteristic etc. of the power supply when using independent
power supply to input terminal (pin 2).
VCC
Vin is decided to the VCC subordinating,
and operates in the range
Power-supply
about 0.8 (V) < Vin < VCC – 0.3 (V).
Input
Output
RNA51958
Vin
GND
Delay capacitor
Cd
Figure 6 Recommended Example
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 9 of 13
RNA51958A, B
Preliminary
Independent
VCC
1
VCC
2
VCC
Independent
Input
Power-supply
Output
Power-supply
Output
Input
RNA51958
RNA51958
Vin
Vin
VCC
GND
GND
Delay capacitor
Cd
GND
Delay capacitor
Cd
Example 1. Independent power supply system
Please do enough verifying about
Example 2. Logic pulse input
(not recommended)
transition characteristic of VCC
and VCC2.
1
Figure 7
3. Calculation of detecting voltage
Detecting voltage Vs can be calculated by the following expression.
However, the error margin is caused in the detecting voltage because input current Iin (standard 100 nA) exists if it
sets too big resistance.
Please set the constant to disregard this error margin.
R + R
1
2
V = 1.25 ×
S
+ Iin × R
1
R
2
error margin
VCC
Power-supply
Output
R1
Iin
→
RNA51958
Vin
R2
Input
GND
Delay capacitor
Cd
Figure 8 Influence of Input Current
4. About the voltage input outside ratings
Please do not input the voltage outside ratings to the input terminal.
An internal protection diode becomes order bias, and a large current flows.
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 10 of 13
RNA51958A, B
Preliminary
Setting of Delay Capacity
Please use capacitor Cd for the delay within the range of 10 F or less.
When a value that is bigger than this is set, the problem such as following (1), (2), and (3) becomes remarkable.
t
VCC
Output
tpd
tPHL
Figure 9 Time Chart at Momentary Voltage-Decrease
(1) The difference at delay time becomes remarkable.
A long delay setting of tens of seconds is fundamentally possible. However, when set delay time is lengthened, the
range of the difference relatively grows, too. When a set value is assumed to be ‘tpd’, the difference occurs in the
range from 0.47 tpd to 2.05 tpd. For instance, 34 seconds can be calculated at 100 F. However, it is likely to
vary within the ranges of 16-70 seconds.
(2) Difficulty to react to a momentary voltage decrease.
For example, the reaction time tPHL is 10 s when delay capacitor Cd = 0.1 F.
The momentary voltage-decrease that is longer than such tPHL are occurs, the detection becomes possible. When the
delay capacitance is enlarged, tPHL also becomes long. For instance, it becomes about 100 to 200 s in case of
circuit constant C1 = 100 F.
(Characteristic graph 1 is used and extrapolation in case of Cd = 100 F.)
Therefore, it doesn't react to momentary voltage-decrease that is shorter than this.
(3) Original delay time is not obtained.
When the momentary voltage-decrease time ‘t’ is equivalent to tPHL, the discharge becomes insufficient and the
charge starts at that state. This phenomenon occurs at large capacitance. And, original delay time tpd is not
obtained.
Please refer to characteristic graph 2. (Delay time versus input pulse width)
Characteristic Graph 1
Reaction Time vs. Delay Capacitance
(Example data)
Characteristic Graph 2
Delay Time vs. Momentary Voltage Decrease Pulse Width
(Example data)
1000
10000
Delay Capacitance
0.01 μF
0.033 μF
0.1 μF
0.33 μF
1 μF
200
100
1000
100
10
2.2 μF
3.3 μF
10
1
1
1
0.01
0.1
1
10
100
10
100
Pulse Width (μs)
1000
10000
Delay Capacitance Cd (μF)
Figure 10 Characteristic Graph
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 11 of 13
RNA51958A, B
Preliminary
Setting of Output Load Resistance (RNA51958B)
High level output voltage can be set without depending on the power-supply voltage because the output terminal is an
open collector type. However, please guard the following notes.
1. Please set it in value (2 V to 17 V) within the range of the power-supply voltage recommendation.
Moreover, please never impress the voltage of maximum ratings 18 V or more even momentarily either.
2. Please set output load resistance (pull-up resistance) RL so that the output current (output inflow current IL) at L
level may become 4 mA or less. Moreover, please never exceed absolute maximum rating (6 mA).
VCC (2 V to 17 V)
RL
6
IL ≤ 4 mA
Figure 11 Output Load Resistance RL
Others
1. Notes when IC is handled are published in our reliability handbook, and please refer it.
The reliability handbook can be downloaded from our homepage (following URL).
http://www.renesas.com/products/common_info/reliability/reliability_root.jsp
2. Additionally, please inquire of our company when there is an uncertain point on use.
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 12 of 13
RNA51958A, B
Preliminary
Package Dimensions
JEITA Package Code
P-SOP8-4.4x4.85-1.27
RENESAS Code
Previous Code
—
MASS[Typ.]
0.1g
PRSP0008DE-C
F
*1
D
NOTE)
8
5
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Reference
1
4
Symbol
Min Nom Max
*3
e
bp
Z
D
4.65 4.85 5.05
x
M
E
A2
4.2
4.4 4.6
1.85
L1
A1 0.00 0.1 0.20
2.03
A
bp 0.34 0.4 0.46
b1
c
c1
0.15 0.20 0.25
L
θ
0° 8°
y
HE 5.7 6.2 6.5
Detail F
e
1.12 1.27 1.42
x
0.12
y
Z
L
0.10
0.75
0.25 0.45 0.65
0.90
L1
JEITA Package Code
P-DIP8-6.3x9.6-2.54
RENESAS Code
PRDP0008AF-B
Previous Code
DP-8FV
MASS[Typ.]
0.54g
D
8
5
1
4
b 3
0.89
Z
Dimension in Millimeters
Min Nom Max
7.62
Reference
Symbol
e1
D
E
9.60 10.6
6.30 7.4
5.06
A
bp
e
c
A1
bp
b3
c
0.5
0.40 0.48 0.56
1.30
0.19 0.25 0.31
e1
( Ni/Pd/Au plating )
θ
15°
0°
e
2.29 2.54 2.79
Z
L
1.27
2.54
REJ03D0915-0302 Rev.3.02
Apr 01, 2010
Page 13 of 13
Notice
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Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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