概述
规格参数
数据手册UPA2761UGR-E1-AT 概述
MOS FIELD EFFECT TRANSISTOR MOS场效应 功率场效应晶体管
UPA2761UGR-E1-AT 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | SOP |
| 包装说明： | SMALL OUTLINE, R-PDSO-G8 | 针数： | 8 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| 风险等级： | 5.84 | Is Samacsys： | N |
| 雪崩能效等级（Eas）： | 8.1 mJ | 配置： | SINGLE WITH BUILT-IN DIODE |
| 最小漏源击穿电压： | 30 V | 最大漏极电流 (Abs) (ID)： | 9 A |
| 最大漏极电流 (ID)： | 9 A | 最大漏源导通电阻： | 0.0185 Ω |
| FET 技术： | METAL-OXIDE SEMICONDUCTOR | JESD-30 代码： | R-PDSO-G8 |
| 元件数量： | 1 | 端子数量： | 8 |
| 工作模式： | ENHANCEMENT MODE | 最高工作温度： | 150 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 极性/信道类型： | N-CHANNEL | 最大功率耗散 (Abs)： | 2.5 W |
| 最大脉冲漏极电流 (IDM)： | 40 A | 认证状态： | Not Qualified |
| 子类别： | FET General Purpose Power | 表面贴装： | YES |
| 端子形式： | GULL WING | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 晶体管应用： | SWITCHING |
| 晶体管元件材料： | SILICON | Base Number Matches： | 1 |
UPA2761UGR-E1-AT 数据手册
通过下载UPA2761UGR-E1-AT数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Preliminary Data Sheet
μ PA2761UGR
MOS FIELD EFFECT TRANSISTOR
Description
R07DS0010EJ0100
Rev.1.00
Jun 01, 2010
The μ PA2761UGR is N-Channel MOS Field Effect Transistor designed for power management applications of a
notebook computer.
Features
•
Low on-state resistance
⎯ RDS(on)1 = 18.5 mΩ MAX. (VGS = 10 V, ID = 9 A)
⎯ RDS(on)2 = 30 mΩ MAX. (VGS = 4.5 V, ID = 7 A)
Low Ciss: Ciss = 550 pF TYP. (VDS = 15 V, VGS = 0 V)
Small and surface mount package (Power SOP8)
RoHS Compliant
•
•
•
Ordering Information
Part No.
LEAD PLATING
PACKING
Package
1
μ PA2761UGR-E1-AT ∗
μ PA2761UGR-E2-AT ∗
Pure Sn (Tin)
Tape 2500 p/reel
Power SOP8
0.08 g TYP.
1
Note: ∗1. Pb-free (This product does not contain Pb in external electrode and other parts.)
Absolute Maximum Ratings (TA = 25°C, All terminals are connected)
Item
Symbol
Ratings
Unit
V
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC)
VDSS
VGSS
ID(DC)
30
25
V
9
A
1
Drain Current (pulse) ∗
ID(pulse)
PT1
40
A
2
Total Power Dissipation ∗
Total Power Dissipation (PW = 10 sec) ∗
1.1
W
W
°C
°C
A
2
PT2
2.5
Channel Temperature
Tch
150
Storage Temperature
Single Avalanche Current ∗
Single Avalanche Energy ∗
Tstg
IAS
−55 to +150
3
9
3
EAS
8.1
mJ
Notes: ∗1. PW ≤ 10 μs, Duty Cycle ≤ 1%
∗2. Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mmt
∗3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100 μH
R07DS0010EJ0100 Rev.1.00
Jun 01, 2010
Page 1 of 6
μ PA2761UGR
Chapter Title
Electrical Characteristics (TA = 25°C, All terminals are connected)
Item
Symbol
Min
Typ
Max
10
Unit
μA
μA
V
Test Conditions
Zero Gate Voltage Drain Current IDSS
VDS = 30 V, VGS = 0 V
VGS = 20 V, VDS = 0 V
Gate Leakage Current
IGSS
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
100
2.5
Gate Cut-off Voltage
Forward Transfer Admittance ∗
1.0
2.5
VDS = 10 V, I = 1 mA
D
1
S
VDS = 10 V, ID = 4.5 A
VGS = 10 V, ID = 9 A
VGS = 4.5 V, ID = 7 A
VDS = 15 V,
Drain to Source On-state
14.3
20.1
550
93
18.5
30
mΩ
mΩ
pF
pF
pF
ns
1
Resistance ∗
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
td(on)
tr
VGS = 0 V,
56
f = 1 MHz
8
VDD = 15 V, ID = 4.5 A,
VGS = 10 V,
3.3
24.5
4
ns
Turn-off Delay Time
Fall Time
td(off)
tf
ns
RG = 10 Ω
ns
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ∗
Reverse Recovery Time
Reverse Recovery Charge
Note: ∗1. Pulsed
QG
5.5
2.1
2.7
nC
nC
nC
V
VDD = 15 V,
QGS
QGD
VF(S-D)
trr
VGS = 5 V,
ID = 9 A
1
1.2
IF = 9 A, VGS = 0 V
IF = 9 A, VGS = 0 V,
di/dt = 100 A/μs
21
ns
Qrr
13.5
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
V
GS
R
L
R
G
= 25 Ω
90%
V
GS
Wave Form
V
GS
10%
0
R
G
PG.
PG.
50 Ω
V
DD
V
DD
V
GS = 20 → 0 V
DS
90%
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
τ
I
D
t
d(on)
t
r
t
d(off)
tf
V
DD
t
on
toff
τ
= 1
μ
s
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
IG
R
L
PG.
50 Ω
V
DD
R07DS0010EJ0100 Rev.1.00
Jun 01, 2010
Page 2 of 6
μ PA2761UGR
Chapter Title
Typical Characteristics (TA = 25°C)
FORWARD BIAS SAFE OPERATING AREA
DERATING FACTOR OF FORWARD BIAS SAFE
OPERATING AREA
120
100
80
60
40
20
0
100
10
I
D(pulse)
P
W
=
3
0
0
μ
1
10
s
1
1 m
m
1
1
s
s
1
10
0
m
1
1
10
s
s
1
Power Dissipation Limited
0.1
T
A
= 25°C
Single Pulse
Mounted on glass epoxy board of
25.4 mm x 25.4 mm x 0.8 mmt
0.01
0
25
50
75 100 125 150 175
0.01
0.1
1
10
100
TC - Case Temperature - °C
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
Single pulse
1000
100
10
R
th(ch-A) = 113.6°C/W
1
0.1
R
th(ch-A): Mounted on a glass epoxy board of 25.4mm x 25.4mm x 0.8 mmt
0.01
100 μ
1 m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
DRAIN CURRENT vs.
FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
50
40
30
20
10
0
10
V
DS = 10 V
Pulsed
8
6
4
2
0
TA
= −55°C
25°C
V
GS = 10 V
75°C
125°C
4.5 V
Pulsed
0
0.2
0.4
0.6
0.8
1
0
1
2
3
4
5
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
R07DS0010EJ0100 Rev.1.00
Jun 01, 2010
Page 3 of 6
μ PA2761UGR
Chapter Title
GATE CUT-OFF VOLTAGE vs. CHANNEL
TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs. DRAIN
CURRENT
3
2.5
2
10
T
A
=
−
55
25
75
°C
°C
°C
°C
1.5
1
1
125
0.5
0
V
DS = 10 V
V
DS = 10 V
= 1 mA
Pulsed
I
D
0.1
-50
0
50
100
150
0.1
1
10
Tch - Channel Temperature - °C
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
50
50
Pulsed
I
D
= 9 A
Pulsed
40
30
20
10
0
40
30
20
10
0
V
GS = 4.5 V
10 V
1
10
ID - Drain Current - A
100
0
5
10
15
20
V
GS - Gate to Source Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
50
1000
100
10
Pulsed
C
iss
40
30
20
10
0
V
GS = 4.5 V,
= 7 A
I
D
C
C
oss
rss
10 V, 9 A
V
GS = 0 V
f = 1 MHz
-50
0
50
100
150
0.1
1
10
100
Tch - Channel Temperature - °C
VDS - Drain to Source Voltage - V
R07DS0010EJ0100 Rev.1.00
Jun 01, 2010
Page 4 of 6
μ PA2761UGR
Chapter Title
DYNAMIC INPUT CHARACTERISTICS
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
7
6
5
4
3
2
1
0
100
V
DD = 24 V
15 V
10
1
6 V
V
GS = 10 V
0 V
I
D
= 9 A
Pulsed
1 1.2
0.1
0
1
2
3
4
5
6
7
0
0.2
0.4
0.6
0.8
QG - Gate Charge - nC
VF(S-D) - Source to Drain Voltage - V
R07DS0010EJ0100 Rev.1.00
Jun 01, 2010
Page 5 of 6
μ PA2761UGR
Chapter Title
Package Drawings (Unit: mm)
Power SOP8
8
5
1, 2, ꢀ
4
; Source
; Gate
5, 6, 7, 8 ; Drain
6.0 0.ꢀ
4.4
1
4
5.ꢀ7 MAX.
0.8
0.5 0.2
0.10
1.27 0.78 MAX.
+0.10
–0.05
0.40
0.12 M
Equivalent Circuit
Drain
Body
Diode
Gate
Source
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred.
R07DS0010EJ0100 Rev.1.00
Jun 01, 2010
Page 6 of 6
Revision History
μPA2761UGR
Description
Summary
Rev.
1.00
Date
Page
June 01, 2010
−
First Eddition Issued
All trademarks and registered trademarks are the property of their respective owners.
C - 1
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