UPD16670W-XXX [RENESAS]
33 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC, WAFER;
| 型号： | UPD16670W-XXX |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 33 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC, WAFER 时钟 驱动 CD 外围集成电路 |
| 文件： | 总26页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16670
1/17, 1/25, 1/33 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
The µ PD16670 is a LCD controller/driver with 1/17, 1/25 and 1/33 duty capable of displaying a dot matrix LCD. It
has 60 segment outputs, 33 common outputs, giving a maximum display capability of 12 columns x 4 lines (at 1/33
duty).
The µ PD16670 includes 4 x mode on-chip booster circuit, capable of operating on single 3 V-power supply.
FEATURES
• Dot matrix LCD controller/driver
• Able to operate using +3-V single power supply
• 4 x mode on-chip boost circuit
• Display contents
1/17 duty: 12 columns x 2 lines + 60 pictograph displays
1/25 duty: 12 columns x 3 lines + 60 pictograph displays
1/33 duty: 12 columns x 4 lines + 60 pictograph displays
• Serial data input (SCK, STB, DATA)
ORDERING INFORMATION
Part number
Package
µ PD16670W-xxx
µ PD16670P-xxx
Wafer
Chip
★
Remark Purchasing the above chip/wafer entails exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published September 2000 NS CP(K)
Printed in Japan
S10297EJ1V0DS00 (1st edition)
The mark ★ shows major revised points.
1995
©
µPD16670
★
1. BLOCK DIAGRAM
SEG
1
SEG60
COM33
COM
1
Segment Driver
Common Driver
33
60
60 bit Latch
33 bit Shift Register
60
60 bit Shift Register
Timing Generator
OSCIN
Parallel/Serial Conversion Circuit
Internal
Oscillator
5
5
OSCOUT
C +
1
CGRAM/
Pictograph
RAM
C −
1
CGROM
5 x 8 x 240 bit
DDRAM
8 x 48 bit
C +
2
5 x 8 x 8 bit
DC/DC
Converter
−
C2
C +
3
C −
3
5
8
8
8
STB
SCK
V
LCD
8
Command
Decoder
V
LC1
LC2
Serial I/F
DATA
V
V
LC3
TDATA
/RESET
V
LC4
VLC5
/LCDOFF
TEST
VDD
VSS
★
Remark
/xxx indicates active low signals.
2
Data Sheet S10297EJ1V0DS00
µPD16670
2. PIN CONFIGURATION (Pad Layout)
Chip size: 4.20 x 5.40 mm2
56
84
55
85
Y
X
24
116
1
23
3
Data Sheet S10297EJ1V0DS00
µPD16670
Table 2−1. Pad Layout
PAD No.
1
Pad Name
X ( m)
Y ( m)
PAD No.
59
Pad Name
SEG41
X ( m)
Y ( m)
µ
µ
µ
µ
+
−
+
−
+
−
C2
C2
C3
C3
C1
C1
1545
−
1425
−
1305
−
1135
−
1015
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
2480
−
1839
−
1719
−
1599
−
1479
−
1359
−
1239
−
1119
−
1319
1199
1079
959
839
719
599
479
359
239
119
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
2479
1880
1760
1640
1520
1400
1280
1160
1040
920
2
60
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
3
61
4
62
5
63
6
845
725
605
435
265
64
−
7
VDD
65
−
−
−
−
8
VLCD
66
9
VLC1
67
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
VLC2
68
VLC3
95
−
69
VLC4
75
70
1
−
VLC5
245
71
121
−
241
−
361
−
481
−
601
−
721
−
841
−
961
−
VSS
365
72
OSCIN
OSCOUT
TEST
TDATA
RESETB
LCDOFFB
STB
485
73
605
74
775
75
895
76
1065
1185
1355
1475
1645
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1837
1679
1559
1439
77
78
79
1081
−
1201
−
1321
−
1441
−
1561
−
1681
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
1837
−
SCK
80
DATA
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
81
82
83
84
85
86
87
88
999
879
759
639
519
399
279
159
89
−
90
−
−
−
−
−
−
−
91
92
SEG8
93
SEG7
94
SEG6
800
95
SEG5
680
96
SEG4
560
39
−
97
SEG3
440
81
98
SEG2
320
201
321
99
SEG1
200
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
80
441
40
−
561
160
−
280
−
400
−
520
−
640
−
760
−
880
−
681
801
921
1041
1161
1281
1401
1521
1641
1761
1881
2479
2479
2479
1000
−
1120
−
1240
−
1360
−
1480
−
1600
−
1720
−
1840
−
4
Data Sheet S10297EJ1V0DS00
µPD16670
3. PIN FUNCTIONS
Pin Symbol
Pin Name
Pad No.
40 to 99
I/O
O
Description
SEG1 to SEG60 Segment
COM1 to COM33 Common
Segment output pins
Common output pins
★
24 to39
100 to116
22
O
COM1 is assigned to common for pictograph.
Data shift clock
SCK
Shift clock
I
During the read-in operation, data is captured in the shift register
at the signal’s rising edge. During a read-out operation, data is
read from the shift register at the signal’s falling edge.
DATA
Data
23
I
Performs input of commands and data.
Input is performed from the MSB on the rise of the shift clock.
Communication is enabled when STB is low.
When at low level, a forced LCD off operation is performed
SEGn = COMn = VSS
STB
Strobe
21
20
I
I
/LCDOFF
LCD off input
/RESET
TDATA
Reset
19
18
I
This pin is used for internal resets at low level.
Test output
O
This is a test output pin. Leave this pin open when using the
device.
TEST
Test pin
17
I
I
Test mode is set when at high level.
OSCIN
OSCOUT
Oscillator pins
15, 16
5, 6
These pins are connected to a 100-kΩ resistance. When using
an external oscillator, input to OSCIN and leave OSCOUT open.
O
−
+
-
-
-
C1 , C1
Capacitor connection 1 to 6
pins
These are capacitor connection pins for the boost circuit.
+
Connect a 1-µF capacitor.
C2 , C2
+
C3 , C3
VDD
VSS
Logic power supply pin 7
−
−
−
Power supply pins for logic
Logic ground pin
14
8
Ground pin for logic
VLCD
Driver power supply
pins
Power supply pin for driver. Output pin for internal boost circuit.
Connect a 1-µF capacitor between this pin and the VSS pin for
boosting.
If not using the internal boost circuit, a direct driver power supply
can be input.
VLC1 - VLC5
Reference power
9 to 13
−
These are reference power supply pins for the LCD driver.
Input divided register by each external power supply pin.
supply pins for driver
5
Data Sheet S10297EJ1V0DS00
µPD16670
Figure 3−1. Example of LCD driver’s circuit and external circuit for boosted circuit
C3
C2
C1
+
+
+
-
+
+
-
-
+
C1
C2
C1
C2
C3
C3
VDD
C4
4 x Boost mode
+
VLCD
R2
VLC1
+
5
C
R1
VLC2
+
C5
R1
VLC3
+
+
+
C
5
R
1
1
V
LC4
C5
R
V
LC5
C5
R
1
VEE
6
Data Sheet S10297EJ1V0DS00
µPD16670
4. LCD DISPLAY DRIVER
µ PD16670, a 5 x 8 segment display and pictograph display segments can be driven.
(1) Example of 1/17 duty connection: 12 columns x 2 lines + 60 pictograph displays
7
9
2
4
57
59
12
14
SEG
1
3
5
11
13
15
56
58
60
6
8
10
COM
1
COM
COM
COM
COM
COM
COM
COM
COM
2
3
4
5
6
7
8
9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
7
Data Sheet S10297EJ1V0DS00
µPD16670
(2) Example of 1/25 duty connection: 12 columns x 3 lines + 60 pictograph displays
7
9
2
4
57
59
12
14
SEG
1
3
5
11
13
15
56
58
60
6
8
10
COM
1
COM
COM
COM
COM
COM
COM
COM
COM
2
3
4
5
6
7
8
9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
8
Data Sheet S10297EJ1V0DS00
µPD16670
(3) Example of 1/33 duty connection: 12 columns x 4 lines + 60 pictograph displays
7
9
2
4
57
59
12
14
SEG
1
3
5
11
13
15
56
58
60
6
8
10
COM
1
COM
COM
COM
COM
COM
COM
COM
COM
2
3
4
5
6
7
8
9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
9
Data Sheet S10297EJ1V0DS00
µPD16670
5. CHARACTER CODE
The relation between character codes and character patterns is shown below. Character codes [0xxx] are allocated
to CGRAM.
Higher bits
0000 0001 0010 0011 0100 0101 0110 0111
1010 1011
1100
1101 1110
1111
Lower
4 bits
bits 4 bits
CG
RAM
(1)
XXXX0000
(2)
(3)
(4)
(5)
(6)
XXXX0001
XXXX0010
XXXX0011
XXXX0100
XXXX0101
XXXX0110
(7)
(8)
(1)
XXXX0111
XXXX1000
XXXX1001
XXXX1010
(2)
(3)
(4)
(5)
(6)
(7)
(8)
XXXX1011
XXXX1100
XXXX1101
XXXX1110
XXXX1111
10
Data Sheet S10297EJ1V0DS00
µPD16670
6. DESCRIPTION OF BLOCKS
6.1 Display Data RAM (DDRAM)
DDRAM addresses are allocated as shown below
1
2
3
4
5
6
7
8
9
10
11
12
1st line
2nd line
3rd line
4th line
00H
12H
24H
36H
01H
13H
25H
37H
02H
14H
26H
38H
03H
15H
27H
39H
04H
16H
28H
3AH
05H
17H
29H
3BH
06H
18H
2AH
3CH
07H
19H
2BH
3DH
08H
1AH
2CH
3EH
09H
1BH
2DH
3FH
0AH
1CH
2EH
40H
0BH
1DH
2FH
41H
Caution DDRAM are used 0BH → 10H, 1BH → 20H, 2BH → 30H, 3BH → 00H when in auto increment mode.
11
Data Sheet S10297EJ1V0DS00
µPD16670
6.2 Character Generator RAM (CGRAM)
CGRAM is RAM to which the user can freely set character patterns. Eight types of 5 x 8 dot character patterns can
be defined. CGRAM is the RAM that contains pictograph display data.
The relation between character codes and CGRAM addresses used to access CGRAM is shown below.
CGRAM
address
D4
D3
D2
D1
D0
CGROM
address
CGRAM
address
D4
D3
D2
D1
D0
CGROM
address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
00H
01H
02H
04H
05H
06H
07H
Caution Some addresses in 06H and all 07H address in CGROM are shared with pictograph data RAM.
12
Data Sheet S10297EJ1V0DS00
µPD16670
Pictograph Display RAM (PDRAM)
6.2.1
Pictograph display RAM addresses used to some parts of CGRAM is shown below.
CGRAM address
D5
D4
D3
D2
D1
CGROM address
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
45
50
55
60
44
49
54
59
43
48
53
58
42
47
52
57
41
46
51
56
06H
5
4
3
2
1
10
15
20
25
30
35
40
9
8
7
6
14
19
24
29
34
39
13
18
23
28
33
38
12
17
22
27
32
37
11
16
21
26
31
36
07H
13
Data Sheet S10297EJ1V0DS00
µPD16670
7. COMMANDS
7.1 Basic format
Command register (CR)
Address register (AR)
+ · · ·
+
+
DATA2 (DT2)
+
DATA1 (DT1)
Address (AR)
7.2 Command register
The command register’s basic configuration is as follows.
LSB
MSB
b7 b6 b5 b4 b3 b2 b1 b0
Selection
Command type
7.2.1 Reset
This command resets all of the commands in the µ PD16670.
LSB
1
MSB
0
0
0
0
0
0
1
7.2.2 Display ON/OFF
This command controls the display’s ON/OFF status.
LSB
MSB
0
0
0
0
1
b2 b1 b0
Selection
000 : LCD OFF (SEG = non-select waveform)
n
111 : LCD ON (Normal operation)
14
Data Sheet S10297EJ1V0DS00
µPD16670
7.2.3 Standby
This command stops the DC/DC converter, which reduces the supply current. The display is set to OFF mode
n
n
LC5
(SEG , COM = V ).
LSB
MSB
0
0
0
1
0
b2 b1 b0
Selection
000 : Normal operation
001 : Standby
7.2.4 Duty setting
This command specifies the duty setting.
LSB
MSB
0
0
0
1
1
b2 b1 b0
Selection
000 : 1/33 duty
001 : 1/25 duty
010 : 1/17 duty
7.2.5 Test mode
This command sets the test mode. The test mode is only for confirming the IC’s operation. Regular or continuous
use while in test mode is not guaranteed.
LSB
MSB
1
1
1
1
1
b2 b1 b0
Selection
000 : Normal operation
001 to 111 : TEST mode
15
Data Sheet S10297EJ1V0DS00
µPD16670
7.3 Address Register
This command selects the address type and specifies addresses.
LSB
0
MSB
1
LSB
b5 b4 b3 b2 b1 b0
MSB
0
+
1
0
b4
0
0
0
0
Selection
Address
0 : DDRAM address
1 : CGRAM address
Caution Operation is not guaranteed if an invalid address is set.
★
7.4 Reset
The contents of the various registers appear as shown below after a reset (command reset or hardware [pin] reset).
Command
Register Contents
Description
b7
0
b6
0
b5
0
b4
0
b3
1
b2
0
b1
0
b0
0
Display ON/OFF
LCD OFF
Standby
0
0
0
1
0
0
0
0
Normal operation
1/33 duty
Duty setting
Test mode
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
Normal operation
7.5 Serial communication format
STB
DATA
SCK
b0
b1
b2
b5
b6
b7
1
2
3
6
7
8
16
Data Sheet S10297EJ1V0DS00
µPD16670
8. CPU ACCESS EXAMPLES
Examples of access procedure are shown below.
8.1 Initialize and Data Write
Command/data
Parameter
STB
Description
b7 B6 b5 b4 b3 b2 b1 b0
Start
H
L
X
0
X
0
X
1
0
X
X
0
X
0
X
1
0
X
X
0
X
0
X
0
0
X
X
0
X
1
X
1
0
X
0
X
1
X
0
0
X
1
X
0
X
0
0
X
1
X
0
X
0
0
X
1
X
1
X
0
0
Reset
All commands initialized
H
L
Duty setting
12 columns by 3 rows + 60 pictographs (1/25 duty)
H
L
Address register 1
Address register 2
CGRAM
L
CGRAM address = 00H
L
D4 D3 D2 D1 D0
Data 1
to
CGRAM data
:
:
:
:
:
:
:
:
:
L
X
X
X
D4 D3 D2 D1 D0
CGRAM data48
H
L
L
L
X
1
0
X
X
1
0
X
X
0
1
X
1
1
X
0
0
X
0
0
X
0
0
X
0
0
X
Address register 1
Address register 2
Pictograph data 1
to
Pictograph data RAM
Pictograph data RAM address = 30H
D5 D4 D3 D2 D1
Pictograph data
:
:
:
:
:
:
:
:
:
L
X
X
D5 D4 D3 D2 D1
X
Pictograph data 4
H
L
L
L
X
1
0
X
X
1
0
X
X
0
1
X
X
1
1
X
0
0
X
0
0
X
0
0
X
0
0
Address register 1
Address register 2
Pictograph data 5
to
Pictograph data RAM
Pictograph data RAM address = 38H
D4 D3 D2 D1 D0
Pictograph data
:
:
:
:
:
:
:
:
:
L
X
X
X
D4 D3 D2 D1 D0
Pictograph data 12
H
L
L
L
X
1
X
1
X
0
X
1
X
0
X
0
X
0
X
0
Address register 1
Address register 2
Character data 1
to
Display data RAM
0
0
0
0
0
0
0
0
Display data RAM address = 00H
D
D
D
D
D
D
D
D
Display data
:
:
:
:
:
:
:
:
:
L
D
D
D
D
D
D
D
D
Character data 36
H
L
X
0
X
0
X
0
X
0
X
1
X
1
X
1
X
1
Display ON/OFF
End
LCD ON (at the STB rising edge)
H
X
X
X
X
X
X
X
X
★
Remark X = Don’t care, D = Data
17
Data Sheet S10297EJ1V0DS00
µPD16670
8.2 Initialize and Data Write (unused pictograph)
Command/data
Parameter
STB
Description
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
L
X
0
X
0
X
1
0
X
X
0
X
0
X
1
0
X
X
0
X
0
X
0
0
X
X
0
X
1
X
1
0
X
X
1
X
0
X
0
0
X
1
X
0
X
0
0
X
1
X
1
X
0
0
Reset
0
All commands initialized
H
L
X
1
X
0
0
Duty setting
12 columns by 3 rows + 60 pictographs (1/25 duty)
H
L
Address register 1
Address register 2
CGRAM data1
to
CGRAM
L
CGRAM address = 00H
L
D4 D3 D2 D1 D0
CGRAM data
:
:
:
:
:
:
:
:
:
CGRAM data 64
L
X
X
X
D4 D3 D2 D1 D0
H
L
L
L
X
1
X
1
X
0
X
0
X
0
X
0
X
0
X
0
Address register 1
Address register 2
Character data 1
to
Display data RAM
0
0
0
0
0
0
0
0
Display data RAM address = 00H
D
D
D
D
D
D
D
D
Display data
:
:
:
:
:
:
:
:
:
L
D
D
D
D
D
D
D
D
Character data 36
H
L
X
0
X
0
X
0
X
0
X
1
X
1
X
1
X
1
Display ON/OFF
End
LCD ON (at the STB rising edge)
H
X
X
X
X
X
X
X
X
★
Remark X = Don’t care, D = Data
18
Data Sheet S10297EJ1V0DS00
µPD16670
8.3 Change display data
Command/data
Parameter
STB
Description
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
L
L
X
1
0
X
1
0
X
0
0
X
0
1
X
X
0
0
X
0
0
X
0
1
Address register 1
Address register 2
0
Display data RAM
0
Display RAM address = 11H (2 lines 2 clumns)
Display RAM address = 11H,
Character data 1
Character data 2
Character data 3
Character data 4
Character data 5
L
L
L
L
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
Data write: character code (20H: space)
Display RAM address = 12H,
1
0
0
Data write: character code (4EH: ”N”)
Display RAM address = 13H,
Data write: character code (45H: ”E”)
Display RAM address = 14H,
Data write: character code (43H: ”C”)
Display RAM address = 15H,
L
0
0
1
0
0
0
0
0
Data write: character code (20H: space)
End
H
X
X
X
X
X
X
X
X
★
Remark X = Don't Care
8.4 Standby mode
Command/data
b7 b6 b5 b4 b3 b2 b1 b0
Parameter
STB
Description
Start
H
L
X
0
X
0
X
0
X
1
X
X
0
X
0
X
1
Standby
0
Standby
H
L
X
0
X
0
X
0
X
1
X
0
X
0
X
0
X
0
Standby off
End
Normal operation Note
H
X
X
X
X
X
X
X
X
Note When in standby mode, DC/DC converter is stop.
If the display operation mode is set before entering the standby mode, it may not be normally working until
DC/DC converter, which set after cleaning the standby mode.
★
Remark X = Don't Care
19
Data Sheet S10297EJ1V0DS00
µPD16670
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Symbol
VDD
Rating
Unit
Logic power supply voltage
Logic input voltage
−0.3 to +7.0
−0.3 to VDD+0.3
−0.3 to +16.0
V
V
V
V
V
VIN
Driver supply voltage
VLCD
Driver reference supply input voltage
VLC1-VLC5
VOUT
−0.3 to VLCD+0.3
−0.3 to VDD+0.3
Logic system output voltage
(SEGn, COMn)
Operating ambient temperature
TA
−40 to +85
°C
°C
Storage temperature
Tstg
−55 to +150
★
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = 25°C, VSS = 0 V)
Parameter
Logic power supply voltage
Logic system input voltage
Driver supply voltage
Symbol
VDD
MIN.
TYP.
3.0
MAX.
Unit
2.7
0
3.6
VDD
14.4
VLCD
1.0
V
V
VIN
VLCD
VLC1-VLC5
C1-C3
C4
2.7
0
V
Logic system input voltage
Output capacitance
V
µF
µF
kHz
0.05
0.05
245
0.1
0.1
350
1.0
Oscillation frequency
fOSC
455
20
Data Sheet S10297EJ1V0DS00
µPD16670
Electrical characteristics (Unless otherwise specified, TA = –40 to +85°C, VSS = 0 V, VDD = 2.7 to 3.6 V)
Parameter
Symbol
VIH1
Condition
SCK,STB,DATA,/RESET,/LCDOFF
SCK,STB,DATA,/RESET,/LCDOFF
TEST,OSCIN
MIN.
0.8 VDD
0
TYP.
MAX.
VDD
Unit
V
High-level input voltage 1
Low-level input voltage 1
High-level input voltage 2
Low-level input voltage 2
High-level input current
VIL1
VIH2
VIL2
IIH
0.2 VDD
VDD
V
0.7 VDD
0
V
TEST,OSCIN
0.3 VDD
1
V
SCK,STB,DATA,/RESET,/LCDOFF,
OSCIN
µA
TEST
3
15
75
– 1
µA
µA
µA
V
Low-level input current
IIL
SCK,STB,DATA,TEST,OSCIN
/RESET,/LCDOFF
TDATA,IOH = –100 µA
–3
0.8 VDD
VSS
– 15
– 75
VDD
High-level output voltage
Low-level output voltage
VOH
VOL
TDATA,IOL = 100 µA
0.2 VDD
15
V
Common output ON resistance RCOM
Segment output ON resistance RSEG
COM1 to COM33, IIOI = 50 µA
SEG1 to SEG60 , IIOI = 50 µA
VDD = 3 V, fOSC = 350 kHz,
4-fold voltage mode, no load
VDD = 3 V, no load
kΩ
kΩ
µA
30
Current consumption
(Normal mode)
IDD1
IDD2
VLCD
200
300
Current consumption
(Standby mode)
100
µA
Driver voltage (boost voltage)
No load
3.5 VDD
4.0 VDD
V
21
Data Sheet S10297EJ1V0DS00
µPD16670
Switching characteristics (Unless otherwise specified, TA = –40 to +85°C, VSS = 0 V, VDD = 2.7 to 3.6 V)
Parameter
Symbol
fOSC
Conditions
MIN.
245
TYP.
350
MAX.
455
Unit
kHz
Oscillation frequency
Self-oscillation,
VDD = 3 V ± 10 %, R = 100 kΩ
Required timing conditions (Unless otherwise specified, TA = –40 to +85°C, VSS = 0 V, VDD = 2.7 to 3.6 V)
Parameter
Clock frequency
Symbol
fOSC
Conditions
OSCIN external clock
MIN.
TYP.
350
MAX.
455
Unit
kHz
245
0.4 fOSC
0.4 fOSC
1.2
High-level clock pulse width
Low-level clock pulse width
Shift clock cycle
OSCIN external clock
OSCIN external clock
SCK
0.6 fOSC
0.6 fOSC
−
tWHC
tWLC
tCYK
tWHK
−
ns
ns
ns
ns
ns
ns
ns
ns
High-level shift clock pulse width
Low-level shift clock pulse width
Shift clock hold time
Data setup time
SCK
350
SCK
350
tWLK
tHSTBK
tDS
STB ↓ → SCK ↓
DATA ↑↓ → SCK ↑
350
★
★
100
Data hold time
450
tDH
SCK ↑ → DATA ↑↓
SCK ↑ → STB ↑
STB hold time
350
tHKSTB
tWSTB
STB pulse width
350
Switching characteristic waveform
1/fOSC
tWHC
OSCIN
V
IH
V
IL
WLC
t
tWSTB
V
IH
STB
SCK
DATA
V
IL
V
IL
t
CYK
tHKSTB
tHSTBK
t
WLK
tWHK
V
IH
V
IL
t
DS
tDH
V
IH
IL
V
22
Data Sheet S10297EJ1V0DS00
µPD16670
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
23
Data Sheet S10297EJ1V0DS00
µPD16670
★
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Semiconductor Device Mounting Technology (C10535E)
•
The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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