UPD16676W_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

PD16676

µ

1/16, 1/32 DUTY LCD CONTROLLER/DRIVER

DESCRIPTION

µPD16676 is a controller/driver containing RAMs capable of full-dot LCD displays. One of these IC chips can drive

the full-dot LCD up to 61-by-16 dots.

These ICs are the most suitable for Kanji character or Chinese character pagers, as well as graphic pagers,

displaying 16-by-16 dots per character.

FEATURES

• LCD driver with built-in display RAM

• Dot display RAM: 2560 bits

• Output: 61 segments & 16 commons

• 8-bit parallel interface

• Oscillation circuit incorporated

•

ORDERING INFORMATION

Part Number

Package

µPD16676P

µPD16676W

Chips

Wafer

µPD16676GF-3BA

100-PIN PLASTIC QFP (14 x 20 mm)

Remark Purchasing the above products in terms of chips per wafer requires an exchange of other documents as

well, including a memorandum of the product quality. Therefore, those who are interested in this regard

are advised to contact an NEC salesperson for further details.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No.

Date Published June 1999 NS CP(K)

Printed in Japan

S10561EJ5V0DS00 (5th edition)

The mark • shows major revised points.

1996

©

µ

PD16676

1. BLOCK DIAGRAM

SEG

0

SEG60

COM

0

COM15

Segment Driver

Common Driver

16

61

Common Counter

61-bit Latch

Timing

Generator

Display Data RAM

(2560 bits)

OSC

1

2

Internal

Oscillator

Column Address Decoder

Column Address

Counter & Register

8

DB

0-DB

7

A0

V

LC1

LC2

LC3

LC4

LC5

Parallel

8

Command

Decoder

Interface

E(/RD)

R,/W(/WR)

/RESET

M,/S

FR

V

DD

V

SS

Remark /xxx indicates active low signals.

2

Data Sheet S10561EJ5V0DS00

µ

PD16676

2. PIN CONFIGURATION (Pad Layout)

50 49

3231

51

52

30

29

79

80

2

1

81 82

99 100

3

Data Sheet S10561EJ5V0DS00

µ

PD16676

3. PIN CONNECTION

Pin No.

1

Pin Symbol

I/O

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Pin Symbol

SEG²¹

SEG²⁰

SEG¹⁹

SEG¹⁸

SEG¹⁷

SEG¹⁶

SEG¹⁵

SEG¹⁴

SEG¹³

SEG¹²

SEG¹¹

SEG¹⁰

SEG⁹

SEG⁸

SEG⁷

SEG⁶

SEG⁵

SEG⁴

SEG³

SEG²

SEG¹

SEG⁰

A0

I/O

Output

Input

COM⁵

COM⁶

COM⁷

COM⁸

COM⁹

COM¹⁰

COM¹¹

COM¹²

COM¹³

COM¹⁴

COM¹⁵

SEG⁶⁰

SEG⁵⁹

SEG⁵⁸

SEG⁵⁷

SEG⁵⁶

SEG⁵⁵

SEG⁵⁴

SEG⁵³

SEG⁵²

SEG⁵¹

SEG⁵⁰

SEG⁴⁹

SEG⁴⁸

SEG⁴⁷

SEG⁴⁶

SEG⁴⁵

SEG⁴⁴

SEG⁴³

SEG⁴²

SEG⁴¹

SEG⁴⁰

SEG³⁹

SEG³⁸

SEG³⁷

SEG³⁶

SEG³⁵

SEG³⁴

SEG³³

SEG³²

SEG³¹

SEG³⁰

SEG²⁹

SEG²⁸

SEG²⁷

SEG²⁶

SEG²⁵

SEG²⁴

SEG²³

SEG²²

Output

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

OSC¹

OSC²

E(/RD)

R,/W(/WR)

V^SS

Input

Output

Input

—

DB⁰

Input/Output

—

DB¹

DB²

DB³

DB⁴

DB⁵

DB⁶

DB⁷

V^DD

/RESET

FR

Input

Input/Output

—

V^LC5

V^LC3

—

V^LC2

—

M,/S

Input

V^LC4

—

V^LC1

—

COM⁰

COM¹

COM²

COM³

COM⁴

Output

4

Data Sheet S10561EJ5V0DS00

µ

PD16676

4. PIN COORDINATES

Chip Size

:

4.04 x 5.53 mm²

120 x 120 µm²

108 x 108 µm²

Pad Size Al Area

Pad Size Open Area

Pin No.

1

X (µm)

Y (µm)

−2230

−2076

−1922

−1768

−1614

−1460

−1306

−1152

−998

−844

−690

−536

−382

−228

−74

Pin No.

X (µm)

668.8

Y (µm)

2517.2

2242.8

2092.8

1942.8

1792.8

1642.8

1492.8

1342.8

1192.8

1042.8

892.8

Pin No.

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

X (µm)

−1771

−1767.8

−1745

−1595

−1395

−1245

−1045

−895

Y (µm)

−757.2

1771

1418.8

1268.8

1118.8

968.8

818.8

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

2

518.8

−907.2

3

368.8

−1149.4

−1299.4

−1489.4

−1639.4

−1839.4

−1989.4

−2139.4

−2289.4

−2513.4

4

218.8

5

68.8

6

−81.2

7

−231.2

−381.2

−531.2

−681.2

−831.2

−981.2

−1131.2

−1281.2

−1431.2

−1771

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

80

234

−682.6

−532.2

−382.2

−106.6

69.8

388

542

696

850

1004

1158

1312

1466

1620

1774

1928

2082

2236

2517.2

219.8

369.8

569.8

719.8

742.8

952.4

592.8

1102.4

1252.4

1402.4

1552.4

442.8

292.8

142.8

−7.2

−157.2

−307.2

−457.2

−607.2

5

Data Sheet S10561EJ5V0DS00

µ

PD16676

5. PIN DESCRIPTIONS

5.1 Power System

Pin Symbol

V^DD

Pin Name

Pin No.

87

I/O

—

Function Description

Power supply pin

Ground

Power supply

Ground

V^SS

78

V^LC1to V^LC5

Reference power supply for

drivers

90,91,92,

94,95

Reference power supply for LCD driving

5.2 Logic system

Pin Symbol

Pin Name

Pin No.

93

I/O

Function Description

Input

M,/S

Master/Slave selection

Switches between the master chip and the slave

chip.

Input/

FR

LCD to AC signal

89

Exchanges synchronizing signals (LCD-to-AC

signals) in connecting cascades.

This pin is for output if the chip is the master, and for

input if the chip is the slave.

Output

Input/

Output

Input

DB⁰to DB⁷

A0

Data Bus

79 to 86

73

Data inputs/outputs

Data/Instruction Switching

This pin is used for switching between the display

data and the instruction.

High level : Display data

Low level : Instruction

Input

/RESET

Reset and 68/80-series

switching

88

This pin performs reset at the edge of the low-level

pulse. At that level, it performs switching 68/80

series modes.

High level : 68 series MPU interface

Low level : 80 series MPU interface

68 series mode : Enable signal

80 series mode : Read enable signal

68 series mode : Read/Write signal

80 series mode : Write enable signal

Oscillation (connected with a register between

OSC²)

Input

E(/RD)

R,/W(/WR)

OSC¹

Enable and read enable

76

77

74

75

Read/Write and Write

enable

Input

Oscillation pin

Output

OSC²

Oscillation pin

Oscillation (connected with a register between

OSC¹)

5.3 Driver System

Pin Symbol

Pin Name

Pin No.

I/O

Description

Output

SEG⁰to

SEG⁶⁰

Segment

72 to 12

Segment output pins

Output

COM⁰to

COM¹⁵

Common

96 to 100,

1 to 11

Common output pins

If the chip is a slave, these pins correspond to

COM¹⁶to COM³¹.

6

Data Sheet S10561EJ5V0DS00

µ

PD16676

6. COMMANDS

Command

/RD /WR A0 DB⁷DB⁶DB⁵DB⁴DB³DB²DB¹DB⁰

Function

1

Display ON/OFF

1

0

1

0

1

0

1

0/1 ON/OFF of the whole display is

performed independent of the

display RAM’s data or internal

state.

1: ON, 0: OFF (Power save at

static drive ON)^Note

2

Display start line

Page address set

1

0

1

0

1

Display start address

(0 to 31)

Determines the RAM line

displayed on the uppermost line

(COM⁰) of the display.

Sets display RAM pages in the

page address register.

Sets display RAM’s column

address in the column address

register.

3

4

1

0

1

0

1

0

Pages

(0 to 3)

Column(segment)

address set

Column addresses

(0 to 79)

5

Status read

0

1

0

B

U

S

Y

A

D

C

O

N

/

O

F

R

E

S

E

T

0

Reads status

BUSY

1: During internal operation

0: READY status

ADC

1: Clockwise output(Normal

rotation)

0: Counterclockwise output

(Reverse)

ON/OFF

1: Display OFF, 0: Display ON

RESET

1: Being reset, 0: Normal

6

Display data write

1

0

1

Write Data

Read data

Displays the

data bus data

and writes it

onto the

display RAM.

Reads the data column

in the display

RAM onto the incremented.

data bus.

Accesses the

display RAM of

a pre-specified

address. After

access, the

7

8

Display data read

ADC select

0

1

0

1

0

address is

1

0

1

0

0/1 This command is used to

reverse the correspondence

relationship between display

RAM’s column addresses and

segment driver outputs.

0: Clockwise output (Normal

rotation)

1: Counterclockwise output

(Reverse)

9

Static drive

ON/OFF

1

0

1

0

1

0

1

0

0/1 Selects between the normal

display operation and the static

all-lamp-driven display.

1: Static drive (Power save)^Note

0: Normal display operation

0/1 Selects between two different

liquid-crystal cell driving duties.

1: 1/32 duty

10 Duty select

1

0

1

0

1

0

1

0

0: 1/16 duty

11 Read modify write

0

Increments the column address

counter only when writing the

display data; but not when

reading it.

12 END

13 Reset

1

0

1

0

1

0

1

0

1

0

Cancels read modify write mode

Sets the display start line

register to the first line.

Sets the column address

counter and the page address

register to 0.

Note If the static drive is turned ON in the display OFF state, the machine is placed in the power save state.

7

Data Sheet S10561EJ5V0DS00

µ

PD16676

7. DISPLAY RAM MAP

Column Address

0

79

DB0

Page 0

(640 bits)

DB7

7

8

Page 1

(640 bits)

15

16

Page 2

(640 bits)

23

24

Page 3

(640 bits)

31

Line Address

8

Data Sheet S10561EJ5V0DS00

µ

PD16676

•

8. Line Address Circuit

As is shown in Figure 8-1, the line address circuit specifies the line address that corresponds to a COM output for

displaying the contents of display data RAM. The display start line address set command specifies line address of to

0

the COM output.

The screen can be scrolled by dynamically changing the line address via the display start line address set

command.

Figure 8-1. Specification of Display Start Line Address in Display Data RAM

Page

Line

Address

COM

Output

Data

₁DB

DB

0

COM⁰

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

Page0

0

1

0

1

Page1

Page2

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1

Page3

Remark

COM¹⁶to COM³¹are valid in only 1/32 duty.

9

Data Sheet S10561EJ5V0DS00

µ

PD16676

•

9. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T^A= 25 °C, V^SS= 0 V)

Parameter

Symbol

Rating

Unit

V

Supply voltage

V^DD

V^LC1to V^LC4

V^LC5

–0.3 to +6.5

Driver reference supply input voltage

Logic system input voltage

V^DD–13 to V^DD+0.3

V^DD–13 to +0.3

−0.3 to V^DD+ 0.3

V^LC5–0.3 to V^DD+ 0.3

−40 to +85

V

V^IN1

V

Logic system output voltage

Logic system input/output voltage

Driver system output voltage

Operating ambient temperature

Storage temperature

V^OUT1

V^I/O1

V^OUT2

T^A

V

°C

T^stg

−65 to +150

Cautions 1. If the absolute maximum rating of even one of the above parameters is exceeded even

momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,

specify the values exceeding which the product may be physically damaged. Be sure to use the

product within the range of the absolute maximum ratings.

2. Ensure that the phase relationship is V^DD≥ V^LC1≥ V^LC2≥ V^LC3≥ V^LC4≥ V^LC5.

Recommended Operating Range (V^SS= 0 V)

Parameter

Symbol

MIN.

2.7

TYP.

MAX.

5.5

V^DD

0

Unit

V

Supply voltage

V^DD

V^LC1to V^LC4

V^LC5

Reference supply voltage

Logic system input voltage

V^DD–12

0

V

V^IN1

V^DD

V

10

Data Sheet S10561EJ5V0DS00

µ

PD16676

Electrical Characteristics (Unless otherwise specified, T^{A =}−40 to +85 °C, V^DD= 2.7 to 5.5 V)

Parameter

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

High-level output voltage

Symbol

V^IH1

Condition

A0, DB⁰to DB⁷, E, R,/W

FR, M,/S, /RESET

MIN.

TYP.^Note

MAX.

Unit

V

0.8 V^DD

V^IH2

V^IL1

V^IL2

I^IH

V

A0, DB⁰to DB⁷, E, R,/W

FR, M,/S, /RESET

0.2 V^DD

1

V

A0, E, R,/W, /RESET

µA

V

I^IL

–1

V^OH1

I^OUT= –3 mA, DB⁰to DB⁷,

V^DD= 4.5 to 5.5 V

0.8 V^DD

High-level output voltage

V^OH2

V^OH3

I^OUT= –2 mA, FR, V^DD= 4.5 to 5.5 V 0.8 V^DD

V

I^OUT= –120 µA, OSC²,

V^DD= 4.5 to 5.5 V

0.8 V^DD

Low-level output voltage

V^OL1

I^OUT= 3 mA, DB⁰to DB⁷,

V^DD= 4.5 to 5.5 V

0.2 V^DD

V

Low-level output voltage

V^OL2

V^OL3

I^OUT= 2 mA, FR, V^DD= 4.5 to 5.5 V

0.2 V^DD

V

I^OUT= 120 µA, OSC²,

V^DD= 4.5 to 5.5 V

High-level output voltage

V^OH1

I^OUT= –1.5 mA, DB⁰to DB⁷,

V^DD= 2.7 to 4.5 V

0.8 V^DD

V

High-level output voltage

V^OH2

V^OH3

I^OUT= –1 mA, FR, V^DD= 2.7 to 4.5 V 0.8 V^DD

V

I^OUT= –80 µA, OSC²,

0.8 V^DD

V^DD= 2.7 to 4.5 V

Low-level output voltage

V^OL1

I^OUT= 1.5 mA, DB⁰to DB⁷,

V^DD= 2.7 to 4.5 V

0.2 V^DD

V

Low-level output voltage

V^OL2

V^OL3

I^OUT= 1 mA, FR, V^DD= 2.7 to 4.5 V

0.2 V^DD

V

I^OUT= 80 µA, OSC²,

V^DD= 2.7 to 4.5 V

High-level leak current

I^LOH

I^LOL

R^ON

I^DD0

I^DD1

DB⁰to DB⁷, V^IN/OUT= V^DD

3

µA

kΩ

µA

pF

Low-level leak current

DB⁰to DB⁷, V^IN/OUT= V^SS

–3

Driver output ON resistor

Static current consumption

Dynamic current consumption

T^A= 25 °C, V^DD= 5 V, V^LC5= V^SS

T^A= 25 °C, V^DD= 3.5 V, V^LC5= V^SS

7.5

50

1.0

15.0

30.0

500

8.0

21

External clock: 18 kHz

Self-oscillation: R = 1.3 MΩ

During access: t^CYC= 200 kHz

T^A= 25 °C, f = 1 MHz

Dynamic current consumption

Input capacitance

I^DD3

C^IN

Oscillator frequency

f^OSC

In self-oscillation, V^DD= 5.0 V,

15

11

18

16

kHz

2%

R = 1.3 MΩ ±

In self-oscillation, V^DD= 3.0 V,

2%

Oscillator frequency

f^OSC

21

kHz

R = 1.3 MΩ ±

/RESET↓→Internal reset release

Reset time

t^R

1.0

1000

µs

Remark The TYP. value is a reference value when T^A= 25 °C.

11

Data Sheet S10561EJ5V0DS00

µ

PD16676

4

AC Characteristics 1 (Unless otherwise specified, T^A= − 0 to +85 °C, V^DD= 4.5 to 5.5 V)

80 Series MPU Read/Write Timing

Parameter

Address hold time

Symbol

t^AH8

Condition

MIN.

10

TYP.

MAX.

Unit

ns

A0

Address setup time

System cycle time

Control pulse width

Data setup time

t^AW8

t^CYC8

t^CC

20

/WR, /RD

DB⁰to DB⁷

1000

200

80

t^DS8

t^DH8

t^ACC8

t^OH8

Data hold time

10

/RD access time

Output disable time

DB⁰to DB⁷, C^L= 100 pF

90

60

10

68 Series MPU Read/Write Timing

Parameter

Symbol

Condition

A0, R,/W

MIN.

1000

20

TYP.

MAX.

Unit

ns

System cycle time

Address setup time

Address hold time

Data setup time

Data hold time

t^CYC6

t^AW6

t^AH6

t^DS6

t^DH6

t^OH6

t^ACC6

t^EW

10

DB⁰to DB⁷

80

10

Output disable time

Access time

DB⁰to DB⁷, C^L= 100 pF

10

60

90

Enable pulse width

READ

E

100

80

WRITE

12

Data Sheet S10561EJ5V0DS00

µ

PD16676

4

AC Characteristics 2 (Unless otherwise specified, T^A= − 0 to +85 °C, V^DD= 2.7 to 4.5 V)

80 Series MPU Read/Write Timing

Parameter

Address hold time

Symbol

t^AH8

Condition

MIN.

20

TYP.

MAX.

Unit

ns

A0

Address setup time

System cycle time

Control pulse width

Data setup time

t^AW8

t^CYC8

t^CC

40

/WR, /RD

DB⁰to DB⁷

2000

400

160

20

t^DS8

t^DH8

t^ACC8

t^OH8

Data hold time

/RD access time

Output disable time

DB⁰to DB⁷, C^L= 100 pF

180

120

20

68 Series MPU Read/Write Timing

Parameter

Symbol

Condition

A0, R,/W

MIN.

2000

40

TYP.

MAX.

Unit

ns

System cycle time

Address setup time

Address hold time

Data setup time

Data hold time

t^CYC6

t^AW6

t^AH6

t^DS6

t^DH6

t^OH6

t^ACC6

t^EW

20

DB⁰to DB⁷

160

20

Output disable time

Access time

DB⁰to DB⁷, C^L= 100 pF

20

120

180

Enable pulse width

READ

E

200

160

WRITE

13

Data Sheet S10561EJ5V0DS00

µ

PD16676

Test Point of Switching Characteristics

V

IH

V

IH

Input

V

IL

V

IL

V

OH

V

OH

Output

V

OL

V

OL

Waveforms of Switching Characteristics

80 Series MPU Read/Write Timing

t

AH8

A0

t

CYC8

CC

t

AW8

t

/WR,/RD

t

DH8

t

DS8

DB

0

- DB

7

(WRITE)

t

ACC8

t

OH8

DB

0

- DB

7

(READ)

68 Series MPU Read/Write Timing

t

CYC6

E

R,/W

A0

t

AW6

t

EW

t

AH6

t

DH6

t

DS6

DB

0

- DB

7

(READ)

t

OH6

t

ACC6

DB

0

- DB

7

(READ)

14

Data Sheet S10561EJ5V0DS00

µ

PD16676

Reset

/RESET

t

R

Internal Status

Reset status

OSC

1/f^OSC

15

Data Sheet S10561EJ5V0DS00

µ

PD16676

•

10. Application Circuit Example

VDD

FR

M,/S

OSC

1

µPD16676

Master Chip

OSC

2

61 SEG

16 COM

LCD

16 COM

61 SEG

A0,

/RESET,

4

M,/S

GND

PD16676

Slave Chip

µ

E,/RD,

R,/W, /WR

OSC

1

8

FR

DB0

- DB

7

16

Data Sheet S10561EJ5V0DS00

µ

PD16676

•

11. PACKAGE DRAWING

100 PIN PLASTIC QFP (14x20)

A

B

80

81

51

50

detail of lead end

S

C D

R

Q

31

30

100

1

F

M

J

G

H

I

P

K

M

S

N

S

L

NOTE

Each lead centerline is located within 0.15 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

23.2±0.2

20.0±0.2

14.0±0.2

D

F

17.2±0.2

0.8

G

H

0.6

0.32±0.08

I

0.15

J

K

L

0.65 (T.P.)

1.6±0.2

0.8±0.2

+0.08

M

0.17

−0.07

0.10

N

P

Q

R

S

2.7

0.125±0.075

5°±5°

2.825±0.175

S100GF-65-3BA-4

17

Data Sheet S10561EJ5V0DS00

µ

PD16676

•

12. RECOMMENDED SOLDERING CONDITIONS

Please consult with our sales offices for soldering conditions of the µPD16676.

Type of Surface Mount Device

µPD16676GF-3BA : 100-PIN PLASTIC QFP (14 x 20 mm)

18

Data Sheet S10561EJ5V0DS00

µ

PD16676

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

19

Data Sheet S10561EJ5V0DS00

µ

PD16676

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M7 98. 8


型号：	UPD16676W
厂家：	NEC
描述：	1/16, 1/32 DUTY LCD CONTROLLER/DRIVER 1/16 ， 1/32 DUTY LCD控制器/驱动显示驱动器驱动程序和接口接口集成电路控制器 CD
文件：	总20页 (文件大小：117K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD16676W [NEC]

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