UPD16680W [RENESAS]
LIQUID CRYSTAL DISPLAY DRIVER, UUC, WAFER;型号: | UPD16680W |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | LIQUID CRYSTAL DISPLAY DRIVER, UUC, WAFER 驱动 接口集成电路 |
文件: | 总46页 (文件大小:411K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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April 1st, 2010
Renesas Electronics Corporation
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16680
1/53, 1/40 DUTY, LCD CONTROLLER/DRIVER WITH BUILT-IN RAM
DESCRIPTION
The µPD16680 is a driver which contains a RAM capable of full - dot LCD display. The single µPD16680 IC chip can
operate a full - dot (up to 100 by 51 dots) LCD and pictographs (100 pictographs).
The µPD16680 can operate on single 3 V-power supply, is suitable for graphic pagers and cellular.
FEATURES
• LCD driver with a built-in display RAM
• Can operate on single 3 V-power supply
• Booster circuit incorporated : Switchable 3 or 4 folds
• Dot display RAM : 100 x 51 bits
• Pictographic display RAM : 100 bits
• Pictographic display's duty changeable : 1/53 or 1/40 duty
• Output for full-dot : 100 segments and 52 commons
• Data input based on serial & 4-bit / 8-bit parallel switch over
• String resister to output bias level incorporated
• Selectable LCD driving bias level (select from 1/8 bias, 1/7 bias, 1/6 bias)
• Oscillation circuit incorporated
• D/A converter incorporated (for LCD driving voltage adjustment)
ORDERING INFORMATION
Part number
Package
µPD16680W/P
Wafer/Chip(Matched COG mounting)
Remark Purchasing the above products in term of chips per requires an exchange of other documents as well,
including a memorandum on the product quality. Therefore those who are interested in this regard are
advised to contact an NEC salesperson for further details.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published July 1999 NS CP(K)
Printed in Japan
S12694EJ2V0DS00(2nd edition)
The mark • shows major revised points.
1997, 1999
©
µPD16680
1. BLOCK DIAGRAM
Remark /xxx indicates active low signals.
2
Data Sheet S12694EJ2V0DS00
µPD16680
2. PIN CONFIGURATION (Top view)
Chip Size : 12.5 mm x 1.89 mm
249
115
250
114
Y
X
264
100
1
99
3
Data Sheet S12694EJ2V0DS00
µPD16680
Table 2-1. Pad Layout (1/2)
Pin No.
Pin Name
Pin No.
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Pin Name
X(µm)
–5883.2
–5763.2
–5643.2
–5523.2
–5403.2
–5283.2
–5163.2
–5043.2
–4923.2
–4803.2
–4683.2
–4563.2
–4443.2
–4323.2
–4203.2
–4083.2
–3963.2
–3843.2
–3723.2
–3603.2
–3483.2
–3363.2
–3243.2
–3123.2
–3003.2
–2883.2
–2763.2
–2643.2
–2523.2
–2403.2
–2283.2
–2163.2
–2043.2
–1923.2
–1803.2
–1683.2
–1563.2
–1443.2
–1323.2
–1203.2
–1083.2
–963.2
–843.2
–723.2
–603.2
–483.2
–363.2
–243.2
–123.2
–3.2
Y(µm)
–811.0
X(µm)
2036.8
Y(µm)
–811.0
+
1
2
3
4
5
6
7
8
Dummy
Dummy
Dummy
VLCBS1
VLCBS1
Dummy
VLCBS2
VLCBS2
Dummy
VLCBS3
VLCBS3
Dummy
AMPOUT
AMPOUT
Dummy
AMPIN(-)
AMPIN(-)
Dummy
AMPIN(+)
AMPIN(+)
Dummy
VDD
VDD
Dummy
VLC5
VLC5
VLC5
Dummy
VLC4
VLC4
VLC4
Dummy
VLC3
VLC3
VLC3
Dummy
VLC2
VLC2
VLC2
Dummy
VLC1
VLC1
VLC1
Dummy
VLCD
VLCD
VLCD
VDD
VDD
VDD
VSS
VSS
C3
+
+
–
–
–
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
C3
C3
C3
C3
C3
2156.8
2276.8
2396.8
2516.8
2636.8
2756.8
2876.8
2996.8
3116.8
3236.8
3356.8
3476.8
3596.8
3716.8
3836.8
3956.8
4076.8
4196.8
4316.8
4436.8
4556.8
4676.8
4796.8
4916.8
5036.8
5156.8
5276.8
5396.8
5516.8
5636.8
5756.8
5876.8
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6112.0
6030.0
5940.0
5850.0
5760.0
5670.0
5580.0
5490.0
5400.0
5310.0
5220.0
5130.0
5040.0
4950.0
4860.0
4770.0
4680.0
4590.0
4500.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–811.0
–682.2
–592.2
–502.2
–412.2
–322.2
–232.2
–142.2
–52.2
37.8
127.8
217.8
307.8
397.8
487.8
577.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
VDD
VDD
VDD
Dummy
VEXT
DACHA
AMPCHA
OSCIN
OSCOUT
VDD
OSCBRI
D0(DATA)
D1
D2
D3
D4
D5
D6
D7(NS)
WS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
STB
E(SCK)
/RESET
VDD
TESTOUT
Dummy
Dummy
Dummy
Dummy
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
Dummy
Dummy
Dummy
Dummy
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
PCOM
SEG100
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
116.8
236.8
356.8
476.8
596.8
716.8
836.8
956.8
1076.8
1196.8
1316.8
1436.8
1556.8
1676.8
1796.8
1916.8
VSS
Dummy
+
C1
+
C1
+
C1
–
C1
–
C1
–
C1
+
C2
+
C2
+
C2
–
C2
–
C2
–
C2
817.8
4
Data Sheet S12694EJ2V0DS00
µPD16680
Table 2-1. Pad Layout (2/2)
Pin No.
Pin Name
Pin No.
Pin Name
X(µm)
4410.0
Y(µm)
817.8
X(µm)
–1530.0
–1620.0
–1710.0
–1800.0
–1890.0
–1980.0
–2070.0
–2160.0
–2250.0
–2340.0
–2430.0
–2520.0
–2610.0
–2700.0
–2790.0
–2880.0
–2970.0
–3060.0
–3150.0
–3240.0
–3330.0
–3420.0
–3510.0
–3600.0
–3690.0
–3780.0
–3870.0
–3960.0
–4050.0
–4140.0
–4230.0
–4320.0
–4410.0
–4500.0
–4590.0
–4680.0
–4770.0
–4860.0
–4950.0
–5040.0
–5130.0
–5220.0
–5310.0
–5400.0
–5490.0
–5580.0
–5670.0
–5760.0
–5850.0
–5940.0
–6030.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
–6112.0
Y(µm)
817.8
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
4320.0
4230.0
4140.0
4050.0
3960.0
3870.0
3780.0
3690.0
3600.0
3510.0
3420.0
3330.0
3240.0
3150.0
3060.0
2970.0
2880.0
2790.0
2700.0
2610.0
2520.0
2430.0
2340.0
2250.0
2160.0
2070.0
1980.0
1890.0
1800.0
1710.0
1620.0
1530.0
1440.0
1350.0
1260.0
1170.0
1080.0
990.0
900.0
810.0
720.0
630.0
540.0
450.0
360.0
270.0
180.0
90.0
0.0
–90.0
–180.0
–270.0
–360.0
–450.0
–540.0
–630.0
–720.0
–810.0
–900.0
–990.0
–1080.0
–1170.0
–1260.0
–1350.0
–1440.0
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
817.8
577.8
487.8
397.8
307.8
217.8
127.8
37.8
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
Dummy
Dummy
Dummy
Dummy
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
PCOM
Dummy
Dummy
-52.2
-142.2
-232.2
-322.2
-412.2
-502.2
-592.2
-682.2
5
Data Sheet S12694EJ2V0DS00
µPD16680
3. PIN DESCRIPTIONS
3.1 Power System Pins
Pin Symbol
VDD
Pin Name
Pin No.
I/O
-
Function Description
Logic and booster power
supply pin
22, 23,
48 to 50,
73 to 75,
82, 96
Power supply pin for logic and booster circuit.
VSS
Logic and driver ground
pin
51 to 53
-
-
Ground pin for logic and driver circuit.
VLCD
Driver power supply pin
45 to 47
Driver power supply pin. Output pin of internal booster circuit.
Please connect with a 1 µF booster capacitor to ground.
When not using the internal booster circuit, the driver power
can be turned on directly.
★
VLC1 to VLC5
Driver reference power
supply
25 to 27,
29 to 31,
33 to 35,
37 to 39,
41 to 43
4, 5, 7,
-
Reference power supply pin for LCD drive.
When the internal bias is selected, be sure to leave it open.
When display contrast is bad, connect a capacitor between
these pins and ground.
VLCBS1 to
VLCBS3
Bias level select pin
-
-
When the internal bias is selected, Connecting these pins
outside the IC, the bias level can be changed.
Capacitor connection pins for booster circuit. When using
internal booster circuit, connect a 1µF capacitor between
these pins.
8, 10, 11
55 to 72
–
C1+, C1
Capacitor connection pins
–
C2+, C2
–
C3+, C3
6
Data Sheet S12694EJ2V0DS00
µPD16680
3.2 Logic System Pins (1/2)
Pin Symbol
WS
Pin Name
Pin No.
92
I/O
I
Function Description
This pin selects the word length.
At High level, it become an 8-bit parallel interface.
Word length select pin
(Word Select)
At Low level, when D7(NS) is High level, it become a serial
interface.
When the word length is 4 bits, data is transferred in the
upper-to-low sequence by mean of data busses D0 to D3.
The word length cannot be changed after power-on.
This pin selects whether to use the internal D/A converter for
LCD driving voltage adjustment or not.
DACHA
STB
D/A converter select pin
Strobe
78
93
I
I
At High level, D/A converter is used. At Low level, unused.
This pin is select signal of device, strobe signal for data
transfer. Data transfer is initialized at falling/rising edge of
STB.
Data can be input/output at Low level either in parallel
interface or serial interface mode.
When STB is High level, Enable/shift clock is bypassed.
When using parallel interface mode, this pin becomes the
data enable input. In reading-in, data is fetched into the
interface buffer at rising edge. In reading-out, data is fetched
from interface buffer at falling edge.
E(SCK)
Enable(shift clock)
94
I
When using serial interface mode, this pin becomes the data
shit clock.
In reading-in, data is fetched into the interface buffer at rising
edge.
In reading-out, data is fetched from interface buffer at falling
edge.
D0(DATA)
Data-bus(data)
84
I/O
When using parallel interface mode, this pin becomes the D0
bit of data-bus.
When using serial interface mode, this pin becomes the
input/output pin of the command and display data (3 states).
When using parallel interface mode, these pin becomes the
D1 to D3 bits of data-bus. When using serial interface mode,
keep them H or L.
D1 to D3
D4 to D6
D7(NS)
Data-bus
85 to 87
88 to 90
91
I/O
I/O
I/O
Data-bus
When using parallel interface mode, these pin become the D4
to D6 bits of data-bus. When using serial interface mode, keep
them H or L.
Data-bus(nibble select)
When word select (WS) is High level, this pin becomes the D7
bit of data-bus.
When word select (WS) is Low level, This pin becomes nibble
select pin. At High level, selected 4-bit parallel interface.
At Low level, selected serial interface.
TESTOUT
/RESET
TEST signal output
Reset
97
95
O
I
When to do test, this pin is output for test signal.
When using in normal operation, this pin leave open.
At Low level, the µPD16680 is initialized.
7
Data Sheet S12694EJ2V0DS00
µPD16680
3.2 Logic System Pins (2/2)
Pin Symbol
AMPCHA
Pin Name
Pin No.
79
I/O
I
Function Description
Select operational amplifier mode.
Amp mode select pin
At High level, “Level capacitor mode”.
At Low level, “LCD driving mode”.
VEXT
LCD reference supply
switching
77
I
Select the method for supplying LCD power circuit. At High
level, LCD driving voltage is supplied external circuit. At Low
level, it is supplied internal circuit.
These pins are connected with the 1 MΩ resistor. When using
external oscillation, input into the OSCIN , and leaving the
OSCOUT open.
OSCIN
Oscillation pin
Blinking Clock
80
81
83
I
O
I
OSCOUT
OSCBRI
This pin is oscillation input for Blinking. To input 2 Hz external
clock, when to use Blinking by external clock mode.
When not to use this pin, keep it H or L.
8
Data Sheet S12694EJ2V0DS00
µPD16680
3.3 Driver System Pins
Pin Symbol
Pin Name
Pin No.
I/O
O
Function Description
SEG1 to
SEG100
COM1 to
COM51
Segment
132 to 231
Segment output pins.
Common
102 to 112,
117 to 130,
232 to 247,
252 to 261
131, 262
O
Common output pins
PCOM
Pictographic common
O
I
Common output pins for pictograph.
(Same waveform output from these pins.)
AMPIN(+)
Operational amplifier input
19, 20
These pins are the input pins of operational amplifier for LCD
driving voltage adjustment.
When using the internal D/A converter, leave AMPIN(+) open.
When not using the internal D/A converter, it is necessary to
input the reference voltage.
AMPIN(-)
AMPOUT
16,17
13,14
AMPIN(–) is connected to the resister for LCD driving voltage
adjustment.
See 4. LCD DRIVING VOLTAGE CONTROL CIRCUIT.
This is the input pin of operational amplifier for LCD driving
voltage adjustment. Normally it is connected to the resister for
LCD driving voltage adjustment. See 4. LCD DRIVING
VOLTAGE CONTROL CIRCUIT. It recommends to connect to
this pin a 0.1 to 1 µF capacitor to make the output of the
internal operational amplifier be stable.
Operational amplifier
output
O
Dummy
Dummy pad
1, 2, 3, 9, 12,
15, 18, 21,
24, 28, 32,
33, 40, 44,
54, 76,
-
Dummy pins are not connected to the internal circuit. Leave
open if they are not used.
98 to 101,
113 to 116,
248 to 251,
263, 264
4. LCD DRIVING VOLTAGE CONTROL CIRCUIT
DACHA
D/A
Converter
V
EXT
Reference power circuit
+
AMPIN(+)
−
VLCBS1
AMPIN(−)
AMPout
VLC1
V
LC2
V
LC3
V
LCBS3
VLC4
VLC5
VSS
VLCBS2
R2
C1
R1
9
Data Sheet S12694EJ2V0DS00
µPD16680
5. POWER CIRCUIT
The µPD16680 incorporate the booster circuit is switchable between 3 and 4 folds. The boosting magnitude of
internal booster circuit is selected by the capacitor connection.
The reference power circuit is switchable between internal driving circuit and external driving circuit. The method
for supplying the reference circuit selected by VEXT pin (H : External, L : Internal ).
5.1 Booster circuit
–
–
Using Internal driving circuit, to connect condenser for boosting between C1+ and C1 , C2+ and C2 , C3+ and C3– , to
connect condenser between VLCD and VDD to be stable boosting voltage. And to set VEXT pin to low level, internal
booster circuit boost voltage between VDD and VSS to 3 or 4 folds.
The booster circuit is using clock made by internal oscillation circuit. It is necessary that oscillation to be operated.
+
+
–
C1 , C1– ,C2+ ,C2– ,C3 ,C3 , V are pins for booster circuit. To use the wire that have low register value to connect
DD
these pins.
Figure 5-1 3x and 4x Booster Circuits
VLCD = 4VDD = 12 V
(4-fold boost)
VLCD = 3VDD = 9 V
(3-fold boost)
VDD = 3 V
VSS = 0 V
–
–
Remarks 1. When to use 3-fold booster circuit, not to connect condenser between C3+ and C2 , C1+ and C1 , leave
–
open C2+ and C3 .
2. When to use external power supply circuit, booster circuit is not operating.
10
Data Sheet S12694EJ2V0DS00
µPD16680
5.2 LCD driving circuit
5.2.1 To use internal driving circuit, not to use D/A converter ( VEXT = L , DACHA = L )
When to internal driving circuit is chosen, boosted voltage be used for power of internal operational amplifier
1
2
(+)
adjusting LCD driving voltage. To connect external resister R , R , and input reference voltage to AMPIN pin. It is
possible to adjust LCD driving voltage of VLC1 . If using thermistor to adjust LCD driving voltage according to the
2
temperature characteristic of LCD panel, we recommend connecting it with R in parallel.
The value of VLC1 can be computed by the following formula.
Equation 5-1
R2
′
R1
VLC1 = AMPIN(+) = (1+
) VREF
2
th
R x R
Remark R2′ =
2
th
R + R
Figure 5-2 When not using Internal power supply select or D/A converter
DACHA
D/A
Converter
VREF
to Internal driving circuit
+
AMPIN(+)
−
AMPIN(-)
AMPout
VLC1
Rth
R2
R1
C1
11
Data Sheet S12694EJ2V0DS00
µPD16680
5.2.2 To use internal driving circuit and D/A converter ( VEXT = L , DACHA = H )
(+)
To use D/A converter, it is possible to adjust reference voltage VREF inputted to AMPIN pin for LCD driving by
command.
To set 6-bit data to D/A converter register, reference voltage VREF is choose one level from 64 level in 1/2 VDD to VDD
.
The formula of VLC1 is as same written in Equation 5-1.
Figure 5-3 Using internal power supply select and D/A converter
VDD
VDD
D/A
Converter
DACHA
to Internal driving circuit
VREF
+
AMPIN(+)
Open
−
AMPIN(-)
AMPout
VLC1
Rth
R2
R1
C1
.
5.2.3 To use external driving circuit ( VEXT = H )
When external voltage supply circuit for LCD driving is chosen, operational amplifier incorporated IC is off.
Therefore, it is impossible to use operational amplifier for LCD driving and D/A converter function. LCD driving
voltage is adjust by the voltage inputted to VLCD and VLC1 pins directly.
Remarks 1. Set VLCD ≥ VLC1.
2. DACHA , AMPIN(+), AMPIN(-) are CMOS input. Set H level or L level.
3. Set AMPOUT pin "open".
12
Data Sheet S12694EJ2V0DS00
µPD16680
5.3 REFERENCE VOLTAGE CIRCUIT
5.3.1 To use internal reference voltage circuit ( VEXT = L )
When internal driving circuit is chosen, 6 levels for LCD reference voltage (VLC1, VLC2, VLC3, VLC4, VLC5, VSS) is
generate by internal breeder resister.
5.3.2 To use external driving circuit ( VEXT = H )
When external driving circuit is chosen, operational amplifier incorporated IC is Off. It is necessary to input voltage
to VLC1, VLC2, VLC3, VLC4 and VLC5 directly.
Generally, These levels are made by external breeder resister. The display dignity of LCD declines when these
resistance values are big, it is necessary to choose the resistance value which corresponds with the LCD panel.
There is an effect that improves display dignity when connecting a capacitor with each level pins and the ground. It is
necessary to choose the condenser value which corresponds with the LCD panel.
Figure 5-3. Reference voltage circuit
★
AMPOUT
V
LC1
+
−
to SEG, COM Outputs
R
R
V
LC2
+
−
to COM Output
V
LC3
+
−
to SEG Output
VLCBS1
Voltage follower for level voltage
R
R
R
V
LCBS2
VLCBS3
V
LC4
+
−
to SEG Output
R
R
V
LC5
+
−
to COM Output
V
SS
to SEG, COM Output
13
Data Sheet S12694EJ2V0DS00
µPD16680
5.4 Setting BIAS value
When internal driving circuit chosen, by connecting the interval of the pin VLCBS1, VLCBS2, VLCBS3 outside the IC, the
bias value can be set from the 1/6 bias, the 1/7 bias, the 1/8 bias.
Bias value
1/8 bias
Pin connection
LCBS1, VLCBS2, VLCBS3 All open
V
1/7 bias
1/6 bias
To connect VLCBS1 and VLCBS2, or VLCBS2 and VLCBS3
To connect VLCBS1 and VLCBS3, VLCBS2 is open.
5.5 Voltage followers for level power supply
CHA
By the input of AMP
pin, it controls voltage follower for the LCD drive level power supply.
• LCD driving mode ( AMPCHA = L )
When this mode is chosen, The voltage follower maximizes electric current supply ability for LCD drive. It
doesn't need to connect the external capacitor for the level stability.
• Level capacitor mode ( AMPCHA = H )
When this mode is chosen, The voltage follower maximizes electric current supply ability for the external
condenser charging. In this mode, it needs to connect the external capacitor ( 0.1 to 1.0 µF ) for the level stability.
Caution When using this mode without connecting capacitor, the display dignity will be bad.
14
Data Sheet S12694EJ2V0DS00
µPD16680
5.6 Application circuit example
5.6.1 To use internal driving circuit, LCD driving mode
A) Boost 4folds (not to use D/A converter)
B) Boost 3 folds
V
DD
Note1
AMPIN(+)
V
V
DD
V
DD
Rth(Thermistor)
R1
R2
AMPIN(−)
LCD
V
LCD
+
+
+
C
C
C
C
2
C2
AMPOUT
+
C +
1
+
V
LC1
C1
+
+
+
1
1
1
C1
−
−
V
LC2
C
1
2
C1
+
C
+ Note2
Open
C
2
Open
−
V
LC3
C2
−
C
2
3
+
C
C1
+
+
V
V
LC4
LC5
C
3
C −
3
−
Note2
Open
C
3
V
V
EXT
SS
AMPCHA
V
V
EXT
SS
Notes 1.
IN(+)
When to use D/A converter, AMP
is open.
+
C , C – are open.
2.
2
3
Remark
µ
C1 = C2 = 1.0 m
15
Data Sheet S12694EJ2V0DS00
µPD16680
5.6.2 To use internal driving circuit, LCD driving mode
A) Boost 4folds(not to use D/A converter)
B) Boost 3 folds
VDD
Note1
V
V
DD
AMPIN(+)
V
DD
Rth(Thermistor)
R2
AMPIN(−)
LCD
VLCD
+
+
+
R1
C
C
C
C
2
C
2
AMPOUT
+
+
C +
1
VLC1
C
1
+
+
+
1
1
1
+
C1
VLC2
−
−
C
1
2
C
1
+
+
C
V
LC3
LC4
Note2
+
Open
+
C2
+
−
V
C2
−
C
2
3
+
C
C1
+
VLC5
+
C
3
+
C −
3
−
Note2
Open
C3
V
DD
V
V
EXT
SS
AMPCHA
V
EXT
SS
V
Notes 1.
2.
IN(+)
When to use D/A converter, AMP
is open.
+
C , C – are open.
2
3
Remark
µ
C1 = C2 = 1.0 m
16
Data Sheet S12694EJ2V0DS00
µPD16680
5.6.3 To use external driving circuit
To use 1/6 bias
AMPIN(+)
AMPIN(−)
AMPOUT
V
DD
Open
External power supply
VLCD
C +
1
V
LC1
R
R
−
C
1
2
V
V
V
LC2
LC3
+
C
Open
−
C
2
3
+
C
2R
R
LC4
LC5
C −
3
V
V
DD
R
V
EXT
V
SS
17
Data Sheet S12694EJ2V0DS00
µPD16680
6. LCD DRIVING
The µPD16680 is able to choose duty 1/53 duty or 140 duty.
6.1 1/53 duty driving
When 1/53 duty is chosen, the µPD16680 outputs a choice signal once at 1 frame from the dot part common
1
51
outputs (COM to COM ), the pictograph part common outputs (PCOM).
1 Frame
1
2
3
4
5
6
7
8
51 52 53
1
2
3
4
5
6
7
8
51 52 53
VLC1
VLC2
VLC3
SEG1
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
COM1
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
COM2
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
PCOM
VLC4
VLC5
VSS
18
Data Sheet S12694EJ2V0DS00
µPD16680
6.2 1/40 duty driving
When 1/40 duty is chosen, the µPD16680 outputs a choice signal once at 1 frame from the dot part common outputs
1
19
27
45
(COM to COM , COM to COM ), the pictograph part common outputs (PCOM ).
1 Frame
1
2
3
4
5
6
7
8
38 39 40
1
2
3
4
5
6
7
8
38 39 40
VLC1
VLC2
VLC3
SEG1
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
COM1
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
COM2
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
PCOM
VLC4
VLC5
VSS
19
Data Sheet S12694EJ2V0DS00
µPD16680
7. LCD DISPLAY
The µPD16680 can display 100 by 51 dots (called full-dot display) LCD display and 100 pictographs.
Figure 7-1 LCD matrix
2
4
6
8
10
12
14
16
18
90
92
94
96
98
100
1
3
5
7
9
11
13
15
17
89
91
93
95
97
99
PCOM
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM47
COM48
COM49
COM50
COM51
20
Data Sheet S12694EJ2V0DS00
µPD16680
8. GROUP ADDRESSES
8.1 Dot display
The group addresses of dot display are assigned as follows.
To be chosen the address is increment, when X address goes to 0CH, next address is 00H. At this time, Y address
goes to next address. When Y address goes to 33H, next address is 00H, too.
X address
02H
01H
0BH
0CH
00H
00H
01H
02H
03H
32H
33H
X
X
X
X
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4
Remark Data of X address = 0CH : b7 to b4 are data, b3 to b0 are don't care.
★
When 1/53 duty and using 1/40 duty are used, the RAM addresses and the common pins used are as follows.
Use RAM
Don’t use RAM
Y addresses
Use common pins
Don’t use common
pins
Duty
Y addresses
1/53 duty
1/40 duty
00H to 33H
00H to 12H
1AH to 2CHNote
-
COM1 to COM51
COM1 to COM19
COM27 to COM45
-
13H to 19H
2DH to 33H
COM20 to COM26
COM46 to COM51
Note If address incrementation is set when 1/40 duty is used, the X address value following 0CH is 00H. At the
same time the Y address is incremented by 1. The Y address value following 12H is 1AH, and the value
following 2CH is 00H.
21
Data Sheet S12694EJ2V0DS00
µPD16680
8.2 Pictograph
The group addresses of pictograph are assigned as follows.
To be chosen the address is increment, X address goes to 0CH, next address is 00H.
X address
00H 01H 02H 03H
0BH 0CH
00H
(PCOM)
b0
b5
b3
b2 b1
b7 b6
b4
8 bits
Table 8-1 PCOM (Y address = 00H)
Segment output No.
X address
b7
b6
b5
b4
b3
b2
b1
7
b0
8
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
1
2
3
4
5
6
9
17
25
33
41
49
57
65
73
81
89
97
10
18
26
34
42
50
58
66
74
82
90
98
11
19
27
35
43
51
59
67
75
83
91
99
12
20
28
36
44
52
60
68
76
84
92
100
13
21
29
37
45
53
61
69
77
85
93
X
14
22
30
38
46
54
62
70
78
86
94
X
15
23
31
39
47
55
63
71
79
87
95
X
16
24
32
40
48
56
64
72
80
88
96
X
Remark Data of X address = 0CH :b7 to b4 are data, b3 to b0 are don’t care.
22
Data Sheet S12694EJ2V0DS00
µPD16680
8.3 Blink data
The group addresses of brink data are assigned as follows.
To be chosen the address is increment, when X address goes to 0CH, next address is 00H.
X address
00H 01H 02H 03H
0BH 0CH
00H
(PCOM)
b0
b5
b3
b2 b1
b7 b6
b4
8 bits
Table 8-2 PCOM (Y address = 00H)
Segment output No.
X address
b7
b6
b5
b4
b3
b2
b1
7
b0
8
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
1
2
3
4
5
6
9
17
25
33
41
49
57
65
73
81
89
97
10
18
26
34
42
50
58
66
74
82
90
98
11
19
27
35
43
51
59
67
75
83
91
99
12
20
28
36
44
52
60
68
76
84
92
100
13
21
29
37
45
53
61
69
77
85
93
X
14
22
30
38
46
54
62
70
78
86
94
X
15
23
31
39
47
55
63
71
79
87
95
X
16
24
32
40
48
56
64
72
80
88
96
X
Remark Data of X address = 0CH :b7 to b4 are data, b3 to b0 are don’t care.
23
Data Sheet S12694EJ2V0DS00
µPD16680
9. COMMAND
9.1 Basic form
Command Register (CR)
Command Register (CR)
Address Register (CR)
Extend Select Register (ESR)
+
+
+
X address (XAD)
Data 1 (DT1)
Y address (YAD)
+
.....
+
Command Register (CR)
9.2 Command register
The command register’s basic configuration is as follows.
LSB
MSB
b7 b6 b5 b4 b3 b2 b1 b0
Choices
Command Type (0 x H to B x H)
Table 7-1 Command Table
Register
D4 D3
Command
D7
0
D6
D5
1
D2
1
D1
1
D0
1
Reset
0
0
0
0
0
1
0
0
0
0
Display ON/OFF
Standby
0
0
0
1
0
1
0
1
1
1
0
1
1
0
0
1
b2
b2
0
b1
b1
0
b0
b0
0
0
0
D/A converter setting
Duty setting
Blink setting
Data R/W mode
Test mode
0
1
0
0
b3
b2
b2
b2
b2
b1
b1
b1
b0
b0
b0
b0
0
0
1
1
1
1
24
Data Sheet S12694EJ2V0DS00
µPD16680
9.2.1 Reset
The all IC's commands are initialized.
LSB
1
MSB
0
0
1
1
1
0
0
9.2.2 Display ON/OFF
ON/OFF of the display is controlled.
LSB
MSB
0
0
0
0
1
b2 b1 b0
Choices
000 : LCD OFF (SEG
001 : LCD OFF (SEG
111 : LCD ON
n
, COM
n
, PCOM
n
n
= Vss)
n, COM
n
, PCOM
= non-serective output)
9.2.3 Standby
The DC/DC converter is stopped, thus reducing the supply current. This display is placed in the OFF state (SEGn,
COMn = VSS).
Even at Standby, it is possible to write command and data.
LSB
MSB
0
0
0
b2 b1 b0
1
0
Cohices
000 : Nomal operation
001 : Standby (DC/DC converter halt, all display OFFNote, OSC halt)
Note SEGn, COMn, PCOM = VSS
25
Data Sheet S12694EJ2V0DS00
µPD16680
9.2.4 D/A converter setting
The internal D/A converter is set. D/A converter output voltage is controlled from 1/2V to V
DD
DD
.
LSB
0
MSB
0
LSB
MSB
0
0
1
0
0
0
b5 b4 b3 b2 b1 b0
0
1
+
Extend Choices
D/A Converter output voltage
00H(MIN.) to 3FH(MAX.)
Caution After resetting, it is set to 20H.
9.2.5 Duty setting
The duty is set.
LSB
MSB
0
0
0
b2 b1 b0
1
1
Choices
000 : 1/53 duty
001 : 1/40 duty Note
Note If the duty cycle is 1/40, leave open from COM39 to COM51.
9.2.6 Blink setting
The blinks of the pictograph of the address whose blink data is “1” are controlled.
LSB
MSB
0
1
0
b2 b1 b0
0
0
Choices
000 : Blink halt
001 : Blink start (Blink frequency = fOSC/32768)
010 : Blink start (Blink frequency = fBRI Note /2)
Note This refers to the frequency of the external clock which is input from the OSCBR1 pin.
26
Data Sheet S12694EJ2V0DS00
µPD16680
9.2.7 Data R/W mode
Data Read/Write (R/W), increment, address counter resetting, etc. are set in this mode.
DATA
LSB
LSB
MSB
1
MSB
. . .
0
1
b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
+
+
Choices 1
00 : The address is incremented starting from the current one Note1
01 : Current address retained
Choices 2
0 : Data writing
1 : Data reading Note2
Notes 1. When X address and Y address goes to last address, next address is 00H.
2. The data read mode is canceled at STB's rising edge (Switched to data write mode).
Remark When using serial data transfer, it is necessary to write 8-bit data. No assurance is IC's operation when
STB is rising during data transfer.
9.2.8 Test mode
The test mode is set. The test mode is for checking IC’s operation, and no assurance is made for its regular use or
continued operation.
LSB
MSB
1
0
1
b2 b1 b0
1
1
000 : Nomal Operation
001 to 111 : Test mode
27
Data Sheet S12694EJ2V0DS00
µPD16680
★
9.3 Address register
Selects the address type and specifies the address.
MSB
1
LSB
0
MSB
0
LSB
MSB
0
LSB
1
b5
0
0
0
0
0
b3 b2 b1 b0
0
b5 b2 b1 b0
b4 b3
b4
0
+
+
Y address
Dot display group address : 00H to 33H
Pictograph group address : 00H
Blink group address : 00H
X address
Dot display group address : 00H to 0CH
Pictograph group address : 00H to 0CH
Blink group address : 00H to 0CH
Choice1
00 : Dot address
01 : Pictograph group address
10 : Blink data group address
Caution If unspecified addresses have been set, operation is not assured.
10. RESETTING
When reset (command reset, hardware (terminal) reset), the contents of each register are as follows.
Register contents
Register name
Status
b7 b6 b5 b4 b3 b2 b1 b0
Display ON / OFF
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LCD OFF (SEGn, COMn, PCOM = VSS)
Standby
Normal operation
Duty setting
1/53 duty
D/A converter setting
Blink setting
To set 20H
Blink halt
Data R/W mode
Data write, the address is incremented(+1) starting
from current address.
Test mode
1
0
1
1
1
0
0
0
Normal operation
28
Data Sheet S12694EJ2V0DS00
µPD16680
11. COMMUNICATION FORMAT
11.1 serial
11.1.1 Reception 1 (Command/Data write : 1 byte)
STB
DATA
SCK
b7
b6
b5
b2
b1
b0
1
2
3
6
7
8
11.1.2 Reception 2 (Command/Data write : 2 bytes or more)
STB
b7
b6
b5
b2
b1
b0
b6
b5
b4
b3
DATA
SCK
b7
6
7
8
1
2
4
5
3
1
2
3
Command 1
Command 2/Data
11.1.3 Transmission (Command/Data read)
STB
b7
b6
b5
b2
b1
b0
b7
2
b6
3
b5
4
b4
5
b3
DATA
SCK
6
7
8
1
6
1
2
3
Data Read Command
Wait time : tWAIT
Data read
29
Data Sheet S12694EJ2V0DS00
µPD16680
11.2 Parallel
11.2.1 8-bit parallel interface
STB
D0
to D
7
E
11.2.2 4-bit parallel interface
STB
D0
to D
7
Upper
Lower
Upper
Lower
Upper
Lower
E
30
Data Sheet S12694EJ2V0DS00
µPD16680
12 CPU ACCESS EXAMPLE
12.1 Initialize and write data
Command / Data
Item
STB
Explanation
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
L
x
0
x
0
x
1
0
0
x
x
0
x
0
x
1
0
0
x
x
1
x
0
x
0
0
0
x
x
0
x
1
x
0
0
0
x
x
0
x
1
x
0
0
0
x
x
1
x
0
x
0
0
0
x
x
1
x
0
x
0
0
0
x
x
1
x
0
x
0
0
0
x
Reset
H
L
Duty setting
1/53 duty
H
L
Address Register 1
Address Register 2
Address Register 3
Dot address
L
X address = 00H
Y address = 00H
L
H
Data write,
Data R/W mode
L
L
1
0
1
1
0
0
0
0
The address is incremented starting from the current one.
Dot display Data 1
D
D
D
D
D
D
D
D
Dot data
(63 bytes)
Dot display Data 663
L
H
L
D
x
D
x
D
x
D
x
D
x
D
x
D
x
D
x
Address Register 1
Address Register 2
Address Register 3
1
0
0
x
1
0
0
x
0
0
0
x
1
0
0
x
0
0
0
x
0
0
0
x
0
0
0
x
0
0
0
x
Pictograph group address
X address = 00H
L
L
Y address = 00H
H
Data write,
Data R/W mode
L
L
1
0
1
1
0
0
0
0
The address is incremented starting from the current one.
Pictograph Data 1
D
D
D
D
D
D
D
D
Pictograph data
(13 bytes)
Pictograph Data 13
L
H
L
D
x
D
x
D
x
D
x
D
x
D
x
D
x
D
x
Display ON / OFF
End
0
x
0
x
0
x
0
x
1
x
1
x
1
x
1
x
LCD ON
H
Remark x = Don't Care, D = data
31
Data Sheet S12694EJ2V0DS00
µPD16680
12.2 Change display data and pictograph data (All data are changed)
Command / Data
Item
STB
Explanation
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
L
x
1
0
0
x
x
1
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
Address Register 1
Address Register 2
Address Register 3
Dot address
L
X address = 00H
Y address = 00H
L
H
Data write,
Data R/W mode
L
L
1
0
1
1
0
0
0
0
The address is incremented starting from the current one.
Dot display Data 1
D
D
D
D
D
D
D
D
Dot data
(663 bytes)
Dot display Data 663
L
H
L
D
x
D
x
D
x
D
x
D
x
D
x
D
x
D
x
Address Register 1
Address Register 2
Address Register 3
1
0
0
x
1
0
0
x
0
0
0
x
1
0
0
x
0
0
0
x
0
0
0
x
0
0
0
x
0
0
0
x
Pictograph group address
X address = 00H
L
L
Y address = 00H
H
Data write,
Data R/W mode
L
L
1
0
1
1
0
0
0
0
The address is incremented starting from the current one.
Pictograph Data 1
D
D
D
D
D
D
D
D
Pictograph data
(13 bytes)
Pictograph Data 13
End
L
D
x
D
x
D
x
D
x
D
x
D
x
D
x
D
x
H
Remark x = Don't Care, D = data
32
Data Sheet S12694EJ2V0DS00
µPD16680
12.3 Read display data and pictograph data (All data are read)
Command / Data
Item
STB
Explanation
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
L
x
1
0
0
x
x
1
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
Address Register 1
Address Register 2
Address Register 3
Dot address
L
X address = 00H
Y address = 00H
L
H
Data read,
Data R/W mode
L
L
1
0
1
1
0
1
0
0
The address is incremented starting from the current one.
Dot display Data 1
D
D
D
D
D
D
D
D
Dot data
(663 bytes)
Dot display Data 663
L
H
L
D
x
D
x
D
x
D
x
D
x
D
x
D
x
D
x
Address Register 1
Address Register 2
Address Register 3
1
0
0
x
1
0
0
x
0
0
0
x
1
0
0
x
0
0
0
x
0
0
0
x
0
0
0
x
0
0
0
x
Pictograph group address
X address = 00H
L
L
Y address = 00H
H
Data read,
Data R/W mode
L
L
1
0
1
1
0
1
0
0
The address is incremented starting from the current one.
Pictograph Data 1
D
D
D
D
D
D
D
D
Pictograph data
(13 bytes)
Pictograph Data 13
End
L
D
x
D
x
D
x
D
x
D
x
D
x
D
x
D
x
H
Remark x = Don't Care, D = data
33
Data Sheet S12694EJ2V0DS00
µPD16680
12.4 Blink data setting
Command / Data
Item
STB
Explanation
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
L
x
1
0
0
x
x
1
0
0
x
x
1
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
x
0
0
0
x
X
0
0
0
x
Address Register 1
Address Register 2
Address Register 3
Blink group address
X address = 00H
Y address = 00H
L
L
H
Data write,
Data R/W mode
Blink Data 1
L
L
1
0
1
1
0
0
0
0
The address is incremented starting from the current one.
★
D
D
D
D
D
D
D
D
Blink data
(13 bytes)
Blink Data 13
L
H
L
D
x
D
x
D
x
D
x
D
x
D
x
D
x
D
x
★
★
Blink setting
End
0
x
1
x
0
x
0
x
0
x
0
x
1
x
0
x
Blink start, blink frequency = fBRI/2
H
Remark x= Don't Care, D = data
34
Data Sheet S12694EJ2V0DS00
µPD16680
13. ELECTRICAL SPECIFICATIONS
Absolute maximum ratings (TA =+25°C, VSS =0 V)
Parameter
Supply voltage (4-fold voltage mode)
Supply voltage (3-fold voltage mode)
Driver supply voltage
Symbol
Ratings
–0.3 to +3.75
Unit
V
VDD
VDD
–0.3 to +5.0
V
VLCD
–0.3 to +15.0, VDD ≤ VLCD
–0.3 to VLCD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VLCD+0.3
–0.3 to VLCD+0.3
–40 to +85
V
Driver reference supply input voltage
Logic system input voltage
Logic system output voltage
Logic system input/output voltage
Driver system input voltage
Driver system output voltage
Operating temperature
VLC1 to VLC5
VIN1
V
V
VOUT1
VI/01
V
V
VIN2
V
VOUT2
TA
V
°C
°C
Storage temperature
Tstg
–55 to +150
Caution If the absolute maximum rating of even one of the above parameters is exceeded even
momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,
specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the range of the absolute maximum ratings.
Recommended operating range
Parameter
Symbol
VDD
MIN.
2.4
2.4
5.0
0
TYP.
10
MAX.
3.0
Unit
V
Supply voltage (4-fold voltage mode)
Supply voltage (3-fold voltage mode)
VDD
4.0
V
Note
Driver supply voltage
VLCD
VIN
12
V
Logic system input voltage
Driver system input voltage
VDD
V
VLC1 to VLC5
0
VLCD
V
Note
When to use external LCD driving, this parameter is recommended.
Remarks1. When to use external LCD driving, keep VSS < VLC5 < VLC4 < VLC3 < VLC2 < VLC1 ≤ VLCD
2. When power on or power off moment, keep VDD ≤ VLCD
3. When to use internal LCD driving circuit and not to use D/A converter, keep voltage inputted to
IN(+)
AMP
DD
pin to 1.0V to V .
35
Data Sheet S12694EJ2V0DS00
µPD16680
Electrical characteristics (Unless otherwise specified, TA = –40 to +85°C, 4-fold voltage mode : VDD = 2.7 to 3.0V or
3-fold voltage mode : VDD = 2.7 to 4.0 V)
Parameter
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
High-level leakage current
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
★
VIH
V
0.8 VDD
VIL
V
0.2 VDD
1
IIH1
Except DO/DATA, D1 to D7
Except DO/DATA, D1 to D7
IOUT = –1.5 mA, Except OSCOUT
IOUT = 4 mA, Except OSCOUT
µA
µA
V
IIL1
–1
VOH
VOL
ILOH
VDD–0.5
0.5
10
V
µA
DO/DATA, D1 to D7
VIN/OUT = VDD
Low -level leakage current
ILOL
RCOM
RSEG
VLCD
IDD11
–10
2
µA
kΩ
kΩ
DO/DATA, D1 to D7
VIN/OUT = VSS
Common output ON resistance
Segment output ON resistance
Driver voltage (Booster voltage)
VLCn →COMn, VLCD ≥ 3VDD
lIOl = 50 µA
4
VLCn→SEGn, VLCD ≥ 3VDD
lIOl = 50 µA
3-fold voltage mode
V
V
★
★
2.7 VDD
3.6 VDD
3.0 VDD
4.0 VDD
4-fold voltage mode
Current consumption (VDD)
Level condenser mode
fOSC = 32 kHz, Display-off data output
VDD = 3.0 V,3-fold voltage mode
Not to access to RAM.
95
µA
µA
µA
fOSC = 32 kHz, Display-off data output
VDD = 3.0 V,4-fold voltage mode
Not to access to RAM.
125
160
Current consumption (VDD)
LCD driving mode
IDD12
★
fOSC = 32 kHz, Display-off data output
VDD = 3.0 V,3-fold voltage mode
Not to access to RAM.
fOSC = 32 kHz, Display-off data output
VDD = 3.0 V,4-fold voltage mode
Not to access to RAM.
250
10
µA
µA
Driver current consumption
(VDD, Standby)
IDD21
VDD = 3.0 V
36
Data Sheet S12694EJ2V0DS00
µPD16680
Switching characteristics (Unless otherwise specified, TA = –40 to +85°C, VDD = 2.7 to 3.3 V)
Parameter
Oscillation frequency
Transfer delay time 1
Transfer delay time 2
Symbol
FOSC
tPHL
Conditions
MIN.
TYP.
MAX.
38
Unit
kHz
ns
Self-oscillation
25
32
SCK↓ → DATA↓
SCK↓ → DATA↑
100
300
tPLH
ns
Remarks 1. The TYP. value is a reference value when TA =+25°C.
★
2. The time for one frame is found from the following formula.
1 frame = 1/fosc x 8 x number of duties
(Example)
OSC
f
= 32 kHz, 1/53, then the result is :
1 frame = 33 µs x 8 x 53 = 13.25 ms 75.5 Hz
37
Data Sheet S12694EJ2V0DS00
µPD16680
Required conditions for timing (Unless otherwise specified, TA = –40 to +85°C, VDD = 2.7 to 3.3 V)
1. Common
Parameter
Symbol
fOSC
Conditions
OSCIN external clock
MIN.
20
TYP.
32
MAX.
50
Unit
kHz
µs
Clock frequency
tWHC1
tWLC1
tWHC2
tWLC2
tr, tf
OSCIN external clock
OSCIN external clock
OSCBRI external clock
OSCBRI external clock
OSCBRI external clock
/RESET pin
10
25
High-level clock pulse width
Low -level clock pulse width
High-level clock pulse width
10
25
µs
400
400
ns
ns
Low -level clock pulse width
Rise/Fall time
100
ns
Reset pulse width
tWRE
50
µs
Remark The TYP. value is a reference value when TA =+25°C.
2. Serial interface
Parameter
Shift clock cycle
Synbol
tCYK
Conditions
MIN.
900
295
295
400
40
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK
SCK
SCK
tWHK
High-level shift clock pulse width
Low-level shift clock pulse width
tWLK
tHSTBK
tDS1
STB↓ → SCK↓
DATA → SCK↑
SCK↑ → DATA
SCK↑ → STB↑
Shift clock hold time
Data setup time
Data hold time
STB hold time
STB pulse width
Wait timeNote
tDH1
40
tHKSTB
tWSTB
tWAIT
400
210
100
8th CLK↑ →1st CLK↓
Note See 11.1.3 Transmission (Command/Data read).
3. Parallel interface
Parameter
Symbol
tCYCE
tWHE
Conditions
MIN.
900
295
295
210
400
400
40
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
E↑ → E↑
Enable cycle time
E
E
High-level enable pulse width
tWLE
Low-level enable pulse width
STB pulse width
tWSTB
tHKSTB
tHSTBK
tDS2
STB hold time
Enable hold time
Data setup time
Data hold time
D0 to D7 → E↑
D0 to D7 → E↓
tDH2
40
38
Data Sheet S12694EJ2V0DS00
µPD16680
Switching characteristics waveforms
AC measurement point
V
V
IH
Input
V
IL
OH
Output
VOL
AC characteristics waveform
OSCIN
t
WHC1
t
WLC1
1/fOSC
t
f
t
r
OSCBR1
t
WHC2
t
WLC2
Serial interface (Input)
STB
t
CYK
t
WSTB
t
HSTBK
t
HKSTB
t
WHK
SCK
t
DS1
t
DH1
DATA
Serial interface (Output)
SCK
t
PHL
t
PLH
DATA
39
Data Sheet S12694EJ2V0DS00
µPD16680
4-bit parallel interface
STB
t
CYCE
t
HSTBK
t
WHE
t
WLE
E
t
DH2
t
DS2
Dn
Upper bit
Lower bit
Upper bit
STB
t
WSTB
t
HKSTB
E
Dn
Upper bit
Upper bit
Lower bit
8-bit parallel interface
STB
t
WSTB
t
CYCE
t
HSTBK
t
HKSTB
t
WHE
t
WLE
E
t
DH2
t
DS2
Dn
Reset
/RESET
t
WRE
40
Data Sheet S12694EJ2V0DS00
µPD16680
[MEMO]
41
Data Sheet S12694EJ2V0DS00
µPD16680
[MEMO]
42
Data Sheet S12694EJ2V0DS00
µPD16680
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
43
Data Sheet S12694EJ2V0DS00
µPD16680
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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