UPD16908K9-5B4-A [RENESAS]
SPECIALTY ANALOG CIRCUIT, PQCC56, 8 X 8 MM, PLASTIC, WQFN-56;
| 型号： | UPD16908K9-5B4-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SPECIALTY ANALOG CIRCUIT, PQCC56, 8 X 8 MM, PLASTIC, WQFN-56 ISM频段 |
| 文件： | 总38页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16908
DC-DC CONVERTER IC FOR ORGANIC EL DISPLAYS
DESCRIPTION
The µ PD16908 is composed of a 4ch step-up circuit (chopper method), a 2ch polarity-inverted circuit (chopper
method) and a 3ch series regulator, and is ideal for the power supply for organic EL displays.
FEATURES
• Output voltage setting function via serial interface
• On-chip soft start circuit
• Low current consumption achieved by full CMOS
• On-chip timer latch short-circuit protection circuit
• Adjustable oscillation frequency (200 to 800 kHz)
• MOS FET directly driven by push-pull-configured output stage
• Mounted on 56-pin plastic WQFN (8 x 8)
ORDERING INFORMATION
Part Number
Package
µ PD16908K9-5B4-A
56-pin plastic WQFN (8 x 8)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17102EJ2V0DS00 (2nd edition)
Date Published October 2004 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2004
µ PD16908
1. BLOCK DIAGRAM
C
SS1
C
SS2
C
SS3
C
SS4
C
SS5
C
SS6
R
T
C
T
C
DLY
V
REF
24
28
32
37
17
21
39
38
41
40
34
V
DD
Reference
voltage
2.0 V
Triangular
wave
oscillator
Timer latch
short-circuit
protection
circuit
Soft start circuit
11 NPVDD
7
PVDD
Undervoltage
lockout circuit
22
FB1
E/A1
−
+
23
I1
I
+
−
−
10 OUT1
PWM
compa-
rator 1
9
PGND1
26
27
FB2
E/A2
−
+
I
I2
+
8
OUT2
−
−
PWM
compa-
rator 2
30
31
FB3
E/A3
−
+
I
I3
+
6
5
OUT3
−
−
PWM
PGND2
compa-
rator 3
35
36
FB4
E/A4
−
+
I
I4
+
4
OUT4
−
−
PWM
compa-
rator 4
13
PGND3
15
16
FB5
E/A5
−
+
I
I5
+
12
14
OUT5
OUT6
−
−
PWM
compa-
rator 5
19
20
FB6
E/A6
−
+
I
I6
+
−
−
25
29
33
N.C.
N.C.
N.C.
PWM
comparator 6
2
1
BVDD
−
OUT7
LVDD 43
+
45
46
44
51
47
48
49
50
42
18
SDA
SCL
E/A7
56
55
I
I7
−
CS
OUT8
Control logic
block
and
serial interface
block
+
DCON
SHDNB
TEST3
TEST1
TEST2
AGND2
E/A8
54
53
II8
−
OUT9
+
E/A9
52
3
II9
PGND4
AGND1
2
Data Sheet S17102EJ2V0DS
µ PD16908
2. PIN CONFIGURATION (Top View)
42 41 40 39 38 37 36 35 34 33 32 31 30 29
LVDD
CS
43
44
45
46
28
27
26
25
24
23
22
21
20
19
C
SS2
I
I2
SDA
SCL
FB2
N.C.
SHDNB 47
TEST3 48
TEST1 49
TEST2 50
DCON 51
CSS1
I
I1
FB1
CSS6
I
I6
I
I9
52
OUT9 53
54
OUT8 55
56
FB6
18 AGND1
II8
17
16
15
CSS5
I
I5
II7
FB5
1
2
3
4
5
6
7
8
9
10 11 12 13 14
3
Data Sheet S17102EJ2V0DS
µ PD16908
3. PIN FUNCTIONS
(1/2)
Pin No. Symbol
Pin Name
I/O
Output
Description
1
2
3
4
5
6
7
OUT7
BVDD
Output 7
Output of ch7 series regulator (E/A)
Buffer regulator power supply
Power ground
Output 4
Power supply
Ground
Power supply for series regulator (ch7 to ch9)
Power ground
PGND4
OUT4
PGND2
OUT3
PVDD
Output
Output for driving Power MOS FET of ch4
Power ground
Power ground
Output 3
Ground
Output
Output for driving Power MOS FET of ch3
Power supply for output buffer stage of ch1 to ch4
Power supply for output buffer
stage
Power supply
8
9
OUT2
Output 2
Output
Ground
Output for driving Power MOS FET of ch2
Power ground
PGND1
OUT1
Power ground
Output 1
10
11
Output
Output for driving Power MOS FET of ch1
Power supply for output buffer stage of ch5 and ch6
NPVDD
Power supply for output buffer
stage
Power supply
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
OUT5
PGND3
OUT6
FB5
II5
Output 5
Output
Ground
Output
Output
Input
Output for driving Power MOS FET of ch5
Power ground
Power ground
Output 6
Output for driving Power MOS FET of ch6
Feedback of ch5 E/A
Feedback
Inversion input
Soft start capacitance 5
Analog ground
Feedback
Inversion input of ch5 E/A
CSS5
AGND1
FB6
II6
Output
Ground
Output
Input
Capacitance connection pin for ch5 soft start
Analog ground
Feedback of ch6 E/A
Inversion input
Soft start capacitance 6
Feedback
Inversion input of ch6 E/A
CSS6
FB1
II1
Output
Output
Input
Capacitance connection pin for ch6 soft start
Feedback of ch1 E/A
Inversion input
Soft start capacitance 1
−
Inversion input of ch1 E/A
CSS1
N.C.
FB2
II2
Output
−
Capacitance connection pin for ch1 soft start
Leave open, or short to GND or LVDD
Feedback of ch2 E/A
Feedback
Output
Input
Inversion input
Soft start capacitance 2
−
Inversion input of ch2 E/A
CSS2
N.C.
FB3
II3
Output
−
Capacitance connection pin for ch2 soft start
Leave open, or short to GND or LVDD
Feedback of ch3 E/A
Feedback
Output
Input
Inversion input
Soft start capacitance 3
−
Inversion input of ch3 E/A
CSS3
N.C.
VDD
Output
−
Capacitance connection pin for ch3 soft start
Leave open, or short to GND or LVDD
Power supply for DC-DC converter
Feedback of ch4 E/A
Power supply
Feedback
Power supply
Output
Input
FB4
II4
Inversion input
Soft start capacitance 4
Inversion input of ch4 E/A
CSS4
Output
Capacitance connection pin for ch4 soft start
4
Data Sheet S17102EJ2V0DS
µ PD16908
(2/2)
Pin No. Symbol
Pin Name
I/O
Description
38
39
40
41
CT
Timing capacitor
Timing resistance
Reference voltage
Short-circuit protection
circuit delay capacitance
Analog ground
Power supply for control
logic
Output
Output
Output
Output
Capacitor connection for triangular wave generation
Resistance connection for triangular wave generation
Power supply for reference voltage
RT
VREF
CDLY
Capacitor connection for timer latch
42
43
AGND2
Ground
Analog ground
LVDD
Power supply
Power supply for control logic
44
45
46
47
48
49
50
51
CS
Chip select
Input
input
input
input
Input
Input
Input
Input
Chip select
SDA
Serial data input
Serial clock input
Shut-down input
Test 3
Serial data input for controlling each output
Serial clock input for controlling each output
Shut down the IC
SCL
SHDNB
TEST3
TEST1
TEST2
DCON
Short to LVDD
Test 1
Short to GND
Test 2
Short to GND
Output turn-on control
Output of the channel selected by serial data is switched
ON.
52
53
54
55
56
II9
Inversion input
Output 9
Input
Output
Input
Inversion input of ch9 E/A
Output of ch9 series regulator (E/A)
Inversion input of ch8 E/A
Output of ch8 series regulator (E/A)
Inversion input of ch7 E/A
OUT9
II8
Inversion input
Output 8
OUT8
II7
Output
Input
Inversion input
5
Data Sheet S17102EJ2V0DS
µ PD16908
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Unless otherwise specified, TA = 25°C)
Parameter
Power supply voltage
Symbol
Condition
Rating
Unit
V
VDD
−0.5 to +6
−0.5 to +6
Power supply voltage for output buffer
stage 1
PVDD
(ch1 to ch4)
V
Power supply voltage for output buffer
stage 2
NPVDD
(ch5 and ch6)
−0.5 to +6
V
Buffer regulator power supply voltage
Control logic power supply voltage
Analog input pin voltage
Control logic input voltage
Output current (DC) 1-6
Output current (pulse) 1-6
Output current (DC) 7-9
Total power dissipation
BVDD
LVDD
−0.5 to +6
−0.5 to +6
−0.5 to +6
V
V
V
VAIN
FB, II
VCLIN
SHDNB, DCON, SDA, SCL, CS
OUT1 to OUT6
−0.5 to LVDD + 0.5
V
IO(DC)1-6
IO(pulse)1-6
IO(DC)7-9
PT
20
200
20
mA
mA
mA
W
OUT1 to OUT6
OUT7 to OUT9
Glass epoxy board of 100 mm x 100 mm
x 1 mm with copper foil area of 15%
0.8
Operating ambient temperature
Operating junction temperature
Storage temperature
TA
−30 to +75
−30 to +125
−55 to +125
°C
°C
°C
TJ
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
6
Data Sheet S17102EJ2V0DS
µ PD16908
Recommended Operating Conditions (Unless otherwise specified, TA = 25°C)
Parameter
Power supply voltage
Symbol
VDD
Condition
MIN.
2.7
TYP.
3.3
MAX.
Unit
V
5.5
5.5
Power supply voltage for output buffer
stage 1
PVDD
(ch1 to ch4)
2.7
3.3
V
Power supply voltage for output buffer
stage 2
NPVDD
(ch5 and ch6)
2.7
3.3
5.5
V
Buffer regulator power supply voltage
Control logic power supply voltage
Control logic input voltage
Operating frequency
Timing capacitance
BVDD
LVDD
VCLIN
fOSC
3.0
2.7
2.7
200
60
3.3
3.3
3.3
700
5.5
3.6
3.6
800
240
22
V
V
SHDNB, DCON, SDA, SCL, CS
V
kHz
pF
kΩ
µs
ns
ns
ns
ns
µs
µs
CCT
Capacitance connected to CT
Resistance connected to RT
Timing resistance
RRT
5.1
Serial clock period
tprd
10
SCL waiting time
t(SCL-CS)
t(CS-SCL)
tsetup
thold
500
50
50
50
2
CS waiting time
SDA set-up time
SDA hold time
SCL high-pulse time
SCL low-pulse time
tpw
tnw
2
50%
50%
CS
SDA
SCL
D
1
D
2
D
3
D
4
D
8
50%
50%
50%
50%
50%
50%
t
(SCL-CS)
t
setup
t
hold
t
pw
t
nw
t
(CS-SCL)
t
prd
7
Data Sheet S17102EJ2V0DS
µ PD16908
Electrical Characteristics (Unless otherwise specified, VDD = NPVDD = PVDD = LVDD = BVDD = 3.3 V, fOSC = 700 kHz,
TA = 25°C)
(1/2)
Overall
Parameter
Symbol
Condition
MIN.
TYP.
5
MAX.
8
Unit
Shut-down current
IDD(SHD)
SHDNB = L,
µA
VDD + NPVDD + PVDD + BVDD + LVDD
DCON = L, SHDNB = H,
VDD + NPVDD + PVDD + BVDD + LVDD
VDD
Standby current
IDD(SB)
2.04
3.75
mA
Circuit operation current 1
Circuit operation current 2
Circuit operation current 3
Circuit operation current 4
Circuit operation current 5
IDD
2.04
3.0
3.75
5.7
1.8
345
45
mA
mA
mA
µA
PIDD
NPIDD
BIDD
LIDD
PVDD, CL = 150 pF, FB = VDD
NPVDD, CL = 150 pF, FB = AGND
BVDD, no-load, II = BVDD
LVDD
0.96
180
24
µA
Triangular Wave Oscillator Block
Condition
Parameter
Symbol
MIN.
TYP.
MAX.
+10
Unit
%
Oscillation frequency setting
accuracy
fOSC
CCT = 150 pF, RRT = 11 kΩ
−10
Triangular wave low-level
voltage
VTH(L)
VTH(H)
1.1
1.8
V
V
Triangular wave high-level
voltage
Reference Voltage Block
Condition
Parameter
Reference voltage
Symbol
VREF
MIN.
1.97
TYP.
2.0
1
MAX.
2.03
2
Unit
V
IREF = 1 mA
Maximum output current
IREF
mA
PWM Comparator Block
Condition
Parameter
Maximum duty 1-4
Maximum duty 5-6
Symbol
DMAX.1-4
DMAX.5-6
MIN.
TYP.
85
MAX.
Unit
%
ch1 to ch4
ch5 and ch6
85
%
Undervoltage Lockout Circuit Block
Condition
Parameter
Symbol
MIN.
1.01
TYP.
1.45
MAX.
1.89
Unit
V
Operation start voltage at
power application
VDD(L-H)
Operation stop voltage
Hysteresis width
VDD(H-L)
VH
0.89
5
1.27
60
1.65
V
mV
Short-circuit Protection Circuit Block
Parameter
Symbol
VTH(FB)1-4
VTH(FB)5-6
VTH(DLY)
IDLY
Condition
FB (ch1 to ch4)
FB (ch5 and ch6)
CDLY
MIN.
1.9
TYP.
2
MAX.
2.1
Unit
V
FB detection voltage 1-4
FB detection voltage 5-6
DLY detection voltage
Short-circuit source current
0.76
0.76
1
0.8
0.8
2
0.84
0.84
4
V
V
µA
8
Data Sheet S17102EJ2V0DS
µ PD16908
(2/2)
Soft Start Block
Parameter
CSS detection voltage 1-4
CSS detection voltage 5-6
Charge current
Symbol
VTH(CSS)1-4
VTH(CSS)5-6
ICSS
Condition
MIN.
1.47
0.79
1
TYP.
1.55
1.35
2
MAX.
Unit
V
CSS1 to CSS4
CSS5 and CSS6
1.63
1.59
4
V
µA
Output Block (ch1 to ch6)
Condition
Parameter
Symbol
Ronp
MIN.
TYP.
10
MAX.
15
Unit
Ω
Output turn-on resistance-p
Output turn-off resistance-n
IO = 15 mA
IO = 15 mA
Ronn
10
15
Ω
E/A Block (ch1 to ch4)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
0.694
Unit
V
E/A1 input threshold voltage
VITH1
ch1OUT control bit is fixed to default setting
(D [0:5] = 000000), offset is not included.
ch2OUT control bit is fixed to default setting
(D [0:5] = 000000), offset is included.
ch3OUT control bit is fixed to default setting
(D [0:5] = 000000), offset is not included.
Offset is not included.
0.666
0.680
0.680
0.700
0.720
0.694
E/A2 input threshold voltage
E/A3 input threshold voltage
VITH2
VITH3
V
V
0.666
0.680
1.000
E/A4 input threshold voltage
E/A1 input offset voltage
E/A3 input offset voltage
E/A4 input offset voltage
VITH4
0.980
1.020
40
V
VIOFF1
VIOFF3
VIOFF4
VREF = 2 V
0
0
0
mV
mV
mV
40
40
E/A Block (ch5 and ch6)
Condition
Parameter
Symbol
VITH5
MIN.
TYP.
MAX.
Unit
V
E/A5 input threshold voltage
E/A6 input threshold voltage
E/A5 input offset voltage
E/A6 input offset voltage
Offset is not included.
0.980
0.980
1.000
1.000
1.020
1.020
VITH6
V
mV
0
0
40
40
VIOFF5
VIOFF6
VREF = 2 V
mV
E/A Block (ch7 to ch9)
Condition
Parameter
Symbol
VITH7
MIN.
0.980
0.980
0.980
−10
TYP.
1.000
1.000
1.000
MAX.
1.020
1.020
1.020
30
Unit
V
E/A7 input threshold voltage
E/A8 input threshold voltage
E/A9 input threshold voltage
E/A7 input offset voltage
E/A8 input offset voltage
E/A9 input offset voltage
I/O differential voltage
Offset is not included.
VITH8
V
VITH9
V
VIOFF7
VIOFF8
VIOFF9
VDIFF
VREF = 2 V
mV
mV
mV
V
−10
30
−10
30
BVDD − OUT7 to OUT9, IO = 10 mA
1
Control Logic Block and Serial Interface Block
Condition
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
V
High-level input voltage
VIH(L)
SHDNB, DCON, SDA, SCL, CS
LVDD
x 0.8
Low-level input voltage
Input leak current
VIL(L)
IL
SHDNB, DCON, SDA, SCL, CS
LVDD
x 0.2
1
V
V
SHDNB, DCON, SDA, SCL, CS,
VIN = AGND to LVDD
9
Data Sheet S17102EJ2V0DS
µ PD16908
5. TIMING CHART
LVDD
V
DD
PVDD
Power supply
NPVDD
BVDD
SHDNB
DCON
CS
Input signal
SCL
SDA
V
REF
C
T
OUT1 to OUT4
OUT5, OUT6
OUT7 to OUT9
Output signal
10
Data Sheet S17102EJ2V0DS
µ PD16908
6. I/O PIN EQUIVALENT CIRCUIT (Protection Circuit)
Pin No.
Symbol
Internal Circuit
Configuration
Analog output
Power supply
Ground
Specified Protection
Power Supply Connection (refer to Figure 6−1)
Element
VDD Side
GND Side
AGND, PGND
AGND, PGND
PGND
1
OUT7
BVDD
PGND4
OUT4
PGND2
OUT3
PVDD
OUT2
PGND1
OUT1
NPVDD
OUT5
PGND3
OUT6
FB5
Output protection 1
Power supply protection
Power supply protection
Output protection 1
Power supply protection
Output protection 1
Power supply protection
Output protection 1
Power supply protection
Output protection 1
Power supply protection
Output protection 1
Power supply protection
Output protection 1
Output protection 1
Input protection 1
Output protection 1
Power supply protection
Output protection 1
Input protection 1
Output protection 1
Output protection 1
Input protection 1
Output protection 2
−
BVDD
2
BVDD
3
VDD, PVDD, NPVDD, LVDD
4
Logic output
Ground
PVDD
AGND, PGND
PGND
5
VDD, PVDD, NPVDD, LVDD
6
Logic output
Power supply
Logic output
Ground
PVDD
AGND, PGND
AGND, PGND
AGND, PGND
AGND, PGND
AGND, PGND
AGND, PGND
AGND, PGND
PGND
7
PVDD
8
PVDD
9
VDD, PVDD, NPVDD, LVDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Logic output
Power supply
Logic output
Ground
PVDD
NPVDD
NPVDD
VDD, PVDD, NPVDD, LVDD
Logic output
Analog output
Gate input
NPVDD
AGND, PGND
AGND
VDD
II5
VDD
AGND
CSS5
AGND1
FB6
Analog output
Ground
VDD
AGND
VDD, PVDD, NPVDD, LVDD
AGND
Analog output
Gate input
VDD
VDD
VDD
VDD
VDD
VDD
−
AGND
II6
AGND
CSS6
FB1
Analog output
Analog output
Gate input
AGND
AGND
II1
AGND
CSS1
N.C.
FB2
Analog output
−
AGND
−
Analog output
Gate input
Output protection 1
Input protection 1
Output protection 2
−
VDD
VDD
VDD
−
AGND
II2
AGND
CSS2
N.C.
FB3
Analog output
−
AGND
−
Analog output
Gate input
Output protection 1
Input protection 1
Output protection 2
−
VDD
VDD
VDD
−
AGND
II3
AGND
CSS3
N.C.
VDD
Analog output
−
AGND
−
Power supply
Analog output
Gate input
Power supply protection
Output protection 1
Input protection 1
Output protection 2
Output protection 2
Output protection 2
Output protection 2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AGND, PGND
AGND
FB4
II4
AGND
CSS4
CT
Analog output
Analog output
Analog output
Analog output
AGND
AGND
RT
AGND
VREF
AGND
11
Data Sheet S17102EJ2V0DS
µ PD16908
（2/2）
Pin No.
Symbol
Internal Circuit
Configuration
Analog output
Ground
Specified Protection
Element
Power Supply Connection (refer to Figure 6−1)
VDD Side
GND Side
AGND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
CDLY
Output protection 2
Power supply protection
Power supply protection
Input protection 1
Input protection 1
Input protection 1
Input protection 1
Input protection 1
Input protection 1
Input protection 1
Input protection 1
Input protection 1
Output protection 1
Input protection 1
Output protection 1
Input protection 1
VDD
AGND2
LVDD
CS
VDD, PVDD, NPVDD, LVDD
AGND
Power supply
Gate input
Gate input
Gate input
Gate input
Gate input
Gate input
Gate input
Gate input
Gate input
Analog output
Gate input
Analog output
Gate input
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
BVDD
BVDD
BVDD
BVDD
BVDD
AGND, PGND
AGND
SDA
AGND
SCL
AGND
SHDNB
TEST3
TEST1
TEST2
DCON
II9
AGND
AGND
AGND
AGND
AGND
AGND
OUT9
II8
AGND, PGND
AGND
OUT8
II7
AGND, PGND
AGND
Figure 6−1.
Input Protection 1
DD side
V
GND side
Output Protection 1
Output Protection 2
Power Supply Protection
DD side
V
DD side
V
DD side
V
GND side
GND side
GND side
12
Data Sheet S17102EJ2V0DS
µ PD16908
7. CONTROL LOGIC BLOCK
7.1 SHDNB Pin (Pin No. 47)
The internal circuits (E/A, PWM comparator, triangular wave oscillator) are stopped by the SHDNB pin and the serial
interface registers are reset. The capacitor connected between the CSS1 to CSS6 pins also discharges.
SHDNB
State of IC
Serial Interface
L
Shut down (OUT1 to OUT4 = fixed to GND, OUT5 and OUT6 = fixed to
Input disable
VDD, and OUT7 to OUT9 = fixed to GND)
ON
H
Input enable
7.2 DCON Pin (Pin No. 51)
The outputs are switched OFF by the DCON pin while the internal circuits are operating (serial interface input
possible). The capacitor connected between the CSS1 to CSS6 pins also discharges.
DCON
State of IC
Serial Interface
L
Standby (All channel output turns off, and the internal circuits operate.)
(OUT1 to OUT4 = fixed to GND, OUT5 and OUT6 = fixed to VDD, and
OUT7 to OUT9 = fixed to GND)
Input enable
H
The channel specified by ON/OFF control bit of the serial interface turns
on.
13
Data Sheet S17102EJ2V0DS
µ PD16908
8. SERIAL INTERFACE BLOCK
8.1 Control Data (Default = All “0”)
Data is the turn of D11, D10, D9, ⋅⋅⋅, and D0, and please input it.
First
Last
LSB
MSB
D
11
D
10
D
9
D
8
D7
D6
D
5
D
4
D
3
D
2
D
1
D0
Output voltage control bit
Output Voltage
D5
D
4
D
3
D
2
D
1
D
0
0
0
0
0
0
0
0
0
0
0
0
1
Refer to
8.2 Details of Output
Voltage Control Bits.
1
1
1
1
1
1
1
1
1
1
0
1
Unused
Output voltage control bit
Input Data
Output
D11
D
10
D
9
−
Unused
0
0
0
1
0
1
0
1
0
1
ch1 output voltage
ch2 output voltage
ch3 output voltage
Unused
ch1OUT
0
0
0
1
1
1
1
0
1
1
0
0
1
1
ch2OUT
ch3OUT
−
ON/OFF control 1
ON/OFF control 2
Unused
ch1OUT to ch6OUT
ch7OUT to ch9OUT
−
14
Data Sheet S17102EJ2V0DS
µ PD16908
8.2 Details of Output Voltage Control Bits
Input data configuration of input address control bit
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
Unused
ch1 output voltage
Table 8−1. ch1 Output Voltage (ch1OUT) Control Bit
D
5
D
4
D
3
D
2
D
1
D
0
E/A1 Threshold Voltage TYP.
V
ITH1 [V]
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Caution The output voltage value becomes ch1OUT ≅ VITH1 x ( (R11 + R12) /R12).
15
Data Sheet S17102EJ2V0DS
µ PD16908
Input data configuration of input address control bit
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
Unused
ch2 output voltage
Table 8−2. ch2 Output Voltage (ch2OUT) Control Bit
D
5
D
4
D
3
D
2
D
1
D
0
E/A2 Threshold VoltageTYP.
ITH2
V
[V]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
Caution The output voltage value becomes ch2OUT ≅ VITH2 x ( (R21 + R22) /R22).
16
Data Sheet S17102EJ2V0DS
µ PD16908
Input data configuration of input address control bit
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
Unused
ch3 output voltage
Table 8−3. ch3 Output Voltage (ch3OUT) Control Bit
D
5
D
4
D
3
D
2
D
1
D
0
E/A3 Threshold Voltage TYP.
ITH3
V
[V]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
Caution The output voltage value becomes ch3OUT ≅ VITH3 x ( (R31 + R32) /R32).
17
Data Sheet S17102EJ2V0DS
µ PD16908
Input data configuration of input address control bit
D11
1
D10
0
D9
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
Unused
Unused
ON/OFF control 1
ON/OFF control 2
1
1
0
• ON/OFF control bit 1
D5
D4
D3
D2
D1
D0
Input Data
Output of ch6
Output of ch5
Output of ch4
Output of ch3
Output of ch2
Output of ch1
0
1
ON
OFF (E/A and PWM operation stop)
• ON/OFF control bit 2
D5
D4
D3
D2
D1
Output of ch8
ON
D0
Input Data
Unused
Unused
Unused
Output of ch9
Output of ch7
0
1
−
−
OFF (E/A and PWM operation stop)
18
Data Sheet S17102EJ2V0DS
µ PD16908
8.3 Serial Correspondence Timing
MSB
LSB
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDA
SCL
CS
Read at the rising
High-level load
• The 12-bit serial data inputted by the SDA pin is loaded to the shift register at the rising edge of the signal inputted to
the SCL pin. The loaded data is loaded to the shift register at the rising edge of the signal inputted to the CS pin.
Be sure to fix the signal input to the SCL pin to low level at the rising and falling edges of the signal input to the CS
pin.
• If the data which is loaded to shift register while the CS pin is low level is less than 12 bits, the loaded data is
cancelled. If the loaded data is more than 12 bits, the 12-bit data is valid in the last of the loaded data.
19
Data Sheet S17102EJ2V0DS
µ PD16908
9. TYPICAL CHARACTERISTICS (Unless Otherwise Specified, VDD = NPVDD = PVDD = LVDD =
BVDD = 3.3 V, fOSC = 700 kHz, TA = 25°C, Reference Value)
VREF vs. VDD
VREF vs. TA
2.1
2.05
2
2.1
2.05
2
1.95
1.9
1.95
1.9
2.5
3
3.5
4
4.5
5
5.5
6
-40
-20
0
20
40
60
80
VDD - V
TA - °C
fOSC vs. VDD
fOSC vs. TA
1000
900
800
700
600
500
1000
900
800
700
600
500
2.5
3
3.5
4
4.5
5
5.5
6
-40
-20
0
20
40
60
80
VDD - V
TA - °C
fOSC vs. RRT
10000
1000
100
10
CCT = 68 pF
150 pF
220 pF
330 pF
1
1
10
100
1000
RRT - kΩ
20
Data Sheet S17102EJ2V0DS
µ PD16908
DMAX.1-4 vs. VDD
DMAX.1-4 vs. TA
100
90
80
70
60
50
100
90
80
70
60
50
2.5
3
3.5
3.5
3.5
4
4.5
5
5.5
5.5
5.5
6
-40
-20
0
20
40
60
80
VDD - V
TA - °C
DMAX.5-6 vs. VDD
DMAX.5-6 vs. TA
100
90
80
70
60
50
100
90
80
70
60
50
2.5
3
4
4.5
5
6
-40
-20
0
20
40
60
80
VDD - V
TA - °C
IDLY vs. VDD
IDLY vs. TA
8
6
4
2
0
8
6
4
2
0
µ
µ
2.5
3
4
4.5
5
6
-40
-20
0
20
40
60
80
VDD - V
TA - °C
21
Data Sheet S17102EJ2V0DS
µ PD16908
ICSS vs. VDD
ICSS vs. TA
8
6
4
2
0
8
6
4
2
0
µ
µ
2.5
3
3.5
4
4.5
5
5.5
6
-40
-20
0
20
40
60
80
VDD - V
TA - °C
22
Data Sheet S17102EJ2V0DS
µ PD16908
10. OPERATION EXPLANATION OF EACH BLOCK
10.1 Reference Voltage Circuit Block
The reference voltage circuit block outputs reference voltage (2.0 V TYP.) by which temperature compensation is
carried out by supplying voltage by the VDD (No. 34) pin. The reference voltage is used as the reference voltage of
each internal circuit, and can be extracted to outside by the VREF (No. 40) pin to 1 mA TYP..
10.2 Triangular Wave Oscillator Block
The triangular wave oscillator block performs self-excited oscillation using the timing capacitance and timing resistor
externally attached to the CT (No. 38) pin and RT (No. 39) pin, respectively, and outputs a symmetric triangular wave
with an amplitude of 1.1 to 1.8 V TYP. to the CT (No. 38) pin.
This triangular wave is supplied to the inversion input pin of the PWM comparator.
10.3 E/A Block
The input threshold voltage of E/A is the voltage set by the output voltage control bit of the serial interface for E/A1 to
E/A3 (default = all zero; 0.68 V TYP.), and 1.0 V TYP. for E/A4 to E/A9.
Note that E/A7 to E/A9 operate as a series regulator.
10.4 PWM Comparator Block
The PWM comparator compares the triangular wave signal and E/A output signal (or maximum duty) and controls
the output ON duty.
10.5 Output Circuit Block
The output circuit block of ch1 to ch6 is of push-pull configuration and can directly drive a Power MOS FET. The
output current capacity is 200 mA MAX. for pulse output and 20 mA MAX. for DC output.
The output current capacity of the output circuit block of ch7 to ch9 is 20 mA MAX. for DC output
10.6 Undervoltage Lockout Circuit Block
The undervoltage lockout circuit block shuts down the IC if the power supply voltage is insufficient at power
application or shut down in order to prevent malfunction of the IC.
23
Data Sheet S17102EJ2V0DS
µ PD16908
10.7 Soft Start Block of the Step-up DC-DC Converter Output (ch1 to ch4)
ch1 is soft-started by a capacitor connected to the CSS1 (No. 24) pin. Also, ch2 to ch4 are respectively soft-started by
a capacitor connected to the CSS2 (No. 28) pin, CSS3 (No. 32) pin, and CSS4 (No. 37) pin.
Soft start is executed by charging the capacitor connected to each CSS pin and gradually increasing the voltage at the
CSS pin. On starting the IC, the voltage at each CSS pin is connected to the non-inverted input of E/A. Soft start is
executed by increasing the non-inverted input voltage of E/A from 0 V and gradually prolonging the output ON duty.
(Figure 10−1 and 10−2)
Figure 10−1.
Threshold voltage of E/A1 to E/A4
1.8 V
DTC
DTC
FB1 to FB4
C
T
(VDD) V
FB1 to FB4
1.1 V
0 V
ON
V
TH(CSS)1-4 = 1.55 V
CSS1 to CSS4
ON
ON
ON
ON
ON
ON
ON
ON
OUT1 to OUT4
Setting voltage
V
OUT
(Outputs of ch1 to ch4)
Power ON
Figure 10−2.
38
C
T
V
OUT
Triangular wave
oscillator
(Outputs of ch1 to ch4)
Undervoltage
lockout circuit
FB1 to FB4
E/A1 to E/A4
PWM1 to PWM4
II1 to II4
OUT1 to OUT4
−
+
−
−
+
+
ch1 to ch3: 0.68 V
ch4: 1 V
DTC
C
DLY
41
Timer latch short-circuit
protection circuit
←ICSS
Soft start circuit
C
SS1 to CSS4
24
Data Sheet S17102EJ2V0DS
µ PD16908
10.8 Soft Start Block of the Polarity-inverted DC-DC Converter Output (ch5 and ch6)
ch5 is soft-started by a capacitor connected to the CSS5 (No. 17) pin. Also, ch6 is soft-started by a capacitor
connected to the CSS6 (No. 21) pin.
Soft start is executed by charging the capacitor connected to each CSS pin and gradually increasing the voltage at the
CSS pin. The CSS pin voltage is connected to the PWM non-inverted input (DTC) via a 200 kΩ resistor. At startup,
raising the PWM non-inverted input (DTC) voltage from about 0.4 gradually lengthens the output ON duty, causing a
soft start (Figure 10−3 and 10−4).
Note that if the DTC voltage and FB voltage are switched while the output ON duty is still small (less than 50%)
following a soft start, inrush current may occur at the point of switching. In this case, suppress the inrush current by
either raising the operating frequency or increasing the inductance of the coil used by the DC-DC converter.
Figure 10−3.
1.8 V
1.75 V
FB5, FB6
DTC
(VDD) V
C
T
DTC
FB5, FB6
1.1 V
About 0.4 V
0 V
V
TH(CSS)5-6 = 1.35 V TYP.
C
SS5, CSS6
0 V
ON
ON
ON ON
ON
ON
ON
ON
ON
ON
ON
OUT5, OUT6
VOUT
(Outputs of ch5 and ch6)
Setting voltage
Power ON
Figure 10−4.
SW switches from D to E when the FB voltage
becomes higher than point A.
38
CT
Triangular wave
oscillator
V
REF
Undervoltage
lockout circuit
FB5, FB6
E/A5, E/A6
−
I
I5, II6
PWM5, PWM6
OUT5, OUT6
E
−
+
−
+
SW
DTC
D
1 V
V
OUT
C
DLY
41
Timer latch short-circuit
protection circuit
(Outputs of ch5 and ch6)
Soft start circuit
DTC
B
200 kΩ
←ICSS
A
C
C
SS5, CSS6
SW
1.75 V
1.15 V
1.15 V
About 0.4 V
(VDD) V
About 1.35 V
1.75 V
About 0.4 V
SS5, CSS6
SW switches from B to C as soon as
voltage of A becomes 1.75 V.
C
0 V
25
Data Sheet S17102EJ2V0DS
µ PD16908
10.9 Short-circuit Protection Circuit Block (Timer latch type)
If the voltage of ch1 to ch4, which are the step-up DC-DC converter outputs, drops, the voltage of the inversion input
pin of the E/A, which is feeding back the output, also drops, and the E/A output (FB) is stepped up. If the voltage of
this E/A output (FB) reaches or exceeds the FB detection voltage of the short-circuit protection circuit (VTH(FB)1-4 = 2.0
V TYP.), the timer circuit starts operating and the capacitor connected to the CDLY (No. 41) pin starts charging. When
the voltage of the capacitor connected the CDLY (No. 41) pin reaches the CDLY protection voltage (VTH(DLY) = 0.8 V
TYP.), all the outputs of the IC are latched to OFF (Figure 10−5 and 10−6).
If the voltage of ch5 and ch6, which are the polarity-inverted DC-DC converter outputs, is stepped up, the voltage of
the inversion input pin of the E/A, which is feeding back the output, is also stepped up, and the E/A output (FB) is
stepped down. If the voltage of this E/A output (FB) falls below the FB detection voltage of the short-circuit protection
circuit (VTH(FB)5-6 = 0.8 V TYP.), the timer circuit starts operating and the capacitor connected to the CDLY (No. 41) pin
starts charging. When the voltage of the capacitor connected to the CDLY (No. 41) pin reaches the CDLY detection
voltage (VTH(DLY) = 0.8 V TYP.), all the outputs of the IC are latched to OFF (Figure 10−5 and 10−7).
As long as the E/A output (FB) of any of ch1 to ch6 is at least the FB detection voltage of the short-circuit protection
circuit, the capacitor connected to the CDLY (No. 41) pin continues to charge. (Figure 10−8)
To reset the latch circuit when the short-circuit protection circuit is activated, decrease the supply voltage (VDD) to the
operation stop voltage level (VDD(H-L) = 1.39 V TYP.), or set the SHDNB (No. 47) pin or DCON (No. 51) pin to low level.
Figure 10−5.
41
(Output of ch1)
(Output of ch2)
(Output of ch3)
(Output of ch4)
C
DLY
22
23
ch1SCP
FB1
E/A1
E/A2
E/A3
E/A4
E/A5
E/A6
comparator
−
+
I
I1
+
−
I
DLY
26
27
ch2SCP
comparator
FB2
−
The capacitor connected to
SS6 is discharged.
+
I
I2
C
SS1 to C
+
−
Comparator
+
Latch circuit
SCP signal
−
30
31
ch3SCP
comparator
FB3
All the outputs of ch1
to ch6 makes it stop.
−
+
0.8 V
I
I3
+
−
35
36
ch4SCP
comparator
FB4
−
+
I
I4
+
−
The capacitor connected to CDLY starts charging
when the FET switches from ON to OFF,
and the comparator outputs the SCP signal
when CDLY reaches 0.8 V.
2.0 V
V
REF
15
16
ch5SCP
− comparator
FB5
A channel that is switched OFF by the serial
interface is not involved in the timer latch function.
−
I
I5
+
+
(Output of ch5)
V
REF
19
20
ch6SCP
− comparator
FB6
−
I
I6
+
+
(Output of ch6)
0.8 V
26
Data Sheet S17102EJ2V0DS
µ PD16908
Figure 10−6.
FB1 to FB4
1.8 V
2 V
DTC
FB1 to FB4
C
T
1.1 V
Stop of operation
OUT1 to OUT4
V
OUT
The outputs of ch1 to ch4
are switched OFF.
(Outputs of ch1 to ch4)
The short-circuit protection circuit
latches the outputs at 0.8 V and
the outpus are switched OFF.
The outputs of ch1 to ch4
are load-short-circuited.
CDLY
0.8 V
The short-circuit protection circuit causes the capacitor
to start charging when FB1 to FB4 = 2.0 V or higher.
Figure 10−7.
1.8 V
FB5, FB6
DTC
C
T
0.8 V
1.1 V
FB5, FB6
Stop of operation
OUT5, OUT6
ON
The outputs of ch5 and ch6
are switched OFF.
V
OUT
(Outputs of ch5 and ch6)
The short-circuit protection circuit
latches the outputs at 0.8 V and
the outpus are switched OFF.
The outputs of ch5 and ch6
are load-short-circuited.
0.8 V
C
DLY
The short-circuit protection circuit causes the capacitor
to start charging when FB5 and FB6 = 0.8 V or less.
Figure 10−8.
FB1 to FB4
2 V
CT
FB5, FB6
FB1 to FB4
0.8 V
The short-circuit protection circuit
latches the outputs at 0.8 V and
the outpus are switched OFF.
FB5, FB6
0.8 V
C
DLY
As long as one of ch1 to ch6 is at
least the FB ditection voltage,
the capacitor connected to CDLY
If all the outputs of ch1 to ch6 fall
below the FB ditection voltage,
even momentarily, charge of the
capacitor connected to CDLY is reset.
contunues to charge.
27
Data Sheet S17102EJ2V0DS
µ PD16908
11. NOTES ON USE
11.1 Method of Setting Output Voltage
The method of setting the output voltage of ch1 to ch4 is shown in Figure 11−1, the method of setting the output
voltage of ch5 and ch6 is shown in Figure 11−2, and the method of setting the output voltage of ch5 to ch7 is shown
in Figure 11−3.
The output voltage can be calculated by using the expression in the figure.
Figure 11−1. The Method of Setting the Output Voltage of the Step-up Circuit of ch1 to ch4
VOUT = (1 + R1/R2) x VITH
VOUT
(Outputs of ch1 to ch4)
E/A1 to E/A4
−
R1
R2
I
I1 to II4
+
V
ITH
FB1 to FB4
Caution VITH of ch1 to ch3 depends on the serial interface.
VITH of ch4 is 1.0 V TYP..
Figure 11−2. The Method of Setting the Output Voltage of the Polarity-inverted Circuit of ch5 and ch6
VOUT = (1 + R1/R2) x 1.0 − R2/R1 x VREF
V
REF
(Reference voltage/40-pin)
E/A5, E/A6
−
R1
R2
II5, II6
+
1.0 V TYP.
FB5, FB6
−VOUT
(Outputs of ch5 and ch6)
Figure 11−3. The Method of Setting the Output Voltage of ch7 to ch9
VOUT = (1 + R1/R2) x 1.0
R1
II7 to II9
−
R2
+
OUT7 to OUT9
1.0 V TYP.
28
Data Sheet S17102EJ2V0DS
µ PD16908
11.2 Method of Handling Pins of Unused Channels
Figure 11−4 to 11−8 show how to handle the pins when not using ch1 to ch3, ch5 and ch6, ch7 to ch9, and the serial
interface, respectively.
Figure 11−4. Handling of Pins When Not Using ch1 to ch3
34
V
DD
Soft start circuit
C
SS1 to CSS3
FB1 to FB3
Undervoltage
lockout circuit
E/A1 to E/A3
−
I
I1 to II3
PWM1 to PWM3
+
−
−
+
OUT1 to OUT3
Timer latch short-circuit
protection circuit
Triangular wave
oscillator
Figure 11−5. Handling of Pins When Not Using ch4
34
V
DD
37
Soft start circuit
C
SS4
FB4
Undervoltage
lockout circuit
35
36
E/A4
−
II4
PWM4
+
+
−
4
OUT4
−
Timer latch short-circuit
protection circuit
Triangular wave
oscillator
Figure 11−6. Handling of Pins When Not Using ch5 and ch6
34
V
DD
Soft start circuit
C
SS5, CSS6
FB5, FB6
Undervoltage
lockout circuit
E/A5, E/A6
−
I
I5, II6
PWM5, PWM6
+
−
−
+
OUT5, OUT6
Timer latch short-circuit
protection circuit
Triangular wave
oscillator
29
Data Sheet S17102EJ2V0DS
µ PD16908
Figure 11−7. Handling of Pins When Not Using ch7 to ch9
E/A7 to E/A9
−
OUT7 to OUT9
+
I
I7 to II9
Figure 11−8. Handling of Pins When Not Using the Serial Interface
43
LVDD
SC
44
SDA
SCL
Serial
interface block
45
46
11.3 Method of Setting Oscillation Frequency
The oscillation frequency can be arbitrarily set by the timing resistor (RRT) connected to the RT (No. 39) pin, and the
timing capacitance (CCT) value connected to the CT (No. 38) pin.
Expression <1> shows an approximate expression of the oscillation frequency (fOSC). However, because this is an
approximate expression, be sure to check the frequency on the actual device, especially when using a high frequency.
fOSC [Hz] = 1.43/ (RRT [Ω] x CCT [F]) ⋅⋅⋅⋅⋅⋅ <1>
11.4 Method of Setting Soft-start Time
Expression <2> shows an approximate expression of the soft-start charge time of ch1 to ch4, tSS1 to tSS4.
tSS1 to tSS4 [s] = 0.775 x CSS [µF] ⋅⋅⋅⋅⋅⋅ <2>
Expression <3> shows an approximate expression of the soft-start charge time of ch5 and ch6, tSS5 and tSS6.
tSS5 and tSS6 [s] = 0.675 x CSS [µF] ⋅⋅⋅⋅⋅⋅ <3>
Note, however, that the startup characteristics of each channel differ depending on the load conditions of that
channel, as mentioned in 10.7 Soft Start Block of the Step-up DC-DC Converter Output (ch1 to ch4) (Figure
10−1), and 10.8 Soft Start Block of the Polarity-inverted DC-DC Converter Output (ch5 and ch6) (Figure
10−3),so tSS does not equal the rise time of the output voltage of each channel. Therefore, be sure to check the soft-
start time on the actual device.
30
Data Sheet S17102EJ2V0DS
µ PD16908
11.5 Method of Calculating Delay Time of Short-circuit Protection Circuit
Expression <4> shows an approximate expression of the short-circuit protection circuit delay time, tDLY.
tDLY [s] = 0.4 x CDLY [µF] ⋅⋅⋅⋅⋅⋅ <4>
11.6 Method of Handling Pins When Short-circuit Protection Circuit is Unused
When the short-circuit protection circuit is unused, connected the CDLY (No. 41) pin to the AGND (No. 18 and 42) pin.
11.7 Method of Preventing Malfunction of Short-circuit Protection Circuit
If noise is superimposed on the CDLY (No. 41) pin, the internal latch circuit may malfunction, causing the outputs to
stop operating.
To prevent this kind of malfunction, reduce the wiring impedance between the CDLY (No. 41) pin and the AGND (No.
18 and 42) pins, and take measures so that noise is not superimposed on the CDLY (No. 41) pin.
Note that if the soft-start time is longer than the short-circuit protection circuit may operate before the output of the
channel rises. Therefore, be sure to determine the short-circuit protection circuit delay time on the actual device.
11.8 Notes on Actual Pattern Wiring
When actually wiring the pattern, separate the ground of the control lines from the ground of the power lines, so that
there is as little common impedance by using a bypass capacitor (etc.), so that noise is not superimposed on the VDD
(No. 34) pin or the VREF (No. 40) pin.
11.9 Notes on Pin Connections
If there is more than one pin of any pin type, ensure that all the pins are connected. Also, always apply the same
potential to the power supply pins VDD (No. 34) pin, PVDD (No. 7) pin, and NPVDD (No. 11) pin.
31
Data Sheet S17102EJ2V0DS
µ PD16908
12. EXAMPLE OF APPLICATION CIRCUIT
µ
µ
µ
0.047 F
0.047
F
0.047
F
150 pF
µ
µ
µ
µ
µ
F
0.047
F
0.047
F
0.047
F
11 kΩ
0.1
41
F
0.1
40
2.7 to 5.5 V
24
28
32
37
17
21
39
38
C
SS1
C
SS2
C
SS3
C
SS4
C
SS5
C
SS6
R
T
C
T
C
DLY
V
REF
34
DD
+
22
Battery
2.7 to 5.5 V
V
NPV
µ
µ
µ
0.1
0.1
0.1
F
F
F
Triangular
wave
oscillator
Reference
voltage
2.0 V
µ
µ
µ
Timer latch
short-circuit
protection
circuit
F
F
F
DD11
Soft start circuit
+
22
PVDD
7
+
22
FB1
Undervoltage
lockout circuit
22
µ
10
H
ch1OUT
620 kΩ
100 kΩ
ch1OUT
OUT1
10
+
10
−
+
23
9 V/100 mA
2200 pF
+
−
−
I
I1
µ
µ
µ
µ
F
F
F
F
51 kΩ
9
PGND1
FB2
26
27
µ
10
H
ch2OUT
100 kΩ
510 kΩ
ch2OUT
8 V/100 mA
OUT2
−
+
+
10
2200 pF
+
−
−
I
I2
8
47 kΩ
FB3
30
31
µ
10
H
ch3OUT
100 kΩ
750 kΩ
ch3OUT
7.5 V/100 mA
OUT3
−
+
+
10
2200 pF
+
−
−
I
I3
6
5
75 kΩ
PGND2
FB4
35
36
µ
10 H
ch4OUT
100 kΩ
300 kΩ
ch4OUT
5 V/100 mA
OUT4
−
+
+
10
2200 pF
+
−
−
I
I4
4
75 kΩ
13
FB5
PGND3
V
REF
15
16
100 kΩ
150 kΩ
750 kΩ
OUT5
12
−
+
2200 pF
+
−
−
I
I5
ch5OUT
−4 V/150 mA
ch5OUT
µ
µ
10
+
F
F
FB6
µ
10
H
V
REF
19
20
100 kΩ
150 kΩ
750 kΩ
−
+
OUT6
14
2200 pF
N.C.
+
−
−
I
I6
ch6OUT
−4 V/150 mA
25
29
33
ch6OUT
10
+
µ
10
H
N.C.
2
1
N.C.
BVDD
3.3 V
−
OUT7
220 kΩ
DD 43
+
LV
ch7OUT
2.0 V/1 mA
+
TEST3
µ
10
F
F
F
3.3 V
48
II7
56
55
220 kΩ
SDA 45
−
OUT8
240 kΩ
SCL 46
CS 44
Control logic
block
and
serial interface
block
ch8OUT
1.8 V/1 mA
+
C
P
U
+
µ
10
II8
54
53
300 kΩ
DCON 51
−
OUT9
180 kΩ
47
SHDNB
ch9OUT
1.5 V/1 mA
+
+
µ
49
50
42
18
10
TEST1
II9
TEST2
AGND2
AGND1
52
3
360 kΩ
PGND4
Caution The constants shown in this figure are for reference only and do not guarantee the characteristics.
Set the constants and use appropriate components in accordance with the actual operating
conditions.
32
Data Sheet S17102EJ2V0DS
µ PD16908
13. PACKAGE DRAWING
56-PIN PLASTIC WQFN (8x8)
HD
D
D /2
HD /2
4−C0.5
42
43
29
28
A2
E /2
A1
C
HE E
DETAIL OF P PART
HE /2
15
14
56
1
x4
A
c1
c2
f
S A B
ZE
ZD
y1
S
b1
b
S
(UNIT:mm)
ITEM DIMENSIONS
y
D
E
7.75
TERMINAL SECTION
P
S
x4
7.75
0.20
8.00
8.00
0.20
B
f
t
S A B
HD
HE
t
+0.08
–0.04
A
0.67
A
+0.02
A1
0.03
0.64
–0.025
A2
b
0.23 0.05
0.20 0.03
0.17
b1
c
c1
c2
e
0.14−0.16
0.14−0.20
0.50
0.08MIN.
e
Lp
0.40 0.10
0.05
Lp
x
M
0.08MIN.
NOTES
b
x
S A B
1 "t" AND "f" EXCLUDES MOLD FLASH
0.08
y
2 ALTHOUGH THERE ARE 4 TERMINALS IN THE CORNER PART
OF A PACKAGE, THESE TERMINALS ARE NOT DESIGNED FOR
INTERCONNECTION, BUT FOR MANUFACTURING PROCESS OF
THE PACKAGE, THEREFOR DO NOT INTEND TO SOLDER THESE
4 TERMINALS, SOLDERABLITY OF THE 4 TERMINALS ARE NOT
GUARANTEED.
0.10
y1
ZD
ZE
0.625
0.625
P56K9-50-9B4
33
Data Sheet S17102EJ2V0DS
µ PD16908
14. RECOMMENDED SOLDERING CONDITIONS
The µ PD168103 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
µ PD16908K9-9B4-A: 56-pin plastic WQFN (8 x 8)
Process
Conditions
Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher),
Count: Three times or less, Exposure limit: 3 days Note (after that, prebake at 125°C
for 10 hours), Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended.
<Precaution>
IR60-103-3
Products other than in heat-resistant trays (such as those packaged in a magazine,
taping, or non-thermal-resistant tray) cannot be baked in their package.
Note After opening the dry pack, store it a 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
34
Data Sheet S17102EJ2V0DS
µ PD16908
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
35
Data Sheet S17102EJ2V0DS
µ PD16908
•
The information in this document is current as of October, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
UPD17002CU
Microcontroller, 4-Bit, MROM, 8MHz, CMOS, PDIP48, 0.600 INCH, SHRINK, PLASTIC, DIP-48
NEC
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