UPD44164362F5-E33-EQ1

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

µPD44164082, 44164182, 44164362

18M-BIT DDRII SRAM

2-WORD BURST OPERATION

Description

The µPD44164082 is a 2,097,152-word by 8-bit, the µPD44164182 is a 1,048,576-word by 18-bit and the µPD44164362

is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using

full CMOS six-transistor memory cell.

The µPD44164082, µPD44164182 and µPD44164362 integrates unique synchronous peripheral circuitry and a burst

counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.

These products are suitable for applications which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

• 1.8 ± 0.1 V power supply and HSTL I/O

• DLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output clocks (C and /C) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability with µs restart

• User programmable impedence output

• Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15821EJ2V0DS00 (2nd edition)

Date Published April 2002 NS CP(K)

Printed in Japan

The mark shows major revised points.

2001

©

µPD44164082, 44164182, 44164362

Ordering Information

Part number

Cycle

Clock

Organization Core Supply

I/O

Package

Time Frequency (word x bit)

Voltage

V

Interface

ns

MHz

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

µPD44164082F5-E30-EQ1

µPD44164082F5-E33-EQ1

µPD44164082F5-E40-EQ1

µPD44164082F5-E50-EQ1

µPD44164082F5-E60-EQ1

µPD44164182F5-E30-EQ1

µPD44164182F5-E33-EQ1

µPD44164182F5-E40-EQ1

µPD44164182F5-E50-EQ1

µPD44164182F5-E60-EQ1

µPD44164362F5-E30-EQ1

µPD44164362F5-E33-EQ1

µPD44164362F5-E40-EQ1

µPD44164362F5-E50-EQ1

µPD44164362F5-E60-EQ1

3.0

3.3

4.0

5.0

6.0

3.0

3.3

4.0

5.0

6.0

3.0

3.3

4.0

5.0

6.0

2 M x 8-bit

1 M x 18-bit

512 K x 36-bit

1.8 ± 0.1

HSTL

165-pin PLASTIC

FBGA (13 x 15)

Preliminary Data Sheet M15821EJ2V0DS

2

µPD44164082, 44164182, 44164362

Pin Configurations (Marking Side)

/××× indicates active low signal.

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44164082F5-EQ1]

1

2

3

A

4

5

/NW1

NC

A

6

7

NC

/NW0

A

8

9

A

10

V^SS

NC

V^REF

DQ1

NC

TMS

11

CQ

DQ3

NC

DQ2

NC

ZQ

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

VSS

NC

V^REF

NC

DQ6

NC

TCK

R, /W

A

/K

/LD

A

NC

DQ4

NC

DQ5

V^DDQ

NC

DQ7

A

K

NC

V^DDQ

NC

A

V^SS

A

V^SS

V^DD

V^SS

A

V^SS

A

V^SS

V^DD

V^SS

A

V^SS

V^DDQ

V^SS

V^DDQ

V^SS

G

H

J

NC

DQ0

NC

TDI

K

L

M

N

P

R

V^SS

A

C

A

/C

A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: Echo clock

DQ0 to DQ7

/LD

: Data inputs / outputs

: Synchronous load

: Read Write input

: Nybble Write data select

: Input clock

TDI

TCK

TDO

CQ, /CQ

V^REF

VDD

R, /W

/NW0, /NW1

K, /K

: HSTL input reference input

: Power Supply

: Ground

C, /C

: Output clock

ZQ

: Output impedance matching

: DLL disable

V^DDQ

V^SS

/DLL

NC

: No connection

Remark Refer to Package Drawing for the index mark.

Preliminary Data Sheet M15821EJ2V0DS

3

µPD44164082, 44164182, 44164362

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44164182F5-EQ1]

1

2

V^SS

3

4

5

/BW1

NC

A

6

7

NC

/BW0

A

8

9

A

10

V^SS

NC

11

CQ

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

A

R, /W

A

/K

/LD

A

DQ9

NC

K

NC

V^DDQ

NC

A

DQ8

NC

V^SS

A0

V^SS

A

V^SS

DQ7

NC

DQ10

DQ11

NC

V^SS

V^DD

V^SS

A

V^SS

V^DD

V^SS

A

V^SS

NC

V^DDQ

V^SS

V^DDQ

V^SS

NC

DQ6

DQ5

NC

DQ12

NC

G

H

J

DQ13

V^DDQ

NC

V^REF

NC

V^REF

DQ4

NC

ZQ

NC

K

L

NC

DQ14

NC

DQ3

DQ2

NC

DQ15

NC

M

N

P

R

NC

DQ1

NC

DQ16

DQ17

A

V^SS

NC

A

C

A

NC

DQ0

TDI

TCK

A

/C

A

TMS

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: Echo clock

DQ0 to DQ17

/LD

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

CQ, /CQ

V^REF

V^DD

R, /W

/BW0, /BW1

K, /K

: HSTL input reference input

: Power Supply

: Ground

C, /C

: Output clock

ZQ

: Output impedance matching

: DLL disable

VDDQ

V^SS

/DLL

NC

: No connection

Remark Refer to Package Drawing for the index mark.

Preliminary Data Sheet M15821EJ2V0DS

4

µPD44164082, 44164182, 44164362

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44164362F5-EQ1]

1

2

3

4

5

/BW2

/BW3

A

6

7

/BW1

/BW0

A

8

9

A

10

V^SS

11

CQ

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

V^SS

NC

R, /W

A

/K

/LD

A

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

V^DDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

A

K

NC

V^DDQ

NC

A

NC

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

V^SS

A0

V^SS

A

V^SS

DQ17

NC

DQ29

NC

V^SS

V^DD

V^SS

A

V^SS

V^DD

V^SS

A

V^SS

V^DDQ

V^SS

V^DDQ

V^SS

DQ15

NC

DQ30

DQ31

V^REF

NC

G

H

J

NC

V^REF

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

NC

DQ33

NC

M

N

P

R

DQ11

NC

DQ35

NC

V^SS

A

C

A

DQ9

TMS

TCK

A

/C

A

A0, A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: Echo clock

DQ0 to DQ35

/LD

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

CQ, /CQ

V^REF

V^DD

R, /W

/BW0 to /BW3

K, /K

: HSTL input reference input

: Power Supply

: Ground

C, /C

: Output clock

ZQ

: Output impedance matching

: DLL disable

VDDQ

V^SS

/DLL

NC

: No connection

Remark Refer to Package Drawing for the index mark.

Preliminary Data Sheet M15821EJ2V0DS

5

µPD44164082, 44164182, 44164362

Pin Identification

Symbol

Description

A0

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on future

devices. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used as the

lowest order address bit permitting a random starting address within the burst operation. These inputs are

ignored when device is deselected.

/LD

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition

includes address and read/write direction. All transactions operate on a burst of 2 data (one clock periods of

bus activity).

R, /W

Synchronous Read/Write Input: When /LD is LOW, this input designates the access type (READ when /R, W is

HIGH, WRITE when /R, W is LOW) for the loaded address. /R, W must meet the setup and hold times around

the rising edge of K.

/NWx

/BWx

Synchronous Byte Writes (Nybble Writes on x8): When LOW these inputs cause their respective byte or nybble

to be registered and written during WRITE cycles. These signals must meet setup and hold times around the

rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations

for signal to data relationships.

K, /K

C, /C

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous

inputs must meet setup and hold times around the clock rising edges.

Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of

C is used as the output timing reference for first output data. The rising edge of /C is used as the output

reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to

force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied

HIGH, C and /C must remain HIGH and not be toggled during device operation.

/DLL

ZQ

DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to

ground. Alternately, this pin can be connected directly to V^DDQ, which enables the minimum impedance mode.

This pin cannot be connected directly to GND or left unconnected.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK

IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to V^SSif the JTAG function is not used in the

circuit.

VREF

HSTL Input Reference Voltage: Nominally V^DDQ/2. Provides a reference voltage for the input buffers.

DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and /K. Output

data is synchronized to the respective C and /C data clocks or to K and /K if C and /C are tied to HIGH.

x8 device uses DQ0-DQ7. Remaining signals are NC.

x18 device uses DQ0-DQ17. Remaining signals are NC.

x36 device uses DQ0-DQ35. Remaining signals are NC.

NC signals are read in the JTAG scan chain as the logic level applied to the ball site.

CQ, /CQ

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q

tristates.

TDO

VDD

IEEE 1149.1 Test Output: 1.8V I/O level.

Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics

and Operating Conditions for range.

VSS

NC

Power Supply: Ground

No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level

applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.

Preliminary Data Sheet M15821EJ2V0DS

6

µPD44164082, 44164182, 44164362

Block Diagram

CLK

Burst

Logic

A0'

A0

D0

Q0

R

Address

Register

Address

/LD

/W

E

Compare

/C

C

A0''

A0'''

Output control

Logic

Write address

Register

K

E

A0'

Input

Register

/A0'

A0'

ZQ

0

2 :1

MUX

Memory

Array

CLK

/A0'

C

1

A0'

Output Buffer

E

DQ

0

1

/K

Input

Register

E

A0'''

Output Enable

Register

C

R, /W

Register

E

Burst Sequence

Linear Burst Sequence Table

[µPD44164182, µPD44164362]

A0

0

A0

1

External Address

1st Internal Burst Address

1

0

Preliminary Data Sheet M15821EJ2V0DS

7

µPD44164082, 44164182, 44164362

Truth Table

Operation

/LD R, /W

CLK

DQ

WRITE cycle

L

L → H

Data in

Load address, input write data on two

consecutive K and /K rising edge

READ cycle

Input data

Input clock

D(A1)

D(A2)

K(t+1) ↑

/K(t+1) ↑

L

H

L → H

Data out

Load address, read data on two

consecutive C and /C rising edge

NOP (No operation)

Output data

Output clock

Q(A1)

Q(A2)

/C(t+1) ↑

C(t+2) ↑

H

X

L → H

Hi-Z

Previous state

STANDBY(Clock stopped)

Stopped

Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges

except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst

address in accordance with the linear burst sequence.

7. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

Preliminary Data Sheet M15821EJ2V0DS

8

µPD44164082, 44164182, 44164362

Byte Write Operation

[µPD44164082]

Operation

Write D0-7

K

L → H

–

/K

–

/NW0

/NW1

0

1

0

1

0

1

L → H

–

Write D0-3

Write D4-7

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44164182]

Operation

Write D0-17

K

L → H

–

/K

–

/BW0

/BW1

0

1

0

1

0

1

L → H

–

Write D0-8

L → H

–

L → H

–

Write D9-17

Write nothing

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44164362]

Operation

Write D0-35

K

L → H

–

/K

–

/BW0

/BW1

/BW2

/BW3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L → H

–

Write D0-8

L → H

–

L → H

–

Write D9-17

Write D18-26

Write D27-35

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

Preliminary Data Sheet M15821EJ2V0DS

9

µPD44164082, 44164182, 44164362

Bus Cycle State Diagram

LOAD NEW

ADDRESS

Count = 0

Load, Count = 2

READ DOUBLE

Write

Read

WRITE DOUBLE

Count = Count + 2

COUNT = Count + 2

Load

NOP,

Count = 2

NOP

Supply voltage provided

Power UP

Remarks 1. A0 is internally advanced in accordance with the burst order table.

Bus cycle is terminated after burst count = 2.

2. State machine control timing sequence is controlled by K.

Preliminary Data Sheet M15821EJ2V0DS

10

µPD44164082, 44164182, 44164362

Electrical Specifications

Absolute Maximum Ratings

Parameter

Unit

Symbol Conditions

MIN.

–0.5

TYP.

MAX.

V

Supply voltage

VDD

VDDQ

VIN

+2.9

Output supply voltage

Input voltage

VDD

VDD + 0.5 (2.9 V MAX.)

VDDQ + 0.5 (2.9 V MAX.)

+125

V

Input / Output voltage

Junction temperature

Storage temperature

VI/O

Tj

°C

Tstg

–55

+125

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (Tj = 20 to 110 °C)

Parameter

Supply voltage

Symbol

VDD

Conditions

MIN.

1.7

TYP.

MAX.

1.9

Unit

V

Note

Output supply voltage

High level input voltage

Low level input voltage

Clock input voltage

VDDQ

VIH

1.4

VDD

V

VREF + 0.1

–0.3

VDDQ + 0.3

VREF – 0.1

VDDQ + 0.3

0.95

V

1

VIL

V

VIN

–0.3

V

Reference voltage

VREF

0.68

V

Note1 Overshoot: V^{IH (AC)}≤ VDD + 0.7 V for t ≤ TKHKH/2

Undershoot: VIL (AC) ≥ – 0.5V for t ≤ TKHKH/2

Power-up: V^IH≤ VDDQ + 0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V for t ≤ 200 ms

During normal operation, VDDQ must not exceed VDD.

Control input signals may not have pulse widths less than TKHKL (MIN) or operate at cycle rates

less than TKHKH (MIN).

Capacitance (TA = 25 °C, f = 1MHz)

Parameter

Input capacitance

Symbol

CIN

Test conditions

VIN = 0 V

MIN.

TYP.

MAX.

Unit

pF

4

6

5

7

6

Input / Output capacitance

Clock Input capacitance

CI/O

VI/O = 0 V

Vclk = 0 V

pF

Cclk

pF

Remark These parameters are periodically sampled and not 100% tested.

Preliminary Data Sheet M15821EJ2V0DS

11

µPD44164082, 44164182, 44164362

DC Characteristics (T^j= 20 to 110°C, V^DD= 1.8 ± 0.1 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

Note

x8, x18 x36

Input leakage current

I/O leakage current

Operating supply current

(Read Write cycle)

ILI

–2

–

+2

µA

ILO

IDD

V^IN≤ VIL or V^IN≥ VIH, –E30

525

475

400

330

280

255

235

200

170

150

710

640

545

445

380

265

240

210

180

160

mA

II/O = 0 mA

–E33

–E40

–E50

–E60

Cycle = MAX.

Standby supply current

(NOP)

ISB1

V^IN≤ VIL or V^IN≥ VIH, –E30

mA

II/O = 0 mA

–E33

–E40

–E50

–E60

Cycle = MAX.

High level output voltage

Low level output voltage

VOH(Low) |IOH| ≤ 0.1 mA

Note1

VDDQ – 0.2

VDDQ/2–0.08

VSS

–

VDDQ

V

3, 4

VOH

VDDQ/2+0.08

0.2

VOL(Low) I^OL≤ 0.1 mA

Note2

VOL

VDDQ/2–0.08

VDDQ/2+0.08

Notes 1. Outputs are impedance-controlled. | I^OH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impedance-controlled. I^OL= (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values. AC I/O curves are available upon request.

4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.

Preliminary Data Sheet M15821EJ2V0DS

12

µPD44164082, 44164182, 44164362

AC Characteristics (T^j= 20 °C to 110 °C, V^DD= 1.8 ± 0.1 V)

AC Test Conditions

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

Test Points

0.25 V

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

V

DDQ / 2

0.75 V

50 Ω

V

REF

ZO = 50 Ω

SRAM

250 Ω

ZQ

Remark CL includes capacitances of the probe and jig, and stray capacitances.

Preliminary Data Sheet M15821EJ2V0DS

13

µPD44164082, 44164182, 44164362

Read and Write Cycle

-E30

(333 MHz) (300 MHz) (250 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

-E33

-E40

-E50

-E60

Parameter

Symbol

Unit Note

(200 MHz) (167 MHz)

Clock

Average Clock cycle time (K, /K, C, /C) TKHKH

ns

1

2

3.0

–

3.6

0.2

–

3.3

–

4.0

0.2

–

4.0

–

5.0

0.2

–

5.0

–

6.0

0.2

–

6.0

–

7.5

0.2

–

Clock phase jitter (K, /K, C, /C)

Clock HIGH time (K, /K, C, /C)

Clock LOW time (K, /K, C, /C)

Clock to /clock (K→/K., C→/C.)

Clock to /clock (/K→K., /C→C.)

Clock to data clock (K→C., /K→/C.)

DLL lock time (K, C)

TKC var

TKHKL

ns

1.20

1.35

0

1.32

1.49

0

1.6

1.8

0

2.0

2.2

0

2.4

2.7

0

TKLKH

ns

–

TKH /KH

T /KHKH

TKHCH

ns

–

ns

–

ns

1.30

–

1.45

–

1.8

–

2.3

–

2.8

–

TKC lock

TKC reset

Cycle

ns

3

1,024

30

1,024

30

1,024

30

1,024

30

1,024

30

K static to DLL reset

–

Output Times

C, /C HIGH to output valid

C, /C HIGH to output hold

C, /C HIGH to echo clock valid

C, /C HIGH to echo clock hold

CQ, /CQ HIGH to output valid

CQ, /CQ HIGH to output hold

C HIGH to output High-Z

C HIGH to output Low-Z

TCHQV

TCHQX

ns

–

– 0.27

–

0.27

–

– 0.29

–

0.29

–

– 0.35

–

0.35

–

– 0.38

–

0.38

–

– 0.40

–

0.40

–

TCHCQV

TCHCQX

TCQHQV

TCQHQX

TCHQZ

0.25

–

0.27

–

0.33

–

0.36

–

0.38

–

– 0.25

–

– 0.27

–

– 0.33

–

– 0.36

–

– 0.38

–

4

0.27

–

0.29

–

0.35

–

0.38

–

0.40

–

– 0.27

–

– 0.29

–

– 0.35

–

– 0.38

–

– 0.40

–

0.27

–

0.29

–

0.35

–

0.38

–

0.40

–

TCHQX1

– 0.27

– 0.29

– 0.35

– 0.38

– 0.40

Setup Times

Address valid to K rising edge

Control inputs valid to K rising edge

Data-in valid to K, /K rising edge

TAVKH

TIVKH

TDVKH

ns

5

0.4

0.3

–

0.4

–

0.5

0.4

–

0.6

0.5

–

0.7

0.6

–

0.33

Hold Times

K rising edge to address hold

K rising edge to control inputs hold

K, /K rising edge to data-in hold

TKHAX

TKHIX

TKHDX

ns

5

0.4

0.3

–

0.4

–

0.5

0.4

–

0.6

0.5

–

0.7

0.6

–

0.33

Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).

2. Clock phase jitter is the variance from clock rising edge to the next expected colck rising edge.

3. V^DDslew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.

DLL lock time begins once V^DDand input clock are stable.

It is recommended that the device is kept inactive during these cycles.

4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

5. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN).

4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.

5. V^DDQ is 1.5 VDC.

Preliminary Data Sheet M15821EJ2V0DS

14

µPD44164082, 44164182, 44164362

Read and Write Timing

READ

NOP

READ

NOP

WRITE

READ

(burst of 2)

(burst of 2) (burst of 2)

(burst of 2)

1

2

3

4

5

6

7

8

9

10

TKHKH

K

TKHKL TKLKH

TKLKH

TKH/KH

T/KHKH

/K

/LD

TIVKH

TKHIX

R, /W

TAVKH

TKHAX

Address

DQ

A0

A1

A2

A3

A4

TKHDX

TDVKH

D21

D22

D23

D24

Q01 Q02 Q11

TCHQX

Q12

Qx2

Q41 Q42

TCQHQX

TCQHQV

TCHQX1

TCHQV

TCHQZ

TCHQX

TKHCH

TCHQV

CQ

TCHCQX

TCHCQV

/CQ

C

TCHCQX

TCHCQV

TKHKL TKLKH TKHKH TKH/KH T/KHKH

/C

Remarks 1. Q01 refers to output from address A0.

Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disable (High-Z) one clock cycle after a NOP.

3. The second NOP cycle is not necessary for correct device operation;

however, at high clock frequencies it may be required to prevent bus contention.

Preliminary Data Sheet M15821EJ2V0DS

15

µPD44164082, 44164182, 44164362

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

2R

Description

Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

Test Mode Select. This is the command input for the TAP controller state machine.

TMS

TDI

10R

11R

Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is deter-mined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

1R

Test Data Output. Output changes in response to the falling edge of TCK. This is the

output side of the serial registers placed between TDI and TDO.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (20 °C ≤ Tj ≤ 110 °C, 1.7 V ≤ V^DD≤ 1.9 V, unless otherwise noted)

Parameter

Symbol

ILI

Conditions

0 V ≤ V^IN≤ V^DD

MIN.

–5.0

TYP.

MAX.

+5.0

Unit

µA

Note

JTAG Input leakage current

JTAG I/O leakage current

–

ILO

0 V ≤ V^IN≤ V^DDQ,

µA

Outputs disabled

JTAG input high voltage

JTAG input low voltage

JTAG output high voltage

VIH

VIL

1.3

–0.3

1.6

1.4

–

VDD+0.3

V

+0.5

–

VOH1

VOH2

VOL1

VOL2

| IOHC | = 100 µA

| IOHT | = 2 mA

IOLC = 100 µA

IOLT = 2 mA

–

JTAG output low voltage

0.2

0.4

–

Preliminary Data Sheet M15821EJ2V0DS

16

µPD44164082, 44164182, 44164362

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

Preliminary Data Sheet M15821EJ2V0DS

17

µPD44164082, 44164182, 44164362

JTAG AC Characteristics (Tj = 5 to 110 °C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Note

Clock

Clock cycle time

Clock frequency

Clock high time

Clock low time

t^THTH

f^TF

t^THTL

t^TLTH

100

–

10

–

ns

MHz

ns

40

–

ns

Output time

TCK low to TDO unknown

TCK low to TDO valid

TDI valid to TCK high

TCK high to TDI invalid

t^TLOX

t^TLOV

t^DVTH

t^THDX

0

–

20

–

ns

10

–

Setup time

TMS setup time

Capture setup time

t^MVTH

t^CS

10

–

ns

Hold time

TDI hold time

Capture hold time

t^THMX

t^CH

10

–

ns

JTAG Timing Diagram

Preliminary Data Sheet M15821EJ2V0DS

18

µPD44164082, 44164182, 44164362

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The shift register bit

nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the

input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

107

bit

Boundary register

bit

ID Register Definition

Part number Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 0001 0010

0000 0000 0001 0011

0000 0000 0001 0100

ID [11:1] vendor ID no.

00000010000

ID [0] fix bit

µPD44164082

µPD44164182

µPD44164362

2M x 8

1M x 18

XXXX

1

00000010000

512K x 36

00000010000

Preliminary Data Sheet M15821EJ2V0DS

19

µPD44164082, 44164182, 44164362

SCAN Exit Order

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

no.

x8

x18 x36

no.

x8

x18

x36

no.

x8

x18

NC

x36

NC

1

2

/C

C

A

6R

6P

6N

7P

7N

7R

8R

8P

9R

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

NC

10D

9E

73

74

NC

2C

3E

2D

2E

1E

2F

3F

1G

1F

DQ4 DQ11 DQ20

3

NC DQ7 DQ17 10C

75

NC

DQ29

NC

4

NC

NC DQ16 11D

76

5

NC

9C

9D

77

NC

6

78

DQ12 DQ30

7

DQ3 DQ8 DQ8 11B

79

NC

DQ21

NC

8

NC

NC DQ7 11C

80

9

NC

CQ

V^SS

A

NC

9B

10B

11A

10A

9A

81

NC

10

11

12

13

14

15

16

17

NC DQ0 DQ0 11P

82

DQ5 DQ13 DQ22 3G

NC

NC DQ9 10P

83

NC

DQ31 2G

NC

10N

9P

84

NC

1J

2J

85

NC DQ1 DQ11 10M

A

8B

86

DQ14 DQ23

3K

3J

NC

NC DQ10 11N

A

7C

87

NC

DQ32

NC

9M

9N

A

A0

/LD

A0

6C

88

2K

1K

2L

3L

1M

1L

3N

8A

89

NC

18 DQ0 DQ2 DQ2 11L

NC

NC /BW1 7A

90

DQ6 DQ15 DQ33

19

20

21

22

23

24

25

NC

NC DQ1 11M

55 /NW0 /BW0 /BW0 7B

91

NC

DQ24

NC

9L

56

57

58

K

6B

6A

92

10L

/K

93

NC

NC DQ3 DQ3 11K

NC

NC /BW3 5B

94

DQ16 DQ25

NC

NC DQ12 10K

59 /NW1 /BW1 /BW2 5A

95

NC

DQ34 3M

NC

9J

60

61

62

63

64

65

66

67

68

69

70

71

72

R, /W

A

4A

5C

4B

3A

2A

1A

96

NC

1N

2M

3P

2N

2P

1P

3R

4R

4P

5P

5N

5R

9K

97

26 DQ1 DQ4 DQ13 10J

A

98

DQ7 DQ17 DQ26

27

28

29

30

31

32

33

34

NC

NC DQ4 11J

A

NC

99

NC

A

DQ35

NC

ZQ

NC

11H

10G

9G

V^SS

/CQ

100

101

102

103

104

105

106

107

NC

NC DQ9 DQ27 2B

NC DQ5 DQ5 11F

NC

NC DQ18 3B

A

NC

NC DQ14 11G

NC

1C

1B

A

NC

9F

A

10F

NC DQ10 DQ19 3D

A

35 DQ2 DQ6 DQ6 11E

36 NC NC DQ15 10E

NC

NC DQ28 3C

NC NC 1D

A

Preliminary Data Sheet M15821EJ2V0DS

20

µPD44164082, 44164182, 44164362

JTAG Instructions

Instructions

EXTEST

Description

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction

register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented

in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does

respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the

instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the

RAM output are forced to Hi-Z any time the instruction is loaded.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed

in the test-logic-reset state.

BYPASS

SAMPLE

The BYPASS instruction is loaded in the instruction register when the bypass register is placed between

TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the

board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE is a Standard 1149.1 mandatory public instruction. When the SAMPLE instruction is loaded in

the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs

input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from

the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input

buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable

input will not harm the device, repeatable results cannot be expected. RAM input signals must be

stabilized for long enough to meet the TAPs input data capture setup plus hold time (t^CSplus t^CH). The

RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring

contents into the boundary scan register. Moving the controller to shift-DR state then places the

boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1

compliant.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive

drive state (Hi-Z) and the boundary register is connected between TDI and TDO when the TAP controller

is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

1

0

1

IDCODE

0

1

0

SAMPLE-Z

RESERVED

SAMPLE

1

0

1

0

1

0

1

RESERVED

BYPASS

1

0

1

Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.

Preliminary Data Sheet M15821EJ2V0DS

21

µPD44164082, 44164182, 44164362

TAP Controller State Diagram

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs.

TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and

may be left unconnected. But they may also be tied to VDD through a 1k resistor.

TDO should be left unconnected.

Preliminary Data Sheet M15821EJ2V0DS

22

µPD44164082, 44164182, 44164362

Package Drawing

165-PIN PLASTIC FBGA (13x15)

E

w S B

ZD

ZE

B

11

10

9

8

7

A

6

5

D

4

3

2

1

R P N M L K J H G F E D C B A

w S A

INDEX MARK

y1 S

A2

h

A

S

ITEM MILLIMETERS

A1

e

y

D

E

13.00

15.00

1.50

0.50

1.00

0.60

1.40

0.40

1.00

0.45

0.08

0.15

0.20

S

ZD

ZE

e

φ M

x

φ

b

S A B

h

A

A1

A2

b

y

x

w

y1

This package drawing is a preliminary version. It may be changed in the future.

Preliminary Data Sheet M15821EJ2V0DS

25

µPD44164082, 44164182, 44164362

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

µPD44164082F5-EQ1: 165-pin PLASTIC FBGA (13 x 15)

µPD44164182F5-EQ1: 165-pin PLASTIC FBGA (13 x 15)

µPD44164362F5-EQ1: 165-pin PLASTIC FBGA (13 x 15)

Preliminary Data Sheet M15821EJ2V0DS

26

µPD44164082, 44164182, 44164362

Revision History

Edition/

Page

2nd edition/ Throughout Throughout Modification Pin Configurations, Pin Identification,

Type of

Location

Description

Date

This

edition

revision

(Previous edition → This edition)

Address inputs: Ax → A

April 2002

Scan Exit Order

p.1

Modification Function Name

18M-BIT CMOS SYNCHRONOUS

FAST SRAM DOUBLE DATA RATE

→ 18M-BIT DDRII SRAM

µPD44164362

Addition

Description

p.2

Modification Ordering Information

Deletion

Package code: Fx-EQx → F5-EQ1

Remark

p.3-5

p.6

p. 3-5

p.6

Modification Pin Configurations

Modification Pin Identification

Modification Block Diagram

Package code: Fx → F5-EQ1

ZQ: V^DD→ V^DDQ

p.7

/K → K

Linear Burst Sequence Table

Internal Burst Address

→ 1st Internal Burst Address

Item of Ax

Deletion

p.14

Modification TKC var (MAX.)

-E30: 0.08 → 0.2, -E33: 0.08 → 0.2,

-E40: 0.10 → 0.2, -E50: 0.13 → 0.2,

-E60: 0.15 → 0.2

TKH /KH (MAX.)

-E30: 1.65 → −, -E33: 1.82 → −,

-E40: 2.2 → −, -E50: 2.75 → −,

-E60: 3.3 → −

Addition

Modification TAVKH, TIVKH, TKHAX, TKHIX (MIN.) -E40: 0.4 → 0.5

TDVKH, TKHDX (MIN.) -E30: 0.4 → 0.3, -E33: 0.4 → 0.33,

T /KHKH

-E50: 0.6 → 0.5, -E60: 0.7 → 0.6

Note 1, 2, 4

Addition

Modification

Addition

Note 1 → 5, Note 2 → 3

Note 3

Remark 5

p.15

p.20

p.25

p.26

p.15

p.20

p.25

p.26

Addition

Read and Write Timing

T /KHKH

Modification Scan Exit Order

Addition Package Drawing

Modification Types of Surface Mount Devices

Bit no. 48, 64: NC → V^SS

Package drawing (Preliminary version)

Package code: Fx → F5-EQ1

Preliminary Data Sheet M15821EJ2V0DS

27

µPD44164082, 44164182, 44164362

[MEMO]

Preliminary Data Sheet M15821EJ2V0DS

28

µPD44164082, 44164182, 44164362

[MEMO]

Preliminary Data Sheet M15821EJ2V0DS

29

µPD44164082, 44164182, 44164362

[MEMO]

Preliminary Data Sheet M15821EJ2V0DS

30

µPD44164082, 44164182, 44164362

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Preliminary Data Sheet M15821EJ2V0DS

31

µPD44164082, 44164182, 44164362

•

The information in this document is current as of April, 2002. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data

books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products

and/or types are available in every country. Please check with an NEC sales representative for

availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4


型号：	UPD44164362F5-E33-EQ1
厂家：	RENESAS TECHNOLOGY CORP
描述：	DDR SRAM, 512KX36, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165 双倍数据速率静态存储器
文件：	总32页 (文件大小：211K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD44164362F5-E33-EQ1 [RENESAS]

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