UPD44321182GF-A60Y [RENESAS]
ZBT SRAM, 2MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100;
| 型号： | UPD44321182GF-A60Y |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ZBT SRAM, 2MX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD44321182, 44321362
32M-BIT ZEROSBSRAM
PIPELINED OPERATION
Description
The µPD44321182 is a 2,097,152-word by 18-bit and the µPD44321362 is a 1,048,576-word by 36-bit ZEROSB
static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD44321182 and µPD44321362 are optimized to eliminate dead cycles for read to write, or write to read
transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and
output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input
(CLK).
The µPD44321182 and µPD44321362 are suitable for applications which require synchronous operation, high speed,
low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The µPD44321182 and µPD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for
high density and low capacitive loading.
Features
• Low voltage core supply : VDD = 3.3 ± 0.165 V / 2.5 ± 0.125 V
• Synchronous operation
• Operating temperature : TA = 0 to 70 °C (-A50, -A60)
TA = –40 to +85 °C (-A50Y, -A60Y)
• 100 percent bus utilization
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs and outputs for pipelined operation
• All registers triggered off positive clock edge
• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 3.2 ns (200 MHz), 3.5 ns (167 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 to /BW4 (µPD44321362)
/BW1 and /BW2 (µPD44321182)
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
The mark
shows major revised points.
Document No. M16024EJ4V0DS00 (4th edition)
Date Published November 2003 NS CP(K)
Printed in Japan
2002
µPD44321182, 44321362
Ordering Information
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Operating
Temperature
°C
Package
µPD44321182GF-A50
3.2
3.5
3.2
3.5
3.2
3.5
3.2
3.5
200
167
200
167
200
167
200
167
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
3.3 ± 0.165 3.3 V or 2.5 V LVTTL
2.5 ± 0.125 2.5 V LVTTL
0 to 70
100-pin PLASTIC
LQFP (14 x 20)
µPD44321182GF-A60
µPD44321362GF-A50
µPD44321362GF-A60
µPD44321182GF-A50Y Note
µPD44321182GF-A60Y Note
µPD44321362GF-A50Y Note
µPD44321362GF-A60Y Note
–40 to +85
Note Under development
2
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Pin Configurations
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 × 20)
[µPD44321182GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A20
NC
NC
2
3
V
DDQ
4
V
V
DD
Q
V
SSQ
5
SSQ
NC
NC
6
NC
7
I/OP1
I/O8
I/O9
8
I/O10
9
I/O7
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
Q
V
DD
DD
Q
I/O11
I/O12
I/O6
I/O5
V
V
V
DD
DD
DD
V
V
V
SS
DD
DD
V
SS
ZZ
I/O13
I/O14
I/O4
I/O3
V
DD
Q
Q
V
V
DD
Q
V
SS
SSQ
I/O15
I/O16
I/OP2
NC
I/O2
I/O1
NC
NC
V
SS
Q
Q
V
V
SS
Q
V
DD
DD
Q
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for the 1-pin index mark.
3
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Pin Identifications
[µPD44321182GF]
Symbol
Pin No.
Description
A0 to A20
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 83, 84, 43, 80
I/O1 to I/O16
I/OP1, I/OP2
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,
18, 19, 22, 23
74, 24
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
ADV
85
/CE, CE2, /CE2
/WE
98, 97, 92
88
/BW1, /BW2
/G
93, 94
86
CLK
89
/CKE
87
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
31
ZZ
64
VDD
VSS
14, 15, 16, 41, 65, 66, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Power Supply
Output Buffer Ground
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 51, No Connection
52, 53, 56, 57, 75, 78, 79, 95, 96
4
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
100-pin PLASTIC LQFP (14 × 20)
[µPD44321362GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O17
I/O18
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2
I/O16
I/O15
2
3
V
DD
Q
Q
4
V
V
DD
Q
V
SS
5
SSQ
I/O19
I/O20
I/O21
I/O22
6
I/O14
I/O13
I/O12
I/O11
7
8
9
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
Q
V
DD
DD
Q
I/O23
I/O24
I/O10
I/O9
VDD
VDD
VDD
V
V
V
SS
DD
DD
V
SS
ZZ
I/O25
I/O26
I/O8
I/O7
V
DD
Q
Q
V
V
DD
Q
V
SS
SSQ
I/O27
I/O28
I/O29
I/O30
I/O6
I/O5
I/O4
I/O3
V
SS
Q
Q
V
V
SS
Q
V
DD
DD
Q
I/O31
I/O32
I/OP4
I/O2
I/O1
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for the 1-pin index mark.
5
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Pin Identifications
[µPD44321362GF]
Symbol
Pin No.
Description
A0 to A19
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 83, 84, 43
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
I/OP1 to I/OP4
51, 80, 1, 30
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
ADV
85
/CE, CE2, /CE2
/WE
98, 97, 92
88
/BW1 to /BW4
/G
93, 94, 95, 96
86
89
87
31
CLK
/CKE
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
ZZ
64
VDD
VSS
14, 15, 16, 41, 65, 66, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
38, 39, 42
Output Buffer Power Supply
Output Buffer Ground
No Connection
6
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Block Diagrams
[µPD44321182]
21
19
21
A0 to A20
MODE
Address
register 0
A1
A0
A1’
A0’
Burst
logic
ADV
K
K
CLK
/CKE
21
21
Write address
register 1
Write address
register 0
Memory Cell Array
ADV
/BW1
/BW2
Write registry and
data coherency
control logic
Write
drivers
1,024 rows
18
18
I/O1 to I/O16
I/OP1, I/OP2
2,048 x 18 columns
(37,748,736 bits)
/WE
E
E
18
18
18
Input
register 1
Input
register 0
E
E
Read
logic
/G
/CE
CE2
/CE2
ZZ
Power down control
Burst Sequence
[µPD44321182]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A20 to A2, A1, A0
A20 to A2, A1, /A0
A20 to A2, /A1, A0
A20 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
7
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
[µPD44321362]
20
18
20
A0 to A19
MODE
Address
register 0
A1
A0
A1’
A0’
Burst
logic
ADV
K
K
CLK
/CKE
20
20
Write address
register 1
Write address
register 0
Memory Cell Array
1,024 rows
ADV
/BW1
/BW2
/BW3
/BW4
/WE
Write registry and
data coherency
control logic
Write
drivers
36
36
I/O1 to I/O32
I/OP1 to I/OP4
1,024 x 36 columns
(37,748,736 bits)
E
E
36
36
36
Input
register 1
Input
register 0
E
E
Read
logic
/G
/CE
CE2
/CE2
ZZ
Power down control
Burst Sequence
[µPD44321362]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A19 to A2, A1, A0
A19 to A2, A1, /A0
A19 to A2, /A1, A0
A19 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
8
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
State Diagram
DS
BURST
DS
DS
DESELECT
READ
WRITE
DS
DS
WRITE
READ
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
BURST
BURST
WRITE
WRITE
READ
BURST
READ
BURST
WRITE
BURST
BURST
Command
DS
Operation
Deselect
Read
New Read
New Write
Write
Burst
Burst Read, Burst Write or Continue Deselect
Remarks 1. States change on the rising edge of the clock.
2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH
only blocks the clock (CLK) input and does not change the state of the device.
9
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Asynchronous Truth Table
Operation
Read Cycle
/G
L
I/O
Data-Out
High-Z
Read Cycle
H
×
Write Cycle
High-Z, Data-In
High-Z
Deselected
×
Remark × : don’t care
Synchronous Truth Table
Operation
Deselected
/CE
H
×
CE2 /CE2 ADV
/WE /BWs /CKE
CLK
I/O
Address
None
Note
×
L
×
×
H
×
H
×
H
×
×
×
×
H
×
L
×
L
×
L
×
×
L
L
×
×
×
×
H
×
L
×
L
×
×
×
×
×
×
×
×
L
L
H
H
×
L
L
L
L
L
L
L
L
L
L
H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
High-Z
High-Z
High-Z
High-Z
Data-Out
Data-Out
Data-In
Data-In
High-Z
High-Z
−
1
1
1
1
Deselected
None
Deselected
×
L
None
Continue Deselected
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Write Abort
Write Cycle / Write Abort
Stall / Ignore Clock Edge
×
H
L
None
L
External
Next
×
H
L
L
External
Next
×
H
L
L
External
Next
×
H
×
×
Current
2
Notes 1. Deselect status is held until new “Begin Burst” entry.
2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (Low-
impedance). If it occurs during a write cycle, the bus will remain High impedance. No write operation will
be performed during the Ignore Clock Edge cycle.
Remarks 1. × : don’t care
2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.
/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.
10
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Partial Truth Table for Write Enables
[µPD44321182]
Operation
Read Cycle
/WE
H
/BW1
/BW2
×
L
×
H
L
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / All Bytes
L
L
H
L
L
L
Write Abort / NOP
L
H
H
Remark × : don’t care
[µPD44321362]
Operation
/WE
H
L
/BW1
/BW2
/BW3
/BW4
Read Cycle
×
L
×
H
L
×
H
H
L
×
H
H
H
L
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
Write Cycle / All Bytes
L
H
H
H
L
L
H
H
L
L
H
L
L
L
Write Abort / NOP
L
H
H
H
H
Remark × : don’t care
ZZ (Sleep) Truth Table
ZZ
≤ 0.2 V
Chip Status
Active
Active
Sleep
Open
≥ VDD − 0.2 V
11
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Conditions
MIN.
–0.5
TYP.
MAX.
+4.0
Unit
V
VDD
VDDQ
VIN
Output supply voltage
Input voltage
–0.5
VDD
V
–0.5 Note
–0.5 Note
0
VDD + 0.5
VDDQ + 0.5
70
V
Input / Output voltage
Operating ambient
temperature
VI/O
TA
V
-A50, -A60
°C
-A50Y, -A60Y
–40
+85
Storage temperature
Tstg
–55
+125
°C
Note –2.0 V (MIN.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (VDD = 3.3 ± 0.165 V)
(1/2)
Unit
Parameter
Supply voltage
Symbol
Conditions
MIN.
TYP.
3.3
MAX.
3.465
VDD
3.135
V
2.5 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
3.3 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.375
1.7
–0.3 Note
2.5
2.9
VDDQ + 0.3
+0.7
V
V
V
VIL
VDDQ
VIH
3.135
2.0
–0.3 Note
3.3
3.465
VDDQ + 0.3
+0.8
V
V
V
VIL
Note –0.8 V (MIN.) (Pulse width : 2 ns)
Recommended DC Operating Conditions (VDD = 2.5 ± 0.125 V)
(2/2)
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
2.375
2.375
1.7
TYP.
2.5
MAX.
2.625
Unit
V
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.5
2.625
V
VDDQ + 0.3
+0.7
V
VIL
–0.3 Note
V
Note –0.8 V (MIN.) (Pulse width : 2 ns)
12
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
DC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)
Parameter
Input leakage current
I/O leakage current
Operating supply current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit
µA
VIN (except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled.
Device selected, Cycle = MAX. -A50, -A50Y
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA -A60, -A60Y
Device deselected, Cycle = 0 MHz,
VIN ≤ VIL or VIN ≥ VIH, All inputs are static.
Device deselected, Cycle = 0 MHz,
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V,
ILO
–2
+2
µA
IDD
410
360
70
mA
Standby supply current
ISB
mA
ISB1
60
VI/O ≤ 0.2 V, All inputs are static.
ISB2
ISBZZ
VOH
VOL
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
130
60
Power down supply current
2.5 V LVTTL Interface
High level output voltage
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
mA
V
IOH = –2.0 mA
IOH = –1.0 mA
IOL = +2.0 mA
IOL = +1.0 mA
1.7
2.1
Low level output voltage
0.7
0.4
V
3.3 V LVTTL Interface
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
IOL = +8.0 mA
2.4
V
V
0.4
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
CIN
Test condition
VIN = 0 V
MIN.
TYP.
MAX.
6.0
Unit
pF
Input capacitance
Input / Output capacitance
Clock input capacitance
CI/O
VI/O = 0 V
8.0
pF
Cclk
Vclk = 0 V
6.0
pF
Remark These parameters are periodically sampled and not 100% tested.
13
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
AC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)
AC Test Conditions
2.5 V LVTTL Interface
Input waveform (Rise / Fall time≤ 2.4 ns)
2.4 V
1.2 V
Test points
1.2 V
1.2 V
V
SS
Output waveform
1.2 V
Test points
3.3 V LVTTL Interface
Input waveform (Rise / Fall time≤ 3.0 ns)
3.0 V
1.5 V
Test points
Test points
1.5 V
V
SS
Output waveform
1.5 V
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
Figure External load at test
ZO = 50 Ω
I/O (Output)
C
L
50 Ω
V
T
= +1.2 V / +1.5 V
Remark CL includes capacitances of the probe and jig, and stray capacitances.
14
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Read and Write Cycle
Parameter
Symbol
-A50, -A50Y
(200 MHz)
-A60, -A60Y
(167 MHz)
Unit
Notes
Standard
Alias
TCYC
TCD
MIN.
MAX.
–
MIN.
MAX.
–
Cycle time
TKHKH
TKHQV
TGLQV
TKHQX1
TKHQX2
TGLQX
TGHQZ
TKHQZ
TKHKL
TKLKH
TAVKH
5
–
6
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time
3.2
3.2
–
3.5
3.5
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
Output disable to output High-Z
Clock high to output High-Z
Clock high pulse width
Clock low pulse width
TOE
–
–
TDC1
TDC2
TOLZ
TOHZ
TCZ
1.5
1.5
0
1.5
1.5
0
1, 2
–
–
–
–
1
1
0
3.2
3.2
–
0
3.5
3.5
–
1.5
1.8
1.8
1.5
1.5
1.8
1.8
1.5
1, 2
TCH
TCL
–
–
Setup times
Address
TAS
–
–
Address advance TADVVKH
TADVS
TCES
TCSS
TDS
Clock enable
Chip enable
Data in
TEVKH
TCVKH
TDVKH
TWVKH
TKHAX
Write enable
Address
TWS
TAH
Hold times
0.5
–
0.5
–
ns
3
Address advance TKHADVX
TADVH
TCEH
TCSH
TDH
(1.0)
(–)
(1.0)
(–)
Clock enable
Chip enable
Data in
TKHEX
TKHCX
TKHDX
TKHWX
TZZE
Write enable
TWH
TZZE
TZZR
Power down entry time
–
–
10
10
–
–
12
12
ns
ns
Power down recovery time
TZZR
Notes 1. Transition is measured 200 mV from steady state.
2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than
TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min.,
VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.).
3. These values apply when VDD = 3.3 V 0.165 V with a 3.3 V LVTTL interface, or when VDD = 2.5 V
0.125 V with a 2.5 V LVTTL interface.
Values in parentheses apply when VDD = 3.3 V 0.165 V with a 2.5 V LVTTL interface.
15
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
READ / WRITE CYCLE
1
2
TKHKH
3
4
5
6
7
8
9
10
CLK
TKHKL TKLKH
TEVKH TKHEX
TCVKH TKHCX
/CKE
/CEs Note 1
ADV
TADVVKH TKHADVX
TWVKH TKHWX
TWVKH TKHWX
/WE
/BWs Note 2
Address
A1
A2
A3
A4
A5
A6
A7
TAVKH TKHAX
High-Z
High-Z
High-Z
D (A1)
D (A2)
D (A2+1)
D (A5)
Data In
TDVKH TKHDX
TKHQX1
TKHQX2
Q (A3)
TGLQV TKHQZ
High-Z
High-Z
Q (A4)
Q (A4+1)
Q (A6)
Data Out
/G
TKHQX2
TGHQZ
TKHQV
TGLQX
BURST
WRITE
D (A2+1)
BURST
READ
Q (A4+1)
WRITE
D (A1)
WRITE
D (A2)
READ
Q (A3)
READ
Q (A4)
WRITE
D (A5)
READ
Q (A6)
WRITE
Q (A7)
Command
DESELECT
Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When
/CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables
(/BW1, /BW2, /BW3 or /BW4) are LOW.
16
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
NOP, STALL AND DESELECT CYCLE
1
2
3
4
5
6
7
8
9
10
CLK
/CKE
/CEs
ADV
/WE
/BWs
Address
A1
A2
A3
A4
A5
High-Z
High-Z
High-Z
D (A1)
D (A4)
Data In
TKHQZ
High-Z
High-Z
Q (A2)
Q (A3)
Q (A5)
TKHQX2
Data Out
WRITE
D (A1)
READ
Q (A2)
READ
Q (A3)
WRITE
D (A4)
READ
Q (A5)
CONTINUE
DESELECT
Command
STALL
STALL
NOP
DESELECT
17
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
POWER DOWN (ZZ) CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
TKHKH
CLK
/CKE
TKHKL TKLKH
/CEs Note
ADV
/WE Note
/BWs
Address
/G
A1
A2
High-Z
High-Z
Data Out
ZZ
Q1 (A2)
Q (A1)
TZZE
TZZR
Power Down (ISBZZ) State
Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.2 and No.3 in this figure) prior to power
down state entry.
18
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
14.0 0.2
16.0 0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125 0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
19
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD44321182 and µPD44321362.
Types of Surface Mount Devices
µPD44321182GF : 100-pin PLASTIC LQFP (14 x 20)
µPD44321362GF : 100-pin PLASTIC LQFP (14 x 20)
20
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
Revision History
Edition/
Page
Type of
revision
Location
Description
Date
This
edition
Previous
edition
(Previous edition → This edition)
3rd edition/ Throughout Throughout
Sep. 2003
Addition
Modification
Deletion
-A75Y, -A85Y
"Note Under development" was added
Integrate -C75, -C85 to -A75, -A85
-A65, -A65Y (133MHz)
−
−
4th edition/
Nov. 2003
p.15
p.15
Modification Read and Write Cycle
Hold times
Values when VDD = 3.3 V 0.165 V, with 2.5 V
LVTTL interface have been added.
Note 3 has been added.
21
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
[MEMO]
22
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
23
Preliminary Data Sheet M16024EJ4V0DS
µPD44321182, 44321362
ZEROSB is a trademark of NEC Electronics Corporation.
•
The information in this document is current as of November, 2003. The information is
subject to change without notice. For actual design-in, refer to the latest publications of
NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of
NEC Electronics products. Not all products and/or types are available in every country.
Please check with an NEC Electronics sales representative for availability and additional
• information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
•
•
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
• customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
• redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
©2020 ICPDF网 联系我们和版权申明