UPD44647184AF5-E25-FQ1-A [RENESAS]
IC,SYNC SRAM,QDR,4MX18,CMOS,BGA,165PIN,PLASTIC;
| 型号： | UPD44647184AF5-E25-FQ1-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SYNC SRAM,QDR,4MX18,CMOS,BGA,165PIN,PLASTIC 时钟 静态存储器 内存集成电路 |
| 文件： | 总42页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
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DATA SHEET
MOS INTEGRATED CIRCUIT
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
72M-BIT QDRTM II+ SRAM
2.0 & 2.5 CLOCK CYCLES READ LATENCY
4-WORD BURST OPERATION
Description
The μPD44647094A-A and μPD44647096A-A are 8,388,608-word by 9-bit, the μPD44647184A-A and μPD44647186A-A
are 4,194,304-word by 18-bit and the μPD44647364A-A and μPD44647366A-A are 2,097,152-word by 36-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD44647xx4A-A is for 2.0 clock cycles and the μPD44647xx6A-A is for 2.5 clock cycles read latency. The
μPD44647094A-A, μPD44647096A-A, μPD44647184A-A, μPD44647186A-A, μPD44647364A-A and μPD44647366A-
A integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock
pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (15 x 17)
• HSTL interface
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Four-tick burst for reduced address frequency
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two Echo clocks (CQ and CQ#)
• Data Valid pin (QVLD) supported
• Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 2.5 ns (400 MHz) for 2.0 clock cycles read latency,
2.0 ns (500 MHz) for 2.5 clock cycles read latency
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
• On-Die Termination (ODT) for better signal quality (Selectable ON/OFF by user)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M19962EJ2V0DS00 (2nd edition)
Date Published March 2010
2009, 2010
Printed in Japan
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Ordering Information
2.0 Clock Cycles Read Latency
Part number
Cycle
Time
ns
Clock
Frequency
MHz
400
Organization Core Supply
I/O
Package
(word x bit)
Voltage
V
Interface
μPD44647094AF5-E25-FQ1-A Note
μPD44647094AF5-E30-FQ1-A
μPD44647094AF5-E33-FQ1-A
μPD44647184AF5-E25-FQ1-A Note
μPD44647184AF5-E30-FQ1-A
μPD44647184AF5-E33-FQ1-A
μPD44647364AF5-E25-FQ1-A Note
μPD44647364AF5-E30-FQ1-A
μPD44647364AF5-E33-FQ1-A
2.5
3.0
3.3
2.5
3.0
3.3
2.5
3.0
3.3
8M x 9
1.8 ± 0.1
HSTL
165-pin PLASTIC
BGA (15 x 17)
Lead-free
333
300
400
4M x 18
2M x 36
333
300
400
333
300
Note Please contact our sales.
2.5 Clock Cycles Read Latency
Part number
Cycle
Time
ns
Clock
Frequency
MHz
500
Organization Core Supply
I/O
Package
(word x bit)
Voltage
V
Interface
μPD44647096AF5-E20-FQ1-A Note
μPD44647096AF5-E22-FQ1-A
μPD44647096AF5-E25-FQ1-A
μPD44647096AF5-E30-FQ1-A
μPD44647186AF5-E20-FQ1-A Note
μPD44647186AF5-E22-FQ1-A
μPD44647186AF5-E25-FQ1-A
μPD44647186AF5-E30-FQ1-A
μPD44647366AF5-E20-FQ1-A Note
μPD44647366AF5-E22-FQ1-A
μPD44647366AF5-E25-FQ1-A
μPD44647366AF5-E30-FQ1-A
2.0
2.2
2.5
3.0
2.0
2.2
2.5
3.0
2.0
2.2
2.5
3.0
8M x 9
1.8 ± 0.1
HSTL
165-pin PLASTIC
BGA (15 x 17)
Lead-free
450
400
333
500
4M x 18
2M x 36
450
400
333
500
450
400
333
Note Please contact our sales.
Data Sheet M19962EJ2V0DS
2
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Feature Differences between QDR II and QDR II+
Features
Frequency (DLL/PLL ON)
Organization
QDR II
200 MHz to 333 MHz
x9 / x18 / x36
1.8 ± 0.1 V
QDR II+
300 MHz to 500 MHz
x9 / x18 / x36
1.8 ± 0.1 V
Note
VDD
VDDQ
1.8 ± 0.1 V or 1.5 ± 0.1 V
1.5 clock cycles
1.0 clock cycle
Single Ended (K, K#)
Yes
1.8 ± 0.1 V or 1.5 ± 0.1 V
2.0 & 2.5 clock cycles
1.0 clock cycle
Single Ended (K, K#)
No
Read Latency
1
2
Write Latency
Input Clocks (K, K#)
Output Clocks (C, C#)
Echo Clock Number (CQ, CQ#)
Package
1 Pair
1 Pair
3
165-pin PLASTIC BGA (15 x 17)
Yes
165-pin PLASTIC BGA (15 x 17)
Yes
Individual Byte Write (BWx#)
QVLD
No
Yes
4
5
ODT
No
Yes
Notes 1. QDR II+ read latency is not user selectable. Offered as two different devices. 2.5 clock cycle is consortium
standard, and 2.0 clock cycle is vendor option.
2. QDR II+ write latency is 1.0 clock cycle regardless of read latency.
3. Echo Clocks are single-ended outputs.
4. Edge aligned with Echo Clocks
5. ODT ON/OFF is user selectable.
3
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Pin Configurations
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44647094A-A], [μPD44647096A-A]
8M x 9
1
CQ#
NC
2
A
3
A
4
5
NC
NC/288M
A
6
K#
7
8
9
A
10
A
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
B
C
D
E
F
W#
R#
NC/144M
BW0#
A
NC
NC
D5
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
A
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
D3
NC
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
G
H
J
NC
DLL#
NC
VREF
NC
NC
Q7
NC
D8
K
L
NC
NC
M
N
P
R
NC
NC
VSS
VSS
NC
NC
TCK
A
A
QVLD
ODT
A
A
TDO
A
A
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D8
Q0 to Q8
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0#
K, K#
CQ, CQ#
ZQ
: Byte Write data select
: Input clock
VDDQ
VSS
: Power Supply
: Echo clock
: Ground
: Output impedance matching
: DLL/PLL disable
: Q Valid output
NC
: No connection
DLL#
QVLD
ODT
NC/xxM
: Expansion address for xxMb
: ODT Control Input
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 7A and 5B are expansion addresses: 7A for 144Mb
: 7A and 5B for 288Mb
Data Sheet M19962EJ2V0DS
4
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44647184A-A], [μPD44647186A-A]
4M x 18
1
CQ#
NC
2
3
4
5
BW1#
NC
A
6
K#
7
8
9
A
10
A
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
A
W#
R#
NC/144M
Q9
NC/288M
BW0#
A
D9
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
Q7
NC
D6
NC
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
NC
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
Q12
D13
VREF
NC
NC
NC
VREF
Q4
D3
G
H
J
NC
DLL#
NC
K
L
NC
NC
NC
Q15
NC
NC
Q1
NC
D0
M
N
P
R
NC
NC
D17
NC
VSS
VSS
NC
A
A
QVLD
ODT
A
A
TDO
TCK
A
A
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
D0 to D17
Q0 to Q17
R#
TDI
TCK
TDO
VREF
VDD
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
W#
: Write input
BW0#, BW1#
K, K#
: Byte Write data select
: Input clock
VDDQ
VSS
: Power Supply
CQ, CQ#
ZQ
: Echo clock
: Ground
: Output impedance matching
: DLL/PLL disable
: Q Valid output
NC
: No connection
DLL#
NC/xxM
: Expansion address for xxMb
QVLD
ODT
: ODT Control Input
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A and 7A are expansion addresses: 2A for 144Mb
: 2A and 7A for 288Mb
5
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44647364A-A], [μPD44647366A-A]
2M x 36
1
2
3
4
5
BW2#
BW3#
A
6
K#
7
BW1#
BW0#
A
8
9
10
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
CQ#
Q27
D27
D28
Q29
Q30
D30
DLL#
D31
Q32
Q33
D33
D34
Q35
TDO
A
W#
R#
A
NC/288M
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
NC/144M
Q17
Q7
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
A
K
A
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
VSS
VSS
D9
A
A
QVLD
ODT
A
A
D0
A
A
A
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D35
Q0 to Q35
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0# to BW3#
K, K#
: Byte Write data select
: Input clock
VDDQ
VSS
: Power Supply
CQ, CQ#
ZQ
: Echo clock
: Ground
: Output impedance matching
: DLL/PLL disable
: Q Valid output
NC
: No connection
DLL#
NC/xxM
: Expansion address for xxMb
QVLD
ODT
: ODT Control Input
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A and 10A are expansion addresses: 10A for 144Mb
10A and 2A for 288Mb
Data Sheet M19962EJ2V0DS
6
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Pin Identification
Symbol
Type
Description
A
Input
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. All transactions operate on a burst of four words (two clock periods of bus
activity). These inputs are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).
D0 to Dxx
Q0 to Qxx
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See Pin Configurations for ball site location of individual signals.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Output
Synchronous Data Outputs: Output data is synchronized to the respective K and K# rising edges.
Data is output in synchronization with K and K#, depending on the R# command. See Pin
Configurations for ball site location of individual signals.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
R#
Input
Input
Input
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K. If a READ
command (R# = LOW) is input, an input of R# on the subsequent rising edge of K is ignored.
W#
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K. If a
WRITE command (W# = LOW) is input, an input of W# on the subsequent rising edge of K is ignored.
BWx#
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals must meet setup and hold times around the rising edges
of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
K, K#
CQ, CQ#
ZQ
Input
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
Output
Input
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely and do
not stop when Q tristates. If K and K# are stopped, CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. Q, CQ, CQ# and QVLD output impedance are set to 0.2 x RQ, where RQ is a resistor
from this bump to ground. The output impedance can be minimized by directly connect ZQ to VDDQ.
This pin cannot be connected directly to GND or left unconnected. The output impedance is adjusted
every 20 μs upon power-up to account for drifts in supply voltage and temperature. After replacement
for a resistor, the new output impedance is reset by implementing power-on sequence.
DLL#
Input
DLL/PLL Disable: When DLL# is LOW, the operation can be performed at a clock frequency slower
than TKHKH (MAX.) without the DLL/PLL circuit being used. The AC/DC characteristics cannot be
guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a 10
kΩ or less resistor.
QVLD
ODT
Output
Input
Q valid Output: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ#.
ODT Control Input: When the ODT control pin is HIGH, the ODT function is turned on at Dxx and
BWx# pins. The ODT resistors are set to 0.6 x RQ, where RQ is a resistor from ZQ pin bump to
ground. When the ODT Control pin is LOW or No Connect, the ODT function is turned off. The ODT
ON/OFF is set at power-on sequence. The ODT can not change the state after power-on. To enable
ODT function, ODT pin must be HIGH and it can be connected to VDDQ through a 10 kΩ or less
resistor.
TMS
TDI
Input
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function
is not used in the circuit.
TCK
Input
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used
in the circuit.
TDO
Output
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
VREF
VDD
–
Supply
Power Supply: 1.8
V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
VDDQ
Supply
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See
Recommended DC Operating Conditions and DC Characteristics for range.
VSS
NC
Supply
–
Power Supply: Ground
No Connect: These signals are not connected internally.
7
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Block Diagram
[μPD44647094A-A], [μPD44647096A-A]
21
ADDRESS
R#
21
ADDRESS
REGISTRY
W#
& LOGIC
K
W#
MUX
MUX
BW0#
9
2
18
18
18
Q0 to Q8
36
DATA
9
221x 36
MEMORY
ARRAY
REGISTRY
& LOGIC
D0 to D8
R#
18
K
CQ,
CQ#
K
K
QVLD
K, K#
K#
[μPD44647184A-A], [μPD44647186A-A]
20
ADDRESS
R#
20
ADDRESS
REGISTRY
W#
& LOGIC
K
W#
MUX
MUX
BW0#
36
36
36
18
BW1#
Q0 to Q17
72
DATA
18
2
20x 72
MEMORY
D0 to D17
REGISTRY
& LOGIC
ARRAY
2
36
K
CQ,
CQ#
R#
K
K
QVLD
K, K#
K#
[μPD44647364A-A], [μPD44647366A-A]
19
ADDRESS
R#
19
ADDRESS
REGISTRY
W#
& LOGIC
K
W#
MUX
MUX
BW0#
72
72
72
72
36
2
BW1#
BW2#
BW3#
Q0 to Q35
19x 144
144
DATA
REGISTRY
& LOGIC
2
MEMORY
ARRAY
36
D0 to D35
CQ,
CQ#
R#
K
K
K
QVLD
K, K#
K#
Data Sheet M19962EJ2V0DS
8
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Power-On Sequence in QDR II+ SRAM
QDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ
can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up. The
following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ
can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
- Apply VDD before VDDQ.
- Apply VDDQ before VREF or at the same time as VREF.
Select ODT ON/OFF.
Provide stable clock for more than 20 μs to lock the DLL/PLL.
DLL/PLL Constraints
The DLL/PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified
as TKC var. The DLL/PLL can cover 190 MHz as the lowest frequency. If the input clock is unstable and the
DLL/PLL is enabled, then the DLL/PLL may lock onto an undesired clock frequency.
ODT initialization
The ODT ON/OFF is set at power-on sequence. When the ODT Control pin is HIGH before applying stable clock,
the ODT function is turn on. When the ODT Control pin is LOW or No Connect, the ODT function is off. The ODT
can not change the state after power-on.
Power-On Waveforms
V
DD/VDDQ
V
DD/VDDQ Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
DLL#
ODT
Fix HIGH or LOW (or No Connect)
Clock
20 μs or more
Stable Clock
Unstable Clock
Normal Operation
Start
9
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
On-Die Termination (ODT)
On-Die Termination (ODT) is enabled by setting ODT control pin to HIGH at power-on sequence. The ODT resistors
(RTT) are set to 0.6 x RQ, where RQ is a resistor from ZQ pin bump to ground. With ODT on, all the Ds and BW#s are
terminated to VDDQ and VSS with a resistance RTT x 2. The command, address, and clock signals are not terminated.
Figure below shows the equivalent circuit of a Dxx and BWx# receiver with ODT. ODT at the Ds and BW#s are always
on.
When the ODT control pin is LOW or No Connect at power-on sequence, the ODT function is always off.
When the ODT be changed the state after power-on, the AC/DC characteristics cannot be guaranteed.
On-Die Termination DC Parameters
Description
On-Die termination
External matching resistor
Symbol
RTT
MIN.
105
175
TYP.
150
MAX.
210
Units
Ω
RQ
250
350
Ω
Remark The allowable range of RQ to guarantee impedance matching a tolerance of ± 20 % is between 175 Ω
and 350 Ω.
On- Die Termination-Equivalent Circuit
VDDQ
SW
R
TT x 2
Receiver
Dxx, BWx#
R
TT x 2
SW
VSS
QDR Consortium specification for ODT is defined when 6R is HIGH and vendor specification when 6R is LOW or
Floating. NEC specification is "Disabled" with 6R LOW or Floating as follows.
ODT-option clarification
6R input
ODT function
Consortium specification
Termination value
Consortium specification
NEC specification
Active
NEC specification
HIGH
Active
RTT = 0.6 x RQ
RTT = 0.6 x RQ
LOW
Vendor specification
Vendor specification
Disabled
Vendor specification
Vendor specification
–
–
Floating
Disabled
Note
In case of nominal value (RQ = 250 Ω), RTT = 150 Ω.
Data Sheet M19962EJ2V0DS
10
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Truth Table
2.0 Clock Cycles Read Latency
[μPD44647094A-A], [μPD44647184A-A], [μPD44647364A-A]
Operation
CLK
R#
H
W#
L
D or Q
WRITE cycle
L → H
Data in
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Input data
Input clock
DA(A+0)
DA(A+1)
DA(A+2)
DA(A+3)
K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑
L → H
L
X
Data out
Load address, read data on two
consecutive K and K# rising edge
NOP (No operation)
Output data
Output clock
QA(A+0)
QA(A+1)
QA(A+2)
QA(A+3)
K(t+2) ↑ K#(t+2) ↑ K(t+3) ↑ K#(t+3) ↑
L → H
H
X
H
X
D = X, Q = High-Z
Previous state
Clock stop
Stopped
2.5 Clock Cycles Read Latency
[μPD44647096A-A], [μPD44647186A-A], [μPD44647366A-A]
Operation
CLK
R#
H
W#
L
D or Q
WRITE cycle
L → H
Data in
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Input data
Input clock
DA(A+0)
DA(A+1)
DA(A+2)
DA(A+3)
K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑
L → H
L
X
Data out
Load address, read data on two
consecutive K and K# rising edge
NOP (No operation)
Output data
QA(A+0)
QA(A+1)
QA(A+2)
QA(A+3)
Output clock K#(t+2) ↑ K(t+3) ↑ K#(t+3) ↑ K(t+4) ↑
L → H
H
X
H
X
D = X, Q = High-Z
Previous state
Clock stop
Stopped
Remarks
Remarks listed below are for both products with 2.0 and 2.5 Clock Cycles Read Latency.
1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# when clock is stopped. This is not essential but permits most rapid restart
by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
11
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Byte Write Operation
[μPD44647094A-A], [μPD44647096A-A]
Operation
Write D0 to D8
K
L → H
–
K#
–
BW0#
0
0
1
1
L → H
–
Write nothing
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD44647184A-A], [μPD44647186A-A]
Operation
Write D0 to D17
K
L → H
–
K#
–
BW0#
BW1#
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
–
Write D0 to D8
Write D9 to D17
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44647364A-A], [μPD44647366A-A]
Operation
Write D0 to D35
K
K#
–
BW0#
BW1#
BW2#
BW3#
L → H
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
–
L → H
–
L → H
–
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Data Sheet M19962EJ2V0DS
12
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Bus Cycle State Diagram
LOAD NEW
READ ADDRESS;
R_Count = 0;
R_Init = 1
LOAD NEW
WRITE ADDRESS;
W_Count = 0
Always
W# = LOW & W_Count = 4
R# = LOW & R_Count = 4
Always
WRITE DOUBLE;
READ DOUBLE;
W_Count = W_Count+2
R_Count = R_Count+2
R# = HIGH
& R_Count = 4
W# = LOW
R_Init = 0
W_Count = 2
Always
R_Count = 2
Always
R# = LOW
W# = HIGH
& W_Count = 4
INCREMENT READ
ADDRESS BY TWO
R_Init = 0
INCREMENT WRITE
ADDRESS BY TWO
R# = HIGH
W# = HIGH
READ PORT NOP
R_Init = 0
WRITE PORT NOP
Power UP
Supply voltage
provided
Supply voltage
provided
Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously.
Read and write cannot be simultaneously initiated. Read takes precedence.
3. State machine control timing is controlled by K.
13
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
VDDQ
VIN
Conditions
Rating
–0.5 to +2.5
Unit
V
Supply voltage
Output supply voltage
Input voltage
–0.5 to VDD
V
–0.5 to VDD + 0.5 (2.5 V MAX.)
–0.5 to VDDQ + 0.5 (2.5 V MAX.)
0 to 70
V
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
V
TA
°C
°C
Tstg
–55 to +125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
1.7
TYP.
1.8
MAX.
1.9
Unit
V
Note
Output supply voltage
Input HIGH voltage
Input LOW voltage
Clock input voltage
Reference voltage
VDDQ
VIH (DC)
VIL (DC)
VIN
1.4
VDD
V
1
VREF + 0.1
–0.3
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
0.95
V
1, 2
1, 2
1, 2
V
–0.3
V
VREF
0.68
V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C)
Parameter
Input HIGH voltage
Input LOW voltage
Symbol
VIH (AC)
VIL (AC)
Conditions
MIN.
MAX.
Unit
Note
VREF + 0.2
V
V
1
1
VREF – 0.2
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
Data Sheet M19962EJ2V0DS
14
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x18
+2
Unit Note
x9
x36
Input leakage current
ILI
–2
–2
μA
μA
4, 5
4
I/O leakage current
ILO
IDD
+2
Operating supply current
(Read cycle / Write cycle)
VIN ≤ VIL or VIN ≥ VIH
-E20 Note1
-E22 Note1
-E25
780
730
690
580
520
460
440
410
380
370
850 1000
mA
II/O = 0 mA
795
740
650
590
480
455
430
400
390
VDDQ
925
850
720
650
530
500
470
440
430
Cycle = MAX.
-E30
-E33
Standby supply current
(NOP)
ISB1
VIN ≤ VIL or VIN ≥ VIH
II/O = 0 mA
-E20 Note1
-E22 Note1
-E25
mA
Cycle = MAX.
Inputs static
-E30
-E33
Output HIGH voltage
Output LOW voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note2
VDDQ – 0.2
VDDQ/2–0.12
VSS
V
V
6, 7
6, 7
6, 7
6, 7
VDDQ/2+0.12
0.2
VOL(Low) IOL ≤ 0.1 mA
VOL Note3
VDDQ/2–0.12
VDDQ/2+0.12
Notes 1. -E20 and -E22 are valid for 2.5 Clock Cycles Read Latency products.
2. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
4. Measured with ODT off.
5. ODT pin is internally tied to VSS, so input leakage current value is ±5 μA.
6. AC load current is higher than the shown DC values.
7. HSTL outputs meet JEDEC HSTL Class I standards.
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
MIN.
MAX.
Unit
pF
Input capacitance (Address, Control)
Input / Output capacitance
(D, Q, CQ, CQ#, QVLD)
4
5
CI/O
VI/O = 0 V
pF
Clock Input capacitance
Cclk
Vclk = 0 V
4
pF
Remark These parameters are periodically sampled and not 100% tested.
15
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Thermal Characteristics
Parameter
Thermal resistance
Symbol
Substrate
4-layer
Airflow
TYP.
19.5
12.0
18.1
11.3
0.01
0.05
0.01
0.04
2.14
Unit
θ ja
0 m/s
1 m/s
0 m/s
1 m/s
0 m/s
1 m/s
0 m/s
1 m/s
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
from junction to ambient air
8-layer
4-layer
8-layer
Thermal characterization parameter
from junction to the top center
of the package surface
Ψ jt
Thermal resistance
from junction to case
θ jc
Data Sheet M19962EJ2V0DS
16
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
AC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 to VDD)
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
0.75 V
Test Points
0.25 V
Output waveform
V
DDQ / 2
Test Points
VDDQ / 2
Output load condition
Figure 1. External load at test
V
DDQ / 2
0.75 V
50 Ω
V
REF
ZO = 50 Ω
SRAM
250 Ω
ZQ
17
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Read and Write Cycle
Parameter
Symbol
-E20 Note1
-E22 Note1
-E25
-E30
-E33
Unit Note
(333 MHz)
(500 MHz)
(450 MHz)
(400 MHz)
(300 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time (K, K#)
Clock phase jitter (K, K#)
Clock HIGH time (K, K#)
Clock LOW time (K, K#)
Clock HIGH to Clock# HIGH
(K → K#)
TKHKH
TKC var
TKHKL
TKLKH
TKHK#H
ns
ns
2
3
2.0
5.25
0.15
2.2
5.25
0.15
2.5
5.25
0.20
3.0
5.25
0.20
3.3
5.25
0.20
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
TKHKH
TKHKH
ns
0.85
0.95
1.06
1.28
1.40
Clock# HIGH to Clock HIGH
(K# → K)
TK#HKH
ns
0.85
0.95
1.06
1.28
1.40
DLL/PLL lock time (K)
K static to DLL/PLL reset
TKC lock
μs
4
5
20
30
20
30
20
30
20
30
20
30
TKC reset
ns
Output Times
CQ HIGH to CQ# HIGH
(CQ → CQ#)
TCQHCQ#H
TCQ#HCQH
ns
ns
6
6
0.6
0.6
0.7
0.7
0.81
0.81
1.03
1.03
1.15
1.15
CQ# HIGH to CQ HIGH
(CQ# → CQ)
K, K# HIGH to output valid
K, K# HIGH to output hold
K, K# HIGH to echo clock valid
K, K# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
K HIGH to output High-Z
K HIGH to output Low-Z
CQ, CQ# HIGH to QVLD valid
TKHQV
TKHQX
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.45
0.45
0.15
0.45
0.45
0.45
0.15
0.45
0.45
0.45
0.20
0.45
0.45
0.45
0.20
0.45
0.45
0.45
0.20
0.45
– 0.45
– 0.45
– 0.15
– 0.45
– 0.45
– 0.45
– 0.15
– 0.45
– 0.45
– 0.45
– 0.20
– 0.45
– 0.45
– 0.45
– 0.20
– 0.45
– 0.45
– 0.45
– 0.20
– 0.45
TKHCQV
TKHCQX
TCQHQV
TCQHQX
TKHQZ
7
7
TKHQX1
TCQHQVLD
– 0.15 0.15 – 0.15 0.15 – 0.20 0.20 – 0.20 0.20 – 0.20 0.20
Setup Times
Address valid to K rising edge
Control inputs (R#, W#) valid to
K rising edge
TAVKH
TIVKH
ns
ns
8
8
0.33
0.33
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Data inputs and write data select
inputs (BWx#) valid to
TDVKH
ns
8
0.25
0.28
0.28
0.28
0.28
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs
(R#, W#) hold
TKHAX
TKHIX
ns
ns
8
8
0.33
0.33
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
K, K# rising edge to data inputs
and write data select inputs
(BWx#) hold
TKHDX
ns
8
0.25
0.28
0.28
0.28
0.28
Notes 1. -E20 and -E22 are valid for 2.5 Clock Cycles Read Latency products.
2. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle regardless of RL = 2.0 and 2.5 clock cycles products in this operation. The AC/DC characteristics
cannot be guaranteed, however.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
Data Sheet M19962EJ2V0DS
18
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
4. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.
DLL/PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.
5. K input is monitored for this operation. See below for the timing.
K
TKC reset
or
K
TKC reset
6. Guaranteed by design.
7. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
8. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. VDDQ is 1.5 V DC.
19
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Read and Write Timing
2.0 Clock Cycles Read Latency
[μPD44647094A-A], [μPD44647184A-A], [μPD44647364A-A]
WRITE
READ
NOP
NOP
WRITE
READ
NOP
1
2
3
4
5
6
7
8
K
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
K#
R#
TIVKH TKHIX
TKHIX
TIVKH
W#
A0
A2
A1
A3
Address
Data in
TDVKH TKHDX
TDVKH TKHDX
TAVKH
TKHAX
D10
D11
D12
D13
D30
D31
D32
D33
ODT state
D, BW#
ODT-ON
TCQHQVLD
TCQHQVLD
QVLD
TKHQV
TKHQX
TKHQV
TKHQX
Read Latency = 2.0 clock cycles
TKHQX1
TKHQZ
Q23
Data out
Q20
Q21
Q22
Q00
Q01
Q02
Q03
TCQHQX
TCQHQV
TCQHQX
TCQHQV
TKHCQV
TKHCQX
CQ
TCQHCQ#H
TCQ#HCQH
TKHCQV
TKHCQX
CQ#
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 4.0 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].
3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.
Write data is forwarded immediately as read results. This remark applies to whole diagram.
4. When the ODT control pin is LOW or No Connect, the ODT function is always off.
Data Sheet M19962EJ2V0DS
20
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
2.5 Clock Cycles Read Latency
[μPD44647096A-A], [μPD44647186A-A], [μPD44647366A-A]
WRITE
NOP
READ
NOP
WRITE
READ
NOP
1
2
3
4
5
6
7
8
K
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
K#
R#
TIVKH TKHIX
TKHIX
TIVKH
W#
A0
A2
A1
A3
Address
Data in
TDVKH TKHDX
TDVKH
TKHDX
TAVKH
TKHAX
D10
D11
D12
D13
D30
D31
D32
D33
ODT state
D, BW#
ODT-ON
TCQHQVLD
TCQHQVLD
QVLD
TKHQV
TKHQX
TKHQV
TKHQX
Read Latency = 2.5 clock cycles
TKHQX1
TKHQZ
Data out
Q20
Q21
Q22
Q23
Q00
Q01
Q02
Q03
TCQHQX
TCQHQV
TCQHQX
TCQHQV
TKHCQV
TKHCQX
CQ
TCQHCQ#H
TCQ#HCQH
TKHCQV
TKHCQX
CQ#
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 4.5 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].
3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.
Write data is forwarded immediately as read results. This remark applies to the whole diagram.
4. When the ODT control pin is LOW or No Connect, the ODT function is always off.
21
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Application Example
R =
R =
ZQ
ZQ
250 Ω
250 Ω
CQ#
CQ#
CQ
Q
QVLD
CQ
Q
SRAM#1
SRAM#4
. . .
D
A
D
QVLD
R#
W# BWx# K/K#
A
R# W# BWx# K/K#
V
t
SRAM
Controller
R
Data In
Data Out
Address
R#
W#
BW#
QVLD
V
t
R
SRAM#1 CQ/CQ#
V
t
R
R
SRAM#4 CQ/CQ#
V
t
Source CLK/CLK#
Return CLK/CLK#
V
t
R
R = 50 Ω V = Vref
t
Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ#, QVLD and Q with termination.
Ds and BW#s have ODT.
Data Sheet M19962EJ2V0DS
22
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
TCK
Pin assignments
2R
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state machine.
TMS
TDI
10R
11R
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between TDI and
TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
ILI
Conditions
MIN.
−5.0
−5.0
MAX.
+5.0
+5.0
Unit
μA
JTAG Input leakage current
JTAG I/O leakage current
0 V ≤ VIN ≤ VDD
ILO
0 V ≤ VIN ≤ VDDQ,
μA
Outputs disabled
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
VIH
VIL
1.3
−0.3
1.6
VDD+0.3
+0.5
V
V
V
V
V
V
VOH1
VOH2
VOL1
VOL2
| IOHC | = 100 μA
| IOHT | = 2 mA
IOLC = 100 μA
IOLT = 2 mA
1.4
JTAG output LOW voltage
0.2
0.4
23
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
0 V
0.9 V
Test Points
Output waveform
0.9 V
Test Points
0.9 V
Output load
Figure 2. External load at test
V
TT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
Data Sheet M19962EJ2V0DS
24
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Symbol
Conditions
MIN.
50
MAX.
20
Unit
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
tTHTH
fTF
ns
MHz
ns
tTHTL
tTLTH
20
20
ns
Output time
TCK LOW to TDO unknown
TCK LOW to TDO valid
tTLOX
tTLOV
0
ns
ns
10
Setup time
TMS setup time
TDI valid to TCK HIGH
Capture setup time
tMVTH
tDVTH
tCS
5
5
5
ns
ns
ns
Hold time
TMS hold time
tTHMX
tTHDX
tCH
5
5
5
ns
ns
ns
TCK HIGH to TDI invalid
Capture hold time
JTAG Timing Diagram
t
THTH
TCK
t
MVTH
t
THTL
t
TLTH
TMS
TDI
t
THMX
t
DVTH
t
THDX
t
TLOV
t
TLOX
TDO
25
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
bit
Instruction register
Bypass register
3
1
bit
ID register
32
109
bit
Boundary register
bit
ID Register Definition
2.0 Clock Cycles Read Latency
Part number
Organization ID [31:28] vendor revision no.
ID [27:12] part no.
0000 0000 1001 0101
0000 0000 1001 0110
0000 0000 1001 0111
ID [11:1] vendor ID no. ID [0] fix bit
μPD44647094A-A
μPD44647184A-A
μPD44647364A-A
8M x 9
4M x 18
2M x 36
XXXX
XXXX
XXXX
00000010000
00000010000
00000010000
1
1
1
2.5 Clock Cycles Read Latency
Part number
Organization ID [31:28] vendor revision no.
ID [27:12] part no.
0000 0000 1010 0001
0000 0000 1010 0010
0000 0000 1010 0011
ID [11:1] vendor ID no. ID [0] fix bit
μPD44647096A-A
μPD44647186A-A
μPD44647366A-A
8M x 9
4M x 18
2M x 36
XXXX
XXXX
XXXX
00000010000
00000010000
00000010000
1
1
1
Data Sheet M19962EJ2V0DS
26
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
SCAN Exit Order
Bit
Signal name
Bump
ID
Bit
Signal name
x9 x18 x36
Bump
ID
Bit
Signal name
Bump
ID
no.
x9
x18 x36
no.
no.
x9
x18
x36
1
2
ODT
QVLD
A
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
NC
NC
NC
NC
Q4
D4
NC D15 10D
NC Q15 9E
73
74
NC
Q5
D5
NC
NC
NC Q28
Q11 Q20
D11 D20
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
3
6N
7P
Q7
D7
Q7 10C
D7 11D
75
4
A
76
NC
D29
5
A
7N
7R
8R
8P
NC D16 9C
NC Q16 9D
77
NC Q29
6
A
78
NC Q12 Q21
7
A
Q8
D8
Q8 11B
D8 11C
79
NC
NC
NC
Q6
D6
D12 D21
NC D30
8
A
80
9
A
9R
11P
10P
NC
NC
NC D17
9B
81
NC Q30
Q13 Q22
D13 D22
DLL#
10
11
12
13
Q0
D0
NC Q17 10B
82
CQ
A
11A
83
NC NC
NC NC
D9 10N
Q9 9P
A
NC 10A
84
A
9A
8B
7C
6C
8A
85
NC
NC
NC
D31
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
NC
Q1
D1
Q1 10M
D1 11N
A
86
NC Q31
2J
A
87
NC Q14 Q23
3K
3J
NC NC D10 9M
NC NC Q10 9N
NC
R#
88
NC
NC
NC
Q7
D7
NC
NC
D14 D23
NC D32
89
2K
1K
2L
3L
1M
1L
3N
3M
1N
Q1
Q2
Q2
D2 11M
9L
NC NC Q11 10L
11L
NC
NC
NC BW1# 7A
90
NC Q32
Q15 Q24
D15 D24
D1
D2
BW0#
K
7B
6B
6A
91
NC NC D11
92
K#
93
NC
D33
NC
NC
Q3
D3
Q3 11K
D3 10K
NC BW3# 5B
94
NC Q33
NC BW1# BW2# 5A
95
NC Q16 Q25
NC NC D12
9J
W#
A
4A
5C
4B
3A
2A
1A
96
NC
NC
NC
Q8
D8
NC
NC
D16 D25
NC D34
NC NC Q12 9K
97
Q2
D2
Q4
D4
ZQ
Q4
D4
10J
11J
11H
A
98
NC Q34 2M
A
99
Q17 Q26
D17 D26
3P
2N
A
NC
CQ#
NC
100
101
102
103
104
105
106
107
108
109
NC NC D13 10G
NC NC Q13 9G
NC
D35
2P
NC
NC
NC
NC
Q9 Q18 2B
D9 D18 3B
NC Q35
1P
NC
NC
Q5
D5
Q5 11F
D5 11G
A
A
A
A
A
A
–
3R
NC D27 1C
NC Q27 1B
4R
NC NC D14
9F
4P
NC NC Q14 10F
NC Q10 Q19 3D
NC D10 D19 3C
5P
Q3
D3
Q6
D6
Q6 11E
D6 10E
5N
NC
NC D28 1D
5R
Internal
27
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
JTAG Instructions
Instructions
Description
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output drive is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
BYPASS
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is
placed in the test-logic-reset state.
When the BYPASS instruction is loaded in the instruction register, the bypass register is placed
between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This
allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-
DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to sample metastable input will not harm the device, repeatable results
cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving
the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
2
0
1
1
RESERVED
SAMPLE / PRELOAD
RESERVED
RESERVED
BYPASS
1
0
0
1
0
1
2
2
1
1
0
1
1
1
Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
Data Sheet M19962EJ2V0DS
28
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Output Pin States of CQ, CQ#, QVLD and Q
Instructions
Control-Register Status
Output Pin Status
CQ, CQ#, QVLD
Q
EXTEST
0
1
0
1
0
1
0
1
0
1
Update
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
High-Z
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 109).
Boundary Scan
Register
CAPTURE
Register
There are three statuses:
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM
Output
Update
Register
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
Update
QDR
Pad
SRAM
SRAM
Output
Driver
High-Z
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
High-Z
JTAG ctrl
In case checking the QVLD output status in EXTEST mode,
please make sure stay DLL# pin HIGH.
29
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Boundary Scan Register Status of Output Pins CQ, CQ#, QVLD and Q
Instructions
SRAM Status
Boundary Scan Register Status
Note
CQ, CQ#, QVLD
Q
Pad
Pad
–
EXTEST
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
Pad
Pad
–
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
No definition
–
–
Pad
Pad
Internal
Internal
–
Pad
Pad
Internal
Pad
–
No definition
–
–
Boundary Scan
Register
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
CAPTURE
Register
There are two statuses:
Internal
SRAM
Output
Update
Register
Pad
: Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
Pad
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
Data Sheet M19962EJ2V0DS
30
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix
them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also
when the TAP controller is not used.
31
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
Data Sheet M19962EJ2V0DS
32
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
33
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Package Drawing
165-PIN PLASTIC BGA(15x17)
w
S
B
ZD
B
E
ZE
11
10
9
8
7
A
6
5
D
4
3
2
1
R P N M L K J H G F E D C B A
INDEX MARK
w
S A
A
(UNIT:mm)
ITEM DIMENSIONS
A2
y1
S
D
E
15.00 0.10
17.00 0.10
0.30
S
w
A
1.35 0.11
0.37 0.05
0.98
A1
A2
e
y
e
x
A1
A B
S
1.00
M
b
S
+0.10
b
0.50
0.05
x
0.10
y
0.15
y1
ZD
ZE
0.25
2.50
1.50
P165F5-100-FQ1-1
NEC Elect ronics Corporation 2009
Data Sheet M19962EJ2V0DS
34
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD44647094AF5-FQ1-A
μPD44647184AF5-FQ1-A
μPD44647364AF5-FQ1-A
μPD44647096AF5-FQ1-A
μPD44647186AF5-FQ1-A
μPD44647366AF5-FQ1-A
: 165-pin PLASTIC BGA (15 x 17), Lead free
: 165-pin PLASTIC BGA (15 x 17), Lead free
: 165-pin PLASTIC BGA (15 x 17), Lead free
: 165-pin PLASTIC BGA (15 x 17), Lead free
: 165-pin PLASTIC BGA (15 x 17), Lead free
: 165-pin PLASTIC BGA (15 x 17), Lead free
Related Document
Document Name
Document Number
μPD44647094A, 44647184A, 44647364A, 44647096A, 44647186A, 44647366A
Data Sheet (Leaded products)
M19063
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the
ground and so forth.
35
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Revision History
Edition/
Date
Page
Type of
revision
Location
Description
This
Previous
edition
(Previous edition → This edition)
edition
2nd edition/ Throughout Throughout Modification
Mar. 2010
Preliminary Data Sheet →Data Sheet
Data Sheet M19962EJ2V0DS
36
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
[MEMO]
37
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
[MEMO]
Data Sheet M19962EJ2V0DS
38
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
39
Data Sheet M19962EJ2V0DS
μPD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor,
Renesas, IDT, NEC Electronics, and Samsung.
•
The information in this document is current as of March, 2010. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets,
etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or
types are available in every country. Please check with an NEC Electronics sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
•
•
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality and safety of NEC Electronics products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. In addition, NEC
Electronics products are not taken measures to prevent radioactive rays in the product design. When customers
use NEC Electronics products with their products, customers shall, on their own responsibility, incorporate
sufficient safety measures such as redundancy, fire-containment and anti-failure features to their products in
order to avoid risks of the damages to property (including public or social property) or injury (including death) to
persons, as the result of defects of NEC Electronics products.
•
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on
a
customer-designated "quality assurance program" for a specific application. The recommended applications
of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the
quality grade of each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E0904E
相关型号：
UPD44647184AF5-E30-FQ1-A
IC,SYNC SRAM,QDR,4MX18,CMOS,BGA,165PIN,PLASTICWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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RENESAS
UPD44647184AF5-E33-FQ1-A
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UPD44647184F5-E27-FQ1
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UPD44647184F5-E30-FQ1
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UPD44647184F5-E30-FQ1-A
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NEC
UPD44647184F5-E33-FQ1
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UPD44647184F5-E33-FQ1-A
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UPD44647186F5-E25-FQ1
4MX18 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UPD44647186F5-E25-FQ1-A
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UPD44647186F5-E27-FQ1
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UPD44647186F5-E27-FQ1-A
4MX18 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UPD44647186F5-E30-FQ1
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NEC
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