UPD4664312-B65X [RENESAS]
STANDARD SRAM;
| 型号： | UPD4664312-B65X |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | STANDARD SRAM 静态存储器 内存集成电路 |
| 文件： | 总38页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The µPD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile
Specified RAM featuring Low Power Static RAM compatible function and pin configuration.
The µPD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
• 4,194,304 words by 16 bits organization
• Fast access time: 65, 75 ns (MAX.)
• Fast page access time: 18, 25 ns (MAX.)
• Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
• Low voltage operation: 2.7 to 3.1 V (-B65X)
2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O)
• Operating ambient temperature: TA = –25 to +85 °C
• Output Enable input for easy application
• Chip Enable input: /CS pin
• Standby Mode input: MODE pin
• Standby Mode1: Normal standby (Memod valid)
• Standby Mode2: Density of memory s variable
µPD4664312
Access
time
O
Operating
ambient
Supply current
At operating
At standby µA (MAX.)
ns (MAX
temperature mA (MAX.)
°C
Density of data hold
I/O
–
64M bits 16M bits 8M bits 4M bits 0M bit
-B65X Note
-BE75X Note
65
75
to 3.1
–25 to +85
45
40
100
60
50
45
10
2.7 to 3.1 1.65 to 2.1
Note Under development
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15867EJ6V0DS00 (6th edition)
The mark shows major revised points.
Date Published November 2005 NS CP (K)
Printed in Japan
2001, 2005
µPD4664312-X
Ordering Information
µPD4664312-X is mainly shipping by wafer.
Please consult with our sales offices for package samples and ordering information.
2
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Pin Configurations
The following are pin configurations of package sample.
/xxx indicates active low signal.
93-pin TAPE FBGA (12 x 9)
[ -B65X ]
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
N P
B C D E F G H J K L M
P N
M L D C B A
A
Top View
N
A
B
C
D
E
F
G
K
L
M
P
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
A17
A4
C
NC
NC
NC
NC
NC
NC
A15
A12
A19
MOD
A21
A13
NC
I/O15
I/O13
I/O4
I/O3
I/O9
/OE
GND
I/O7
NC
NC
A11
A8
I/O14
I/O5
NC
I/O6
NC
I/O12
NC
NC
/WE
NC
/LB
A5
V
CC
NC
NC
NC
I/O10
I/O0
/CS
I/O11
I/O2
I/O8
NC
I/O1
GND
A0
NC
NC
A2
A1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0 to A21
: Address inputs
/LB, /UB
VCC
: Byte data select
: Power supply
: Ground
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
GND
NC Note
MODE
/WE
/OE
: Standby mode
: Write enable
: Output enable
: No Connection
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
3
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
93-pin TAPE FBGA (12 x 9)
[ -BE75X ]
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
N P
B C D E F G H J K L M
P N
M L K J H G F E D C B A
A
Top View
N
A
B
C
D
E
F
G
H
J
M
P
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
A14
A10
NC
NC
A16
N
NC
NC
NC
NC
NC
NC
A15
A12
A19
MODE
NC
A21
A13
A9
O4
I/O3
I/O9
/OE
/O7
NC
NC
A11
A8
I/O14
I/O5
I/O12
NC
NC
/WE
NC
/LB
A7
A20
NC
A1
V
CC
V
CC
Q
NC
NC
NC
I/O10
I/O0
/CS
I/O11
I/O2
I/O8
/UB
A6
O1
GND
A0
NC
NC
A3
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0 to A21
: Addres
/LB, /UB
VCC
: Byte data select
: Power supply
I/O0 to I/O15 : Dauts
/CS
:
VCCQ
GND
NC Note
: Input / Output power supply
: Ground
MODE
/WE
/OE
: Stanmode
: Write enable
: Output enable
: No Connection
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
4
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Block Diagram
Standby mode control
V
CC
Refresh
control
VCCQ
GND
Memory cell array
67,108,864 bits
Refresh
counter
Row
decoder
A0
Address
buffer
A21
Sense
Sw
I/O0 to I/O7
Output data
controller
Input data
controller
r
I/O8 to I/O15
dress buffer
/CS
MODE
/LB
/UB
/WE
/OE
Remark VCCQ is the input / output power supply for -BE75X.
5
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Truth Table
/CS MODE /OE
/WE
/LB
/UB
Mode
I/O
Supply
I/O0 to I/O7
High-Z
High-Z
High-Z
High-Z
DOUT
I/O8 to I/O15
High-Z
High-Z
High-Z
High-Z
DOUT
current
H
×
×
L
H
H
L
×
×
×
H
L
×
×
×
H
×
×
H
×
Not selected (Standby Mode 1)
Not selected (Standby Mode 1)
Not selected (Standby Mode 2) Note
Output disable
ISB1
×
ISB2
H
H
H
×
×
ICCA
L
L
Word read
L
H
L
Lower byte read
DOUT
High-Z
DOUT
H
L
Upper byte read
High-Z
DIN
H
L
L
Word write
DIN
L
H
L
Lower byte write
DIN
High-Z
DIN
H
Upper byte write
High-Z
Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Stade Status Transition).
Remark ×: VIH or VIL, H: VIH, L: VIL
6
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
CONTENTS
1. Initialization .................................................................................................................................................................... 8
2. Partial Refresh ............................................................................................................................................................... 9
2.1 Standby Mode........................................................................................................................................................... 9
2.2 Density Switching...................................................................................................................................................... 9
2.3 Standby Mode Status Transition ............................................................................................................................... 9
2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................. 10
3. Page Read Operation................................................................................................................................................... 11
3.1 Features of Page Read Operation .......................................................................................................................... 11
3.2 Page Length............................................................................................................................................................ 11
3.3 Page-Corresponding Addresses ............................................................................................................................. 11
3.4 Page Start Address................................................................................................................................................. 11
3.5 Page Direction....................................................................................................................................................... 11
3.6 Interrupt during Page Read Operation ...................................................................................................... 11
3.7 When page read is not used ............................................................................................................ 11
4. Mode Register Settings......................................................................................................................... 12
4.1 Mode Register Setting Method......................................................................................................... 12
4.2 Cautions for Setting Mode Register ................................................................................................. 13
5. Electrical Specifications......................................................................................................................... 14
6. Timing Charts........................................................................................................................................ 19
7. Package Drawing .................................................................................................................................. 29
8. Recommended Soldering Conditions.................................................................................................... 30
9. Revision History .................................................................................................................................... 31
7
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
1. Initialization
Initialize the µPD4664312-X at power application using the following sequence to stabilize internal circuits.
(1) Following power application, make MODE high level after fixing MODE to low level for the period of tVHMH. Make
/CS high level before making MODE high level.
(2) /CS and MODE are fixed to high level for the period of tMHCL.
Normal operation is possible after the completion of initialization.
Figure1-1. Initialization Timing Chart
Normal Operation
Initialization
/CS (Input)
t
CHMH
tMHCL
t
VHMH
MODE (Input)
VCC
V
CC (MIN.)
Cautions 1. Make MODE low level when startinupply.
2. tVHMH is specified from when tply voltage reaches the prescribed minimum value (VCC
(MIN.)).
Initialization Timing
Parameter
Symbol
tVHMH
MIN.
50
MAX.
Unit Note
Power application to MOD
/CS high level to MODE high l
Following power application
µs
ns
µs
tCHMH
0
tMHCL
200
MODE high level hold to /CS low level
8
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
2. Partial Refresh
2.1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 64M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2.2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the mode
register, these settings are retained until they are set again, while applying the power supply. However, the mode register
setting will become undefined if the power is turned off, so set the mode register again after power application. (For how
to perform mode register settings, refer to section 4. Mode Register Settings.)
2.3 Standby Mode Status Transition
In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are higtandby Mode 2, MODE is
low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to petion the same way as after
applying power, in order to return to normal operation from Standby Mode 2nsity has been set to 16M bits,
8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform o return to normal operation from
Standby Mode 2.
For the timing charts, refer to Figure 6-14. Standby Mode 2 6M bits / 8M bits / 4M bits) Entry / Exit
Timing Chart, Figure 6-15. Standby Mode 2 (data not helTiming Chart.
9
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 2-1. Standby Mode State Machine
Power On
Initialization
Initial State
/CS = VIL
MODE = VIH
Active
MODE = VIL
MODE = VIH
/CS = VIH or
,
MODE = VIL
/LB, /UB = VIH
/CS = VIL
,
/CS = VIL
MODE = VIH
,
MODE = VIH
ode 2
/ 8M bits
4M bits)
MODE = VIL
Standby
Mode 1
MODE = VIL
Standby Mode 2
(Data not held)
2.4 Addresses for Which Partial Refrted
Data hold density
16M bits
respondence address
000000H to 0FFFFFH
8M bits
4M bits
000000H to 07FFFFH
000000H to 03FFFFH
10
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
3. Page Read Operation
3.1 Features of Page Read Operation
Features
Page length
8 Words Mode
8 words
Page read-corresponding addresses
Page read start address
Page direction
A2, A1, A0
Don’t care
Don’t care
Enabled Note
Interrupt during page read operation
Note An interrupt is output when /CS = H or in case A3 or a higher address changes.
3.2 Page Length
8 words is supported as the page lengths.
3.3 Page-Corresponding Addresses
The page read-enabled addresses are A2, A1, and A0. Fix addresses , A1, and A0 during page read
operation.
3.4 Page Start Address
Since random page read is supported, any address (A2, used as the page read start address.
3.5 Page Direction
Since random page read is possible, there is on the page direction.
3.6 Interrupt during Page Read Op
When generating an interrupt dueither make /CS high level or change A3 and higher addresses.
3.7 When page read is n
Since random page read ed, even when not using page read, random access is possible as usual.
11
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
4. Mode Register Settings
The partial refresh density can be set using the mode register. Since the initial value of the mode register at power
application is undefined, be sure to set the mode register after initialization at power application. When setting the density
of partial refresh, data before entering the partial refresh mode is not guaranteed. (This is the same for re-setup.)
However, since partial refresh mode is not entered unless MODE = L when partial refresh is not used, it is not necessary
to set the mode register. Moreover, when using page read without using partial refresh, it is not necessary to set the
mode register.
4.1 Mode Register Setting Method
The mode register setting mode can be entered by successively writing two specific data after two continuous reads of
the highest address (3FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two
write cycles).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting hart, Figure 6-13. Mode
Register Setting Flow Chart.
Table 4-1. shows the commands and command sequences.
Table 4-1. Command s
Command sequence
1st bus cycle
(Read cycle)
2nd bus
(Re
rd bus cycle
(Write cycle)
4th bus cycle
(Write cycle)
Partial refresh density
16M bits
Address
Data
Ad
Address
Data
00H
00H
00H
00H
Address
Data
04H
05H
06H
07H
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFF
–
–
FFH
3FFFFFH
–
–
–
–
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
8M bits
4M bits
0M bit
4th bus cycle (Write cycle)
I/O
15
0
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
Mode Register setting
0
PL
PD
Page length
1
8 words
I/O1 I/O0
Density
16M bits
8M bits
4M bits
0M bit
Partial refresh
density
0
0
1
1
0
1
0
1
12
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
4.2 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling /CS and /OE, toggle /CS at every
cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CS at the first and second read cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the
mode register is not performed correctly.
When the highest address (3FFFFFH) is read consecutively three or more times, the mode register setting entries are
not performed correctly. (Immediately after the highest address is read, the setting of the mode register is not performed
correctly.) Perform the setting of the mode register after power application or after accessing other than the highest
address.
Once the refresh density has been set in the mode register, these settings are retained until they are set again, while
applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the
mode register again after power application.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode
Register Setting Flow Chart.
13
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
5. Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol Condition
Rating
Unit
-B65X
–0.5 Note to +4.0
–
-BE75X
Supply voltage
VCC
VCCQ
VT
–0.5 Note to +4.0
–0.5 Note to +4.0
V
V
Input / Output supply voltage
Input / Output voltage
–0.5 Note to VCC + 0.4 (4.0 V MAX.) –0.5 Note to VCCQ + 0.4 (4.0 V MAX.)
V
Operating ambient temperature TA
–25 to +85
–25 to +85
°C
°C
Storage temperature
Tstg
–55 to +125
–55 to +125
Note –1.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maum Rating conditions for
extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
-B65X
-BE75X
Unit
MIN.
2.7
MIN.
2.7
MAX.
3.1
Supply voltage
VCC
VCCQ
VIH
V
V
Input / Output supply voltage
High level input voltage
Low level input voltage
–
1.65
2.1
0.
CC+0.3
0.2VCC
+85
0.8VCCQ
–0.3 Note
–25
VCCQ+0.3
0.2VCCQ
+85
V
VIL
V
Operating ambient temperature TA
°C
Note –0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25°C, f = 1 MHz
Parameter
Input capacitance
Input / Output capacitance
Test condition
MIN.
TYP.
MAX.
8
Unit
pF
= 0 V
VI/O = 0 V
10
pF
Remarks 1. VIN: Input volta/O: Input / Output voltage
2. These parameters are not 100% tested.
14
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
Density of
data hold
-B65X
TYP.
Unit
MIN.
–1.0
–1.0
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
µA
µA
ILO
VI/O = 0 V to VCC, /CS = VIH or
/WE = VIL or /OE = VIH
/CS = VIL, Minimum cycle time,
II/O = 0 mA
Operating supply current
Standby supply current
ICCA
ISB1
ISB2
45
mA
/CS ≥ VCC − 0.2 V,
64M bits
60
100
µA
MODE ≥ VCC − 0.2 V
/CS ≥ VCC − 0.2 V,
16M bits
8M bits
4M bits
0M bit
50
45
40
60
50
45
10
MODE ≤ 0.2 V
High level output voltage
Low level output voltage
VOH
VOL
IOH = –0.5 mA
IOL = 1 mA
V
V
0.2VCC
Remark VIN: Input voltage, VI/O: Input / Output voltage
DC Characteristics (Recommended Operating Conditions Unle Noted) (2/2)
Parameter
Symbol
Test condition
of
ta hold
-BE75X
TYP.
Unit
MIN.
–1.0
–1.0
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCCQ
µA
µA
ILO
VI/O = 0 V to or
/WE = V
/CS cycle time,
Operating supply current
Standby supply current
ICCA
IS
40
mA
Q − 0.2 V,
≥ VCCQ − 0.2 V
CS ≥ VCCQ − 0.2 V,
MODE ≤ 0.2 V
64M bits
60
100
µA
16M bits
8M bits
4M bits
0M bit
50
45
40
60
50
45
10
High level output voltage
Low level output voltage
VOH
VOL
IOH = –0.5 mA
IOL = 1 mA
0.8VCCQ
V
V
0.2VCCQ
Remark VIN: Input voltage, VI/O: Input / Output voltage
15
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ -B65X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
Vcc
0.8Vcc
Vcc / 2
Test points
Vcc / 2
0.2Vcc
GND
5ns
Output Waveform
Vcc / 2
Test points
Vcc / 2
[ -BE75X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
VccQ
0.8VccQ
VccQ / 2
T
VccQ / 2
0.2VccQ
GND
5ns
Output Waveform
Test points
VccQ / 2
Output Load
AC characteristics directe should be measured with the output load shown in Figure 5-1, Figure 5-2.
Figure 5-1.
[ -B65X ]
Figure 5-2.
[ -BE75X ]
CL: 30 pF
CL: 30 pF
5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ)
5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ)
ZO = 50 Ω
ZO = 50 Ω
I/O (Output)
I/O (Output)
CL
50 Ω
CL
50 Ω
V
CC / 2
V
CCQ / 2
Remark CL includes capacitance of the probe and jig, and stray capacitance.
16
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Read Cycle
Parameter
Symbol
-B65X
-BE75X
Unit Note
MAX.
MIN.
65
MAX.
MIN.
75
Read cycle time
tRC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
Address access time
tAA
65
65
45
65
75
75
50
75
/CS access time
tACS
tOE
/OE to output valid
/LB, /UB to output valid
tBA
Output hold from address change
Page read cycle time
tOH
5
5
tPRC
tPAA
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tASO
tOHAH
tCHAH
tBHAH
tCLOL
tOLCH
tCP
18
25
Page access time
18
25
/CS to output in low impedance
/OE to output in low impedance
/LB, /UB to output in low impedance
/CS to output in high impedance
/OE to output in high impedance
/LB, /UB to output in high impedance
Address set to /OE low level
/OE high level to address hold
/CS high level to address hold
/LB, /UB high level to address hold
/CS low level to /OE low level
/OE low level to /CS high level
/CS high level pulse width
/LB, /UB high level pulse width
/OE high level pulse width
10
5
10
5
5
25
25
25
25
25
25
0
–5
0
0
–5
0
0
0
ns 3, 4
10,000
10,000
0
10,000
10,000
ns
ns
ns
ns
ns
5
2
50
10
10
2
tB
5
Notes 1. Output load: 30 pF
2. Output load: 5 p
3. When tASO ≥ | tCH |, tCHAH and tBHAH (MIN.) are –15 ns.
t
CHAH, tBHAH
Address (Input)
/LB, /UB, /CS (Input)
/OE (Input)
t
ASO
4. tBHAH is specified from when both /LB and /UB become high level.
5. tCLOL and tOP (MAX.) are applied while /CS is being hold at low level.
17
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Write Cycle
Parameter
Symbol
-B65X
-BE75X
Unit Note
MIN.
65
55
55
55
50
0
MAX.
MIN.
75
60
60
60
55
0
MAX.
Write cycle time
tWC
tCW
ns
/CS to end of write
ns
Address valid to end of write
/LB, /UB to end of write
Write pulse width
tAW
ns
tBW
ns
tWP
ns
Write recovery time
tWR
tCP
ns
/CS pulse width
10
10
10
0
10
10
10
0
ns
/LB, /UB high level pulse width
/WE high level pulse width
Address setup time
tBP
ns
tWHP
tAS
ns
ns
/OE high level to address hold
/CS high level to address hold
/LB, /UB high level to address hold
Data valid to end of write
Data hold time
tOHAH
tCHAH
tBHAH
tDW
–5
0
ns
ns
1
0
ns 1, 2
30
0
5
0
ns
ns
tDH
/OE high level to /WE set
/WE high level to /OE set
tOES
tOEH
0
0
10,000
10,000
ns
ns
3
10
10
Notes 1. When tAS ≥ | tCHAH |, | tBHAH | and tCP ≥ 18 ns, tMIN.) are –15 ns.
t
CHAH, tBHAH
Address (Inpu
/LB, /UB
(Input)
t
AS
2. tBHAH is specified from when both /LB and /UB become high level.
3. tOES and tOEH (MAX.) are applied while /CS is being hold at low level.
18
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
6. Timing Charts
Figure 6-1. Read Cycle Timing Chart 1 (/CS Controlled)
t
RC
t
RC
A3
A2
A1
Address (Input)
/CS (Input)
t
ACS
t
CHAH
t
CHAH
t
ACS
t
CP
t
CP
t
CLZ
t
CLZ
t
CHZ
t
CHZ
/OE (Input)
/LB, /UB (Input)
I/O (Output)
L
L
High-Z
High-Z
High-Z
Data Out Q1
a Out Q2
Remark In read cycle, MODE and /WE should be fixed to high lev
Figure 6-2. Read Cyclrt 2 (/OE Controlled)
t
RC
t
RC
Address (Input)
/CS (Input)
A3
A2
t
BHAH
t
t
AA
t
BHAH
L
t
OE
t
OHAH
t
ASO
t
ASO
t
OHAH
/OE (Input)
t
OP
t
OP
/LB, /UB (Input)
t
OHZ
t
OLZ
t
OHZ
t
OLZ
High-Z
High-Z
High-Z
I/O (Output)
Data Out Q1
Data Out Q2
Remark In read cycle, MODE and /WE should be fixed to high level.
19
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-3. Read Cycle Timing Chart 3 (/CS, /OE Controlled)
t
RC
t
RC
Address (Input)
/CS (Input)
A2
A1
A3
t
t
CHAH
t
AA
t
OHAH
t
ACS
t
OLCH
t
BHAH
t
BHAH
CHZ
OHAH
t
t
CLZ
t
OE
t
ASO
t
OHZ
t
CLOL
t
OE
/OE (Input)
/LB, /UB (Input)
I/O (Output)
t
OHZ
t
OLZ
t
OLZ
High-Z
High-Z
High-Z
Data Out Q1
Q2
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-4. Read Cycle Timing Cs Controlled)
t
RC
t
RC
A2
A1
A3
Address (Input)
/CS (Input)
t
AA
t
AA
L
/OE (Input)
L
L
/LB, /UB (Input)
t
OH
t
OH
t
OH
I/O (Output)
Data Out Q2
Data Out Q1
Remark In read cycle, MODE and /WE should be fixed to high level.
20
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-5. Read Cycle Timing Chart 5 (/LB, /UB Controlled)
tRC
tRC
Address (Input)
A2
A1
A3
/CS (Input)
/OE (Input)
L
L
tBHAH
tBHAH
/LB, /UB (Input)
I/O (Output)
tBP
tBP
t
BA
t
BA
t
BHZ
tBHZ
t
BLZ
t
BLZ
High-Z
High-Z
High-Z
Data Out Q1
2
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-6. Page Read Chart
t
RC
t
PRC
t
PRC
t
PRC
t
PRC
t
PRC
tPRC
Address
(A3 to A21) (Input)
A
N
A
N+1
A
N+4
A
N+5
A
N+6
AN+7
Page Address
(A0 to A2) (Input)
t
OH
/CS (Input)
/OE (Input)
t
CHZ
t
OHZ
t
AA
t
PAA
t
PAA
t
PAA
t
PAA
t
PAA
t
PAA
t
PAA
t
OH
t
OH
tOH
t
OH
t
OH
t
OH
t
OH
High-Z
I/O (Output)
Q
N
Q
N+1
Q
N+2
Q
N+3
Q
N+4
Q
N+5
Q
N+6
QN+7
Remarks 1. In read cycle, MODE and /WE should be fixed to high level.
2. /LB and /UB are low level.
21
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-7. Write Cycle Timing Chart 1 (/CS Controlled)
tWC
tWC
A3
Address (Input)
A2
A1
tAS
tAS
tCW
tAS
tWR
tWR
tCW
/CS (Input)
/WE (Input)
tCP
tCP
L
L
/LB, /UB (Input)
tOHAH
tASO
tOES
tOEH
/OE (Input)
I/O (Input)
t
DW
t
DH
tDH
High-Z
High-
High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins , or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while e output state.
3. In write cycle, MODE and /OE shouhigh level.
Remark Write operation is done during thof a low level /CS, /WE, /LB and/or /UB.
22
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-8. Write Cycle Timing Chart 2 (/WE Controlled)
tWC
tWC
A3
Address (Input)
/CS (Input)
A2
A1
t
CHAH
tCHAH
tCW
tCW
tAS
t
WP
t
WR
t
CP
t
AS
t
WP
t
WR
tCP
/WE (Input)
t
WHP
tBHAH
tBHAH
/LB, /UB (Input)
tOHAH
tASO
t
OES
tOEH
/OE (Input)
I/O (Input)
t
DW
t
DH
tDH
High-Z
High-
High-Z
Data In D1
ata In D2
Cautions 1. During address transition, at least one of pins or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while output state.
3. In write cycle, MODE and /OE shouhigh level.
Remark Write operation is done during the of a low level /CS, /WE, /LB and/or /UB.
23
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-9. Write Cycle Timing Chart 3 (/WE Controlled)
t
WC
t
WC
A3
Address (Input)
/CS (Input)
A2
A1
t
AW
t
AW
L
t
AS
t
WP
t
WR
t
AS
t
WP
t
WR
/WE (Input)
t
WHP
t
BHAH
t
BHAH
/LB, /UB (Input)
t
OHAH
t
ASO
t
OES
t
OEH
/OE (Input)
I/O (Input)
t
DW
t
DH
t
DH
High-Z
High-
High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while e output state.
3. In write cycle, MODE and /OE shouhigh level.
Remark Write operation is done during thof a low level /CS, /WE, /LB and/or /UB.
24
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-10. Write Cycle Timing Chart 4 (/LB, /UB Controlled)
tWC
tWC
Address (Input)
A3
A2
A1
/CS (Input)
/WE (Input)
L
tBW
tWR
tAS
tBW
tAS
tWR
/LB, /UB (Input)
tBP
tBP
tOHAH
tASO
tOES
tOEH
/OE (Input)
I/O (Input)
t
DW
t
DH
t
DH
High-Z
High-
High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins , or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while e output state.
3. In write cycle, MODE and /OE shouhigh level.
Remark Write operation is done during thof a low level /CS, /WE, /LB and/or /UB.
25
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-11. Write Cycle Timing Chart 5 (/LB, /UB Independent Controlled)
tWC
tWC
Address (Input)
A1
A3
A2
/CS (Input)
/WE (Input)
L
tAS
tBW
tWR
/LB (Input)
tAS
tBW
tWR
/UB (Input)
/OE (Input)
tBP
tOHAH
tASO
tOES
tOEH
tDW
tDH
High-Z
High-Z
I/O0 to I/O7 (Input)
I/O8 to I/O15 (Input)
Data In D1
tDW
tDH
High-Z
Data In D2
Cautions 1. During address transone of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input dpins while they are in the output state.
3. In write cyd /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
26
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-12. Mode Register Setting Timing Chart
Mode Register Setting
tRC
tRC
tWC
tWC
Address (Input)
/CS (Input)
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
/OE (Input)
tWP
tWR
tWP
tWR
/WE (Input)
tDW
t
t
DW
t
DH
High-Z
High-Z
xxxxH
I/O (Input)
/LB, /UB (Input)
Figure 6-13. Modtting Flow Chart
ess= 3FFFFFH
th toggled the /CS, /OE
No
Address= 3FFFFFH
Read with toggled the /CS, /OE
Address = 3FFFFFH
Write
No
No
Data = 00H?
No
Address = 3FFFFFH
Write
Fail
Note
Data = xxH?
Mode register setting exit
End
Note xxH = 04H, 05H, 06H, 07H
27
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart
MODE (Input)
tCHML
tMHCL1
/CS (Input)
Standby
mode 1
Standby mode 2
(Data hold: 16M bits / 8M bits / 4M bits)
Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart
MODE (Input)
/CS (Input)
tCHML
Standby mode 2
(Data not held
Standby
mode 1
Standby Mode 2 Entry / Exit
Parameter
Sym
MIN.
0
MAX.
Unit Note
ns
Standby mode 2 entry
/CS high level to MODE low level
Standby mode 2 exit to normal operation
MODE high level to /CS low level
tMHCL2
30
ns
1
2
Standby mode 2 exit to normal
MODE high level to /CS lo
200
µs
Notes 1. This is the time it to return to normal operation from Standby Mode 2 (data hold: 16M bits / 8M bits / 4M
bits).
2. This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
28
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
7. Package Drawing
The following is a package drawing of package sample.
93-PIN TAPE FBGA (12x9)
ZD
ZE
w
S
B
B
E
10
9
8
7
6
5
4
3
2
1
A
P N M E D C B A
INDEX MARK
w
S A
ITEM MILLIMETERS
A
D
E
9.0 0.1
12.0 0.1
0.2
A2
y1
S
w
e
0.8
A
1.3 0.1
0.16 0.05
1.14
A1
A2
b
0.40 0.05
0.08
y
S
e
x
φ
φ
y
0.1
b
y1
ZD
ZE
0.2
0.9
0.8
P93F9-80-CR2
29
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
8. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD4664312-X package sample.
Type of Surface Mount Device
µPD4664312F9-CR2: 93-pin TAPE FBGA (12 x 9)
30
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
9. Revision History
Edition/
Date
Page
Type of
revision
Location
Description
(Previous edition → This edition)
This
edition
Previous
edition
6h edition/
Nov. 2005
Throughout Throughout Modification Part number
The part numbers have been uncarried.
“Note” has been added to -B65X.
Remark
–
p.16
p.16
Addition
AC Characteristics
Output Load
p.17
p.20
p.17
p.21
Modification Read Cycle
Addition Figure 6-3. Read Cycle
Timing Chart 3
-BE75X tOLCH (MIN.) : 45 ns → 50 ns
tOLCH
p.21
p.22
Modification Figure 6-6. Page Read
Cycle Timing Chart
tACS → tAA
31
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
[ MEMO ]
32
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
[ MEMO ]
33
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
[ MEMO ]
34
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destructiote oxide and
ultimately degrade the device operation. Steps must be taken to stop genectricity as
much as possible, and quickly dissipate it when it has occurred. Etrol must be
adequate. When it is dry, a humidifier should be used. It is recommeg insulators that
easily build up static electricity. Semiconductor devices must be srted in an anti-static
container, static shielding bag or conductive material. All tesnt tools including work
benches and floors should be grounded. The operatonded using a wrist strap.
Semiconductor devices must not be touched with bare ecautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define tha MOS device. Immediately after the power
source is turned ON, devices with resnot yet been initialized. Hence, power-on does
not guarantee output pin levels, I/ents of registers. A device is not initialized until the
reset signal is received. A ret be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF S
In the case of s different power supplies for the internal operation and external
interface, as the external power supply after switching on the internal power supply.
When swsupply off, as a rule, switch off the external power supply and then the
internal pose of the reverse power on/off sequences may result in the application of an
overvoltage to nternal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
35
Preliminary Data Sheet M15867EJ6V0DS
µPD4664312-X
•
The information in this document is current as of November, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
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customers or third parties arising from the use of these cirand information.
•
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majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
UPD4664312-BE75X
STANDARD SRAMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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RENESAS
UPD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATIONWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NEC
UPD4664312F9-B65X-CR2
64M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATIONWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD4664312F9-BE75X-CR2
64M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATIONWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NEC
UPD46710ALN-12
SRAM|2X16KX10|BICMOS-TTL|LDCC|52PIN|PLASTICWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
UPD46710ALN-15
SRAM|2X16KX10|BICMOS-TTL|LDCC|52PIN|PLASTICWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
UPD46710LN-15
SRAM|2X16KX10|BICMOS-TTL|LDCC|52PIN|PLASTICWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
UPD46710LN-20
SRAM|2X16KX10|BICMOS-TTL|LDCC|52PIN|PLASTICWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
UPD46741ALP-12
x20 SRAMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD46741ALP-15
x20 SRAMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
UPD46741LP-15
x20 SRAMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ETC
UPD46741LP-20
x20 SRAMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
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