UPD70F3008YGJ-16-8EU [RENESAS]
UPD70F3008YGJ-16-8EU;
| 型号： | UPD70F3008YGJ-16-8EU |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | UPD70F3008YGJ-16-8EU 光电二极管 外围集成电路 |
| 文件： | 总419页 (文件大小：1731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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2.
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4.
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User’s Manual
V854TM
32/16-Bit Single-Chip Microcontroller
Hardware
µPD703006
µPD703008
µPD70F3008
µPD703008Y
µPD70F3008Y
Document No. U11969EJ3V0UM00 (3rd edition)
Date Published March 1999 N CP(K)
©
1997
Printed in Japan
[MEMO]
2
User’s Manual U11969EJ3V0UM00
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
V854, and V850 Family are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
UNIX is a registered trademark licensed by X/Open Company Limited in the United States and other countries.
User’s Manual U11969EJ3V0UM00
3
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products
may be prohibited without governmental license. To export or re-export some or all of these products from a country other than
Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed
: µPD703006, 70F3008, 70F3008Y
The customer must judge the need for license: µPD703008, 703008Y
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96.5
4
User’s Manual U11969EJ3V0UM00
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
User’s Manual U11969EJ3V0UM00
5
Major Revisions in This Edition
Page
Contents
Throughout
Deletion of BVDD and BVSS
Modification of voltage of VPP
Addition of µPD703006 to the target devices
p.44
p.47
Modification of description in 2.3 (19) MODE0 to MODE2 (Mode 0 to 2)
Modification of recommended connection method for pins P40/AD0 to P47/AD7, P50/AD8
to P57/AD15, P60/A16 to P67/A23, P90/LBEN/WRL, P91/UBEN, P92/R/W/WRH, P93/
DSTB/RD, P94/ASTB, P95/HLDAK, P96/HLDRQ, WAIT, and MODE0 to MODE2 in 2.4
Pin I/O Circuit Type and Connection of Unused Pins
p.53
Modification of description of EP flag in Figure 3-3 Program Status Word (PSW)
Modification of description in 3.3.2 Specifying operation mode
Addition of Caution in 6.5.1 (2) IDLE mode
p.54
p.140
p.140
p.140
p.142
p.149
Modification of description in 6.5.1 (3) (a) PLL mode
Modification of description in 6.5.1 (3) (b) Direct mode
Modification of description of CESEL bit in 6.5.2 (1) Power save control register (PSC)
Modification of description in 6.6 (1) Securing time using internal time base counter
(NMI pin input)
p.150
Modification of description in 6.6 (2) Securing time by signal level width (RESET pin
input)
p.159
p.161
p.206
p.220
p.241
p.242
p.276
Addition of Note in 7.2 (1) Timer 0 (24-bit timer/event counter)
Addition of description in 7.2.1 (1) Timers 0, 0L (TM0, TM0L)
Addition to the item Transfer rate in 8.2.1 Features
Addition to the item High transfer speed in 8.3.1 Features
Addition of Note to bits 4 and 5 in 8.4.4 (3) IIC clock selection register (IICCL)
Addition of Caution to 8.4.4 (4) IIC shift register (IIC)
Addition of 8.4.6 (15) (b) Operation during communication reservation (when a multi-
master is used), (c) Start operation after communication reservation (when a multi-
master is used), and (d) STT setting timing (when a multi-master is used)
Modification of description of function of bits FR2 to FR0 in the table in 9.3 (2) A/D
converter mode register 1 (ADM1)
p.299
p.301
Modification of setting value of ADM1 register in the table of operation and trigger modes
in 9.4.2 Operation mode and trigger mode
pp.308 to 310,
312 to 318
p.319
Addition of Tables 9-1 to 9-9 and Figures 9-6 to 9-14
Modification of description in 9.8.2 Interval of the external/timer trigger
Addition of description in 13.2 (2) Power-ON reset
p.379
p.380
Modification of initial values after reset of timer registers (TM0, TM1, TM0L, TM1L, TM20
to TM24, TM3) in Table 13-2 Initial Values after Reset of Each Register (1/2)
Deletion of CSI2 in 14.3 Programming Environment
p.384
p.385
p.388
Deletion of CSI2, SO2, SI2, and SCK2 in 14.4 Communication System
Deletion of CSI2 and the pin used by CSI2 in the table of pins used by each serial
interface in 14.5.2 Serial interface pin
p.392
p.393
Deletion of CSI2 in Table 14-1 List of Communication Systems
Modification of the table of flash memory control commands in 14.6.4 Communication
command
The mark
shows major revised points in this edition.
6
User’s Manual U11969EJ3V0UM00
INTRODUCTION
Readers
This manual is intended for users who understand the functions of the V854
(µPD703006,703008,70F3008,703008Y,70F3008Y)anddesignapplicationsystems
using the V854.
Purpose
This manual is intended to enable users to understand the hardware functions
described in the Organization below.
Organization
The V854 User’s Manual is divided into two parts: hardware (this manual) and
architecture (V850 FamilyTM Architecture User’s Manual) manuals.
Hardware
• Pin function
Architecture
• Data type
• CPU function
• Register set
• Internal peripheral function
• Flash memory programming
mode
• Instruction format and instruction set
• Interrupt and exception
• Pipeline operation
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To find out the details of a register whose the name is known:
→ Refer to APPENDIX A REGISTER INDEX.
• To findout the details of a function whose name is known:
→ Refer to APPENDIX C INDEX.
• To understand the details of an instruction function:
→ Refer to the V850 Family Architecture User’s Manual available separately.
• To understand the overall functions of the V854:
→ Read this manual according to the Table of Contents.
Conventions
Data significance:
Active low:
Higher digits on the left and lower digits on the right
xxx (overscore over pin or signal name)
High order at high stage and low order at low stage
Footnote for items marked with Note in the text
Information requiring particular attention
Supplementary information
Memory map address:
Note:
Caution:
Remark:
Number representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefixes indicating power of 2 (address space, memory capacity):
K (kilo): 210 = 1024
M (mega): 220 = 10242
G (giga): 230 = 10243
User’s Manual U11969EJ3V0UM00
7
Related documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
• Documents related to devices
Document Name
Document No.
U10243E
V850 Family Architecture User’s Manual
V850 Family Instruction Table
µPD703008 Data Sheet
U10229E
To be prepared
To be prepared
U12756E
µPD703008Y Data Sheet
µPD70F3008 Data Sheet
µPD70F3008Y Data Sheet
V854 Hardware User’s Manual
U12755E
This manual
• Documents related to development tools (User’s Manual)
Document Name
IE-703002-MC (In-circuit emulator)
Document No.
U11595E
U12420E
U12839E
IE-703008-MC-EM1 (In-circuit emulator option board)
CA850 (C Compiler Package)
Operation (UNIXTM based)
Operation (WindowsTM based)
C Language
U12827E
U12840E
U10543E
U13716E
U13430E
U13431E
Assembly Language
Operation Windows based
Basics
ID850 (Ver.1.31) (Integrated Debugger)
RX850 (Real Time OS)
Technical
Installation
Fundamental
Technical
U13410E
U13773E
U13772E
U13774E
U11158E
U13737E
RX850 Pro (Real Time OS)
Installation
RD850 (Task Debugger)Note
RD850 (Ver.3.0) (Task Debugger)
AZ850 (System Performance Analyzer)
U11181E
SM850 (Ver.2.0) (System Simulator) Operation Windows based.
Under preparation
Note
Supports ID850 (Ver.1.31)
8
User’s Manual U11969EJ3V0UM00
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION .............................................................................................................. 23
1.1 General ..................................................................................................................................... 23
1.2 Features ................................................................................................................................... 24
1.3 Application Fields ................................................................................................................... 25
1.4 Ordering Information.............................................................................................................. 25
1.5 Pin Identification (Top View) ................................................................................................. 26
1.6 Function Block Configuration............................................................................................... 28
1.6.1
1.6.2
Internal block diagram ................................................................................................................. 28
Internal units................................................................................................................................. 29
CHAPTER 2 PIN FUNCTIONS ............................................................................................................. 31
2.1 Pin Function List..................................................................................................................... 31
2.2 Pin Status................................................................................................................................. 36
2.3 Pin Function ............................................................................................................................ 37
2.4 Pin I/O Circuit Type and Connection of Unused Pins....................................................... 47
2.5 I/O Circuits of Pins ................................................................................................................. 48
CHAPTER 3 CPU FUNCTIONS ........................................................................................................... 49
3.1 Features ................................................................................................................................... 49
3.2 CPU Register Set .................................................................................................................... 50
3.2.1
3.2.2
Program register set .................................................................................................................... 51
System register set ...................................................................................................................... 52
3.3 Operation Modes..................................................................................................................... 54
3.3.1
3.3.2
Operation modes ......................................................................................................................... 54
Specifying operation mode .......................................................................................................... 54
3.4 Address Space ........................................................................................................................ 56
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
CPU address space ..................................................................................................................... 56
Image (Virtual Address Space) ................................................................................................... 57
Wrap-around of CPU address space .......................................................................................... 58
Memory map ................................................................................................................................ 59
Area .............................................................................................................................................. 60
External expansion mode ............................................................................................................ 67
Recommended use of address space ........................................................................................ 69
Peripheral I/O registers ............................................................................................................... 71
Specific registers.......................................................................................................................... 77
CHAPTER 4 BUS CONTROL FUNCTION .......................................................................................... 81
4.1 Features ................................................................................................................................... 81
4.2 Bus Control Pins and Control Register............................................................................... 82
4.2.1
4.2.2
Bus control pins ........................................................................................................................... 82
Control register ............................................................................................................................ 82
4.3 Bus Access .............................................................................................................................. 83
4.3.1
Number of access clocks ............................................................................................................ 83
9
User’s Manual U11969EJ3V0UM00
4.3.2
Bus width ...................................................................................................................................... 84
4.4 Memory Block Function......................................................................................................... 85
4.5 Wait Function .......................................................................................................................... 86
4.5.1
4.5.2
4.5.3
Programmable wait function ........................................................................................................ 86
External wait function .................................................................................................................. 87
Relations between programmable wait and external wait ......................................................... 87
4.6 Idle State Insertion Function................................................................................................. 88
4.7 Bus Hold Function .................................................................................................................. 89
4.7.1
4.7.2
4.7.3
Outline of function........................................................................................................................ 89
Bus hold procedure...................................................................................................................... 89
Operation in power save mode ................................................................................................... 89
4.8 Bus Timing............................................................................................................................... 90
4.9 Bus Priority .............................................................................................................................. 97
4.10 Memory Boundary Operation Condition ............................................................................. 97
4.10.1 Program space ............................................................................................................................. 97
4.10.2 Data space ................................................................................................................................... 97
4.11 Internal Peripheral I/O Interface ........................................................................................... 98
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION ................................................. 99
5.1 Features ................................................................................................................................... 99
5.2 Non-Maskable Interrupt ....................................................................................................... 102
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Operation.................................................................................................................................... 103
Restore ....................................................................................................................................... 105
Non-maskable interrupt status flag (NP) .................................................................................. 106
Noise elimination circuit of NMI pin .......................................................................................... 106
Edge detection function of NMI pin........................................................................................... 106
5.3 Maskable Interrupts .............................................................................................................. 107
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
Operation.................................................................................................................................... 109
Restore ....................................................................................................................................... 111
Priorities of maskable interrupts ............................................................................................... 112
Interrupt control register (xxICn) ............................................................................................... 116
In-service priority register (ISPR).............................................................................................. 118
Maskable interrupt status flag (ID)............................................................................................ 118
Noise elimination........................................................................................................................ 119
Edge detection function ............................................................................................................. 120
Frequency divider ...................................................................................................................... 124
5.4 Software Exception .............................................................................................................. 126
5.4.1
5.4.2
5.4.3
Operation.................................................................................................................................... 126
Restore ....................................................................................................................................... 127
Exception status flag (EP) ......................................................................................................... 128
5.5 Exception Trap ...................................................................................................................... 129
5.5.1
5.5.2
5.5.3
Illegal op code definition............................................................................................................ 129
Operation.................................................................................................................................... 129
Restore ....................................................................................................................................... 130
5.6 Multiple interrupt processing.............................................................................................. 131
5.7 Interrupt Response Time ..................................................................................................... 133
10
User’s Manual U11969EJ3V0UM00
5.8 Periods Where Interrupt is Not Acknowledged................................................................ 133
CHAPTER 6 CLOCK GENERATOR FUNCTION ............................................................................. 135
6.1 Features ................................................................................................................................. 135
6.2 Configuration......................................................................................................................... 135
6.3 Selecting Input Clock ........................................................................................................... 136
6.3.1
6.3.2
6.3.3
Direct mode ................................................................................................................................ 136
PLL mode ................................................................................................................................... 136
Clock control register (CKC) ..................................................................................................... 137
6.4 PLL Lock-up .......................................................................................................................... 139
6.5 Power Save Control.............................................................................................................. 140
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
General ....................................................................................................................................... 140
Control registers......................................................................................................................... 142
HALT mode ................................................................................................................................ 143
IDLE mode ................................................................................................................................. 145
Software STOP mode ................................................................................................................ 147
6.6 Specifying Oscillation Stabilization Time ......................................................................... 149
6.7 Clock Output Control ........................................................................................................... 152
6.7.1
6.7.2
6.7.3
Configuration .............................................................................................................................. 152
CLKOUT signal output control .................................................................................................. 152
CLO signal output control.......................................................................................................... 153
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) ..................................... 157
7.1 Features ................................................................................................................................. 157
7.2 Basic Configuration.............................................................................................................. 158
7.2.1
7.2.2
7.2.3
7.2.4
Timer 0 ....................................................................................................................................... 161
Timer 1 ....................................................................................................................................... 162
Timer 2 ....................................................................................................................................... 164
Timer 3 ....................................................................................................................................... 165
7.3 Control Register .................................................................................................................... 166
7.4 Timer 0 Operation ................................................................................................................. 174
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
Count operation ......................................................................................................................... 174
Count clock selection................................................................................................................. 175
Overflow ..................................................................................................................................... 176
Clearing/starting timer ............................................................................................................... 177
Capture operation ...................................................................................................................... 179
Compare operation .................................................................................................................... 181
7.5 Timer 1 Operation ................................................................................................................. 183
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
Count operation ......................................................................................................................... 183
Count clock selection................................................................................................................. 183
Overflow ..................................................................................................................................... 184
Clearing/starting timer ............................................................................................................... 185
Capture operation ...................................................................................................................... 186
Compare operation .................................................................................................................... 187
7.6 Timer 2 Operation ................................................................................................................. 188
7.6.1
Count operation ......................................................................................................................... 188
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User’s Manual U11969EJ3V0UM00
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
Count clock selection................................................................................................................. 188
Overflow ..................................................................................................................................... 189
Clearing/starting timer ............................................................................................................... 189
Compare operation .................................................................................................................... 189
Toggle output ............................................................................................................................. 191
7.7 Timer 3 Operation ................................................................................................................. 192
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
Count operation ......................................................................................................................... 192
Count clock selection................................................................................................................. 192
Overflow ..................................................................................................................................... 192
Clearing/starting timer ............................................................................................................... 193
Capture operation ...................................................................................................................... 193
Compare operation .................................................................................................................... 194
7.8 Application Examples .......................................................................................................... 195
7.9 Note......................................................................................................................................... 203
CHAPTER 8 SERIAL INTERFACE FUNCTION ............................................................................... 205
8.1 Features ................................................................................................................................. 205
8.2 Asynchronous Serial Interface (UART) ............................................................................. 206
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Features ..................................................................................................................................... 206
Configuration of asynchronous serial interface ........................................................................ 207
Control registers......................................................................................................................... 209
Interrupt request......................................................................................................................... 215
Operation.................................................................................................................................... 216
8.3 Clocked Serial Interface 0 to 3 (CSI0 to CSI3) ................................................................. 220
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
Features ..................................................................................................................................... 220
Configuration .............................................................................................................................. 220
Control registers......................................................................................................................... 222
Basic operation .......................................................................................................................... 224
Transmission in CSI0 to CSI3 ................................................................................................... 226
Reception in CSI0 to CSI3 ........................................................................................................ 227
Transmission/reception in CSI0 to CSI3 .................................................................................. 228
System configuration example .................................................................................................. 230
8.4 I2C Bus (µPD703008Y and 70F3008Y only) ....................................................................... 231
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
Features ..................................................................................................................................... 231
Functions .................................................................................................................................... 232
Configuration .............................................................................................................................. 234
Serial interface control register ................................................................................................. 236
I2C bus functions ........................................................................................................................ 242
Definition and controls of I2C bus ............................................................................................. 243
Communication operation.......................................................................................................... 277
Timing chart ............................................................................................................................... 279
8.5 Baud Rate Generator 0 to 3 (BRG0 to BRG3) .................................................................. 286
8.5.1
8.5.2
8.5.3
Configuration and function ........................................................................................................ 286
Baud rate generator compare registers 0 to 3 (BRGC0 to BRGC3) ...................................... 291
Baud rate generator prescaler mode registers 0 to 3 (BPRM0 to BPRM3) ........................... 292
8.6 Selection of Operational Serial Interface .......................................................................... 293
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User’s Manual U11969EJ3V0UM00
CHAPTER 9 A/D CONVERTER ......................................................................................................... 295
9.1 Features ................................................................................................................................. 295
9.2 Configuration......................................................................................................................... 295
9.3 Control Register .................................................................................................................... 297
9.4 A/D Converter Operation ..................................................................................................... 301
9.4.1
9.4.2
Basic operation of A/D converter .............................................................................................. 301
Operation mode and trigger mode ............................................................................................ 301
9.5 Operation in the A/D Trigger Mode .................................................................................... 308
9.5.1
9.5.2
Select mode operation............................................................................................................... 308
Scan mode operation................................................................................................................. 310
9.6 Operation in the Timer Trigger Mode ................................................................................ 311
9.6.1
9.6.2
Select mode operation............................................................................................................... 311
Scan mode operation................................................................................................................. 314
9.7 Operation in the External Trigger Mode............................................................................ 315
9.7.1
9.7.2
Select mode operation (External trigger select)....................................................................... 315
Scan mode operation (External trigger scan) .......................................................................... 318
9.8 Precautions Regarding Operations.................................................................................... 319
9.8.1
9.8.2
9.8.3
9.8.4
Stop of conversion operations .................................................................................................. 319
Interval of the external/timer trigger.......................................................................................... 319
Operation in the standby mode ................................................................................................. 319
Compare coincide interrupt in the timer trigger mode ............................................................. 319
CHAPTER 10 REAL-TIME OUTPUT FUNCTION ............................................................................. 321
10.1 Configuration and Function ................................................................................................ 321
10.2 Control Register .................................................................................................................... 322
10.3 Operation ............................................................................................................................... 322
10.4 Example .................................................................................................................................. 323
CHAPTER 11 PWM UNIT................................................................................................................... 325
11.1 Features ................................................................................................................................. 325
11.2 Configuration......................................................................................................................... 326
11.3 Control Register .................................................................................................................... 327
11.4 PWM Operations ................................................................................................................... 330
11.4.1 Basic operations of PWM .......................................................................................................... 330
11.4.2 Enabling/disabling PWM operation ........................................................................................... 332
11.4.3 Specification of active level of PWM pulse .............................................................................. 333
11.4.4 Specification of PWM pulse width rewrite cycle....................................................................... 333
11.4.5 Repetition frequency .................................................................................................................. 335
CHAPTER 12 PORT FUNCTION ....................................................................................................... 337
12.1 Features ................................................................................................................................. 337
12.2 Basic Configuration of Ports .............................................................................................. 338
12.3 Port Pin Function .................................................................................................................. 348
12.3.1 Port 0 .......................................................................................................................................... 348
12.3.2 Port 1 .......................................................................................................................................... 350
12.3.3 Port 2 .......................................................................................................................................... 352
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User’s Manual U11969EJ3V0UM00
12.3.4 Port 3 .......................................................................................................................................... 354
12.3.5 Port 4 .......................................................................................................................................... 357
12.3.6 Port 5 .......................................................................................................................................... 359
12.3.7 Port 6 .......................................................................................................................................... 361
12.3.8 Port 7, port 8 .............................................................................................................................. 363
12.3.9 Port 9 .......................................................................................................................................... 364
12.3.10 Port 10 ........................................................................................................................................ 366
12.3.11 Port 11 ........................................................................................................................................ 368
12.3.12 Port 12 ........................................................................................................................................ 371
12.3.13 Port 13 ........................................................................................................................................ 373
12.3.14 Port 14 ........................................................................................................................................ 375
CHAPTER 13 RESET FUNCTION ..................................................................................................... 377
13.1 Features ................................................................................................................................. 377
13.2 Pin Function .......................................................................................................................... 377
13.3 Initialize .................................................................................................................................. 379
CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y ONLY) ..................................... 383
14.1 Features ................................................................................................................................. 383
14.2 Writing by Flash Writer ........................................................................................................ 383
14.3 Programming Environment ................................................................................................. 384
14.4 Communication System ....................................................................................................... 385
14.5 Pin Handling .......................................................................................................................... 386
14.5.1 VPP pin ........................................................................................................................................ 387
14.5.2 Serial interface pin ..................................................................................................................... 388
14.5.3 Reset pin .................................................................................................................................... 390
14.5.4 NMI pin ....................................................................................................................................... 390
14.5.5 Mode pin..................................................................................................................................... 390
14.5.6 Port pin ....................................................................................................................................... 390
14.5.7 Other signal pin.......................................................................................................................... 390
14.5.8 Power supply.............................................................................................................................. 390
14.6 Programming Method........................................................................................................... 391
14.6.1 Flash memory control ................................................................................................................ 391
14.6.2 Flash memory programming mode ........................................................................................... 392
14.6.3 Selection of communication mode ............................................................................................ 392
14.6.4 Communication command ......................................................................................................... 393
14.6.5 Resources used ......................................................................................................................... 393
CHAPTER 15 DIFFERENCES BETWEEN VERSIONS .................................................................... 395
15.1 Differences between Versions with I2C Function and Versions without
I2C Function ........................................................................................................................... 395
15.2 Differences between On-chip Flash Memory Versions, On-chip Mask ROM
Versions, and ROM-less Versions ..................................................................................... 395
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User’s Manual U11969EJ3V0UM00
APPENDIX A REGISTER INDEX ....................................................................................................... 397
APPENDIX B INSTRUCTION SET LIST ........................................................................................... 403
APPENDIX C INDEX ........................................................................................................................... 409
15
User’s Manual U11969EJ3V0UM00
LIST OF FIGURES (1/4)
Figure No.
Title
Page
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
Program Counter (PC) ................................................................................................................ 51
Interrupt Source Register (ECR) ................................................................................................ 52
Program Status Word (PSW) ..................................................................................................... 53
CPU Address Space ................................................................................................................... 56
Image on Address Space ........................................................................................................... 57
External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes) ................................... 64
External Memory Area (when expanded to 4 Mbytes).............................................................. 65
External Memory Area (when fully expanded)........................................................................... 66
Recommended Memory Map...................................................................................................... 70
4-1.
Example of Inserting Wait States ............................................................................................... 87
5-1.
Non-Maskable Interrupt Processing ......................................................................................... 103
Accepting Non-Maskable Interrupt Request ............................................................................ 104
RETI Instruction Processing ..................................................................................................... 105
Block Diagram of Maskable Interrupt ....................................................................................... 108
Maskable Interrupt Processing ................................................................................................. 110
RETI Instruction Processing ..................................................................................................... 111
Example of Interrupt Nesting Process ..................................................................................... 113
Example of Processing Interrupt Requests Simultaneously Generated ................................ 115
Example of Noise Elimination Timing ...................................................................................... 119
Software Exception Processing ................................................................................................ 126
RETI Instruction Processing ..................................................................................................... 127
Exception Trap Processing ....................................................................................................... 129
RETI Instruction Processing ..................................................................................................... 130
Pipeline Operation at Interrupt Request Acknowledge (General Description)....................... 133
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
6-1.
6-2.
Block Configuration ................................................................................................................... 151
CLO Signal Output Timing ........................................................................................................ 153
7-1.
7-2.
7-3.
Basic Operation of Timer 0....................................................................................................... 174
Operation after Occurrence of Overflow (when ECLR0 = 0, OST0 = 1) ............................... 176
Clearing/Starting Timer by TCLR0 Signal Input
(when ECLR0 = 1, CCLR0 = 0, OST0 = 0) ............................................................................. 177
Relations between Clear/Start by TCLR0 Signal Input and Overflow
7-4.
(when ECLR0 = 1, OST0 = 1) .................................................................................................. 178
Clearing/Starting Timer by CC03 Coincidence (when CCLR0 =1, OST0 = 0) ...................... 178
Relations between Clear/Start by CC03 Coincidence and Overflow Operation
7-5.
7-6.
(when CCLR0 = 1, OST0 = 1) .................................................................................................. 179
Example of TM0 Capture Operation ........................................................................................ 180
Example of TM0 Capture Operation (when both edges are specified) .................................. 180
Example of Compare Operation ............................................................................................... 181
7-7.
7-8.
7-9.
16
User’s Manual U11969EJ3V0UM00
LIST OF FIGURES (2/4)
Figure No.
Title
Page
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
Example of TM0 Compare Operation (set/reset output mode)............................................... 182
Basic Operation of Timer 1....................................................................................................... 183
Operation after Occurrence of Overflow (OST1 = 1) .............................................................. 185
Clearing/Starting Timer by Software (when OST1 = 1) .......................................................... 185
Example of TM1 Capture Operation ........................................................................................ 186
Example of Compare Operation ............................................................................................... 187
Basic Operation of Timer 2....................................................................................................... 188
Operation with CM2n at 1 to FFFFH........................................................................................ 190
When CM2n is Set to 0............................................................................................................. 190
Example of Toggle Output Operation ...................................................................................... 191
Basic Operation of Timer 3....................................................................................................... 192
Example of TM3 Capture Operation
(when ES301 = 0, ES300 = 0, CMS3 = 0, CE3 = 1) .............................................................. 194
Example of Timing of Interval Timer Operation (timer 2) ....................................................... 195
Setting Procedure of Interval Timer Operation (timer 2)......................................................... 195
Pulse Width Measurement Timing (timer 0) ............................................................................ 196
Setting Procedure for Pulse Width Measurement (timer 0) .................................................... 197
Interrupt Request Processing Routine Calculating Pulse Width (timer 0) ............................. 197
Example of PWM Output Timing .............................................................................................. 198
Example of PWM Output Programming Procedure................................................................. 199
Example of Interrupt Request Processing Routine, Modifying Compare Value .................... 200
Example of Frequency Measurement Timing .......................................................................... 201
Example of Set-up Procedure for Frequency Measurement .................................................. 202
Example of Interrupt Request Processing Routine Calculating Cycle ................................... 202
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
8-1.
Block Diagram of Asynchronous Serial Interface .................................................................... 208
Format of Transmit/Receive Data of Asynchronous Serial Interface ..................................... 216
Asynchronous Serial Interface Transmission Completion Interrupt Timing ........................... 217
Asynchronous Serial Interface Reception Completion Interrupt Timing................................. 219
Receive Error Timing ................................................................................................................ 219
Block Diagram of Clocked Serial Interface .............................................................................. 221
Timing of 3-Wire Serial I/O Mode (transmission) .................................................................... 226
Timing of 3-Wire Serial I/O Mode (reception).......................................................................... 227
Timing of 3-Wire Serial I/O Mode (transmission/reception) .................................................... 229
Example of CSI System Configuration..................................................................................... 230
Example of Serial Bus Configuration Using I2C Bus ............................................................... 232
Block Diagram of I2C Bus ......................................................................................................... 233
Pin Configuration ....................................................................................................................... 242
Serial Data Transfer Timing of I2C Bus.................................................................................... 243
Start Condition........................................................................................................................... 243
Address ...................................................................................................................................... 244
Transfer Direction Specification ............................................................................................... 245
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
17
User’s Manual U11969EJ3V0UM00
LIST OF FIGURES (3/4)
Figure No.
Title
Page
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
Acknowledge Signal .................................................................................................................. 246
Stop Condition ........................................................................................................................... 247
Wait Signal ................................................................................................................................ 248
Example of Arbitration Timing .................................................................................................. 272
Communication Reservation Timing ........................................................................................ 274
Communication Reservation Procedure................................................................................... 275
STT Setting Timing Procedure ................................................................................................. 276
Master Operation Procedure .................................................................................................... 277
Slave Operation Procedure ...................................................................................................... 278
Example of Master → Slave Communication
(9-clock wait is selected both for master and slave) ............................................................... 280
Example of Slave → Master Communication
8-28.
8-29.
(9-clock wait is selected both for master and slave) ............................................................... 283
Block Diagram of Baud Rate Generator .................................................................................. 287
9-1.
Block Diagram of A/D Converter .............................................................................................. 296
Relation between Analog Input Voltage and A/D Conversion Result .................................... 300
Operation Timing Example of Select Mode: 1-Buffer Mode (ANI1) ....................................... 303
Operation Timing Example of Select Mode: 4-Buffer Mode (ANI6) ....................................... 304
Operation Timing Example of Scan Mode: 4-Channel Scan (ANI0 to ANI3) ........................ 306
Example of 1-Buffer Mode (A/D trigger select 1-buffer) Operation ........................................ 308
Example of 4-Buffer Mode (A/D trigger select 4-buffer) Operation ........................................ 309
Example of Scan Mode (A/D trigger scan) Operation............................................................. 310
Example of 1-Buffer Mode (timer trigger select 1-buffer) Operation ...................................... 312
Example of Operation in 4-Buffer Mode (timer trigger select 4-buffer) .................................. 313
Example of Scan Mode (timer trigger scan) Operation........................................................... 314
Example of 1-Buffer Mode (external trigger select 1-buffer) Operation ................................. 316
Example of 4-Buffer Mode (external trigger select 4-buffer) Operation ................................. 317
Example of Scan Mode (external trigger scan) Operation...................................................... 318
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
10-1.
10-2.
Block Diagram of Real-Time Output Port ................................................................................ 321
Operational Timings of Real-Time Output Port ....................................................................... 323
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
Configuration of PWM Unit ....................................................................................................... 326
Basic Operations of PWM......................................................................................................... 330
Example of PWM Output by Main Pulse and Additional Pulse .............................................. 331
Example of PWM Output Operation ......................................................................................... 331
Operation Timing of PWM ........................................................................................................ 332
Setting of Active Level of PWM Output ................................................................................... 333
Example 1 of PWM Output Timing (PWM pulse width rewrite cycle 2(x+8)/fPWMC) ................. 334
Example 2 of PWM Output Timing (PWM pulse width rewrite cycle 2x/fPWMC) ...................... 334
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User’s Manual U11969EJ3V0UM00
LIST OF FIGURES (4/4)
Figure No.
Title
Page
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
Block Diagram of Type A .......................................................................................................... 342
Block Diagram of Type B .......................................................................................................... 342
Block Diagram of Type C.......................................................................................................... 343
Block Diagram of Type D.......................................................................................................... 343
Block Diagram of Type E .......................................................................................................... 344
Block Diagram of Type F .......................................................................................................... 344
Block Diagram of Type G ......................................................................................................... 345
Block Diagram of Type H.......................................................................................................... 345
Block Diagram of Type I ........................................................................................................... 346
Block Diagram of Type J .......................................................................................................... 346
Block Diagram of Type K .......................................................................................................... 347
19
User’s Manual U11969EJ3V0UM00
LIST OF TABLES (1/2)
Table No.
Title
Page
3-1.
3-2.
3-3.
Program Registers ...................................................................................................................... 51
System Register Numbers .......................................................................................................... 52
Interrupt/Exception Table ............................................................................................................ 61
4-1.
5-1.
Bus Priority .................................................................................................................................. 97
Interrupt List............................................................................................................................... 100
6-1.
6-2.
6-3.
6-4.
6-5.
Operation of Clock Generator by Power Save Control ........................................................... 141
Operating Status in HALT Mode .............................................................................................. 143
Operating Status in IDLE Mode ............................................................................................... 145
Operating Status in Software STOP Mode .............................................................................. 147
Example of Count Time ............................................................................................................ 151
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
List of Real-Time Pulse Unit (RPU) Configuration .................................................................. 158
Capture Trigger Signal to 24-Bit Capture Register ................................................................. 179
Interrupt Request Signal from 24-Bit Compare Register ........................................................ 181
Capture Trigger Signal to 24-Bit Capture Register ................................................................. 186
Interrupt Request Signal from 24-Bit Compare Register ........................................................ 187
Capture Trigger Signal to 16-Bit Capture Register ................................................................. 193
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
Default Priority of Interrupts...................................................................................................... 215
I2C Bus Configuration................................................................................................................ 234
INTIIC Generation Timing and Wait Control ............................................................................ 270
Definition of Extension Code Bit............................................................................................... 271
Wait Time................................................................................................................................... 273
Baud Rate Generators 0 to 3 Set-up Values (when typical clocks are used) ....................... 289
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
Correspondence between Analog Input Pin and ADCRn Register
(1-buffer mode (A/D trigger select 1-buffer)) ........................................................................... 308
Correspondence between Analog Input Pin and ADCRn Register
(4-buffer mode (A/D trigger select 4-buffer)) ........................................................................... 309
Correspondence between Analog Input Pin and ADCRn Register
(scan mode (A/D trigger scan) ................................................................................................. 310
Correspondence between Analog Input Pin and ADCRn Register
(1-buffer mode (timer trigger select 1-buffer)) ......................................................................... 312
Correspondence between Analog Input Pin and ADCRn Register
(4-buffer mode (timer trigger select 4-buffer)) ......................................................................... 313
Correspondence between Analog Input Pin and ADCRn Register
(scan mode (timer trigger scan)) .............................................................................................. 314
Correspondence between Analog Input Pin and ADCRn Register
(1-buffer mode (external trigger select 1-buffer)) .................................................................... 315
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User’s Manual U11969EJ3V0UM00
LIST OF TABLES (2/2)
Table No.
Title
Page
9-8.
9-9.
Correspondence between Analog Input Pin and ADCRn Register
(4-buffer mode (external trigger select 4-buffer)) .................................................................... 317
Correspondence between Analog Input Pin and ADCRn Register
(scan mode (external trigger scan)) ......................................................................................... 318
13-1.
13-2.
Operating Status of I/O and Output Pins During Reset Period .............................................. 378
Initial Values after Reset of Each Register.............................................................................. 380
14-1.
List of Communication Systems ............................................................................................... 392
21
User’s Manual U11969EJ3V0UM00
[MEMO]
22
User’s Manual U11969EJ3V0UM00
CHAPTER 1 INTRODUCTION
The V854 is a product of NEC’s V850 Family single-chip microcontrollers for real-time control applications. This
chapter briefly outlines the V854.
1.1 General
The V854 is a 32-/16-bit single-chip microcontroller that employs the CPU core of the V850 Family of high-
performance 32-bit single-chip microcontrollers for real-time control applications, and integrates peripheral functions
such as ROM/RAM, real-time pulse unit, serial interface, A/D converter, and PWM.
The V854 is provided with multiplication instructions that are executed with a hardware multiplier, saturated
operation instructions, and bit manipulation instructions that are ideal for digital servo control applications, in addition
to the basic instructions that have a high real-time response speed and can be executed in 1 clock cycle. This
microcontroller can be employed for many applications including real-time control systems such as AV applications
including digital still cameras and camera built-in VCRs; communication applications including portable telephones
and portable information terminals. In any of these applications, the V854 demonstrates an extremely high cost
effectiveness. Especially, the real-time pulse unit that can realize VCR software servo control is provided; therefore,
the system/servo/camera control of camera built-in VCR is realized by one chip.
User’s Manual U11969EJ3V0UM00
23
CHAPTER 1 INTRODUCTION
1.2 Features
Number of instructions
: 74
Minimum instruction execution time : 30 ns (at internal 33 MHz)
General register
Instruction set
: 32 bits x 32
: Signed multiply (16 bits x 16 bits → 32 bits): 1 to 2 clocks
Saturated operation instructions (with overflow/underflow detection
function)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Memory space
: 16 Mbytes linear address space (common program/data)
Memory block division function: 2 Mbytes/block
Programmable wait function
Idle state insertion function
External bus interface
Internal memory
: 16-bit data bus (address/data multiplexed)
Bus hold function
External wait function
:
Part Number
Internal ROM
Internal RAM
4 Kbytes
µPD703006
None
µPD703008,
128 K (Mask ROM)
4 Kbytes
703008Y
µPD70F3008,
128 K (Flash memory)
4 Kbytes
70F3008Y
Interrupt/exception
: External interrupt: 22 (including NMI)
Internal interrupt : 31 sources
Exception
: 1 source
Eight levels of priorities can be set.
I/O line
: Input port: 16
I/O port : 96
Real-time pulse unit
Serial interface
: 24-bit timer/event counter: 2 ch
16-bit interval timer: 6 ch
: Asynchronous serial interface (UART)
Synchronous or clocked serial interface (CSI)
I2C bus interface (I2C) (µPD703008Y and 70F3008Y only)
UART/CSI: 1 ch
CSI: 2 ch
CSI/I2C: 1 ch
Dedicated baud rate generator: 4 ch
24
User’s Manual U11969EJ3V0UM00
CHAPTER 1 INTRODUCTION
PWM (Pulse Width Modulation)
A/D converter
: 12- to 16-bit resolution PWM: 4 ch
: 8-bit resolution A/D converter: 16 ch
Clock generator
: Multiplication function by PLL clock synthesizer (multiplication by one
or five)
2-frequency division function by external clock
: HALT/IDLE/software STOP mode
Clock output stop function
Power save function
Package
: 144-pin plastic LQFP: pin pitch: 0.5 mm
: Complete static circuit
CMOS technology
1.3 Application Fields
System/servo/camera control of camera built-in VCRs, etc.
Portable cameras such as digital still cameras, etc.
Portable telephones and portable information terminals, etc.
1.4 Ordering Information
Part number
Package
Internal ROM
None
µPD703006GJ-33-8EU
µPD703008GJ-25-×××-8EU
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
Mask ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
µPD703008YGJ-25-×××-8EU 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
µPD703008YGJ-33-×××-8EU 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
µPD70F3008GJ-16-8EUNote
µPD70F3008YGJ-16-8EUNote 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
Note
Under development
Remark ××× indicates ROM code suffix.
User’s Manual U11969EJ3V0UM00
25
CHAPTER 1 INTRODUCTION
1.5 Pin Identification (Top View)
VDD
CLKOUT
WAIT
1
108
107
106
105
104
103
102
101
100
99
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
VDD
2
3
P96/HLDRQ
P95/HLDAK
P94/ASTB
P93/DSTB/RD
P92/R/W/WRH
P91/UBEN
P90/LBEN/WRL
P67/A23
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
P66/A22
97
P65/A21
96
P64/A20
95
P63/A19
94
P62/A18
93
P61/A17
92
P60/A16
91
VSS
VSS
90
P17
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
VDD
89
P16/TI20/INTP20
P15/TO20
P14/TI1/INTP14
P13/INTP13
P12/INTP12
P11/INTP11
P10/INTP10
P07/TI0/INTP05
P06/TCLR0/INTP04
P05/INTP03
P04/INTP02
P03/INTP01
P02/INTP00
P01/TO01
P00/TO00
VDD
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VSS
Notes 1. SCL and SDA are available only for µPD703008Y and 70F3008Y.
2. Leave open when external clock is connected to X1 pin.
3. µPD703006, 703008, 703008Y
: NC
µPD70F3008, 70F3008Y : VPP (Connect to VSS via a resistor (RVPP) in normal operating mode)
4. Connect directly to VSS in the normal operation mode.
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CHAPTER 1 INTRODUCTION
Pin name
P00 to P07
P10 to P17
P20 to P26
P30 to P36
P40 to P47
P50 to P57
P60 to P67
P70 to P77
: Port0
: Port1
: Port2
: Port3
: Port4
: Port5
: Port6
: Port7
: Port8
: Port9
A16 to A23
: Address Bus
AD0 to AD15 : Address/Data Bus
ADTRG : AD Trigger Input
ANI0 to ANI15 : Analog Input
ASTB
: Address Strobe
: Analog VDD
AVDD
AVREF
: Analog Reference Voltage
: Analog VSS
P80 to P87
P90 to P96
AVSS
CKSEL
CLKOUT
CLO
: Clock Select
P100 to P103 : Port10
P110 to P117 : Port11
P120 to P127 : Port12
P130 to P137 : Port13
P140 to P147 : Port14
: Clock Output
: Clock Output (Divided)
: Power Supply for Clock Generator
: Ground for Clock Generator
: Data Strobe
CVDD
CVSS
DSTB
PLLSEL
: PLL Select
HLDAK
HLDRQ
INTP00 to
INTP05,
INTP10 to
INTP14,
INTP20 to
INTP24,
INTP30,
INTP50 to
INTP53
LBEN
: Hold Acknowledge
: Hold Request
PWM0 to PWM3 : Pulse Width Modulation
RD
: Read
: Reset
: Interrupt Request from Peripherals
RESET
RTP0 to RTP7 : Real-time Port
R/W
RXD
: Read/Write Status
: Receive Data
SCK0 to SCK3 : Serial Clock
SCL
: Serial Clock
: Serial Data
: Serial Input
: Serial Output
: Timer Clear
: Timer Input
SDA
SI0 to SI3
SO0 to SO3
TCLR0
: Lower Byte Enable
: Mode
MODE0 to
MODE2
NC
TI0, TI1,
TI20 to TI24
: No Connection
TO00, TO01, : Timer Output
TO20 to TO24
NMI
: Non-maskable Interrupt Request
TXD
UBEN
VDD
: Transmit Data
: Upper Byte Enable
: Power Supply
VPP
: Programming Power Supply
: Ground
VSS
WAIT
WRH
WRL
X1, X2
: Wait
: Write Strobe High Level Data
: Write Strobe Low Level Data
: Crystal
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CHAPTER 1 INTRODUCTION
1.6 Function Block Configuration
1.6.1 Internal block diagram
ROM
CPU
ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16 to A23
AD0 to AD15
NMI
Instruction
queue
PC
INTC
RPU
INTP00 to INTP05
INTP10 to INTP14
INTP20 to INTP24
INTP30
32-bit
barrel shifter
Note
Multiplier
INTP50 to INTP53
16 x 16 → 32
System
register
TO00, TO01
TO20 to TO24
TCLR0
BCU
HLDRQ
HLDAK
RAM
4 KB
General
register
32 bits x 32
ALU
TI0, TI1
RD
WRL
WRH
TI20 to TI24
RTP0 to RTP7
RTP
SO0/TXD
SI0/RXD
SCK0
CSI0/UART
BRG0
CKSEL
CSO
PLLSEL
A/D
converter
Port
SO1/SDA
SI1
SCK1/SCL
CSI1/I2C
CLKOUT
X1
CG
X2
MODE0 to MODE2
BRG1
CSI2
RESET
SO2
SI2
VDD
SCK2
VSS
CVDD
CVSS
VPP/NC
BRG2
CSI3
SO3
SI3
SCK3
BRG3
PWM
PWM0 to PWM3
Note µPD703006
: None
: 128 Kbytes (Mask ROM)
µPD70F3008, 70F3008Y : 128 Kbytes (Flash Memory)
µPD703008, 703008Y
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CHAPTER 1 INTRODUCTION
1.6.2 Internal units
(1) CPU
Executes almost all instruction processing such as address calculation, arithmetic/logic operation, and data
transfer in 1 clock by using a 5-stage pipeline.
Dedicated hardware devices such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)
are provided to increase the speed of processing complicated instructions.
(2) Bus control unit (BCU)
Initiates the necessary number of external bus cycles based on the physical address obtained by the CPU.
If the CPU does not issue a request to start a bus cycle when an instruction is fetched from external memory
area, it generates a prefetch address to prefetch an instruction code. The prefetched instruction code is loaded
into the internal instruction queue.
(3) Internal ROM
The µPD703008 and 703008Y incorporate mask ROM (128 Kbytes) and the µPD70F3008 and 70F3008Y
incorporate flash memory (128 Kbytes). They are each mapped starting from address 00000000H. The
µPD703006 does not contain internal ROM.
Access is enabled/disabled by the MODE0 to MODE2 pins. With the internal flash memory device, the
programming mode is specified by these two pins.
This internal ROM is accessed in 1 clock by the CPU when an instruction is fetched.
(4) Internal RAM
4 Kbytes RAM is mapped starting from address FFFFE000H. This RAM can be accessed in 1 clock by the
CPU when data is accessed.
(5) Interrupt controller (INTC)
Processes interrupt requests (NMI, INTP00 to INTP05, INTP10 to INTP14, INTP20 to INTP24, INTP30, and
INTP50 to INTP53) from the internal peripheral hardware and external sources. Eight levels of priorities can
be specified for these interrupt requests, and multiplexed processing control can be performed on an interrupt
source.
(6) Clock generator (CG)
By the internal PLL, supplies the CPU clock whose frequency is five times, one time (when internal PLL is
used), or 1/2 times (when internal PLL is not used) the frequency of the oscillator connected across the X1
and X2 pins. Input from an external clock source can also be referenced instead of using the oscillator.
(7) Real-time pulse unit (RPU)
Provides two 24-bit timer/event counter channels, six 16-bit interval timer channels, and capabilities for
measuring pulse width and generation of programmable pulse outputs.
(8) Serial interface (SIO)
The serial interface consists of 4 channels in total of asynchronous serial interfaces (UART) and synchronous
or clocked serial interfaces (CSI). One of these channels can be switched between UART and CSI, one channel
can be switched between CSI and I2C (µPD703008Y and 70F3008Y only), and the other two channels are
fixed to CSI.
UART transfers data by using the TXD and RXD pins.
CSI transfers data by using the SO, SI, and SCK pins.
I2C transfers data by using the SDA and SCL pins.
The serial clock source can be selected from the baud rate generator output and system clock.
User’s Manual U11969EJ3V0UM00
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CHAPTER 1 INTRODUCTION
(9) Ports
The ports have functions as general ports and functions as control pins as shown below.
Port
Port0
Port1
Port2
I/O
Port Function
General port
Control Function
8-bit I/O
Timer I/O, external interrupt
1-bit input,
6-bit I/O
NMI, A/D converter trigger, external interrupt
Port3
Port4
Port5
Port6
Port7
Port8
Port9
7-bit I/O
8-bit I/O
Serial interface
External address/data bus
External address bus
8-bit input
7-bit I/O
A/D converter analog input
External bus interface control signal I/O
PWM output
Port10 4-bit I/O
Port11 8-bit I/O
Port12
Timer I/O, external interrupt
Serial interface
Port13
Real time output port
—
Port14
(10) PWM (Pulse Width Modulation)
The V854 is provided with four channels of PWM signal output for which the 12- to 16-bit resolutions can be
selected. The PWM output can be used as a D/A converter output by connecting an external low pass filter.
It is suitable for controlling the actuator of motors, etc.
(11) A/D converter
This is a high speed, high resolution 8-bit A/D converter with 16 analog input pins. Converts with a sequential
conversion method.
(12) RTP
Real time output function which transfers the 8-bit data previously set to output latch with the coincidence signal
of compare register. RTP can output data to port at the accurate timing specified with timer.
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CHAPTER 2 PIN FUNCTIONS
The following table shows the names and functions of the V854’s pins. These pins can be divided by function into
port pins and other pins.
2.1 Pin Function List
(1) Port pins
(1/2)
Pin Name
P00
I/O
I/O
Function
Alternate Function
TO00
Port 0.
8-bit I/O port.
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P30
P31
P32
P33
P34
P35
P36
P40 to P47
TO01
Can be specified in input/output mode in 1-bit units.
INTP00
INTP01
INTP02
INTP03
TCLR0/INTP04
TI0/INTP05
INTP10
INTP11
INTP12
INTP13
TI1/INTP14
TO20
I/O
Port 1.
8-bit I/O port.
Can be specified in input/output mode in 1-bit units.
TI20/INTP20
–
Input
I/O
NMI
Port 2.
P20 is input-only port.
INTP30
ADTRG
INTP50
INTP51
INTP52
INTP53
SO0/TXD
SI0/RXD
SCK0
This pin operates as NMI input when valid edge is input.
Bit 0 in P2 register signifies NMI input state.
P21 to P26 are 6-bit input/output port pins.
Can be specified in input/output mode in 1-bit units.
I/O
Port 3.
7-bit I/O port.
Can be specified in input/output mode in 1-bit units.
SO1/SDA
SI1
SCK1/SCL
–
I/O
AD0 to AD7
Port 4.
8-bit I/O port.
Can be specified in input/output mode in 1-bit units.
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Alternate Function
AD8 to AD15
Pin Name
I/O
I/O
Function
Port 5.
P50 to P57
8-bit I/O port.
Can be specified in input/output mode in 1-bit units.
P60 to P67
I/O
Port 6.
A16 to A23
8-bit I/O port.
Can be specified in input/output mode in 1-bit units.
Port 7.
P70 to P77
P80 to P87
Input
Input
I/O
ANI0 to ANI7
ANI8 to ANI15
8-bit input only port.
Port 8.
8-bit input only port.
Port 9.
P90
LBEN/WRL
UBEN
7-bit I/O port.
P91
Can be specified in input/output mode in 1-bit units.
P92
R/W/WRH
DSTB/RD
ASTB
P93
P94
P95
HLDAK
HLDRQ
PWM0
P96
Port 10.
P100
P101
P102
P103
P110
P111
P112
P113
P114
P115
P116
P117
P120
P121
P122
P123
P124
P125
P126
P127
P130 to P137
I/O
I/O
4-bit I/O port.
PWM1
Can be specified in input/output mode in 1-bit units.
PWM2
PWM3
Port 11.
TO21
8-bit I/O port.
TI21/INTP21
TO22
Can be specified in input/output mode in 1-bit units.
TI22/INTP22
TO23
TI23/INTP23
TO24
TI24/INTP24
SO2
I/O
Port 12.
8-bit I/O port.
SI2
Can be specified in input/output mode in 1-bit units.
SCK2
SO3
SI3
SCK3
–
CLO
I/O
I/O
RTP0 to RTP7
Port 13.
8-bit I/O port.
Can be specified in input/output mode in 1-bit units.
P140 to P147
–
Port 14.
8-bit I/O port.
Can be specified in input/output mode in 1-bit units.
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CHAPTER 2 PIN FUNCTIONS
(2) Pins other than port pins
(1/3)
Alternate Function
P00
Pin Name
TO00
I/O
Function
Output Pulse signal output from timer 0 and 2.
TO01
TO20
TO21
TO22
TO23
TO24
TCLR0
TI0
P01
P15
P110
P112
P114
P116
Input
Input
External clear signal input to timer 0.
P06/INTP04
P07/INTP05
P14/INTP14
P16/INTP20
P111/INTP21
P113/INTP22
P115/INTP23
P117/INTP24
P02 to P05
External count clock input to timer 0, 1, and 2.
TI1
TI20
TI21
TI22
TI23
TI24
INTP00 to INTP03 Input
External capture trigger input to timer 0. Also used to input external
maskable interrupt request.
INTP04
INTP05
Input
External maskable interrupt request input.
P06/TCLR0
P07/TI0
INTP10 to INTP13 Input
P10 to P13
External capture trigger input to timer 1. Also used to input external
maskable interrupt request.
INTP14
INTP20
INTP21
INTP22
INTP23
INTP24
INTP30
Input
Input
External maskable interrupt request input.
External maskable interrupt request input.
P14/TI1
P16/TI20
P111/TI21
P113/TI22
P115/TI23
P117/TI24
P21
Input
External capture trigger input to timer 3. Also used to input external
maskable interrupt request.
INTP50 to INTP53 Input
NMI Input
External maskable interrupt request input.
Non-maskable interrupt request input.
P23 to P26
P20
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CHAPTER 2 PIN FUNCTIONS
(2/3)
Pin Name
SO0
I/O
Function
Alternate Function
Output Serial transmit data output from CSI0 to CSI3 (3-wire).
P30/TXD
P33/SDA
P120
SO1
SO2
SO3
SI0
P123
Input
Serial receive data input to CSI0 to CSI3 (3-wire).
Serial clock I/O from/to CSI0 to CSI3 (3-wire).
P31/RXD
P34
SI1
SI2
P121
SI3
P124
SCK0
SCK1
SCK2
SCK3
SDA
SCL
TXD
RXD
I/O
P32
P35/SCL
P122
P125
I/O
Serial transmit/receive data I/O from/to I2C.
Serial clock I/O from/to I2C.
P33/SO1
P35/SCK1
P30/SO0
P31/SI0
P100 to P103
P40 to P47
P50 to P57
P60 to P67
P90/WRL
P91
Output Serial transmit data output from UART.
Input Serial receive data input to UART.
PWM0 to PWM3 Output Pulse signal output from PWM.
AD0 to AD7
AD8 to AD15
A16 to A19
LBEN
I/O
16-bit multiplexed address/data bus when external memory is used.
Output Higher address bus when external memory is used.
Output Lower byte enable signal output of external data bus.
Higher byte enable signal output of external data bus.
External read/write status output.
UBEN
R/W
P92/WRH
P93/RD
P94
DSTB
External data strobe signal output.
ASTB
External address strobe signal output.
HLDAK
Output Bus hold acknowledge output.
P95
HLDRQ
WRL
Input
Bus hold request input.
P96
Output Lower byte write strobe signal output to external data bus.
Higher byte write strobe signal output to external data bus.
Output Read strobe signal output to external data bus.
P90/LBEN
P92/R/W
P93/DSTB
P70 to P77
P80 to P87
P130 to P137
P127
WRH
RD
ANI0 to ANI7
ANI8 to ANI15
RTP0 to RTP7
CLO
Input
Analog input to A/D converter.
Output Real time output port.
Output System clock output (with frequency division function).
CKSEL
Input
Input
Input to specify clock generator operation mode.
Input to specify the number of PLL multiplication.
–
PLLSEL
CLKOUT
–
Output System clock output.
–
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CHAPTER 2 PIN FUNCTIONS
(3/3)
Pin Name
WAIT
I/O
Input
Input
Input
Input
–
Function
Control signal input inserting wait state to bus cycle.
Specifies operation mode.
Alternate Function
–
MODE0 to MODE2
–
RESET
X1
System reset input.
–
System clock oscillator connecting pins. Supply external clock to X1.
–
X2
–
ADTRG
AVREF
AVDD
AVSS
CVDD
CVSS
VDD
Input
Input
–
A/D converter external trigger input.
Reference voltage input for A/D converter.
Positive power supply for A/D converter.
Ground for A/D converter.
P22
–
–
–
–
–
Positive power supply for clock generator.
Ground for clock generator.
–
–
–
–
Positive power supply.
–
VSS
–
Ground.
–
VPP
–
High voltage applying pin for program write/verify. (µPD70F3008, 70F3008Y only)
Internally unconnected (µPD703006, 703008, 703008Y only)
–
NC
–
–
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CHAPTER 2 PIN FUNCTIONS
2.2 Pin Status
The operating status of each pin in each operation mode is as follows:
Operating Status
Software
STOP
Mode
IDLE
Mode
Bus
Hold
Idle
State
HALT
Mode
Reset
Pin
AD0 to AD15
A16 to A23
LBEN, UBEN
R/W
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Operates
L
Hi-Z
Hi-Z
Hi-Z
RetainedNote 1
Retained
Hi-Z
RetainedNote 1
Retained
Hi-Z
H
H
DSTB, WRL, WRH, RD
ASTB
Hi-Z
H
H
Hi-Z
H
H
HLDRQ
–
Operates
Operates
–
Operates
Operates
–
HLDAK
Hi-Z
–
Hi-Z
–
Hi-Z
–
WAIT
–
CLKOUT
OperatesNote 2
L
–
OperatesNote 2 OperatesNote 2 OperatesNote 2
Hi-Z
: high-impedance
Retained : Retains status in external bus cycle immediately before
L
H
–
: low-level output
: high-level output
: input not sampled
Notes 1. Undefined immediately after the bus hold end.
2. Low-level output in single chip mode 1, flash memory programming mode, and clock output inhibit mode.
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2.3 Pin Function
(1) P00 to P07 (Port0) ... 3-state I/O
These pins constitute an 8-bit I/O port, port 0. They also serves as control signal pins.
P00 to P07 function not only as I/O port pins, but also as the I/O pins of the real-time pulse unit (RPU) and
external interrupt request input pins. Each bit of port 0 can be specified in the port or control mode, by using
port 0 mode control register (PMC0).
(a) Port mode
P00 to P07 can be set in the input or output mode in 1-bit units by using port 0 mode register (PM0).
(b) Control mode
P00 to P07 can be set in the port or control mode in 1-bit units by the PMC0 register.
(i)
TO00, TO01 (Timer Output) ... output
These are pulse signals output pins for timer 0.
(ii) TCLR0 (Timer Clear) ... input
This pin inputs an external clear signal to timer 0.
(iii) TI0 (Timer Input) ... input
This pin inputs an external count clock to timer 0.
(iv) INTP00 to INTP05 (Interrupt Request from Peripherals) ... input
These pins are the external interrupt request input pins.
(2) P10 to P17 (Port 1) ... 3-state I/O
These pins constitute an 8-bit I/O port, port 1, which can be set in the input or output mode in 1-bit units.
P10 to P17 function as ports, as well as RPU inputs/outputs and external interrupt request inputs. In the
operation mode, port control can be selected in 1-bit units, and is specified by the port 1 mode control register
(PMC1).
(a) Port mode
P10 to P17 can be set in the input or output mode in 1-bit units by using port 1 mode register (PM1).
(b) Control mode
P10 to P17 can be set in the port or control mode in 1-bit units by the PMC1 register.
(i)
TO20 (Timer Output) ... output
This is pulse signal output pin for timer 2.
(ii) TI1, TI20 (Timer Input) ... input
These pins are external count clock input pins of timer 1 and timer 2.
(iii) INTP10 to INTP14 (Interrupt Request from Peripherals) ... input
These pins are the external interrupt request input pins and capture trigger input pins of timer 1.
(iv) INTP20 (Interrupt Request from Peripherals) ... input
This pin is the external interrupt request input pin.
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CHAPTER 2 PIN FUNCTIONS
(3) P20 to P26 (Port 2) ... 3-state I/O
These pins constitute an I/O port, port 2, which can be set in the input or output mode in 1-bit units, except
P20, which is an input only pin. These pins function not only as port pins but also as NMI input, external interrupt
request input, and A/D converter external trigger.
Each bit of this port can be specified in the port or control mode by using port 2 mode control register (PMC2).
(a) Port mode
P21 to P26 can be set in the input or output mode in 1-bit units by port 2 mode register (PM2).
P20 is the input-only port and operates as NMI input when a valid edge is input.
(b) Control mode
P21 to P26 can be set in the port or control mode in 1-bit units by the PMC2 register.
P20 is fixed to control mode.
(i)
NMI (Non-maskable Interrupt Request) ... input
This is an input pin for the non-maskable interrupt request signal.
(ii) INTP30, INTP50 to INTP53 (Interrupt Request from Peripherals) ... input
These pins are the external interrupt request input pins.
(iii) ADTRG (AD Trigger Input) ... input
This pin is external trigger input pin of A/D converter.
(4) P30 to P36 (Port 3) ... 3-state I/O
These pins constitute an 7-bit I/O port, port 3. They also function as control signal pins. P30 to P36 function
not only as I/O port pins but also as serial interface I/O pins in the control mode.
Each bit of port 3 can be specified in the port or control mode in 1-bit units by using port 3 mode control register
(PMC3).
(a) Port mode
P30 to P36 can be set in the input or output mode in 1-bit units by port 3 mode register (PM3).
(b) Control mode
P30 to P36 can be set in the port or control mode in 1-bit units by the PMC3 register.
(i)
TXD (Transmit Data) ... output
This is a serial transmit data output pin for the UART.
When transmission is disabled : High impedance
When transmission is enabled : High level
(ii) RXD (Receive Data) ... input
This is a serial receive data input pin for the UART.
(iii) SDA (Serial Data)...I/O
This pin is I2C serial receive data I/O pin. Since this pin is open drain output, connect external pull-
up resistor. (µPD703008Y and 70F3008Y only)
(iv) SCL (Serial Clock) ... I/O
This pin is I2C serial clock I/O pin. Since this pin is the open-drain output, connect external pull-
up resistor. (µPD703008Y and 70F3008Y only)
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(v) SO0, SO1 (Serial Output 0, 1) ... output
These are serial transmit data output pin for the CSI.
Since SO1 is open drain output, connect external pull-up resistor.
(vi) SI0, SI1 (Serial Input 0, 1) ... input
These are serial receive data input pin for the CSI.
(vii) SCK0, SCK1 (Serial Clock 0, 1) ... 3-state I/O
These pins input/output the serial clock of CSI.
Since SCK1 is open drain output, connect external pull-up resistor to output.
(5) P40 to P47 (Port 4) ... 3-state I/O
These pins constitute an 8-bit I/O port, port 4. They also form a portion of the address/data bus connected
to external memory.
P40 to P47 function not only as I/O port pins but also as time sharing address/data bus pins (AD0 to AD7)
in the control mode (external expansion mode) when an external memory is connected.
Operation mode is specified by the mode specification pin (MODE) and the memory expansion mode register
(MM).
(a) Port mode
P40 to P47 can be set in the input or output port mode in 1-bit units by using port 4 mode register (PM4).
(b) Control mode (External Expansion Mode)
P40 to P47 can be specified as AD0 to AD7 by using the MODE pin and MM register.
(i)
AD0 to AD7 (Address/Data 0 to 7) ... 3-state I/O
These pins constitute a multiplexed address/data bus when the external memory is accessed. They
function as the A0 to A7 output pins of a 24-bit address in the address timing (T1 state), and as the
lower 8-bit data I/O bus pins of 16-bit data in the data timing (T2, TW, T3).
The output status of these pins changes in synchronization with the rising edge of the clock in each
state of the bus cycle. AD0 to AD7 go into a high-impedance state in the idle state (TI).
Since SO1 is open drain output, connect external pull-up resistor to output.
(6) P50 to P57 (Port 5) ... 3-state I/O
These pins constitute an 8-bit I/O port, port 5. They also form a portion of the address/data bus connected
to external memory.
P50 to P57 function not only as I/O port pins but also as multiplexed address/data bus pins (AD8 to AD15)
in the control mode (external expansion mode) when an external memory is connected.
Operation mode is specified by the mode specification pin (MODE) and memory expansion mode register
(MM).
(a) Port mode
P50 to P57 can be set in the input or output port mode in 1-bit units by using port 5 mode register (PM5).
(b) Control mode (External Expansion Mode)
P50 to P57 can be specified as AD8 to AD15 by using the MODE pin and MM register.
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(i)
AD8 to AD15 (Address/Data 8 to 15) ... 3-state I/O
These pins constitute a multiplexed address/data bus when the external memory is accessed. They
function as the A8 to A15 output pins of a 24-bit address in the address timing (T1 state), and as
the higher 8-bit data I/O bus pins of 16-bit data in the data timing (T2, TW, T3).
The output status of these pins changes in synchronization with the rising of the clock in each state
of the bus cycle. AD8 to AD15 go into a high-impedance state in the idle state (TI).
(7) P60 to P67 (Port 6) ... 3-state I/O
These pins constitute an 8-bit I/O port, port 6. They also form a portion of the address/data bus connected
to external memory.
P60 to P67 function not only as I/O port pins but also as address bus pins (A16 to A23) in the control mode
(external expansion mode) when an external memory is connected. This port can be set in the port or control
mode in 2-bit units by using mode specification pin (MODE) and memory expansion mode register (MM).
(a) Port mode
P60 to P67 can be set in the input or output port mode in 1-bit units by using port 6 mode register (PM6).
(b) Control mode (External Expansion Mode)
P60 to P67 can be specified as A16 to A23 by using the MODE pin and MM register.
(i)
A16 to A23 (Address 16 to 23) ... output
These pins constitute the higher 8 bits of a 24-bit address bus when the external memory is
accessed.
The output status of these pins changes in synchronization with the rising edge of the clock in the
T1 state. During the idle state (TI), the address of the bus cycle immediately before entering the
idle state is retained.
(8) P70 to P77 (Port 7), P80 to P87 (Port 8) ... input
Port 7 and port 8 each are an 8-bit input-only port whose pins are all fixed to input.
P70 to P77 and P80 to P87 function as input ports, as well as A/D converter analog inputs in the control mode.
However, the input port and analog input pin cannot be switched.
(a) Port mode
P70 to P77 and P80 to P87 are dedicated input ports.
(b) Control mode
P70 to P77 also function as ANI0 to ANI7 pins and P80 to P87 also function as ANI8 to ANI15 pins, and
cannot be switched.
(i)
ANI0 to ANI15 (Analog Input) ... input
These pins are analog input pins to A/D converter.
To prevent erroneous operation due to noise, connect a capacitor between these pins and AVSS.
Make sure that voltage other than the range of AVSS and AVREF should not be applied to the input
pin used for A/D converter input. If there should be the possibility that noise whose voltage is AVREF
or more or noise whose voltage is AVSS or less is generated, clamp the voltage using a diode with
small VF.
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(9) P90 to P96 (Port 9) ... 3-state I/O
These pins constitute a 7-bit I/O port, port 9, and are also used to output control signals.
P90 to P96 function not only as I/O port pins but also as control signal output pins and bus hold control signal
output pins in the control mode (external expansion mode) when an external memory is used.
If port 9 is accessed in 8-bit units, the higher 1-bit is ignored if the access is write, and undefined if the access
is read.
Operation mode is specified by the mode specification pin (MODE) and memory expansion mode register
(MM).
(a) Port mode
P90 to P96 can be set in the input or output port mode in 1-bit units by using port 9 mode register (PM9).
(b) Control mode (External Expansion Mode)
P90 to P96 can be used to output control signals when so specified by the MODE pin and MM register
when an external memory is used.
(i)
LBEN (Lower Byte Enable) ... output
This is the lower byte enable signal of the 16-bit external data bus.
This signal changes in synchronization with the rising edge of the clock in the T1 state of the bus
cycle. The status of the bus signal remains unchanged in the idle state (TI).
(ii) UBEN (Upper Byte Enable) ... output
This is the upper byte enable signal of the 16-bit external data bus. It becomes active (low) in byte
access to an odd address. It becomes inactive (high) in byte access to an even address.
This signal changes in synchronization with the rising of the clock in the T1 state of the bus cycle.
The status of the bus signal remains unchanged in the idle state (TI).
Access
UBEN
LBEN
A0
0
Word Access
Half-word Access
Byte Access Even address
Odd address
0
0
1
0
0
0
0
1
0
0
1
(iii) R/W (Read/Write Status) ... output
This is a status signal output pin that indicates whether the bus cycle for external access is a read
or write cycle. It goes high in the read cycle and low in the write cycle.
This signal changes in synchronization with the rising edge of the clock in the T1 state of the bus
cycle. It goes high in the idle state (TI).
(iv) DSTB (Data Strobe) ... output
This is the access strobe signal of the external data bus.
It becomes active (low) in the T2 or TW state of the bus cycle, and becomes inactive (high) in the
idle state (TI).
(v) ASTB (Address Strobe) ... output
This is the latch strobe signal of the external address bus.
It becomes active (low) in synchronization with the falling edge of the clock in the T1 state of the
bus cycle, and becomes inactive (high) in synchronization with the falling edge of the clock in the
T3 state. It goes high in the idle state (TI).
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(vi) HLDAK (Hold Acknowledge) ... output
This is an acknowledge signal output pin that indicates that the V854 has set the address bus, data
bus, and control bus in the high-impedance state in response to a bus hold request.
As long as this signal is active, the address bus, data bus, and control bus remain in a high impedance
state.
(vii) HLDRQ (Hold Request) ... input
This input pin is used by an external device to request that the V854 relinquish control of the address
bus, data bus, and control bus. This pin can be input asynchronously with CLKOUT. When this
signal becomes active, the V854 sets the address bus, data bus, and control bus in the high-
impedance state, after the current bus cycle completes. If there is no current bus activity, the address
bus, data bus, and control bus are immediately set to high-impedance. HLDAK is then made active
and the bus and control lines are released.
(viii) WRL (Write Strobe Low Byte Data) ... output
This is a write strobe signal output pin for the lower byte of the external 16-bit data bus.
(ix) WRH (Write Strobe High Byte Data) ... output
This is a write strobe signal output pin for the upper byte of the external 16-bit data bus.
(x) RD (Read Strobe)... output
This is a read strobe signal output pin for the external 16-bit data bus.
(10) P100 to P103 (Port 10) ... 3-state I/O
Port 10 is a 4-bit I/O port that can be set in the input or output mode in 1-bit units.
In addition to the function as a port, the pins constituting port 10 are used as output of PWM in the control
mode.
If port 10 is accessed in 8-bit units, the higher 4-bit is ignored if the access is write, and undefined if the access
is read.
(a) Port mode
P100 to P103 can be set in the input or output mode, in 1-bit units, by the port 10 mode register (PM10).
(b) Control mode
P100 to P103 function as output pins for PWM control signals when the function is enabled by the port
10 mode control register (PMC10).
(i)
PWM0 to PWM 3 (Pulse Width Modulation 0 to 3) ... output
These are pulse signals output pins for the PWM.
(11) P110 to P117 (Port 11) ... 3-state I/O
Port 11 is an 8-bit I/O port that can be set in the input or output mode in 1-bit units. In addition to the function
as a port, the pins constituting port 11 are used as input/output of RPU or external interrupt request input.
(a) Port mode
P110 to P117 can be set in the input or output mode, in 1-bit units, by the port 11 mode register (PM11).
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(b) Control mode
P110 to P117 function as input and output pins for timer 2 when the function is enabled by the port 11
mode control register (PMC11).
(i)
TO21 to TO24 (Timer Output) ... output
These are pulse signals output pins for timer 2.
(ii) TI21 to TI24 (Timer Input) ... input
This pin inputs an external counter clock to timer 2.
(iii) INTP21 to INTP24 (Interrupt Request from Peripherals) ... input
These pins are the external interrupt request input pins.
(12) P120 to P127 (Port 12) ... 3-state I/O
Port 12 is an 8-bit I/O port that can be set in the input or output mode in 1-bit units. In addition to the function
as a port, the pins constituting port 12 are used as serial interface I/O in the control mode.
(a) Port mode
P120 to P127 can be set in the input or output mode, in 1-bit units, by the port 12 mode register (PM12).
(b) Control mode
P120 to P127 function as input and output of serial interface control signal and output of clock signal by
setting of port 12 mode control register (PMC12). However, P126 pin functions only as a port.
(i)
SO2, SO3 (Serial Output 2, 3) ... output
These are serial transmit data output pins for the CSI.
(ii) SI2, SI3 (Serial Input 2, 3) ... input
These are serial receive data input pins for the CSI.
(iii) SCK2, SCK3 (Serial Clock 2, 3) ... 3-state I/O
These are the serial clock I/O pins of CSI.
(iv) CLO (Clock Output (Divided)) ... output
This is an output pin for the system clock (with frequency division function).
(13) P130 to P137 (Port 13) ... 3-state I/O
Port 13 is an 8-bit I/O port that can be set in the input or output mode in 1-bit units. In addition to the function
as a port, it is used as real-time output port in the control mode.
(a) Port mode
P130 to P137 can be set in the input or output mode, in 1-bit units, by the port 13 mode register (PM13).
(b) Control mode
P130 to P137 function as real-time output port by setting of port 13 mode control register (PMC13).
(i)
RTP0 to RTP7 (Real-time Port 0 to 7) ... output
These pins are real-time output port.
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(14) P140 to P147 (Port 14) ... 3-state I/O
Port 14 is an 8-bit I/O port that can be set in the input or output mode in 1-bit units. Port 14 functions only
as a port.
(15) CKSEL (Clock Select) ... input
This is the input pin that specifies the operation mode of the clock generation circuit. The input value of this
pin cannot be changed during normal operation.
CKSEL
Operation Mode
0
1
PLL mode
Direct mode
(16) PLLSEL (PLL Select) ... input
This is the input pin that specifies the number of PLL multiplication in the PLL mode (CKSEL = 0). The input
value of this pin cannot be changed during normal operation.
This pin has no function in the direct mode (CKSEL = 1) and should be treated as an unused pin.
PLLSEL
PLL Multiplication
Multiplication by 1
Multiplication by 5
0
1
(17) CLKOUT (Clock Output) ... output
This pin outputs the system clock, even during reset in the ROM-less mode. In the single-chip mode 1, the
CLKOUT signal is not output until the PSC register is set (low level output). However, in the single-chip mode
2, the CKOUT signal is output.
(18) WAIT (Wait) ... input
This control signal input pin inserts a data wait state to the bus cycle, and can be activated asynchronously
to CLKOUT. This pin is sampled at the falling edge of the clock in the T2 and TW states of the bus cycle.
If the set/hold time for the sampling timing is not satisfied, the wait state may not be inserted.
(19) MODE0 to MODE2 (Mode 0 to 2) ... input
These pins specify the operation mode of the V854. Operation modes are roughly classified as normal
operation mode and flash memory programming mode. Normal operation modes are further classified as
single-chip mode and ROM-less mode. The input value of these pins cannot be changed during normal
operation. For details, refer to 3.3 Operation Modes.
(a) µPD703006
MODE2
MODE1
MODE0
Operation Mode
ROM-less mode 1
ROM-less mode 2
Normal operation
mode
0
0
0
0
0
1
Other than above
Setting prohibited
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(b) µPD703008, 703008Y
MODE2
0
MODE1
0
MODE0
Operation Mode
0
1
0
1
ROM-less mode 1
Normal operation
mode
0
0
0
0
1
1
ROM-less mode 2
Single-chip mode 1
Single-chip mode 2
Other than above
Setting prohibited
(c) µPD70F3008, 70F3008Y
MODE2
MODE1
MODE0
Operation Mode
0
0
0
0
0
1
ROM-less mode 1
ROM-less mode 2
Single-chip mode 1
Single-chip mode 2
Normal operation
mode
0
0
1
1
1
1
0
1
1
Flash memory programming mode
Setting prohibited
Other than above
(20) RESET (Reset) ... input
The RESET signal is an asynchronous input signal. A valid low-level signal on the RESET pin initiates a system
reset, regardless of the clock operation. In addition to normal system initialization/start functions, the RESET
signal is also used for exiting processor power save modes (HALT, IDLE, or STOP).
(21) X1, X2 (Crystal) ... input
An oscillator for internal system clock generation is connected across these pins.
An external clock source can also be referenced by connecting the external clock input to the X1 pin and leaving
the X2 pin open.
(22) CVDD (Power Supply for Clock Generator)
This pin supplies positive power to the clock generator.
(23) CVSS (Ground for Clock Generator)
This is the ground pin of the clock generator.
(24) VDD (Power Supply)
This pin supplies positive power. Connect all the VDD pins to a positive power supply.
(25) VSS (Ground)
This is a ground pin. Connect all the VSS pins to ground.
(26) AVDD (Analog VDD)
Analog power supply pin for A/D converter.
(27) AVSS (Analog VSS)
Ground pin for A/D converter.
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(28) AVREF (Analog Reference Voltage) ... input
This is a reference voltage input pin for the A/D converter.
(29) VPP (Programming Power Supply)
This pin supplies positive power for the PROM mode.
This is for µPD70F3008 or 70F3008Y.
(30) NC (No Connection)
This pin is not connected internally.
This is for the µPD703006, 703008, and 703008Y.
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2.4 Pin I/O Circuit Type and Connection of Unused Pins
When connecting to VDD or VSS via resistor, it is recommended to use 1 to 10-kΩ resistor.
Pin
I/O Circuit Type
Recommended Connection
P00/TO00, P01/TO01
5
Independently connect to VDD or VSS via resistor.
P02/INTP00 to P05/INTP03,
5-K
P06/TCLR0/INTP04, P07/TI0/INTP05
P10/INTP10 to P13/INTP13,
P14/TI1/INTP14, P16/TI20/INTP20
P15/TO20, P17
P20/NMI
5
2
Connect directly to VSS.
P21/INTP30, P22/ADTRG,
P23/INTP50 to P26/INTP53
5-K
Independently connect to VDD or VSS via resistor.
P30/TXD/SO0
5
5-K
13-G
5
P31/RXD/SI0, P32/SCK0, P34/SI1
P33/SO1/SDA, P35/SCK1/SCL
P36
P40/AD0 to P47/AD7
P50/AD8 to P57/AD15
P60/A16 to P67/A23
P70/ANI0 to P77/ANI7
P80/ANI8 to P87/ANI15
5
Input state: Independently connect to VDD or VSS via resistor.
Output state: Leave open.
Connect directly to VSS.
9
5
P90/LBEN/WRL, P91/UBEN,
P92/R/W/WRH, P93/DSTB/RD, P94/ASTB,
P95/HLDAK, P96/HLDRQ
Input state: Independently connect to VDD or VSS via resistor.
Output state: Leave open.
P100/PWM0 to P103/PWM3
5
Independently connect to VDD or VSS via resistor.
P110/TO21, P112/TO22, P114/TO23,
P116/TO24
P111/TI21/INTP21, P113/TI22/INTP22,
P115/TI23/INTP23, P117/TI24/INTP24
5-K
P120/SO2
5
5-K
5
P121/SI2, P122/SCK2
P123/SO3
P124/SI3, P125/SCK3
P126, P127/CLO
P130/RTP0 to P137/RTP7
P140 to P147
WAIT
5-K
5
1
3
2
Connect directly to VDD.
CLKOUT
Leave open.
MODE0 to MODE2
RESET
–
AVREF, AVSS, CVSS
AVDD, CVDD
–
–
1
Connect directly to VSS.
Connect directly to VDD.
Connect directly to VDD or VSS.
PLLSEL
CKSEL
VPP/NC
–
Connect to VSS via resistor (RVPP).
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2.5 I/O Circuits of Pins
Type 5-K
data
Type 1
VDD
P-ch
VDD
IN/OUT
P-ch
IN
output
disable
N-ch
N-ch
input
enable
Type 2
Type 9
P-ch
comparator
+
–
IN
IN
N-ch
VREF (threshold voltage)
input enable
Schmitt trigger input with hysteresis characteristics
Type 3
Type 13-G
data
VDD
IN/OUT
P-ch
OUT
output
N-ch
disable
N-ch
input
enable
Type 5
VDD
P-ch
data
IN/OUT
output
disable
N-ch
input
enable
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The CPU of the V854 is based on the RISC architecture and executes most instructions in one clock cycle by using
a 5-stage pipeline.
3.1 Features
Minimum instruction cycle: 30 ns (at internal 33-MHz operation)
Address space: 16 Mbytes linear
General registers: Thirty-two 32-bit registers
Internal 32-bit architecture
Five-stage pipeline control
Multiplication/division instructions
Saturated operation instructions
Single-clock 32-bit shift instruction
Long/short instruction format
Four types of bit manipulation instructions
• Set
• Clear
• Not
• Test
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3.2 CPU Register Set
The registers of the V854 can be classified into two categories: a general-purpose program register set and a
dedicated system register set. All the registers are 32 bits wide. For details, refer to V850 Family User’s Manual
Architecture.
Program register set
System register set
31
0
31
0
0
r0
Zero Register
EIPC
Exception/Interrupt PC
r1
Reserved for Address Generation
Interrupt Stack Pointer
Stack Pointer (SP)
EIPSW
Exception/Interrupt PSW
r2
r3
31
r4
Global Pointer (GP)
Text Pointer (TP)
FEPC
Fatal Error PC
r5
FEPSW
Fatal Error PSW
r6
r7
31
ECR
0
0
r8
Exception Cause Register
Program Status Word
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
31
PSW
Element Pointer (EP)
Link Pointer (LP)
31
PC
0
Program Counter
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3.2.1 Program register set
The program register set includes general registers and a program counter.
(1) General registers
Thirty-two general registers, r0 to r31, are available. Any of these registers can be used as a data variable
or address variable.
However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers.
Also, r1 to r5 and r31 are implicitly used by the assembler and C compiler. Therefore, before using these
registers, their contents must be saved so that they are not lost. The contents must be restored to the registers
after the registers have been used.
Table 3-1. Program Registers
Name
r0
Usage
Zero register
Operation
Always holds 0
r1
Assembler-reserved register
Interrupt stack pointer
Stack pointer
Working register for generating immediate
Stack pointer for interrupt handler
r2
r3
Used to generate stack frame when function is called
Used to access global variable in data area
Register to indicate the start of the text areaNote
Address/data variable registers
r4
Global pointer
Text pointer
r5
r6 to r29
r30
r31
PC
–
Element pointer
Link pointer
Base pointer register when memory is accessed
Used by compiler when calling function
Program counter
Holds instruction address during program execution
Note Area in which program code is mapped.
(2) Program counter
This register holds the address of the instruction under execution. The lower 24 bits of this register are valid,
and bits 31 to 24 are fixed to 0. If a carry occurs from bit 23 to 24, it is ignored.
Bit 0 is fixed to 0, and branching to an odd address cannot be performed.
Figure 3-1. Program Counter (PC)
31
2423
1 0
0
After reset
00000000H
PC
Fixed to 0
Instruction address under execution
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3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
Table 3-2. System Register Numbers
System Register Name
EIPC
No.
0
Operation
Usage
Status saving registers during
interrupt
TheseregisterssavethePCandPSWwhenanexception
or interrupt occurs. Because only one set of these
registers is available, their contents must be saved when
multiple interrupts are enabled.
EIPSW
1
Status saving registers for NMI
Interrupt source register
FEPC
FEPSW
ECR
2
3
4
These registers save PC and PSW when NMI occurs.
If exception, maskable interrupt, or NMI occurs, this
register will contain information referencing the interrupt
source. The high-order 16 bits of this register are called
FECC, to which exception code of NMI is set. The low-
order 16 bits are called EICC, to which exception code
of exception/interrupt is set (refer to Figure 3-2).
PSW
5
Program status word
Program status word is collection flags that indicate
program status (instruction execution result) and CPU
status (refer to Figure 3-3).
Reserved
6 to 31
To read/write these system registers, specify a system register number indicated by the system register load/store
instruction (LDSR or STSR instruction).
Figure 3-2. Interrupt Source Register (ECR)
31
1615
0
0
After reset
00000000H
ECR
FECC
EICC
Bit Position
31 to 16
Bit Name
Function
FECC
Fatal Error Cause Code
Exception code of NMI. (For exception code, refer to Table 5-1.)
15 to 0
EICC
Exception/Interrupt Cause Code
Exception code of exception/interrupt.
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Figure 3-3. Program Status Word (PSW)
31
8 7 6 5 4 3 2 1 0
After reset
00000020H
PSW
RFU
NP EP ID SAT CY OV S Z
Bit Position
31 to 8
7
Bit Name
RFU
Function
Reserved field (fixed to 0).
NMI Pending
NP
Indicates that NMI processing is in progress. This flag is set when NMI is accepted,
and disables multiple interrupts.
6
EP
Exception Pending
Indicates that trap processing is in progress. This flag is set when an exception
occurs. Interrupt request is accepted even if this flag is set.
5
4
ID
Interrupt Disable
Indicates that accepting maskable interrupt request is disabled.
SAT
Saturated Math
This flag is set if result of executing saturated operation instruction overflows (if
overflow does not occur, value of previous operation is held).
3
2
CY
OV
Carry
This flag is set if carry or borrow occurs as result of operation (if carry or borrow
does not occur, it is reset).
Overflow
This flag is set if overflow occurs during operation (if overflow does not occur, it
is reset).
1
0
S
Z
Sign
This flag is set if result of operation is negative. It is reset if result is positive.
Zero
This flag is set if result of operation is zero (if result is not zero, it is reset).
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3.3 Operation Modes
3.3.1 Operation modes
The V854 has the following operations modes. These modes are selected by the MODE pin (n = 0 to 2).
(1) Normal operation modes
(a) Single-chip mode (µPD703008, 70F3008, 703008Y, 70F3008Y only)
After the system has been released from the reset status, the pins related to the bus interface are set
for port mode, execution branches to the reset entry address of the internal ROM, and instruction
processing is started. However, access to external memory and peripheral devices can be enabled by
setting in the external memory expansion mode register by instruction (MM: refer to 3.4.6 (1)).
CLKOUT signal output is disabled when reset in the single-chip mode 1. However, it is input in the single-
chip mode 2.
(b) ROM-less mode
After the system has been released from the reset status, the pins related to bus interface are set for control
mode, execution branches to the reset address of external memory, and instruction processing is started.
Instruction fetch and data access to internal ROM are disabled.
UBEN, LBEN, R/W, and DSTB signal are output when reset in the ROM-less mode. UBEN, WRL, WRH,
and RD signal are output in the ROM-less mode 2.
(2) Flash memory programming mode (µPD70F3008, 70F3008Y only)
This mode is provided only to on-chip flash memory model. If flash memory write voltage (7.8 V) is input to
VPP pin, the program operation to internal flash memory by flash writer is possible.
3.3.2 Specifying operation mode
The operation mode of the V854 is specified depending on the status of the MODE pin. Set these pins in the
application system (n = 0 to 2).
If the setting is changed during operation, the operation is not guaranteed.
(a) µPD703006
MODE2
MODE1
MODE0
Operation Mode
ROM-less mode 1
ROM-less mode 2
Normal operation
mode
0
0
0
0
1
1
Other than above
Setting prohibited
(b) µPD703008, 703008Y
MODE2
MODE1
MODE0
Operation Mode
Normal operation
mode
0
0
0
0
0
0
1
1
0
1
0
1
ROM-less mode 1
ROM-less mode 2
Single-chip mode 1
Single-chip mode 2
Other than above
Setting prohibited
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(c) µPD70F3008, 70F3008Y
Pin Status
MODE2 MODE1
Operation Mode
VPP
MODE0
Normal operation
mode
0 V
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
ROM-less mode 1
ROM-less mode 2
Single-chip mode 1
Single-chip mode 2
0 V
0 V
0 V
7.8 V
Flash memory programming mode
Setting prohibited
Other than above
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3.4 Address Space
3.4.1 CPU address space
The CPU of the V854 is of 32-bit architecture and supports up to 4 Gbytes of linear address space (data space)
during operand addressing (data access). When referencing instruction addresses, a linear address space (program
space) of up to 16 Mbytes is supported.
Figure 3-4 shows the CPU address space.
Figure 3-4. CPU Address Space
CPU address space
FFFFFFFFH
Data area
(4-Gbyte linear)
01000000H
00FFFFFFH
Program area
(16-Mbyte linear)
00000000H
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3.4.2 Image (Virtual Address Space)
The core CPU supports 4 Gbytes of “virtual” addressing space, or 256 memory blocks, each containing 16-Mbyte
memory locations. In actuality, the same 16-Mbyte block is accessed regardless of the values of bits 31 to 24 of the
CPU address. Figure 3-5 shows the image of the virtual addressing space.
Because the higher 8 bits of a 32-bit CPU address are ignored and the CPU address is only seen as a 24-bit external
physical address, the physical location XX000000H is equally referenced by multiple address values 00000000H,
010000000H, 02000000H... through FF000000H.
Figure 3-5. Image on Address Space
CPU address space
FFFFFFFFH
Image
FF000000H
FEFFFFFFH
Image
Physical address space
XXFFFFFFH
XX000000H
FE000000H
FDFFFFFFH
Peripheral I/O
Internal RAM
Image
Image
External memory
Internal ROM
02000000H
01FFFFFFH
01000000H
00FFFFFFH
Image
00000000H
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3.4.3 Wrap-around of CPU address space
(1) Program space
Of the 32 bits of the PC (program counter), the higher 8 bits are set to “0”, and only the lower 24 bits are valid.
Even if a carry or borrow occurs from bit 23 to bit 24 as a result of branch address calculation, the higher 8
bits ignore the carry or borrow and remain “0”.
Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address
00FFFFFFH are contiguous addresses. The above-mentioned state in which the lower-limit and the upper-
limit addresses of the memory space are contiguous addresses is called wraparound.
Caution
No instruction can be fetched from the 4-Kbyte area of 00FFF000H to 00FFFFFFH because
this area is defined as peripheral I/O area. Therefore, do not execute any branch operation
instructions in which the destination address will reside in any part of this area.
Program space
00FFFFFEH
00FFFFFFH
00000000H
00000001H
(+) direction
(–) direction
Program space
(2) Data space
The result of operand address calculation that exceeds 32 bits is ignored.
Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address
FFFFFFFFH are contiguous addresses, and the data space is wrapped around at the boundary of these
addresses.
Data space
FFFFFFFEH
FFFFFFFFH
00000000H
00000001H
(+) direction
(–) direction
Data space
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3.4.4 Memory map
The V854 reserves areas as shown below. Each mode is specified by using the MODEn pin at reset (n = 0 to
2).
Single-chip modeNote
Peripheral I/O area
Internal RAM area
Single-chip modeNote
(external expansion mode)
ROM-less mode
Peripheral I/O area
Internal RAM area
XXFFFFFFH
Peripheral I/O area
Internal RAM area
4 KB
4 KB
XXFFF000H
XXFFEFFFH
XXFFE000H
XXFFDFFFH
(access prohibited)
External memory
area
External memory
area
16 MB
XX100000H
XX0FFFFFH
Internal
Internal
ROM area
1 MB
ROM area
XX000000H
Note µPD703008, 70F3008, 703008Y, 70F3008Y only.
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3.4.5 Area
(1) Internal ROM area
A 1-Mbyte area corresponding to addresses 000000H to 0FFFFFH is reserved for the internal ROM area. The
V854 is provided with physical internal ROM as follows:
Caution
Internal ROM products are µPD703008, 70F3008, 703008Y and 70F3008Y only.
• Physical internal ROM: 000000H to 01FFFFH (128 Kbytes)
The image of 000000H to 01FFFFH is seen in the rest of the area (020000H to 0FFFFFH).
XX0FFFFFH
Image
XX0E0000H
XX0DFFFFH
Physical internal ROM
01FFFFH
Internal ROM
XX040000H
XX03FFFFH
Interrupt/exception table
000000H
Image
Image
XX020000H
XX01FFFFH
XX000000H
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Interrupt/exception table
The V854 increases the interrupt response speed by assigning destination addresses corresponding to
interrupts/exceptions.
The collection of these destination addresses is called an interrupt/exception table, which is located in the
internal ROM area. When an interrupt/exception request is granted, execution jumps to the corresponding
destination address, and the program written at that memory address is executed. Table 3-3 shows the
sources of interrupts/exceptions, and the corresponding addresses.
Table 3-3. Interrupt/Exception Table
Start Address of Interrupt/Exception Table
00000000H
Interrupt/Exception Source
RESET
00000010H
00000040H
00000050H
00000060H
00000080H
00000090H
000000A0H
000000B0H
000000C0H
000000D0H
000000E0H
000000F0H
00000100H
00000110H
00000120H
00000130H
00000140H
00000150H
00000160H
00000170H
00000180H
00000190H
000001A0H
000001B0H
000001C0H
000001D0H
000001E0H
000001F0H
00000200H
00000210H
00000220H
00000230H
00000240H
00000250H
00000260H
NMI
TRAP0n (n = 0 to FH)
TRAP1n (n = 0 to FH)
ILGOP
INTOV0/INTP04/INTP05
INTOV1/INTP14
INTCC00/INTP00
INTCC01/INTP01
INTCC02/INTP02
INTCC03/INTP03
INTC10
INTC11
INTCP12
INTCP13
INTCM10
INTCM11
INTCM20/INTP20
INTCM21/INTP21
INTCM22/INTP22
INTCM23/INTP23
INTCM24/INTP24
INTCC3/INTP30
INTCSI0
INTCSI1
INTCSI2
INTCSI3
INIIC
INTSER
INTSR
INTST
INTAD
INTP50
INTP51
INTP52
INTP53
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Caution The internal ROM area becomes the external memory area in ROM-less mode or in the
µPD703006. For normal operation after reset, keep the destination address for the reset
routine in external memory address 0.
(2) Internal RAM area
The V854 is provided with 4 Kbytes of addresses FFE000H to FFEFFFH as a physical internal RAM area.
XXFFEFFFH
Internal RAM
XXFFE000H
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(3) Peripheral I/O area
A 4-Kbyte area of addresses FFF000H to FFFFFFH is reserved as a peripheral I/O area. The V854 is provided
with a 1-Kbyte area of addresses FFF000H to FFF3FFH as a physical peripheral I/O area, and the image of
FFF000H to FFF3FFH can be seen on the rest of the area (FFF400H to FFFFFFH).
XXFFFFFFH
Image
XXFFFC00H
XXFFFBFFH
Physical peripheral I/O
Image
3FFH
XXFFF800H
Peripheral I/O
XXFFF7FFH
Image
Image
000H
XXFFF400H
XXFFF3FFH
XXFFF000H
Peripheral I/O registers associated with the operation mode specification and the state monitoring for the on-
chip peripherals are all memory-mapped to the peripheral I/O area. Program fetches are not allowed in this
area.
Cautions 1. The least significant bit of an address is not decoded since all registers reside on an
even address. If an odd address (2n + 1) in the peripheral I/O area is referenced, the
register at the next lowest even address (2n) will be accessed.
2. If a register that can be accessed in byte units is accessed in half-word units, the higher
8 bits become undefined, if the access is a read operation. If a write access is made,
only the data in the lower 8 bits is written to the register.
3. If a register with n address that can be accessed only in halfword units is accessed with
a word operation, the operation is replaced with two halfword operations. The first
operation (lower 16 bits) accesses to the register with n address and the second
operation (higher 16 bits) accesses to the register with n + 2 address.
4. If a register with n address that can be accessed in word units is accessed with a word
operation, the operation is replaced with two halfword operations. The first operation
(lower 16 bits) accesses to the register with n address and the second operation (higher
16 bits) accesses to the register with n + 2 address.
5. Addresses that are not defined as registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.
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(4) External memory area
The µPD703008, 70F3008, 703008Y, and 70F3008Y can use an area of up to xx100000H to xxFFDFFFH as
an external memory area in the single-chip mode.
The µPD703006, 703008, 70F3008, 703008Y, and 70F3008Y can use an area of up to xx000000H to
xxFFDFFFH as an external memory area in the ROM-less mode.
In the external memory area, 64 K, 256 K, 1 M, 4 M, or 16 Mbytes of physical external memory can be allocated
when the external expansion mode is specified. The same image as that of the physical external memory
can be seen continuously on the external memory area, as shown in Figure 3-6, when the memory is not fully
expanded (to 16 Mbytes).
The internal RAM area, peripheral I/O area, and internal ROM area in single-chip mode are not subject to
external memory access.
Figure 3-6. External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)
XXFFFFFFH
Peripheral I/O
Internal RAM
XXFFDFFFH
Image
Physical external memory
XFFFFH
External memory
Image
Image
X0000H
XX100000H
Internal ROMNote
XX000000H
Note The image of the physical external memory can be seen continuously in the ROM-less mode or with
the µPD703006.
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Figure 3-7. External Memory Area (when expanded to 4 Mbytes)
XXFFFFFFH
XXFFDFFFH
Peripheral I/O
Internal RAM
Image
Physical external memory
3FFFFFH
External memory
Image
000000H
Image
XX100000H
XX000000H
Internal ROMNote
Note The image of the physical external memory can be seen continuously in the ROM-less mode or with
the µPD703006.
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Figure 3-8. External Memory Area (when fully expanded)
XXFFFFFFH
Peripheral I/O
Internal RAM
XXFFDFFFH
External memory
XX100000H
Internal ROMNote
XX000000H
Note This area becomes an external memory area in the ROM-less mode or with the µPD703006.
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3.4.6 External expansion mode
The V854 allows external devices to be connected to the external memory space by using the pins of ports
4, 5, 6, and 9. To connect an external device, the port pins must be set in the external expansion mode by using
the MODEn pins and memory expansion mode register (MM). The MODEn pins specify the operation mode of the
V854.
For specifying, refer to 3.3.2 Specifying operation mode.
In ROM-less mode, the pins of port 4 to port 6 and P90 to P94 become the control mode during reset, thereby
the external memory can be used.
In single-chip mode, the port/control mode alternate pins become the port mode, thereby the external memory
cannot be used. When the external memory is used (external expansion mode), specify the MM register by the
program (the memory area is set by the MM register).
Remark n = 0 to 2
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(1) Memory expansion mode register (MM)
This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external
device can be connected to the external memory area of up to 16 Mbytes. However, the external device cannot
be connected to the internal RAM area, peripheral I/O area, and internal ROM area in the single-chip mode
(access is restricted to external locations 100000H through FFE00H).
The MM register can be read/written in 8- or 1-bit units. However, bits 4 to 7 are fixed to 0.
7
0
6
0
5
0
4
0
3
2
1
0
Address
After reset
MM
MM3
MM2
MM1
MM0
FFFFF04CH 07H (in ROM-less mode)
00H (in single-chip mode)
Bit Position
3
Bit Name
Function
MM3
Memory Expansion Mode
Specifies operation mode of P95 and P96 of port 9.
MM3
Operation Mode
Port mode
External expansion mode HLDAK HLDRQ
P95
P96
0
1
Port
2 to 0
MM2 to MM0 Memory Expansion Mode
Specifies operation mode of ports 4, 5, 6, and 9 (P90 to P94).
MM2
MM1
MM0
Address
Space
Port 4
Port 5
Port 6
Port 9
(P90 to P94)
0
0
0
1
0
1
–
Port mode
64-KB
expansion
AD0 to
AD7
AD8 to
AD15
LBEN,
UBEN,
R/W,
A16
A17
1
1
1
1
0
0
1
1
0
256-KB
expansion
DSTB,
ASTB,
WRL,
WRH,
RD
A18
1
1-MB
expansion
A19
A20
0
1
4-MB
expansion
A21
A22
A23
16-MB
expansion
Others
RFU (reserved)
Remark For the details of the operation of each port pin, refer to 2.3 Pin Function.
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3.4.7 Recommended use of address space
The architecture of the V854 requires that a register that serves as a pointer be secured for address generation
in operand data accessing for data space. The address in this pointer register ±32 Kbytes can be accessed directly
from instruction. However, general register used as a pointer register is limited. Therefore, by minimizing the
deterioration of address calculation performance when changing the pointer value, the number of usable general
registers for handling variables is maximized, and the program size can be saved because instructions for calculating
pointer addresses are not required.
To enhance the efficiency of using the pointer in connection with the memory map of the V854, the following points
are recommended:
(1) Program space
Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to “0”, and only the lower 24 bits are
valid. Therefore, acontiguous16-Mbytespace, startingfromaddress00000000H, unconditionallycorresponds
to the memory map of the program space.
(2) Data space
For the efficient use of resources to be performed through the wrap-around feature of the data space, the
continuous 8-Mbyte address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4-
Gbyte CPU are used as the data space. With the V854, 16-Mbyte physical address space is seen as 256
images in the 4-Gbyte CPU address space. The highest bit (bit 23) of this 24-bit address is assigned as address
sign-extended to 32 bits.
Application of wrap-around
For example, when R = r0 (zero register) is specified for the LD/ST disp 16 [R] instruction, an addressing range
of 00000000H ± 32 Kbytes can be referenced with the sign-extended, 16-bit displacement value. By mapping
the external memory in the 24-Kbyte area in the figure, all resources including on-chip hardware can be
accessed with one pointer.
The zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers
for the pointer.
0001FFFFH
00007FFFH
Internal
32 KB
ROM area
(R =) 00000000H
Peripheral I/O
4 KB
4 KB
FFFFF000H
FFFFE000H
Internal RAM area
External memory
area
24 KB
FFFF8000H
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Figure 3-9. Recommended Memory Map
Program space
Data space
FFFFFFFFH
Peripheral I/O
FFFFF3D2H
FFFFF3D1H
FFFFF000H
FFFFEFFFH
Internal
RAM
XXFFFFFFH
Peripheral I/O
FFFFE000H
FFFFDFFFH
XXFFF3D2H
XXFFF3D1H
XXFFF000H
XXFFEFFFH
External
memory
FF800000H
FF7FFFFFH
Internal
RAM
XXFFE000H
XXFFDFFFH
01000000H
00FFFFFFH
Peripheral I/ONote
External
memory
XX800000H
XX7FFFFFH
00FFF000H
00FFEFFFH
XX100000H
XX0FFFFFH
XX020000H
XX01FFFFH
Internal
RAM
Internal
ROM
00FFE000H
00FFDFFFH
16 MB
XX000000H
External
memory
00800000H
007FFFFFH
External
memory
00100000H
000FFFFFH
00020000H
0001FFFFH
8 MB
Internal
ROM
Internal
ROM
00000000H
Note This area cannot be used as a program area.
Remarks 1. The vertical arrows ( ) indicate the recommended area.
2. In this figure, the µPD703008 is set in the single-chip mode and the recommended
memory map when the external expanded memory mode being used is shown.
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3.4.8 Peripheral I/O registers
(1/6)
Bit Units for
Manipulation
Address
Function Register Name
Symbol
R/W
R/W
After Reset
1 bit 8 bits 16 bits 32bits
FFFFF000H Port 0
FFFFF002H Port 1
FFFFF004H Port 2
FFFFF006H Port 3
FFFFF008H Port 4
FFFFF00AH Port 5
FFFFF00CH Port 6
FFFFF00EH Port 7
FFFFF010H Port 8
P0
P1
P2
P3
P4
P5
P6
P7
P8
Undefined
R
FFFFF012H Port 9
P9
R/W
FFFFF014H Port 10
P10
FFFFF016H Port 11
P11
FFFFF018H Port 12
P12
FFFFF01AH Port 13
P13
FFFFF01CH Port 14
P14
FFFFF020H Port 0 mode register
FFFFF022H Port 1 mode register
FFFFF024H Port 2 mode register
FFFFF026H Port 3 mode register
FFFFF028H Port 4 mode register
FFFFF02AH Port 5 mode register
FFFFF02CH Port 6 mode register
FFFFF032H Port 9 mode register
FFFFF034H Port 10 mode register
FFFFF036H Port 11 mode register
FFFFF038H Port 12 mode register
FFFFF03AH Port 13 mode register
FFFFF03CH Port 14 mode register
FFFFF040H Port 0 mode control register
FFFFF042H Port 1 mode control register
FFFFF044H Port 2 mode control register
FFFFF046H Port 3 mode control register
FFFFF04CH Memory expansion mode register
FFFFF054H Port 10 mode control register
FFFFF056H Port 11 mode control register
FFFFF058H Port 12 mode control register
PM0
FFH
PM1
PM2
PM3
PM4
PM5
PM6
PM9
PM10
PM11
PM12
PM13
PM14
PMC0
PMC1
PMC2
PMC3
MM
00H
01H
00H
00H/07H
00H
PMC10
PMC11
PMC12
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Bit Units for
Manipulation
Address
Function Register Name
Symbol
R/W
R/W
After Reset
1 bit 8 bits 16 bits 32bits
FFFFF05AH Port 13 mode control register
FFFFF060H Data wait control register
FFFFF062H Bus cycle control register
PMC13
DWC
BCC
00H
FFFFH
AAAAH
FFFFF064H System control register
SYC
00H/1H
00H/C0H
00H
FFFFF070H Power save control register
PSC
FFFFF072H Clock control register
CKC
FFFFF078H System status register
SYS
0000000XB
Undefined
00H
FFFFF084H Baud rate generator compare register 0
FFFFF086H Baud rate generator prescaler mode register 0
FFFFF088H Clocked serial interface mode register 0
FFFFF08AH Serial I/O shift register 0
BRGC0
BPRM0
CSIM0
SIO0
Undefined
00H
FFFFF094H Baud rate generator compare register 1
FFFFF096H Baud rate generator prescaler mode register 1
FFFFF098H Clocked serial interface mode register 1
FFFFF09AH Serial I/O shift register 1
BRGC1
BPRM1
CSIM1
SIO1
Undefined
00H
FFFFF0A4H Baud rate generator compare register 2
FFFFF0A6H Baud rate generator prescaler mode register 2
FFFFF0A8H Clocked serial interface mode register 2
FFFFF0AAH Serial I/O shift register 2
BRGC2
BPRM2
CSIM2
SIO2
Undefined
FFFFF0B4H Baud rate generator register 3
BRGC3
FFFFF0B6H Baud rate generator prescaler mode register
FFFFF0B8H Clocked serial interface mode register 3
FFFFF0BAH Serial I/O shift register 3
BPRM3
CSIM3
SIO3
00H
Undefined
80H
FFFFF0C0H Asynchronous serial interface mode register 0
FFFFF0C2H Asynchronous serial interface mode register 1
FFFFF0C4H Asynchronous serial interface status register
FFFFF0C8H Receive buffer (9 bits)
ASIM0
ASIM1
ASIS
00H
R
RXB
Undefined
FFFFF0CAH Receive buffer L (lower 8 bits)
FFFFF0CCH Transmit shift register (9 bits)
RXBL
TXS
W
FFFFF0CEH Transmit shift register L (lower 8 bits)
FFFFF0E0H IIC control register
TXSL
IICC
R/W
R
00H
FFFFF0E2H IIC status register
IICS
FFFFF0E4H IIC clock selection register
FFFFF0E6H IIC shift register
IICCL
IIC
R/W
FFFFF0E8H Slave address register
FFFFF100H Interrupt control register
FFFFF102H Interrupt control register
FFFFF104H Interrupt control register
SVA
OVIC0
OVIC1
CC0IC0
47H
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Bit Units for
Manipulation
Address
Function Register Name
Symbol
R/W
R/W
After Reset
1 bit 8 bits 16 bits 32bits
FFFFF106H Interrupt control register
FFFFF108H Interrupt control register
FFFFF10AH Interrupt control register
FFFFF10CH Interrupt control register
FFFFF10EH Interrupt control register
FFFFF110H Interrupt control register
FFFFF112H Interrupt control register
FFFFF114H Interrupt control register
FFFFF116H Interrupt control register
FFFFF118H Interrupt control register
FFFFF11AH Interrupt control register
FFFFF11CH Interrupt control register
FFFFF11EH Interrupt control register
FFFFF120H Interrupt control register
FFFFF122H Interrupt control register
FFFFF124H Interrupt control register
FFFFF126H Interrupt control register
FFFFF128H Interrupt control register
FFFFF12AH Interrupt control register
FFFFF12CH Interrupt control register
FFFFF12EH Interrupt control register
FFFFF130H Interrupt control register
FFFFF132H Interrupt control register
FFFFF134H Interrupt control register
FFFFF136H Interrupt control register
FFFFF138H Interrupt control register
FFFFF13AH Interrupt control register
FFFFF13CH Interrupt control register
FFFFF166H In-service priority register
FFFFF170H Command register
CC0IC1
CC0IC2
CC0IC3
P1IC0
47H
P1IC1
P1IC2
P1IC3
CM1IC0
CM1IC1
CM2IC0
CM2IC1
CM2IC2
CM2IC3
CM2IC4
CM3IC0
CSIC0
CSIC1
CSIC2
CSIC3
IIIC0
SEIC0
SRIC0
STIC0
ADIC0
P51C0
P51C1
P51C2
P51C3
ISPR
R
W
00H
Undefined
00H
PRCMD
INTM0
INTM1
INTM2
INTM5
INTM6
INTM7
EDVC0
EDVC1
FFFFF180H External interrupt mode register 0
FFFFF182H External interrupt mode register 1
FFFFF184H External interrupt mode register 2
FFFFF18AH External interrupt mode register 5
FFFFF18CH External interrupt mode register 6
FFFFF18EH External interrupt mode register 7
FFFFF1B0H Event divide control register 0
FFFFF1B2H Event divide control register 1
R/W
01H
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Bit Units for
Manipulation
Address
Function Register Name
Symbol
R/W
After Reset
1 bit 8 bits 16 bits 32bits
FFFFF1B4H Event divide control register 2
FFFFF1B6H Event divide counter 0
FFFFF1B8H Event divide counter 1
FFFFF1BAH Event divide counter 2
FFFFF1C0H Event selection register
EDVC2
EDV0
EDV1
EDV2
EVS
R/W
R
01H
00H
R/W
FFFFF230H Timer overflow status register
FFFFF232H Timer output control register 0
FFFFF234H Timer output control register 1
FFFFF240H Timer control register 00
FFFFF242H Timer control register 01
FFFFF244H Timer control register 02
FFFFF250H Timer 0
TOVS
TOC0
TOC1
TMC00
TMC01
TMC02
TM0
01H
00H
R
00000000H
Undefined
FFFFF254H Capture/compare register 00
FFFFF258H Capture/compare register 01
FFFFF25CH Capture/compare register 02
FFFFF260H Capture/compare register 03
FFFFF264H Timer 0L
CC00
CC01
CC02
CC03
TM0L
CC00L
CC01L
CC02L
CC03L
TMC1
TM1
R/W
R
0000H
FFFFF266H Capture/compare register 00L
FFFFF268H Capture/compare register 01L
FFFFF26AH Capture/compare register 02L
FFFFF26CH Capture/compare register 03L
FFFFF270H Timer control register 1
FFFFF274H Timer 1
R/W
Undefined
01H
R
00000000H
Undefined
FFFFF278H Compare register 10
FFFFF27CH Compare register 11
FFFFF280H Capture register 10
FFFFF284H Capture register 11
FFFFF288H Capture register 12
FFFFF28CH Capture register 13
FFFFF290H Timer 1L
CM10
CM11
CP10
R/W
R
CP11
CP12
CP13
TM1L
CM10L
CM11L
CP10L
CP11L
CP12L
CP13L
TMC20
TM20
0000H
FFFFF292H Compare register 10L
FFFFF294H Compare register 11L
FFFFF296H Capture register 10L
FFFFF298H Capture register 11L
FFFFF29AH Capture register 12L
FFFFF29CH Capture register 13L
FFFFF2A0H Timer control register 20
FFFFF2B0H Timer 20
R/W
R
Undefined
R/W
R
01H
0000H
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Bit Units for
Manipulation
Address
Function Register Name
Symbol
R/W
R/W
After Reset
1 bit 8 bits 16 bits 32bits
FFFFF2B2H Compare register 20
FFFFF2C0H Timer control register 21
FFFFF2D0H Timer 21
CM20
Undefined
01H
TMC21
TM21
R
0000H
Undefined
01H
FFFFF2D2H Compare register 21
FFFFF2E0H Timer control register 22
FFFFF2F0H Timer 22
CM21
R/W
TMC22
TM22
R
0000H
Undefined
01H
FFFFF2F2H Compare register 22
FFFFF300H Timer control register 23
FFFFF310H Timer 23
CM22
R/W
TMC23
TM23
R
0000H
Undefined
01H
FFFFF312H Compare register 23
FFFFF320H Timer control register 24
FFFFF330H Timer 24
CM23
R/W
TMC24
TM24
R
0000H
Undefined
01H
FFFFF332H Compare register 24
FFFFF340H Timer control register 3
FFFFF350H Timer 3
CM24
R/W
TMC3
TM3
R
0000H
Undefined
FFFFF352H Capture/compare register 3
FFFFF354H Capture register 3
CC3
R/W
R
CP3
FFFFF360H PWM control register 3
FFFFF362H PWM modulo register 0
FFFFF364H PWM prescaler register 0
FFFFF368H PWM control register 1
FFFFF36AH PWM modulo register 1
FFFFF36CH PWM prescaler register 1
FFFFF370H PWM control register 2
FFFFF372H PWM modulo register 2
FFFFF374H PWM prescaler register 2
FFFFF378H PWM control register 3
FFFFF37AH PWM modulo register 3
FFFFF37CH PWM prescaler register 3
FFFFF380H A/D converter mode register 0
FFFFF382H A/D converter mode register 1
FFFFF390H A/D conversion result register 0
FFFFF392H A/D conversion result register 1
FFFFF394H A/D conversion result register 2
FFFFF396H A/D conversion result register 3
FFFFF398H A/D conversion result register 4
FFFFF39AH A/D conversion result register 5
FFFFF39CH A/D conversion result register 6
PWMC0
PWM0
PWPR0
PWMC1
PWM1
PWPR1
PWMC2
PWM2
PWPR2
PWMC3
PWM3
PWPR3
ADM0
ADM1
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
R/W
05H
Undefined
00H
05H
Undefined
00H
05H
Undefined
00H
05H
Undefined
00H
07H
R
Undefined
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Bit Units for
Manipulation
Address
Function Register Name
Symbol
R/W
After Reset
1 bit 8 bits 16 bits 32bits
FFFFF39EH A/D conversion result register 7
FFFFF3C0H Port 13 buffer register
FFFFF3C2H Output latch
ADCR7
PB
R
Undefined
00H
R/W
RTP
FFFFF3D0H Clock output mode register
CL0M
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3.4.9 Specific registers
Specific registers are registers that are protected from being written with illegal data due to program runaway, etc.
The write access of these specific registers is executed in a specific sequence, and if abnormal
store operations occur, this is notified by the system status register (SYS). The V854 has two specific registers, the
clock control register (CKC) and power save control register (PSC). For details of the CKC register, refer to 6.3.3,
and for details of the PSC register, refer to 6.5.2.
The following sequence shows the data setting of the specific registers.
(1) Set the PSW NP bit to 1 (interrupt disabled).
(2) Write arbitrary 8-bit data in the command register (PRCMD).
(3) Write the set data in the specific registers (by the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
(4) Return the PSW NP bit to 0 (interrupt disable canceled).
(5) To shift to the software STOP mode or IDLE mode, insert the NOP instructions (2 or 5 instructions).
No special sequence is required when reading the specific registers.
Cautions 1. If an interrupt request is accepted between the time PRCMD is issued (2) and the specific
register write operation (3) that follows immediately after, the write operation to the specific
register is not performed and a protection error (PRERR bit of SYS register is “1”) may occur.
Therefore, set the NP bit of PSW to 1 (1) to disable the acceptance of INT/NMI.
The above also applies when a bit manipulation instruction is used to set a specific register.
Moreover, to ensure that the execution routine following release of the software STOP/IDLE
mode is performed correctly, insert the NOP instruction as a dummy instruction (5). If the
value of the ID bit of PSW does not change as the result of execution of the instruction to
return the NP bit to 0 (4), insert two NOP instructions, and if the value of the ID bit of PSW
changes, insert five NOP instructions.
A description example is given below.
[Description example] : In case of PSC register
LDSR rX,5
; NP bit = 1
ST.B r0,PRCMD [r0]
ST.B rD,PSC [r0]
LDSR rY,5
; Write to PRCMD
; PSC register setting
; NP bit = 0
NOP
; Dummy instruction (2 or 5 instructions)
.
.
.
NOP
(next instruction)
; ExecutionroutinefollowingcancellationofsoftwareSTOP/IDLEmode
.
.
.
rX: Value to be written to PSW
rY: Value to be written back to PSW
rD: Value to be set to PSC
When saving the value of PSW, the value of PSW prior to setting the NP bit must be transferred
to the rY register.
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2. The instructions ((4) interrupt disable cancel, (5) NOP instruction) following the store
instruction for the specific register for setting the software STOP mode and IDLE mode are
executed before a power save mode is entered.
(1) Command Register (PRCMD)
The command register (PRCMD) is a register used when write-accessing the special register to prevent
incorrect writing to the special registers due to the erroneous program execution.
This register can be read/written in 8-bit units. It becomes undefined values in a read cycle.
Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
7
6
5
4
3
2
1
0
Address
FFFFF170H
After reset
Undefined
PRCMD
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
Bit Position Bit Name
Function
7 to 0
REG7 to
REG0
Registration Code
Specific Register
Registration Code
CKC
PSC
Arbitrary 8-bit data
Arbitrary 8-bit data
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(2) System status register (SYS)
This register is allocated with status flags showing the operating state of the entire system. This register can
be read/written in 8- or 1-bit units.
7
0
6
0
5
0
4
3
0
2
0
1
0
0
Address
FFFFF078H
After reset
0000000XB
SYS
PRERR
UNLOCK
Bit Position
4
Bit Name
Function
PRERR
Protection Error Flag
Indicates that writing to a special register has not be executed in the correct sequence, and
protection error occurred.
Accumulate flag
0 : Protection error does not occur.
1 : Protection error occurs.
0
UNLOCK
Unlock Status Flag
Read-only flag. Indicates the PLL unlock state. (For details, refer to 6.4 PLL Stabilization.)
0 : Locked
1 : Unlocked
Operation conditions of PRERR Flag
• Set conditions:
(PRERR = “1”)
(1) If the store instruction most recently executed to peripheral I/O does not write
data to the PRCMD register, but to the specific register.
(2) If the first store instruction executed after the write operation to the
PRCMD register is to a peripheral I/O register other than the specific registers.
• Reset conditions:
(PRERR = “0”)
(1) When “0” is written to the PRERR flag of the SYS register.
(2) At system reset.
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[MEMO]
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The V854 is provided with an external bus interface function by which external memories such as ROM and RAM,
and I/O can be connected.
4.1 Features
16-bit data bus
Can be connected to external devices with pins having alternate function as port
Wait function
• Programmable wait function of up to 3 states per 2 blocks
• External wait function through WAIT pin
Idle state insertion function
Bus mastership arbitration function
Bus hold function
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4.2 Bus Control Pins and Control Register
4.2.1 Bus control pins
The following pins are used for interfacing to external devices:
External Bus Interface Function
Address/data bus (AD0 to AD7)
Corresponding Port (pins)
Port 4 (P40 to P47)
Port 5 (P50 to P57)
Port 6 (P60 to P67)
Port 9 (P90 to P93)
Port 9 (P94)
Address/data bus (AD8 to AD15)
Address bus (A16 to A23)
Read/write control (LBEN, UBEN, R/W, DSTB, WRL, WRH, RD)
Address strobe (ASTB)
Bus hold control (HLDRQ, HLDAK)
External wait control (WAIT)
Port 9 (P95, P96)
WAIT
The bus interface function of each pin is enabled by the memory expansion mode register (MM). In ROM-less
mode, the bus interface function of each pin is unconditionally enabled by the MODE input (n = 0 to 2). For the details
of specifying an operation mode of the external bus interface, refer to 3.4.6 (1) Memory expansion mode register
(MM).
4.2.2 Control register
(1) System control register (SYC)
This register switches control signals for bus interface.
The system control register can be read/written in 8- or 1-bit units.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
After reset
BIC
SYC
FFFFF064H 00H (in single-chip mode 1, 2
and ROM-less mode 1)
(in ROM-less mode 2)
01H
Bit Position
1
Bit Name
Function
BIC
Bus Interface Control
Changes bus interface control signal
0 : DSTB, R/W, UBEN, LBEN signal outputs
1 : RD, WRL, WRH, UBEN signal outputs
RD, WRL, WRH, and UBEN signals are output immediately after reset in ROM-less mode 2.
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4.3 Bus Access
4.3.1 Number of access clocks
The number of basic clocks necessary for accessing each resource is as follows:
Resource (bus width)
Bus Cycle Type
Internal ROM
(32 bits)
Internal RAM
(32 bits)
Internal Peripheral
I/O (16 bits)
External Memory
(16 bits)
Instruction fetch
1
3
3
1
Disabled
3 + n
3 + n
3 + n
Operand data access
Remarks 1. Unit : clock/access
2. n
: number of wait insertions
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4.3.2 Bus width
The V854 carries out peripheral I/O access and external memory access in 8-, 16-, or 32-bit. The following shows
the operation for each access.
(1) Byte access (8 bits)
Byte access is divided into two types, the access to even address and the access to odd address.
(a) Access to even address
(b) Access to odd address
15
15
8
8
7
0
7
7
0
7
0
0
Byte data
External data bus
Byte data
External data bus
(2) Halfword access (16 bits)
In halfword access to external memory, data is dealt with as it is because the data bus is fixed to 16 bits.
15
15
0
0
Halfword data External data bus
(3) Word access (32 bits)
In word access to external memory, lower halfword is accessed first and then the upper halfword is accessed.
First
Second
31
31
16
15
16
15
15
0
15
0
0
0
Word data
External data bus
Word data
External data bus
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4.4 Memory Block Function
The 16-Mbyte memory space is divided into memory blocks of 1-Mbyte units. The programmable wait function
and bus cycle operation mode can be independently controlled for every two memory blocks.
FFFFFFH
FFFFFFH
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
Peripheral I/O area
FFF000H
F00000H
EFFFFFH
FFEFFFH
E00000H
DFFFFFH
Internal RAM area
FFE000H
D00000H
CFFFFFH
C00000H
BFFFFFH
B00000H
AFFFFFH
A00000H
9FFFFFH
900000H
8FFFFFH
800000H
7FFFFFH
External memory area
700000H
6FFFFFH
600000H
5FFFFFH
500000H
4FFFFFH
400000H
3FFFFFH
300000H
2FFFFFH
200000H
1FFFFFH
100000H
0FFFFFH
Internal ROM areaNote
000000H
Note In the ROM-less modes or for the µPD703006, this area becomes the external memory area.
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4.5 Wait Function
4.5.1 Programmable wait function
To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a
bus cycle for two memory blocks. The number of wait states can be programmed by using data wait control register
(DWC). Immediately after the system has been reset, three data wait states are automatically programmed for all
memory blocks.
(1) Data wait control register (DWC)
This register can be read/written in 16-bit units.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
FFFFF060H
After reset
FFFFH
DW71 DW70 DW61 DW60 DW51 DW50 DW41 DW40 DW31 DW30 DW21 DW20 DW11 DW10 DW01 DW00
DWC
Bit Position
15 to 0
Bit Name
Function
DWn1
Data Wait
Specifies number of wait states to be inserted
DWn0
(n = 0 to 7)
DWn1
DWn0
Number of wait states to be inserted
0
0
1
1
0
1
0
1
0
1
2
3
n
0
1
2
3
4
5
6
7
Blocks into which wait states are inserted
Blocks 0/1
Blocks 2/3
Blocks 4/5
Blocks 6/7
Blocks 8/9
Blocks 10/11
Blocks 12/13
Blocks 14/15
Cautions 1. Block 0 is reserved for the internal ROM area in the single-chip mode. It is not subject
to programmable wait control, regardless of the setting of DWC, and is always accessed
without wait states.
2. The internal RAM area of block 15 is not subject to programmable wait control and is
always accessed without wait states. The peripheral I/O area of this block is not subject
to programmable wait control, either. The only wait control is dependent upon the
execution of each peripheral function.
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4.5.2 External wait function
When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be
inserted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device.
The external WAIT signal does not affect the access times of the internal ROM, internal RAM, and peripheral I/
O areas. Input of the external WAIT signal can be done asynchronously to CLKOUT and is sampled at the falling
edge of the clock in the T2 and TW states of a bus cycle. If the set up and hold time of the WAIT input are not satisfied,
the wait state may or may not be inserted in the next state.
4.5.3 Relations between programmable wait and external wait
A wait cycle is inserted as a result of an OR operation between the wait cycle specified by the set value of
programmable wait and the wait cycle controlled by the WAIT pin. In other words, the number of wait cycles is
determined by the programmable wait value or the length of evaluation at the WAIT input pin.
Programmable wait
Wait control
Wait by WAIT pin
For example, if the number of programmable wait states is 2 and the timing of the WAIT pin input signal is as
illustrated below, three wait states will be inserted in the bus cycle.
Figure 4-1. Example of Inserting Wait States
T1
T2
TW
TW
TW
T3
CLKOUT
WAIT pin
Wait by WAIT pin
Programmable wait
Wait control
Remark
: valid sampling timing
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4.6 Idle State Insertion Function
To facilitate interfacing with low-speed memory devices and meeting the data output float delay time (tDF) on
memory read accesses, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle
following continuous bus cycles starts after one idle state.
Specifying insertion of the idle state is programmable by using the bus cycle control register (BCC).
Immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks.
(1) Bus cycle control register (BCC)
This register can be read/written in 16-bit units.
15 14 13 12 11 10
9
8
0
7
6
0
5
4
0
3
2
0
1
0
0
Address
FFFFF062H
After reset
AAAAH
BCC
BC71
0
BC61
0
BC51
0
BC41
BC31
BC21
BC11
BC01
Bit Position
Bit Name
Function
15, 13, 11,
9, 7, 5, 3, 1
BCn1
Bus Cycle
(n = 0 to 7)
Specifies insertion of idle state.
0: Not inserted
1: Inserted
n
Blocks into Which Idle State Is Inserted
Blocks 0/1
0
1
2
3
4
5
6
7
Blocks 2/3
Blocks 4/5
Blocks 6/7
Blocks 8/9
Blocks 10/11
Blocks 12/13
Blocks 14/15
Cautions 1. Block 0 is reserved for the internal ROM area in the single-chip mode; therefore, no
insertion of the idle state can be specified for block 0 regardless of the BCC settings.
2. The internal RAM area and peripheral I/O area of block 15 are not subject to insertion of
the idle state.
3. Be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. If these bits are set to 1, the operation
is not guaranteed.
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4.7 Bus Hold Function
4.7.1 Outline of function
When P95 and P96 of port 9 are programmed to be in the control mode, the functions of the HLDRQ and HLDAK
pins become valid.
When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus,
the external address/data bus and strobe pins go into a high-impedance state, and the bus is released (bus hold
status). When the HLDRQ pin becomes inactive (high) indicating that the request for the bus is cleared, these pins
are driven again.
During bus hold period, the V854 continues internal operation until the next external memory access.
In the bus hold status, the HLDAK pin becomes active (low).
This feature can be used to design a system where two or more bus masters exist, such as when multi-processor
configuration is used and when a DMA controller is connected.
Bus hold request is not acknowledged between the first and the second word access. Bus hold request is also
acknowledged between read access and write access in read modify write access of bit manipulation instruction.
4.7.2 Bus hold procedure
The procedure of the bus hold function is illustrated below.
<1> HLDRQ = 0 accepted
<2> All bus cycle start request pending
<3> End of current bus cycle
<4> Bus idle status
Normal status
- - - - - - - - - - -
<5> HLDAK = 0
Bus hold status
<6> HLDRQ = 1 accepted
<7> HLDAK = 1
- - - - - - - - - - -
Normal status
<8> Clears bus cycle start request pending
<9> Start of bus cycle
HLDRQ
HLDAK
<1>
<
2>
<
3><4><5>
<6> <7><8><9>
4.7.3 Operation in power save mode
In the STOP or IDLE mode, the system clock is stopped. Consequently, the bus hold status is not set even if the
HLDRQ pin becomes active.
In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the
bus hold status is set. When the HLDRQ pin becomes inactive, the HLDAK pin becomes inactive. As a result, the
bus hold status is cleared, and the HALT mode is set again.
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4.8 Bus Timing
(1) Memory read (0 wait)
T1
T2
T3
CLKOUT
Address
A16 to A23
AD0 to AD15
ASTB
Address
Data
R/W
H
WRL,
WRH
DSTB,
RD
UBEN,
LBEN
WAIT
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The dotted line indicates the high-impedance state.
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(2) Memory read (1 wait)
T1
T2
TW
T3
CLKOUT
Address
A16 to A23
AD0 to AD15
ASTB
Address
Data
R/W
H
WRL,
WRH
DSTB,
RD
UBEN,
LBEN
WAIT
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The dotted line indicates the high-impedance state.
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(3) Memory read (0 wait, idle state)
T1
T2
T3
TI
CLKOUT
Address
A16 to A23
AD0 to AD15
ASTB
Address
Data
R/W
DSTB,
RD
WRL,
WRH
H
UBEN,
LBEN
WAIT
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The dotted line indicates the high-impedance state.
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(4) Memory read (1 wait, idle state)
T1
T2
TW
T3
TI
CLKOUT
A16 to A23
AD0 to AD15
ASTB
Address
Data
Address
R/W
WRL,
WRH
H
DSTB,
RD
UBEN,
LBEN
WAIT
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The dotted line indicates the high-impedance state.
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(5) Memory write (0 wait)
T1
T2
T3
CLKOUT
Address
A16 to A23
AD0 to AD15
ASTB
DataNote
Address
R/W
RD
H
DSTB
WRL,
WRH
UBEN,
LBEN
WAIT
Note AD0 to AD7 output invalid data when odd address byte data is accessed.
AD8 to AD15 output invalid data when even address byte data is accessed.
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The dotted line indicates the high-impedance state.
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(6) Memory write (1 wait)
T1
T2
TW
T3
CLKOUT
Address
A16 to A23
AD0 to AD15
ASTB
Address
DataNote
R/W
RD
H
DSTB
WRL,
WRH
UBEN,
LBEN
WAIT
Note AD0 to AD7 output invalid data when odd address byte data is accessed.
AD8 to AD15 output invalid data when even address byte data is accessed.
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The dotted line indicates the high-impedance state.
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CHAPTER 4 BUS CONTROL FUNCTION
(7) Bus hold timing
T2
T3
TH
TH
TH
TH
TI
T1
CLKOUT
HLDRQ
HLDAK
A16 to A23
Address
Undefined Address
Undefined
AD0 to AD15
Address
Data
Address
ASTB
R/W
DSTB,
RD,
WRL,
WRH
UBEN,
LBEN
Undefined
WAIT
Remarks 1.
indicates the sampling timing.
2. The dotted line indicates the high-impedance state.
Caution
When the bus hold state is entered after the write cycle, a high-level signal may be briefly
output from the R/W pin immediately before the HLDAK signal changes from the high
level to the low level.
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4.9 Bus Priority
There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch
(continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch
(branch), and instruction fetch (continuous) in that order.
The instruction fetch cycle may be inserted in between the read access and write access of read-modify-write
access.
No instruction fetch cycle and bus hold are inserted between the lower half-word access and higher half-word
access of word operations.
Table 4-1. Bus Priority
External Bus Cycle
Bus hold
Priority
1
2
3
4
Operand data access
Instruction fetch (branch)
Instruction fetch (continuous)
4.10 Memory Boundary Operation Condition
4.10.1 Program space
(1) Do not execute branch to the peripheral I/O area or continuous fetch from the internal RAM area to peripheral
I/O area. Of course, it is impossible to fetch from external memory. If branch or instruction fetch is executed
nevertheless, the NOP instruction code is continuously fetched.
(2) A prefetch operation straddling over the peripheral I/O area (invalid fetch) does not take place if a branch
instruction exists at the upper-limit address of the internal RAM area.
4.10.2 Data space
Only the address aligned at the half-word (when the least significant bit of the address is “0”)/word (when the lowest
2 bits of the address are “0”) boundary is accessed for data half-word (16 bits)/word (32 bits) long.
Therefore, access that straddles over the memory or memory block boundary does not take place.
For the details, refer to V850 Family Architecture User’s Manual .
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4.11 Internal Peripheral I/O Interface
Access to the internal peripheral I/O area is not output to the external bus. Therefore, the internal peripheral
I/O area can be accessed in parallel with instruction fetch access.
Accesses to the internal peripheral I/O area takes, in most cases, three clock cycles. However, when accessing
to certain timer/counter registers, wait may take place from 3 to 4 cycles.
Peripheral I/O Register
CC00 to CC03
Access
Read
Number of Waits
Number of Cycles
2
0/2
1
8
6/8
4
Write
Read
Write
Read
Write
CC00L to CC03L, CC3
0/1
2
3/4
8
CP10 to CP13, CM10
CM11, TM0, TM1
0
6
CP10L, CP13L, CM10L, CM11L, Read
1
4
TM0L, TM1L, CP3, TM3
CM20 to CM24
Write
Read
Write
Read
Write
Read
Write
0
3
0/1
0/1
0/1
0
6/8
6/8
6/8
6
TM20 to TM24
Others
0
3
0
3
Remark In 32-bit access, two 16-bit accesses are executed. Therefore, the numbers
of waits and cycles are twice those in 16-bit access.
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The V854 is provided with a dedicated interrupt controller (INTC) for interrupt processing and can process a total
of 32 interrupt requests.
An interrupt is an event that occurs independently of program execution, and an exception is an event that occurs
dependently on program execution. Generally, an exception takes precedence over an interrupt.
The V854 can process interrupt requests from the internal peripheral hardware and external sources. Moreover,
exception processing can be started by the TRAP instruction (software exception) or by generation of an exception
event (fetching of an illegal op code).
5.1 Features
Interrupt
• Non-maskable interrupt: 1 source
• Maskable interrupt: 31 sources
• 8 levels programmable priorities control
• Multiple interrupt control according to priority
• Mask specification for each maskable interrupt request
• Noise elimination, edge detection, and valid edge of external interrupt request signal can be specified.
Exception
• Software exception: 32 sources
• Exception trap: 1 source (illegal op code exception)
Interrupt/exception sources are listed in Table 5-1.
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Table 5-1. Interrupt List (1/2)
Interrupt/Exception Source
Default
Priority
Exception
Vector
Restored
PC
Classification
Interrupt
Type
Control
Generating
Unit
Name
Generating Source
Code
Address
Register
Reset
RESET
–
–
–
–
–
Reset input
–
–
–
–
–
–
0
0000H
00000000H Undefined
00000010H nextPC
00000040H nextPC
00000050H nextPC
00000060H nextPC
00000080H nextPC
Non-maskable Interrupt
NMI
NMI input
–
0010H
Exception
Software
TRAP0nNote
TRAP1nNote
ILGOP
TRAP instruction
TRAP instruction
Illegal op code
–
004nNote
005nNote
0060H
H
H
exception
Exception
–
–
Exception trap Exception
Maskable
Interrupt
INTOV0/
INTP04/
INTP05
OVIC0 Timer 0 overflow/
INTP04, INTP05 input
Pin/RPU
0080H
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTOV1/
INTP14
OVIC1 Timer 1 overflow/
INTP14 input
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
1
2
3
4
5
0090H
00A0H
00B0H
00C0H
00D0H
00000090H nextPC
000000A0H nextPC
000000B0H nextPC
000000C0H nextPC
000000D0H nextPC
INTP00/
CC0IC0 INTP00/CC00
coincidence
INTCC00
INTP01/
CC0IC1 INTP01/CC01
coincidence
INTCC01
INTP02/
CC0IC2 INTP02/CC02
coincidence
INTCC02
INTP03/
CC0IC3 INTP03/CC03
coincidence
INTCC03
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTCP10
INTCP11
INTCP12
INTCP13
INTCM10
INTCM11
P1IC0
P1IC1
P1IC2
P1IC3
INTP10 input
Pin
Pin
6
7
00E0H
00F0H
0100H
0110H
0120H
0130H
0140H
000000E0H nextPC
000000F0H nextPC
00000100H nextPC
00000110H nextPC
00000120H nextPC
00000130H nextPC
00000140H nextPC
INTP11 input
INTP12 input
Pin
8
INTP12/INTP13 input
Pin
9
CM1IC0 CM10 coincidence
CM1IC1 CM11 coincidence
RPU
RPU
Pin/RPU
10
11
12
INTP20/
CM2IC0 INTP20/CM20
coincidence
INTCM20
Interrupt
Interrupt
Interrupt
Interrupt
INTP21/
CM2IC1 INTP21/CM21
coincidence
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
13
14
15
16
0150H
0160H
0170H
0180H
00000150H nextPC
00000160H nextPC
00000170H nextPC
00000180H nextPC
INTCM21
INTP22/
CM2IC2 INTP22/CM22
coincidence
INTCM22
INTP23/
CM2IC3 INTP23/CM23
coincidence
INTCM23
INTP24/
CM2IC4 INTP24/CM24
coincidence
INTCM24
Note n: value of 0 to FH
Remarks 1. Default Priority : Priority that takes precedence when two or more maskable interrupt requests
occur at the same time. The highest priority is 0.
Restored PC
: The value of the PC saved to EIPC or FEPC when interrupt/exception processing
is started. However, the value of the PC saved when an interrupt is granted during
the DIVH (division) instruction execution is the value of the PC of the current
instruction (DIVH).
2. The execution address of the illegal instruction when an illegal op code exception occurs is calculated
with (Restored PC – 4).
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Table 5-1. Interrupt List (2/2)
Interrupt/Exception Source
Default
Priority
Exception
Vector
Restored
PC
Classification
Type
Control
Generating
Unit
Name
Generating Source
Code
Address
Register
Maskable
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTP30/
INTCC3
CC3IC0 INTP30/CC3
coincidence
Pin/RPU
17
18
19
20
21
0190H
00000190H nextPC
000001A0H nextPC
000001B0H nextPC
000001C0H nextPC
000001D0H nextPC
INTCSI0
INTCSI1
INTCSI2
INTCSI3
CSIC0 CSI0 transmission/
reception completion
CSI
01A0H
01B0H
01C0H
01D0H
CSIC1 CSI1 transmission/
reception completion
CSI
CSIC2 CSI2 transmission/
reception completion
CSI
CSIC3 CSI3 transmission/
reception completion
CSI
Interrupt
Interrupt
Interrupt
INTIIC
INTSER
INTSR
IIIC0
I2C interrupt
I2C
22
23
24
01E0H
01F0H
0200H
000001E0H nextPC
000001F0H nextPC
00000200H nextPC
SEIC0
UART reception error
UART
UART
SRIC0 UART reception
completion
Interrupt
INTST
STIC0
UART transmission
completion
UART
25
0210H
00000210H nextPC
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTAD
ADIC0 A/D conversion end
ADC
Pin
Pin
Pin
Pin
26
27
28
29
30
0220H
0230H
0240H
0250H
0260H
00000220H nextPC
00000230H nextPC
00000240H nextPC
00000250H nextPC
00000260H nextPC
INTP50
INTP51
INTP52
INTP53
P5IC0
P5IC1
P5IC2
P5IC3
INTP50 input
INTP51 input
INTP52 input
INTP53 input
Remarks 1. Default Priority : Priority that takes precedence when two or more maskable interrupt requests
occur at the same time. The highest priority is 0.
Restored PC
: The value of the PC saved to EIPC or FEPC when interrupt/exception processing
is started. However, the value of the PC saved when an interrupt is granted during
the DIVH (division) instruction execution is the value of the PC of the current
instruction (DIVH).
2. The execution address of the illegal instruction when an illegal op code exception occurs is calculated
with (Restored PC – 4).
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5.2 Non-Maskable Interrupt
The non-maskable interrupt is accepted unconditionally, even when interrupts are disabled (DI states) in the
interrupt disabled (DI) status. The NMI is not subject to priority control and takes precedence over all the other
interrupts.
The non-maskable interrupt request is input from the NMI pin. When the valid edge specified by bit 0 (ESN0) of
the external interrupt mode register 0 (INTM0) is detected on the NMI pin, the interrupt occurs.
While the service routine of the non-maskable interrupt is being executed (PSW.NP = 1), the acceptance of another
non-maskable interrupt request is kept pending. The pending NMI is accepted after the original service routine of
the non-maskable interrupt under execution has been terminated (by the RETI instruction), or when PSW.NP is cleared
to 0 by the LDSR instruction. Note that if two or more NMI requests are input during the execution of the service
routine for an NMI, the number of NMIs that will be acknowledged after PSW.NP goes to “0”, is only one.
The operation at the execution of pending non-maskable interrupt request differs depending on the V854 operation
mode.
(1) In single-chip mode
The operation is returned to the main routine once and at least one instruction in the main routine is executed
between the end of the first non-maskable interrupt processing and the start of the pending non-maskable
interrupt processing.
(2) In ROM-less mode
The pending non-maskable interrupt processing starts following the end of the first non-maskable interrupt
processing. The operation is not returned to the main routine.
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5.2.1 Operation
If the non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers
control to the handler routine:
(1) Saves the restored PC to FEPC.
(2) Saves the current PSW to FEPSW.
(3) Writes exception code 0010H to the higher half-word (FECC) of ECR.
(4) Sets the NP and ID bits of PSW and clears the EP bit.
(5) Loads the handler address (00000010H) of the non-maskable interrupt routine to the PC, and transfers control.
Figure 5-1 illustrates how the non-maskable interrupt is processed.
Figure 5-1. Non-Maskable Interrupt Processing
NMI input
INTC accepted
Non-maskable interrupt request
CPU processing
1
PSW. NP
0
Interrupt request pending
FEPC
FEPSW
← restored PC
← PSW
ECR. FECC ← 0010H
PSW. NP
PSW. EP
PSW. ID
PC
← 1
← 0
← 1
← 00000010H
Interrupt processing
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Figure 5-2. Accepting Non-Maskable Interrupt Request
(a) If a new NMI request is generated while an NMI service routine is executing:
Main routine
(PSW. NP = 1)
NMI request →
NMI request → NMI request pending because PSW. NP = 1
Pending NMI request processed
(b) If a new NMI request is generated twice while an NMI service routine is executing:
Main routine
NMI request → Kept pending because NMI service program is being processed
NMI request →
NMI request → Kept pending because NMI service program is being processed
Only one NMI request is accepted even though
two or more NMI requests are generated
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5.2.2 Restore
Execution is restored from the non-maskable interrupt processing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
(1) Restores the values of PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0
and the NP bit of PSW is 1.
(2) Transfers control back to the restored PC address and PSW status.
Figure 5-3 illustrates how the RETI instruction is processed.
Figure 5-3. RETI Instruction Processing
RETI instruction
1
PSW. EP
0
1
PSW. NP
0
PC
← EIPC
PC
← FEPC
PSW
← EIPSW
PSW
← FEPSW
Original processing restored
Caution
When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during the non-
maskable interrupt process, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using
the LDSR instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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5.2.3 Non-maskable interrupt status flag (NP)
The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This
flag is set when all the interrupts and requests have been accepted, and masks all interrupt requests and exceptions
to prohibit multiple interrupts from being acknowledged.
31
8 7 6 5 4 3 2 1 0
After reset
00000020H
PSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z
Bit Position
7
Bit Name
NP
Function
NMI Pending
Indicates that NMI interrupt processing is under execution
0: No NMI interrupt processing
1: NMI interrupt currently processing
5.2.4 Noise elimination circuit of NMI pin
NMI pin noise is eliminated with analog delay. The delay time is 60 to 220 ns. The signal input that changes in
less than this time period is not internally acknowledged.
NMI pin is used for canceling the software stop mode. In the software stop mode, noise elimination does not use
system clock for noise elimination because the internal system clock is stopped.
5.2.5 Edge detection function of NMI pin
INTM0 is a register that specifies the valid edge of the non-maskable interrupt (NMI). The valid edge of NMI can
be specified as the rising or falling edge by the ESN0 bit of this register.
This register can be read or written in 8- or 1-bit units.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
FFFFF180H
After reset
00H
INTM0
ESN0
Bit Position
0
Bit Name
ESN0
Function
Edge Select NMI
Specifies valid edge of NMI pin
0: Falling edge
1: Rising edge
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5.3 Maskable Interrupts
Maskable interrupt requests can be masked by interrupt control registers. The V854 has 31 maskable interrupt
sources.
If two or more maskable interrupt requests are generated at the same time, they are accepted according to the
default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control
registers, allowing programmable priority control.
When an interrupt request has been acknowledged, the acceptance of other maskable interrupts is disabled and
the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt processing routine, the interrupt enabled (EI) status is set which
enables interrupts having a higher priority to immediately interrupt the current service routine in progress. Note that
only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested.
To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the
EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI
instruction.
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
g e n e r a t i o n c i r c u i t
H a n d l e r a d d r e s s
x x P R n
P r i o r i t y c o n t r o l l e r
S e l e c t o r
S e l e c t o r
R P U
R P U
R P U
R P U
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5.3.1 Operation
If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine:
(1) Saves the restored PC to EIPC.
(2) Saves the current PSW to EIPSW.
(3) Writes an exception code to the lower half-word of ECR (EICC).
(4) Sets the ID bit of PSW and clears the EP bit.
(5) Loads the corresponding handler address to the PC, and transfers control.
Figure 5-5 illustrates how the maskable interrupts are processed.
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-5. Maskable Interrupt Processing
INT input
INTC accepted
No
Interrupt request?
XXIF = 1
Yes
No
Interrupt unmasked?
XXMK = 0
Yes
Priority higher than
that of interrupt currently
processed?
No
No
No
Yes
Priority higher
than that of other interrupt
request?
Yes
Highest default
priority of interrupt requests
with same priority?
Yes
Maskable interrupt request
Interrupt request pending
CPU processing
1
1
PSW. NP
0
PSW. ID
0
←
←
←
EIPC
EIPSW
ECR. EICC
restored PC
PSW
exception code
Interrupt process pending
PSW. EP ← 0
PSW. ID
PC
← 1
vector address
←
Interrupt processing
The INT input masked by the interrupt controllers and the INT input that occurs while the other interrupt is being
processed (when PSW.NP = 1 or PSW.ID = 1) are internally pended by the interrupt controller. When the interrupts
are unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, the pending INT
input starts the new maskable interrupt processing.
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5.3.2 Restore
To restore execution from the maskable interrupt processing, the RETI instruction is used.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address
of the restored PC.
(1) Restores the values of PC and PSW from EIPC and EIPSW because the EP bit of PSW is 0 and the NP bit
of PSW is 0.
(2) Transfers control to the restored PC address and PSW status.
Figure 5-6 illustrates the processing of the RETI instruction.
Figure 5-6. RETI Instruction Processing
RETI instruction
1
PSW. EP
0
1
PSW. NP
0
PC
← EIPC
PC
← FEPC
PSW
← EIPSW
PSW
← FEPSW
Restores original processing
Caution
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the
maskable interrupt process, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using
the LDSR instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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5.3.3 Priorities of maskable interrupts
The V854 provides multiple interrupt service that accepts an interrupt while servicing another interrupt. Multiple
interrupts can be controlled by priority levels.
There are two types of priority level control: control based on the default priority levels, and control based on the
programmable priority levels that are specified by the interrupt priority level specification bits (xxPRn0 to xxPRn2)
of the interrupt control register (xxICn). When two or more interrupts having the same priority level specified by the
xxPRn0 to xxPRn2 are generated at the same time, the control based on default priority levels services them in the
order of the priority level allocated to each interrupt request type (default priority level) beforehand. For more
information refer to Table 5-1. The programmable priority control customizes interrupt requests into eight levels by
setting the priority level specification flag.
The relation between the programmable priority levels and default priority levels is as follows.
Programmable priority levels > Default priority levels
Note that when an interrupt is acknowledged, the ID flag of PSW is automatically set to “1”. Therefore, when multiple
interrupts are to be used, clear the ID flag to “0” beforehand (for example, by placing the EI instruction into the interrupt
service program) to set the interrupt enable mode.
Remarks xx : Each peripheral unit identifier (OV, CC0, P1, CM1, CM2, CC3, CS, II, SE, SR, ST, AD, P5)
n
: Peripheral unit number (0 to 4)
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Figure 5-7. Example of Interrupt Nesting Process (1/2)
Main routine
EI
Processing of a
EI
Processing of b
Interrupt
request b
(level 2)
Interrupt request a
Interrupt request b is accepted because the priority of
b is higher than that of a and interrupts are enabled.
(level 3)
Processing of c
Interrupt request c
(level 3)
Interrupt request d
(level 2)
Although the priority of interrupt request d is higher
than that of c, d is kept pending because interrupts
are disabled.
Processing of d
Processing of e
EI
Interrupt request e
(level 2)
Interrupt request f is kept pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request f
(level 3)
Processing of f
Processing of g
EI
Interrupt request
(level 1)
h
Interrupt request g
(level 1)
Interrupt request h is kept pending even if interrupts are
enabled because its priority is the same as that of g.
Processing of h
Remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation.
2. The default priority in the figure indicates the relative priority between two interrupt requests.
Caution
The data of the EIPC and EIPSW registers must be saved before executing multiple interrupts.
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-7. Example of Interrupt Nesting Process (2/2)
Main routine
Processing of i
EI
Processing of k
EI
Interrupt
request j
(level 3)
Interrupt request i
(level 2)
Interrupt request j is kept pending because its
priority is lower than that of i. k that occurs after j
is accepted because it has the higher priority.
Interrupt request k
(level 1)
Processing of j
Processing of l
Interrupt requests m and n are kept pending
because processing of l is performed in the
interrupt disabled status.
Interrupt
request m
(level 3)
Interrupt request l
(level 2)
Interrupt request n
(level 1)
Pending interrupt requests are accepted after
processing of interrupt request l.
At this time, interrupt requests n is accepted first
even though m has occurred first because the
priority of n is higher than that of m.
Processing of n
Processing of m
Processing of o
Processing of p
EI
Processing of q
EI
Interrupt request o
(level 3)
EI
Interrupt
request p
(level 2)
Processing of r
Interrupt
request q
(level 1)
EI
Interrupt
request r
(level 0)
If levels 3 to 0 are accepted
Processing of s
Pending interrupt requests t and u are accepted
after processing of s.
Because the priorities of t and u are the same, u is
accepted first because it has the higher default
priority, regardless of the order in which the
interrupt requests have been generated.
Interrupt
request t
(level 2)
Note 1
Note 2
Interrupt request s
(level 1)
Interrupt request u
(level 2)
Processing of u
Processing of t
Notes 1. Lower default priority
2. Higher default priority
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Figure 5-8. Example of Processing Interrupt Requests Simultaneously Generated
Main routine
EI
Interrupt request a (level 2)
Interrupt request b (level 1)
Interrupt request c (level 1)
Interrupt request
b and c are accepted
Processing of interrupt request b
•
•
first according to their priorities.
Because the priorities of b and c
are the same, b is accepted first
because it has the higher default
priority.
Default priority a > b > c
Processing of interrupt request c
Processing of interrupt request a
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5.3.4 Interrupt control register (xxICn)
An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each
maskable interrupt request.
The interrupt control register can be read/written in 8- or 1-bit units.
7
6
5
0
4
0
3
0
2
1
0
Address
FFFFF100H to
FFFFF13CH
After reset
47H
xxICn
xxIFn
xxMKn
xxPRn2 xxPRn1 xxPRn0
Bit Position
Bit Name
xxIFn
Function
7
Interrupt Request Flag
Interrupt request flag
0: Interrupt request not issued
1: Interrupt request issued
xxIFn flag is automatically reset by hardware when interrupt request is accepted.
6
xxMKn
Mask Flag
Interrupt mask flag
0: Enables interrupt processing
1: Disables interrupt processing (pending)
2 to 0
xxPRn2 to xxPRn0 Priority
Specifies eight levels of priorities for each interrupt
xxPRn2
xxPRn1
xxPRn0
Interrupt priority specification bit
Specifies level 0 (highest)
Specifies level 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Specifies level 2
Specifies level 3
Specifies level 4
Specifies level 5
Specifies level 6
Specifies level 7 (lowest)
Remark xx : identification name of each peripheral unit (OV, CC0, P1, CM1, CM2, CC3, CS, II, SE, SR, ST,
AD, P5)
n : peripheral unit number (0 to 4)
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Address and bit of each interrupt control register is as follows:
Address
Register
Bit
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
FFFFF100H
FFFFF102H
FFFFF104H
FFFFF106H
FFFFF108H
FFFFF10AH
FFFFF10CH
FFFFF10EH
FFFFF110H
FFFFF112H
FFFFF114H
FFFFF116H
FFFFF118H
FFFFF11AH
FFFFF11CH
FFFFF11EH
FFFFF120H
FFFFF122H
FFFFF124H
FFFFF126H
FFFFF128H
FFFFF12AH
FFFFF12CH
FFFFF12EH
FFFFF130H
FFFFF132H
FFFFF134H
FFFFF136H
FFFFF138H
FFFFF13AH
FFFFF13CH
OVIC0
OVIF0
OVIF1
CC0IF0
CC0IF1
CC0IF2
CC0IF3
P1IF0
OVMK0
OVMK1
CC0MK0
CC0MK1
CC0MK2
CC0MK3
P1MK0
P1MK1
P1MK2
P1MK3
CM1MK0
CM1MK1
CM2MK0
CM2MK1
CM2MK2
CM2MK3
CM2MK4
CC3MK0
CSMK0
CSMK1
CSMK2
CSMK3
IIMK0
OVPR02 OVPR01 OVPR00
OVPR12 OVPR11 OVPR10
CC0PR02 CC0PR01 CC0PR00
CC0PR12 CC0PR11 CC0PR10
CC0PR22 CC0PR21 CC0PR20
CC0PR32 CC0PR31 CC0PR30
OVIC1
CC0IC0
CC0IC1
CC0IC2
CC0IC3
P1IC0
P1PR02
P1PR12
P1PR22
P1PR32
P1PR01
P1PR11
P1PR21
P1PR31
P1PR00
P1PR10
P1PR20
P1PR30
P1IC1
P1IF1
P1IC2
P1IF2
P1IC3
P1IF3
CM1IC0
CM1IC1
CM2IC0
CM2IC1
CM2IC2
CM2IC3
CM2IC4
CC3IC0
CSIC0
CSIC1
CSIC2
CSIC3
IIIC0
CM1IF0
CM1IF1
CM2IF0
CM2IF1
CM2IF2
CM2IF3
CM2IF4
CC3IF0
CSIF0
CSIF1
CSIF2
CSIF3
IIIF0
CM1PR02 CM1PR01 CM1PR00
CM1PR12 CM1PR11 CM1PR10
CM2PR02 CM2PR01 CM2PR00
CM2PR12 CM2PR11 CM2PR10
CM2PR22 CM2PR21 CM2PR20
CM2PR32 CM2PR31 CM2PR30
CM2PR42 CM2PR41 CM2PR40
CC3PR02 CC3PR01 CC3PR00
CSPR02 CSPR01 CSPR00
CSPR12 CSPR11 CSPR10
CSPR22 CSPR21 CSPR20
CSPR32 CSPR31 CSPR30
IIPR02
IIPR01
IIPR00
SEIC0
SRIC0
STIC0
SEIF0
SRIF0
STIF0
SEMK0
SRMK0
STMK0
ADMK0
P5MK0
P5MK1
P5MK2
P5MK3
SEPR02 SEPR01 SEPR00
SRPR02 SRPR01 SRPR00
STPR02 STPR01 STPR00
ADPR02 ADPR01 ADPR00
ADIC0
P5IC0
ADIF0
P5IF0
P5PR02
P5PR12
P5PR22
P5PR32
P5PR01
P5PR11
P5PR21
P5PR31
P5PR00
P5PR10
P5PR20
P5PR30
P5IC1
P5IF1
P5IC2
P5IF2
P5IC3
P5IF3
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5.3.5 In-service priority register (ISPR)
This register holds the priority level of the maskable interrupt currently accepted. When an interrupt request is
accepted, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while
the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority
is automatically reset to 0 by hardware. However, it is not reset when execution is returned from non-maskable
processing or exception processing.
This register can be only read in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF166H
After reset
00H
ISPR
ISPR7
ISPR6
ISPR5
ISPR4
ISPR3
ISPR2
ISPR1
ISPR0
Bit Position
7 to 0
Bit Name
Function
ISPR7 to
ISPR0
In-Service Priority Flag
Indicates priority of interrupt currently accepted
0: Interrupt request with priority n not accepted
1: Interrupt request with priority n accepted
Remark n: 0 to 7 (priority level)
5.3.6 Maskable interrupt status flag (ID)
The interrupt disable status flag (ID) of the PSW controls the enabling and disabling of maskable interrupt requests.
31
8 7 6 5 4 3 2 1 0
After reset
00000020H
PSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z
Bit Position
5
Bit Name
ID
Function
Interrupt Disable
Indicates enabling/disabling of maskable interrupt processing.
0: Maskable interrupt accepting enabled
1: Maskable interrupt accepting disabled (pending)
It is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value is
also modified by the RETI instruction or LDSR instruction when referencing the
PSW.
Non-maskable interrupt and exceptions are acknowledged regardless of this flag.
When a maskable interrupt is accepted, ID flag is automatically set to 1 by
hardware.
The interrupt request generated during the accepting disabled period (ID:1) is
accepted when the xxIFn bit of xxICn is set to 1, and ID flag is reset to 0.
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5.3.7 Noise elimination
INTP, TI, TCLR, and ADTRG pins are attached with respective digital noise elimination circuit. Thereby, the input
levels of these pins are sampled at each sampling clock (fSMP). As a result, if the same level cannot be detected three
times consecutively, the input pulse is eliminated as a noise.
The noise elimination time for each pin is shown below. The sampling clock of INTP30 pin can be selected from
φ, φ/64, φ/128, or φ/256. For the settings, write values to INTM7 register (refer to 5.3.8 (2) (a) External interrupt
request register 7 (INTM7)).
Pin
INTP00 to INTP03
TCLR0/INTP04
TI0/INTP05
fSMP
Noise Elimination Time
2 to 3 system clocks
φ
φ
φ
φ
φ
φ
φ
φ
INTP10 to INTP13
TI1/INTP14
TI20/INTP20 to TI24/INTP24
ADTRG
INTP30
2 to 3 system clocks
φ/64
128 to 192 system clocks
256 to 384 system clocks
512 to 768 system clocks
φ/128
φ/256
Remark fSMP : Sampling clock
: Internal system clock
φ
Figure 5-9. Example of Noise Elimination Timing
f
SMP
Input signal
2 clocks min.Note 2
3 clocks max.Note 1
Internal signal
Rising edge
detected
Falling edge
detected
Notes 1. Unrecognizable noise pulse width
2. Recognizable signal pulse width
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Cautions 1. In the case that the input pulse width is two to three sampling clocks, it is indefinite whether
the input pulse is detected as a valid edge or eliminated as a noise.
2. To securely detect the level as a pulse, input the same level at least three sampling clocks.
3. When noise is generated in synchronization with sampling, its may recognized as noise. In
such cases, attach a filter to the input pin to eliminate the noise.
5.3.8 Edge detection function
(1) Edge detection of INTP pin (except INTP30 pin), TI pin, TCLR pin, ADTRG pin
These pins can be programmably selected. The valid edge can be selected from the followings:
• Rising edge
• Falling edge
• Both rising and falling edges
The detected INTP signal becomes an interrupt source or capture trigger.
The block diagram of the edge detection of these pins is shown below.
Rising edge
detection
Interrupt request or
each type of trigger
Input signal
Noise elimination
Falling edge
detection
fSMP
φ
ESn1 ESn0
Remark n = 00 to 05, 10 to 14, 20 to 24, 50 to 53, AD
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(2) External interrupt mode registers 1 to 6 (INTM1 to INTM6)
These registers specify the valid edges of external interrupt requests or each type of trigger that are input from
external pins.
The valid edge of each pin can be specified to be the rising, falling, and both rising and falling edges.
Both the registers can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF182H
After reset
00H
ES031
ES030
ES021
ES020
ES011
ES010
ES001
ES000
INTM1
Control pin
INTM2
INTP03
INTP02
INTP01
INTP00
ES111
ES110
ES101
ES141
ES100
ES051
ES131
ES050
ES041
ES040
FFFFF184H
FFFFF186H
FFFFF188H
FFFFF18CH
FFFFF18EH
00H
00H
00H
00H
00H
Control pin
INTM3
INTP11
INTP10
INTP05/TI0
INTP04/TCLR0
ES201
ES200
ES240
ES140
ES230
ES130
ES220
ES121
ES120
ES210
Control pin
INTM4
INTP20/TI20
INTP14/TI1
INTP13
INTP12
ES241
ES231
ES221
ES211
Control pin
INTM5
INTP24/TI24
INTP23/TI23
INTP22/TI22
INTP21/TI21
0
0
0
0
0
0
ESAD1 ESAD0
ADTRG
Control pin
INTM6
ES531
ES530
ES521
ES520
ES511
ES510
ES501
ES500
Control pin
INTP53
INTP52
INTP51
INTP50
Bit Position
Bit Name
Function
7, 5, 3, 1
6, 4, 2, 0
ESn1, ESn0
Edge Select
(n = 00 to 05, Specifies valid edges of INTPm pin and ADTRG pin (m = 00 to 05, 10 to 14, 20 to 24,
10 to 14, 50 to 53)
20 to 24,
50 to 53,
AD)
ESn1
ESn0
Operation
0
0
1
1
0
1
0
1
Falling edge
Rising edge
RFU (reserved)
Both rising and falling edges
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(3) Edge detection of INTP30 pin
To set the valid edge of INTP30 pin, write values to INTM7 register. The valid edge can be selected from
the followings.
• Rising edge
• Falling edge
• Both rising and falling edges
The edge detected INTP30 signal becomes the capture trigger of CC3 register and CP3 register of timer
function. The triggers of CC3 register and CP3 register have reverse edges. However, when both edges are
specified, either one trigger is valid.
The block diagram of the edge detection of INTP30 pin is shown below.
Rising edge
CC3 capture trigger
detection
INTP30
Noise elimination
Falling edge
detection
f
SMP
CP3 capture trigger
φ
φ
/64
ES301 ES300
φ
φ
/128
/256
SCS1 SCS0
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(a) External interrupt mode register 7 (INTM7)
This register specifies the sampling clock (fSMP) and the valid edge of digital noise elimination by INTP30
pins.
This register can be read/written in 8- or 1-bit units.
7
6
5
0
4
0
3
0
2
0
1
0
Address
FFFFF18EH
After reset
00H
INTM7
ES301
ES300
SCS1
SCS0
Bit Position
7, 6
Bit Name
Function
ES301,
ES300
Edge Select
Specifies valid edge of INTP30 pin
ES301
ES300 INTP30, CC3 Capture Trigger
CP3 Capture Trigger
Rising edge
0
0
1
0
1
Falling edge
0
Rising edge
Falling edge
1
1
Without selection edge
Both rising and falling edges
Both rising and falling edges
Not captured
Remark
φ: internal system clock
1, 0
SCS1, SCS0
Sampling Clock Select
Specifies sampling clock
SCS1
SCS0 Sampling Clock Pulse Width Eliminated Minimum Pulse Width
(fSMP)
as Noise
Recognized as Signal
0
0
1
0
1
φ
2/φ
3/φ
0
φ/64
φ/128
φ/256
128/φ
256/φ
512/φ
192/φ
384/φ
768/φ
1
1
Remark
φ: internal system clock
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.3.9 Frequency divider
The V854 can internally divide the frequency of the signals input to P11 to P13 (INTP11 to INTP13) pins. The
divided result becomes external interrupt request signal or timer capture trigger.
Frequency division ratio is set to event divide control register (EDVC) and comparing it with the value in event divide
counter (EDV), and if they coincide, the value becomes the internal event signal, so that the frequency of the INTP
signal is divided. 1 to 64 frequency division is possible for INTP11 and INTP12 signal. If INTP12 signal is divided
1 to 64 , it can be further divided 1 to 128. However, INTP13 signal cannot be used when this function is used.
The block diagram of the INTP11 to INTP13 input is shown below.
RPU
1 to 64 frequency division
(EDV0, EDVC0)
INTP11
INTP12
INTP13
Noise elimination
Noise elimination
Noise elimination
Edge detection
Edge detection
Edge detection
INTCP11
RPU
1 to 64 frequency division
(EDV1, EDVC1)
INTCP12
RPU
1 to 128 frequency division
(EDV2, EDVC2)
Selector
ESE bit
INTCP13
The block diagram of the frequency divider is shown below.
Clear
Input valid edge
EDVn
Coincidence
Internal event signal
EDVCn
Remark n = 0 to 2
(1) Event divide counter 0 to 2 (EDV0 to EDV2)
This register counts the valid edge of the INTPn input signal (n = 11 to 13). The EDV0 and EDV1 registers
are configured with a 6-bit counter, and EDV2 register is configured with a 7-bit counter.
These registers are cleared at the following timings:
• Coincidence of the value in the event divide control register (EDVCn) and the count value
• Write to EDVCn register
Remark n = 0 to 2
These registers can be only read in 8/1-bit units. Edge inputs may not be counted when changing the
specification of the valid edge of the INTMn register (n = 1 to 6).
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7
0
6
0
5
4
3
2
1
0
Address
After reset
00H
EDV05 EDV04 EDV03 EDV02 EDV01 EDV00
EDV0
EDV1
FFFFF1B6H
0
0
FFFFF1B8H
FFFFF1BAH
00H
00H
EDV15 EDV14 EDV13 EDV12 EDV11 EDV10
0
EDV2
EDV25 EDV24 EDV23 EDV22 EDV21 EDV20
EDV26
(2) Event divide control register 0 to 2 (EDVC0 to EDVC2)
These registers set the frequency division ratio of the valid edge of INTPn input signal (n = 11 to 13). The
set value as it is becomes the frequency division ratio. However, when 0 is set, the frequency division ratio
is the maximum, that is, the frequency division of EDVC0 and EDVC1 is 64 and that of EDVC2 is 128.
Bits 7 and 6 of EDVC0 and bit 7 of EDVC2 are fixed to 0, and if 1 is written, it will be ignored.
These registers can be read/written in 8- or 1-bit units.
7
0
6
0
5
4
3
2
1
0
Address
After reset
01H
EDVC05 EDVC04 EDVC03 EDVC02 EDVC01 EDVC00
EDVC0
EDVC1
FFFFF1B0H
0
0
FFFFF1B2H
FFFFF1B4H
01H
01H
EDVC15 EDVC14 EDVC13 EDVC12 EDVC11 EDVC10
0
EDVC2
EDVC25 EDVC24 EDVC23 EDVC22 EDVC21 EDVC20
EDVC26
(3) Event select register (EVS)
This register selects the signal to be input to EDV2 register.
This register can be read/written in 8- or 1-bit units.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
After reset
00H
Address
FFFFF1C0H
EVS
ESE
Bit Position
0
Bit Name
ESE
Function
Event Select
Selects input signal to EDV2 register
0: INTP13 signal
1: INTP12 signal frequency division result by EDVC1 register
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.4 Software Exception
A software exception is generated when the CPU executes the TRAP instruction, and can be always accepted.
5.4.1 Operation
If a software exception occurs, the CPU performs the following processing, and transfers control to the handler
routine:
(1) Saves the restored PC to EIPC.
(2) Saves the current PSW to EIPSW.
(3) Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
(4) Sets the EP and ID bits of PSW.
(5) Loads the handler address (00000040H or 00000050H) of the software exception routine in the PC, and
transfers control.
Figure 5-10 illustrates how a software exception is processed.
Figure 5-10. Software Exception Processing
TRAP instructionNote
CPU processing
EIPC
← restored PC
← PSW
EIPSW
ECR.EICC ← exception code
PSW.EP ← 1
PSW.ID
PC
← 1
← handler address
Exception processing
Note TRAP instruction format: TRAP vector (where vector is 0 to 1FH)
The handler address is determined by the operand of the TRAP instruction (vector). If the vector is 0 to 0FH, the
handler address is 00000040H; if the operand is 10H to 1FH, it is 00000050H.
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5.4.2 Restore
To restore or return execution from the software exception service routine, the RETI instruction is used.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address
of the restored PC.
(1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of PSW is 1.
(2) Transfers control to the restored PC address and PSW status.
Figure 5-11 illustrates the processing of the RETI instruction.
Figure 5-11. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
1
PSW.NP
0
PC
← EIPC
PC
← FEPC
PSW
← EIPSW
PSW
← FEPSW
Original processing restored
Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the
software exception process, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction
immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.4.3 Exception status flag (EP)
The EP flag in PSW is a status flag used to indicate that trap processing is in progress. It is set when a trap occurs.
31
8 7 6 5 4 3 2 1 0
After reset
00000020H
PSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z
Bit Position
Bit Name
EP
Function
6
Exception Pending
Indicates that trap processing is in progress
0: Trap processing not in progress
1: Trap processing in progress
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5.5 Exception Trap
The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V854,
an illegal op code exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap.
An illegal op code exception occurs if the subop code field of an instruction to be executed next is not a valid op
code.
5.5.1 Illegal op code definition
An illegal op code is defined to be a 32-bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B
to 1111B.
15
x
1312 11 10
5 4
0 31
27 26
232221 20
16
x
0 0 1 1
to
x
x
x
x 1 1 1 1 1 1 x
x
x
x
x
x
x
x
x
x
x x x x x x
1 1 1 1
x : don’t care
Caution
It is recommended that the illegal op code not be defined since an instruction may newly be
assigned later.
5.5.2 Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine:
(1) Saves the restored PC to EIPC.
(2) Saves the current PSW to EIPSW.
(3) Writes an exception code (0060H) to the lower 16 bits (EICC) of ECR.
(4) Sets the EP and ID bits of PSW.
(5) Loads the handler address (00000060H) for the exception trap routine to the PC, and transfers control.
Figure 5-12 illustrates how the exception trap is processed.
Figure 5-12. Exception Trap Processing
Exception trap (ILGOP) occurs
CPU processing
EIPC
← restored PC
← PSW
EIPSW
ECR.EICC ← exception code
PSW.EP
PSW.ID
PC
← 1
← 1
← 00000060H
Exception processing
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5.5.3 Restore
To restore or return execution from the exception TRAP, the RETI instruction is used.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
(1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of PSW is 1.
(2) Transfers control to the restored PC address and PSW status.
Figure 5-13 illustrates the processing of the RETI instruction.
Figure 5-13. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
1
PSW.NP
0
PC
← EIPC
PC
← FEPC
PSW
← EIPSW
PSW
← FEPSW
Original processing restored
Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the
exception trap process, in order to restore the PC and PSW correctly during recovery by the
RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction
immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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5.6 Multiple interrupt processing
Multiple interrupt processing is a function that allows the nesting of interrupts. If a higher priority interrupt is
generated and accepted, it will be allowed to stop a current interrupt service routine in progress. Execution of the
original routine will resume once the higher priority interrupt routine is completed.
If an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later
interrupt will be pended.
Multiple processing control of maskable interrupts is performed when in the state of interrupt acceptance (ID =
0). To perform maskable interrupt even in an interrupt processing routine, this control must be set in the state of
acceptance (ID = 0). If a maskable interrupt acceptance or exception is generated during a service program of
maskable interrupt or exception, EIPC and EIPSW must be saved.
The following example shows the procedure of interrupt nesting.
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(1) To accept maskable interrupts in service routine
Service routine of maskable interrupt or exception
...
...
• Saves EIPC to memory or register
• Saves EIPSW to memory or register
• EI instruction (enables interrupt acceptance)
...
...
← Accepts maskable interrupt.
...
...
• DI instruction (disables interrupt acceptance)
• Restores saved value to EIPSW
• Restores saved value to EIPC
• RETI instruction
(2) To generate exception in service program
Service program of maskable interrupt or exception
...
...
• Saves EIPC to memory or register
• Saves EIPSW to memory or register
...
• TRAP instruction
← Accepts exception such as TRAP instruction
← Accepts exception such as illegal op code
• Illegal op code
...
• Restores saved value to EIPSW
• Restores saved value to EIPC
• RETI instruction
Priorities 0 to 7 (0 is the highest priority) can be programmed for each maskable interrupt request for multiple
interrupt processing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt
request control register (xxICn) corresponding to each maskable interrupt request. At system reset, the
interrupt request is masked by the xxMKn bit, and the priority level is set to 7 by the xxPRn0 to xxPRn2 bits.
The priorities of maskable interrupts are as follows:
(High)
Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7
(Low)
Interrupt processing that has been suspended as a result of multiple interrupt processing is resumed after the
interrupt processing of the higher priority has been completed and the RETI instruction has been executed.
A pending interrupt request is accepted after the current interrupt processing has been completed and the
RETI instruction has been executed.
Caution Inthenon-maskableinterruptprocessingroutine(timeuntiltheRETIinstructionisexecuted),
maskable interrupts are not accepted but are suspended.
Remarks xx: Each peripheral unit identifier (OV, CC0, P1, CM1, CM2, CC3, CS, II, SE, SR, ST, AD, P5)
n: Peripheral unit number (0 to 4)
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5.7 Interrupt Response Time
Interrupt Response Time from the interrupt request generation to the interrupt processing activation is as follows:
Figure 5-14. Pipeline Operation at Interrupt Request Acknowledge (General Description)
7 to 14 system clocks
4 system clocks
Internal system clock
(CLKOUt output)
Interrupt request
Instruction 1
IF ID EX MEM WB
Instruction 2
IFx IDx
IFx
Instruction 3
INT1 INT2 INT3 INT4
IF ID EX MEM WB
Interrupt acknowledge operation
Instruction (start instruction of
interrupt processing routine)
INT1 to INT4 : interrupt acknowledge processing
IFx
IDx
: invalid instruction fetch
: invalid instruction decode
Interrupt Response Time (internal system clock)
Internal interrupt External interrupt
Condition
Minimum
11
13
Except the condition below:
• In IDLE/software STOP mode
• External bus is accessed
Maximum
18
20
•
Two or more interrupt request non-sample instructions are executed in
succession
• Access to interrupt control register
5.8 Periods Where Interrupt is Not Acknowledged
An interrupt request is acknowledged while an instruction is being executed. However, no interrupt request will
be acknowledged between an interrupt request non-sample instruction and the next instruction.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (vs. PSW)
In the following conditions, an interrupt may not be acknowledged.
(1) Immediately after the RETI instruction execution
(2) Immediately after the data write to the following registers.
• Interrupt control register (xxICn)
• Command register (PRCMD)
• In-service priority register (ISPR)
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[MEMO]
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The clock generator (CG) produces and controls the internal system clock (φ) which is supplied to all the internal
hardware units including the CPU.
6.1 Features
Multiplication function by PLL (Phase Locked Loop) synthesizer
Clock source
• Oscillation through oscillator connection: fXX = φ, φ/5
• External clock input: fXX = φ, 2 × φ, φ/5
Power save control
• HALT mode
• IDLE mode
• Software STOP mode
• Clock output inhibit function
Internal system clock output function
6.2 Configuration
φ
x1
(fXX
CPU and internal peripheral I/O
CLKOUT
)
x2
Clock Generator
CKSEL
CLO
TBC
f
TBC
PLLSEL
Remark
φ
: Internal system clock
fTBC : Time base counter (TBC) input clock (= fXX/2)
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6.3 Selecting Input Clock
The clock generator consists of an oscillator and a PLL synthesizer. It generates, for example, a 32.768 (Max. 33)-
MHz internal system clock (φ) when a 6.5536-MHz crystal resonator or ceramic resonator is connected across the
X1 and X2 pins at 5-x multiplication.
An external clock can be directly connected to the oscillator circuit. In this case, input the clock signal to the X1
pin, and leave the X2 pin open.
The clock generator is provided with two basic operation modes: PLL mode and direct mode. The operation modes
are selected by the CKSEL pin. The CKSEL pin is latched at reset.
CKSEL
Operation Mode
PLL mode
Direct mode
0
1
Caution Use CKSEL pin with a fixed input level. Changing the level during operations of this pin may cause
erroneous operation.
6.3.1 Direct mode
In the direct mode, external clock with frequency twice higher than that of the internal system clock is input. Because
the oscillator circuit and PLL synthesizer do not run, power consumption is significantly reduced. This mode is mainly
used for application systems that operate the V854 in a relatively low frequency. Considering EMI measures, the
PLL mode is recommended when the external clock frequency (fXX) is 32 MHz (internal system clock (φ) = 16 MHz)
or more.
6.3.2 PLL mode
In the PLL mode, an external clock is input by connecting an external oscillator, which is multiplied by the PLL
synthesizer to generate the internal system clock (φ).
The PLL multiplication number that can be selected is either one or five. The PLL multiplication number can be
selected by the PLLSEL pin (refer to 2.3.16 PLLSEL).
PLLSEL
Multiplication
1-x multiplication
5-x multiplication
0
1
Cautions 1. Fix the PLLSEL pin so that the input level does not change (changing the input level of this
pin during operation may cause erroneous operation). When this pin is set in the direct mode
(CKSEL = 1), the PLLSEL pin has no function. Treat it as an unused pin.
2. When using an external by a resonator, use this mode with fXX = 16 MHz max.
At reset, with reference to the input clock frequency (fXX), an internal system clock (φ) that is either equivalent to
the base clock (1 x fXX) or five times the base clock (5 x fXX) is generated depending on whether 1-x or 5-x multiplication
is selected.
In the PLL mode, when the clock supply from the external oscillator or external clock source is stopped, the internal
system clock (φ) based on the freerunning frequency of the voltage-controlled oscillator circuit (VCO) in the clock
generator continues operating. In this case, φ is approximately 1 MHz (target). Do not use this mode expecting to
obtain the freerunning frequency.
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Examples of the clock used in the PLL mode
Multiplication
Internal System Clock Frequency (φ) [MHz]
External Oscillator/External Clock Frequency (fXX) [MHz]
1-x multiplication
33.000
25.000
20.000
16.000
33.000
25.000
20.000
16.000
33.000Note
25.000Note
20.000Note
16.000
5-x multiplication
6.6000
5.0000
4.0000
3.2000
Note Cannot be oscillated by a resonator. Oscillate not higher than 16 MHz.
6.3.3 Clock control register (CKC)
This is an 8-bit register which controls the internal system clock frequency. It can be written only by a specific
combination of instruction sequences so that its contents are not written by mistake due to erroneous program
execution.
This register can be read/written in 8- or 1-bit units.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address
FFFFF072H
After reset
00H
CKC
CKDIV1 CKDIV0
Bit Position
1, 0
Bit Name
Function
CKDIV1,
CKDIV0
Clock Divide
Sets the internal system clock frequency in the PLL mode.
Pins
CKC
Internal System
Operation Mode
Direct mode
Clock (φ)
CKSEL
PLLSEL
CKDIV1
CKDIV0
H
H
H
L
L
L
L
L
L
L
L
Note
0
0
1
fXX/2
Note
Any values
Setting prohibited
Note
L
1
0
0
1
1
0
0
1
1
Any values Setting prohibited
PLL mode (1-x
multiplication)
0
1
0
1
0
1
0
1
fXX/2
L
Setting prohibited
L
fXX/5
L
fXX/10
PLL mode (5-x
multiplication)
H
fXX/5
H
Setting prohibited
H
fXX
H
fXX/2
Note Connect VDD or VSS directly (refer to 2.4 Pin I/O Circuit Type and
Connection of Unused Pins).
Remark H : High level input
L : Low level input
fXX: Input clock
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The sequence of setting data in this register is the same as the power save control register (PSC). However, the
limitation items listed in Cautions 2 for the 3.4.9 Specific registers do not apply. For details, refer to 6.5.2 Control
register.
(1) Example of settings
The example of settings is as below.
Pins
PLLSEL
CKC Register
CKDIV1 CKDIV0
Input Clock
(fXX)
Internal System
Operation Mode
Direct mode
Clock (φ)
CKSEL
H
L
L
L
L
L
L
Note
0
0
16 MHz
8 MHz
PLL mode (1-x
multiplication)
L
L
0
1
1
0
1
1
0
0
1
0
0
1
33 MHz
33 MHz
6.6 MHz
3.3 MHz
33 MHz
6.6 MHz
3.3 MHz
33 MHz
L
33 MHz
PLL mode (5-x
multiplication)
H
H
H
6.6 MHz
6.6 MHz
6.6 MHz
Other than the above
Note Connect directly to VDD or VSS.
Setting prohibited
Remark
H
L
: High level input
: Low level input
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6.4 PLL Lock-up
Following the power-on reset or when existing the software STOP mode is released, a certain length of time will
be required for the PLL to stabilize. This required time is called PLL lock-up time. The status in which the frequency
is not stable is called unlock status and the status in which it has been stabilized is called lock status.
Two system status registers are available to check the stabilization of the PLL frequency: UNLOCK flag that
indicates the stabilization status of the PLL frequency, and PRERR flag that indicates occurrence of a protection error
(for the details of the PRERR flag, refer to 3.4.9 (2) System status register (SYS)).
The SYS register, which contains these UNLOCK and PREERR flags, can be read/written in 8- or 1-bit units.
7
0
6
0
5
0
4
3
0
2
0
1
0
0
Address
FFFFF078H
After reset
0000000xB
SYS
PRERR
UNLOCK
Bit Position
0
Bit Name
UNLOCK
Function
Unlock Status Flag
This is a read-only flag and indicates unlock status of PLL.
It holds “0” as long as lock up status is maintained, and is not changed even if system is
reset.
0 : Indicates lock status
1 : Indicates unlock status
Remark For the description of the PRERR flag, refer to 3.4.9 (2) System status register (SYS).
If the unlock status condition should arise, due to a power or clock source failure, the UNLOCK flag should be
checked to verify that the PLL has stabilized before performing any execution speed dependent operations, such as
real-time processing.
Static processing such as setting of the on-chip hardware units and initialization of the register data and memory
data, however, can be executed before the UNLOCK flag is reset.
The following is the relation between the oscillation stabilization time (the time from the oscillator starts oscillating
until the input wave form stabilizes) and the PLL lockup time (the time until the frequency stabilizes) when using an
oscillator:
Oscillation stabilization time < PLL lockup time
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6.5 Power Save Control
6.5.1 General
The V854 is provided with the following power save or standby modes to reduce power consumption when CPU
operation is not required.
(1) HALT mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues operation but the operating clock
of the CPU stops. The internal peripherals continue to function in reference to the internal system clock. Total
power consumption of the system can be reduced through intermittent operation between normal operation
and HALT modes.
A dedicated instruction (HALT instruction) transfers to the V854 to the HALT mode.
(2) IDLE mode
In this mode, both the CPU clock and the internal system clock are stopped to further reduce power con-
sumption. However, since the clock generator continues to run, normal operation can resume without having
to wait for the oscillator and PLL circuits to stabilize.
Setting the PSC register, which is a specific register, transfers the V854 to the IDLE mode.
The IDLE mode is somewhere between the STOP and HALT modes in terms of clock stabilization time and
power consumption, and is used in applications where the clock oscillation time should be eliminated but low
power consumption is required.
Caution When inputting external clocks, continue the supply of clocks.
(3) Software STOP mode
In this mode, the CPU clock, the internal system clock, and the clock generator are stopped, reducing power
consumption to just the leakage current. In this state, power consumption is minimized.
Setting the PSC register, which is a specific register, transfers the V854 to the software STOP mode.
(a) PLL mode
Setting the register by software transfers the V854 to the software STOP mode. As soon as the oscillator
circuit stops, the clock output of the PLL synthesizer is stopped. After the software STOP mode has been
released, it is necessary to allow for stabilization time of the oscillator and system clock. Moreover, the
lock up or stabilization time of the PLL may also be necessary, depending on the application.
(b) Direct mode
The software STOP mode cannot be used in direct mode.
(4) Clock output inhibit
Output of the system clock from the CLKOUT pin is prohibited.
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The operations of the clock generator in the normal, HALT, IDLE, and software STOP modes are shown in Table
6-1.
By combining and selecting the mode best suited for a specific application, the power consumption of the system
can be effectively reduced.
Table 6-1. Operation of Clock Generator by Power Save Control
Oscillator
Circuit
Clock Supply
to Peripheral
I/O
PLL
Clock Supply
to CPU
Clock Source
Standby Mode
Synthesizer
(OSC)
PLL mode
Oscillation by
Normal
crystal oscillator
External clock
HALT
IDLE
x
x
x
x
x
STOP
Normal
HALT
IDLE
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
STOP
Normal
HALT
IDLE
x
x
x
x
x
Direct mode
x
x
x
x
x
STOP
: Operates
: Stops
x
Status Transition Diagram
Released by RESET, NMI input, or
maskable interrupt request
Normal
HALT mode setting
Released by RESET or NMI input
Released by RESET or
NMI input
HALT
Software STOP mode setting
IDLE mode setting
IDLE
Software STOP
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6.5.2 Control registers
(1) Power save control register (PSC)
This is an 8-bit register that controls the power save mode. This is a specific register, and only the access
by the specific sequence is valid during write cycles. For details, refer to 3.4.9 Specific registers.
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
0
2
1
0
0
Address
FFFFF070H
After reset
PSC
DCLK1 DCLK0
TBCS
CESEL
IDLE
STP
Note
Bit Position
7, 6
Bit Name
Function
DCLKn
(n = 1, 0)
Disable CLKOUT
Specifies operation mode of CLKOUT pin
DCLK1
DCLK0
Mode
0
0
1
1
0
1
0
1
Normal output mode
RFU (reserved)
RFU (reserved)
Clock output inhibit mode
5
4
TBCS
Time Base Count Select
Selects a number of dividing of time base counter, and specifies oscillation stabilization time.
0: 215/fTBC (s)
1: 216/fTBC (s)
For details, refer to explanation of “Time base counter (TBC)” in section 6.6 “Specifying
Oscillation Stabilization Time”.
CESEL
Crystal/External Select
Specifies functions of X1 and X2 pins
0: Oscillator connected to X1 and X2 pins
1: External clock connected to X1 pin
When CESEL = 1, the software STOP mode cannot be used.
2
1
IDLE
STP
IDLE Mode
Specifies IDLE mode.
When “1” is written to this bit, IDLE mode is entered.
When IDLE mode is released, this bit is automatically reset to “0”.
STOP Mode
Specifies software STOP mode.
When “1” is written to this bit, STOP mode is entered.
When STOP mode is released, this bit is automatically reset to “0”.
Note 00H (in ROM-less mode 1 and 2, in single-chip mode 2)
C0H (in single-chip mode 1 and the PROM mode)
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6.5.3 HALT mode
(1) Entering and operation status
In the HALT mode, the clock generator (oscillator circuit and PLL synthesizer) operates, while the operating
clock of the CPU stops. The internal peripherals continue to function in reference to the internal system clock.
The total lower consumption of the system can be reduced by entering the HALT mode during the idle time
of the CPU.
This mode is entered by the HALT instruction.
In the HALT mode, program execution is stopped, but the contents of the registers and internal RAM
immediately before entering the HALT mode are retained. The on-chip peripheral functions that are not
dependent on the instruction processing of the CPU continue to operate.
Table 6-2 shows the status of each hardware unit in the HALT mode.
Table 6-2. Operating Status in HALT Mode
Function
Clock Generator
Internal System Clock
CPU
Operating Status
Operates
Operates
Stops
I/O Port
Retained
Operates
Peripheral Function
Internal Data
Status of internal data before setting of HALT mode, such
asCPUregisters,status,data,andinternalRAMcontents,
are retained.
AD0 to AD15
High impedanceNote
External
Expansion
Mode
A16 to A23
LBEN, UBEN
R/W
RetainedNote
High-impedance when HLDAK = 0
High level
outputNote
DSTB, WRL,
WRH, RD
ASTB
HLDAK
Operates
CLKOUT
CLO
Clock output (when clock output is not disabled)
Retained (CLE bit of the CLOM register = 0)
Clock output (CLE bit of the CLOM register = 1)
Note The instruction fetch operation continues even after the HALT instruction
has been executed, until the internal instruction prefetch queue becomes
full. After the queue has become full, the operation is stopped in the status
indicated in the above Table 6-2.
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(2) Releasing HALT mode
The HALT mode can be released by the non-maskable interrupt request, an unmasked maskable interrupt
request, or a RESET signal input.
(a) Releasing by interrupt request
The HALT mode is unconditionally released by the NMI request or an unmasked maskable interrupt
request, regardless of the priority. However, if the HALT mode is set in an interrupt processing routine,
the operation will differ as follows:
(i) If an interrupt request with a priority lower than that of the interrupt request under execution is
generated, the HALT mode is released, but the newly generated interrupt request is not accepted.
The new interrupt request will be kept pending.
(ii) If an interrupt request with a priority higher (including NMI request) than the interrupt request under
execution is generated, the HALT mode is released, and the interrupt request is also accepted.
Operation after HALT mode has been released by interrupt request
Releasing Source
NMI request
Interrupt Enable (EI) Status Interrupt disable (DI) Status
Branches to handler address
Maskable interrupt request Branches to handler address Executes next instruction
or executes next instruction
(b) Releasing by RESET signal input
The same operation as the normal reset operation is performed.
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6.5.4 IDLE mode
(1) Entering and operation status
In this mode, both the CPU clock and the internal system clock are stopped to further reduce power
consumption. However, since the clock generator continues to run, normal operation can resume without
having to wait for the oscillator and PLL circuit to stabilize.
The IDLE mode is entered when the PSC register is programmed by the store (ST/SST) instruction or bit
manipulation (SET1/CLR1/NOT1) instruction.
Execution of the program is stopped in the IDLE mode, but the contents of the registers and internal RAM
immediately before entering the IDLE mode are retained. The on-chip peripheral functions are stopped in this
mode. External bus hold request (HLDRQ) is not accepted.
Table 6-3 shows the hardware status in the IDLE mode.
Table 6-3. Operating Status in IDLE Mode
Function
Clock Generator
Internal System Clock
CPU
Operating Status
Operates
Stops
Stops
I/O Port
Retained
Stops
Peripheral Function
Internal Data
Status of all internal data immediately before IDLE mode
is entered, such as CPU registers, status, data, and
internal RAM contents, are retained.
AD0 to AD15
High-impedance
External
Expansion
Mode
A16 to A23
LBEN, UBEN
R/W
DSTB, WRL,
WRH, RD
ASTB
HLDAK
CLKOUT
CLO
Low level output
RetainedNote
Note Set the CLE bit of the CLOM register to 0 before switching over to the IDLE
mode.
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(2) Releasing IDLE mode
The IDLE mode is released by the NMI signal input or RESET signal input.
(a) Releasing by NMI signal input
The NMI request is accepted and serviced as soon as the IDLE mode has been released.
If the IDLE mode is entered in the NMI processing routine, however, only the IDLE mode is released, and
the interrupt will not be accepted. The interrupt request will be retained and kept pending.
The interrupt processing that is started by the NMI signal input when the IDLE mode is released is treated
in the same manner as a normal NMI interrupt that is processed (because there is only one vector address
of the NMI interrupt). Therefore, if it is necessary to distinguish between the two types of NMI interrupts,
a software flag should be defined in advance, and the flag must be set before setting the IDLE flag by
the store/bit manipulation instruction. By checking this flag during the NMI interrupt processing, the NMI
used to released the IDLE mode can be distinguished from the normal NMI.
(b) Releasing by RESET signal input
The same operation as the normal reset operation is performed.
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6.5.5 Software STOP mode
(1) Entering and operation status
In this mode, the CPU clock, the internal system clock, and the clock generator are stopped, reducing power
consumption to only leakage current. In this state, power consumption is minimized.
The software STOP mode is entered by programming the PSC register (Specific register) using the store (ST/
SST) or bit manipulation (SET1/CLR1/NOT1) instruction (refer to 3.4.9 Specific register).
It is necessary to ensure the oscillation stabilization time of the oscillator circuit after the software STOP mode
has been released, when the oscillator connection mode (CESEL bit = “0”) are set.
In the software STOP mode, program execution is stopped, but all the contents of the registers and internal
RAM immediately before entering the STOP mode are retained. The on-chip peripheral function also stops
operation.
Table 6-4 shows the hardware status in the software STOP mode.
Table 6-4. Operating Status in Software STOP Mode
Function
Clock Generator
Internal System Clock
CPU
Operating Status
Stops
Stops
Stops
I/O PortNote 1
Retained
Stops
Peripheral Function
Internal DataNote 1
Status of all internal data immediately before software
STOP mode is set, such as CPU registers, status, data,
and internal RAM contents, are retained.
AD0 to AD15
High-impedance
External
Expansion
Mode
A16 to A23
LBEN, UBEN
R/W
DSTB, WRL,
WRH, RD
ASTB
HLDAK
CLKOUT
CLO
Low level output
RetainedNote 2
Notes 1. When the value of VDD is within the operating range.
Even if VDD drops below the minimum operating voltage, the contents
of the internal RAM can be retained if the data retention voltage VDDDR
is maintained.
2. Set the CLE bit of the CLOM register to 0 before switching over to the
software STOP mode.
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(2) Releasing software STOP mode
The STOP mode is released by the NMI signal input or RESET signal input.
It is necessary to ensure the oscillation stabilization time when releasing from the STOP mode in the PLL mode
(CKSEL bit = “0”) and oscillator connection mode (CESEL bit = “0”).
Moreover, the lock up time of the PLL may also be necessary, depending on the application. For details, refer
to section 6.4 PLL Lock-up.
(a) Releasing by NMI signal input
When the STOP mode is released by the NMI signal, the NMI request is also accepted.
If the STOP mode is set in an NMI processing routine, however, only the STOP mode is released, and
the interrupt is not accepted. The interrupt request is retained and kept pending.
NMI interrupt processing on releasing STOP mode
The interrupt processing that is started by the NMI signal input when the STOP mode is released is treated
in the same manner as a normal NMI interrupt that is processed (because there is only one handler address
of the NMI interrupt). Therefore, if it is necessary to distinguish between the two types of NMI interrupts,
a software flag should be defined in advance, and the flag must be set before setting the STOP flag by
the store/bit manipulation instruction. By checking this flag during the NMI interrupt processing, the NMI
used to released the STOP mode can be distinguished from the normal NMI.
(b) Releasing by RESET signal input
The operation same as the normal reset operation is performed.
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6.6 Specifying Oscillation Stabilization Time
The time required for the oscillator circuit to become stabilized after the STOP mode has been released can be
specified in the following two ways:
(1) Securing time using internal time base counter (NMI pin input)
When the valid edge is input to the NMI pin, the STOP mode is released. When the inactive edge is input
to the pin, the time base counter (TBC) starts counting, and the time required for the clock output from the
oscillator circuit to become stabilized is specified by that count time.
~
Oscillation stabilization time (Active level width after valid edge of NMI input has been detected) + (Count
time of TBC)
After a specific time has elapsed, the system clock output is started, and execution branches to the handler
address of the NMI interrupt.
STOP mode set
Oscillation waveform
System clock
STOP status
NMI input
Oscillator circuit stops
Count time of time
base counter
During inactivity, the NMI pin should be kept at the inactive level (e.g. when the valid edge is specified to be
the falling edge).
If an operation to enter the STOP mode is performed while a valid edge has been input to the NMI pin before
the CPU accepts the interrupt, the STOP mode will immediately be released. If the clock generator is driven
by a PLL (CKSEL = 0) and an oscillator (CESEL = 0), program execution is started after the oscillation
stabilization time specified in the time base counter has elapsed.
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CHAPTER 6 CLOCK GENERATOR FUNCTION
(2) Securing time by signal level width (RESET pin input)
The STOP mode is released when the falling edge is input to the RESET pin.
The time required for the clock output from the oscillator circuit to become stabilized is specified by the low-
level width of the signal input to the RESET pin.
After the rising edge has been input to the RESET pin, operation of the internal system clock begins, and
execution branches to the vector address that is used when the system is reset.
STOP mode set
Oscillation waveform
System clock
STOP status
RESET signal
Internal system
reset signal
Oscillator stabilization time
secured by RESET
Oscillator circuit stops
Time base counter (TBC)
The time base counter (TBC) is used to secure the oscillation stabilization time of the oscillator circuit
when the software STOP mode is released.
• In oscillator connecting mode (CESEL = 0)
TBC counts the oscillation stabilization time after the STOP mode is released, and the execution
of a program is started after the counting is completed.
In both the PLL mode (CKSEL = 0) and oscillator connecting mode (CESEL = 0), the count clock of TBC
is selected by the TBCS bit of the PSC register and the following count time can be set.
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Table 6-5. Example of Count Time
TBCS
Frequency Division
Count Time
fXX = 5.0 MHz
13.1 ms
26.2 ms
fXX = 6.6 MHz
9.8 ms
19.6 ms
fXX = 25.0 MHz
2.6 ms
5.2 ms
fXX = 33.0 MHz
2.0 ms
0
1
215/fTBC
216/fTBC
4.0 ms
fTBC: fXX/2
Figure 6-1. Block Configuration
f
TBC
Overflow
Oscillation stabilization time
control circuit
CG
TBC (15/16 bits)
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6.7 Clock Output Control
The V854 can output CLKOUT signal which has the same frequency as that of the system clock and CLO signal
which is the frequency division of the system clock.
•
•
CLKOUT signal = φ (system clock)
CLO signal = φ, φ/2, φ/4, φ/8, φ/16
The V854 can also be used as a 1-bit output port.
6.7.1 Configuration
LV
0
0
CLE
0
FS2
FS1
FS0
CLOM register
φ
φ/2
/4
φ
CL0
φ/8
φ
/16
φ
CLKOUT
6.7.2 CLKOUT signal output control
The operation mode of the CLKOUT pin can be selected by the DCLK0 and DCLK1 bits of the PSC register.
By using this operation mode in combination with the HALT, IDLE, or software STOP mode, the power dissipation
can be effectively reduced (for how to write these bits, refer to 6.5.2 Control registers).
Clock output inhibit mode
The clock output from the CLKOUT pin is inhibited.
This mode is ideal for single-chip mode systems or systems that fetch instructions to external expansion devices
or asynchronously accesses data.
Because the operation of CLKOUT is completely stopped in this mode, the power dissipation can be minimized
and radiation noise from the CLKOUT pin can be suppressed.
CLKOUT
(normal mode)
L
(Fixed to low level)
CLKOUT
(clock output inhibit mode)
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The PSC register reset value is 00H in ROMless mode 1 and 2 and single-chip mode 2 and C0H in single-chip
mode 1 and PROM mode. Therefore, the CLKOUT signal is output during the reset period in ROMless mode 1 and
2 and single-chip mode 2. In single-chip mode 1, the CLKOUT signal is not output until the DCLK1 and DCLK0 bits
of the PSC register are set to “11” after reset is released (low level output).
In the PROM mode, the CLKOUT signal is not output (low level output).
6.7.3 CLO signal output control
The clock to be output to CLO pin can be selected by the FS bit of the CLOM register.
CLO pin outputs a signal which has the same level as that of the LV bit when the CLE bit is 0. Signal is output
synchronized with the clock (the frequency selected by the FS bit ) immediately after the CLE bit is set to 1.
Then, if the CLE bit is set to 0, the same level as that of the LV bit is output, and the output operation thereafter
is stopped.
Figure 6-2. CLO Signal Output Timing
(a) When LV = 0
φ/n
CLE
CLO
(b) When LV = 1
/n
φ
CLE
CLO
Remark n = 1, 2, 4, 8, 16
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CHAPTER 6 CLOCK GENERATOR FUNCTION
(1) Clock output mode register (CLOM)
This register controls clock output function. This register can be read/written in 8- or 1-bit units.
7
6
0
5
0
4
3
0
2
1
0
Address
FFFFF3D0H
After reset
00H
CLOM
LV
CLE
FS2
FS1
FS0
Bit Position
7
Bit Name
Function
LV
Level
Selects output level of CLO signal
0 : Low-level output
1 : High-level output
4
CLE
Clock Enable
Controls clock output of CLO signal
0 : Outputs the contents of LV bit
1 : Outputs the clock selected by FS2 to FS0 bits
2 to 0
FS2 to
FS0
Frequency Select
Selects the frequency of CLO signal
FS2
FS1
0
FS0
0
Selection of Frequency
0
φ
0
0
1
φ/2
φ/4
φ/8
φ/16
0
1
0
0
1
1
1
0
0
Others
Setting prohibited
φ: Internal system clock
Remark
Caution Do not change the values of the other bits (LV, FS2 to FS0) during setting of the CLE bit (1).
Do not change the values of other bits (LV, FS2 to FS0) simultaneously with changing the
value of the CLE bit.
(2) 1-bit output port
When the CLE bit is 0, CLO pin outputs the signals of the same level as that of the LV bit. When the contents
of the LV bit is changed, CLO signal changes immediately.
LV
CLO
LV ← 1
LV ← 0
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(3) Operations in standby mode
(a) HALT mode
The status before setting HALT mode is maintained. Clock continues to be output while clock is being
output. When clock output is disabled, the signal of the same level that of the LV bit before HALT mode
is set is output.
(b) Software STOP mode/IDLE mode
Disables clock output before setting these modes (the CLE bit is cleared by software). The signal of the
same level as that of the LV bit before these modes are set is output from the CLO pin.
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[MEMO]
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7.1 Features
Timer 0: 24-bit timer/event counter (1 channel)
• Capture/compare registers: 4
• Can be used as a trigger of A/D converter (CC03 coincidence)
• Set/reset outputs: 2
• Clearing and starting timer
• External input pulse measurement
• Overflow interrupt request and overflow flag
• Applications: measurement of pulse interval and frequency, output of pulses with various waveforms
Timer 1: 24-bit timer/event counter (1 channel)
• Capture registers: 4
• Compare registers: 2
• INTP edge detection circuit with 1 to 64/1 to 128 frequency divider
• Can be used as a trigger of real time output port (CM10 coincidence)
• Overflow interrupt request and overflow flag
• Clearing and starting timer
• Applications: measurement of pulse interval and frequency of software servo, etc.
Timer 2: 16-bit interval timer counter (5 channels)
• Compare registers: 1
• Toggle output: 1
• External input pulse measurement
• Clearing and starting timer
• Applications: interval timer, pulse counter, and pulse output of constant period for software
Timer 3: 16-bit interval timer (1 channel)
• Dedicated capture register: 1
• Capture/compare register: 1
• INTP edge detection circuit with digital noise elimination
• Clearing and starting timer
• Applications: measurement of pulse interval and frequencies such as pulse width measurement of remote
controllers
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
7.2 Basic Configuration
Table 7-1. List of Real-Time Pulse Unit (RPU) Configuration
Timer Bit
Width
Count Clock Register Read/
Clear Condition
Generated
Interrupt
Signal
Capture Trigger
Compare
Match
Write
(R/W)
Trigger
φ/2, φ/4, φ/8,
φ/16, φ/32, φ/64,
φ/128, φ/256,
TI0 pin input
Timer 0 24
TM0
R
• INTOV0 input
INTOV0
—
—
CC00
CC01
CC02
CC03
R/W
• TCLR0 input
INTCC00 INTP00
INTCC01 INTP01
INTCC02 INTP02
INTCC03 INTP03
TO00 (S)
TO00 (R)
TO01 (S)
• INTCC03 input
TO01 (R),
A/D converter
φ, φ/2, φ/4,
φ/8, φ/16, φ/32,
φ/64, φ/128,
φ/256,
Timer 1 24
TM1
R
• INTOV1 input
• Software clear
INTOV1
—
—
—
—
CP10
CP11
INTCP10 INTP10
INTCP11 Frequency division
of INTP11
TI1 pin input
CP12
CP13
CM10
INTCP12 Frequency division
of INTP12
—
—
INTCP13 Frequency division
of INTP12/INTP13
R/W
INTCM10
—
Real time
output port
CM11
TM20
CM20
TM21
CM21
TM22
CM22
TM23
CM23
TM24
CM24
TM3
INTCM11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
φ/2, φ/4, φ/8,
φ/16, φ/32, φ/64,
φ/128, φ/256,
TI2n pin input
(n = 0 to 4)
Timer 2 16
R
• INTCM2n input
• Software clear
—
TO20 (T)
—
R/W
R
INTCM20
—
R/W
R
INTCM21
—
TO21 (T)
—
R/W
R
INTCM22
—
TO22 (T)
—
R/W
R
INTCM23
—
TO23 (T)
—
R/W
R
INTCM24
—
TO24 (T)
—
φ/2, φ/4, φ/8,
φ/16, φ/32, φ/64,
φ/128, φ/256
Timer 3 16
• INTCC3 input
CC3
R/W
R
• Capture trigger of CC3 INTCC3
INTP30
—
CP3
• Software clear
—
—
—
Remark
φ
: Internal system clock
S/R : Set/reset
: Toggle output
T
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(1) Timer 0 (24-bit timer/event counter)
Clear and
count control
Noise
elimination
Edge
detection
TCLR0/INTP04
TI0/INTP05
INTOV0/
INTP04/
INTP05
Noise
elimination
Edge
detection
φ/2
φ/4
TM0 (24)
OVF0
φ/256
Noise
Edge
INTP00
INTP01
INTP02
INTP03
CC00 (24)
CC01 (24)
CC02 (24)
CC03 (24)
Q
S
elimination
detection
TO00
TO01
Noise
elimination
Edge
detection
RNote
Q
Q
Q
Noise
elimination
Edge
detection
S
Noise
elimination
Edge
detection
RNote
A/D converter
INTCC00/INTP00
INTCC01/INTP01
INTCC02/INTP02
INTCC03/INTP03
Note Reset priority.
Remark φ: Internal system clock
(2) Timer 1 (24-bit timer/event counter)
CS1
Clear and
Noise
elimination
Edge
detection
INTOV1/
INTP14
count control
TI1/INTP14
φ
φ/2
TM1 (24)
OVF1
φ/256
Noise
Edge
INTP10
INTP11
INTP12
CP10 (24)
CP11 (24)
CP12 (24)
CP13 (24)
CM10 (24)
CM11 (24)
elimination
detection
Noise
elimination
Edge
detection
1 to 64
frequency division
Noise
elimination
Edge
detection
1 to 64
frequency division
1 to 128
frequency division
Noise
elimination
Edge
detection
INTP13
INTCM10
RTP
INTCM11
INTCP10
INTCP11
INTCP12
INTCP13
Remark φ: Internal system clock
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(3) Timer 2 (16-bit interval timer counter)
CS2
INTCM2n/INTP2n
Clear & start
control
Noise
elimination
Edge
detection
TI2n/INTP2n
φ/2
φ/4
TM2n (16)
CM2n (16)
OVF2n
φ/256
T
Q
TO2n
Remark n : 0 to 4
φ : Internal system clock
(4) Timer 3 (16-bit interval timer)
CS3
Clear & start
control
φ/2
φ/4
TM3 (16)
OVF3
φ/256
Noise
elimination
Edge
CC3 (16)
CP3 (16)
INTP30
detection
INTCC3
Edge
detection
φ
φ/64
φ/128
φ/256
Remark φ: Internal system clock
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7.2.1 Timer 0
(1) Timers 0, 0L (TM0, TM0L)
TM0 functions as a 24-bit interval timer, free-running timer or event counter for external signals. It is used
to measure cycles and frequency, and also for pulse generation.
Only 32-bit read access is enabled for TM0 (however, the high-order 8 bits are fixed to 0), and only 16-bit read
access is enabled for TM0L.
To read the low-order 24 bits of timer 0, specify TM0 with word access, and to read the low-order 16 bits only,
specify TM0 with half-word access.
31
24 23
0
0
Address
FFFFF250H
After reset
00000000H
TM0
00000000
15
Address
FFFFF264H
At reset
0000H
TM0L
TM0 counts up the internal count clock or external count clock. The timer is started or stopped by the CE0
bit of timer control register 00 (TMC00).
(2) Capture/compare registers 00 to 03 (CC00 to CC03, CC00L to CC03L)
The capture/compare registers are 24-bit registers connected to TM0. They can be used as capture registers
or compare registers depending on the specification of timer control register 01 (TMC01).
32-bit read/write access is enabled for CC0n (however, the high-order 8 bits are fixed to 0, and are ignored
during write operation), and 16-bit read/write access is enabled for CC0nL.
To access the low-order 24 bits or the low-order 16 bits of these registers, specify CC0n and CC0nL,
respectively.
31
24 23
0
0
Addresses
FFFFF254H to
FFFFF260H
After reset
Undefined
CC0n
00000000
15
Addresses
FFFFF266H to
FFFFF26CH
After reset
Undefined
CC0nL
Remark n = 0 to 3
(a) When used as a capture register
When a capture/compare register is used as a capture register, it detects the valid edge of the
corresponding external interrupt INTPn (n = 10 to 13) as a capture trigger. Timer 0 latches the count value
in synchronization with the capture trigger (capture operation). The latched value is held by the capture
register until the next capture operation is performed.
(b) When used as a compare register
When a capture/compare register is used as a compare register, it compares its contents with the value
of the timer at each clock tick.
Compareregisterssupporttheset/resetoutputfunction. Inotherwords, theysetorresetthecorresponding
timer output synchronously with the coincidence signal generation.
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
7.2.2 Timer 1
(1) Timers 1, 1L (TM1, TM1L)
TM1 functions as a 24-bit free-running timer or event counter. Timers 1 to 14 are used to measure cycles
and frequency, and also for programmable pulse generation.
TM1 is specified in 32-bit access, and TM1L is specified in lower 16-bit acccess. Only 32-bit read access is
enabled for TM1, and only 16-bit read access is enabled for TM1L.
31
24 23
0
0
Address
FFFFF274H
After reset
00000000H
TM1
00000000
15
Address
FFFFF290H
After reset
0000H
TM1L
TM1 counts up the internal count clock or external count clock. The timer is started or stopped by the CE1
bit of timer control register 1 (TMC1).
(2) Capture registers 10 to 13 (CP10 to CP13, CP10L to CP13L)
The capture registers are 24-bit registers connected to TM1. These registers can be only read in 32-bit units.
CP1n is specified in 32-bit access to this register. CP1nL is specified in lower 16-bit access.
Only 32-bit read access is enabled for CP1n, and only 16-bit read access is enabled for CP1nL.
31
24 23
0
0
Addresses
FFFFF280H to
FFFFF28CH
After reset
Undefined
CP1n
00000000
15
Addresses
FFFFF296H to
FFFFF29CH
After reset
Undefined
CP1nL
Remark n = 0 to 3
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(3) Compare registers 10, 11 (CM10, CM11, CM10L, CM11L)
The compare registers are 24-bit registers connected to TM1. These registers can be read or written in 32-
bit units.
CM1n is specified in 32-bit access to this register. CM1nL is specified in lower 16-bit access.
CM1n can be read or written in 32-bit units. The values written in bits 24 to 31 are ignored.
CM1nL can be read or written in 16-bit units. 00H is written in the higher bits (bits 16 to 23) in write access
to CM1nL.
31
24 23
0
0
Addresses
FFFFF278H,
FFFFF27CH
After reset
Undefined
CM1n
00000000
15
Addresses
FFFFF292H,
FFFFF294H
After reset
Undefined
CM1nL
Remark n = 0, 1
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
7.2.3 Timer 2
(1) Timers 20 to 24 (TM20 to TM24)
TM2n is a 16-bit timer and is mainly used as an interval timer for software.
TM2n can be only read in 16-bit units.
15
0
Addresses
FFFFF2B0H to
FFFFF330H
After reset
0000H
TM2n
Remark n = 0 to 4
TM2n is started or stopped by the CE2n bit of timer control register 2n (TMC2n).
The count clock is selected by the TMC2n register from φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256, and TI2n
input.
Caution
When the value of the timer coincides with the value of the compare register (CM2n), the
timer is cleared by the next clock tick. If the division ratio is large and results in a slow
clock period, the timer value may not be cleared to zero yet, if the timer is read immediately
after the occurrence of the coincidence signal interrupt.
The count clock cannot be changed during timer operations.
(2) Compare registers 20 to 24 (CM20 to CM24)
The compare registers are 16-bit registers connected to TM2n. These registers can be read or written in 16-
bit units.
15
0
Addresses
FFFFF2B2H to
FFFFF332H
After reset
Undefined
CM2n
Remark n = 0 to 4
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7.2.4 Timer 3
(1) Timer 3 (TM3)
TM3 is a 16-bit timer and is mainly used as an interval timer for software.
This timer can be only read in 16-bit units.
15
0
Address
FFFFF350H
After reset
0000H
TM3
TM3 is started or stopped by the CE3 bit of timer control register 3 (TMC3).
The count clock is selected by the TMC3 register from φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, or φ/256.
Caution
When the value of the timer matches the value of the compare register (CM4), the timer is
cleared by the next clock tick. If the division ratio is large and results in a slow clock period,
the timer value may not be cleared to zero yet, if the timer is read immediately after the
occurrence of the coincidence signal interrupt.
The count clock cannot be changed during timer operations.
(2) Capture compare register 3 (CC3)
CC3 is a 16-bit register connected to TM3. This register can be read/written in 16-bit units.
15
0
Address
FFFFF352H
After reset
Undefined
CC3
(3) Capture register 3 (CP3)
CP3 is a 16-bit register connected to TM3. This register can be only read in 16-bit units.
15
0
Address
FFFFF354H
After reset
Undefined
CP3
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
7.3 Control Register
(1) Timer control register 00 (TMC00)
TMC00 specifies control of count enable/disable and the count clock of TM0.
This register can be read/written in 8- or 1-bit units.
7
6
5
0
4
0
3
2
1
0
Address
FFFFF240H
After reset
01H
TMC00
CE0
OST0
PRM03 PRM02 PRM01 PRM00
Bit Position
7
Bit Name
Function
CE0
Count Enable
Specifies enable/disable of timer/count.
0 : Timer count disabled (stops at TM0 = 000000H)
1 : Timer count enabled
When TMC02. ECLR0 = 1, the timer does not start counting up until TCLR0 input.
When TMC02. ECLR0 = 0, writing “1” to the CE0 bit triggers count start of the timer.
Therefore, even ECLR0 = 0 is set after setting CE0 with ECLR0 = 1, the timer does not
start.
6
OST0
Overflow Stop
Specifies the operation after overflow of timer.
0 : The timer continues counting after overflow has occurred
1 : The timer retains 000000H and stops after overflow has occurred
The timer resumes counting when the following operation is performed.
When ECLR0 = 0: writing 1 to CE0 bit
When ECLR0 = 1: trigger inputting to timer clear pin (TCLR0)
3 to 0
PRM03 to
PRM00
Prescaler Clock Mode
Selects the count clock frequency.
PRM03 PRM02 PRM01 PRM00
Count Clock
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
φ/2
0
φ/4
0
φ/8
0
φ/16
0
φ/32
0
φ/64
0
φ/128
1
1
φ/256
TI0 input
Setting prohibited
Others
Caution
Remark
Do not change the count clock frequency while the timer operates.
φ: Internal system clock
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(2) Timer control register 01 (TMC01)
TMC01 selects the function of the capture/compare register and sets enable/disable of the timer clear function.
The contents of the register and the timer count operation are not affected even if the contents of TMC01 is
rewritten during timer 0 operation.
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF242H
After reset
00H
TMC01
CMS03 CMS02 CMS01 CMS00
IMS03
IMS02
IMS01
IMS00
Bit Position
7 to 4
Bit Name
Function
CMS03 to
CMS00
Capture/Compare Mode Select
Selects the operation mode of the capture/compare register (CC0n).
Set in combination with the IMS bit. For the contents of the setting, refer to the explanation
of the IMS bit.
3 to 0
IMS03 to
IMS00
Interrupt Mode Select
Selects the interrupt source. Set in combination with the CMS bit.
CMS0n
0
IMS0n
0
CC0n Register Operation Mode/Interrupt Source Selection
Operates as a capture register. Interrupt is generated at capture
timing.
0
1
1
0
Setting prohibited
Operatesasacompareregister. Interruptisgeneratedbycoincidence
signal of compare register. Capture trigger from INTP0n is ignored.
1
1
Operates as a compare register. Interrupt is generated at INTP0n
signal input timing.
Remark n = 0 to 3
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(3) Timer control register 02 (TMC02)
TMC02 selects the function of the capture/compare register and sets enable/disable of the timer clear function.
This register can be read/written in 8- or 1-bit units.
7
0
6
0
5
4
3
0
2
0
1
0
Address
FFFFF244H
After reset
00H
TMC02
IMS05
IMS04
ECLR0 CCLR0
Bit Position
5, 4
Bit Name
Function
IMS05,
Interrupt Mode Select
Selects the interrupt source.
IMS04
IMS05
IMS04
Selection of Interrupt Source
0
0
1
1
0
1
0
1
Overflow interrupt is generated by TM0
Interrupt is generated by INTP04
Interrupt is generated by INTP05
Interrupt is generated by OR of INTP04 and INTP05
1
ECLR0
External Input Timer Clear
Controls clear and start of TM0 by external clear input (TCLR0).
ECLR0
Clear and Start of TM0
0
1
TM0 is not cleared
TM0 is cleared and count up starts
0
CCLR0
Compare Input Timer Clear
Controls clear and start of TM0 by CC03 match.
CCLR0
Clear and Start of TM0
0
1
TM0 is not cleared
TM0 is cleared and count up starts
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(4) Timer control register 1 (TMC1)
TMC1 specifies count enable/disable and controls the count clock of TM1.
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF270H
After reset
01H
TMC1
CE1
OST1
CS1
IMS1
PRM13 PRM12 PRM11 PRM10
Bit Position
7
Bit Name
Function
CE1
Count Enable
Specifies enable/disable of timer count.
0 : Timer count disabled (stops at TM1 = 000000H)
1 : Timer count enabled
6
OST1
Overflow Stop
Specifies the operation after overflow of timer.
0 : The timer continues counting after overflow has occurred
1 : The timer retains 000000H and stops after overflow has occurred
The timer resumes counting when the following operation is performed.
Writing 1 to CE1 bit
Writing 1 to CS1 bit
5
4
CS1
Clear & Start
Controls clear/start of TM1 by software. This bit is always 0 when writing.
0 : Continues counting
1 : Clears TM1 and resumes counting
IMS1
Interrupt Mode Select
Selects interrupt source.
0 : Interrupt occurs by overflow of TM1
1 : Interrupt occurs by INTP14 signal
3 to 0
PRM13 to
PRM10
Prescaler Clock Mode
Selects the count clock frequency.
PRM13 PRM12 PRM11 PRM10
Count Clock
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
φ
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
TI1 input
Caution
Remark
Do not change the count clock frequency while the timer operates.
φ: Internal system clock
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(5) Timer control register 20 to 24 (TMC20 to TMC24)
TMC2n specifies count enable/disable and controls the count clock of TM2n.
This register can be read/written in 8- or 1-bit units.
7
6
5
4
0
3
2
1
0
Address
FFFFF2A0H
After reset
01H
TMC20
TMC21
TMC22
TMC23
TMC24
CE20
IMS20
CS20
PRM203 PRM202 PRM201 PRM200
PRM213 PRM212 PRM211 PRM210
PRM223 PRM222 PRM221 PRM220
PRM233 PRM232 PRM231 PRM230
Address
FFFFF2C0H
After reset
01H
CE21
CE22
CE23
CE24
IMS21
IMS22
IMS23
IMS24
CS21
CS22
CS23
CS24
0
0
0
0
Address
FFFFF2E0H
After reset
01H
Address
FFFFF300H
After reset
01H
Address
FFFFF320H
After reset
01H
PRM243 PRM242 PRM241 PRM240
Bit Position
7
Bit Name
CE2n
Function
Count Enable
Specifies enable/disable of timer count.
0 : Timer count disabled (stops at TM2n = 0000H)
1 : Timer count enabled
6
5
IMS2n
CS2n
Interrupt Mode Select
Selects interrupt source.
0 : Interrupt is generated by coincidence signal of the compare register (CM2n)
1 : Interrupt is generated by INTP2n signal
Clear & Start
Controls clear/start of TM2n by software. This bit is set to 0 when reading.
0 : Continues counting
1 : Clears TM2n and resumes counting
3 to 0
PRM2n3 to
PRM2n0
Prescaler Clock Mode
Selects the count clock frequency.
PRM2n3 PRM2n2 PRM2n1 PRM2n0
Count Clock
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
φ/2
0
φ/4
0
φ/8
0
φ/16
0
φ/32
0
φ/64
0
φ/128
1
1
φ/256
TI2n input
Setting prohibited
Others
Caution
Remark
Do not change the count clock frequency while the timer operates.
φ: Internal system clock
Remark n = 0 to 4
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(6) Timer control register 3 (TMC3)
TMC3 specifies count enable/disable and controls the count clock of TM3.
This register can be read/written in 8- or 1-bit units.
7
6
0
5
4
3
2
1
0
Address
FFFFF340H
After reset
01H
TMC3
CE3
CS3
CMS3
PRM33 PRM32 PRM31 PRM30
Bit Position
7
Bit Name
CE3
Function
Count Enable
Specifies enable/disable of timer count.
0 : Timer count disabled (stops at TM3 = 0000H)
1 : Timer count enabled
5
4
CS3
Clear & Start
Controls clear/start of TM3 by software. This bit is always 0 when reading.
0 : Continues counting
1 : Clears TM3 and resumes counting
CMS3
Capture/Compare Mode Select
Selects capture/compare mode.
0 : Operates as a capture register
1 : Operates as a compare register
3 to 0
PRM33 to
PRM30
Prescaler Clock Mode
Selects the count clock frequency.
PRM33 PRM32 PRM31 PRM30
Count Clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
φ/2
0
φ/4
0
φ/8
0
φ/16
0
φ/32
0
φ/64
0
1
φ/128
φ/256
Others
Setting prohibited
Caution
Remark
Do not change the count clock frequency while the timer operates.
φ: Internal system clock
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(7) Timer output control registers 0 and 1 (TOC0, TOC1)
TOC0, TOC1 control the timer outputs from the TO00, TO01, and TO20 to TO24 pins.
These registers can be read/written in 8- or 1-bit units.
7
0
6
0
5
4
3
2
1
0
Address
FFFFF232H
After reset
00H
TOC0
TOC1
ENTO20 ALV20 ENTO01 ALV01 ENTO00 ALV00
Address
FFFFF234H
After reset
00H
ENTO24 ALV24 ENTO23 ALV23 ENTO22 ALV22 ENTO21 ALV21
Bit Position
7, 5, 3, 1
Bit Name
ENTOn
Function
Enable TO pin
Enables corresponding timer output (TOn).
0: Timer output is disabled. The anti-phase levels of ALVn bit (inactive levels) are output
from TOn pins. Even if coincidence signal is generated from corresponding compare
register, levels of TOn pins do not change.
1: Timer output function is enabled. Timer output changes when coincidence signal
is generated from corresponding compare register. After the timer output has been
enabled before the first coincidence signal is generated, the anti-phase levels of
ALVn bit (inactive levels) are output.
6, 4, 2, 0
ALVn
Active Level TO pin
Specifies the active level of timer output.
0: Active-low
1: Active-high
Remarks 1. The flip-flops of the TO00 and TO01 outputs is a reset priority.
2. n = 00, 01, 20 to 24
Caution
The TO00, TO01 outputs are not changed by the external interrupt signals (INTP00 to
INTP03). When using the TO00 and TO01 signals, specify the capture/compare registers as
compare registers CMS00 to CMS03 (set CMS00 to CMS03 to “1”).
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(8) Timer overflow status register (TOVS)
The overflow flags TM0 to TM3 are assigned.
This register can be read/written in 8- or 1-bit units.
By testing and resetting the TOVS register via software, occurrence of an overflow can be polled.
7
6
5
4
3
2
1
0
Address
FFFFF230H
After reset
00H
TOVS
OVF3
OVF24 OVF23 OVF22 OVF21 OVF20
OVF1
OVF0
Bit Position
7 to 0
Bit Name
OVFn
Function
Overflow Flag
TMn overflow flag.
0: No overflow
1: Overflow
From TM0 and TM1, the interrupt requests (INTOV0 and INTOV1) are generated for the interrupt
controller in synchronization with the overflow. However, the interrupt operation and TOVS are
independent from each other, and the overflow flags (OVF0 and OVF1) from TM0 and TM1 can
be rewritten in the same manner as in other overflow flags.
At this time, the interrupt request flags (OVF0 and OVF1) corresponding to INTOV0 and INTOV1
are not affected.
No transmission is executed to the TOVS register during access from the CPU. Therefore, even
if an overflow occurs when the TOVS register is being read, the overflow flag value will not be
updated and this overflow condition will be reflected the next time the TOVS register is read.
Remark n = 0, 1, 20 to 24, and 3
(9) External interrupt mode registers 1 to 4, 7 (INTM1 to INTM4, INTM7)
These registers set the following 3 types of valid edges:
• Sets valid edge of external interrupt request signal (INTP) when using CP10 to CP13 (timer 1), CC3,
CP3 (timer 3) as capture registers.
• Sets valid edges at external count clock input (TI) of timer 0, timer 1, and timer 2.
• Sets valid edges at timer clear (TCLR0) of timer 0.
For the details, refer to CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
(
(
10) Event divide counter 0 to 2 (EDV0 to EDV2)
Counts valid edges detected by the INTM1 to INTM3 registers. For the details, refer to 5.3 Maskable Interrupt.
11) Event divide control register 0 to 2 (EDVC0 to EDVC2)
Sets the frequency division ratio of event divide counter (EDV0 to EDV2). For the details, refer to5.3. Maskable
Interrupt.
(
12) Event selection register (EVS)
Selects INTP signal to input to the EDV2 register. For the details, refer to 5.3 Maskable Interrupt.
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7.4 Timer 0 Operation
7.4.1 Count operation
Timer 0 functions as a 24-bit interval timer or event counter, as specified by timer control registers 00 to 02 (TMC00
to TMC02).
Timer 0 performs counting up by count clock. Start/stop of counting is controlled by the CE0 bit of timer control
register 00 (TMC00).
(1) Start counting
Timer 0 starts counting by setting the CE0 bit to 1 while the ECLR0 bit of the TMC02 register is 0. However,
when the ECLR0 bit is 1, timer 0 does not start counting until the TCLR0 signal is input. Therefore, it does
not start counting by setting ECLR = 0 after setting CE0 = 1 while ECLR0 = 1.
Writing 1 to TM0 during counting operations (CE0 = 1) does not clear the TM0 register, and timer 0 continues
counting.
(2) Stop counting
Timer 0 stops counting by setting the CE0 bit to 0. If the OST bit of the TMC00 register is set to 1, timer 0
stops operation after occurrence of overflow. However, the value of the timer register can immediately be
cleared by setting CE0 = 0.
Figure 7-1. Basic Operation of Timer 0
Count clock
TM0
000000H 000001H 000002H 000003H
FFFBFEH FFFBFFH
000000H 000001H 000002H 000003H
Count starts
CE0 ← 1
Count disabled
CE0 ← 0
Count starts
CE0 ← 1
Remark ECLR0 = 0
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7.4.2 Count clock selection
An internal or external count clock frequency can be input to timer 0. Which count clock frequency is used is selected
by the PRM00 to PRM03 bits of the TMC00 register.
Caution
Do not change the count clock frequency while the timer operates.
(1) Internal count clock
An internal count clock frequency is selected by the PRM bit of the TMC00 register, from φ/2, φ/4, φ/8, φ/16,
φ/32, φ/64, φ/128, and φ/256.
PRM03
PRM02
PRM01
PRM00
Internal Count Clock
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
(2) External count clock
The signal input to the TI0 pin is counted. At this time, timer 0 operates as an event counter.
To set an external count clock see the table as follows.
PRM03
1
PRM02
1
PRM01
1
PRM00
1
External Count Clock
TI0 input
The valid edge of TI0 is specified by the ES bit of the INTM2 register.
ES051
ES050
Valid Edge
Falling edge
0
0
1
1
0
1
0
1
Rising edge
RFU (reserved)
Both rising and falling edges
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
7.4.3 Overflow
If the TM0 register overflows as a result of counting the count clock frequency to FFFFFFH, a flag is set to the
OVF0 flag of the TOVS registers, and an overflow interrupt (INTOV0) is generated. The value of the OVF0 flag is
retained until it is changed by user application.
The operation of the TM0 register after occurrence of overflow is determined by the OST0 bit.
(1) Operation after occurrence of overflow when OST0 = 0
The TM0 register continues counting.
(2) Operation after occurrence of overflow when OST0 = 1
TM0 = 000000H is retained, and the TM0 register stops counting. At this time TM0 stops with CE0 = 1. Perform
the following to resume counting.
• When ECLR0 = 0 : write 1 to CE0 bit
• When ECLR0 = 1 : trigger input to timer clear pin (TCLR0)
The operation is not affected even if the CE0 bit is set to 1 during count operation.
Figure 7-2. Operation after Occurrence of Overflow (when ECLR0 = 0, OST0 = 1)
Overflow
FFFFFFH
Overflow
FFFFFFH
Count starts
TM0
0
OST0 ← 1
CE0 ← 1
CE0 ← 1
INTOV0
Remark ECLR0 = 0
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7.4.4 Clearing/starting timer
There are three methods of clearing/starting timer 0: by overflow, by TCLR0 signal input, and by CC03 coincidence.
(1) Clearing/starting by overflow
For the details of the operation, refer to 7.4.3 Overflow.
(2) Clearing/starting by TCLR0 signal input
Timer 0 usually starts the count operation when the CE0 bit of the TMC00 register is set to 1. It is also possible
to clear TM0 and start the count operation by using external input TCLR0.
When the valid edge is input to TCLR0 after ECLR0 = 1, OST0 = 0, and the CE0 bit is set to 1, the count operation
is started. If the valid edge is input to TCLR0 during operation, TM0 clears its value and then resume the count
operation (refer to Figure 7-3).
When the valid edge is input to the TCLR0 signal after ECLR0 = 0, OST0 = 1, and the CE0 bit is set to 1,
the count operation is started. When TM0 overflows, the count operation is stopped once and is not resumed
until the valid edge is input to TCLR0. If the valid edge of TCLR0 is detected during count operation, TM0
is cleared and continues counting (refer to Figure 7-4). Timer 0 does not resume counting even if the CE0
bit is set to 1 after occurrence of overflow. When CE0 =0, TCLR0 input is invalid.
Figure 7-3. Clearing/Starting Timer by TCLR0 Signal Input (when ECLR0 = 1, CCLR0 = 0, OST0 = 0)
Overflow
FFFFFFH
Clear & start
Count starts
TM0
0
ECLR0 ← 1
CE0 ← 1
TCLR0
TCLR0
INTOV0
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 7-4. Relations between Clear/Start by TCLR0 Signal Input and Overflow (when ECLR0 = 1, OST0 = 1)
Overflow
FFFFFFH
Count starts
TM0
0
CE0 ← 1
TCLR0 ← 1
TCLR0 ← 1
TCLR0 ← 1
INTOV0
(3) Clearing/starting by CC03 match
Timer 0 usually starts the count operation when CCLR =1, CMS03 = 1, and the CE0 bits of the TMC00 registers
are set to 1. It is also possible to clear TM0 and start the count operation by generation of CC03 match
(INTC03).
When CCLR0 = 1, CMS03 = 1, and the CE0 bit is set to 1, the count operation is started. If CC03 match is
generated during operation, TM0 clears its value and then resumes the count operation (refer to Figure 7-
5).
If a value smaller than the current count value of TM0 is set to CC03 during count operation, overflow of TM0
occurs (refer to Figure 7-6). For the operation after occurrence of overflow, refer to 7.4.3 Overflow.
Figure 7-5. Clearing/Starting Timer by CC03 Match (when CCLR0 =1, OST0 = 0)
Overflow
FFFFFFH
Clear & start
n
Clear & Clear &
start start
k
m
m
Count starts
TM0
0
CCLR0 ← 1
CC03 ← n
CE0 ← 1
CC03 ← m
INTOV0
INTCC03
Remark n > k > m
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Figure 7-6. Relations between Clear/Start by CC03 Coincidence and Overflow Operation
(when CCLR0 = 1, OST0 = 1)
Overflow
FFFFFFH
Clear & start
n
k
Clear & start
m
Count starts
TM0
0
CCLR0 ← 1
CC03 ← n
CE0 ← 1
CC03 ← m
CE0 ← 1
INTOV0
INTCC03
Remark n > k > m
7.4.5 Capture operation
When the TMC01 register is set to a capture register, the capture/compare registers (CC00 to CC03) perform
capture operations that capture and hold the count values of TM0 and load them to a capture register in
asynchronization with an external trigger. The valid edge from the external interrupt request input pin INTP0n is used
as the capture trigger. In synchronization with this capture trigger signal, the count values of TM0 during counting
are captured and loaded to the capture register and the interrupt request INTCC0n is simultaneously issued. The
value of the capture register is retained until the next capture trigger is generated.
When the capture timing to a capture register and write operation to a register by instruction are in contention,
the latter is given priority and the capture operation is ignored.
Table 7-2. Capture Trigger Signal to 24-Bit Capture Register
Capture Trigger Signal
INTP00
Capture Register
CC00/CC00L
Interrupt Request
INTCC00
INTP01
CC01/CC01L
CC02/CC02L
CC03/CC03L
INTCC01
INTCC02
INTCC03
INTP02
INTP03
The valid edge of the capture trigger is set by the external interrupt mode register (INTM1).
When both the rising and falling edges are specified as the capture trigger, the width of an externally input pulse
can be measured. If either the rising or falling edge is specified as the capture trigger, the frequency of the input
pulse can be measured.
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 7-7. Example of TM0 Capture Operation
n
TM0
0
CE0
Capture trigger
CC00
n
INTP00
(Capture trigger)
(Capture trigger)
Remark The capture operation is not performed even if the interrupt request (INTP00) is input when CE0 is
cleared to 0.
Figure 7-8. Example of TM0 Capture Operation (when both edges are specified)
FFFFFFH
D1
TM0 count value
D2
D0
CE0 ← 1
OVF0 ← 1
(Count starts)
(overflow)
Interrupt request
(INTP00)
Capture register
(CC00)
D0
D1
D2
Remark D0 to D2 : count value of TM0
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7.4.6 Compare operation
When the TMC01 register is set as a compare register, the capture/compare registers (CC00 to CC03) perform
a comparison between the value of the compare register with the count values of TM0.
When the count values of TM0 coincide with the value of the compare register programmed in advance, a
coincidence signal is sent to the output control circuit (refer to Figure 7-9). The levels of the timer output pins (TO)
can be changed by the coincidence signal, and an interrupt request signal INTCC can be generated at the same time
(n = 00, 01).
Table 7-3. Interrupt Request Signal from 24-Bit Compare Register
Compare Register
CC00/CC00L
CC01/CC01L
CC02/CC02L
CC03/CC03L
Interrupt Request
INTCC00
Compare Match Trigger
TO00 (S)
INTCC01
TO00 (R)
INTCC02
TO01 (S)
INTCC03
TO01 (R), A/D converter
Remark S/R: set/reset
Figure 7-9. Example of Compare Operation
Timer 0
Count clock
n – 1
n
n + 1
TM0
n
CC00
Coincidence detected
INTCC00
Remark Note that the coincidence signal INTCC is generated immediately after TM0 is incremented as shown
above.
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Timer 0 has two timer output pins: TO00 and TO01.
The count values of TM0 are compared with the values of CC02. When the two values coincide, the output level
of the TO01 pin is set. The count values of TM0 are also compared with the values of CC03. When the two values
coincide, the output levels of the TO01 pin are reset.
Similarly, the count values of TM0 are compared with the values of CC00. When the two values coincide, the output
levels of the TO00 pin are set. The count values of TM0 are also compared with the values of CC01. When the two
values coincide, the output levels of the TO00 pin are reset.
The output levels of the TOn pins can be specified by the TOC0 register (n = 00, 01).
Figure 7-10. Example of TM0 Compare Operation (set/reset output mode)
FFFFFFH
FFFFFFH
CC01
CC01
CC00
CC00
CC00
TM0 count value
0
CE0 ← 1
(Count starts)
OVF0 ← 1
(overflow)
OVF0 ← 1
(overflow)
Interrupt request
(INTCC00)
Interrupt request
(INTCC01)
TO00 pin
ENTO00 ← 1
ALV00 ← 1
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7.5 Timer 1 Operation
7.5.1 Count operation
Timer 1 functions as a 24-bit free-running timer or event counter, as specified by timer control register 1 (TMC1).
Timer 1 performs counting up by count clock. Start/stop of counting is controlled by the CE1 bit of timer control
register 1 (TMC1).
(1) Start counting
Timer 1 starts counting by setting the CE1 bit to 1.
Writing 1 to TM1 during counting operations (CE1 = 1) does not clear the TM1 register, and timer 1 continues
counting.
(2) Stop counting
Timer 1 stops counting by setting the CE1 bit to 0. If the OST bit of the TMC1 register is set to 1, timer 1 stops
operation after occurrence of overflow. However, the value of the timer register can immediately be cleared
by setting CE1 = 0.
Figure 7-11. Basic Operation of Timer 1
Count clock
TM1
000000H 000001H 000002H 000003H
FFFBFEH FFFBFFH
0000H
000001H 000002H 000003H
Count starts
CE1 ← 1
Count disabled
CE1 ← 0
Count starts
CE1 ← 1
7.5.2 Count clock selection
An internal or external count clock frequency can be input to timer 1. Which count clock frequency is used is selected
by the PRM10 to PRM13 bits of the TMC1 register.
Caution
Do not change the count clock frequency while the timer operates.
(1) Internal count clock
An internal count clock frequency is selected by the PRM bits of the TMC1 register, from φ, φ/2, φ/4, φ/8, φ/16,
φ/32, φ/64, φ/128, and φ/256.
PRM13
PRM12
PRM11
PRM10
Internal Count Clock Frequency
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
φ
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) External count clock
The signal input to the TI1 pins is counted. At this time, timer 1 operates as an event counter.
To set an external count clock, see the table below.
PRM13
1
PRM12
1
PRM11
1
PRM10
1
External Count Clock
TI1 input
The valid edge of TI1 is specified by the ES bits of the INTM3 register.
ES141
ES140
Valid Edge
Falling edge
0
0
1
1
0
1
0
1
Rising edge
RFU (reserved)
Both rising and falling edges
7.5.3 Overflow
If overflow occurs as a result of counting the TM1 register count clock frequency to FFFFFFH, a flag is set to the
OVF1 bits of the TOVS register, and an overflow interrupt (INTOV1) is generated.
The value of the OVF1 flag is retained until it is changed by user application.
The operation of the TM1 register after occurrence of overflow is determined by the OST1 bit.
(1) Operation after occurrence of overflow when OST1 = 0
The TM1 register continues counting.
(2) Operation after occurrence of overflow when OST1 = 1
TM1 = 000000H is retained, and the TM1 register stops counting. At this time TM1 stops with CE1 = 1. Perform
the following to resume counting.
• Write 1 to CE1 bit
• Write 1 to CS1 bit
The operation is not affected even if the CE1 bit is set to 1 during count operation.
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Figure 7-12. Operation after Occurrence of Overflow (OST1 = 1)
Overflow
Overflow
FFFFFFH
FFFFFFH
Count starts
TM1
0
OST ← 1
CE1 ← 1
CE1 ← 1
INTOV1
7.5.4 Clearing/starting timer
There are two methods of clearing/starting timer 1: by overflow and by software.
(1) Clearing/starting by overflow
For the details of the operation, refer to 7.5.3 Overflow.
(2) Clearing/starting by software
When the CS1 bit is set to 1 by software, the TM1 register clears its value and starts counting from 0.
However, this setting of the bit is valid only when the value of the CE1 bit is 1.
Figure 7-13. Clearing/Starting Timer by Software (when OST1 = 1)
Overflow
FFFFFFH
Clear & start
Count starts
TM1
0
CE1 ← 1
or
CS1 ← 1
CE1 ← 1
CS1 ← 1
INTOV1
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7.5.5 Capture operation
A capture operation that captures and holds the count values of TM1 and loads them to a capture register in
asynchronization with an external trigger can be performed. The trigger divided by the valid edge from the external
interrupt request input pin INTP1n is used as the capture trigger. In synchronization with this capture trigger signal,
the count values of TM1n during counting, are captured and loaded to the capture register and the interrupt request
INTCP1n is simultaneously issued. The value of the capture register is retained until the next capture trigger is
generated.
Table 7-4. Capture Trigger Signal to 24-Bit Capture Register
Capture Trigger Signal
INTP10
Capture Register
CP10/CP10L
Interrupt Request
INTCP10
Divide of INTP11
CP11/CP11L
CP12/CP12L
CP13/CP13L
INTCP11
INTCP12
INTCP13
Divide of INTP12
Divide of INTP12/INTP13
The valid edge of the INTP1n input is set by the external interrupt mode registers (INTM2, INTM3). The frequency
dividing ratio of the INTCP11 to INTCP13 triggers is set by the EDVCn register and the EVS register. For the details,
refer to 5.3.9 Frequency divider.
Figure 7-14. Example of TM1 Capture Operation
FFFFFFH
TM1
count value
D3
D2
D1
D5
D7
D0
D4
D6
0H
CE1 ← 1
(Count starts)
OVF1 ← 1
(Overflow)
CS1 ← 1
Software
(
)
clear
INTP12
INTCP12
INTCP13
CP12
D0
D1
D2
D3
D2
D4
D5
D6
D5
D7
CP13
Remark ESE ← 1
EDVC1 ← 2
EDVC2 ← 3
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7.5.6 Compare operation
A comparison between the value in a compare register with the count values of TM1 can be performed.
When the count values of TM1 coincide with the value of the compare register programmed in advance, INTCM10
coinciding with CM10 is generated as a trigger of the real time output port. An interrupt request signal INTCM can
be generated at the same time.
Table 7-5. Interrupt Request Signal from 24-Bit Compare Register
Compare Register
CM10/CM10L
Interrupt Request
INTCM10
INTCM11
Compare Match Trigger
Real time output port
—
CM11/CM11L
Figure 7-15. Example of Compare Operation
Timer 1
Count clock
n – 1
n
n + 1
TM1
n
CM10
Coincidence detected
INTCM10
Remark Note that the coincidence signal INTCM is generated immediately after TM1 is incremented as shown
above.
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7.6 Timer 2 Operation
7.6.1 Count operation
Timer 2 functions as a 16-bit interval timer. The operation is specified by the timer control registers 20 to 24 (TMC20
to TMC24).
The operation of timer 2 counts the internal count clocks (φ/2 to φ/256 or the external count clock (TI2n)) specified
by the PRM2n0 to PRM2n3 bits of the TMC2n register.
If the count value of TM2n coincides with the value of CM2n, the value TM2n is cleared while simultaneously a
coincidence interrupt (INTCM2n) is generated and the TO2n signal is output in toggle.
Remark n = 0 to 4
Figure 7-16. Basic Operation of Timer 2
Count clock
TM2n
0000H
0001H 0002H 0003H
FBFEH FBFFH
0000H 0001H 0002H 0003H
Count starts
CE2n ← 1
Count disabled
CE2n ← 0
Count starts
CE2n ← 1
7.6.2 Count clock selection
An internal or external count clock frequency can be input to timer 2. Which count clock frequency is used is selected
by the PRM2n0 to PRM2n3 bits of the TMC2n register (n = 0 to 4).
Caution
Do not change the count clock frequency while the timer operates.
(1) Internal count clock
An internal count clock frequency is selected by the PRM bits of the TMC2n register, from φ/2, φ/4, φ/8, φ/16,
φ/32, φ/64, φ/128, and φ/256.
PRM2n3 PRM2n2 PRM2n1 PRM2n0 Internal Count Clock Frequency
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
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(2) External count clock
The signal input to the TI2n pins are counted. At this time, timer 2 operates as an event counter.
To set an external count clock see the table below.
PRM2n3 PRM2n2 PRM2n1 PRM2n0
External Count Clock
TI2n input
1
1
1
1
The valid edge of TI2n is specified by the ES bits of the INTM3 and the INTM4 registers.
ES2n1
ES2n0
Valid Edge
Falling edge
0
0
1
1
0
1
0
1
Rising edge
RFU (reserved)
Both rising and falling edges
Remark n = 0 to 4
7.6.3 Overflow
If TM2n overflows as a result of counting the internal count clock, a flag is set to the OVF2n bit of the TOVS register
(n = 0 to 4).
7.6.4 Clearing/starting timer
There are two methods of clearing/starting timer 2: by coincidence with a compare register and by software.
(1) Clearing/starting by coincidence signal of a compare register
When the set value of the compare register (CM2n) and the value of TM2n coincide, TM2n clears its value
at the next count clock and starts count operation (n = 0 to 4). At the same time, it generates an interrupt request
signal (INTCM20 to INTCM24) and a timer output trigger.
The interval time set to a compare register can be calculated by the following expression:
(Set value + 1) x Count cycle
For the details, refer to 7.6.5 Compare operation.
(2) Clearing/starting by software
When the value of the CS2n bit of the TMC2n register is set to 1, TM2n clears its value at the next count clock
and starts count operation (n = 0 to 4). However, the setting of this bit is valid only when the value of the CE2n
bit is 1 (n = 0 to 4).
7.6.5 Compare operation
A comparison can be performed with the counter values of TM20 to TM24 and the compare registers (CM20 to
CM24).
When the count value of TM2n coincides with the value of the compare register, a coincidence interrupt (INTCM2n)
is generated. As a result, TM2n is cleared to 0 at the next count timing (refer to Figure 7-17). This function allows
timer 2 to be used as an interval timer.
CM2n can be also set to 0. In this case, a coincidence is detected when TM2n overflows and is cleared to 0, and
INTCM2n is generated. The value of TM2n is cleared to 0 at the next count timing, but INTCM2n is not generated
when a coincidence occurs at this time (refer to Figure 7-18).
Remark n = 0 to 4
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 7-17. Operation with CM2n at 1 to FFFFH
Count clock
Count up
TM2n clear
Clear
TM2n
CM2n
N
0
1
N
Coincidence detection
(INTCM2n)
Remark Interval time = (N + 1) × count clock cycle
N = 1 to 65535 (FFFFH)
Figure 7-18. When CM2n is Set to 0
Count clock
Count up
TM2n clear
Clear
FFFFH
0
0
1
TM2n
CM2n
0
Coincidence detected
(INTCM2n)
Overflow
Remark Interval time = (FFFFH + 2) × count clock cycle
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7.6.6 Toggle output
Toggle output is an operation mode to invert output levels each time the value of the compare register (CM20 to
CM24) coincides with that of CM2n (n = 0 to 4). The relations between timers to be compared and compare register
to timer outputs are shown below.
• TM20, CM20 → TO20
• TM21, CM21 → TO21
• TM22, CM22 → TO22
• TM23, CM23 → TO23
• TM24, CM24 → TO24
Figure 7-19. Example of Toggle Output Operation
n
n
n
n
n
TM20
count value
0H
CE20 ← 1
INTCM20
ALV20
ENTO20
TO20 output
Remark
n
: CM20 register value
: write by software
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7.7 Timer 3 Operation
7.7.1 Count operation
Timer 3 functions as a 16-bit interval timer. The operation is specified by the timer control registers 3 (TMC3).
The operation of timer 3 counts the internal count clocks (φ/2 to φ/256) specified by the PRM30 to PRM33 bits of
the TMC3 register.
If the count value of TM3 coincides with the value of CC3, the value TM3 is cleared while simultaneously a
coincidence interrupt (INTCC3) is generated.
Figure 7-20. Basic Operation of Timer 3
Count clock
TM3
0000H
0001H 0002H 0003H
FBFEH FBFFH
0000H 0001H 0002H 0003H
Count starts
CE3 ← 1
Count disabled
CE3 ← 0
Count starts
CE3 ← 1
7.7.2 Count clock selection
An internal count clock frequency is selected by the PRM30 to PRM33 bits of the TMC3 register, from φ/2, φ/4,
φ/8, φ/16, φ/32, φ/64, φ/128, and φ/256.
Caution
Do not change the count clock frequency while the timer operates.
PRM33
PRM32
PRM31
PRM30
Internal Count Clock Frequency
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
7.7.3 Overflow
If TM3 overflows as a result of counting the internal count clock, a flag is set to the OVF3 bit of the TOVS register.
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7.7.4 Clearing/starting timer
There are three methods of clearing/starting timer 3: by coincidence of compare register, by capture trigger of CC3,
and by software.
(1) Clearing/starting by compare coincidence of CC3
If CC3 is specified as a compare register by the CMS 3 bit, TM3 clears its value at the next count clock and
starts count operation when the set value of the compare register (CC3) and the value of TM3 coincide. At
the same time, an interrupt request (INTCC30) is generated.
The interval timer set to a compare register can be calculated by the following expression:
(Set value + 1) x Count cycle
For the details, refer to 7.7.6 Compare operation.
(2) Clearing/staring by capture trigger of CC3
If CC3 is specified as a capture register by the CMS3 bit, when a capture trigger of CC3 is generated, the
count value of TM3 is captured in CC3, TM3 is cleared, and count operation is started. At the same time,
an interrupt request (INTCC3) is generated.
(3) Clearing/starting by software
When the CS3 bit of the TMC3 register is set to 1, the TM1 register clears its value and start counting from
0.
However, this setting of the bit is valid only when the value of the CE3 bit is 1.
7.7.5 Capture operation
When the TMC3 register is set as a capture register, the capture/compare register (CC3) performs a capture
operation that captures and holds the count value of TM3 and loads it to a capture register in synchronization with
an external trigger and in asynchronization with the count clock. The valid edge from the external interrupt request
input pin INTP30 is used as the capture trigger. In synchronization with this capture trigger signal the count values
of TM3 during counting are captured and loaded to the capture register. The value of the capture register is retained
until the next capture trigger is generated.
When the capture timing of the capture register and the write operation to the register are in contention, the latter
is given priority and the capture operation is ignored.
Table 7-6. Capture Trigger Signal to 16-Bit Capture Register
Capture Source
INTP30
Selection of Valid Edge
Capture Trigger
CC3
CP3
Interrupt Request
↓
↑
↑
↓
—
↑↓
INTCC3
—
↑↓
—
The valid edge of the capture trigger is set by the external interrupt mode register (INTM7). When the CC3 trigger
is set to the falling edge and the CP3 trigger is set to the rising edge, input pulse width and input pulse cycle from
external can be measured with one interrupt (INTCC3).
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Figure 7-21. Example of TM3 Capture Operation (when ES301 = 0, ES300 = 0, CMS3 = 0, CE3 = 1)
D0
D4
TM3
D2
D3
D1
0H
INTP30
CC3 trigger
CP3 trigger
D0
D2
D4
CC3
D1
D3
CP3
INTCC3
7.7.6 Compare operation
When the TM3 register is set as a compare register, the capture/compare register (CC3) performs a comparison
between the value in a compare register and the count value of TM3.
When the count value of TM3 coincides with the value of the compare register programmed in advance, clear and
start of TM3 is performed, and interrupt request signal INTCC3 is generated at the same time.
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7.8 Application Examples
(1) Operation as interval timer (timer 0, timer 2, and timer 3)
The following shows that timer 2 used as an interval timer that repeatedly generates an interrupt request at
time intervals specified by the count value set in advance to compare register CM20. Figure 7-22 shows the
timing. Figure 7-23 illustrates the setting procedure.
Figure 7-22. Example of Timing of Interval Timer Operation (timer 2)
n
n
TM20
count value
0
Count starts
Clear
Clear
Compare register
(CM20)
n
Interrupt request
(INTCM20)
t
Remark n : value of CM20 register
t : interval time = (n + 1) x count clock cycle
Figure 7-23. Setting Procedure of Interval Timer Operation (timer 2)
Interval timer initial setting
; Specifies count clock
Setting of TMC20 register
Sets count value to CM20 register
CM20 ← n
Count starts
TMC20. CE20 ← 1
; Sets CE20 bit to 1
INTCM20 interrupt
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) Pulse width measurement (timer 0, timer 1, and timer 3)
An example of pulse width measurement is shown below.
In this example, the width of the high or low level of an external pulse input to the INTP00 pin is measured.
The value of timer 1 (TM0) is captured to a capture/compare register (CC00) in synchronization with the valid
edge of the INTP00 pin (both the rising and falling edges) and is pended, as shown in Figure 7-24.
To calculate the pulse width, the difference between the count value of TM0 captured to the CC00 register
on detection of the nth valid edge (Dn), and the count value on detection of the (n – 1)th valid edge
(Dn – 1) is calculated. This difference is multiplied by the count clock.
Figure 7-24. Pulse Width Measurement Timing (timer 0)
FFFFFFH
D1
D3
TM0 count value
0
D0
D2
Capture
Capture
Capture
Capture
External pulse input
(INTP00)
Interrupt request
(INTCC00)
Interrupt request
(INTOV0)
Capture/compare register
(CC00)
D0
t1
D1
t2
D2
t3
D3
t1 = (D1 – D0) x count clock cycle
t2 = {(1000000H – D1) + D2} x count clock cycle
t3 = (D3 – D2) x count clock cycle
Remark D0 to D3: count value of TM0
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Figure 7-25. Setting Procedure for Pulse Width Measurement (timer 0)
Pulse width measurenent initial setting
; Specifies count clock
Setting of TMC00 register
Setting of INTM1 register
INTM1. ES001 ← 1
INTM1. ES000 ← 1
; Specifies both edges as valid
edge of INTP00 input signal
Setting of TMC01 register
TMC01. CMS00 ← 0
TMC01. IMS00 ← 0
; Sets capture operation
Initialization of buffer memory
for capture data storage
X0 ← 0
Count starts
TMC00. CE0 ← 1
; Sets CE0 bit to 1
Enables interrupt
INTP00 interrupt
Figure 7-26. Interrupt Request Processing Routine Calculating Pulse Width (timer 0)
INTP00 interrupt processing
Calculation of pulse width
; Xn, Yn : variable
Yn = CC00 – Xn–1
; tn : pulse width
tn = Yn x count clock cycle
Stores nth capture data to
buffer memory
Xn ← CC00
RETI
Caution
If an overflow occurs two times or more between (n – 1)th capture and nth capture, the
pulse width cannot be measured.
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(3) PWM output (timer 0)
Any square wave can be output to timer output pin (TOn) by combining the use of timer 0 and the timer output
function and can be used as a PWM output.
Shown below is an example of PWM output using two capture/compare registers, CC00 and CC01. In this
case, a PWM signal with an accuracy of 24 bits can be output from the TO00 pin. Figure 7-27 shows the timing.
When timer 0 is used as a 24-bit timer, the rising timing of the PWM output is determined by the value set
to capture/compare register CC00, and the falling timing is determined by the value set to capture/compare
register CC01.
The interval frequency of timer output can be changed freely by using compare coincidence of CC03 and by
clearing and starting TM0.
Figure 7-27. Example of PWM Output Timing
FFFFFFH
FFFFFFH
FFFFFFH
CC01
CC01
CC00
D01
CC00
D02
Match
CC00
D00
Match
D10
D11
TM0 count value
0
Match
Match Match
D01
Capture/compare register
(CC00)
D00
D02
Interrupt request
(INTCC00)
Capture/compare register
(CC01)
D10
D11
D12
D1
Interrupt request
(INTCC01)
Timer output
(TO00 pin)
t1
t2
Remark D00 to D02, D10 to D13 : set value of compare register
t1 = {(1000000H – D00) + D01} x count clock cycle
t2 = {(1000000H – D10) + D11} x count clock cycle
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Figure 7-28. Example of PWM Output Programming Procedure
PWM output initial setting
Setting of TOC1n register
TOCn. ENTO0n ← 1
; Specifies active level (high level)
Enables timer ouput
TOCn. ALV0n ← 1
Setting of TMC01 register
; Specifies operation of CC00 and CC01 registers
TMC01. CMS00 ← 1
(specifies compare operation)
TMC01. CMS01 ← 1
Specifies P00 pin as timer
output pin TO00 by PMC0 register
PMC0. PMC00 ← 1
; Specifies count clock of TM0
Setting of TMC00 register
Sets count value to CC00 register
CC00 ← D00
Sets count value to CC01 register
CC01 ← D10
Count starts
TMC00. CE0 ← 1
; Sets CE0 bit to 1
Enables interrupt
INTCC00 interrupt
INTCC01 interrupt
Remark n = 0 and 1
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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 7-29. Example of Interrupt Request Processing Routine, Modifying Compare Value
INTCC00 interrupt processing
INTCC01 interrupt processing
Sets time (number of counts) to set TO00
output to 1 next, to compare register CC00
Sets time (number of counts) to reset TO00
output to 0 next, to compare register CC01
RETI
RETI
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(4) Frequency measurement (timer 0, timer 1, and timer 3)
Timer 0, timer 1, and timer 3 can be used to measure the cycle or frequency of an external pulse input to the
INTP pin.
Shown below is an example where the frequency of the external pulse input to the INTP00 pin is measured
with an accuracy of 24 bits, by combining the use of timer 0 and the capture/compare register CC00.
The valid edge of the INTP00 input signal is specified by the INTM1 register to be the rising edge.
To calculate the frequency, the difference between the count value of TM0 captured to the CC00 register at
the nth rising edge (Dn), and the count value captured at the (n – 1)th rising edge (Dn – 1), is calculated, and
the value multiplied by the count clock frequency.
The frequency measurement exceeding the maximum count value of TM0 is performed by counting the number
of overflow with the INTOV0 overflow interrupt request.
Figure 7-30. Example of Frequency Measurement Timing
FFFFFFH
FFFFFFH
FFFFFFH
TM0 count value
0
D2
D0
D1
Interrupt request
(INTOV0)
External interrupt request
(INTP00)
t1
t2
Capture/compare register
(CC00)
D0
D1
D2
t1 = {(1000000H – D0) + D1} x count clock cycle frequency
t2 = {(1000000H – D1) + D2} x count clock cycle frequency
Remark D0 to D2 : count value of TM0
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Figure 7-31. Example of Set-up Procedure for Frequency Measurement
Cycle measurement initial setting
; Specifies count clock of TM0
Setting of TMC00 register
; Specifies CC00 register
as capture register
Setting of TMC01 register
TMC01. CMS00 ← 0
Setting of INTM1 register
INTM1. ES01 ← 0
; Specifies rising edge as valid
edge of INTP00 signal
INTM1. ES00 ← 1
Initialization of buffer memory
for capture data storage
X0 ← 0
Count starts
TMC00. CE0 ← 1
; Sets CE0 bit to 1
Enables interrupt
INTP00 interrupt
Figure 7-32. Example of Interrupt Request Processing Routine Calculating Cycle
INTP00 interrupt processing
Calculation of cycle
Yn1 = (10000H – Xn–1) + CC00
tn = Yn x count clock cycle
; tn : cycle
Stores nth capture data to
buffer memory
Xn ← CC00
RETI
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7.9 Note
Coincidence is detected by the compare register immediately after the timer value matches the compare register
value, and does not take place in the following cases:
(1) When compare register is rewritten (timer 0 to timer 3)
Count clock
Value of timer
Compare register value
Coincidence detection
n – 1
n
n + 1
m
n
Writing to register
L
Coincidence does not occur
Coincidence does not occur
(2) When timer is cleared by external input (timer 0)
Count clock
Value of timer
n
n – 1
0
External clear input
Compare register value
0000H
Coincidence detection
L
Coincidence does not occur
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(3) When timer is cleared (timer 0, timer 2, and timer 3)
Count clock
Value of timer
FFFEHNote 1
FFFFHNote 2
0
0
1
Internal coincidence clear
Compare register value
Coincidence detection
0000H
↑
Coincidence does not occur
Notes 1. FFFFFEH for timer 0
2. FFFFFFH for timer 0
Remark When timer 0 or timer 1 is operated as a free running timer, the timer value is cleared to 0 when
the timer overflows.
Count clock
FFFEHNote 1 FFFFHNote 2
0
1
2
3
Value of timer
Overflow interrupt
Notes 1. FFFFFEH for timer 0
2. FFFFFFH for timer 0
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CHAPTER 8 SERIAL INTERFACE FUNCTION
8.1 Features
The V854 is provided with three types of serial interfaces which operate as 6-channel transmission/reception
channels. Four channels can be used simultaneously.
There are the following three types of interfaces.
(1) Asynchronous serial interface (UART) : 1 channel
(2) Clocked serial interface (CSI)
(3) I2C bus interface (I2C)
: 4 channels
: 1 channel (µPD703008Y and 70F3008Y only)
The UART transmits/receives 1-byte serial data following a start bit and can perform full-duplex communication.
The CSI uses three signal lines to high-speed synchronous data transfers data (3-wire serial I/O): serial clock
(SCKn), serial input (SIn), and serial output (SOn) lines.
The I2C uses two signal lines, which are serial clock (SCL) and serial data bus (SDA), to transfer data (µPD703008Y
and 70F3008Y only).
Caution UART and CSI0, and CSI1 and I2C share the same pin respectively. Either one of these is selected
according to ASIM0 and ASIM1.
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8.2 Asynchronous Serial Interface (UART)
8.2.1 Features
Transfer rate: 150 bps to 153600 bps (Baud rate generator used, @ φ = 33-MHz operation)
110 bps to 614400 bps (Baud rate generator used, @ φ = 19.660-MHz operation)
110 bps to 38400 bps (Baud rate generator used, @ φ = 16-MHz operation)
Max. 1031 kbps (φ/2 use, @φ = 33-MHz operation)
Full-duplex communication: internal receive buffer (RXB)
Two-pin configuration: TXD: transmit data output pin
RXD: receive data input pin
Receive error detection function
• Parity error
• Framing error
• Overrun error
Interrupt sources: 3
• Receive error interrupt (INTSER)
• Reception completion interrupt (INTSR)
• Transmission completion interrupt (INTST)
Character length of transmit/receive data is specified by ASIMn registers.
Character length: 7, 8 bits
9 bits (when extended)
Parity function: odd, even, 0, none
Transmit stop bit: 1, 2 bits
Dedicated internal baud rate generator
Remark φ : Internal system clock
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8.2.2 Configuration of asynchronous serial interface
The asynchronous serial interface is controlled by the asynchronous serial interface mode register (ASIMn)
and the asynchronous serial interface status register (ASIS). The receive data is stored in the receive buffer (RXB),
and the transmit data is written to the transmit shift register (TXS).
Figure 8-1 shows the configuration of the asynchronous serial interface.
(1) Asynchronous serial interface mode registers (ASIM0, ASIM1)
ASIMn are 8-bit registers that specify the operation of the asynchronous serial interface.
(2) Asynchronous serial interface status registers (ASIS)
ASIS are registers containing flags that indicate receive errors, if any, and a transmit status flag. Each receive
error flag is set to 1 when a receive error occurs, and is reset to 0 when data is read from the receive buffer
(RXB), or when new data is received (if the next data contains an error, the corresponding error flag is set).
The transmit status flag is set to 1 when transmission is started, and reset to 0 when transmission ends.
(3) Reception control parity check
The reception operation is controlled according to the contents programmed in the ASIMn registers. During
the receive operation, errors such as parity error are also checked. If an error is found, the appropriate value
is set to the ASIS registers.
(4) Receive shift register
This shift register converts the serial data received on the RXD pin into parallel data. When it receives 1 byte
of data, it transfers the receive data to the receive buffer.
This register cannot be directly operated.
(5) Receive buffers (RXB, RXBL)
RXB are 9-bit buffer registers that hold receive data. If data of 7 or 8 bits/character is received, 0 is stored
to the most significant bit position of these registers.
If these registers are accessed in 16-bit units, RXB are specified. To access in lower 8-bit units, RXBL are
specified.
While reception is enabled, the receive data is transferred from the receive shift register to the receive buffer
in synchronization with shift-in processing of 1 frame.
When the data is transferred to the receive buffer, a reception completion interrupt request (INTSR) occurs.
(6) Transmit shift registers (TXS, TXSL)
TXS are 9-bit shift registers used for transmit operation. When data is written to these registers, the
transmission operation is started.
A transmission complete interrupt request (INTST) is generated after each complete data frame is transmitted.
When these registers are accessed in 16-bit units, TXS are specified. To access in lower 8-bit units, TXSL
are specified.
(7) Transmission parity control
A start bit, parity bit, and stop bit are appended to the data written to the TXS registers, according to the contents
programmed in the ASIMn registers, to control the transmission operation.
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(8) Selector
Selects the source of the serial clock.
Figure 8-1. Block Diagram of Asynchronous Serial Interface
Internal bus
8
8
16/8
ASIM0
ASIM1
16/8
8
Receive
buffer
RXB
RXBL
TXE RXE PS1 PS0 CL SL SOLS
NOT EBS
ASIS
Transmit
shift register
Receive
shift register
TXS
TXSL
PE FE OVE SOT
RXD
TXD
Receive
control parity
check
Transmission
parity control
INTST
INTSER
INTSR
1
1
Internal system
clock (
16
16
)
1
2
Baud rate
generator
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8.2.3 Control registers
(1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1)
These registers specify the transfer mode of the UART.
They can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
0
Address
FFFFF0C0H
After reset
80H
ASIM0
TXE
RXE
PS1
PS0
CL
SL
SCLS
Bit Position
Bit Name
Function
7
TXE
Transmit Enable
Enable/disable transmission.
0 : Disable transmission
1 : Enable transmission
6
RXE
Receive Enable
Enable/disable reception.
0 : Disable reception
1 : Enable reception
When reception is disabled, the receive shift register does not detect the start bit.
Data is not shifted into the receive shift register and neither is any transfer to the receive
buffer performed. Therefore, the previous contents of the receive buffer are retained. When
reception is enabled, the data is shifted into the receive shift register and transferred to the
receive buffer when one complete frame has been received. A reception completion interrupt
(INTSRn) is generated in synchronization with the transfer to the receive buffer.
If this bit is set to receive disabled status during receive operation, the data being received is
relinquished and the data before the receive operation is started is read out.
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Bit Position
5, 4
Bit Name
PS1, PS0
Function
Parity Select
Specifies parity bit.
PS1
0
PS0
Operation
No parity. Extended bit operation
0
1
0
0 parity
Transmission side → Transmits with parity bit 0
Reception side → Does not generate parity error on reception
1
1
0
1
Odd parity
Even parity
•
•
Even parity
Parity bit is set to “1” when number of bits equal to one in received data is odd. If number
of bits that are one is even, parity bit is cleared to 0. In this way, number of bits that are “1”
in transmit data and parity bit is controlled to become even. During reception, number of bits
that are “1” in receive data and parity bit are counted. If it is odd, parity error occurs.
Odd parity
In contrast to even parity, number of bits included in transmit data and parity bit that are “1”
is controlled to become odd.
Since no parity bit check is performed during reception, no parity error occurs.
•
•
0 parity
Parity bit is cleared to “0” during transmission, regardless of transmit data.
Since no parity bit check is performed during reception, no parity error occurs.
No parity
No parity bit is appended to the transmit data.
Reception is performed on assumption that there is no parity bit. Because no parity bit is used,
parity error does not occur.
Extended bit operation can be specified by EBS bit of ASIM1 register.
3
2
CL
SL
Character Length
Specifies character length of one frame.
0 : 7 bits
1 : 8 bits
Stop Bit Length
Specifies stop bit length.
0 : 1 bit
1 : 2 bits
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Bit Position
0
Bit Name
SCLS
Function
Serial Clock Source
Specifies serial clock.
0 : Specified by BRGC0 and BPRM0
1 : φ/2
•
When SCLS = 1
φ/2 is selected as serial clock source. In asynchronous mode, baud rate is expressed as
follows because sampling rate of x16 is used:
φ/2
Baud rate =
bps
16
Value of baud rate when typical clock is used based on above expression is as follows:
33 MHz 25 MHz 20 MHz 16 MHz 12.5 MHz 10 MHz 8 MHz 5 MHz
φ
Baud rate 1031 K 781 K
625 K
500 K
390 K
312 K
250 K
156 K
•
When SCLS = 0
Baud rate generator output is selected as serial clock source. For details of baud rate
generator, refer to 8.5 Baud Rate Generator 0 to 3 (BRG0 to BRG3).
Caution The operation of UART is not guaranteed if these registers are changed while UART is
transmitting/receiving data.
Remark φ: Internal system clock
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address
FFFFF0C2H
After reset
00H
ASIM1
NOT
EBS
Bit Position
1
Bit Name
Function
NOT
Not
Inverts the output level from TXD pin.
0 : Does not invert the output level
1 : Inverts output level
Use this function to connect an external circuit having inverted level to TXD pin.
0
EBS
Extended Bit Select
Specifies extended bit operation of transmit/receive data when no parity is specified (PS0 = 0,
PS1 = 0).
0 : Disables extended bit operation
1 : Enables extended bit operation
When extended bit operation is enabled, 1 data bit is appended as most significant bit to 8-bit
transmit/receive data, and therefore 9-bit data is communicated.
Extended bit operation is valid only when no parity is specified by ASIM0 register. If zero, even,
or odd parity is specified, specification by EBS bit is invalid, and extended bit is not appended.
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(2) Asynchronous serial interface status register (ASIS)
This register contains three error flags that indicate the receive error status for each character received and
the status of the transmit shift register.
The error flags always indicate the status of an error that has occurred most recently. If two or more errors
occur before the current received data, only the status of the error that has occurred last is retained.
If a receive error occurs, read the data of the receive buffer RXB/RXBL after reading the ASIS register, and
then clear the error flag.
This register can only be read in 8- or 1-bit units.
7
6
0
5
0
4
0
3
0
2
1
0
Address
FFFFF0C4H
After reset
00H
ASIS
SOT
PE
FE
OVE
Bit Position
7
Bit Name
SOT
Function
Status of Transmission
Status flag that indicates transmission operation status.
Set (1) : Beginning of transmission of a data frame (writing to TXS register)
Clear (0) : End of transmission of a data frame (occurrence of INTST)
When serial data transfer begins, this flag will indicate if the transmit shift register is ready to be
written or not.
2
1
0
PE
Parity Error
Status flag that indicates parity error.
Set (1) : Transmit parity and receive parity do not match
Clear (0) : No error; this flag is automatically cleared to 0 when the data is read from the
receive buffer.
FE
Framing Error
Status flag that indicates framing error.
Set (1) : Stop bit is not detected
Clear (0) : No error; this flag is automatically cleared to 0 when the data is read from the
receive buffer.
OVE
Overrun Error
Status flag that indicates overrun error.
Set (1) : Overrun error; Contents of the receive shift register are transferred to the receive
buffer before the previous data has been read by the CPU. This will cause an over
writing of data and the previous information will be lost.
Clear (0) : No error; this flag is automatically cleared to 0 when the data is read from the
receive buffer.
Because contents of receive shift register are transferred to receive buffer each time one frame
of data has been received, if overrun error occurs, next receive data is written over contents of
receive buffer, and previous receive data is discarded.
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(3) Receive buffers (RXB, RXBL)
RXB are 9-bit buffer registers that hold the receive data. When a 7- or 8-bit character is received, the higher
bit of these registers are 0.
When reading 16-bit data from the receive buffer, RXB is specified. When data is read from the lower 8bits,
RXBL is specified.
During the state where reception is enabled the receive data is transferred from the receive shift register to
the receive buffer synchronizing one complete frame of data has been shifted in.
When the receive data is transferred to the receive buffer, a reception completion interrupt request (INTSR)
occurs.
During the state where reception is disabled the data is not transfered into the reception buffer even when
one complete frame of data has been shifted in and the data of the reception buffer is retained. In addition,
the reception completion interrupt request is not generated. RxB is only possible for reading in 16-bit units
and RXBL in 8-/1-bit units.
15 14 13 12 11 10
9
0
8
7
6
5
4
3
2
1
0
Address
FFFFF0C8H
After reset
Undefined
RXB
0
0
0
0
0
0
RXEB RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0
7
6
5
4
3
2
1
0
Address
FFFFF0CAH
After reset
Undefined
RXBL
RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0
Bit Position
8
Bit Name
RXEB
Function
Receive Extended Buffer
Extended bit when 9-bit character is received.
These bits are cleared to zero when 7- or 8-bit character is received.
7 to 0
RXB7 to
RXB0
Receive Buffer
These bits store receive data.
RXB7 is cleared to zero when 7-bit character is received.
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(4) Transmit shift registers (TXS, TXSL)
TXS are 9-bit shift registers for data transmission. The transmit operation is started when data is written to
these registers during transmission enable status.
If data is written to the transmit shift register in the transmission disabled status, the values written are ignored.
Transmission complete interrupt request (INTST) is generated after each complete data frame including TXS
is transmitted.
In the case of access in 16-bit units, TXS is specified. To access the lower 8bits, TXSL is specified.
TXS can only be written to TXS in 16-bit units, and TXSL in 8-bit units.
15 14 13 12 11 10
9
0
8
7
6
5
4
3
2
1
0
Address
FFFFF0CCH
After reset
Undefined
TXS
0
0
0
0
0
0
TXED TXS7 TXS6 TXS5 TXS4 TXS3 TXS2 TXS1 TXS0
7
6
5
4
3
2
1
0
Address
FFFFF0CEH
After reset
Undefined
TXSL
TXS7 TXS6 TXS5 TXS4 TXS3 TXS2 TXS1 TXS0
Bit Position
8
Bit Name
TXED
Function
Transmit Extended Data
Extended bit on transmission of 9-bit/character.
7 to 0
TXS7 to
TXS0
Transmit Shifter
Writes transmit data.
Caution Since the UART does not have a transmit buffer, an interrupt request due to the end of
transmission is not generated but an interrupt request (INTST) is generated in synchronization
with the end of transmission of one frame of data.
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8.2.4 Interrupt request
UART generates the following three types of interrupt requests:
•
•
•
Receive error interrupt (INTSER)
Reception completion interrupt (INTSR)
Transmission completion interrupt (INTST)
Of these three, the receive error interrupt has the highest default priority, followed by the reception completion
interrupt and transmission completion interrupt.
Table 8-1. Default Priority of Interrupts
Interrupt
Receive error
Priority
1
2
3
Reception completion
Transmission completion
(1) Receive error interrupt (INTSER)
A receive error interrupt occurs as a result of ORing the three types of receive errors described in description
of the ASIS registers when reception is enabled.
This interrupt does not occur when reception is disabled.
(2) Reception completion interrupt (INTSR)
The reception completion interrupt occurs if data is received in the receive shift register and then transferred
to the receive buffer when reception is enabled.
This interrupt also occurs when a receive error occurs, but the receive error interrupt has higher priority.
The reception completion interrupt does not occur when reception is disabled.
(3) Transmission completion interrupt (INTST)
Because the UART does not have a transmit buffer, a transmission completion interrupt occurs when one frame
of transmit data including a 7-/8-/9-bit character is shifted out from the transmit shift register.
The transmission completion interrupt is output when the last bit of data has been transmitted.
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8.2.5 Operation
(1) Data format
Full-duplex serial data is transmitted/received.
One data frame of the transmit/receive data consists of a start bit, character bit, parity bit, and stop bit, as
shown in Figure 8-2.
The length of the character bit, parity, and the length of the stop bit in one data frame are specified by the
asynchronous serial interface mode registers (ASIMn).
Figure 8-2. Format of Transmit/Receive Data of Asynchronous Serial Interface
1 data frame
Parity/
Start
bit
Stop
bit
D0
D1
D2
D3
D4
D5
D6
D7
extended
bit
Character bit
• Start bit........................ 1 bit
• Character bit ............... 7/8 bits
• Parity/extended bit...... Even/odd/0/none/extended bit
• Stop bit ........................ 1/2 bits
(2) Transmission
Transmission is started when data is written to the transmit shift registers (TXS or TXSL). The next data is
written to the TXS or TXSL registers by the service routine of the transmission completion interrupt processing
routine (INTST).
(a) Transmission enabled status
Set using the TXE bit of the ASIM0 register.
TXE = 1 : Transmission enabled status
TXE = 0 : Transmission disabled status
However, to set the transmission enabled status, set both the CTXE0 and CRXE0 bits of the clocked serial
interface mode register (CSIM0) to “0”.
Because the UART does not have a CTS (transmission enabled signal) input pin, use a general input port
when checking whether the other is in the reception enabled status.
(b) Starting transmission
In the transmission enabled status, transmission starts when data is written to the transmission shift
register (TXS or TXSL). The transmit data is transferred starting from the start bit with the LSB first. The
start bit, parity bit, and stop bit are automatically appended.
Data cannot be written to the transmission shift register in the transmission disabled status, and values
written are ignored.
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(c) Transmission interrupt request
When one frame of data or character has been completely transferred, a transmission completion interrupt
request (INTST) occurs.
Unless the data to be transmitted next is written to the TXS or TXSL registers, the transmission is aborted.
The communication rate drops unless the next transmit data is written to the TXS or TXSL registers
immediately after transmission has been completed.
Cautions 1. Generally, the transmission completion interrupt (INTST) is generated when the
transmit shift register (TXS or TXSL) is empty. However, by RESET input, the
transmission completion interrupt (INTST) is not generated when the transmit shift
register (TXS or TXSL) is empty.
2. During the transmit operation, writing data into the TXS or TXSL register is ignored
(the data is discarded) until INTST is generated.
Figure 8-3. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
Stop
Parity/
extend
D0
D1
D2
D6
D7
TXD (output)
Start
INTST interrupt
(b) Stop bit length: 2
Parity/
extend
Stop
D0
D1
D2
D6
D7
TXD (output)
Start
INTST interrupt
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(3) Reception
When reception is enabled, sampling of the RXD pin is started, and reception of data begins when the start
bit is detected. Each time one frame of data or character has been received, the reception completion interrupt
(INTSR) occurs. Usually, the receive data is transferred from the receive buffer (RXB or RXBL) to memory
by this interrupt processing.
(a) Reception enabled status
Reception is enabled when the RXE bits of the ASIM registers are set to 1.
RXE = 1: Reception is enabled
RXE = 0: Reception is disabled
However, to set the reception enabled status, set both the CTXE and CRXE bits of the clocked serial
interface mode register (CSIM) to “0”.
When reception is disabled, the receive hardware stands by in the initial status.
At this time, the reception completion interrupt/receive error interrupt does not occur, and the contents
of the receive buffer are retained.
(b) Starting reception
Reception is started when the start bit is detected.
The RXD pin is sampled with the serial clock from baud rate generator. The RXD pin is sampled again
eight clocks after the falling edge of the RXD pin has been detected. If the RXD pin is low at this time,
it is recognized as the start bit, and reception is started. After that, the RXD pin is sampled in 16 clock
ticks.
If the RXD pin is high eight clocks after the falling edge of the RXD pin has been detected, this falling
edge is not recognized as the start bit. The serial clock counter is reinitialized, and the UART waits for
the input of the next falling edge or valid start bit.
(c) Reception completion interrupt request
When one frame of data has been received with RXE = 1, the receive data in the shift register is transferred
to RXB, and a reception completion interrupt request (INTSR) is generated.
If an error occurs, the receive data that contains an error is transferred to the receive buffer (RXB or RXBL),
andthetransmissioncompletioninterrupt(INTSR)andreceiveerrorinterrupt(INTSER)occursimultaneously.
If the RXE bit is reset (0) during receive operation, the receive operation stops immediately. In this case,
the contents of the receive buffer (RXB or RXBL) and the asynchronous serial interface status register
(ASIS) do not change, and neither reception completion interrupt (INTSR) nor reception error interrupt
(INTSER) is generated.
When RXE = 0 (reception disabled), no reception completion interrupt occurs.
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Figure 8-4. Asynchronous Serial Interface Reception Completion Interrupt Timing
Stop
Parity/
extend
D0
D1
D2
D6
D7
RXD (input)
Start
INTSR interrupt
(d) Reception error flag
Three error flags, parity error, framing error, and overrun error flags, are related with the reception
operation.
The receive error interrupt request occurs as a result of ORing these three error flags.
By reading the contents of the ASIS registers, the error which caused the receive error interrupt (INTSER)
can be identified.
The contents of the ASIS registers are reset to 0 when the receive buffer (RXB or RXBL) is read or the
next data frame is received (if the next data contains an error, the corresponding error flag is set).
Receive
Error Cause
Parity error
Framing error
Overrun error
Parity specified during transmission does not coincide with parity of receive data
Stop bit is not detected
Next data is completely received before data is read from receive buffer
Figure 8-5. Receive Error Timing
Stop
Parity/
extend
D0
D1
D2
D6
D7
RXD (input)
Start
INTSR interrupt
INTSER interrupt
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8.3 Clocked Serial Interface 0 to 3 (CSI0 to CSI3)
8.3.1 Features
Number of channels: 4 channels (CSIn)
High transfer speed CSI0, CSI2, CSI3: 8.25 Mbps max. (φ/4 use, φ = 33 MHz)
CSI1: 2.00 Mbps max.
Half duplex communication
Character length: 8 bits
MSB first/LSB first selectable
External serial clock input/internal serial clock output selectable
3 wires: SOn : serial data output
SIn
SCKn : serial clock I/O
Interrupt source: 4
: serial data input
• Transmission/reception completion interrupt (INTCSIn)
Remark n = 0 to 3
φ: Internal system clock
8.3.2 Configuration
CSIn is controlled by the clocked serial interface mode register (CSIMn). The transmit/receive data is read/written
from/to the serial I/O shift register (SIOn) (n = 0 to 3).
(1) Clocked serial interface mode registers (CSIM0 to CSIM3)
CSIMn are 8-bit registers that specify the operation of CSIn.
(2) Serial I/O shift registers (SIO0 to SIO3)
SIOn registers are 8-bit registers that convert serial data into parallel data, and vice versa. SIOn are used
for both transmission and reception.
Data is shifted in (received) or shifted out (transmitted) from the MSB or LSB side.
The actual transmitting and receiving of data is actually performed by writing data to and reading data from
the SIOn registers.
(3) Selector
Selects the serial clock to be used.
(4) Serial clock control circuit
Controls supply of the serial clock to the shift register. When the internal clock is used, it also controls the
clock output to the SCKn pin.
(5) Serial clock counter
Counts the serial clocks being output and the serial clocks received during transmission/reception to check
whether 8-bit data has been transmitted or received.
(6) Interrupt control circuit
Controls whether an interrupt request is generated when the serial clock counter has counted eight serial
clocks.
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Figure 8-6. Block Diagram of Clocked Serial Interface
CSI0
CSIM0
CTXE0 CRXE0 CSOT0 MOD0 CLS01 CLS00
SO latch
D
Q
Serial I/O shift register (SIO0)
SI0
SO0
BRG0
/2
1
2
Serial clock
control circuit
SCK0
Interrupt
control circuit
INTCSI0
Serial clock counter
SI1
SO1Note
CSI1
CSI2
CSI3
SCK1Note
SI2
SO2
SCK2
SI3
SO3
SCK3
Note This is an open-drain pin. When using this pin, connect it to VDD via a resistor.
Remark φ: Internal system clock
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8.3.3 Control registers
(1) Clocked serial interface mode register 0 to 3 (CSIM0 to CSIM3)
These registers specify the basic operation mode of CSIn.
They can be read/written in 8- or 1-bit units (note, however, that bit 5 can only be read).
7
6
5
4
0
3
0
2
1
0
After reset
00H
Address
FFFFF088H
CSIM0
CSIM1
CSIM2
CSIM3
CTXE0 CRXE0 CSOT0
CTXE1 CRXE1 CSOT1
CTXE2 CRXE2 CSOT2
CTXE3 CRXE3 CSOT3
MOD0
CLS01
CLS00
After reset
00H
Address
FFFFF098H
0
0
0
0
0
0
MOD1
MOD2
MOD3
CLS11
CLS21
CLS31
CLS10
CLS20
CLS30
After reset
00H
Address
FFFFF0A8H
After reset
00H
Address
FFFFF0B8H
Bit Position
7
Bit Name
Function
CTXEn
CRXEn
CSI Transmit Enable
Enables or disables transmission.
0 : Disables transmission
1 : Enables transmission
When CTXEn = “0”, both SOn and SIn pins go into high-impedance state.
6
CSI Receive Enable
Disables or enables reception.
0 : Disables reception
1 : Enables reception
If serial clock is received when both transmission is enabled (CTXEn = 1) and reception is
disabled, “0” is input to shift register.
If this bit is set to reception disabled status (CRXEn = 0) during receive operation, the
contents of the SIOn register become undefined.
5
2
CSOTn
CSI Status of Transmission
Indicates that transfer operation is in progress.
Set (1) : Transmission enable and start timing (writing to SIO0 register)
Clear (0) : Transmission cleared and end timing (INTCSI occurs)
This bit is used to check whether writing to serial I/O shift register (SIO) is permitted or not.
Serial data transfer is started by enabling transmission (CTXEn = 1).
MODn
Mode
Specifies operation mode.
0 : MSB first
1 : LSB first
Remark n = 0 to 3
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Bit Position
1, 0
Bit Name
CLSn1, CLSn0 Clock Source
Specifies serial clock.
Function
CLSn1 CLSn0
Specifies Serial Clock
SCKn pin
Input
0
0
1
1
0
1
0
1
External clock
Internal clock
Specified by BPRMn registerNote 1
Output
Output
Output
φ/4Note 2
φ/2Note 2
Notes 1. For setting of BPRMn register, refer to section 8.5 Baud Rate Generator 0 to 3
(BRG0 to BRG3).
2. φ/4 and φ/2 indicate dividing signals (φ : internal system clock).
Remark n = 0 to 3
Caution Set the CLSn1 and CLSn0 bits, in the transmission/reception disable state (CTXEn bit = CRXEn
bit = 0). If these bits are set in a state other than transmission/reception disabled, normal
operation is not guaranteed.
(2) Serial I/O shift register 0 to 3 (SIO0 to SIO3)
These registers convert 8-bit serial data into parallel data, and vice versa. The actual transmitting and receiving
of data is performed by writing data to and reading data from the SIOn registers.
A shift operation is performed when CTXE = “1” or CRXE = “1”.
These registers can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF08AH
After reset
Undefined
SIO0
SIO1
SIO2
SIO3
SIO07
SIO06
SIO05
SIO04
SIO03
SIO02
SIO01
SIO00
Address
FFFFF09AH
After reset
Undefined
SIO17
SIO27
SIO37
SIO16
SIO26
SIO36
SIO15
SIO25
SIO35
SIO14
SIO24
SIO34
SIO13
SIO23
SIO33
SIO12
SIO22
SIO32
SIO11
SIO21
SIO31
SIO10
SIO20
SIO30
Address
FFFFF0AAH
After reset
Undefined
Address
FFFFF0BAH
After reset
Undefined
Bit Position
7 to 0
Bit Name
Function
SIOn7 to
SIOn0
Serial I/O
Data is shifted in (received) or out (transmitted) from MSB or LSB side.
(n = 0 to 3)
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8.3.4 Basic operation
(1) Transfer format
The CSI performs interfacing by using three lines: one clock line and two data lines.
Serial transfer is started by executing an instruction that writes transfer data to the SIOn register.
During transmission, the data is output from the SOn pin in synchronization with the falling edge of SCKn.
During reception, the data input to the SIn pin is latched in synchronization with the rising of SCKn.
SCKn stops when the serial clock counter overflows (at the rising edge of the 8th count), and SCKn remains
high until the next data transmission or reception is started. At the same time, a transmission/reception
completion interrupt (INTCSI) is generated.
Caution
If CTXE is changed from 0 to 1 after the transmit data is sent to the SIOn registers, serial
transfer will not begin.
Remark n = 0 to 3
Input data latched
SCKn
SIn
1
2
3
4
5
6
7
8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SOn
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CSOTn bit
INTCSIn interrupt
Serial transmission/
reception completion
interrupt occurs
Transfer starts in synchronization with falling of SCKn
Execution of SIOn write instruction
Remark n = 0 to 3
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(2) Enabling transmission/reception
Each CSIn has only one 8-bit shift register and does not have a buffer. Transmission and reception are
therefore performed simultaneously.
(a) Transmission/reception enabling condition
The transmission/reception enabling condition of CSIn is specified by the CTXEn and CRXEn bits of the
CSIMn register.
CTXEn
CRXEn
Transmission/Reception Operation
Transmission/reception disabled
Reception enabled
0
0
1
1
0
1
0
1
Transmission enabled
Transmission/reception enabled
Remark n = 0 to 3
Remarks 1. When CTXEn bit is 0, SOn pin output of CSIn becomes high impedance.
When CTXEn bit is 1, the data of the SIOn register of CSIn is output.
2. When CRXEn bit = 0, the shift register input is “0”.
When CRXEn bit = 1, the serial input data is input to the shift register.
3. To receive the transmit data and to check whether bus contention occurs, set CTXEn bit and
CRXEn bit to 1.
(b) Starting transmission/reception
Transmission/reception is started by reading/writing the SIOn registers. Transmission/reception is
controlled by setting the transmission enable bit (CTXEn) and reception enable bit (CRXEn) as follows:
CTXEn
CRXEn
Start Condition
Does not start
0
0
1
1
0
0
1
Reads SIOn registers
Writes SIOn registers
Writes SIOn registers
Rewrites CRXEn bits
0
1
0 → 1
Remark n = 0 to 3
In the above table, note that these bits should be set in advance of data transfer. For example,
if the CTXEn bit is not changed from 0 to 1 before reading data from or writing data to the SIOn registers,
transfer will not begin. The bottom of the table means that, if the CRXEn bit is changed from 0 to 1
when the CTXEn bit is “0”, the serial clock will be generated to initiate receive operation.
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8.3.5 Transmission in CSI0 to CSI3
Transmission is started when data is written to the SIOn register after transmission has been enabled by the clocked
serial interface mode register (CSIMn) (n = 0 to 3).
(1) Starting transmission
Transmission is started by writing the transmit data to the shift register (SIOn) after the CTXE bit of the
clocked serial interface mode registers (CSIMn) has been set (the CRXE bit is cleared to “0”).
If the CTXE bit is reset to 0, the SOn pin goes into a high-impedance state.
(2) Transmitting data in synchronization with serial clock
(a) When internal clock is selected as serial clock
When transmission is started, the serial clock is output from the SCKn pin, and at the same time, data
is sequentially output to the SOn pin from SIOn in synchronization with the falling edge of the serial clock.
(b) When external clock is selected as serial clock
When transmission is started, the data is sequentially output from SIOn to the SOn pin in synchronization
with the falling of the serial clock input to the SCKn pin immediately after transmission has been started.
The shift operation is not performed even if the serial clock is input to the SCKn pin if transmission is not
enabled, and the output level of the SOn pin will not change.
Figure 8-7. Timing of 3-Wire Serial I/O Mode (transmission)
SCKn
1
2
3
4
5
6
7
8
SIn
SOn
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSIn interrupt
Serial transmission/
reception completion
interrupt occurs
Transfer starts in synchronization with falling of SCKn
Execution of SIOn write instruction
Remark n = 0 to 3
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8.3.6 Reception in CSI0 to CSI3
Reception is started if the status is changed from reception disabled to reception enabled status by the clocked
serial interface mode registers (CSIMn) or if the SIOn registers are read by the CPU with reception enabled (n = 0
to 3).
(1) Starting reception
Reception can be started in the following two ways:
<1> Changing the status of the CRXEn bits of the CSIMn registers from “0” (reception disabled) to “1”
(reception enabled)
<2> Reading the receive data from the shift registers (SIOn) when the CRXEn bits of the CSIMn registers
are “1” (reception enabled)
If CRXEn bit of the CSIMn register has already been set to “1”, writing “1” to these bits do not initiate receive
operation. When bit CRXEn = 0, the shift register inputs are “0”.
(2) Receiving data in synchronization with serial clock
(a) When internal clock is selected as serial clock
When reception is started, the serial clock is output from the SCKn pin, and at the same time, data is
sequentially loaded from the SIn pin to SIOn in synchronization with the rising edge of the serial clock.
(b) When external clock is selected as serial clock
When reception is started, the data is sequentially loaded from the SIn pin to SIOn in synchronization
with the rising of the serial clock input to the SCKn pin immediately after reception has been started. The
shift operation is not performed even if the serial clock is input to the SCKn pin when reception is not
enabled.
Figure 8-8. Timing of 3-Wire Serial I/O Mode (reception)
SCKn
1
2
3
4
5
6
7
8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SIn
SOn
INTCSIn interrupt
Serial transmission/
reception completion
interrupt occurs
Transfer starts in synchronization with falling edge of SCKn
Execution of SIOn write instruction
Remark n = 0 to 3
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8.3.7 Transmission/reception in CSI0 to CSI3
Transmission and reception can be executed simultaneously if both transmission and reception are enabled by
the clocked serial interface mode registers (CSIMn) (n = 0 to 3).
(1) Starting transmission/reception
Transmission and reception can be performed simultaneously (transmission/reception operation) when both
the CTXEn and CRXEn bits of the clocked serial interface mode registers (CSIMn) are set to 1.
Transmission/reception can be started by writing the transmit data to the shift register n (SIOn) when both
the CTXEn and CRXEn bits of the CSIMn register are “1” (transmission/reception enabled state)
If CRXEn bit of the CSIMn register has already been set to “1”, writing “1” to this bit does not initiate transmit/
receive operation.
(2) Transmitting data in synchronization with serial clock
(a) When internal clock is selected as serial clock
When transmission/reception is started, the serial clock is output from the SCKn pin, and at the same
time, data is sequentially set to the SOn pin from SIOn in synchronization with the falling edge of the serial
clock. Simultaneously, the data of the SIn pin is sequentially loaded to SIOn in synchronization with the
rising edge of the serial clock.
(b) When external clock is selected as serial clock
When transmission/reception is started, the data is sequentially output from SIOn to the SOn pin in
synchronization with the falling edge of the serial clock input to the SCKn pin immediately after
transmission/reception has been started. The data of the SIn pin is sequentially loaded to SIOn in
synchronization with the rising edge of the serial clock. The shift operation is not performed even if the
serial clock is input to the SCKn pin when transmission/reception is not enabled, and the output level of
the SOn pin does not change.
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Figure 8-9. Timing of 3-Wire Serial I/O Mode (transmission/reception)
SCKn
1
2
3
4
5
6
7
8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SIn
SOn
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSIn
Serial transmission/
reception completion
interrupt occurs
Transfer starts in synchronization with falling edge of SCKn
Execution of SIOn write instruction
Remark n = 0 to 3
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8.3.8 System configuration example
Data 8 bits long is transferred by using three types of signal lines: serial clock (SCKn), serial input (SIn), and serial
output (SOn). This feature is effective for connecting peripheral I/Os and display controllers that have a conventional
clocked serial interface.
To connect two or more devices, a handshake line is necessary.
Various devices can be connected, because it can be specified whether the data is transmitted starting from the
MSB or LSB.
Figure 8-10. Example of CSI System Configuration
(3-wire serial l/O
Master CPU
3-wire serial I/O)
Slave CPU
SCKn
SOn
SCKn
SIn
SIn
SOn
Port (Interrupt)
Port
Port
Interrupt (Port)
Handshake line
Remark n = 0 to 3
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8.4 I2C Bus (µPD703008Y and 70F3008Y only)
8.4.1 Features
I2C bus format
Multi-master serial bus
Serial data automatic discrimination function
Transfer speed: standard mode : 100 Kbps max.
high-speed mode : 400 Kbps max.
Chip select by address
Wake-up function
Acknowledge signal (ACK) control function
Wait signal (WAIT) control function
Arbitration control function
Conflict detection function
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8.4.2 Functions
The following two modes are available for I2C bus.
• Operation stop mode
• I2C (Inter IC) bus mode (supports multi-master)
(1) Operation stop mode
Used when serial transfer is not carried out, reduces power consumption.
(2) I2C bus mode (supports multi-master)
Performs 8-bit data transfer with more than one device, using two lines, each for the serial clock (SCL) and
the serial data bus (SDA).
Conforming to I2C bus format, either “start condition”, “data”, or “stop condition” can be output onto serial data
bus in transmission. These data can be automatically detected by hardware in reception.
Because SCL and SDA are open drain outputs, pull-up resistors are required for the serial clock line and the
serial data bus line.
Figure 8-11. Example of Serial Bus Configuration Using I2C Bus
+VDD +VDD
Serial data bus
Serial clock
Master CPU2
Slave CPU2
Master CPU1
Slave CPU1
SDA
SCL
SDA
SCL
Address 1
Address 0
SDA
SCL
Slave CPU3
Address 2
SDA
SCL
Slave IC
Address 3
SDA
SCL
Slave IC
Address N
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Figure 8-12. Block Diagram of I2C Bus
Internal bus
IIC control register (IICC)
IIC status register (IICS)
IICE LREL WREL SPIE WTIM ACKE STT SPT
MSTS ALD EXC COI TRC ACKD STD SPD
Slave address register (SVA)
Coincidence signal
CLEAR
SET
SO latch
CL0 CL1
Q
D
SDA
IIC shift register (IIC)
Data retention time
correction circuit
Acknowledge
detection circuit
RESET
N-ch open-
drain output
Wake-up
control circuit
Acknowledge
detection circuit
DFC
Start condition
detection circuit
Noise elimination circuit
DFC
Stop condition
detection circuit
Noise elimination circuit
DFC
Serial clock
counter
Interrupt request signal
INTIIC
Noise elimination circuit
SCL
generation circuit
Serial clock
Serial clock wait
control circuit
control circuit
N-ch open-
drain output
Internal system clock (φ )
Prescaler
CLD DAD SMC DFC CL1 CL0
IIC clock selection register (IICL)
Internal bus
CHAPTER 8 SERIAL INTERFACE FUNCTION
8.4.3 Configuration
The I2C bus is configured with the following hardware.
Table 8-2. I2C Bus Configuration
Item
Register
Configuration
IIC shift register (IIC)
Slave address register (SVA)
Control register
IIC clock selection register (IICCL)
IIC status register (IICS)
IIC control register (IICC)
(1) IIC shift register (IIC)
IIC is a register that converts 8-bit serial data into parallel data, and vice versa. IIC is used both for transmission
and reception.
The actual transmission and reception of data is performed by writing data to and reading data from the IIC
shift register.
This register is set by 8-bit memory manipulation instruction. It becomes 00H by RESET input.
(2) Slave address register (SVA)
SVA is a register that sets the local address with 8-bit memory manipulation instruction when used as a slave.
It becomes 00H by RESET input.
(3) SO latch
Retains SDA pin output level.
(4) Wake-up control circuit
Generates interrupt requests when the address value set in the slave address register (SVA) and the reception
address coincide or when an extension code is received.
(5) Clock selector
Selects the sampling clock to be used.
(6) Serial clock counter
Counts the serial clocks to be output or input in transmission/reception and checks whether 8-bit data has
been transmitted/received.
(7) Interrupt request signal generation circuit
Controls generation of interrupt request signals.
I2C interrupt is generated by the following two triggers.
• The eighth or the ninth count of the serial clock (set by WTIM bitNote).
• The generation of an interrupt by the stop condition detection (set by SPIE bitNote).
Note WTIM bit : bit 3 of IIC control register (IICC)
SPIE bit : bit 4 of IIC control register (IICC)
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(8) Serial clock control circuit
Generates clocks to be output to SCL pin from the sampling clock in the master mode.
(9) Serial clock wait control circuit
Controls wait timings.
(10) Acknowledgeoutputcircuit,stopconditiondetectioncircuit,startconditiondetectioncircuit,acknowledge
detection circuit
Performs output and detection of various control signals.
(11) Data retention time correction circuit
Generates data retention time for the fall of the serial clock.
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8.4.4 Serial interface control register
I2C bus is controlled by the following three registers.
• IIC control register (IICC)
• IIC status register (IICS)
• IIC clock selection register (IICCL)
The following registers are also used.
• IIC shift register (IIC)
• Slave address register (SVA)
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(1) IIC control register (IICC)
This register performs enabling/disabling I2C operation, setting of wait timing, and other settings of I2C
operation.
This register is set by 1- or 8-bit memory manipulation instruction.
It becomes 00H by RESET input.
7
6
5
4
3
2
1
0
Address
FFFFF0E0H
After reset
00H
IICC
IICE
LREL
WREL
SPIE
WTIM
ACKE
STT
SPT
Bit Position
7
Bit Name
Function
IICE
I2C Enable
Enables or disables I2C operation. The data in IICC is not cleared.
0 : Disables I2C operation. Presets I2C status register (IICS) and disables internal operation.
1 : Enables I2C operation
Set condition : Instruction
Clear condition : Instruction, reset input
6
LREL
Line Release
Exits from the communication in progress, releases the bus, and waits for the start of the next
communication.
0 : Normal operation
1 : Exits from communication and enters wait status
This bit is used when an extension code not related to the local register is received. SCL and
SDA lines go into high-impedance status. The following flags are cleared.
EXC, ACKD, COI, MSTS, TRC, STD
Set condition : Instruction
Clear condition : Reset input, or automatically cleared after execution.
5
WREL
Wait Release
Selects whether releasing wait or not.
0 : Does not release wait
1 : Releases wait
Set condition : Instruction
Clear condition : Reset input, or automatically cleared after execution.
Caution
If wait is released when TRC = 1 and WREL are set to the ninth clock, TRC is
cleared and SDA line goes into high impedance status.
4
SPIE
Stop Condition Interrupt Enable
Disable or enables generation of INTIIC interrupt request by stop condition detection.
0 : Disables
1 : Enables
Set condition : Instruction
Clear condition : Instruction, reset input
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Bit Position
3
Bit Name
WTIM
Function
Wait Timing
Controls generation of wait and interrupt request.
0 : Interrupt request generates at the fall of the eighth clock
For master : Waits keeping clock output in low level after outputting eight clocks
For slave : Waits for master setting clock output in low level after inputting eight clocks
1 : Interrupt request generates at the fall of the ninth clock
For master : Waits keeping clock output in low level after outputting nine clocks
For slave : Waits for master setting clock output in low level after inputting nine clocks
The setting of this bit becomes invalid while transferring address. When EXC = 1, wait is
compulsorily inserted at the eighth clock, and when COI = 1, wait is compulsorily inserted at the
ninth clock, and then the setting of this bit becomes valid. For master, wait is inserted at the ninth
clock while transferring address. The slave which has received the local address enters wait
status at the fall of the ninth clock after the generation of acknowledge.
Set condition : Instruction
Clear condition : Instruction, reset input
2
ACKE
Acknowledge Enable
Controls acknowledge.
0 : Disables acknowledge
1 : Enables automatic acknowledge output. SDA line becomes low level during the 9-clock
period. However, it is invalid while transferring address and valid when EXC = 1.
Set condition : Instruction
Clear condition : Instruction, reset input
1
STT
Start Condition Trigger
Selects whether generating start condition or not.
0 : Does not generate start condition
1 : Generates start condition
When bus is released (stop status): generates start condition by changing SDA line from
high-level to low-level (starts up as master). And then, secures specification time and sets
SCL to low level.
When not joining bus (STT is set after STD =1 is set): this bit functions as a start condition
reservation flag. When this bit is set, it automatically generates start condition after bus is
released.
Set condition : Instruction
Clear condition : Instruction, reset input, when start condition is detected for master, (MSTS =
1 and STD = 1), or when defeated in arbitration.
0
SPT
Stop Condition Trigger
Selects whether generating stop condition or not.
If this bit is set in the early stage of communication, it outputs low-level to SDA line and generates
stop condition.
0 : Does not generate stop condition
1 : Generates stop condition
Sets SCL line to high level after setting SDA line to low level, or waits SCL becomes high
level. And then, it secures specification time , changes SDA line from low level to high level,
and generates stop condition.
Set condition : Instruction
Clear condition : Instruction, reset input, when stop condition is detected, or when defeated in
arbitration.
Caution When performing transmission/reception of master between enabling operation (IICE = 1) and
the first stop condition detection, generate a stop condition once by setting the SPT bit.
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(2) IIC status register (IICS)
IIC status register indicates the I2C status.
This register is set by 1- or 8-bit memory manipulation instruction. It can only be read.
It becomes 00H by RESET input.
7
6
5
4
3
2
1
0
Address
FFFFF0E2H
After reset
00H
IICS
MSTS
ALD
EXC
COI
TRC
ACKD
STD
SPD
Bit Position
7
Bit Name
MSTS
Function
Master Status
Indicates master status.
0 : Slave status or communication wait status
1 : Master status
Set condition : Start condition generation
Clear condition : Stop condition detection, ALD = 1, LREL = 1, IICE = 1 -> 0, or reset input
6
ALD
Arbitration Defeat
Detects arbitration defeat.
0 : Arbitration has not occurred, or win in arbitration
1 : Defeat in arbitration. MSTS flag is cleared.
Set condition : Arbitration defeat
Clear condition : IICE = 0, reset input, or after IICS read.
A bit manipulation instruction is executed to another bit of the IICS register.
5
EXC
Extension Code
Indicates reception of extension code.
0 : Extension code is not received
1 : Extension code is received
Set condition : The higher 4 bits of the received address are 0000 or 1111 (set at the rise of
the eighth clock).
Clear condition : Start condition detection, stop condition detection, LREL= 1, IICE = 0, or reset
input
4
COI
Coincident Address
Indicates coincidence of received address and local address.
0 : Addresses do not coincide
1 : Addresses coincide
Set condition : Coincidence of received address and local address (SVA) (set at the rise of
the eighth clock)
Clear condition : Start condition detection, LREL = 1, IICE = 0, or reset input
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Bit Position
3
Bit Name
TRC
Function
Transmit/Receive Condition
Indicates current communication status.
0 : Receiving status (status other than transmitting status). SDA line goes into high-impedance
state.
1 : Transmitting status. The value of SO latch can be output to SDA line (valid after the fall of
the ninth clock of the first byte).
Set condition : Start condition generation (STD = 1 and MSTS = 1) for master.
1 is input to the LSB (transfer direction specification bit) of the first byte for
slave.
Clear condition : LREL = 1, IICE = 0, ALD = 1, reset input, stop condition detection.
1 is output to the LSB (transfer direction specification bit) of the first byte for
master.
Start condition detection (STD = 1 and MSTS = 0) for slave when not joining
communication.
2
1
0
ACKD
Acknowledge Detected
Indicates detection of acknowledge signal.
0 : Not detected
1 : Detected
Set condition : SDA line becomes low-level at the rise of the ninth clock of SCL.
Clear condition : LREL = 1, the rise of the first clock of the next byte, stop condition detection,
IICE= 0, or reset input
STD
Start Condition Detected
Indicates detection of start condition.
0 : Start condition not detected
1 : Start condition detected. Indicates address transfer period.
Set condition : Start condition detection
Clear condition : Stop condition detection, LREL = 1, the rise of the first clock of the byte following
the address transfer period, IICE = 0, or reset input
SPD
Stop Condition Detected
Indicates detection of stop condition.
0 : Stop condition not detected
1 : Stop condition detected. Communication in the master ends. Bus is released.
Set condition : Stop condition detection
Clear condition : The rise of the first clock of the address transfer byte after start condition
detection and after setting this bit, IICE = 0, or reset input.
Cleared with clock input even without start condition.
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(3) IIC clock selection register (IICCL)
IICCL is a register that sets the transfer clock of I2C.
This register is set by 1- or 8-bit memory manipulation instruction.
It becomes 00H by RESET input.
7
0
6
0
5
4
3
2
1
0
Address
FFFFF0E4H
After reset
00H
IICCL
CLDNote DADNote
SMC
DFC
CL1
CL0
Bit Position
5
Bit Name
Function
CLD
DAD
SMC
DFC
SCL Level Detected
Indicates SCL line level detection result. Valid only when IICE = 1.
0 : SCL line is low level.
1 : SCL line is high level.
4
3
2
SDA Level Detected
Indicates the SDA line level detection result. Valid only when IICE = 1.
0 : SDA line is low level.
1 : SDA line is high level.
Speed Mode Control
Switches operation mode.
0 : Standard mode
1 : High-speed mode
Digital Filter Condition
Enables or disables digital filter operation.
0 : OFF
1 : ON
Digital filter can be used in high-speed mode. The response becomes slow when digital filter
is used.
1, 0
CL1, CL0
Clock
Selects internal clock according to the system clock.
CL1 CL0
Standard Mode
Transfer clock
DFC=0 DFC=1
High-speed Mode
Transfer clock
DFC=0 DFC=1
0
0
1
1
0
1
0
1
φ = 4.0 to 8.0 MHz
φ/88
φ/92
φ/176
φ/352
—
φ = 8.0 to 16.0 MHz φ/48
φ/48
φ/48
φ/96
—
φ = 10.0 to 16.0 MHz φ/172
φ = 16.0 to 33.0 MHz φ/344
φ = 8.0 to 16.0 MHz φ/48
φ = 16.0 to 33.0 MHz φ/96
Setting prohibited
—
Setting prohibited
—
Remark
φ: Internal system clock
Note Bit 4 and bit 5 are Read Only bits.
(4) IIC shift register (IIC)
IIC shift register performs serial transmission/reception (shift operation) in synchronization with the serial
clock.
This register can be read/written in 8-/1-bit units. However, do not write data to IIC register during data transfer.
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Caution
In operations during restart, carry out writing of address data to the IIC shift register after
the start conditions trigger is cleared and the start conditions are detected.
7
6
5
4
3
2
1
0
Address
FFFFF0E6H
After reset
00H
IIC
IIC07
IIC06
IIC05
IIC04
IIC03
IIC02
IIC01
IIC00
(5) Slave address register (SVA)
Slave address register stores slave address of I2C bus.
This register can be read/written in 8-/1-bit units. However, bit 0 is fixed to 0.
7
6
5
4
3
2
1
0
0
Address
FFFFF0E8H
After reset
00H
SVA
SVA07 SVA06
SVA05 SVA04
SVA03 SVA02 SVA01
8.4.5 I2C bus functions
(1) Pin configuration
The configuration of the serial clock pin (SCL) and the serial data bus pin (SDA) is as follows.
(a) SCL ............ Pin to input/output serial clock
Output is N-ch open drain both for master and slave. Input is Schmitt input.
(b) SDA ........... I/O multiplexed pin for serial data
Output is N-ch open drain both for master and slave. Input is Schmitt input.
Because the outputs of serial clock line and the serial data bus line are N-ch open drain, external pull-up
resistors are required.
Figure 8-13. Pin Configuration
Slave device
VDD
Master device
SCL
SDA
SCL
SDA
Clock output
(Clock output)
Clock input
VDD
(Clock input)
Data output
Data input
Data output
Data input
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8.4.6 Definition and controls of I2C bus
The serial data communication format of I2C bus and the signals used are explained below.
Figure 8-14 shows each transfer timing of “start condition”, “data”, and “stop condition”, which are output onto the
serial data bus of I2C bus.
Figure 8-14. Serial Data Transfer Timing of I2C Bus
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SCL
SDA
Address R/W ACK
Data
ACK
Data
ACK
Stop
Start
condition
condition
Start condition, slave address, and stop condition are output from the master.
The acknowledge signal (ACK) is output either from the master or the slave (normally, it is output from the reception
side of 8-bit data)
The serial clock (SCL) is kept being output from the master. However, the slave can extend the low level period
of SCL and insert wait.
(1) Start condition
The start condition is generated when the SDA pin changes from high level to low level while the SCL pin is
high level. The start condition of the SCL pin and the SDA pin is a signal which is the master outputs to the
slave when a serial transfer starts. The slave is provided with the hardware to detect the start condition.
Figure 8-15. Start Condition
H
SCL
SDA
Start condition is output by setting (1) the STT bit of the IICC register in the stop condition detection status
(the SPD bit of the IICS register = 1). When the start condition is detected, the STD bit of the IICS register
is set (1).
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(2) Address
The 7-bit data following the start condition is defined as an address.
The address is an 7-bit data which the master outputs to select a specific slave from the two or more slaves
connected to the bus line. Therefore, the slaves on the bus line must be assigned different addresses.
The slave detects this condition by hardware, and, in addition, checks if the 7-bit data coincides with the slave
address register (SVA). When the 7-bit data and the value of SVA coincide, a slave is selected, and the slave
performs communication with the master until the master transmits a start or stop condition.
Figure 8-16. Address
1
2
3
4
5
6
7
8
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
Note
Address
INTIIC
Note INTIIC is not generated if address other than the local address or extension code is received while
the slave operates.
The address is output when the 8-bit address consisting of the slave address and the transfer direction
explained in (3) Transfer direction specification are written to the shift register (IIC). The received address
is written to IIC.
The slave address is assigned to the higher 7 bits of IIC.
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(3) Transfer direction specification
The master transmits 1-bit data because it specifies the transmit direction following the 7-bit address.
When the transmit direction specification bit is 0, the master transmits data to the slave.
When the transmit direction specification bit is 1, the master receives data from the slave.
Figure 8-17. Transfer Direction Specification
1
2
3
4
5
6
7
8
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
Transfer direction
specification
Note
INTIIC
Note INTIIC is not generated if address other than the local address or extension code is received while
the slave operates.
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(4) Acknowledge signal (ACK)
The acknowledge signal is a signal for checking serial data reception in the transmit and receive sides.
The receive side sends back the acknowledge signal each time it receives an 8-bit data. The transmit side
receives the acknowledge signal after transmitting the 8-bit data. However, in the case the master is the receive
side, no acknowledge signal is output if the master receives the final data. The transmit side detects whether
the receive side has sent the acknowledge signal back to the transmit side after transmitting 8 bits. If the
acknowledge signal is sent back, the transmit side continues processing considering that reception has been
performed correctly. If the slave does not send back the acknowledge signal, the reception has not been
performed correctly. Therefore, the master outputs a stop condition or restart condition and aborts the
transmission. If the acknowledge signal is not sent back, the following two factors can be considered.
<1> The receptions has not been performed correctly.
<2> The final data has been received.
When the receive side sets the SDA line to low level at the ninth clock, the acknowledge signal (ACK) becomes
active (normal reception response).
When ACKE of the IICC register = 1, the acknowledge signal automatic generation enable status is set.
The TRC bit of the IICS register is set according to the data of the eighth bit following the 7-bit address
information. However, when the value of the TRC bit is 0, set ACKE = 1, because it is receive status.
In the slave receive operation (TRC = 0), if the slave side has received two or more bytes and needs the next
data, set ACKE = 0 so that the master side is disabled to start the next transfer.
Similarly, in the master receive operation (TRC = 0), if the master side receives two or more bytes and needs
the next data, set ACKE = 0 to output the restart condition or the stop condition so that the ACK signal does
not generate. This prevents the MSB data from being output to the SDA line in the slave transmit operation
(transmission stops).
Figure 8-18. Acknowledge Signal
1
2
3
4
5
6
7
8
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
When receiving the local address, the acknowledge signal is automatically output in synchronization with the
fall of the eighth clock of SCL regardless of the value of the ACKE. The acknowledge signal is not output
when receiving an address other than the local address.
The output methods of the acknowledge signal are as follows according to the setting of the wait timing.
• When selecting 8-clock wait : acknowledge signal is output by setting ACKE = 1 before releasing wait.
• When selecting 9-clock wait : acknowledge signal is automatically output in synchronization with the
fall of the eighth clock of SCL by setting ACKE = 1 beforehand.
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(5) Stop condition
The stop condition is generated when the SDA pin changes from low level to high level while the SCL pin is
high level.
The stop condition is a signal which the master outputs to the slave when a serial transfer has ended. The
slave is provided with the hardware to detect the stop condition.
Figure 8-19. Stop Condition
H
SCL
SDA
The stop condition is generated by setting (to 1) bit 0 (SPT) of the IICC control register (IICC). When the stop
condition is detected, bit 0 (SPD) of the IICC status register (IICS) is set (1). When bit 4 (SPIE) of IICC is
set (1), INTIIC is generated.
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(6) Wait signal (WAIT)
The wait signal is a signal by which the master or the slave informs the other that it is preparing for transmitting/
receiving data (wait status).
The master of the slave informs the wait status to the other by inputting the low level to the SCL pin. Both
the master and slave can start the next transfer when the wait status is released.
Figure 8-20. Wait Signal (1/2)
(1) When the master is 9-clock wait, and the slave is 8-clock wait
(master: transmission, slave: reception, ACKE = 1)
Master
Slave is waiting (low level)
while master returns to Hi-Z
Waits after outputting
the ninth clock
IIC ← data (wait released)
IIC
6
7
8
9
1
2
3
SCL
Slave
Waits after outputting
the eighth clock
IIC ← FFH (wait released) or WREL ← 1
IIC
SCL
ACKE
H
Transfer line
SCL
6
7
8
9
1
2
3
SDA
D2
D1
D0
ACK
D7
D6
D5
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Figure 8-20. Wait Signal (2/2)
(2) When both master and slave are 9-clock wait
(master: transmission, slave: reception, ACKE = 1)
Master
Both master and slave wait
after outputting the ninth clock
IIC ← data (wait released)
IIC
6
7
8
9
1
2
3
SCL
Slave
IIC ← FFH (wait released)
or WREL ← 1
IIC
SCL
ACKE
H
Transfer line
SCL
6
7
8
9
1
2
3
SDA
D2
D1
D0
ACK
D7
D6
D5
Output according to the ACKE previously set.
The wait of the IICC register automatically generates according to the setting of WTIM.
Normally, the receive side releases wait when WREL = 1 or when FFH is written to IIC, and the transmit side
releases wait when data is written to IIC.
For the master, wait can be released also with the following method.
• STT = 1
• SPT = 1
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(7) I2C interrupt (INTIIC)
The following shows the INTIIC interrupt request generation timing and the value of the IIC status register (IICS)
in INTIIC interrupt timing.
(a) Master operation
(i)
Start-Address-Data-Data-Stop (normal transmission/reception)
<1> When WTIM = 0
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 10 x x x 110 B
2: IICS = 10 x x x 000 B
3: IICS = 10 x x x 000 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
3
1
2
4
1: IICS = 10 x x x 110 B
2: IICS = 10 x x x 100 B
3: IICS = 10 x x x x 00 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(ii) Start-Address-Data-Start-Address-Data-Stop (restart)
<1> When WTIM = 0
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
4
5
1: IICS = 10 x x x 110 B
2: IICS = 10 x x x 000 B
3: IICS = 10 x x x 110 B
4: IICS = 10 x x x 000 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
2
D7 to D0
AK SP
4
1
3
5
1: IICS = 10 x x x 110 B
2: IICS = 10 x x x x 00 B
3: IICS = 10 x x x 110 B
4: IICS = 10 x x x x 00 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(iii) Start-Code-Data-Data-Stop (extension code transmission)
<1> When WTIM = 0
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 1010 x 110 B
2: IICS = 1010 x 000 B
3: IICS = 1010 x 000 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
3
1
2
4
1: IICS = 1010 x 110 B
2: IICS = 1010 x 100 B
3: IICS = 1010 x x 00 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(b) Slave operation (when receiving slave address data (SVA coincides))
(i)
Start-Address-Data-Data-Stop
<1> When WTIM = 0
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 0001 x 110 B
2: IICS = 0001 x 000 B
3: IICS = 0001 x 000 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
3
1
2
4
1: IICS = 0001 x 110 B
2: IICS = 0001 x 100 B
3: IICS = 0001 x x 00 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(ii) Start-Address-Data-Start-Address-Data-Stop
<1> When WTIM = 0 (SVA coincides after restart)
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
4
5
1: IICS = 0001 x 110 B
2: IICS = 0001 x 000 B
3: IICS = 0001 x 110 B
4: IICS = 0001 x 000 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1 (SVA coincides after restart)
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
2
D7 to D0
AK SP
4
1
3
5
1: IICS = 0001 x 110 B
2: IICS = 0001 x x 00 B
3: IICS = 0001 x 110 B
4: IICS = 0001 x x 00 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(iii) Start-Address-Data-Start-Code-Data-Stop
<1> When WTIM = 0 (receives extension code after restart)
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
4
5
1: IICS = 0001 x 110 B
2: IICS = 0001 x 000 B
3: IICS = 0010 x 010 B
4: IICS = 0010 x 000 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1 (receives extension code after restart)
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
5
1
2
3
4
6
1: IICS = 0001 x 110 B
2: IICS = 0001 x x 00 B
3: IICS = 0010 x 010 B
4: IICS = 0010 x 110 B
5: IICS = 0010 x x 00 B
6: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(iv) Start-Address-Data-Start-Address-Data-Stop
<1> When WTIM = 0 (address does not coincide after restart (except extension code))
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 0001 x 110 B
2: IICS = 0001 x 000 B
3: IICS = 0000 x x 10 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1 (address does not coincide after restart (except extension code))
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
2
D7 to D0
AK SP
1
3
4
1: IICS = 0001 x 110 B
2: IICS = 0001 x x 00 B
3: IICS = 0000 x x 10 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(c) Slave operation (when receiving extension code)
(i) Start-Code-Data-Data-Stop
<1> When WTIM = 0
ST AD6 to AD0 RW AK
1
D7 to D0
AK
D7 to D0
AK SP
2
3
4
1: IICS = 0010 x 010 B
2: IICS = 0010 x 000 B
3: IICS = 0010 x 000 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
ST AD6 to AD0 RW AK
1
D7 to D0
AK
D7 to D0
AK SP
4
2
3
5
1: IICS = 0010 x 010 B
2: IICS = 0010 x 110 B
3: IICS = 0010 x x 00 B
4: IICS = 0010 x x 00 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(ii) Start-Code-Data-Start-Address-Data-Stop
<1> When WTIM = 0 (SVA coincides after restart)
ST AD6 to AD0 RW AK
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
4
5
1: IICS = 0010 x 010 B
2: IICS = 0010 x 000 B
3: IICS = 0001 x 110 B
4: IICS = 0001 x 000 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1 (SVA coincides after restart)
ST AD6 to AD0 RW AK
1
D7 to D0
AK ST AD6 to AD0 RW AK
3
D7 to D0
AK SP
5
2
4
6
1: IICS = 0010 x 010 B
2: IICS = 0010 x 110 B
3: IICS = 0010 x x 00 B
4: IICS = 0001 x 110 B
5: IICS = 0001 x x 00 B
6: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(iii) Start-Code-Data-Start-Code-Data-Stop
<1> When WTIM = 0 (receives extension code after restart)
ST AD6 to AD0 RW AK
1
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
2
3
4
5
1: IICS = 0010 x 010 B
2: IICS = 0010 x 000 B
3: IICS = 0010 x 010 B
4: IICS = 0010 x 000 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1 (receives extension code after restart)
ST AD6 to AD0 RW AK
1
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
6
2
3
4
5
7
1: IICS = 0010 x 010 B
2: IICS = 0010 x 110 B
3: IICS = 0010 x x 00 B
4: IICS = 0010 x 010 B
5: IICS = 0010 x 110 B
6: IICS = 0010 x x 00 B
7: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(iv) Start-Code-Data-Start-Address-Data-Stop
<1> When WTIM = 0 (address does not coincides after restart (except extension code))
ST AD6 to AD0 RW AK
1
D7 to D0
AK ST AD6 to AD0 RW AK
D7 to D0
AK SP
2
3
4
1: IICS = 0010 x 010 B
2: IICS = 0010 x 000 B
3: IICS = 00000 x 10 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1 (address does not coincides after restart (except extension code))
ST AD6 to AD0 RW AK
1
D7 to D0
AK ST AD6 to AD0 RW AK
3
D7 to D0
AK SP
2
4
5
1: IICS = 0010 x 010 B
2: IICS = 0010 x 110 B
3: IICS = 0010 x x 00 B
4: IICS = 00000 x 10 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(d) Operation of not joining communication
(i) Start-Code-Data-Data-Stop
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
1: IICS = 00000001 B
Remark
generates only when SPIE = 1
(e) Operation of arbitration defeat (operates as a slave after arbitration defeat)
(i)
When defeated in arbitration during slave address data transmission
<1> When WTIM = 0
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 0101 x 110 B (example: reads ALD during interrupt processing)
2: IICS = 0001 x 000 B
3: IICS = 0001 x 000 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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<2> When WTIM = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
3
1
2
4
1: IICS = 0101 x 110 B (example: reads ALD during interrupt processing)
2: IICS = 0001 x 100 B
3: IICS = 0001 x x 00 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
(ii) When defeated in arbitration during transmitting extension code
<1> When WTIM = 0
ST AD6 to AD0 RW AK
1
D7 to D0
AK
D7 to D0
AK SP
2
3
4
1: IICS = 0110 x 010 B (example: reads ALD during interrupt processing)
2: IICS = 0010 x 000 B
3: IICS = 0010 x 000 B
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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<2> When WTIM = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
4
1
2
3
5
1: IICS = 0110 x 010 B (example: reads ALD during interrupt processing)
2: IICS = 0010 x 110 B
3: IICS = 0010 x 100 B
4: IICS = 0010 x x 00 B
5: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
(f) Operation of arbitration defeat (does not join after arbitration defeat)
(i)
When defeated in arbitration during transmitting slave address data
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
2
1: IICS = 01000110 B (example: reads ALD during interrupt processing)
2: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
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(ii) When defeated in arbitration during transmitting extension code
ST AD6 to AD0 RW AK
1
D7 to D0
AK
D7 to D0
AK SP
2
1: IICS = 0110 x 010 B (example: reads ALD during interrupt processing)
Set LREL =1 by software (when not joining communication)
2: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
(iii) When defeated in arbitration during transferring data
<1> When WTIM = 0
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
1: IICS = 10001110 B
2: IICS = 01000000 B (example: reads ALD during interrupt processing)
3: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
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<2> When WTIM = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
1: IICS = 10001110 B
2: IICS = 01000100 B (example: reads ALD during interrupt processing)
3: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
(iv) When defeated in restart condition during transferring data
<1> Except extension code (example: SVA does not coincide)
ST AD6 to AD0 RW AK
D7 to Dn
ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
1: IICS = 1000 x 110 B
2: IICS = 01000110 B (example: reads ALD during interrupt processing)
3: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
n = 0 to 6
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<2> Extension code
ST AD6 to AD0 RW AK
D7 to Dn
ST AD6 to AD0 RW AK
2
D7 to D0
AK SP
1
3
1: IICS = 1000 x 110 B
2: IICS = 0110 x 010 B (example: reads ALD during interrupt processing)
Set IICC : LREL = 1 by software (when not joining communication)
3: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
n = 0 to 6
(v) When defeated in stop condition during transferring data
ST AD6 to AD0 RW AK
D7 to Dn
SP
1
2
1: IICS = 1000 x 110 B
2: IICS = 01000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
n = 0 to 6
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(vi) When attempting to generate restart condition and defeated in arbitration because the data
is low level
<1> When WTIM = 0
STT = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 1000 x 110 B
2: IICS = 1000 x 000 B
3: IICS = 01000000 B (example: reads ALD during interrupt processing)
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
STT = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 1000 x 110 B
2: IICS = 1000 x x 00 B
3: IICS = 01000100 B (example: reads ALD during interrupt processing)
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(vii) When attempting to generate restart condition and defeated in arbitration at stop condition
because the data is low level
<1> When WTIM = 0
STT = 1
ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
1: IICS = 1000 x 110 B
2: IICS = 1000 x 000 B
3: IICS = 01000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
STT = 1
ST AD6 to AD0 RW AK
D7 to D0
AK SP
1
2
3
1: IICS = 1000 x 110 B
2: IICS = 1000 x x 00 B
3: IICS = 01000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(viii) When attempting to generate stop condition and defeated in arbitration because the data is
low level
<1> When WTIM = 0
SPT = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 1000 x 110 B
2: IICS = 1000 x 000 B
3: IICS = 01000000 B (example: reads ALD during interrupt processing)
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
<2> When WTIM = 1
SPT = 1
ST AD6 to AD0 RW AK
D7 to D0
AK
D7 to D0
AK
D7 to D0
AK SP
1
2
3
4
1: IICS = 1000 x 110 B
2: IICS = 1000 x x 00 B
3: IICS = 01000000 B (example: reads ALD during interrupt processing)
4: IICS = 00000001 B
Remark
always generates
generates only when SPIE = 1
don’t care
x
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(8) Interrupt request (INTIIC) generation timing and wait control
INTIIC generates and wait control is performed by the settings of the WTIM bit of the IIC control register (IICC)
at the timings shown in Table 8-3.
Table 8-3. INTIIC Generation Timing and Wait Control
WTIM
In Slave Operation
In Master Operation
Address
9Notes 1, 2
9Notes 1, 2
Data Reception Data Transmission
Address
Data Reception Data Transmission
0
1
8Note 2
9Note 2
8Note 2
9Note 2
9
9
8
9
8
9
Notes 1. INTIIC signal and wait of the slave generate at the fall of the ninth clock only when they coincide with
the address set in the slave address register (SVA).
At this time, ACK is output regardless of the setting of ACKE. The slave which has received an extension
code generates INTIIC at the fall of the eighth clock.
2. Neither INTIIC nor wait generates when SVA and the received address do not coincide.
Remark The numbers in the table represent the number of the clocks of the serial clock. Both the interrupt request
and the wait control synchronize with the fall of the serial clock.
(a) When transmitting/receiving address
• In slave operation : The interrupt and the wait timings are determined regardless of the WTIM bit.
• In master operation : The interrupt and the wait timings generates at the fall of the ninth clock
regardless of the WTIM bit.
(b) When receiving data
• In master/slave operation: The interrupt and the wait timings are determined by the WTIM bit.
(c) When transmitting data
• In master/slave operation: The interrupt and the wait timings are determined by the WTIM bit.
(d) Wait release
The following four methods are available for releasing wait.
• Set WREL of the control register (IICC) = 1
• Write operation of IIC shift register (IIC)
• Start condition (STT) set
• Stop condition (SPT) set
When 8-clock wait (WTIM = 0) is selected, the output level of ACK should be determined before wait
release.
(e) Stop condition detection
INTIIC generates when stop condition is detected.
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(9) Address coincidence detection
The I2C bus can select the specific slave device when the master transmits the slave address.
Address coincidence detection can be automatically performed by hardware. If the local address is set to the
slave address register (SVA), INTIIC interrupt request generates only when the slave address transmitted from
the master and the address set in SVA coincide or when an extension code is received.
(10) Error detection
The I2C bus can detect transmission errors by comparing the IIC data before transmission starts and that after
transmission ends because the status of the serial bus during transmission (SDA) is captured also to IIC shift
register (IIC) of the transmitting device. In this case, if the two data differ, it is judged that a transmission error
has occurred.
(11) Extension code
(a) Interrupt request (INTIIC) is issued at the fall of the eighth clock by setting the extension code reception
flag (EXC) regarding it as reception of exception code when the higher 4 bits of the reception address
is either “0000” or “1111”.
The local address stored in the slave address register (SVA) is not affected.
(b) The following is set when “111110xx” is set to SVA by 10-bit address transfer and “111110xx0” is
transferred from the master. However, interrupt request (INTIIC) generates at the fall of the eighth clock.
• Coincidence of the higher 4-bit data: EXC = 1
• Coincidence of the 7-bit data
: COI = 1
(c) The processing after interrupt request is issued differs depending on the data following the extension code.
Therefore, it is performed by software.
For example, LREL is set to 1 and the next communication wait status enters not to operate a device as
a slave after receiving extension code.
Table 8-4. Definition of Extension Code Bit
Slave Address
0000 000
0000 000
0000 001
0000 010
1111 0xx
R/W Bit
Description
General call address
0
1
x
x
x
Start byte
CBUS address
Address reserved for different bus format
10-bit slave address specification
(12) Arbitration
When more than one master simultaneously output start conditions (when setting STT =1 before STD = 1 is
set), master communication continues until the data differs while adjusting the clock. This operation is called
arbitration.
The master which is defeated in arbitration sets the ALD bit of the IIC status register (IICS) at the timing at
which the master is defeated in the arbitration, sets both SCL and SDA lines in Hi-Z status, and releases bus.
The arbitration defeat is detected by software when ALD =1 at the next interrupt request generation timing
(the eighth or ninth clock, stop condition detection, etc.).
For the interrupt generation timing, refer to (7) I2C interrupt (INTIIC).
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Figure 8-21. Example of Arbitration Timing
Master 1
SCL
Hi-Z
Hi-Z
SDA
Master 1 arbitration defeat
Master 2
SCL
SDA
Transfer line
SCL
SDA
Status when Arbitration Occurs
Interrupt Request Issue Timing
Address transmitting
Fall of the eighth or ninth clock after byte transferNote 1
Read/write information after address transmission
Transferring extension code
Read/write information after extension code transmission
Transmitting data
ACK transfer period after data transmission
Transferring data, restart condition detection
Transferring data, stop condition detection
Attempted to output restart condition but data is low level
Attempted to output restart condition but stop condition is detected
Attempted to output stop condition but data is low level
Attempted to restart condition but SCL is low level
Stop condition output (SPIE = 1)Note 2
Fall of the eighth or ninth clock after byte transferNote 1
Stop condition output (SPIE = 1)Note 2
Fall of the eighth or ninth clock after byte transfer
Notes 1. When WTIM (bit 3 of the IIC control register (IICC)) = 1, interrupt generates at the fall of the ninth clock.
When WTIM = 0 and when slave address of extension code is received, interrupt generates at the fall
of the eighth clock.
2. If arbitration may occur, set SPIE = 1 in master operation.
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(13) Wake-up function
Wake-up function generates interrupt request (INTIIC) when the local address and an extension code are
received in the slave function of I2C.
When address does not coincide, unnecessary interrupt does not generate, so that efficient processing is
possible.
When start condition is detected, wake-up wait status is set. Even a master can become a slave as a result
of arbitration defeat (in the case start condition is output), it enters wake-up wait status while transmitting
address.
However, when a stop condition is detected, interrupt enable/disable is determined according to the setting
of the SPIE bit regardless of the wake-up function.
(14) Communication reservation
• When a device could become neither a master or slave in arbitration.
• When a device does not operate as a slave receiving an extension code (when not sending back ACK
and releasing bus with LREL of IICC = 1).
When the STT bit of the IICC is set in the status not joining the bus, a start condition is automatically generated
and wait status is entered after the bus is released (stop condition detection).
When the bus release is detected (stop condition detection), address transfer as a master is started by IIC
write manipulation. At this time the SPIE bit of the IICC should be set.
When STT is set, whether it is operates as start condition or as communication reservation is determined by
the bus status.
• When bus is released
: start condition generation
• When bus is not released (wait status) : communication reservation
Which operation STT has performed is detected by checking the STT bit again after setting STT and giving
wait time.
Secure the wait time as shown in Table 8-5 by software. Wait time can be set by SMC, CL0, and CL1 of IICCL.
Table 8-5. Wait Time
SMC
CL1
0
CL0
0
Wait Time
26 clocks
0
0
0
0
1
1
1
1
0
1
46 clocks
1
0
1
1
37 clocks
16 clocks
0
0
0
1
1
0
1
1
13 clocks
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Figure 8-22. Communication Reservation Timing
Program
processing
STT
= 1
IIC write
Commu-
Hardware
processing
Setting SPD Setting
nication
reserva-
tion
and INTIIC STD
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
Output by the master which
has occupied the bus
The communication reservation is acknowledged at the following timings. The communication reservation
is made by setting the STT of IICC = 1 before stop condition detection after STD of IICS = 1 is set.
SCL
SDA
STD
SPD
Wait status
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Figure 8-23 shows the communication reservation procedure.
Figure 8-23. Communication Reservation Procedure
DI
STT ← 1
; Sets STT flags
(communication reservation)
Definition of
communication reservation
; Defines communication is reserved
(set by defining user flag in any
RAM)
Wait
; Secures wait time by software
(refer to Table 8-5)
(Communication reservation)Note
Yes
STT = 1 ?
No
; Checks STT flag
(Generates start condition)
Cancellation of
communication reservation
Clears user flag
;
IIC <- xxH
; IIC write operation
EI
Note Executes writing to IIC by stop condition interrupt in communication reservation operation.
(15) Other precautions
(a) Multi-master communication
To perform master communication from the status in which stop condition is not detected (bus is not
released) after reset, generate stop condition and release bus before starting master communication.
In multi-master, master communication cannot be performed in the status in which bus is not released
(stop condition is not detected).
Generate stop condition with the following procedure.
<1> Setting IICCL
<2> IICE of IICC ← 1
<3> SPT of IICC ← 1
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(b) Operation during communication reservation (when a multi-master is used)
If a slave is selected during communication reservation, when writing a “1” to the WREL bit, write a “0”
to the STT bit at the same time. After that, following stop condition detection, write a “1” to the STT bit
again.
(c) Start operation after communication reservation (when a multi-master is used)
If the stop condition is detected and the start condition is generated after that, after confirming that the
MSTS bit is 1 (master communication state), confirm that the TRC bit is 1 (transmission operation). At
this time, if the TRC bit is 0, set LREL to withdraw from communication, and carry out communication
reservation (STT = 1) again after the stop condition is detected.
(d) STT setting timing (when a multi-master is used)
Arrange the program as shown in Figure 8-24.
Figure 8-24. STT Setting Timing Procedure
Confirmation of SPD
(SPD = 1)
Setting of STT
(Start operation time loop)
No
STT = 0?
Yes
Setting of WREL
No
MSTS = 1?
Communication reservation
Yes
Setting of STT
Writing of IIC
Communication reservation
Start of communication
Caution The period of time from confirmation of SPD until setting of WREL should be within the
following.
High-speed mode : within 17.5 µs
Standard mode
: within 70.0 µs
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8.4.7 Communication operation
(1) Master operation
The following shows the master communication procedure.
Figure 8-25. Master Operation Procedure
START
IICCL ← xxH
Selects transfer clock
IICC ← xxH
IICE = SPIE = WTIM = 1
STT = 1
No
INTIIC = 1?
Yes
IIC write
Transfer starts
; Detects stop condition
No
No
INTIIC = 1?
Yes
ACKD = 1?
Yes
Generates stop condition
absence of slave of the
(
)
address coincidence
No (Reception)
TRC = 1?
; Address transfer ends
Yes (Transmission)
WTIM = 0
ACKE = 1
IIC write
Transfer starts
WREL = 1
Reception starts
No
INTIIC = 1?
Yes
No
No
INTIIC = 1?
Data processing
Yes
Data processing
Yes
ACKD = 1?
No
Transfer ends?
Generates
restart condition or
stop condition
Yes
ACKE = 0
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(2) Slave operation
The following shows the slave communication procedure.
Figure 8-26. Slave Operation Procedure
START
IICC ← xxH
IICE = 1
No
INTIIC = 1?
Yes
Yes
EXC = 1?
No
Joining
communication?
No
No
Yes
LREL = 1
COI = 1?
Yes
No
TRC = 1?
Yes
WTIM = 1
IIC write
WTIM = 0
ACKE = 1
Transfer starts
WREL = 1
Reception starts
No
INTIIC = 1?
Yes
No
No
INTIIC = 1?
Data processing
Yes
Data processing
Yes
ACKD = 1?
No
Transfer ends?
Generates
restart condition or
stop condition
Yes
ACKE = 0
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8.4.8 Timing chart
In the I2C bus mode, a target slave device is selected from more than one slave device when the master outputs
an address to the serial bus.
The master transmits the TRC bit that indicates the transfer direction of data following the slave address and starts
serial communication with the slave.
Figures 8-27 and 8-28 show the timing charts of data communication.
The shift operation of the shift register (IIC) is performed in synchronization with the fall of the serial clock (SCK),
the transmitted data is transferred to the SO latch, and output from the SDA pin with the MSB first.
The data input to the SDA pin at the rise of SCL is captured by IIC.
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Figure 8-27. Example of Master→ Slave Communication
(9-clock wait is selected both for master and slave) (1/3)
(1) Start condition-address
Processing of
master device
IIC ← Address
IIC ← Data
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
WREL
INTIIC
MSTS
TRC
H
Transmission
Transfer line
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
A6 A5 A4 A3 A2 A1 A0 W ACK
D7 D6 D5 D4
Start
condition
Processing of
slave device
IIC ← FFHNote
IIC
ACKD
STD
SPD
WTIM
ACKE
STT
H
H
SPT
Note
WREL
INTIIC
MSTS
TRC
(When EXC = 1)
L
L
Reception
Note Perform wait release of a slave with either IIC ← FFH or WREL ← 1.
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Figure 8-27. Example of Master → Slave Communication
(9-clock wait is selected both for master and slave) (2/3)
(2) Data
Processing of
master device
IIC ← Data
IIC ← Data
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
WREL
INTIIC
MSTS
TRC
H
H
Transmission
Transfer line
SCL
SDA
8
9
1
2
3
4
5
6
7
8
9
1
2
3
D0
D7 D6 D5 D4 D3 D2 D1 D0
D7
D6 D5
Processing of
slave device
IIC ← FFHNote
IIC ← FFHNote
IIC
ACKD
STD
SPD
H
WTIM
ACKE
STT
H
SPT
Note
Note
WREL
INTIIC
MSTS
TRC
L
L
Reception
Note Perform wait release of a slave with either IIC ← FFH or WREL ← 1.
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Figure 8-27. Example of Master → Slave Communication
(9-clock wait is selected both for master and slave) (3/3)
(3) Stop condition
Processing of
master device
IIC ← Data
IIC ← Address
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
WREL
INTIIC
MSTS
TRC
(When SPIE = 1)
H
Transmission
Transfer line
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
D7 D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5
Stop
Start
condition condition
Processing of
slave device
IIC ← FFHNote
IIC ← FFHNote
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
Note
Note
WREL
INTIIC
MSTS
TRC
(When SPIE = 1)
L
L
Reception
Note Perform wait release of a slave with either IIC ← FFH or WREL ← 1.
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Figure 8-28. Example of Slave → Master Communication
(9-clock wait is selected both for master and slave) (1/3)
(1) Start condition-address
Processing of
master device
IIC ← Address
IIC ← FFHNote
IIC
ACKD
STD
SPD
WTIM
ACKE
STT
H
H
SPT
Note
WREL
INTIIC
MSTS
TRC
Transfer line
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
A6 A5 A4 A3 A2 A1 A0
D7
D6 D5 D4 D3 D2
R
Start
condition
Processing of
slave device
IIC ← Data
IIC
ACKD
STD
SPD
WTIM
ACKE
STT
H
H
SPT
WREL
INTIIC
MSTS
TRC
L
Note Perform wait release of a slave with either IIC ← FFH or WREL ← 1.
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Figure 8-28. Example of Slave → Master Communication
(9-clock wait is selected both for master and slave) (2/3)
(2) Data
Processing of
master device
IIC ← FFHNote
IIC ← FFHNote
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
Note
Note
WREL
INTIIC
MSTS
TRC
H
Reception
L
Transfer line
SCL
SDA
8
9
1
2
3
4
5
6
7
8
9
1
2
3
ACK
D0 ACK
D7
D6 D5 D4 D3 D2 D1 D0
D7
D6 D5
Processing of
slave device
IIC ← Data
IIC ← Data
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
WREL
INTIIC
MSTS
TRC
L
H
Transmission
Note Perform wait release of a slave with either IIC ← FFH or WREL ← 1.
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Figure 8-28. Example of Slave → Master Communication
(9-clock wait is selected both for master and slave) (3/3)
(3) Stop condition
Processing of
master device
IIC ← FFHNote
IIC ← Address
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
Note
WREL
INTIIC
MSTS
TRC
(When SPIE = 1)
Transfer line
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
D7 D6 D5 D4 D3 D2 D1 D0
A6 A5
N–ACK
Stop
Start
Processing of
slave device
condition condition
IIC ← Data
IIC
ACKD
STD
SPD
H
H
WTIM
ACKE
STT
SPT
WREL
INTIIC
MSTS
TRC
(When SPIE = 1)
L
Note Perform wait release of a slave with either IIC ← FFH or WREL ← 1.
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8.5 Baud Rate Generator 0 to 3 (BRG0 to BRG3)
8.5.1 Configuration and function
The serial clock of the serial interface can be selected from the baud rate generator output or φ (internal system
clock) for each channel.
A baud rate generator is provided with the following four systems, which can be set independently.
• For UART/CSI0 (BRG0)
• For I2C/CSI1 (BRG1)
• For CSI2 (BRG2)
• For CSI3 (BRG3)
The serial clock source for the UART is specified by the SCLS bits of the ASIMn registers. The serial clock source
for the CSI is specified by the CLS bits of the CSIMn registers.
When the output of the baud rate generator is specified, the baud rate generator will be used as the clock source.
Because the serial clock for transmission/reception is shared by both the transmission and reception portions, the
same baud rate is used for both transmission and reception.
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Figure 8-29. Block Diagram of Baud Rate Generator
BRG0
BPRM0
BRGC0
Coincidence
Clear
UART
CSI0
TMBRG0
Prescaler
CSI1
I2C
BRG1
BRG2
BRG3
CSI2
CSI3
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(1) Dedicated baud rate generators (BRG0 to BRG3)
The dedicated baud rate generators (BRGn) consist of an 8-bit timer (TMBRGn) that generates a serial clock
for transmission/reception, a compare register (BRGCn), and a prescaler (n = 0 to 3).
(a) Input clock
Internal system clock (φ) is input to the BRGn.
(b) Set-up value of BRGn
(i)
UART
If the dedicated baud rate generator is specified for UART as a serial clock source, the actual baud
rate can be calculated by the following expression, because a sample rate of x16 is used:
φ
Baud rate =
where,
[bps]
m x 2k x 16 x 2
φ : Internal system clock frequency [Hz]
m: BRGC0 set-up value (1 ≤ m ≤ 256Note
)
k : BPR00 to BPR02 prescaler set-up value
Note 256 is set by writing 0 to the BRGC0 register.
(ii) CSI0 to CSI3
If the dedicated baud rate generator is specified for CSIn, the actual baud rate can be calculated
by the following expression (n = 0 to 3):
φ
Baud rate =
where,
[bps]
m x 2k x 2
φ : Internal system clock frequency [Hz]
m: BRGCn set-up value (1 ≤ m ≤ 256Note 1
)
k : BPRn0 to BPRn2 prescaler set-up valueNote 2
Notes 1. m = 256 is set by writing 0 to the BRGCn register.
2. Setting k = 0 is prohibited.
Table 8-6 shows the setup values of the baud rate generator when the typical clocks are used.
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Table 8-6. Baud Rate Generators 0 to 3 Set-up Values (when typical clocks are used) (1/2)
(a) UART
Baud Rate [bps]
φ = 33 MHz
φ = 25 MHz
φ = 16 MHz
BPR BRGC
φ = 12.5 MHz
BPR BRGC Error
BPR BRGC Error
Error
0.03%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.00%
0.16%
6.99%Note
8.51%Note
BPR BRGC Error
110
150
—
5
4
3
2
1
0
0
0
0
0
0
0
0
—
215
215
215
215
215
215
107
100
54
—
5
5
4
3
2
1
0
0
0
0
0
0
0
0
222
163
163
163
163
163
163
81
0.02%
0.15%
0.15%
0.15%
0.15%
0.15%
0.15%
0.47%
0.16%
0.72%
0.00%
1.73%
1.73%
1.73%
5
4
3
2
1
0
0
0
0
0
0
0
0
0
142
208
208
208
208
208
104
52
4
4
3
2
1
0
0
0
0
0
0
0
0
—
222
163
163
163
163
162
82
0.02%
0.15%
0.15%
0.15%
0.15%
0.47%
0.76%
1.73%
1.16%
1.73%
3.85%
1.73%
1.73%
—
0.07%
0.07%
0.07%
0.07%
0.07%
0.07%
0.39%
0.84%
0.54%
0.00%
0.54%
3.29%
1.30%
300
600
1200
2400
4800
9600
40
10400
19200
31250
38400
76800
153600
75
48
38
41
26
20
33
25
16
13
27
20
13
10
13
10
6
5
7
5
3
—
Baud Rate [bps]
φ = 19.660 MHz
BPR BRGC Error
φ = 14.746 MHz
φ = 12.288 MHz
φ = 9.830 MHz
BPR BRGC Error
BPR BRGC Error
BPR BRGC Error
110
150
5
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
176
128
128
128
128
128
128
64
60
32
20
16
8
0.83%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
1.54%
0.00%
1.70%
0.00%
0.00%
0.00%
0.00%
0.00%
5
4
131
192
192
192
192
192
96
0.07%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.70%
0.00%
1.69%
0.00%
0.00%
0.00%
—
4
4
218
160
160
160
160
160
80
0.08%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.21%
0.00%
2.40%
0.00%
0.00%
—
4
4
3
2
1
0
0
0
0
0
0
0
0
0
0
—
176
128
128
128
128
128
64
32
30
16
10
8
0.02%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
1.54%
0.00%
1.70%
0.00%
0.00%
0.00%
0.00%
—
300
3
3
600
2
2
1200
1
1
2400
0
0
4800
0
0
9600
0
48
0
40
10400
19200
31250
38400
76800
153600
307200
614400
0
44
0
37
0
24
0
20
0
15
0
12
0
12
0
10
0
6
0
5
4
4
0
3
—
—
—
—
2
2
—
—
—
—
—
1
1
—
—
—
—
—
Note Cannot be used because the error is too great.
Remark φ: Internal system clock
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Table 8-6. Baud Rate Generators 0 to 3 Set-up Values (when typical clocks are used) (2/2)
(b) CSI
Baud Rate [bps]
φ = 33 MHz
BPR BRGC
φ = 25 MHz
BPR BRGC
φ = 16 MHz
BPR BRGC Error
φ = 12.5 MHz
BPR BRGC Error
Error
—
Error
0.02%
0.15%
0.15%
0.15%
0.15%
0.15%
0.47%
0.76%
1.16%
1.73%
1.73%
1.73%
27.2%Note
1760
2400
—
5
4
3
2
1
1
1
1
1
1
1
1
—
215
215
215
215
215
107
54
5
5
4
3
2
1
1
1
1
1
1
1
1
222
163
163
163
163
163
81
5
4
142
208
208
208
208
104
52
0.03%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
6.99%Note
—
4
4
3
2
1
1
1
1
1
1
1
1
—
222
163
163
163
163
81
0.02%
0.15%
0.15%
0.15%
0.15%
0.47%
0.76%
1.73%
1.16%
1.73%
1.73%
15.2%Note
—
0.07%
0.07%
0.07%
0.07%
0.07%
0.39%
0.54%
0.84%
0.54%
3.29%
4.09%
11.30%Note
4800
3
9600
2
19200
1
38400
1
76800
1
41
153600
166400
307200
614400
1228800
2457600
41
1
26
20
50
38
1
24
19
27
20
1
13
10
13
10
1
7
5
7
5
—
—
—
3
3
2
—
—
—
Baud Rate [bps]
φ = 20 MHz
φ = 14.746 MHz
φ = 12.288 MHz
φ = 9.830 MHz
BPR BRGC Error
BPR
5
BRGC Error
BPR BRGC Error BPR BRGC
Error
0.08%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
2.60%
0.00%
0.00%
16.7%Note
—
1760
2400
178
130
130
130
130
130
65
0.25%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
1.36%
0.16%
1.73%
1.73%
1.73%
1.73%
5
4
3
2
1
1
1
1
1
1
1
1
1
131
192
192
192
192
96
48
24
22
12
6
0.07%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.70%
0.00%
0.00%
0.00%
25%Note
4
4
3
2
1
1
1
1
1
1
1
1
—
218
160
160
160
160
80
4
4
3
2
1
1
1
1
1
1
1
1
1
176
128
128
128
128
64
32
16
15
8
0.26%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
1.50%
0.00%
0.00%
0.00%
0.00%
5
4800
4
9600
3
19200
2
38400
1
76800
1
40
153600
166400
307200
614400
1228800
2457600
1
33
20
1
30
18
1
16
10
1
8
5
4
1
4
3
3
2
1
2
2
—
1
Note Cannot be used because the error is too great.
Remark φ: Internal system clock
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CHAPTER 8 SERIAL INTERFACE FUNCTION
(c) Error of baud rate
The error of the baud rate is calculated as follows:
Actual baud rate (baud rate with error)
Error [%] =
– 1 x 100
Desired baud rate (normal baud rate)
Example: (9520/9600 – 1) x 100 = –0.833 [%]
(5000/4800 – 1) x 100 = +4.167 [%]
(2) Allowable error range of baud rate
The allowable error range depends on the number of bits of one frame.
The basic limit is ±5% of baud rate error and ±4.5% of sample timing with an accuracy of 16 bits. However,
the practical limit should be ±2.3 % of baud rate error, assuming that both the transmission and reception sides
contain an error.
8.5.2 Baud rate generator compare registers 0 to 3 (BRGC0 to BRGC3)
These are 8-bit compare registers that set a timer/count value for the dedicated baud rate generator.
These registers can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF084H
After reset
Undefined
BRGC0
BRGC1
BRGC2
BRGC3
BRG07 BRG06 BRG05 BRG04 BRG03 BRG02 BRG01 BRG00
BRG17 BRG16 BRG15 BRG14 BRG13 BRG12 BRG11 BRG10
BRG27 BRG26 BRG25 BRG24 BRG23 BRG22 BRG21 BRG20
BRG37 BRG36 BRG35 BRG34 BRG33 BRG32 BRG31 BRG30
Address
FFFFF094H
After reset
Undefined
Address
FFFFF0A4H
After reset
Undefined
Address
FFFFF0B4H
After reset
Undefined
Caution The internal timer (TMBRGn) is cleared by writing the BRGC registers. Therefore, do not
rewrite or program the BRGCn registers during transmission/reception operation.
Remark
n = 0 to 3
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8.5.3 Baud rate generator prescaler mode registers 0 to 3 (BPRM0 to BPRM3)
These registers control the timer/count operation of the dedicated baud rate generator and select a count clock.
They can be read/written in 8- or 1-bit units.
7
6
0
5
0
4
0
3
0
2
1
0
Address
FFFFF086H
After reset
00H
BPRM0
BPRM1
BPRM2
BPRM3
BRCE0
BPR02 BPR01 BPR00
BPR12 BPR11 BPR10
BPR22 BPR21 BPR20
BPR32 BPR31 BPR30
Address
FFFFF096H
After reset
00H
BRCE1
BRCE2
BRCE3
0
0
0
0
0
0
0
0
0
0
0
0
Address
FFFFF0A6H
After reset
00H
Address
FFFFF0B6H
After reset
00H
Bit Position
Bit Name
BRCEn
Function
7
Baud Rate Generator Count Enable
Controls count operation of BRGn.
0 : Stops count operation with cleared
1 : Enables count operation
2 to 0
BPRn3 to BPRn0 Baud Rate Generator Prescaler
Specifies count clock input to internal timer (TMBRGn).
BPRn2 BPRn1 BPRn0
Count Clock
(k = 0): CSI use disabled
0
0
0
1
1
0
0
0
1
0
1
0
1
φ
0
φ/2 (k = 1)
φ/4 (k = 2)
φ/8 (k = 3)
φ/16 (k = 4)
φ/32 (k = 5)
Setting prohibited
0
0
1
1
Others
k: Set value of prescaler, φ: Internal system clock
Caution Do not change the count clock during transmission/reception operation.
Remark n = 0 to 3
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CHAPTER 8 SERIAL INTERFACE FUNCTION
8.6 Selection of Operational Serial Interface
CSI0 and CSI1 of the V854 are alternate pins for UART and I2C. Therefore, they are used selecting either UART
or I2C.
The selection is made by the following registers.
(1) Selecting CSI0 or UART
The setting is made by the ASIM0 register and the CSIM0 register.
ASIM0 Register
CSIM0 Register
Selection of Operational Peripheral I/O
TXE
RXE
CTXE0
CRXE0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
Operation stops
Selects UART
0
1
1
0
Selects CSI
0
0
Others
Setting prohibited
(2) Selecting CSI1 or I2C
The setting is made by the IICC register and the CSIM1 register.
IICC Register
CSIM1 Register
Selection of Operational Peripheral I/O
IICE
CTXE1
CRXE1
0
0
0
0
1
1
0
0
1
0
1
Operation stops
Selects I2C
1
0
Selects CSI
0
0
Others
Setting prohibited
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[MEMO]
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CHAPTER 9 A/D CONVERTER
9.1 Features
Analog input: 16 channels
8-bit A/D converter
On-chip A/D conversion result register (ADCR0 to ADCR7)
8 bits x 8
A/D conversion trigger mode
A/D trigger mode
Timer trigger mode
External trigger mode
Sequential conversion
9.2 Configuration
The A/D converter of the V854 adopts the sequential conversion method, and uses the A/D converter mode
registers (ADM0, ADM1), and ADCRn register to perform A/D conversion operations (n = 0 to 7).
(1) Input circuit
Selects the analog input (ANI0 to ANI15) according to the mode set to the ADM0 and ADM1 registers and
then sends it to the sample and hold circuit.
(2) Sample and hold circuit
Samples the analog input sent from the input circuit one by one and sends it to the comparator. During A/
D conversion operations, holds the analog input sampled.
(3) Voltage comparator
Compares the voltage difference between the input analog input and voltage tap of the serial resistor string
output.
(4) Serial resistor string
Generates voltage to coincide with analog input.
The serial resistor string is connected between the reference voltage pin for A/D converter (AVREF) and GND
pin for A/D converter (AVSS). The serial resistor consists of 255 equivalent resistors and two resistors with
half the resistance so that the connection between the two pins is made of 256 equal voltage steps.
The voltage tap of the serial resistor string is selected by a tap selector controlled by the successive
approximation register (SAR).
(5) Successive approximation register (SAR)
8-bit register for setting data for which the value of the voltage tap of the serial resistor string coincides with
the voltage value of the analog input from the most significant bit (MSB) in 1-bit units.
When the setting is made to the least significant bit (LSB) (A/D conversion ends), the contents of the SAR
(conversion result) are held in the A/D conversion result register (ADCRn).
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CHAPTER 9 A/D CONVERTER
(6) A/D Conversion Result Register n (ADCRn)
8-bit register for retaining the A/D conversion result. The conversion result is loaded from the sequential
conversion register (SAR) each time A/D conversion ends.
This register becomes undefined by RESET input.
(7) Controller
Selects the analog input, generates the sample hold circuit operation timing, and controls the conversion trigger
according to the mode set to the ADM0/ADM1 register.
(8) ANI0 to ANI15 pins
16-channel analog input pins for the A/D converter. Input the analog signal to be A/D converted.
Caution
Use ANI0 to ANI15 input voltages within the specification. Especially, if the voltage
exceeding VDD or less than VSS (even if it is within the range of the absolute maximum rating)
is input, the conversion value of the channel may become undefined or the conversion value
of other channels may be affected.
(9) AVREF pin
Pin for inputting the reference voltage of the A/D converter. Converts signals input to the ANI0 to ANI5 pins
to digital signals based on the voltage applied between AVREF and AVSS.
Figure 9-1. Block Diagram of A/D Converter
Serial resistor string
Sample & hold circuit
AVREF
R/2
ANI0
ANI1
R
ANI2
ANI3
ANI4
R/2
AVSS
ANI5
ANI6
ANI7
Voltage
AVDD
comparator
7
7
0
SAR (8)
8
ANI8
ANI9
8
0
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
Noise
Edge
ADTRG
elimination detection
INTAD
Controller
0 7
INTCC03
7
0
ADM0 (8) ADM1 (8)
8
8
8
Internal bus
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CHAPTER 9 A/D CONVERTER
9.3 Control Register
(1) A/D converter mode register 0 (ADM0)
The ADM0 register is an 8-bit register which executes the selection of the analog input pin, specification of
the operation mode, and conversion operations.
This register can be read/written in 8- or 1-bit units, However, when the data is written to the ADM0 register
during A/D conversion operations, the conversion operation is initialized and conversion is executed from the
beginning. Bit 6 cannot be written in and writing executed is ignored.
7
6
5
4
3
2
1
0
Address
FFFFF380H
After reset
00H
ADM0
CE
CS
BS
MS
PS
ANIS2
ANIS1
ANIS0
Bit Position
Bit Name
Function
7
6
5
4
3
CE
Convert Enable
Enables or disables A/D conversion operation.
0: Disabled
1: Enabled
CS
BS
MS
PS
Converter Status
Indicates the status of A/D converter. This bit is read only.
0: Stops
1: Operates
Buffer Select
Specifies buffer mode in the select mode.
0: 1-buffer mode
1: 4-buffer mode
Mode Select
Specifies operation mode of A/D converter.
0: Scan mode
1: Select mode
Pin Select
Switches the analog input pin.
0: Selects ANI0 to ANI7
1: Selects ANI8 to ANI15
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CHAPTER 9 A/D CONVERTER
Bit Position
2 to 0
Bit Name
Function
ANIS2 to
ANIS0
Analog Input Select
Specifies analog input pin to A/D convert.
ANIS2 ANIS1 ANIS0 Select Mode
Scan Mode
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
ANI0/ANI8
ANI1/ANI9
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI0/ANI8
ANI0, ANI1/ANI8, ANI9
ANI0 to ANI2/ANI8 to ANI10
ANI0 to ANI3/ANI8 to ANI11
ANI0 to ANI4/ANI8 to ANI12
1
1
1
0
1
1
1
0
1
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
ANI0 to ANI5/ANI8 to ANI13
ANI0 to ANI6/ANI8 to ANI14
ANI0 to ANI7/ANI8 to ANI15
Caution
When the CE bit is 1 in the timer trigger mode and external trigger mode, the trigger signal
standby state is set. To clear the CE bit, write “0” or reset.
In the A/D trigger mode, the conversion trigger is set by writing 1 to the CE bit. After the
operation, when the mode is changed to the timer trigger mode or external trigger mode without
clearing the CE bit, the trigger input standby state is set immediately after the change.
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CHAPTER 9 A/D CONVERTER
(2) A/D converter mode register 1 (ADM1)
The ADM1 register is an 8-bit register which specifies the conversion operation time and trigger mode.
This register can be read/written in 8- or 1-bit units. However, when the data is written to the ADM1 register
during A/D conversion, the conversion operation is initialized and conversion is executed from the beginning
again.
7
0
6
0
5
4
3
0
2
1
0
Address
FFFFF382H
After reset
07H
TRG1
TRG0
FR2
FR1
FR0
ADM1
Bit Position
5 and 4
Bit Name
Function
TRG1 and
TRG0
Trigger Mode
Specifies trigger mode.
TRG1 TRG0
Trigger Mode
0
1
1
1
0
1
0
1
A/D trigger mode
Timer trigger mode
External trigger mode
Setting prohibited
2 to 0
FR2 to FR0
Frequency
Specifies conversion operation time.
FR2
FR1
FR0
Number of
Conversion Operation Time (µs)
Conversion Clock φ = 33 MHz φ = 25 MHz φ = 16 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
60
–
–
3.1
3.8
–
–
80
–
3.2
4.0
4.8
5.6
7.2
8.0
5.0
100
120
140
180
200
3.0
3.6
4.2
5.4
6.0
6.3
7.5
8.8
11.3
12.5
(3) A/D conversion result register (ADCR0 to ADCR7)
The ADCRn register is an 8-bit register holding the A/D conversion results. It is provided with eight 8-bit
registers.
This register can only be read in 8-/1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF390H to Undefined
FFFFF39EH
After reset
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADCRn
Remark n = 0 to 7
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The following shows the correspondence of each analog input pin to the ADCRn register (except 4-buffer mode).
Analog Input Pin
PS = 0 PS =1
ADCRn Register
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
Figure 9-2 shows the relation between the analog input voltage and the A/D conversion result.
Figure 9-2. Relation between Analog Input Voltage and A/D Conversion Result
255
254
A/D conversion
253
result (ADCRn)
3
2
1
0
1
1
3
2
5
3
507 254 509 255 511
512 256 512 256 512
1
512 256 512 256 512 256
Input voltage/AVREF
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9.4 A/D Converter Operation
9.4.1 Basic operation of A/D converter
A/D conversion is executed in the following order.
(1) The selection of the analog input and specification of the operation mode and trigger mode, etc., should
be set in the ADMn registerNote 1 (n = 0, 1).
When the CE bit of the ADM0 register is set (1), A/D conversion starts during the A/D trigger mode. During
the timer trigger mode and external trigger mode, the trigger standby stateNote 2 is set.
(2) The voltage generated from the voltage tap of the serial resistor string and analog input are compared
by the comparator.
(3) When the comparison of the 8 bits ends, the conversion results are stored in the ADCRn register. When
A/D conversion is performed for the specified number of times, the A/D conversion end interrupt (INTAD)
is generated (n = 0 to 7).
Notes 1. When the ADMn register (n = 0, 1) is changed during A/D conversion, the A/D conversion operation
started before the change is stopped and the conversion results are not stored in the ADCRn register
(n = 0 to 7).
2. During the timer trigger mode and external trigger mode, if the CE bit of the ADM0 register is set to
1, the mode changes to the trigger standby state. The A/D conversion operation is started by the trigger
signal, and the trigger standby state is returned when the A/D conversion operation ends.
9.4.2 Operation mode and trigger mode
The A/D converter can specify various conversion operations by specifying the operation mode and trigger mode.
The operation mode and trigger mode are set by the ADMn register (n = 0, 1).
The following shows the relation between the operation mode and trigger mode.
Trigger Mode
Operation Mode
Setting Value
Analog Input
ADM0
ADM1
A/D trigger
Select
1 buffer
xx01xxxxB
xx11xxxxB
xxx0xxxxB
xx01xxxxB
xx11xxxxB
xxx0xxxxB
xx01xxxxB
xx11xxxxB
xxx0xxxxB
00000xxxB ANI0 to ANI15
00000xxxB
4 buffers
Scan
00000xxxB
Timer trigger
Select
1 buffer
00010xxxB
4 buffers
00010xxxB
Scan
00010xxxB
External trigger
Select
1 buffer
00100xxxB
4 buffers
00100xxxB
Scan
00100xxxB
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(1) Trigger mode
There are three types of trigger modes which serve as the start timing of A/D conversion processing: A/D trigger
mode, timer trigger mode, and external trigger mode. These trigger modes are set by the ADM0 register.
(a) A/D trigger mode
Generates the conversion timing of the analog input for the ANI0 to ANI15 pins inside the A/D converter
unit.
(b) Timer trigger mode
Specifies the conversion timing of the analog input set for the ANI0 to ANI15 pins using the values set
to the RPU compare register.
This register creates the analog input conversion timing by generating the coincidence interrupts of the
capture/compare registers (CC03) connected to the 24-bit TM10.
(c) External trigger mode
Mode which specifies the conversion timing of the analog input to the ANI0 to ANI15 pins using the ADTRG
pin.
(2) Operation mode
There are two types of operation modes which set the ANI0 to ANI15 pins: select mode and scan mode. The
select mode has sub-modes including the one-buffer mode and four-buffer mode. These modes are set by
the ADM0 register.
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(a) Select mode
A/D converts one analog input specified by the ADM0 register. The conversion results are stored in the
ADCRn register corresponding to the analog input (n = 0 to 7). For this mode, the one-buffer mode and
four-buffer mode are provided for storing the A/D conversion results.
• One-buffer mode
A/D converts one analog input specified by the ADM0 register. The conversion results are stored in
the ADCRn register corresponding to the analog input. The analog input and ADCRn register
correspond one to one, and an A/D conversion end interrupt (INTAD) is generated each time one A/
D conversion ends.
Figure 9-3. Operation Timing Example of Select Mode: 1-Buffer Mode (ANI1)
Analog input
ADCR register
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D converter
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• Four-buffer mode
A/D converts one analog input four times and stores the results in the four registers corresponding to
analog input. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions
end.
Figure 9-4. Operation Timing Example of Select Mode: 4-Buffer Mode (ANI6) (1/2)
Data 4
Data 5
ANI6
Data 1
Data 2
Data 3
Data 6
Data 7
Data 1
(ANI6)
Data 2
(ANI6)
Data 3
(ANI6)
Data 4
(ANI6)
Data 5
(ANI6)
Data 6
(ANI6)
Data 7
(ANI6)
A/D conversion
Data 1
(ANI6)
ADCR4
Data 2
(ANI6)
ADCR5
Data 3
(ANI6)
ADCR6
Data 4
(ANI6)
ADCR7
Data 6
(ANI6)
ADCR4
ADCR
INTAD
Conversion starts
ADM0 setting
Conversion starts
ADM0 setting
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Figure 9-4. Operation Timing Example of Select Mode: 4-Buffer Mode (ANI6) (2/2)
Analog input
ADCR register
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D converter
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(b) Scan mode
Selects the analog inputs specified by the ADM0 register sequentially from the ANI0 pin, and A/D
conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to
the analog input. When the conversion of the specified analog input ends, the INTAD interrupt is generated
(n = 0 to 7).
Figure 9-5. Operation Timing Example of Scan Mode: 4-Channel Scan (ANI0 to ANI3) (1/2)
ANI0
Data 1
Data 5
Data 6
ANI1
Data 7
Data 2
ANI2
ANI3
Data 3
Data 4
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI0)
Data 7
(ANI1)
A/D conversion
Data 1
(ANI0)
ADCR0
Data 2
(ANI1)
ADCR1
Data 3
(ANI2)
ADCR2
Data 4
(ANI3)
ADCR3
Data 6
(ANI0)
ADCR0
ADCRn
INTAD
Conversion starts
ADM0 setting
Conversion starts
ADM0 setting
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Figure 9-5. Operation Timing Example of Scan Mode: 4-Channel Scan (ANI0 to ANI3) (2/2)
Analog input
ADCR register
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D converter
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9.5 Operation in the A/D Trigger Mode
When the CE bit of the ADM0 register is set to 1, A/D conversion is started.
9.5.1 Select mode operation
The A/D converter converts the analog input specified by the ADM0 register. The conversion results are stored
in the ADCRn register corresponding to the analog input. In the select mode, the one-buffer mode and four-buffer
mode are supported according to the storing method employed for the A/D conversion results (n = 0 to 7).
(1) 1-buffer mode (A/D trigger select: 1-buffer)
The A/D converter converts one analog input once. The conversion results are stored in one ADCRn register.
The analog input and ADCRn register correspond one to one. (Refer to Table 9-1, Figure 9-6.)
Each time an A/D conversion is executed, an INTAD interrupt is generated and the AD conversion terminates.
When 1 is written to the CE bit of the ADM0 register, A/D conversion can be restarted.
This mode is suitable for applications which read out the result in each A/D conversion.
Table 9-1. Correspondence between Analog Input Pin and ADCRn Register
(1-buffer mode (A/D trigger select 1-buffer))
Analog Input
ANI0/ANI8
A/D Conversion Results Register
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI1/ANI9
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
Figure 9-6. Example of 1-Buffer Mode (A/D trigger select 1-buffer) Operation
ADM0
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter
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(2) 4-buffer mode (A/D trigger select: 4-buffer)
The A/D converter converts one analog input four times and stores the results in four ADCRn registers. (Refer
to Table 9-2, Figure 9-7.) When A/D conversion ends four times, an INTAD interrupt is generated and the
A/D conversion terminates.
When 1 is written to the CE bit of the ADM0 register, A/D conversion is ended.
This mode is suitable for applications which calculate the average of the A/D conversion result.
Table 9-2. Correspondence between Analog Input Pin and ADCRn Register
(4-buffer mode (A/D trigger select 4-buffer))
Analog Input
A/D Conversion Results Register
ADCR0 (First time)
ANI0 to ANI3/ANI8 to ANI11
ADCR1 (Second time)
ADCR2 (Third time)
ADCR3 (Fourth time)
ANI4 to ANI17/ANI12 to ANI15 ADCR4 (First time)
ADCR5 (Second time)
ADCR6 (Third time)
ADCR7 (Fourth time)
Figure 9-7. Example of 4-Buffer Mode (A/D trigger select 4-buffer) Operation
ADM0
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
(×4)
(×4)
A/D Converter
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9.5.2 Scan mode operation
The analog inputs from ANI0/ANI8 to the analog input specified with the ADM0 register are selected sequentially
and converted to digital. The A/D conversion results are stored in the ADCRn register corresponding to the analog
input. (Refer to Table 9-3, Figure 9-8.)
When the conversion of all the specified analog inputs ends, the INTAD interrupt is generated, and A/D conversion
is ended.
When 1 is written to the CE bit of the ADM0 register, A/D conversion can be restarted.
This mode is suitable for applications which always monitor two or more analog inputs.
Table 9-3. Correspondence between Analog Input Pin and ADCRn Register
(scan mode (A/D trigger scan)
Analog Input
ANI0/ANI8
A/D Conversion Results Register
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI1/ANI9
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
Figure 9-8. Example of Scan Mode (A/D trigger scan) Operation
ADM0
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter
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9.6 Operation in the Timer Trigger Mode
The A/D converter can set conversion timings with the coincidence interrupt signals of the RPU compare register.
TM0 and the capture/compare register (CC03) are used for the timer for specifying the analog conversion trigger.
The following two modes are provided according to the specification of the TMC00 register.
(1) One-shot mode
To use the one-shot mode, 1 should be set to the OST0 bit of the TMC00 register (one-shot mode).
When the A/D conversion period is longer than the TM0 period, the TM0 generates an overflow, holds 000000H
and stops. Thereafter, TM00 does not output the coincidence interrupt signal INTCC03 (A/D conversion
trigger) of the compare register, and the A/D converter goes into the A/D conversion standby state. The TM0
count operation restarts when the valid edge of the TCLR0 pin input is detected or when 1 is written to the
CE0 bit of the TMC00 register.
(2) Loop mode
To use the loop mode, 0 should be set to the OST0 bit (normal mode) of the TMC00 register.
When the TM0 generates an overflow, the TM0 starts counting from 000000H again, and the coincidence
interrupt signal INTCC03 (A/D conversion trigger) of the compare register is repeatedly output and A/D
conversion is also repeated.
Coincidence of the compare register can also clear TM0 and restart it.
9.6.1 Select mode operation
The A/D converter converts an analog input (ANI0 to ANI15) specified by the ADM0 register. The conversion results
are stored in the ADCRn register corresponding to the analog input. For the select mode, the one-buffer mode and
four-buffer mode are provided according to the storing method employed for the A/D conversion results.
(1) 1-buffer mode operation (Timer trigger select: 1-buffer)
The A/D converter converts one analog input once and stores the conversion results in one ADCRn register
(Refer to Table 9-4, Figure 9-9).
The A/D converter converts one analog input once using the trigger of the coincidence interrupt signal
(INTCC03) and stores the results in one ADCRn register.
An INTAD interrupt is generated for each A/D conversion and the A/D conversion is ended.
When TM0 is set to the one-shot mode, A/D conversion is ended after one conversion operation. To restart
the A/D conversion, input the valid edge to the TCLR0 pin or write 1 to the CE0 bit of the TMC00 register.
When TM0 is set to the loop mode, A/D conversion is repeated each time the coincidence interrupt is generated,
unless the CE bit of the ADM0 register is set to 0.
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Table 9-4. Correspondence between Analog Input Pin and ADCRn Register
(1-buffer mode (timer trigger select 1-buffer))
Trigger
Analog Input
A/D Conversion
Results Register
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
ANI0/ANI8
ADCR0
ANI1/ANI9
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
Figure 9-9. Example of 1-Buffer Mode (timer trigger select 1-buffer) Operation
INTCC03
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter
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(2) 4-buffer mode operation (Timer trigger select: 4-buffer)
A/D conversion of one analog input is executed four times, and the results are stored in the ADCRn register
(Refer to Table 9-5, Figure 9-10).
The A/D converter converts one analog input four times using the coincidence interrupt signal (INTCC03) as
a trigger, and stores the results in four ADCRn registers.
An INTAD interrupt is generated when the four A/D conversion operations end, and the A/D conversion is
ended.
When the TM0 is set to the one-shot mode, and less than four coincidence interrupts are generated, if the
CE bit is set to 1, the INTAD interrupt is not generated and the standby state is set.
This mode is suitable for applications which calculate the average of the A/D conversion result.
Table 9-5. Correspondence between Analog Input Pin and ADCRn Register
(4-buffer mode (timer trigger select 4-buffer))
Trigger
Analog Input
A/D Conversion
Results Register
INTCC03 interrupt
ANI0 to ANI3/ANI8 to ANI11
ADCR0 (First time)
ADCR1 (Second time)
ADCR2 (Third time)
ADCR3 (Fourth time)
INTCC03 interrupt
ANI4 to ANI7/ANI12 to ANI15 ADCR4 (First time)
ADCR5 (Second time)
ADCR6 (Third time)
ADCR7 (Fourth time)
Figure 9-10. Example of Operation in 4-Buffer Mode (timer trigger select 4-buffer)
INTCC03
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
(×4)
A/D Converter
(×4)
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9.6.2 Scan mode operation
The analog inputs from ANI0/ANI8 to the analog input specified with the ADM0 register are selected sequentially,
and A/D conversion is executed the number of times specified using the coincidence interrupt as trigger.
The conversion results are stored in the ADCRn register corresponding to the analog input (refer to Table 9-6,
Figure 9-11). When the conversion of all the specified analog inputs has been ended, the INTAD interrupt is generated
and A/D conversion is ended. When the coincidence interrupt is generated after all the specified A/D conversion
operations end, A/D conversion is restarted.
When TM0 is set to the one-shot mode, and less than the specified number of coincidence interrupts are generated
the INTAD interrupt is not generated and the standby state is set if the CE bit is set to 1.
This mode is suitable for applications which always monitor two or more analog inputs.
Table 9-6. Correspondence between Analog Input Pin and ADCRn Register
(scan mode (timer trigger scan))
Trigger
Analog Input
A/D Conversion
Results Register
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
INTCC03 interrupt
ANI0/ANI8
ADCR0
ANI1/ANI9
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
Figure 9-11. Example of Scan Mode (timer trigger scan) Operation
INTCC03
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter
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9.7 Operation in the External Trigger Mode
In the external trigger mode, the analog inputs (ANI0 to ANI3) are A/D converted by the ADTRG pin input timing.
The ADTRG pin is also used as the P22 pin. To set the external trigger mode, set the PMC22 bit of the PMC2
register to 1 and bits TRG1 to TRG0 of the ADM1 register to 10.
For the valid edge of the external input signal during the external trigger mode, the rising edge, falling edge, or
both rising and falling edges can be specified using the ESAD1 and ESAD0 bits of the INTM5 register. For details,
refer to 5.3.8 (2) External interrupt mode registers 1 to 6 (INTM1 to INTM6).
9.7.1 Select mode operation (External trigger select)
The A/D converter converts one analog input (ANI0 to ANI15) specified by the ADM0 register. The conversion
results are stored in the ADCRn register corresponding to the analog input. Two select modes, one-buffer mode and
four-buffer mode are available for storing the conversion results.
(1) 1-buffer mode (External trigger select: 1-buffer)
The A/D converter converts one analog input using the ADTRG signal as a trigger. The conversion results
are stored in one ADCRn register (refer to Table 9-7, Figure 9-12). The analog input and the A/D conversion
results register correspond one to one. An INTAD interrupt is generated after one A/D conversion, and A/
D conversion ends.
While the CE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from the
ADTRG pin.
This mode is suitable for applications which read out the result in each A/D conversion.
Table 9-7. Correspondence between Analog Input Pin and ADCRn Register
(1-buffer mode (external trigger select 1-buffer))
Trigger
Analog Input
A/D Conversion
Results Register
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ANI0/ANI8
ADCR0
ANI1/ANI9
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
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Figure 9-12. Example of 1-Buffer Mode (external trigger select 1-buffer) Operation
ADTRG
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter
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(2) 4-buffer mode (External trigger select: 4-buffer)
The A/D converter converts one analog input four times using the ADTRG signal as a trigger and stores the
results in four ADCRn registers (refer to Table 9-8, Figure 9-13). The INTAD interrupt is generated and
conversion ends when the four A/D conversions end.
While the CE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from the
ADTRG pin.
This mode is suitable for applications which calculate the average of the A/D conversion result.
Table 9-8. Correspondence between Analog Input Pin and ADCRn Register
(4-buffer mode (external trigger select 4-buffer))
Trigger
Analog Input
A/D Conversion
Results Register
ADTRG signal
ANI0 to ANI3/ANI8 to ANI11
ADCR0 (First time)
ADCR1 (Second time)
ADCR2 (Third time)
ADCR3 (Fourth time)
ADTRG signal
ANI4 to ANI7/ANI12 to ANI15 ADCR4 (First time)
ADCR5 (Second time)
ADCR6 (Third time)
ADCR7 (Fourth time)
Figure 9-13. Example of 4-Buffer Mode (external trigger select 4-buffer) Operation
ADTRG
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter
(×4)
(×4)
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9.7.2 Scan mode operation (External trigger scan)
The analog inputs from ANI0/ANI8 to the analog input specified with the ADM0 register are selected sequentially
and converted to digital when triggered by the ADTRG signal. The A/D conversion results are stored in the ADCRn
register corresponding to the analog input (refer to Table 9-9, Figure 9-14). When the conversion of all the specified
analog inputs ends, the INTAD interrupt is generated and A/D conversion is ended.
While the CE bit of the ADM0 register is 1, A/D conversion is restarted every time a trigger is input from the ADTRG
pin.
This mode is suitable for applications which always monitor two or more analog inputs.
Table 9-9. Correspondence between Analog Input Pin and ADCRn Register
(scan mode (external trigger scan))
Trigger
Analog Input
A/D Conversion
Results Register
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
ANI0/ANI8
ADCR0
ANI1/ANI9
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
Figure 9-14. Example of Scan Mode (external trigger scan) Operation
ADTRG
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter
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CHAPTER 9 A/D CONVERTER
9.8 Precautions Regarding Operations
9.8.1 Stop of conversion operations
When 0 is written to the CE bit of the ADM0 register during conversion, conversion stops and the conversion results
are not stored in the ADCRn register (n = 0 to 7).
9.8.2 Interval of the external/timer trigger
Set the interval (input time interval) of the trigger during the external or timer trigger mode longer than the conversion
time specified by the FR2 to FR0 bits of the ADM1 register.
When 0 < interval ≤ conversion operation time
When the next external trigger or timer trigger is input during conversion, conversion stops and conversion
starts according to the last timer trigger input.
When conversion operations are stopped, the conversion results are not stored in the ADCRn register
(n = 0 to 7). However, the number of triggers input are counted, and when an interrupt is generated, the
value at which conversion ended is stored in the ADCRn register.
9.8.3 Operation in the standby mode
(1) HALT mode
Continues A/D conversion operations. When canceled by NMI input, the ADM0/ADM1 register and ADCRn
register hold the value (n = 0 to 7).
(2) IDLE mode, STOP mode
As clock supply to the A/D converter is stopped, no conversion operations are performed. When canceled
using NMI input, the ADM0/ADM1 register and the ADCRn register hold the value (n = 0 to 7). However, when
these modes are set during conversion, conversion stops. At this time, if canceled using the NMI input, the
conversion operation resumes, but the conversion result written to the ADCRn register will become undefined.
In the IDLE and STOP modes, operation of the serial resistor string is also stopped to reduce the power
consumption. To further reduce current consumption, set the voltage of the AVREF to VSS.
9.8.4 Compare coincide interrupt in the timer trigger mode
The coincidence interrupt of the compare register becomes the A/D conversion start trigger and conversion
operations are started. At this time, the coincidence interrupt of the compare register also functions as the coincidence
interrupt of the compare register for the CPU. To prevent generation of the coincidence interrupt of the compare
register for the CPU, set interrupt disable using the interrupt mask bit (CC0MK3) of the interrupt control register
(CC0IC3).
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CHAPTER 10 REAL-TIME OUTPUT FUNCTION
10.1 Configuration and Function
The real-time output function is realized by hardware consisting principally of the buffer register (PB) and the output
latch (RTP) as shown in Figure 10-1.
The real-time output function is a procedure that transfers the data previously prepared in the PB register to the
output latch by hardware simultaneously with the generation of CM10 coincidence interrupt of timer 1, and outputs
it to external. The pins to output the data to external are called a real time output port.
The real-time output function can handle 8-bit real-time output data.
Figure 10-1 shows the block diagram of the real-time output port.
Figure 10-1. Block Diagram of Real-Time Output Port
Internal bus
8
Buffer register (PB)
INTCM10
Output latch (RTP)
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10.2 Control Register
(1) Buffer register (PB)
The buffer register is a register to which the data to be output from the real-time output port is written
beforehand.
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF3C0H
After reset
Undefined
PB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
(2) Output latch (RTP)
The output latch is a register to which the data of the PB register is transferred by the coincidence signal with
the CM10 register. Write the value to be output to external to the RTP register before setting the port as a
real-time output port with the PMC13 register.
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF3C2H
After reset
Undefined
RTP
RTP7
RTP6
RTP5
RTP4
RTP3
RTP2
RTP1
RTP0
10.3 Operation
When the corresponding bit is set to the control mode by the PMC13 register, the output pins can be used as a
real-time output port. These pins can be accessed by the PB register and the RTP register.
The data is output by the following procedure.
<1> The data is written to the PB register.
<2> The contents of the PB register is transferred to the RTP register at the generation timing of the compare
coincidence interrupt of timer (INTCM10).
<3> The contents of the RTP register is output to the pins set as the real time output port.
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10.4 Example
The following shows an example of using RTP0 to RTP7 as an 8-bit real-time output port.
The contents of the buffer register (PB) is output to RTP0 to RTP7 in each coincidence of the contents of TM1
and CM10 of timer 1. At this time, the interrupt processing routine is generated in which the data to be output next
and the timing to change the output next are set (refer to Figure 10-2).
For the use of timer 1, refer to 7.2.2 Timer 1.
Figure 10-2. Operational Timings of Real-Time Output Port
FFFFFFH
Timer 1
CM10
CM10
CM10
CM10
0H
INTCM10
interrupt request
Buffer register
PB
D01
D00
D00
D02
D03
D04
Output latch
RTP
D01
D02
D03
Output pins
RTP0 to RTP7
Hi-Z
D01
D02
D03
Rewrites PB and CM10 in the interrupt processing routine of INTCM10
Transfers the contents of PB to the output latch by INTCM10
Timer starts
Turns on output buffer
Sets the data to be output to PB
Sets the first output data to the output latch (RTP)
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CHAPTER 11 PWM UNIT
11.1 Features
PWMn: 4 channels
12- to 16-bit PWM output port
Main pulse + additional pulse configuration
Main pulse 4/5/6/7/8 bits
Additional pulse 8 bits
Repeat frequency: 129 kHz to 2 MHz (fPWMC = 33 MHz)
Pulse width overwrite frequency selection: each one pulse/256 pulse
Active level of the PWM output pulse can be selected.
Operation clock: Can be selected from φ, φ /2, φ /4, φ /8, and φ /16. (φ is the internal system clock)
Remark n = 0 to 3
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11.2 Configuration
Figure 11-1 shows the configuration of the output circuit of PWMn.
(1) Prescaler
Divides the frequency of φ and generates PWM operational clock (fPWMC). Prescaler output is selected by the
PWPn0/PWPn1 bit of the PWPRn register.
(2) Reload control
Controls the reload of the modulo values of x-bit down counter and the 8-bit counter.
2x/fPWMC or 2x+8/fPWMC is selected by the SYNn bit of the PWMCn register for the reload timing (PWM pulse
width rewrite cycle).
(3) x-bit down counter
Controls the output timings of the main pulse.
The value of the modulo H register is loaded to this counter by the reload signal generated in the reload controls
and decremented by PWM operational clock (fPWMC).
Figure 11-1. Configuration of PWM Unit
Internal bus
8
16
8
PWMn
15
8
7
0
PWPRn
PWMCn
x
8
2x/fPWMC 2x+8/fPWMC
Reload
Reload
Selector
fPWMC
φ
/2
/4
/8
x-bit down counter
1/2x
PWM pulse
generation circuit
φ
φ
φ
Output control
circuit
Selector
PWMn
8-bit counter
Remark n = 0 to 3
x = 4 to 8 (specified with the PRM bit)
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11.3 Control Register
(1) PWM control register 0 to 3 (PWMC0 to PWMC3)
Controls PWMn operation, specifies the output active level, and specifies the bit length of the main pulse.
This register can be read/written in 8- or 1-bit units. The contents of this register can also be changed during
PWMn operation (PWME = 1).
7
6
5
4
0
3
0
2
1
0
Address
FFFFF360H to
FFFFF378H
After reset
05H
PWMCn
PMPn2 PMPn1 PMPn0
SYNn PWMEn PALVn
Bit Position
7 to 5
Bit Name
Function
PMPn2 to
PMPn0
PWM Main Pulse
Specifies bit length of x-bit down counter (main pulse)
`
PMPn2 PMPn1 PMPn0
Bit Length
0
0
0
1
1
0
0
1
0
1
0
8 bits
0
7 bits
0
6 bits
0
5 bits
1
4 bits
Others
Setting prohibited
2
1
SYNn
Rewrite Cycle
Specifies PWM pulse width rewrite cycle
0: Large cycle (every PWM 2x+8 cycles (2x+8/fPWMC))
1: Small cycle (every PWM 1 cycle (2x/fPWMC))
PWMEn
PWM Enable
Controls operation/stop of PWMn
0: Operation stops
1: Operation in progress
PWM counter is cleared by changing this bit from 0 to 1.
0
PALVn
PWM Active Level
Specifies PWMn active level
0: Active low
1: Active high
Remark n = 0 to 3
x: number of bits set with PRM
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(2) PWM prescaler register 0 to 3 (PWPR0 to PWPR3)
This register selects the operation clock (fPWMC) of PWMn, and can be read/written in 8- or 1-bit units. Change
the contents of this register while the bits of the PWMCn register are 0. If the contents of this register are
changed when the setting of the PWMEn bit is 1, the operation cannot be guaranteed.
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address
FFFFF364H to
FFFFF37CH
After reset
00H
PWPRn
PWPn1 PWPn0
Bit Position
1, 0
Bit Name
Function
PWPn1,
PWPn0
PWM Prescaler Clock Mode
Selects operation clock of PWMn
PWPn1 PWPn0
Operation Clock (fPWMC)
0
0
1
1
0
1
0
1
φ
φ /2
φ /4
φ /8
φ: Internal system clock
Remark n = 0 to 3
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CHAPTER 11 PWM UNIT
(3) PWM modulo registers 0 to 3 (PWM0 to PWM3)
The PWM modulo registers 0 to 3 are 16-bit registers used to determine the pulse width of the PWMn pulse.
These registers can be read/written in 16-bit units.
These registers consist of the following two parts.
<1> Modulo H register (bit 8 to bit 15)
Indicates the number of bits specified with the PMPn bit of the PWMCn register. This value is the accuracy
when generating the main pulse.
The pulse width rewrite timing depends on the number of bits of this register.
When selecting 4 to 7 bits for the counter with the PMPn bit, set 0 to the rest of the higher bits.
<2> Modulo L register (bit 0 to bit 7)
The value of this register determines the additional timings of the additional pulse to perform minute
adjustment (refer to Figure 11-3).
The value of this register becomes undefined by RESET input. Set the data with initialization program before
enabling PWM output.
The value from 0000H to FFFFH can be set to the PWMn register, and PWM output also changes linearly. When
0000H is set, inactive level is retained. When FFFFH is set, one additional pulse (1/fPWMC) becomes inactive by one
rewrite cycle (216/fPWMC) (refer to Figure 11-4).
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
FFFFF362H to
FFFFF37AH
After reset
Undefined
PWMn
Modulo H register
(for main pulse generation)
Modulo L register
(for additional pulse generation)
Remark n = 0 to 3
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11.4 PWM Operations
11.4.1 Basic operations of PWM
The duty of the PWM pulse output is determined as follows by the value set to the modulo H register of the PWM
modulo register (PWMn: n = 0 to 3 ).
(Value of modulo H register)Note 1 + 1Note 2
Duty of PWM pulse output =
2x
Notes 1. 0 ≤ (Value of modulo H register) ≤ 2x - 1
2. With additional pulse
Remark x = 4 to 8
The repeat frequency of the PWM pulse output is the frequency of the 2x frequency division (= fPWMC/2x) of the PWM
clock (fPWMC) of φ to φ/4 set by the PWM prescaler register (PWPR), and the minimum pulse width is 1/fPWMC.
The PWM pulse output realizes 12- to 16-bit resolution by repeatedly outputting the PWM signal with 4- to 8-bit
resolution and fPWMC/2x repeat frequency for 256 times. The PWM pulse signal with 12- to 16-bit resolution is realized
in 256 cycles by controlling the addition of the additional pulse (1/fPWMC) to the PWM pulse with 4- to 8-bit resolution
determined by the modulo H register according to the value of the modulo L register in 1-cycle units.
Figure 11-2. Basic Operations of PWM
PWM signal
Note
1 cycle of 12- to 16-bit PWM signal
Note PWM pulse: 1 cycle 4- to 8-bit resolution
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Figure 11-3. Example of PWM Output by Main Pulse and Additional Pulse
16-bit resolution is gained when the 256 outputs are averaged
0
1
2
3
4
5
6
7
8
9
10
11
12
13 254 255
PWMn = xx40H
Main pulse
BRM additional pulse
(Modulo L = 40H)
PWM output
PWMn = xxC0H
Main pulse
BRM additional pulse
(Modulo L = C0H)
PWM output
1/fPWMC x T
x
1/fPWMC
1/fPWMC x 2x
Remark fPWMC
: PWM clock frequency
: value of modulo H register
: number of bits of modulo H register (selected with PMP bit)
TX
x
Active level : high level
Figure 11-4. Example of PWM Output Operation
16-bit resolution is gained when the 256 outputs are averaged
10 11 12
0
1
2
3
4
5
6
7
8
9
13 254 255
PWMn = 0000H
Main pulse
L
BRM additional pulse
(Modulo L = 00H)
L
L
PWM output
PWMn = 0001H
Main pulse
BRM additional pulse
(Modulo L = 01H)
L
PWM output
PWMn = FFFFH
Main pulse
BRM additional pulse
(Modulo L = FFH)
PWM output
Remark Condition: number of bits of modulo H register = 8 bits, 16-bit accuracy, active level = high level
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11.4.2 Enabling/disabling PWM operation
To output the PWM pulse, the PWME bit of the PWM control register (PWMCn) is set (1) after setting data to the
PWM prescaler register (PWPRn) and the PWM modulo register (PWMn) (n = 0 to 3).
Thereby, PWM pulse with active level specified by the PALVn bit of the PWMCn register is output from the PWM
output pin.
When the PWMEn bit of the PWMCn register is cleared (0), the PWM output unit immediately stops the PWM output
operation, and the PWM output pin becomes inactive.
(1) Setting when PWM operation starts
When the PWMEn bit of the PWMCn register is set, PWMn goes into operation status. However, the PWM
pin maintains the port mode status even after the operation status is set until the reload signal of the PWMn
register is generated. In addition, the value of the PWMn register is not loaded to the x-bit down counter.
Therefore, when the pulse width rewrite timing is set to 2x+8 (large cycle: SYN bit = 0), operation starts in 2x+8
/
fPWMC max. after the PWMEn bit is set. The SYNn bit of the PWMCn register can be rewritten even during
PWM output.
Initialize the following registers before starting PWMn operation.
• PMC10 register : Setting of the control mode
• PWMn register : Setting of the pulse width
• PWPRn register : Specification of the operational clock of the PWM output circuit
• PWMCn register : Specification of the PWM pulse width rewrite cycle, specification of active level of PWM
pin, PWM operation control, and selection of the number of bits of the main pulse
(2) Setting when PWM operation stops
When the PWMEn bit of the PWMCn register is reset, PWM operation immediately stops.
Figure 11-5. Operation Timing of PWM
PWMEn bit
2x/fPWMC
2x/fPWMC
2x/fPWMC
Reload signal
PWM output
Operation setting
PWM operation setting
PWM operation stop
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11.4.3 Specification of active level of PWM pulse
The PALVn bit of the PWM control register (PWMCn) specifies the active level of the PWM pulse output from the
PWM output pin (n = 0 to 3).
When the PALVn bit is set (1), a pulse with high active level is output, and when it is cleared (0), a pulse with low
active level is output.
When the PALVn bit is rewritten, the active level of the PWM output immediately changes. Figure 11-6 shows
the active level setting and the pin status of the PWM output.
The active level of the PWM output can be changed by manipulating the PALVn bit, regardless of the setting of
the PWMEn bit (enabling/disabling PWM).
Figure 11-6. Setting of Active Level of PWM Output
PALVn
PWMn
(High active)
(Low active)
(Rewriting PALVn bit)
Remark PWMEn = 1 (n = 0 to 3)
11.4.4 Specification of PWM pulse width rewrite cycle
Starting PWM output and changing the PWM pulse width are performed in synchronization either with each 2(x+8)
cycles (2(x+8)/fPWMC) of the PWM pulse or with each 1 cycle (2x/fPWMC) of the PWM pulse. The specification of the PWM
pulse width rewrite cycle is performed with the SYNn bit of the PWMCn register (n = 0 to 3).
When the SYNn bit is cleared (0), the pulse width is changed at every 2(x+8) cycles (2(x+8)/fPWMC) of the PWM pulse.
Therefore, it will take 2(x+8) clocks max. before the pulse with the width corresponding to the data written to the PWMn
register is output.
Figure 11-7 shows an example of the PWM output timing.
On the other hand, when the SYNn bit is set (1), the pulse width is changed at every 1 cycle of the PWM pulse
(2x/fPWMC). In this case, it will take 2x clocks max. before the pulse with the width corresponding to the data written
to the PWMn register is output.
When the PWM pulse rewriting cycle is specified as every 2x/fPWMC (when the SYNn bit is set (1)), the accuracy
of the PWM pulse gained is x bits or more and (x+8) bits or less, which is lower than the accuracy when the rewriting
cycle is specified as 2(x+8)/fPWMC. However, the response is improved because the repeat frequency is increased.
Figure 11-8 shows an example of the PWM output timing when the rewrite timing is 2x/fPWMC.
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Figure 11-7. Example 1 of PWM Output Timing (PWM pulse width rewrite cycle 2(x+8)/fPWMC)
PWM pulse
2(x+8) cycles
PWM pulse
2(x+8) cycles
PWMn
output pin
Contents of
PWMn register
m
l
Enables
PWM output
Rewrites
PWMn register
PWM pulse width
rewrite timing
PWM pulse width
rewrite timing
PWM pulse width
rewrite timing
Cautions 1. The pulse width is rewritten at every 256 cycles of the PWM pulse.
2. The accuracy of the PWM pulse is (x + 8) bits.
Remarks 1. m and l are the contents of the PWMn register.
2. n = 0 to 3
Figure 11-8. Example 2 of PWM Output Timing (PWM pulse width rewrite cycle 2x/fPWMC)
PWM pulse
1 cycle
PWMn
output pin
Contents of
PWMn register
m
k
l
m
Enables
PWM output PWMn register
Rewrites
Rewrites
PWMn register
Rewrites
PWMn register
PWM pulse width
selecting timing
Cautions 1. The pulse width is rewritten at every 1 cycle of the PWM pulse.
2. The accuracy of the PWM pulse is x bits or more and (x + 8) bits or less.
Remarks 1. k, l, and m are the contents of the PWMn register.
2. n = 0 to 3
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11.4.5 Repetition frequency
The repetition frequency of the PWMn is shown below (n = 0 to 3).
Main Pulse
Additional Pulse
Repetition Frequency
Pulse Width Rewrite Cycle
Large Cycle (SYNn bit = 0) Small Cycle (SYNn bit = 1)
4 bits
8 bits
8 bits
8 bits
8 bits
8 bits
fPWMC/16
fPWMC/212
fPWMC/213
fPWMC/214
fPWMC/215
fPWMC/216
fPWMC/24
fPWMC/25
fPWMC/26
fPWMC/27
fPWMC/28
5 bits
6 bits
7 bits
8 bits
fPWMC/32
fPWMC/64
fPWMC/128
fPWMC/256
fPWMC: Select from φ, φ/2, φ/4, and φ/8 by the PWPRn register.
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CHAPTER 12 PORT FUNCTION
12.1 Features
The ports of the V854 have the following features:
Number of pins: input: 16
I/O: 96
Also function as I/O pins of other peripheral functions
Can be set in input/output mode in 1-bit units
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12.2 Basic Configuration of Ports
The V854 is provided with a total of 112 input/output port pins (of which 16 are input-only port pins) that make up
ports 0 to 14. The configuration of the V854’s ports is shown below. (P20 cannot be used for a port function.)
P00
to
P70
to
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
P07
P77
P10
to
P80
to
Port 8
P17
P87
P20
P21
to
P90
to
Port 9
P96
P26
P30
to
P100
to
Port 10
Port 11
Port 12
Port 13
Port 14
P36
P103
P40
to
P110
to
P47
P117
P50
to
P120
to
P57
P127
P60
to
P130
to
P67
P137
P140
to
P147
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(1) Function of each port
The ports of the V854 have the functions shown in the table below.
Each port can be manipulated in 8- or 1-bit units and perform various types of control operations. In addition
to port functions, the ports also have functions as internal hardware input/output pins, when placed in the
control mode.
For the details, refer to the description of each port. Figure 12-1 to 12-11 show the block diagram of the ports.
Port
Pin
Port Function
8-bit I/O
Function in Control Mode
Real time pulse unit (RPU) input/output
Port 0
P00 to P07
External interrupt request input (capture trigger input)
Port 1
Port 2
Port 3
P10 to P17
P20 to P26Note
P30 to P36
8-bit I/O
6-bit I/O
RPU input/output
External interrupt request input (capture trigger input)
P17 is only for port.
Non-maskable interrupt request input
External interrupt request input (capture trigger input)
Analog trigger input
7-bit I/O
8-bit I/O
Serial interface input/output (UART, CSI, I2C)
P36 is only for port.
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port 11
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P96
P100 to P103
P110 to P117
Address/data bus for external memory
8-bit I/O
Address bus for external memory
8-bit input
Analog input to A/D converter (only for input in the port mode)
7-bit I/O
4-bit I/O
8-bit I/O
Control signal input/output for external memory
PWM control signal output
RPU input/output
External interrupt request input
Port 12
P120 to P127
8-bit I/O
Serial interface input/output
Clock output
P126 is only for port.
Port 13
Port 14
P130 to P137
P140 to P147
8-bit I/O
8-bit I/O
Real-time output port
Only for port
Note P20 cannot be used for a port function.
Caution when outputting in the control mode or switching a port that operates as an input/output pin
to the control mode, take the following steps.
(1) Set the corresponding bit of port n (Pn)(n = 0, 1, 3 to 6, 9 to 13) to the inactive level of the
output signal in the control mode.
(2) Switch to the control mode with a port n mode control register (PMCn).
If (1) above is omitted, the contents of port n (Pn) may momentarily be output when switching
from the port mode to control mode.
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(2) Register for setting function at reset and port/control mode of each port pin
(1/2)
Function after Reset (Input/output is shown in parentheses)
Register for
Port Name
Port 0
Pin Name
In Single-Chip In Single-Chip
Mode 2
In ROM-less
Mode 1
In ROM-less
Mode 2
Setting Mode
PMC0
Mode 1
P00 (input)
P01 (input)
P02 (input)
P03 (input)
P04 (input)
P05 (input)
P06 (input)
P07 (input)
P10 (input)
P11 (input)
P12 (input)
P13 (input)
P14 (input)
P15 (input)
P16 (input)
P17 (input)
NMI (input)
P21 (input)
P22 (input)
P23 (input)
P24 (input)
P25 (input)
P26 (input)
P30 (input)
P31 (input)
P32 (input)
P33 (input)
P34 (input)
P35 (input)
P36 (input)
P00/TO00
P01/TO01
P02/INTP00
P03/INTP01
P04/INTP02
P05/INTP03
P06/INTP04/TCLR0
P07/INTP05/TI0
P10/INTP10
P11/INTP11
P12/INTP12
P13/INTP13
P14/INTP14/TI1
P15/TO20
Port 1
PMC1
P16/INTP20/TI20
P17
Port 2
P20/NMI
–
P21/INTP30
P22/ADTRG
P23/INTP50
P24/INTP51
P25/INTP52
P26/INTP53
P30/SO0/TDX
P31/SI0/RXD
P32/SCK0
PMC2
Port 3
PMC3
P33/SO1/SDA
P34/SI1
P35/SCK1/SCL
P36
Port 4
Port 5
Port 6
P40/AD0 to P47/AD7
P50/AD8 to P57/AD15
P60/A16 to P67/A23
P40 to P47 (all input)
P50 to P57 (all input)
P60 to P67 (all input)
AD0 to AD7 (all input/output)
AD8 to AD15 (all input/output) MM
AD16 to A23 (all output) MM
MM
Port 7
Port 8
P70/ANI0 to P77/ANI7
P70/ANI0 to P77/ANI7 (all input)
–
–
P80/ANI8 to P87/ANI15 P80ANI8 to P87ANI15 (all input)
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(2/2)
Function after Reset (Input/output is shown in parentheses)
Register for
Setting Mode
Port Name
Port 9
Pin Name
In Single-Chip In Single-Chip In ROM-less
In ROM-less
Mode 2
Mode 1
Mode 2
Mode 1
P90/LBEN/WRL
P91/UBEN
P90 (input)
LBEN (output) WRL (output) MM
UBEN (output)
P91 (input)
P92 (input)
P93 (input)
P94 (input)
P95 (input)
P96 (input)
P100 (input)
P101 (input)
P102 (input)
P103 (input)
P110 (input)
P111 (input)
P112 (input)
P113 (input)
P114 (input)
P115 (input)
P116 (input)
P117 (input)
P120 (input)
P121 (input)
P122 (input)
P123 (input)
P124 (input)
P125 (input)
P126 (input)
P127 (input)
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
R/W (output)
WRH (output)
DSTB (output) RD (output)
ASTB (output)
P95/HLDAK
P96/HLDRQ
P100/PWM0
P101/PWM1
P102/PWM2
P103/PWM3
P110/TO21
P111/INTP21/TI21
P112/TO22
P113/INTP22/TI22
P114/TO23
P115/INTP23/TI23
P116/TO24
P117/INTP24/TI24
P120/SO2
Port 10
Port 11
PMC10
PMC11
Port 12
PMC12
P121/SI2
P122/SCK2
P123/SO3
P124/SI3
P125/SCK3
P126
P127/CLO
Port 13
Port 14
P130/RTP0 to P137/RTP7 P130 to P137 (all input)
P140 to P147 P140 to P147 (all input)
PMC13
–
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Figure 12-1. Block Diagram of Type A
WRPMC
PMCmn
WRPM
PMmn
Output signal
in control mode
WRPORT
Pmn
Pmn
RDIN
Address
Remark m: port number
n: bit number
Figure 12-2. Block Diagram of Type B
WRPMC
PMCmn
WRPM
PMmn
WRPORT
Pmn
Pmn
Address
RDIN
Input signal
in control mode
Noise elimination
Edge detection
Remark m: port number
n: bit number
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Figure 12-3. Block Diagram of Type C
WRPMC
WRPM
PMCmn
PMmn
Output signal
in control mode
WRPORT
Pmn
Pmn
Address
RDIN
Input signal
in control mode
Remark m: port number
n: bit number
Figure 12-4. Block Diagram of Type D
WRPMC
PMCmn
PMmn
WRPM
WRPORT
Pmn
Pmn
Address
RDIN
Input signal
in control mode
Remark m: port number
n: bit number
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Figure 12-5. Block Diagram of Type E
MODE0 to MODE2 MM0 to MM2
Input/output control circuit
WRPM
PMmn
Output signal
in control mode
WRPORT
Pmn
Pmn
Address
RDIN
Input signal
in control mode
Remark m: port number
n: bit number
Figure 12-6. Block Diagram of Type F
MODE0 to MODE2 MM0 to MM2
Input/output control circuit
WRPM
PMmn
Output signal
in control mode
WRPORT
Pmn
Pmn
Address
RDIN
Remark m: port number
n: bit number
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Figure 12-7. Block Diagram of Type G
Pmn
Input signal
in control mode
ANI0 to ANI15
RDIN
Remark m: 7, 8
n: 0 to 7
Figure 12-8. Block Diagram of Type H
MODE0 to MODE2 MM0 to MM2
Input/output control circuit
WRPM
PM96
P96
WRPORT
P96
Address
RDIN
Input signal
in control mode
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Figure 12-9. Block Diagram of Type I
1
Noise
elimination
P20
Address
RDIN
Edge detection
NMI
Figure 12-10. Block Diagram of Type J
WRPM
PMmn
Pmn
WRPORT
Pmn
RDIN
Address
Remark m: port number
n: bit number
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Figure 12-11. Block Diagram of Type K
WRPMC
WRPM
PMCmn
PMmn
Pmn
Output signal
WRPORT
in control mode
N-ch
Pmn
Address
RDIN
Input signal
in control mode
Remark m: port number
n: bit number
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12.3 Port Pin Function
12.3.1 Port 0
Port 0 is an 8-bit input/output port that can be set to the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF000H
After reset
Undefined
P0
P07
P06
P05
P04
P03
P02
P01
P00
Bit Position
7 to 0
Bit Name
Function
P0n
(n = 7 to 0)
Port 0
I/O port
In addition to the function as a general I/O port, this port can also be used to input/output signals of the real-time
pulse unit (RPU) and input external interrupt requests, when placed in the control mode.
(1) Operations in control mode
Port
Port 0 P00
P01
Control Mode
TO00
Function in Control Mode
Block Type
A
RPU output
TO01
P02
INTP00
External interrupt request input/RPU capture trigger input
B
P03
INTP01
P04
INTP02
P05
INTP03
P06
TCLR0/INTP04
TI0/INTP05
External interrupt request input/RPU input
P07
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(2) Setting input/output mode and control mode
The input/output mode of port 0 is set by port mode register 0 (PM0). The control mode is set by port mode
control register 0 (PMC0).
Port 0 mode register (PM0)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF020H
After reset
FFH
PM0
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
Bit Position
7 to 0
Bit Name
Function
PM00 to PM07
Port Mode
Sets P00 to P07 pins in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Port 0 mode control register (PMC0)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF040H
Afetr reset
00H
PMC0
PMC07 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00
Bit Position
Bit Name
PMC07
Function
7
Port mode Control
Specifies operation mode of P07 pin.
0: I/O port mode
1: External interrupt request input (INTP05)/TI0 input mode
6
5 to 2
1
PMC06
Port Mode Control
Specifies operation mode of P06 pin.
0: I/O port mode
1: External interrupt request input (INTP04)/TCLR0 input mode
PMC05 to
PMC02
Port Mode Control
Specifies operation mode of P05 to P02 pins.
0: I/O port mode
1: External interrupt request input (INTP03 to INTP00)
PMC01
PMC00
Port Mode Control
Specifies operation mode of P01 pin.
0: I/O port mode
1: TO01 output mode
0
Port Mode Control
Specifies operation mode of P00 pin.
0: I/O port mode
1: TO00 output mode
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12.3.2 Port 1
Port 1 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF002H
After reset
Undefined
P1
P17
P16
P15
P14
P13
P12
P11
P10
Bit Position
7 to 0
Bit Name
Function
P1n
(n = 7 to 0)
Port 1
I/O port
In addition to the function as a general I/O port, this port can also be used to input/output signals of the real-time
pulse unit (RPU), and to input external interrupts when placed in the control mode.
(1) Operations in control mode
Port
Port 1 P10
P11
Control Mode
INTP10
Function in Control Mode
Block Type
B
External interrupt request input/RPU capture trigger input
INTP11
INTP12
INTP13
TI1/INTP14
TO20
P12
P13
P14
External interrupt request input
RPU output
P15
A
B
J
P16
TI20/INTP20
–
External interrupt request input/RPU input
Port only
P17
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(2) Setting input/output mode
The input/output mode of port 1 is set by port mode register 1 (PM1). The control mode is set by port mode
control register 1 (PMC1).
Port 1 mode register (PM1)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF022H
After reset
FFH
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
Bit Position
7 to 0
Bit Name
Function
PM1n
Port Mode
(n = 7 to 0)
Sets P1n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Port 1 mode control register (PMC1)
This register can be read/written in 8- or 1-bit units. However, bit 7 is fixed to “0” and ignored when “1” is written.
7
0
6
5
4
3
2
1
0
Address
FFFFF042H
After reset
00H
PMC1
PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10
Bit Position
6
Bit Name
PMC16
Function
Port Mode Control
Specifies operation mode of P16 pin.
0: I/O port mode
1: External interrupt request input (INTP20)/TI20 input mode
5
4
PMC15
PMC14
Port Mode Control
Specifies operation mode of P15 pin.
0: I/O port mode
1: TO20 output mode
Port Mode Control
Specifies operation mode of P14 pin.
0: I/O port mode
1: External interrupt request input (INTP14)/TI1 input mode
3 to 0
PMC13 to
PMC10
Port Mode Control
Specifies operation mode of P13 to P10 pins.
0: I/O port mode
1: External interrupt request input (INTP13 to INTP10)
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12.3.3 Port 2
Port 2 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. P20, however, always
operates as the NMI input when an edge is input.
7
–
6
5
4
3
2
1
0
Address
FFFFF004H
After reset
Undefined
P2
P26
P25
P24
P23
P22
P21
P20
Bit Position
6 to 1
Bit Name
Function
P2n
Port 2
I/O port
NMI input level
(n = 6 to 1)
0
P20
In addition to the function as a port, this port can also be used as the external interrupt request input, when placed
in the control mode.
When port 2 is accessed in 8-bit units for write, the data in the higher 1 bit is ignored. When it is accessed in 8-
bit units for read, undefined data is read.
(1) Operations in control mode
Port
Port 2 P20
P21
Control Mode
NMI
Function in Control Mode
Non-maskable interrupt request input
External interrupt request input (capture trigger input)
A/D converter trigger input
Block Type
I
INTP30
ADTRG
INTP50
INTP51
INTP52
INTP53
B
P22
P23
External interrupt request input
P24
P25
P26
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(2) Setting input/output mode and control mode
The input/output mode of port 2 is set by port mode register 2 (PM2). The control mode is set by port mode
control register 2 (PMC2). P20 is fixed to NMI input.
Port 2 mode register (PM2)
This register can be read/written in 8- or 1-bit units. However, bit 0 and bit 7 are fixed to “1” by hardware and
ignored when 0 is written in.
7
1
6
5
4
3
2
1
0
1
Address
FFFFF024H
After reset
FFH
PM2
PM26
PM25
PM24
PM23
PM22
PM21
Bit Position
6 to 1
Bit Name
Function
PM2n
(n = 6 to 1)
Port Mode
Sets P2n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Port 2 mode control register (PMC2)
This register can be read/written in 8- or 1-bit units. However, bit 0 is fixed to “1” by hardware, and ignored
when “0” is written. Bit 7 is fixed to “0” by hardware, and ignored when “1” is written.
7
0
6
5
4
3
2
1
0
1
Address
FFFFF044H
After reset
01H
PMC2
PMC26 PMC25 PMC24 PMC23 PMC22 PMC21
Bit Position
6 to 3
Bit Name
Function
PMC26 to
PMC23
Port Mode Control
Sets operation mode of P26 to P23 pins.
0: I/O port mode
1: External interrupt request input (INTP53 to INTP50)
2
1
PMC22
PMC21
Port Mode Control
Sets operation mode of P22 pin.
0: I/O port mode
1: AD converter trigger input (ADTRG)
Port Mode Control
Sets operation mode of P21 pin.
0: I/O port mode
1: External interrupt request input (INTP30)
Remark Bit 0 is fixed to NMI input mode.
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12.3.4 Port 3
Port 3 is a 7-bit input/output port that can be set in the input or output mode in 1-bit units.
7
–
6
5
4
3
2
1
0
Address
FFFFF006H
After reset
Undefined
P3
P36
P35
P34
P33
P32
P31
P30
Bit Position
6 to 0
Bit Name
Function
P3n
(n = 6 to 0)
Port 3
I/O port
In addition to the function as a port, this port can also be used as the input/output lines of the serial interface (UART,
CSI, I2C), when placed in the control mode. P33 and P35 are multiplexed with SDA and SCL pin of I2C bus, respectively,
and output is N-ch open drain.
When port 3 is accessed in 8-bit units for write, the data in the higher 1 bit is ignored. When it is accessed in 8-
bit units for read, undefined data is read.
(1) Operations in control mode
Port
Port 3 P30
P31
Control Mode
SO0/TXD
Function in Control Mode
Block Type
Serial interface I/O (UART, CSI, I2C)
A
D
C
K
D
K
J
SI0/RXD
SCK0
P32
P33
SO1/SDA
SI1
P34
P35
SCK1/SCL
–
P36
Port only
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(2) Setting input/output mode and control mode
The input/output mode of port 3 is set by port mode register 3 (PM3). The control mode is set by port mode
control register 3 (PMC3).
Port 3 mode register (PM3)
This register can be read/written in 8- or 1-bit units.
7
1
6
5
4
3
2
1
0
Address
FFFFF026H
After reset
FFH
PM3
PM36
PM35
PM34
PM33
PM32
PM31
PM30
Bit Position
6 to 0
Bit Name
Function
PM3n
(n = 6 to 1)
Port Mode
Sets P3n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
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Port 3 mode control register (PMC3)
This register can be read/written in 8- or 1-bit units. However, the higher 2 bits are fixed to “0” by hardware,
and ignored when “1 “ is written in.
7
0
6
0
5
4
3
2
1
0
Address
FFFFF046H
After reset
00H
PMC3
PMC35 PMC34 PMC33 PMC32 PMC31 PMC30
Bit Position
Bit Name
Function
5
4
3
2
1
0
PMC35
Port Mode Control
Sets operation mode of P35 pin.
0: I/O port mode
1: SCK1/SCL output mode
PMC34
PMC33
PMC32
PMC31
PMC30
Port Mode Control
Sets operation mode of P34 pin.
0: I/O port mode
1: SI1 input mode
Port Mode Control
Sets operation mode of P33 pin.
0: I/O port mode
1: SO1/SDA output mode
Port Mode Control
Sets operation mode of P32 pin.
0: I/O port mode
1: SCK0 I/O mode
Port Mode Control
Sets operation mode of P31 pin.
0: I/O port mode
1: SI0/RXD input mode
Port Mode Control
Sets operation mode of P30 pin.
0: I/O port mode
1: SO0/TXD output mode
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12.3.5 Port 4
Port 4 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF008H
After reset
Undefined
P4
P47
P46
P45
P44
P43
P42
P41
P40
Bit Position
7 to 0
Bit Name
Function
P4n
(n = 7 to 0)
Port 4
I/O port
In addition to the function as a general I/O port, this port also serves as an external address/data bus for external
memory expansion, when placed in the control mode (external expansion mode).
(1) Operation in control mode
Port
Control Mode
Function in Control Mode
Block Type
E
Port 4
P40 to P47 AD0 to AD7
Address/data bus for external memory
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(2) Setting input/output mode and control mode
The input/output mode of port 4 is set by port mode register 4 (PM4). The control mode (external expansion
mode) is set by mode specification pins MODE and memory expansion mode register (MM: refer to 3.4.6 (1))
(n = 0 to 2).
Port 4 mode register (PM4)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF028H
After reset
FFH
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
Bit Position
7 to 0
Bit Name
Function
PM4n
Port Mode
Sets P4n pin in input/output mode.
(n = 7 to 0)
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Operation mode of port 4
Bit of MM Register
Operation Mode
MM2 MM1 MM0 P40
P41 P42
P43
Port
P44 P45
P46
P47
0
0
1
1
1
0
0
1
0
1
1
1
0
Address/data bus
(AD0 to AD7)
0
1
Others
RFU (reserved)
For the details of mode selection by the MODE pins, refer to 3.3.2 Specifying operation mode.
In the ROM-less mode, MM0 to MM2 bits are initialized to 111 at system reset, enabling the external expansion
mode. External expansion can be disabled by programming the MM0 to MM2 bits and setting the port mode. If MM0
to MM2 are cleared to 000, the subsequent external instruction cannot be fetched.
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12.3.6 Port 5
Port 5 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF00AH
After reset
Undefined
P5
P57
P56
P55
P54
P53
P52
P51
P50
Bit Position
7 to 0
Bit Name
P5n
Function
Port 5
I/O port
(n = 7 to 0)
In addition to the function as a general I/O port, this port also serves as an external address/data bus for external
memory expansion, when placed in the control mode (external expansion mode).
(1) Operation in control mode
Port
Control Mode
Function in Control Mode
Block Type
E
Port 5
P50 to P57 AD8 to AD15 Address/data bus for external memory
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(2) Setting input/output mode and control mode
The input/output mode of port 5 is set by port mode register 5 (PM5). The control mode (external expansion
mode) is set by mode specification pins MODEn and memory expansion mode register (MM: refer to 3.4.6
(1)) (n = 0 to 2).
Port 5 mode register (PM5)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF02AH
After reset
FFH
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
Bit Position
7 to 0
Bit Name
Function
PM5n
(n = 7 to 0)
Port Mode
Sets P5n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Operation mode of port 5
Bit of MM Register
Operation Mode
MM2 MM1 MM0 P50
P51
P52
P53 P54
Port
P55 P56
P57
0
0
1
1
1
0
0
1
0
1
1
1
0
Address/data bus
(AD8 to AD15)
0
1
Others
RFU (reserved)
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12.3.7 Port 6
Port 6 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF00CH
After reset
Undefined
P6
P67
P66
P65
P64
P63
P62
P61
P60
Bit Position
7 to 0
Bit Name
Function
P6n
(n = 7 to 0)
Port 6
I/O port
In addition to the function as a general I/O port, this port also serves as an external address bus for external memory
expansion, when placed in the control mode (external expansion mode).
(1) Operation in control mode
Port
Control Mode
Function in Control Mode
Block Type
F
Port 6
P60 to P67 A16 to A23
Address bus for external memory expansion
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(2) Setting input/output mode and control mode
The input/output mode of port 6 is set by port mode register 6 (PM6). The control mode (external expansion
mode) is set by mode specification pins MODEn and memory expansion mode register (MM: refer to 3.4.6
(1)) (n = 0 to 2).
Port 6 mode register (PM6)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF02CH
After reset
FFH
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
Bit Position
7 to 0
Bit Name
Function
PM6n
(n = 7 to 0)
Port Mode
Sets P6n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Operation mode of port 6
Bit of MM Register
Operation Mode
MM2 MM1 MM0 P60
P61 P62
P63
P64
Port
P65
P66
P67
0
0
1
1
1
1
0
0
1
0
1
0
1
1
0
A16
A17
A18
0
A19
1
1
A20
A21
A22
A23
Others
RFU (reserved)
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12.3.8 Port 7, port 8
Port 7 and port 8 are 8-bit input only ports and all pins of port 7 and port 8 are fixed in the input mode.
7
6
5
4
3
2
1
0
Address
FFFFF00EH
After reset
Undefined
P7
P8
P77
P76
P75
P74
P73
P72
P71
P70
7
6
5
4
3
2
1
0
Address
FFFFF010H
After reset
Undefined
P87
P86
P85
P84
P83
P82
P81
P80
In addition to the function as input ports, these ports can also always be used as analog input for the A/D converter.
These ports are used also as the analog input pins (ANI0 to ANI7 and ANI8 to ANI15), but the input port and analog
input pin cannot be switched. The status of each pin can be read by reading out ports.
(1) Normal operation
Port
Control Mode
Function in Control Mode
Block Type
G
Port 7
Port 8
P70 to P77 ANI0 to ANI7 Analog input to A/D converter
P80 to P87 ANI8 to ANI15 (only for input in port mode)
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12.3.9 Port 9
Port 9 is a 7-bit input/output port that can be set in the input or output mode in 1-bit units.
7
–
6
5
4
3
2
1
0
Address
FFFFF012H
After reset
Undefined
P9
P96
P95
P94
P93
P92
P91
P90
Bit Position
6 to 0
Bit Name
Function
P9n
(n = 6 to 0)
Port 9
I/O port
In addition to the function as a general I/O port, this port can also be used to output external bus control signals
and output bus hold control signals, when placed in the control mode (external expansion mode). When port 9 is
accessed in 8-bit units for write, the higher 1 bit is ignored. When it is accessed in 8-bit units for read, undefined
data is read.
(1) Operations in control mode
Port
P90
Control Mode
LBEN/WRL
UBEN
Function in Control Mode
Block Type
F
Port 9
Control signal output for external memory
P91
P92
P93
P94
P95
P96
R/W/WRH
DSTB/RD
ASTB
HLDAK
Bus hold acknowledge signal output
Bus hold request signal input
HLDRQ
H
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(2) Setting input/output mode and control mode
The input/output mode of port 9 is set by port mode register 9 (PM9). The control mode (external expansion
mode) is set by the mode specification pin MODEn and the memory expansion mode register (MM: refer to
3.4.6 (1)) (n = 0 to 2).
Port 9 mode register (PM9)
This register can be read/written in 8- or 1-bit units. However, bit 7 is ignored during write access, and undefined
during read access.
7
–
6
5
4
3
2
1
0
Address
FFFFF032H
After reset
FFH
PM9
PM96
PM95
PM94
PM93
PM92
PM91
PM90
Bit Position
6 to 0
Bit Name
Function
PM9n
(n = 6 to 0)
Port Mode
Sets P9n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Operation mode of port 9
P90 to P94
P95, P96
Bit of MM Register
Operation Mode
MM3
Operation Mode
Port mode
P95
Port
P96
MM2 MM1 MM0 P90
P91
P92
Port
P93
P94
0
1
0
0
1
1
1
0
0
1
0
1
1
External expansion mode HLDAK HLDRQ
1
LBEN, UBEN R/W, DSTB, ASTB
0
WRL
WRH RD
0
1
Others
RFU (reserved)
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12.3.10 Port 10
Port 10 is a 4-bit input/output port that can be set in the input or output mode in 1-bit units.
7
–
6
–
5
–
4
–
3
2
1
0
Address
FFFFF014H
After reset
Undefined
P10
P103
P102
P101
P100
Bit Position
3 to 0
Bit Name
Function
P10n
(n = 3 to 0)
Port 10
I/O port
When port 10 is accessed in 8-bit units for write, the data in the higher 4 bits is ignored. When it is accessed in
8-bit units for read, undefined data is read.
In addition to the function as a general I/O port, this port can also be used to output the PWMn.
(1) Operations in control mode
Port
P100
Control Mode
PWM0
Function in Control Mode
PWM control signal output
Block Type
A
Port 10
P101
P102
P103
PWM1
PWM2
PWM3
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(2) Setting input/output mode and control mode
The input/output mode of port 10 is set by port mode register 10 (PM10). The control mode is set by port mode
control register 10 (PMC10).
Port 10 mode register (PM10)
This register can be read/written in 8- or 1-bit units. However, the higher 4 bits are fixed to “0” by hardware
and ignored when 0 is written in.
7
1
6
1
5
1
4
1
3
2
1
0
Address
FFFFF034H
After reset
FFH
PM10
PM103 PM102 PM101 PM100
Bit Position
3 to 0
Bit Name
Function
PM10n
Port Mode
(n = 3 to 0)
Sets P10n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Port 10 mode control register (PMC10)
This port can be read/written in 8- or 1-bit units. However, the higher 4 bits are fixed to “0” and ignored if “1”
is written in.
7
0
6
0
5
0
4
0
3
2
1
0
Address
FFFFF054H
After reset
00H
PMC10
PMC103 PMC102 PMC101 PMC100
Bit Position
3 to 0
Bit Name
Function
PMC10n
Port Mode Control
(n = 3 to 0)
Sets operation mode of P10n pin.
0: I/O port mode
1: PWMn output mode
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12.3.11 Port 11
Port 11 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF016H
After reset
Undefined
P11
P117
P116
P115
P114
P113
P112
P111
P110
Bit Position
7 to 0
Bit Name
P11n
(n = 7 to 0)
Function
Port 11
I/O port
In addition to the function as a port, this port can also be used to input/output signals of the real-time pulse unit
(RPU) and to input external interrupt requests, when placed in the control mode.
(1) Operations in control mode
Port
P110
Alternate Function
TO21
Function in Control Mode
RPU output
Block Type
Port 11
A
B
A
B
A
B
A
B
P111
P112
P113
P114
P115
P116
P117
TI21/INTP21
TO22
RPU input/external interrupt request input
RPU output
TI22/INTP22
TO23
RPU input/external interrupt request input
RPU output
TI23/INTP23
TO24
RPU input/external interrupt request input
RPU output
TI24/INTP24
RPU input/external interrupt request input
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(2) Setting input/output mode and control mode
The input/output mode of port 11 is set by port mode register 11 (PM11). The control mode is set by port mode
control register 11 (PMC11).
Port 11 mode register (PM11)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF036H
After reset
FFH
PM11
PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110
Bit Position
7 to 0
Bit Name
Function
PM11n
Port Mode
(n = 7 to 0)
Sets P11n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
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Port 11 mode control register (PMC11)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF056H
After reset
00H
PMC11
PMC117 PMC116 PMC115 PMC114 PMC113 PMC112 PMC111 PMC110
Bit Position
Bit Name
PMC117
Function
7
6
5
4
3
2
1
0
Port Mode Control
Sets P117 pin in input/output mode.
0: I/O port mode
1: External interrupt request input (INTP24)/TI24 input mode
PMC116
PMC115
PMC114
PMC113
PMC112
PMC111
PMC110
Port Mode Control
Sets P116 pin in input/output mode.
0: I/O port mode
1: TO24 output mode
Port Mode Control
Sets P115 pin in input/output mode.
0: I/O port mode
1: External interrupt request input (INTP23)/TI23 input mode
Port Mode Control
Sets P114 pin in input/output mode.
0: I/O port mode
1: TO23 output mode
Port Mode Control
Sets P113 pin in input/output mode.
0: I/O port mode
1: External interrupt request input (INTP22)/TI22 input mode
Port Mode Control
Sets P112 pin in input/output mode.
0: I/O port mode
1: TO22 output mode
Port Mode Control
Sets P111 pin in input/output mode.
0: I/O port mode
1: External interrupt request input (INTP21)/TI21 input mode
Port Mode Control
Sets P110 pin in input/output mode.
0: I/O port mode
1: TO21 output mode
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12.3.12 Port 12
Port 12 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF018H
After reset
Undefined
P12
P127
P126
P125
P124
P123
P122
P121
P120
Bit Position
7 to 0
Bit Name
P12n
Function
Port 12
I/O port
(n = 7 to 0)
In addition to the function as a port, this port can also be used as the input/output lines of the serial interface when
placed in the control mode.
(1) Operation in control mode
Port
P120
Alternate-Function Pin
Function in Control Mode
Serial interface output
Block Type
Port 12
SO2
SI2
A
D
C
A
D
C
J
P121
P122
P123
P124
P125
P126
P127
Serial interface input
Serial interface output
Serial interface output
Serial interface input
Serial interface output
Only for port
SCK2
SO3
SI3
SCK3
–
CLO
Clock output
A
(2) Setting input/output mode and control mode
The input/output mode of port 12 is set by the port mode register 12 (PM12). The control mode is set by the
port mode control register 12 (PMC12).
Port 12 mode register (PM12)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF038H
After reset
FFH
PM12
PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
Bit Position
7 to 0
Bit Name
Function
PM12n
Port Mode
(n = 7 to 0)
Set P12n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer ON)
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Port 12 mode control register (PMC12)
Port 12 can be read/written in 8- or 1-bit units. However, bit 6 is fixed to “0” by hardware and ignored if “1”
is written in.
7
6
0
5
4
3
2
1
0
Address
FFFFF058H
After reset
00H
PMC12
PMC127
PMC125 PMC124 PMC123 PMC122 PMC121 PMC120
Bit Position
Bit Name
PMC127
Function
7
5
4
3
2
1
0
Port Mode Control
Sets P127 pin in input/output mode.
0: I/O port mode
1: CLO output mode
PMC125
PMC124
PMC123
PMC122
PMC121
PMC120
Port Mode Control
Sets P125 pin in input/output mode.
0: I/O port mode
1: SCK3 input/output mode
Port Mode Control
Sets P124 pin in input/output mode.
0: I/O port mode
1: SI3 input mode
Port Mode Control
Sets P123 pin in input/output mode.
0: I/O port mode
1: SO3 output mode
Port Mode Control
Sets P122 pin in input/output mode.
0: I/O port mode
1: SCK2 input/output mode
Port Mode Control
Sets P121 pin in input/output mode.
0: I/O port mode
1: SI2 input mode
Port Mode Control
Sets P120 pin in input/output mode.
0: I/O port mode
1: SO2 output mode
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12.3.13 Port 13
Port 13 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF01AH
After reset
Undefined
P13
P137
P136
P135
P134
P133
P132
P131
P130
Bit Position
7 to 0
Bit Name
Function
P13n
Port 13
I/O port
(n = 7 to 0)
In addition to the function as a port, this port can also be used as the output of real time output port.
(1) Operation in control mode
Port
Alternate-Function Pin
Function in Control Mode
Real time output port
Block Type
A
Port 13
P130 to P137 RTP0 to RTP7
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(2) Setting input/output mode and control mode
The input/output mode of port 13 is set by port mode register 13 (PM13). The control mode is set by port mode
control register 13 (PMC13).
Port 13 mode register (PM13)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF03AH
After reset
FFH
PM13
PM137 PM136 PM135 PM134 PM133 PM132 PM131 PM130
Bit Position
7 to 0
Bit Name
Function
PM13n
Port Mode
(n = 7 to 0)
Sets P13n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
Port 13 mode control register (PMC13)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF05AH
After reset
00H
PMC13
PMC137 PMC136 PMC135 PMC134 PMC133 PMC132 PMC131 PMC130
Bit Position
7 to 0
Bit Name
Function
PMC13n
Port Mode Control
(n = 7 to 0)
Sets P13n pin in input/output mode.
0: I/O port mode
1: RTPn output mode
Caution When each bit is set to 1, the output buffer of the corresponding port is turned on,
regardless of the contents of the PM13 register, and the contents of the RTP register are
output. Therefore, initialize the contents of the RTP register before setting each bit to 1.
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12.3.14 Port 14
Port 14 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF01CH
After reset
Undefined
P14
P147
P146
P145
P144
P143
P142
P141
P140
Bit Position
7 to 0
Bit Name
P14n
(n = 7 to 0)
Function
Port 14
I/O port
Port 14 can be used only as a port.
(1) Operation in control mode
Port
P140 to P147
Alternate-Function Pin
–
Function in Control Mode
Block Type
Port 14
Port only
J
(2) Setting input/output mode and control mode
The input/output mode of port 14 is set by port mode register 14 (PM14). Port 14 does not have port mode
control register 14 (PMC14) because it is not provided with the control mode.
Port 14 mode register (PM14)
This register can be read/written in 8- or 1-bit units.
7
6
5
4
3
2
1
0
Address
FFFFF03CH
After reset
FFH
PM14
PM147 PM146 PM145 PM144 PM143 PM142 PM141 PM140
Bit Position
7 to 0
Bit Name
Function
PM14n
Port Mode
(n = 7 to 0)
Sets P14n pin in input/output mode.
0: Output mode (output buffer ON)
1: Input mode (output buffer OFF)
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When the low-level is input to the RESET pin, the system is reset and each on-chip hardware is initialized to the
initial state.
When the RESET pin changes from low-level to high-level, the reset state is released and the CPU starts executing
the program. Initialize the contents of each register in the program as necessary.
13.1 Features
Analog noise elimination circuit (delay of approx. 60 ns) provided on reset pin
13.2 Pin Function
During the reset state, all the pins (except CLKOUT, RESET, X2, VDD, VSS, CVDD, CVSS, AVDD, AVSS and AVREF
pins) are in the high-impedance state.
When an external memory is connected, a pull-up (or pull-down) resistor must be connected to each pin of ports
4, 5, 6, and 9. Otherwise, the memory contents may be lost if these pins go into a high-impedance state.
Also treat signal outputs of the on-chip peripheral I/O function and the output port so that they will not be affected.
In the ROM-less mode and single-chip mode 2, the CLKOUT signal is output even during the reset period (low
level output). In single-chip mode 1, the CLKOUT signal is not output until the PSC register is set. In the flash memory
programming mode, the CLKOUT signal is not output (low level output).
Table 13-1 shows the operating status of each pin during the reset period.
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Table 13-1. Operating Status of I/O and Output Pins During Reset Period
I/O or Output Pin
Pin Status
In Single-Chip In Single-Chip In ROM-less
In ROM-less In Flash Memory
Mode 1
Mode 2
Mode 1
Mode 2
Programming Mode
P00 to P07, P10 to P17, P21 to P26, P30 to (Input)
Hi-Z
P37, P95, P96, P100 to P103, P110 to P117,
P120 to P127, P130 to P137, P140 to P147
P40 to P47, P50 to P57, P69 to P67, P90 to P94 (Input)
(Control Mode)
Hi-Z
AD0 to AD15, A16 to A23
(Port mode)
LBEN
(P90)
Hi-Z
(WRL)
WRL
(P90)
(LBEN)
Hi-Z
Hi-Z
UBEN
R/W
(P91)
(P92)
Hi-Z
(WRH)
Hi-Z
WRH
(P92)
R/W
DSTB
(P93)
Hi-Z
(RD)
Hi-Z
RD
(P93)
(DSTB)
Hi-Z
ASTB
(P94)
HLDAK
CLKOUT
SO0, SO2, TXD
(Port mode)
L
Operates
L
(Port mode)
Operation
Hi-Z
TO00, TO01, TO20 to TO24, RTP0 to RTP7, (Port mode)
SDA, SDL, SO1, SO3, PWM0 to PWM3
Remark Hi-Z : High impedance
L
: Low-level output
(1) Accepting reset signal
RESET pin
Analog
delay
Analog
delay
Analog
delay
Eliminated as noise
Internal system
reset signal
Note
Reset
Reset
accepted
released
Note The internal system reset signal remains active for the duration of at least 4 system clocks after
the reset condition is removed from the RESET pin.
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(2) Power-ON reset
For the reset operations at power-on it is necessary to secure an oscillation stabilization time of 10 ms or more
from when the power supply starts until reset is accepted by the low-level width of the RESET pin. Furthermore,
it is also necessary to secure oscillation stabilization time when an external clock is used in the direct mode.
V
DD
RESET pin
Oscillation
stabilization
time
Analog delay
Reset released
13.3 Initialize
Table 13-2 shows the initial value of each register after reset.
The contents of the registers must be initialized in the program as necessary. Especially, set the following registers
as necessary because they are related to system setting:
Power save control register (PSC) ... X1 and X2 pin function, CLKOUT pin operation, etc.
Data wait control register (DWC) ... Number of data wait states
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Table 13-2. Initial Values after Reset of Each Register (1/2)
Register
Initial Value after Reset
00000000H
Undefined
00000000H
00000020H
Undefined
Undefined
Undefined
Undefined
00000000H
Undefined
Undefined
FFH
r0
r1 to r31
PC
PSW
EIPC
EIPSW
FEPC
FEPSW
ECR
Internal RAM
Port
Output latch (P0 to P6, P9 to P14)
Mode register (PM0 to PM6, PM9 to PM14)
Mode control register (PMC0, PMC1, PMC3, PMC10 to PMC13)
(PMC2)
00H
01H
Memory expansion mode register (MM)
System status register (SYS)
00H/07H
0000000xB
00H
Clock generator
Clock output
Clock output mode register (CLOM)
Real-time pulse unit
Timer control register
(TMC01, TMC02)
00H
01H
(TMC00, TMC1, TMC20 to TMC24, TMC3)
Timer output control register (TOC0, TOC1)
00H
Capture/compare register
Undefined
(CC00 to CC03, CC00L to CC03L, CC3)
Compare register (CM10, CM11, CM10L, CM11L, CM20 to CM24)
Capture register (CP10 to CP13, CP10L to CP13L, CP3)
Undefined
Undefined
Timer register (TM0, TM1, TM0L, TM1L, TM20 to TM24, TM3)
Timer overflow status register (TOVS)
0000H
00H
A/D converter
A/D converter mode register (ADM0, ADM1)
A/D conversion result register (ADCR0 to ADCR7)
07H
Undefined
Caution “Undefined” means an undefined value due to power-on reset or data corruption when a falling
edge of RESET coincides with a data write operation. The previous status of data is retained
by a falling edge of RESET in cases other than the above.
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Table 13-2. Initial Values after Reset of Each Register (2/2)
Register
Initial Value after Reset
Undefined
Undefined
80H
Real-time output function
Serial interface
Port 13 buffer register (PB)
Output latch register (RTP)
Asynchronous serial interface mode register (ASIM0)
Asynchronous serial interface mode register (ASIM1)
Asynchronous serial interface status register (ASIS)
Receive buffer (RXB, RXBL)
00H
00H
Undefined
Undefined
00H
Transmit shift register (TXS, TXSL)
Clocked serial interface mode register (CSIM0 to CSIM3)
Serial I/O shift register (SIO0 to SIO3)
Baud rate generator compare register (BRGC0 to BRGC3)
Baud rate generator prescaler mode register (BPRM0 to BPRM3)
IIC control register (IICC)
Undefined
Undefined
00H
00H
IIC status register (IICS)
00H
IIC clock selection register (IICCL)
00H
IIC shift register (IIC)
00H
Slave address register (SVA)
00H
PWM
PWM control register (PWMC0 to PWMC3)
PWM prescaler register (PWPR0 to PWPR3)
PWM modulo register (PWM0 to PWM3)
05H
00H
Undefined
47H
Interrupt/exception processing function Interrupt control register (xxICn)
In-service priority register (ISPR)
00H
External interrupt mode register (INTM0 to INTM7)
00H
Event divide counter (EDV0 to EDV2)
Event divide control register (EDVC0 to EDVC2)
Event selection register (EVS)
00H
01H
00H
Memory management function
Power save control
Data wait control register (DWC)
Bus cycle control register (BCC)
System control register (SYC)
FFFFH
AAAAH
00H/01H
Undefined
00H/C0H
00H
Command register (PRCMD)
Power save control register (PSC)
Clock control register (CKC)
Caution “Undefined” means an undefined value due to power-on reset or data corruption when a falling
edge of RESET coincides with a data write operation. The previous status of data is retained
by a falling edge of RESET in cases other than the above.
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y ONLY)
The µPD70F3008 and 70F3008Y of the V854 are provided with a 128-Kbyte flash memory. In the instruction fetch
to this flash memory, 4 bytes can be accessed by a single clock as well as the mask ROM version.
Writing to a flash memory can be performed with memory mounted on the target system (on board). The dedicated
flash writer is connected to the target system to perform writing.
The followings can be considered as the development environment and the applications using a flash memory.
Software can be altered after the V854 is solder mounted on the target system.
Small scale production of various models is made easier by differentiating software.
Data adjustment in starting mass production is made easier.
14.1 Features
• 4-byte/1-clock access (in instruction fetch access)
• All area one-shot erase
• Communication through serial interface from the dedicated flash writer
• Erase/writing voltage: VPP = 7.8 V
• On-board programming
• Number of rewrite: 100 times (target)
14.2 Writing by Flash Writer
Writing can be performed either on-board or off-board by the dedicated flash writer.
(1) On-board programming
The contents of the flash memory is rewritten after the V854 is mounted on the target system. Mount
connectors, etc., on the target system to connect the dedicated flash writer.
(2) Off-board programming
Writing to a flash memory is performed by the dedicated program adapter (FA Series Note), etc., before
mounting the V854 on the target system.
Note
FA Series program adapters are made by Naito Densei Machidaseisakusho Co., Ltd.
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y ONLY)
14.3 Programming Environment
The following shows the environment required for writing programs to the flash memory of the V854.
VPP
V
DD
SS
RS-232C
V
RESET
UART/CSI0
Dedicated flash writer
Host machine
V854
A host machine is required for controlling the dedicated flash writer.
UART or CSI is used as the interface between the dedicated flash writer and the V854 to perform writing, erasing,
etc. A dedicated program adapter (FA Series) is required for off-board writing.
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y
14.4 Communication System
The communication between the dedicated flash writer and the V854 is performed by serial communication using
UART or CSI0.
(1) UART
Transfer rate: 1200 to 76800 bps (LSB first)
VPP
V
DD
SS
V
RESET
TXD
Dedicated flash writer
V854
RXD
Clock
(2) CSI0
Transfer rate: up to 8.25 Mbps (MSB first)
VPP
VDD
VSS
RESET
SO0
Dedicated flash writer
V854
SI0
SCK0
Clock
The dedicated flash writer outputs the transfer clock, and the V854 operates as a slave.
When Flashpro II is used as the dedicated flash writer, it generates the following signals to the V854. For the details,
refer to the Flashpro II manual.
Remark Flashpro II is a product of Naitou Densei Machidaseisakusho Co., Ltd.
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y ONLY)
Measurement
FlashproII
I/O
V854
when connected
Signal Name
Pin Function
Writing voltage
Pin Name
CSIn
UART
VPP
VDD
Output
I/O
VPP
VDD
VDD voltage generation/
voltage monitoring
GND
–
Ground
VSS
CLK
Output
Output
Input
Clock output to V854
Reset signal
X1Note
RESET
SI/RXD
SO/TXD
SCK
RESET
SO0/TXD
SI0/RXD
SCK0
Receive signal
Transmit signal
Transfer clock
Output
Output
x
Note Only for off-board writing
Remark : Always connected
: Does not need to connect, if generated on the target board
x : Does not need to connect
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y
14.5 Pin Handling
When performing on-board writing, install a connector on the target system to connect to the dedicated flash writer.
Also, install the function on-board to switch from the normal operation mode to the flash memory programming mode.
When switched to the flash memory programming mode, all the pins not used for the flash memory programming
become the same status as that immediately after reset of single-chip mode 1. Therefore, all the ports become high-
impedance status, so that pin handling is required when the external device does not acknowledge the high-
impedance status.
14.5.1 VPP pin
In the normal operation mode, 0 V is input to VPP pin. In the flash memory programming mode, 7.8-V writing voltage
is supplied to VPP pin. The following shows an example of the connection of VPP pin.
V854
Dedicated flash writer connection pin
VPP
Pull-down resistor (RVPP
)
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y ONLY)
14.5.2 Serial interface pin
The following shows the pins used by each serial interface.
Serial Interface
Pins Used
SO0, SI0, SCK0
TXD, RXD
CSI0
UART
When connecting a dedicated flash writer to a serial interface pin which is connected to other devices on-board,
care should be taken to the conflict of signals and the malfunction of other devices, etc.
(1) Conflict of signals
When connecting a dedicated flash writer (output) to a serial interface pin (input) which is connected to another
device (output), conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other
device or set the other device to the high-impedance status.
V854
Conflict of signals
Dedicated flash writer connection pin
Input pin
The other device
Output pin
In the flash memory programming mode, the signal that the
dedicated flash writer sends out conflicts with signals the other
device outputs. Therefore, isolate the signals on the other
device side.
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y
(2) Malfunction of the other device
When connecting a dedicated flash writer (output or input) to a serial interface pin (input or output) connected
to another device (input), the signal output to the other device may cause the device to malfunction. To avoid
this, isolate the connection to the other device or make the setting so that the input signal to the other device
is ignored.
V854
Dedicated flash writer connection pin
Pin
The other device
Input pin
In the flash memory programming mode, if the
signal the V854 outputs affects the other device,
isolate the signal on the other device side.
V854
Dedicated flash writer connection pin
Pin
The other device
Input pin
In the flash memory programming mode, if the
signal the dedicated flash writer outputs affects the
other device, isolate the signal on the other device
side.
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y ONLY)
14.5.3 Reset pin
When connecting the reset signals of the dedicated flash writer to the RESET pin which is connected to the reset
signal generation circuit on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the connection
to the reset signal generation circuit.
When reset signal is input from the user system during the flash memory programming mode, programming
operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the
dedicated flash writer.
V854
Conflict of signals
Dedicated flash writer connection pin
RESET
Reset signal generation circuit
Output pin
In the flash memory programming mode, the
signal the reset signal generation circuit outputs
conflicts with the signal the dedicated flash writer
outputs. Therefore, isolate the signals on the
reset signal generation circuit side.
14.5.4 NMI pin
Do not change the input signal to the NMI pin during the flash memory programming mode. If the NMI pin is changed
during the flash memory programming mode, the programming may not be performed correctly.
14.5.5 Mode pin
To switch to the flash memory programming mode, change MODE0 through MODE2 to “111” with a jumper, etc.,
applies writing voltage to VPP pin, and release the reset.
14.5.6 Port pin
When the flash memory programming mode is set, all the port pins except the pins which communicate with the
dedicated flash writer become output high-impedance status. The treatment of these port pins are not necessary.
If problems such as disabling output high-impedance status should occurs to the external devices connected to the
port, connect them to VDD or VSS through resistors.
14.5.7 Other signal pin
Connect X1, X2, CKSEL, PLLSEL, and AVREF to the same status as that in the normal operation mode.
14.5.8 Power supply
Supply the same power supplies (VDD, VSS, AVDD, AVSS, CVDD, CVSS) as those in the normal operation mode.
Connect VDD and GND of the dedicated flash writer to VDD and VSS. (The VDD dedicated flash writer is provided with
a power supply monitoring function.)
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y
14.6 Programming Method
14.6.1 Flash memory control
The following shows the procedure that this firmware manipulates the flash memory.
Starts
Switches to flash memory programming mode
Selects communication system
Manipulates flash memory
Supplies RESET pulse
No
Ends ?
Yes
Ends
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y ONLY)
14.6.2 Flash memory programming mode
When rewriting the contents of a flash memory using the dedicated flash writer, set the V854 in the flash memory
programming mode. When switching to modes, set MODE0 through MODE2 and VPP pin before releasing reset.
When performing on-board writing, change modes using a jumper, etc.
VPP
MODE2 MODE1 MODE0
Operation Mode
Normal operation mode ROM-less mode 1
0 V
0 V
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
ROM-less mode 2
Single-chip mode 1
Single-chip mode 2
0 V
0 V
7.8 V
Flash memory programming mode
Setting prohibited
Other than the above
Flash memory programming mode
MODE0 to MODE2
7.8 V
“xx0”
“111”
1
2
· · ·
n
VPP 3V
0 V
RESET
14.6.3 Selection of communication mode
In the V854, a communication system is selected by inputting pulse (16 pulses max.) to VPP pin after switching
to the flash memory programming mode. The VPP pulse is generated by the dedicated flash writer.
The following shows the relation between the number of pulses and the communication systems.
Table 14-1. List of Communication Systems
VPP pulse
Communication System
Remarks
0
8
CSI0
UART
RFU
V854 performs slave operation, MSB first
Communication rate: 9600 bps (at reset), LSB first
Setting prohibited
Others
Caution
When UART is selected, the receive clock is calculated based on the reset command sent
from the dedicated flash writer after receiving VPP pulse.
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CHAPTER 14 FLASH MEMORY (µPD70F3008 AND 70F3008Y
14.6.4 Communication command
The V854 communicates with the dedicated flash writer by means of commands. The command sent from the
dedicated flash writer to the V854 is called a “command”. The response signal sent from the V854 to the dedicated
flash writer is called a “response command”.
Command
Response command
Dedicated flash writer
V854
The following shows the command for flash memory control of the V854. All of these commands are issued from
the dedicated flash writer, and the V854 performs the various processings corresponding to the commands.
Category
Command Name
Function
Verify
Erase
One-shot verify command
Compares the contents of the entire memory
and the input data.
One-shot erase command
One-shot blank check command
High-speed write command
Erases the contents of the entire memory.
Checks the erase state of the entire memory.
Blank check
Data write
Writes data by the specification of the write
address and the number of bytes to be written,
and executes verify check.
Continuous write command
Writes data from the address following the high-
speed write command executed immediately
before, and executes verify check.
System setting and control
Status read out command
Acquires the status of operations.
Sets the oscillating frequency.
Oscillating frequency setting command
Erasing time setting command
Sets the erasing time of one-shot erase.
Writing time setting command
Baud rate setting command
Silicon signature command
Reset command
Sets the writing time of data write.
Sets the baud rate when using UART.
Reads outs the silicon signature information.
Escapes from each state.
The V854 sends back response commands to the commands issued from the dedicated flash writer. The following
shows the response commands the V854 sends out.
Response Command Name
ACK (acknowledge)
Function
Acknowledges command/data, etc.
Acknowledges illegal command/data, etc.
NAK (not acknowledge)
14.6.5 Resources used
According to the flash memory programming mode setting, the resources used consist of the area from FFE000H
to FFE7FFH of the internal RAM and all the registers. Area FFE800H to FFEFFFH of the internal RAM retains data
as long as the power is on. The contents of the registers that are initialized by reset change to the default value.
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CHAPTER 15 DIFFERENCES BETWEEN VERSIONS
15.1 Differences between Versions with I2C Function and Versions without I2C Function
The product names of the versions with the I2C function are µPD703008Y and 70F3008Y. They are identified by
the letter “Y” in the product names.
Product Name
µPD703008Y, 70F3008Y
µPD703006, 703008, 70F3008
Function
I2C function
Available
Not available
Pin
P33/SO1/SDA
P35/SCK1/SCL
P33/SO1
P35/SCK1
Interrupt
INTIIC
Not available
Register IIIC0
Available
Not available (undefined)
IICC
IICS
IICCL
IIC
SAV
15.2 Differences between On-chip Flash Memory Versions, On-chip Mask ROM Versions, and ROM-
less Versions
The product names of the versions with the on-chip flash memory are µPD70F3008 and 70F3008Y. They are
identified by the letter “F” in the product names.
Part Number
µPD703006
µPD703008, 703008Y
µPD70F3008, 70F3008Y
Parameter
On-chip ROM
None
Mask ROM
Flash memory
Flash memory programming pin
Flash memory programming mode
None
None
Provided (VPP)
Provided (VPP = 7.8 V,
MODE0 to MODE2 = High-level)
Electrical specifications
Others
Current consumption, etc. differ. (Refer to each product data sheet.)
Noise immunity and noise radiation differ for each product depending on the
circuit size and mask layout.
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory
version, mask ROM version, and ROM-less version. When pre-producing an application set
with the flash memory version and then mass-producing it with the mask ROM version, be
sure to conduct sufficient evaluations for the set using consumer samples (not engineering
samples) of the mask ROM version.
2. When replacing the flash memory version with the mask ROM version, be sure to write the
same code into the internal ROM’s reserved area.
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APPENDIX A REGISTER INDEX
(1/6)
Symbol
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ADIC0
ADM0
Name
Unit
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
INTC
ADC
ADC
UART
UART
UART
BCU
BRG
BRG
BRG
BRG
BRG
BRG
BRG
BRG
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
INTC
INTC
INTC
INTC
RPU
CG
Page
299
299
299
299
299
299
299
299
116
297
299
209
211
212
88
A/D conversion result register 0
A/D conversion result register 1
A/D conversion result register 2
A/D conversion result register 3
A/D conversion result register 4
A/D conversion result register 5
A/D conversion result register 6
A/D conversion result register 7
Interrupt control register
A/D converter mode register 0
A/D converter mode register 1
Asynchronous serial interface mode register 0
Asynchronous serial interface mode register 1
Asynchronous serial interface status register 1
Bus cycle control register
ADM1
ASIM0
ASIM1
ASIS
BCC
BPRM0
BPRM1
BPRM2
BPRM3
BRGC0
BRGC1
BRGC2
BRGC3
CC00
Baud rate generator prescaler mode register 0
Baud rate generator prescaler mode register 1
Baud rate generator prescaler mode register 2
Baud rate generator prescaler mode register 3
Baud rate generator compare register 0
Baud rate generator compare register 1
Baud rate generator compare register 2
Baud rate generator compare register 3
Capture/compare register 00
292
292
292
292
291
291
291
291
161
161
161
161
161
161
161
161
116
116
116
116
165
137
154
CC00L
CC01
Capture/compare register 00L
Capture/compare register 01
CC01L
CC02
Capture/compare register 01L
Capture/compare register 02
CC02L
CC03
Capture/compare register 02L
Capture/compare register 03
CC03L
CC0IC0
CC0IC1
CC0IC2
CC0IC3
CC3
Capture/compare register 03L
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Capture/compare register 3
CKC
Clock control register
CLOM
Clock output mode register
CG
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APPENDIX A REGISTER INDEX
(2/6)
Symbol
CM10
Name
Unit
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
INTC
INTC
INTC
INTC
CSI
Page
Compare register 10
Compare register 10L
Compare register 11
Compare register 11L
Compare register 20
Compare register 21
Compare register 22
Compare register 23
Compare register 24
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Capture register 10
163
163
163
163
164
164
164
164
164
116
116
116
116
116
116
116
116
162
162
162
162
162
162
162
162
165
116
116
116
116
222
222
222
222
86
CM10L
CM11
CM11L
CM20
CM21
CM22
CM23
CM24
CM1IC0
CM1IC1
CM2IC0
CM2IC1
CM2IC2
CM2IC3
CM2IC4
CC3IC0
CP10
CP10L
CP11
Capture register 10L
Capture register 11
CP11L
CP12
Capture register 11L
Capture register 12
CP12L
CP13
Capture register 12L
Capture register 13
CP13L
CP3
Capture register 13L
Capture register 3
CSIC0
CSIC1
CSIC2
CSIC3
CSIM0
CSIM1
CSIM2
CSIM3
DWC
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Clocked serial interface mode register 0
Clocked serial interface mode register 1
Clocked serial interface mode register 2
Clocked serial interface mode register 3
Data wait control register
CSI
CSI
CSI
BCU
CPU
INTC
INTC
INTC
INTC
ECR
Interrupt source register
52
EDVC0
EDVC1
EDVC2
EDV0
Event divide control register 0
Event divide control register 1
Event divide control register 2
Event divide counter 0
125
125
125
125
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APPENDIX A REGISTER INDEX
(3/6)
Symbol
EDV1
Name
Unit
INTC
INTC
CPU
CPU
INTC
CPU
CPU
I2C
Page
Event divide counter 1
Event divide counter 2
Interrupt status save register
Interrupt status save register
Event selection register
NMI status save register
NMI status save register
IIC control register
125
125
52
EDV2
EIPC
EIPSW
EVS
FEPC
FEPSW
IICC
IICCL
IICS
IIC
52
125
52
52
237
241
239
241
242
116
106
121
121
121
121
121
121
123
118
68
IIC clock selection register
IIC status register
I2C
I2C
IIC shift register
I2C
SVA
IIIC0
INTM0
INTM1
INTM2
INTM3
INTM4
INTM5
INTM6
INTM7
ISPR
MM
Slave address register
Interrupt control register
I2C
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
Port
INTC
INTC
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
External interrupt mode register 0
External interrupt mode register 1
External interrupt mode register 2
External interrupt mode register 3
External interrupt mode register 4
External interrupt mode register 5
External interrupt mode register 6
External interrupt mode register 7
In-service priority register
Memory expansion mode register
OVIC0
OVIC1
P0
Interrupt control register
116
116
348
350
352
354
357
359
361
363
363
364
366
368
371
373
375
Interrupt control register
Port 0
P1
Port 1
P2
Port 2
P3
Port 3
P4
Port 4
P5
Port 5
P6
Port 6
P7
Port 7
P8
Port 8
P9
Port 9
P10
Port 10
Port 11
Port 12
Port 13
Port 14
P11
P12
P13
P14
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APPENDIX A REGISTER INDEX
(4/6)
Symbol
P1IC0
P1IC1
P1IC2
P1IC3
P5IC0
P5IC1
P5IC2
P5IC3
PB
Name
Unit
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
Port
Page
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Port 13 buffer register
Port 0 mode register
116
116
116
116
116
116
116
116
322
349
351
353
355
358
360
362
365
367
369
371
374
375
349
351
353
356
367
370
372
374
78
PM0
Port
PM1
Port 1 mode register
Port
PM2
Port 2 mode register
Port
PM3
Port 3 mode register
Port
PM4
Port 4 mode register
Port
PM5
Port 5 mode register
Port
PM6
Port 6 mode register
Port
PM9
Port 9 mode register
Port
PM10
PM11
PM12
PM13
PM14
PMC0
PMC1
PMC2
PMC3
PMC10
PMC11
PMC12
PMC13
PRCMD
PSC
Port 10 mode register
Port 11 mode register
Port 12 mode register
Port 13 mode register
Port 14 mode register
Port 0 mode control register
Port 1 mode control register
Port 2 mode control register
Port 3 mode control register
Port 10 mode control register
Port 11 mode control register
Port 12 mode control register
Port 13 mode control register
Command register
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
CG
Power save control register
Program status word
CG
142
52, 106, 118, 128
329
329
329
329
327
327
327
PSW
CPU
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM0
PWM1
PWM2
PWM3
PWMC0
PWMC1
PWMC2
PWM modulo register 0 (12 bits)
PWM modulo register 1 (12 bits)
PWM modulo register 2
PWM modulo register 3
PWM control register 0
PWM control register 1
PWM control register 2
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APPENDIX A REGISTER INDEX
(5/6)
Symbol
PWMC3
PWPR0
PWPR1
PWPR2
PWPR3
RTP
Name
Unit
PWM
PWM
PWM
PWM
PWM
RPU
UART
UART
INTC
CSI
Page
PWM control register 3
PWM prescaler register 0
PWM prescaler register 1
PWM prescaler register 2
PWM prescaler register 3
Output latch register
Receive buffer (9 bits)
Receive buffer L (lower 8 bits)
Interrupt control register
Serial I/O shift register 0
Serial I/O shift register 1
Serial I/O shift register 2
Serial I/O shift register 3
Interrupt control register
Interrupt control register
I2C slave address register
System control register
System status register
Timer 0
327
328
328
328
328
322
213
213
116
223
223
223
223
116
116
242
82
RXB
RXBL
SEIC0
SIO0
SIO1
CSI
SIO2
CSI
SIO3
CSI
SRIC0
STIC0
SVA
INTC
INTC
I2C
SYC
BCU
CG
SYS
79, 139
161
161
162
162
164
164
164
164
164
165
166
167
168
169
170
170
170
170
170
171
172
172
TM0
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
TM0L
TM1
Timer 0L
Timer 1
TM1L
TM20
TM21
TM22
TM23
TM24
TM3
Timer 1L
Timer 20
Timer 21
Timer 22
Timer 23
Timer 24
Timer 3
TMC00
TMC01
TMC02
TMC1
TMC20
TMC21
TMC22
TMC23
TMC24
TMC3
TOC0
TOC1
Timer control register 00
Timer control register 01
Timer control register 02
Timer control register 1
Timer control register 20
Timer control register 21
Timer control register 22
Timer control register 23
Timer control register 24
Timer control register 3
Timer output control register 0
Timer output control register 1
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APPENDIX A REGISTER INDEX
(6/6)
Symbol
TOVS
TXS
Name
Unit
RPU
Page
Timer overflow status register
Transmit shift register (9 bits)
173
214
214
UART
UART
TXSL
Transmit shift register L (lower 8 bits)
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APPENDIX B INSTRUCTION SET LIST
Legend
(1) Symbols used for operand description
Symbol
Description
reg1
reg2
immx
dispx
reglD
bit#3
ep
General register (r0 to r31): Used as source register
General register (r0 to r31): Mainly used as destination register
x-bit immediate
x-bit displacement
System register number
3-bit data for bit number specification
Element pointer (r30)
cccc
vector
4-bit data for condition code
5-bit data for trap vector number (00H to 1FH)
(2) Symbols used for operation description
Symbol
Description
←
Assignment
GR[ ]
General register
SR[ ]
System register
zero-extend(n)
sign-extend(n)
load-memory(a,b)
store-memory(a,b,c)
load-memory-bit(a,b)
store-memory-bit(a,b,c)
saturated(n)
Zero-extends n to word length
Sign-extends n to word length
Reads data of size b from address a
Writes data b of size c to address a
Reads bit b of address a
Writes c to bit b of address a
Performs saturated processing of n (n is 2’s complement).
If n is n ≥ 7FFFFFFFH as result of calculation, 7FFFFFFFH.
If n is n ≤ 80000000H as result of calculation, 80000000H.
result
Reflects result on flag
Byte (8 bits)
Half-word (16 bits)
Word (32 bits)
Add
Byte
Halfword
Word
+
–
Subtract
||
Bit concatenation
Multiply
x
÷
Divide
AND
OR
Logical product
Logical sum
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APPENDIX B INSTRUCTION SET LIST
Symbol
Description
XOR
NOT
Exclusive logical sum
Logical negate
logically shift left by
Logical left shift
logically shift right by
arithmetically shift right by
Logical right shift
Arithmetic right shift
(3) Symbols used for execution clock description
Symbol
Description
i : issue
To execute another instruction immediately after instruction execution
To execute same instruction immediately after instruction execution
To reference result of instruction execution by the next instruction
r: repeat
l : latency
(4) Flag operation
Identifier
Description
(Blank)
Not affected
Cleared to 0
Set to 1
0
1
x
Set or cleared according to result
Previously saved value is restored
R
Condition code
Condition
Condition Name
(cond)
Conditional Expression
OV = 1
Description
Code (cccc)
V
0 0 0 0
1 0 0 0
0 0 0 1
Overflow
NV
C/L
OV = 0
CY = 1
No overflow
Carry
Lower (Less than)
NC/NL
Z/E
1 0 0 1
0 0 1 0
1 0 1 0
CY = 0
Z = 1
No carry
No lower (Greater than or equal)
Zero
Equal
NZ/NE
Z = 0
Not zero
Not equal
NH
H
0 0 1 1
1 0 1 1
0 1 0 0
1 1 0 0
0 1 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 1 1 1
1 1 1 1
(CY or Z) = 1
(CY or Z) = 0
S = 1
Not higher (Less than or equal)
Higher (Greater than)
Negative
N
P
S = 0
Positive
T
—
Always (unconditional)
Saturated
SA
LT
GE
LE
GT
SAT = 1
(S xor OV) = 1
(S xor OV) = 0
((S xor OV) or Z) = 1
((S xor OV) or Z) = 0
Less than signed
Greater than or equal signed
Less than or equal signed
Greater than signed
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APPENDIX B INSTRUCTION SET LIST
Instruction Set (alphabetical order) (1/4)
Execution
Clock
Flag
Operand
Code
Operation
Mnemonic
ADD
i
r
l
CY OV
S
x
Z
x
SAT
reg1, reg2
GR[reg2]←GR[reg2]+GR[reg1]
1
1
1
x
x
x
x
x
x
r r r r r 001110RRRRR
r r r r r 010010 i i i i i
r r r r r 110000RRRRR
i i i i i i i i i i i i i i i i
r r r r r 001010RRRRR
r r r r r 110110RRRRR
i i i i i i i i i i i i i i i i
imm5, reg2
GR[reg2]←GR[reg2]+sign-extend(imm5)
GR[reg2]←GR[reg1]+sign-extend(imm16)
1
1
1
1
1
1
x
x
x
x
ADDI
imm16, reg1, reg2
AND
reg1, reg2
GR[reg2]←GR[reg2]AND GR[reg1]
1
1
1
1
1
1
0
0
x
x
x
ANDI
imm16, reg1, reg2
GR[reg2]←GR[reg1]AND zero-extend(imm16)
0
When condition
satisfied
Bcond
CLR1
disp9
ddddd1011ddd c c c c if conditions are satisfied
3
3
3
When condition
not satisfied
Note 1 then PC←PC+sign-extned(disp9)
1
4
1
4
1
4
bit#3, disp16[reg1]
adr←GR[reg1]+sign-extend(disp16)
x
10bbb111110RRRRR
dddddddddddddddd
Z flag←Not(Load-memory-bit(adr, bit#3))
Store-memory-bit(adr, bit#3.0)
CMP
reg1, reg2
imm5, reg2
result←GR[reg2]–GR[reg1]
1
1
1
1
1
1
1
1
1
x
x
x
x
x
x
x
x
r r r r r 001111RRRRR
r r r r r 010011 i i i i i
0000011111100000
0000000101100000
r r r r r 000010RRRRR
result←GR[reg2]–sign-extend(imm5)
PSW.ID←1
DI
(Maskable interrupt disabled)
GR [reg2]←GR [reg2]÷GR [reg1]Note 2
(signed division)
DIVH
EI
reg1, reg2
36 36 36
x
x
x
PSW.ID←0
1
1
3
1
1
3
1
1
3
1000011111100000
0000000101100000
0000011111100000
0000000100100000
r r r r r 11110dddddd
ddddddddddddddd0
Note 3
(Maskable interrupt enabled)
Stops
HALT
JARL
disp22, reg2
GR[reg2]←PC+4
PC←PC+sign-extend(disp22)
JMP
JR
[reg1]
PC←GR[reg1]
3
3
3
3
3
3
00000000011RRRRR
0000011110dddddd
ddddddddddddddd0
Note 3
disp22
PC←PC+sign-extend(disp22)
LD.B
LD.H
disp16[reg1], reg2
disp16[reg1], reg2
adr←GR[reg1]+sign-extend(disp16)
1
1
1
1
2
2
r r r r r 111000RRRRR
dddddddddddddddd
r r r r r 111001RRRRR
ddddddddddddddd0
Note 4
GR[reg2]←sign-extend(Load-memory(adr, Byte))
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]sign-extend(Load-memory(adr, Halfword))
LD.W
disp16[reg1], reg2
adr←GR[reg1]+sign-extend(disp16)
GR[reg2]←Load-memory(adr, Word)
1
1
2
r r r r r 111001RRRRR
ddddddddddddddd1
Note 4
Notes 1. dddddddd is the higher 8 bits of disp9.
2. Only the lower half-word is valid.
3. ddddddddddddddddddddd is the higher 21 bits of disp22.
4. ddddddddddddddd is the higher 15 bits of disp16.
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APPENDIX B INSTRUCTION SET LIST
Instruction Set (alphabetical order) (2/4)
Execution
Clock
Flag
S
Mnemonic
LDSR
Operand
Code
Operation
i
r
l
CY OV
Z
x
SAT
x
r r r r r 111111RRRRR
0000000000100000
Note 1
reg2, regID
SR[regID]←GR[reg2]
regID = EIPC, FEPC
1
1
3
1
1
1
1
1
regID = EIPSW, FEPSW
regID = PSW
x
x
x
r r r r r 000000RRRRR
r r r r r 010000 i i i i i
r r r r r 110001RRRRR
i i i i i i i i i i i i i i i i
r r r r r 110010RRRRR
i i i i i i i i i i i i i i i i
r r r r r 000111RRRRR
MOV
reg1, reg2
GR[reg2]←GR[reg1]
1
1
1
1
1
1
imm5, reg2
GR[reg2]←sign-extend(imm5)
MOVEA
MOVHI
MULH
imm16, reg1, reg2
GR[reg2]←GR[reg1]+sign-extend(imm16)
imm16, reg1, reg2
reg1, reg2
GR[reg2]←GR[reg1]+(imm16 || 016
)
1
1
1
1
1
1
1
1
1
2
2
2
GR[reg2]←GR[reg2]Note 2 xGR[reg1]Note 2
(Signed multiplication)
GR[reg2]←GR[reg2]Note 2 xsign-extend(imm5)
(Signed multiplication)
GR[reg2]←GR[reg1]Note 2 ximm16
r r r r r 010111 i i i i i
imm5, reg2
r r r r r 110111RRRRR
i i i i i i i i i i i i i i i i
0000000000000000
r r r r r 000001RRRRR
01bbb111110RRRRR
dddddddddddddddd
MULHI
imm16, reg1, reg2
(Signed multiplication)
NOP
NOT
NOT1
Uses 1 clock cycle without doing anything
GR[reg2]←NOT(GR[reg1])
1
1
4
1
1
4
1
1
4
reg1, reg2
0
x
x
x
bit#3, disp16[reg1]
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not(Load-memory-bit(adr, bit#3))
Store-memory-bit(adr, bit#3, Z flag)
GR[reg2]←GR[reg2]OR GR[reg1]
r r r r r 001000RRRRR
r r r r r 110100RRRRR
i i i i i i i i i i i i i i i i
0000011111100000
0000000101000000
OR
reg1, reg2
1
1
1
1
1
1
0
0
x
x
x
x
ORI
imm16, reg1, reg2
GR[reg2]←GR[reg1]OR zero-extend(imm16)
RETI
if PSW.EP=1
4
4
4
R
R
R
R
R
then PC ←EIPC
PSW ←EIPSW
else if PSW.NP=1
then PC ←FEPC
PSW ←FEPSW
else PC ←EIPC
PSW ←EIPSW
SAR
reg1, reg2
imm5, reg2
GR[reg2]←GR[reg2]arithmetically shift right
1
1
1
1
1
1
x
x
0
0
x
x
x
x
r r r r r 111111RRRRR
0000000010100000
r r r r r 010101 i i i i i
by GR[reg1]
GR[reg2]←GR[reg2]arithmetically shift right
by zero-extend(imm5)
Notes 1. The op code of this instruction uses the field of reg1 though the source register is shown as reg2 in
the above table. Therefore, the meaning of register specification for mnemonic description and op code
is different from that of the other instructions.
rrrrr = regID specification
RRRRR = reg2 specification
2. Only the lower half-word data is valid.
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APPENDIX B INSTRUCTION SET LIST
Instruction Set (alphabetical order) (3/4)
Execution
Clock
Flag
Mnemonic
Operand
Code
Operation
i
r
l
CY OV
S
x
x
x
x
Z
x
x
x
x
SAT
x
SATADD reg1, reg2
imm5, reg2
r r r r r 000110RRRRR GR[reg2]←saturated(GR[reg2]+GR[reg1])
1
1
1
1
1
1
1
1
1
1
1
1
x
x
x
x
x
x
x
x
r r r r r 010001 i i i i i GR[reg2]←saturated(GR[reg2]+sign-extend(imm5))
x
r r r r r 000101RRRRR
SATSUB reg1, reg2
SATSUBI imm16, reg1, reg2
GR[reg2]←saturated(GR[reg2]–GR[reg1])
x
r r r r r 110011RRRRR GR[reg2]←saturated(GR[reg1]–sign-extend(imm16))
x
i i i i i i i i i i i i i i i i
r r r r r 000100RRRRR
SATSUBR reg1, reg2
GR[reg2]←saturated(GR[reg1]–GR[reg2])
1
1
1
1
1
1
x
x
x
x
x
SETF
SET1
SHL
cccc, reg2
r r r r r 1111110 c c c c if conditions are satisfied
0000000000000000 then GR[reg2]←00000001H
else GR[reg2]←00000000H
bit#3, disp16[reg1]
00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd Z flag←Not(Load-memory-bit(adr, bit#3))
Store-memory-bit(adr, bit#3, 1)
4
4
4
x
reg1, reg2
r r r r r 111111RRRRR GR[reg2]←GR[reg2] logically shift left by GR[reg1]
0000000011000000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
x
x
x
x
0
0
0
0
x
x
x
x
x
x
x
x
r r r r r 010110 i i i i i
imm5, reg2
GR[reg2]←GR[reg1] logically shift left by
zero-extend(imm5)
SHR
reg1, reg2
r r r r r 111111RRRRR GR[reg2]←GR[reg2] logically shift right by GR[reg1]
0000000010000000
imm5, reg2
r r r r r 010100 i i i i i GR[reg2]←GR[reg2] logically shift right by
zero-extend(imm5)
r r r r r 0110ddddddd
SLD.B
SLD.H
SLD.W
SST.B
SST.H
SST.W
ST.B
disp7[ep], reg2
disp8[ep], reg2
disp8[ep], reg2
reg2, disp7[ep]
reg2, disp8[ep]
reg2, disp8[ep]
reg2, disp16[reg1]
adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr, Byte))
r r r r r 1000ddddddd adr←ep+zero-extend(disp8)
Note 1
GR[reg2]←sign-extend(Load-memory(adr, Halfword))
r r r r r 1010dddddd0 adr←ep+zero-extend(disp8)
Note 2 GR[reg2]←Load-memory(adr, Word)
r r r r r 0111ddddddd
adr←ep+zero-extend(disp7)
Store-memory(adr, GR[reg2], Byte)
r r r r r 1001ddddddd adr←ep+zero-extend(disp8)
Note 1
Store-memory(adr, GR[reg2], Halfword)
r r r r r 1010dddddd1 adr←ep+zero-extend(disp8)
Note 2 Store-memory(adr, GR[reg2], Word)
r r r r r 111010RRRRR
adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd Store-memory(adr, GR[reg2], Byte)
Notes 1. ddddddd is the higher 7 bits of disp8.
2. dddddd is the higher 6 bits of disp8.
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APPENDIX B INSTRUCTION SET LIST
Instruction Set (alphabetical order) (4/4)
Execution
Clock
Flag
S
Mnemonic
ST.H
Operand
Code
Operation
i
r
l
CY OV
Z
SAT
r r r r r 111011RRRRR
ddddddddddddddd0
Note
reg2, disp16[reg1]
adr←GR[reg1]+sign-extend(disp16)
1
1
1
Store-memory(adr, GR[reg2], Halfword)
r r r r r 111011RRRRR
ddddddddddddddd1
Note
ST.W
STSR
reg2, disp16[reg1]
regID, reg2
adr←GR[reg1]+sign-extend(disp16)
1
1
1
1
1
1
Store-memory(adr, GR[reg2], Word)
r r r r r 111111RRRRR
0000000001000000
r r r r r 001101RRRRR
r r r r r 001100RRRRR
00000111111 i i i i i
0000000100000000
GR[reg2]←SR[regID]
SUB
reg1, reg2
reg1, reg2
vector
GR[reg2]←GR[reg2]–GR[reg1]
GR[reg2]←GR[reg1]–GR[reg2]
1
1
4
1
1
4
1
1
4
x
x
x
x
x
x
x
x
SUBR
TRAP
EIPC
←PC+4(Restored PC)
←PSW
EIPSW
ECR.EICC ←Interrupt code
PSW.EP ←1
PSW.ID
PC
←1
←00000040H(vector = 00H to 0FH)
00000050H(vector = 10H to 1FH)
r r r r r 001011RRRRR
11bbb111110RRRRR
dddddddddddddddd
r r r r r 001001RRRRR
r r r r r 110101RRRRR
i i i i i i i i i i i i i i i i
TST
reg1, reg2
result←GR[reg2] AND GR[reg1]
1
3
1
3
1
3
0
x
x
x
TST1
bit#3, disp16[reg1]
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not(Load-memory-bit(adr, bit#3))
GR[reg2]←GR[reg2] XOR GR[reg1]
GR[reg2]←GR[reg1] XOR zero-extend(imm16)
XOR
reg1, reg2
1
1
1
1
1
1
0
0
x
x
x
x
XORI
imm16, reg1, reg2
Note ddddddddddddddd is the higher 15 bits of disp16.
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APPENDIX C INDEX
[0]
baud rate generator
1-bit output port .................................................... 154
144-pin plastic LQFP .............................................. 25
compare register 0 to 3 ........................................ 291
baud rate generator
prescaler mode register 0 to 3.............................292
baud rate generators 0 to 3 set-up values .......... 289
BCC ......................................................................... 88
BCn1 (n = 0 to 7).................................................... 88
BCU ......................................................................... 29
BIC .......................................................................... 82
block diagram of ports.......................................... 342
BPRM0 to BPRM3 ................................................ 292
BPRn0 to BPRn3 (n = 0 to 3) .............................. 292
BRCE0 to BRCE3.................................................292
BRGC0 to BRGC3 ................................................ 291
BRGn0 to BRGn7 (n = 0 to 3) .............................291
BS ..........................................................................297
buffer register........................................................ 322
bus access .............................................................. 83
bus control function ................................................ 81
bus control pin ........................................................ 82
bus control unit ....................................................... 29
bus cycle control register ....................................... 88
bus hold ........................................................... 89, 96
bus priority .............................................................. 97
bus timing................................................................ 90
bus width ................................................................. 84
byte access ............................................................. 84
[A]
A/D conversion result register ............................. 299
A/D converter ........................................................ 295
A/D converter mode register 0............................. 297
A/D converter mode register 1............................. 299
A/D trigger mode ......................................... 302, 308
A16 to A23 .............................................................. 40
ACKD .................................................................... 240
ACKE.....................................................................238
AD0 to AD7 ............................................................. 39
AD8 to AD15 ........................................................... 40
ADCR0 to ADCR7 ................................................ 299
address space ................................................. 56, 69
ADIC0 .................................................................... 116
ADIF0 .................................................................... 116
ADM0 .................................................................... 297
ADM1 .................................................................... 299
ADMK0 .................................................................. 116
ADPR00 to ADPR02............................................. 116
ADTRG .................................................................... 38
ALD ....................................................................... 239
ALVn (n = 00, 01, 20 to 24) ................................. 172
ANI0 to ANI15......................................................... 40
ANIS0 to ANIS2 .................................................... 297
application fields ..................................................... 25
arbitration .............................................................. 239
ASIM0, ASIM1 ...................................................... 209
ASIS ...................................................................... 212
assembler reservation register .............................. 51
ASTB ....................................................................... 41
asynchronous serial interface .............................. 206
asynchronous serial interface
[C]
capture operation (timer 0) .................................. 179
capture operation (timer 1) .................................. 186
capture operation (timer 3) .................................. 193
capture register 10 to 13 ...................................... 162
capture register 3 .................................................165
capture/compare register 00 to 03 ......................161
capture/compare register 3 .................................. 165
CC00 to CC03, CC00L to CC03L........................ 161
CC0IC0 to CC0IC3 ............................................... 116
CC0IF0 to CC0IF3................................................ 116
CC0MK0 to CC0MK3 ........................................... 116
CC0PRn0 to CC0PRn2 (n = 0 to 3) .................... 116
CC3 ....................................................................... 165
CC3IC0.................................................................. 116
CC3IF0 .................................................................. 116
CC3MK0 ................................................................ 116
mode register 0, 1 ................................................ 209
asynchronous serial interface
status register ....................................................... 212
AVDD ........................................................................ 45
AVREF ....................................................................... 46
AVSS ........................................................................ 45
[B]
baud rate generator 0 to 3 ................................... 286
User’s Manual U11969EJ3V0UM00
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APPENDIX C INDEX
CC3PR00 to CC3PR02 ........................................ 116
communication command .................................... 393
communication reservation .................................. 273
compare operation (timer 0) ................................ 181
compare operation (timer 1) ................................ 187
compare operation (timer 2) ................................ 189
compare operation (timer 3) ................................ 194
compare register 10, 11 ....................................... 163
compare register 20 to 24 .................................... 164
conflict of signals .................................................. 388
count clock selection (timer 0) .............................175
count clock selection (timer 1) .............................183
count clock selection (timer 2) .............................188
count clock selection (timer 3) .............................192
count operation (timer 0) ...................................... 174
count operation (timer 1) ...................................... 183
count operation (timer 2) ...................................... 188
count operation (timer 3) ...................................... 192
CP10 to CP13, CP10L to CP13L ........................ 162
CP3 ....................................................................... 165
CPU ......................................................................... 29
CPU address space ........................................ 56, 58
CPU function........................................................... 49
CPU register set ..................................................... 50
CRXE0 to CRXE3.................................................222
CS..........................................................................297
CS1 ....................................................................... 169
CS20 to CS24 .......................................................170
CS3 ....................................................................... 171
CSI0 to CSI3......................................................... 220
CSIC0 to CSIC3 ................................................... 116
CSIF0 to CSIF3 .................................................... 116
CSIM0 to CSIM3................................................... 222
CSMK0 to CSMK3 ................................................ 116
CSOT0 to CSOT3.................................................222
CSPRn0 to CSPRn2 (n = 0 to 3)......................... 116
CTXE0 to CTXE3 .................................................222
CVDD ........................................................................ 45
CVSS ........................................................................ 45
CY............................................................................ 53
CCLR0................................................................... 168
CE.......................................................................... 297
CE0 ....................................................................... 166
CE1 ....................................................................... 169
CE20 to CE24 ....................................................... 170
CE3 ....................................................................... 171
CESEL................................................................... 142
CG ........................................................................... 29
CKC ....................................................................... 137
CKDIV0 to CKDIV1............................................... 137
CKSEL..................................................................... 44
CL .......................................................................... 210
CL0, CL1 ............................................................... 241
CLD ....................................................................... 241
CLE ....................................................................... 154
clear/start of timer (timer 0) ................................. 177
clear/start of timer (timer 1) ................................. 185
clear/start of timer (timer 2) ................................. 189
clear/start of timer (timer 3) ................................. 193
CLKOUT .................................................................. 44
CLKOUT signal output control ............................. 152
CLO ......................................................................... 43
CLO signal output control .................................... 153
clock control register ............................................ 137
clock generation function ..................................... 135
clock generator ....................................................... 29
clock output control .............................................. 165
clock output inhibit ....................................... 140, 152
clock output mode register................................... 154
clock serial interface 0 to 3 .................................. 220
clock serial interface mode register 0 to 3 .......... 222
CLOM .................................................................... 154
CLSn0, CLSn1 (n = 0 to 3) .................................. 223
CM10, CM11, CM10L, CM11L............................. 163
CM1IC0, CM1IC1 ................................................. 116
CM1IF0, CM1IF1 .................................................. 116
CM1MK0, CM1MK1 .............................................. 116
CM1PRn0 to CM1PRn2 (n = 0, 1)....................... 116
CM20 to CM24...................................................... 164
CM2IC0 to CM2IC4 .............................................. 116 [D]
CM2IF0 to CM2IF4 ............................................... 116
CM2MK0 to CM2MK4........................................... 116
CM2PRn0 to CM2PRn2 (n = 0 to 4) ................... 116
CMS00 to CMS03................................................. 167
CMS3 .................................................................... 171
COI ........................................................................ 239
command register ................................................... 78
DAD ....................................................................... 241
data space ................................................. 58, 69, 97
data wait control register........................................ 86
DCLK0, DCLK1..................................................... 142
DFC ....................................................................... 241
diagram of processing status ............................... 141
direct mode ........................................................... 136
410
User’s Manual U11969EJ3V0UM00
APPENDIX C INDEX
DSTB ....................................................................... 41
flash memory programming mode ................ 54, 392
FR0 to FR2 ........................................................... 299
frequency divider .................................................. 124
FS0 to FS2............................................................ 154
function block configuration ................................... 28
DWC ........................................................................ 86
DWn0, DWn1 (n = 0 to 7) ...................................... 86
[E]
EBS ....................................................................... 211
ECLR0 ................................................................... 168 [G]
ECR ......................................................................... 52
edge detection function ........................................ 120
EDV0 to EDV2 ...................................................... 124
EDVC0 to EDVC2................................................. 125 [H]
EICC ........................................................................ 52
EIPC ........................................................................ 52
EIPSW ..................................................................... 52
element pointer ....................................................... 51
ENTOn (n = 00, 01, 20 to 24).............................. 172
EP ................................................................... 53, 128 [I]
ES300, ES301 ...................................................... 123
ESE ....................................................................... 125
ESN0 .....................................................................106
ESn0, ESn1 (n = 00 to 05, 10 to 14,
general register....................................................... 51
global pointer .......................................................... 51
halfword access ...................................................... 84
HALT mode .................................................. 140, 143
HLDAK .................................................................... 42
HLDRQ .................................................................... 42
I/O circuit of pins .................................................... 47
I2C bus...................................................................231
I2C interrupt ........................................................... 250
ID .................................................................... 53, 118
IDLE ...................................................................... 142
IDLE mode ................................................... 140, 145
idle state insertion function .................................. 100
IIC ..........................................................................242
IIC clock selection register ................................... 241
IIC control register ................................................ 237
IIC shift register .................................................... 241
IIC status register .................................................239
IICC ....................................................................... 237
IICCL .....................................................................241
IICE ....................................................................... 237
IICS ....................................................................... 239
IIIC0 ....................................................................... 116
IIIF0 ....................................................................... 116
IIMK0 .....................................................................116
IIPR00 to IIPR02................................................... 116
ILGOP ...................................................................100
illegal op code.......................................................129
IMS00 to IMS03 .................................................... 167
IMS04, IMS05 .......................................................168
IMS1 ...................................................................... 169
IMS20 to IMS24 .................................................... 170
in-service priority register ..................................... 118
initial value after reset of each register ............... 380
initialize ................................................................. 379
input clock selection (clock generator) ................136
INTAD....................................................................101
20 to 24, AD, 50 to 53) ........................................ 121
event divide control register 0 to 2 ...................... 125
event divide counter ............................................. 124
event selection register ........................................ 125
EVS ....................................................................... 125
example of CSI system configuration.................. 230
example of inserting wait states ............................ 87
EXC ....................................................................... 239
exception processing function ............................... 99
exception status flag ............................................ 128
exception table........................................................ 61
exception trap ....................................................... 129
extension code...................................................... 271
external count clock............................. 175, 184, 189
external expansion mode ....................................... 67
external interrupt mode register 1 to 6 ................ 121
external interrupt mode register 7 ....................... 123
external memory area ............................................ 65
external wait function ............................................. 87
external trigger mode .................................. 302, 315
[F]
FE .......................................................................... 212
FECC....................................................................... 52
FEPC ....................................................................... 52
FEPSW.................................................................... 52
flash memory ........................................................ 383
User’s Manual U11969EJ3V0UM00
411
APPENDIX C INDEX
INTC ........................................................................ 29 [M]
INTCM10, INTCM11 ............................................. 100
INTCM20 to INTCM24.......................................... 100
INTCP10 to INTCP13 ........................................... 100
INTCSI0 to INTCSI3 ............................................. 101
internal block diagram ............................................ 28
internal count clock.............................. 175, 183, 188
internal peripheral I/O interface ............................. 98
internal RAM area .................................................. 62
Internal ROM area .................................................. 60
internal unit ............................................................. 29
interrupt control register ....................................... 116
interrupt controller .................................................. 29
interrupt list ........................................................... 100
interrupt processing function .................................. 99
interrupt request ................................................... 215
interrupt response time ........................................ 133
interrupt source register ......................................... 52
interrupt stack pointer............................................. 51
interrupt table .......................................................... 61
interval timer ......................................................... 195
INTIIC .................................................................... 250 [N]
INTM0.................................................................... 116
INTM1 to INTM6 ................................................... 121
INTM7.................................................................... 123
INTOV0, INTOV1 .................................................. 100
INTP00 to INTP05 .................................................. 37
INTP0n/IINTCC0n (n = 0 to 3) ............................. 100
INTP10 to INTP14 .................................................. 37
INTP20 .................................................................... 37
INTP21 to INTP24 .................................................. 43
INTP2n/INTCM2n (n = 0 to 4) ............................. 100
INTP30 .................................................................... 38
INTP30/INTCC3 .................................................... 101 [O]
INTP50 to INTP53 ......................................... 38, 101
INTSER ................................................................. 215
INTSR.................................................................... 215
INTST .................................................................... 215
ISPR ...................................................................... 118
ISPR0 to ISPR7 .................................................... 118
maskable interrupt ................................................ 107
maskable interrupt status flag.............................. 118
measurement of cycle .......................................... 201
measurement of pulse width ................................ 196
memory block function ........................................... 85
memory boundary operation condition .................. 97
memory expansion mode register ......................... 68
memory map ........................................................... 59
memory read ........................................................... 90
memory write .......................................................... 94
MM...........................................................................68
MM0 to MM3 ........................................................... 68
MOD0 to MOD3 .................................................... 222
MODE0 to MODE2 ................................................. 44
modulo H register .................................................329
modulo L register.................................................. 329
MS .........................................................................297
MSTS ....................................................................239
multiple interrupt ................................................... 131
NMI ................................................................. 38, 100
NMI pin edge detection function .......................... 106
NMI pin noise elimination ..................................... 106
noise elimination ................................................... 119
normal operation mode .......................................... 54
non-maskable interrupt......................................... 102
non-maskable interrupt status flag ......................106
NOT ....................................................................... 211
NP................................................................... 53, 106
number of access clock ......................................... 83
off-board programming ......................................... 383
on-board programming ......................................... 383
operation in power save mode .............................. 89
operation in the stand-by mode ........................... 155
operation mode ....................................................... 54
ordering information ............................................... 25
OST0 .....................................................................166
OST1 .....................................................................169
output latch ........................................................... 322
OV ...........................................................................53
OVE ....................................................................... 212
overflow (timer 0).................................................. 176
overflow (timer 1).................................................. 184
overflow (timer 2).................................................. 189
[L]
LBEN ....................................................................... 41
link pointer .............................................................. 51
LREL .....................................................................237
LV .......................................................................... 154
412
User’s Manual U11969EJ3V0UM00
APPENDIX C INDEX
overflow (timer 3).................................................. 192
PC............................................................................ 51
PE ..........................................................................212
period in which interrupt is not acknowledged.... 133
peripheral I/O area ................................................. 63
peripheral I/O register ............................................ 71
pin configuration ..................................................... 26
pin function ...................................................... 31, 37
pin status................................................................. 36
PLL lock up ........................................................... 139
PLL mode..............................................................136
PLLSEL ................................................................... 44
PM0 ....................................................................... 349
PM00 to PM07 ...................................................... 349
PM1 ....................................................................... 351
PM10 (register) ..................................................... 367
PM10 to PM17 (bit) .............................................. 351
PM100 to PM103 .................................................. 367
PM11 .....................................................................369
PM110 to PM117 .................................................. 369
PM12 .....................................................................371
PM120 to PM127 .................................................. 371
PM13 .....................................................................373
PM130 to PM137 .................................................. 373
PM14 .....................................................................375
PM140 to PM147 .................................................. 375
PM2 ....................................................................... 353
PM21 to PM26 ...................................................... 353
PM3 ....................................................................... 355
PM30 to PM36 ...................................................... 355
PM4 ....................................................................... 357
PM40 to PM47 ...................................................... 357
PM5 ....................................................................... 360
PM50 to PM57 ...................................................... 360
PM6 ....................................................................... 362
PM60 to PM67 ...................................................... 362
PM9 ....................................................................... 365
PM90 to PM96 ...................................................... 365
PMC0 ....................................................................349
PMC00 to PMC07.................................................349
PMC1 ....................................................................351
PMC10 .................................................................. 367
PMC10 to PMC16.................................................351
PMC100 to PMC103............................................. 367
PMC11 .................................................................. 370
PMC110 to PMC117............................................. 370
PMC12 .................................................................. 372
PMC120 to PMC125, PMC127 ............................372
PMC13 .................................................................. 374
OVFn (n = 0, 1, 20 to 24, 3) ................................ 173
OVIC0, OVIC1 ...................................................... 116
OVIF0, OVIF1 ....................................................... 116
OVMK0, OVMK1 ................................................... 116
OVPRn0 to OVPRn2 (n = 0, 1) ........................... 116
[P]
P0 .......................................................................... 348
P00 to P07 ..................................................... 37, 348
P1 .......................................................................... 350
P10 ........................................................................ 366
P10 to P17 ..................................................... 37, 350
P100 to P103 ................................................. 42, 356
P11 ........................................................................ 368
P110 to P117 ................................................. 42, 368
P12 ........................................................................ 371
P120 to P127 ................................................. 43, 371
P13 ........................................................................ 373
P130 to P137 ................................................. 43, 373
P14 ........................................................................ 375
P140 to P147 ................................................. 44, 375
P1IC0 to P1IC3..................................................... 116
P1IF0 to P1IF3 ..................................................... 116
P1MK0 to P1MK3 ................................................. 116
P1PRn0 to P1PRn2 (n = 0 to 3) .......................... 116
P2 .......................................................................... 352
P20 to P26 ..................................................... 38, 352
P3 .......................................................................... 354
P30 to P36 ..................................................... 38, 354
P4 .......................................................................... 357
P40 to P47 ..................................................... 39, 357
P5 .......................................................................... 359
P50 to P57 ..................................................... 39, 359
P5IC0 to P5IC3..................................................... 116
P5IF0 to P5IF3 ..................................................... 116
P5MK0 to P5MK3 ................................................. 116
P5PRn0 to P5PRn2 (n = 0 to 3) .......................... 116
P6 .......................................................................... 361
P60 to P67 ..................................................... 40, 361
P7 .......................................................................... 363
P70 to P77 ..................................................... 40, 363
P8 .......................................................................... 368
P80 to P87 ..................................................... 40, 368
P9 .......................................................................... 364
P90 to P96 ..................................................... 41, 364
PALV0 to PALV3 .................................................. 327
PB .......................................................................... 322
User’s Manual U11969EJ3V0UM00
413
APPENDIX C INDEX
PMC130 to PMC137............................................. 374
PRCMD ................................................................... 78
PRERR ........................................................... 79, 139
PRM00 to PRM03.................................................166
PRM10 to PRM13.................................................169
PRM2n0 to PRM2n4 (n = 0 to 4)......................... 170
PRM30 to PRM33.................................................171
program counter ..................................................... 51
program register set ............................................... 51
program space ........................................... 58, 69, 97
program status word............................................... 53
programmable wait function ................................... 86
PS ..........................................................................297
PS0, PS1 ..............................................................210
PSC ....................................................................... 142
PSW ...............................................53, 106, 118, 128
PWM........................................................................ 30
PWM control register 0 to 3 ................................. 327
PWM modulo register 0 to 3 ................................ 329
PWM output .......................................................... 198
PWM prescaler register 0 to 3 .............................328
PWM unit ..............................................................325
PWM0 to PWM3 ............................................ 42, 328
PWMC0 to PWMC3 .............................................. 327
PWME0 to PWME3 .............................................. 327
PWPn0, PWPn1 (n = 0 to 3)................................ 328
PWPR0 to PWPR3 ............................................... 328
PMC2 .................................................................... 353
PMC21 to PMC26................................................. 353
PMC3 .................................................................... 356
PMC30 to PMC35................................................. 356
PMPn0 to PMPn2 (n = 0 to 3) ............................. 327
port function .......................................................... 337
ports
Port 0............................................................ 348
Port 1............................................................ 350
Port 2............................................................ 352
Port 3............................................................ 354
Port 4............................................................ 357
Port 5............................................................ 359
Port 6............................................................ 361
Port 7............................................................ 363
Port 8............................................................ 363
Port 9............................................................ 364
Port 10 ......................................................... 366
Port 11 ......................................................... 368
Port 12 ......................................................... 371
Port 13 ......................................................... 373
Port 14 ......................................................... 375
Port mode control register
Port 0 mode control register ....................... 349
Port 1 mode control register ....................... 351
Port 2 mode control register ....................... 353
Port 3 mode control register ....................... 356 [R]
Port 10 mode control register ..................... 367
Port 11 mode control register ..................... 370
Port 12 mode control register ..................... 372
Port 13 mode control register ..................... 374
Port mode register
R/W ......................................................................... 41
r0 to r31 .................................................................. 51
RAM ........................................................................ 29
RD ...........................................................................42
real-time output function ...................................... 321
real-time pulse unit ........................................ 29, 157
receive buffer ........................................................ 213
reception completion interrupt .............................215
reception error interrupt ....................................... 215
recommended connection of unused pins ............ 48
REG0 to REG7 ....................................................... 78
repetition frequency .............................................. 335
RESET .................................................................. 100
RESET .................................................................... 45
reset function ........................................................ 377
ROM ........................................................................ 29
ROM-less mode ...................................................... 54
RPU ......................................................................... 29
RTP ................................................................ 30, 322
RTP0 to RTP7 ........................................................ 43
Port 0 mode register.................................... 349
Port 1 mode register.................................... 351
Port 2 mode register.................................... 353
Port 3 mode register.................................... 355
Port 4 mode register.................................... 358
Port 5 mode register.................................... 360
Port 6 mode register.................................... 362
Port 9 mode register.................................... 365
Port 10 mode register ................................. 367
Port 11 mode register ................................. 369
Port 12 mode register ................................. 371
Port 13 mode register ................................. 374
Port 14 mode register ................................. 375
power save control ............................................... 140
power save control register.................................. 142
414
User’s Manual U11969EJ3V0UM00
APPENDIX C INDEX
RXB, RXBL ........................................................... 213
SRIF0 ....................................................................116
SRMK0 .................................................................. 116
SRPR00 to SRPR02............................................. 116
stack pointer ........................................................... 51
start condition .......................................................243
status saving register for interrupt ......................... 54
status saving register for NMI ................................ 52
STD ....................................................................... 240
STIC0 ....................................................................116
STIF0.....................................................................116
STMK0 .................................................................. 116
stop condition........................................................ 247
STP ....................................................................... 142
STPR00 to STPR02 ............................................. 116
STT........................................................................ 238
SVA ....................................................................... 242
SYC ......................................................................... 82
SYN0 to SYN3 ...................................................... 327
SYS ................................................................ 79, 139
system control register ........................................... 82
system register set ................................................. 52
system status register ............................................ 79
RXB0 to RXB7 ...................................................... 213
RXD ......................................................................... 38
RXE ....................................................................... 209
RXEB.....................................................................213
[S]
S .............................................................................. 53
SAT ......................................................................... 53
SCK0 ....................................................................... 39
SCK1 ....................................................................... 39
SCK2 ....................................................................... 43
SCK3 ....................................................................... 43
SCL ......................................................................... 38
SCLS .....................................................................211
SCS0, SCS1 ......................................................... 123
SDA ......................................................................... 38
securing oscillation stabilization time .................. 149
SEIC0 .................................................................... 116
SEIF0 .................................................................... 116
SEMK0 .................................................................. 116
SEPR00 to SEPR02 ............................................. 116
serial I/O shift register 0 to 3 ............................... 223
serial interface ............................................... 29, 205 [T]
SI0 ........................................................................... 39
SI1 ........................................................................... 39
SI2 ........................................................................... 43
SI3 ........................................................................... 43
single-chip mode .................................................... 54
SIO .......................................................................... 29
SIO0 to SIO3 ........................................................ 213
SIOn0 to SIOn7 (n = 0 to 3) ................................ 213
SL .......................................................................... 210
slave address register .......................................... 242
SMC ........................................................................ 24
SO0 ......................................................................... 39
SO1 ......................................................................... 39
SO2 ......................................................................... 43
SO3 ......................................................................... 43
software exception................................................ 126
software STOP mode .................................. 140, 147
SOT ....................................................................... 212
SPD ....................................................................... 240
specific register....................................................... 77
specification of transfer direction ......................... 245
SPIE ...................................................................... 237
SPT ....................................................................... 238
SRIC0 .................................................................... 116
TBC ....................................................................... 150
TBCS .....................................................................142
TCLR0 .....................................................................37
text pointer .............................................................. 51
TI0 ...........................................................................37
TI1 ...........................................................................37
TI20 ......................................................................... 37
TI21 to TI24 ............................................................ 43
time base counter .................................................150
timer 0 operation .................................................. 174
timer 0, 0L .............................................................161
timer 1 operation .................................................. 183
timer 1, 1L .............................................................162
timer 2 ...................................................................164
timer 2 operation .................................................. 188
timer 20 to 24 .......................................................164
timer 3 ...................................................................165
timer 3 operation .................................................. 192
timer control register 00 ....................................... 166
timer control register 01 ....................................... 167
timer control register 02 ....................................... 168
timer control register 1 ......................................... 169
timer control register 20 to 24.............................. 170
timer control register 3 ......................................... 171
User’s Manual U11969EJ3V0UM00
415
APPENDIX C INDEX
timer output control register 0, 1 ......................... 172
WRL ........................................................................ 42
WTIM .....................................................................238
Word access ........................................................... 84
Wrap-around .................................................... 58, 69
timer overflow status register ............................... 173
timer trigger mode ....................................... 302, 311
timer/counter function ........................................... 157
timing of 3-wire serial I/O mode ......... 226, 227, 229
TM0, TM0L............................................................ 161 [X]
TM1, TM1L............................................................ 162
TM20 to TM24 ...................................................... 164
TM3 ....................................................................... 165 [Z]
TMC00................................................................... 166
TMC01................................................................... 167
TMC02................................................................... 168
TMC1.....................................................................169
TMC20 to TMC24 ................................................. 170
TMC3.....................................................................171
TO00, TO01 ............................................................ 37
TO20 ....................................................................... 37
TO21 to TO24 ......................................................... 43
TOC0, TOC1 ......................................................... 172
toggle output ......................................................... 191
TOVS.....................................................................173
transmission completion interrupt ........................ 215
transmission shift register .................................... 214
TRAP0n, TRAP1n (n = 0 to F) ............................ 100
TRC ....................................................................... 240
TRG0, TRG1 ......................................................... 299
TXD ......................................................................... 38
TXE ....................................................................... 209
TXED .....................................................................214
TXS, TXSL ............................................................ 214
TXS0 to TXS7 ....................................................... 214
X1, X2 .....................................................................45
Z .............................................................................. 53
zero register ............................................................ 51
[U]
UART.....................................................................206
UBEN ...................................................................... 41
UNLOCK ........................................................ 79, 139
[V]
VDD ........................................................................... 45
VPP ........................................................................... 46
VSS ........................................................................... 45
[W]
WAIT ....................................................................... 44
Wake-up function.................................................. 273
Wait function ........................................................... 86
WREL .................................................................... 237
WRH ........................................................................ 42
416
User’s Manual U11969EJ3V0UM00
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CS 99.1
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