UPD780702YGC-XXX-8BT [RENESAS]
8-BIT, MROM, 3.1446MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, PLASTIC, QFP-80;
| 型号： | UPD780702YGC-XXX-8BT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT, MROM, 3.1446MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, PLASTIC, QFP-80 |
| 文件： | 总66页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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RELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD780701Y, 780702Y
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD780701Y and 780702Y are the µPD780701Y Subseries products of the 78K/0 Series. These
microcontrollers have DCAN controller (µPD780701Y), IEBusTM controller (µPD780702Y), A/D converter, timer, serial
interface, interrupt control, and various other peripheral hardware.
The µPD78F0701Y which can operate in the same power supply voltage as the mask ROM version, and various
development tools are under development.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780701Y Subseries User’s Manual:
U13781E
78K/0 Series User’s Manual Instructions: U12326E
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
DCAN (Direct Storage Controller Area Network) controller (incorporated in µPD780701Y)
IEBus (Inter Equipment BusTM) controller (incorporated in µPD780702Y)
Internal ROM: 60 Kbytes
Internal high-speed RAM: 1024 bytes
Internal expansion RAM: 2048 bytes
Buffer RAM for DCAN: 288 bytes (µPD780701Y only)
Minimum instruction execution time can be changed from high-speed (0.32 µs) to low-speed (5.09 µs)
I/O ports: 67
8-bit resolution A/D converter: 16 channels
Serial interface: 4 channels
Timer: 7 channels
Power supply voltage: VDD = 3.5 to 5.5 V
APPLICATIONS
Car audio systems, etc.
ORDERING INFORMATION
Part Number
Package
µPD780701YGC-×××-8BT
µPD780702YGC-×××-8BT
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
Remark ××× indicates ROM code suffix.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. U13920EJ1V0PM00 (1st edition)
Date Published March 1999 N CP(K)
Printed in Japan
1999
©
µPD780701Y, 780702Y
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
µ
µ
µ
EMI-noise reduced version of the PD78078
PD78075B
PD78078
µ
PD78054 with timer and enhanced external interface function
µ
PD78078Y
100-pin
100-pin
µ
µ
ROM-less version of the PD78078
µ
PD78070A
PD78070AY
µ
µ
100-pin
µ
PD78078Y with enhanced serial I/O, and only selected functions are provided
PD78054 with enhanced serial I/O, EMI-noise reduced version
PD780018AY
µ
PD780058
µ
PD780058Y
80-pin
80-pin
80-pin
80-pin
µ
PD78058F
µ
µ
PD78058FY EMI-noise reduced version of the PD78054
µ
µ
PD78054Y
PD78054
µ
µ
µ
PD78018F with UART, D/A converter, and enhanced I/O
PD780024A with expanded RAM
µ
PD780065
µ
µ
µ
PD780034AY
PD780024A with enhanced A/D converter
PD780034A
PD780024A
64-pin
µ
µ
PD78018F with enhanced serial I/O
64-pin
PD780024AY
µ
PD78014H
PD78018F
µ
EMI-noise reduced version of the PD78018F
64-pin
µ
µ
PD78018FY
Basic subseries for control
64-pin
42/44-pin
µ
PD78083
On-chip UART and capable of low-voltage (1.8 V) operation
Inverter control
µ
On-chip inverter control circuit and UART, EMI-noise reduced version
64-pin
PD780988
FIPTM drive
µ
100-pin
100-pin
80-pin
80-pin
80-pin
µ
µ
PD780208
PD78044F with enhanced I/O and FIP C/D, Display output total: 53
PD78044H with enhanced I/O and FIP C/D, Display output total: 48
µ
µ
PD780228
For panel control, on-chip FIP C/D, Display output total: 53
PD780232
PD78044H
78K/0
Series
µ
µ
µ
PD78044F with N-ch open-drain input/output, Display output total: 34
Basic subseries for driving FIP, Display output total: 34
PD78044F
LCD drive
µ
µ
100-pin
100-pin
100-pin
PD780308
PD78064B
µ
PD78064 with enhanced SIO and expanded ROM and RAM
µ
PD780308Y
EMI-noise reduced version of the PD78064
µ
µ
µ
PD78064Y
PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported
100-pin
80-pin
80-pin
80-pin
µ
µ
PD780948
PD78098B
On-chip DCAN controller
PD78054 with IEBusTM controller, EMI-noise reduced version
µ
µ
PD780701Y
On-chip DCAN/IEBus controller
µ
PD780833Y
On-chip J1850 (CLASS2) controller
Meter control
µ
100-pin
80-pin
80-pin
For controlling industrial meters
PD780958
µ
µ
PD780973
PD780955
On-chip controller/driver for driving automobile meters
Ultra low power consumption, on-chip UART
Preliminary Product Information U13920EJ1V0PM00
2
µPD780701Y, 780702Y
OVERVIEW OF FUNCTIONS
Part Number
µPD780701Y
µPD780702Y
Item
Internal
memory
ROM
60 Kbytes
1024 bytes
2048 bytes
288 bytes
High-speed RAM
Expansion RAM
Buffer RAM for DCAN
None
Minimum instruction execution time
On-chip minimum instruction execution time variable function
• 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.09 µs (@ 6.29-MHz operation with system clock)
General-purpose registers
Instruction set
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
I/O ports
Total:
67
56
8
• CMOS I/O:
• TTL input/CMOS output:
• N-ch open-drain I/O:
3
A/D converter
Serial interface
• 8-bit resolution × 16 channels
• Power fail detection function
• 3-wire serial I/O mode:
• UART mode:
2 channels
1 channel
1 channel
• I2C bus mode:
Timer
• 16-bit timer/event counter:
• 8-bit timer/event counter:
• Watch timer:
2 channels
3 channels
1 channel
1 channel
• Watchdog timer:
Timer output
Clock output
5 (8-bit PWM output capable: 3)
49.2 kHz, 98.3 kHz, 197 kHz, 393 kHz, 786 kHz, 1.57 MHz, 3.15 MHz, 6.29 MHz
(@ 6.29-MHz operation with system clock)
Buzzer output
0.768 kHz, 1.54 kHz, 3.07 kHz, 6.14 kHz (@ 6.29-MHz operation with system clock)
Bus controller
DCAN controller
Internal: 20, External: 8
Internal: 1
IEBus controller
Vectored interrupt Maskable
Internal: 19, External: 8
sources
Non-maskable
Software
Power supply voltage
Operating ambient temperature
Package
1
VDD = 3.5 to 5.5 V
TA = −40 to +85°C
80-pin plastic QFP (14 × 14 mm)
Preliminary Product Information U13920EJ1V0PM00
3
µPD780701Y, 780702Y
PIN CONFIGURATION (Top View)
(1) µPD780701Y
• 80-pin plastic QFP (14 × 14 mm)
µPD780701YGC-×××-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P90/ANI8
P91/ANI9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P66
P65
P64
P92/ANI10
P93/ANI11
P94/ANI12
P95/ANI13
P96/ANI14
P97/ANI15
P70/TI52/TO52
P71/SDA0
P27/PCL
P26/ASCK0
P25/TxD0
P24/RxD0
P23/BUZ
P07/INTP7
P06/INTP6
P05/INTP5
P04/INTP4
P22/SCK31
P21/SO31
P20/SI31
P57
P72/SCL0
P73/TO01
P74/TI001
P75/TI011
P76/TI50/TO50
P77/TI51/TO51
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3
P56
P55
P54
P53
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
3. Connect the AVREF pin to VDD0.
Remark When the µPD780701Y and 780702Y are used in applications where the noise generated inside the
microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying
voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is
recommended.
Preliminary Product Information U13920EJ1V0PM00
4
µPD780701Y, 780702Y
(2) µPD780702Y
• 80-pin plastic QFP (14 × 14 mm)
µPD780702YGC-×××-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P90/ANI8
P91/ANI9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P66
P65
P64
P92/ANI10
P93/ANI11
P94/ANI12
P95/ANI13
P96/ANI14
P97/ANI15
P70/TI52/TO52
P71/SDA0
P27/PCL
P26/ASCK0
P25/TxD0
P24/RxD0
P23/BUZ
P07/INTP7
P06/INTP6
P05/INTP5
P04/INTP4
P22/SCK31
P21/SO31
P20/SI31
P57
P72/SCL0
P73/TO01
P74/TI001
P75/TI011
P76/TI50/TO50
P77/TI51/TO51
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3
P56
P55
P54
P53
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
3. Connect the AVREF pin to VDD0.
Remark When the µPD780701Y and 780702Y are used in applications where the noise generated inside the
microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying
voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is
recommended.
Preliminary Product Information U13920EJ1V0PM00
5
µPD780701Y, 780702Y
ANI0 to ANI15:
ASCK0:
Analog Input
P80 to P87:
P90 to P97:
PCL:
Port 8
Asynchronous Serial Clock
Analog Reference Voltage
Analog Ground
Buzzer Output
Regulator for CPU Power Supply
CAN Receive Data
CAN Transmit Data
Internally Connected
Interrupt for Peripherals
IEBus Receive Data
IEBus Transmit Data
Port 0
Port 9
AVREF:
Programmable Clock
Reset
AVSS:
RESET:
BUZ:
RxD0:
Receive Data (for UART0)
Serial Clock (for SIO30, 31)
Serial Clock (for IIC0)
Serial Data
CPUREG:
CRXD:
SCK30, SCK31:
SCL0:
CTXD:
SDA0:
IC:
SI30, SI31:
SO30, SO31:
Serial Input
INTP0 to INTP7:
IRX0:
Serial Output
TI000, TI010, TI001,
TI011, TI50, TI51,
TI52:
ITX0:
P00 to P07:
P20 to P27:
P30 to P36:
P40 to P47:
P50 to P57:
P64 to P67:
P70 to P77:
Timer Input
Port 2
TO00, TO01, TO50,
TO51, TO52:
TxD0:
Port 3
Timer Output
Transmit Data (for UART0)
Power Supply
Ground
Port 4
Port 5
VDD0, VDD1:
Port 6
VSS0, VSS1:
Port 7
X1, X2:
Crystal
Preliminary Product Information U13920EJ1V0PM00
6
µPD780701Y, 780702Y
BLOCK DIAGRAM
(1) µPD780701Y
TO00/P34
TI000/P35
TI010/P36
16-bit TIMER/
EVENT COUNTER 00
(TM00)
8
8
7
8
8
4
8
8
8
PORT 0
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 8
PORT 9
P00 to P07
P20 to P27
P30 to P36
P40 to P47
P50 to P57
P64 to P67
P70 to P77
P80 to P87
P90 to P97
TO01/P73
TI001/P74
TI011/P75
16-bit TIMER/
EVENT COUNTER 01
(TM01)
8-bit TIMER/
EVENT COUNTER 50
(TM50)
TI50/TO50/P76
TI51/TO51/P77
TI52/TO52/P70
8-bit TIMER/
EVENT COUNTER 51
(TM51)
78K/0
CPU
CORE
ROM
60 KBytes
8-bit TIMER/
EVENT COUNTER 52
(TM52)
WATCH TIMER
(WTN0)
INTERNAL INTERNAL
HIGH-SPEED EXPANSION
ANI0/P80 to
ANI7/P87,
ANI8/P90 to
ANI15/P97
WATCHDOG TIMER
(WDT)
16
RAM
RAM
A/D CONVERTER3
(AD3)
1024 Bytes 2048 Bytes
SI30/P30
SO30/P31
SCK30/P32
SERIAL
INTERFACE 30
(SIO30)
(ADCTL3)
AVSS
AVREF
SI31/P20
SO31/P21
SCK31/P22
SERIAL
INTERFACE 31
(SIO31)
I2C BUS
(IIC0)
DCAN CONTROLLER
(DCAN)
CRXD
CTXD
SDA0/P71
SCL0/P72
RxD0/P24
TxD0/P25
ASCK0/P26
UART
(UART0)
DCAN RAM
288 Bytes
INTERRUPT
CONTROL
(INT29)
INTP0/P00 to
INTP7/P07
8
RESET
X1
X2
SYSTEM
CONTROL
CLOCK OUTPUT
CONTROL
PCL/P27
BUZ/P23
VDD1
CPUREG
VSS1
VOLTAGE
REGULATOR
BUZZER OUTPUT
VDD0
VSS0
IC
Preliminary Product Information U13920EJ1V0PM00
7
µPD780701Y, 780702Y
(2) µPD780702Y
TO00/P34
TI000/P35
TI010/P36
16-bit TIMER/
EVENT COUNTER 00
(TM00)
8
8
7
8
8
4
8
8
8
PORT 0
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 8
PORT 9
P00 to P07
P20 to P27
P30 to P36
P40 to P47
P50 to P57
P64 to P67
P70 to P77
P80 to P87
P90 to P97
TO01/P73
TI001/P74
TI011/P75
16-bit TIMER/
EVENT COUNTER 01
(TM01)
8-bit TIMER/
EVENT COUNTER 50
(TM50)
TI50/TO50/P76
TI51/TO51/P77
TI52/TO52/P70
8-bit TIMER/
EVENT COUNTER 51
(TM51)
78K/0
CPU
CORE
ROM
60 KBytes
8-bit TIMER/
EVENT COUNTER 52
(TM52)
WATCH TIMER
(WTN0)
INTERNAL INTERNAL
HIGH-SPEED EXPANSION
ANI0/P80 to
ANI7/P87,
ANI8/P90 to
ANI15/P97
WATCHDOG TIMER
(WDT)
16
RAM
RAM
A/D CONVERTER3
(AD3)
1024 Bytes 2048 Bytes
SI30/P30
SO30/P31
SCK30/P32
SERIAL
INTERFACE 30
(SIO30)
(ADCTL3)
AVSS
AVREF
SI31/P20
SO31/P21
SCK31/P22
SERIAL
INTERFACE 31
(SIO31)
IEBus CONTROLLER
(IEBUS0)
IRX0
ITX0
SDA0/P71
SCL0/P72
RxD0/P24
TxD0/P25
ASCK0/P26
I2C BUS
(IIC0)
UART
(UART0)
INTERRUPT
CONTROL
(INT29)
INTP0/P00 to
INTP7/P07
8
RESET
X1
X2
SYSTEM
CONTROL
CLOCK OUTPUT
CONTROL
PCL/P27
BUZ/P23
V
DD1
VOLTAGE
REGULATOR
CPUREG
BUZZER OUTPUT
V
SS1
V
DD0
V
SS0
IC
Preliminary Product Information U13920EJ1V0PM00
8
µPD780701Y, 780702Y
CONTENTS
1. DIFFERENCES BETWEEN µPD780701Y AND µPD780702Y........................................................... 10
2. PIN FUNCTIONS ................................................................................................................................. 11
2.1 Port Pins.....................................................................................................................................................11
2.2 Non-port Pins.............................................................................................................................................13
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................................15
3. MEMORY SPACE ............................................................................................................................... 17
4. PERIPHERAL HARDWARE FUNCTION FEATURES........................................................................ 18
4.1 Ports ...........................................................................................................................................................18
4.2 Clock Generator.........................................................................................................................................19
4.3 Timer/Counter ............................................................................................................................................20
4.4 Clock Output/Buzzer Output Control Circuit...........................................................................................26
4.5 A/D Converter.............................................................................................................................................27
4.6 Serial Interfaces.........................................................................................................................................28
4.7 DCAN Controller (µPD780701Y only).......................................................................................................31
4.8 IEBus Controller (µPD780702Y only) .......................................................................................................33
5. INTERRUPT FUNCTIONS................................................................................................................... 36
6. STANDBY FUNCTION ........................................................................................................................ 40
7. RESET FUNCTION.............................................................................................................................. 40
8. INSTRUCTION SET............................................................................................................................. 41
9. ELECTRICAL SPECIFICATIONS ....................................................................................................... 44
10. PACKAGE DRAWING......................................................................................................................... 57
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................... 58
APPENDIX B. RELATED DOCUMENTS................................................................................................... 60
Preliminary Product Information U13920EJ1V0PM00
9
µPD780701Y, 780702Y
1. DIFFERENCES BETWEEN µPD780701Y AND µPD780702Y
The essential difference between these two products is the on-chip bus controller.
The main differences between the µPD780701Y and µPD780702Y are outlined in Table 1-1.
Table 1-1. Differences between µPD780701Y and µPD780702Y
Part Number
µPD780701Y
µPD780702Y
Item
On-chip bus controller
Buffer RAM for DCAN
RX Pin (Pin No.62)
TX Pin (Pin No.63)
DCAN controller
IEBus controller
288 bytes
CRXD
None
IRX0
ITX0
CTXD
Internal maskable interrupt
Total: 20 sources (3 sources via the
DCAN controller)
Total: 19 sources (2 sources via the
IEBus controller)
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
2. PIN FUNCTIONS
2.1 Port Pins (1/2)
Pin Name
I/O
Function
After Reset
Input
Alternate Function
INTP0 to INTP7
P00 to P07 Input/output
Port 0.
8-bit input/output port.
Input/output can be specified in 1-bit units. An on-chip pull-up
resistor can be specified by means of software.
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
Input/output
Port 2.
Input
SI31
8-bit input/output port.
SO31
SCK31
BUZ
Input/output can be specified in 1-bit units. An on-chip pull-up
resistor can be specified by means of software.
RxD0
TxD0
ASCK0
PCL
Input/output
Port 3.
An on-chip pull-up resistor can be
specified by means of software.
Input
SI30
7-bit input/output port.
Input/output can be
specified in 1-bit units.
SO30
SCK30
−
N-ch open-drain input/output port
(15-V withstand voltage). LEDs can
be driven directly.
P34
P35
P36
An on-chip pull-up resistor can be
specified by means of software.
TO00
TI000
TI010
−
P40 to P47 Input/output
P50 to P57 Input/output
P60 to P67 Input/output
Port 4.
Input
Input
Input
8-bit input/output port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of
software. Interrupt request flag KRIF is set to 1 by falling edge
detection.
Port 5.
−
−
8-bit input/output port.
TTL level input/CMOS output.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of
software.
Port 6.
4-bit input/output port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of
software.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
2.1 Port Pins (2/2)
Pin Name
P70
I/O
Function
After Reset
Input
Alternate Function
TI52/TO52
Input/output
Port 7.
An on-chip pull-up resistor can be
specified by means of software.
8-bit input/output port.
Input/output can be
specified in 1-bit units.
P71
P72
P73
P74
P75
P76
P77
N-ch open-drain input/output port
(5-V withstand voltage).
SDA0
SCL0
An on-chip pull-up resistor can be
specified by means of software.
TO01
TI001
TI011
TI50/TO50
TI51/TO51
ANI0 to ANI7
P80 to P87 Input/output
Port 8.
Input
Input
8-bit input/output port.
Input/output can be specified in 1-bit units.
P90 to P97 Input/output
Port 9.
ANI8 to ANI15
8-bit input/output port.
Input/output can be specified in 1-bit units.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
2.2 Non-port Pins (1/2)
Pin Name
I/O
Function
After Reset Alternate Function
INTP0 to INTP7 Input
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
Input
P00 to P07
SI30
Input
Serial interface serial data input
Input
P30
SI31
P20
SO30
SO31
SDA0
SCK30
SCK31
SCL0
RxD0
TxD0
Output Serial interface serial data output
Input
P31
P21
I/O
I/O
Serial interface serial data input/output
Serial interface serial clock input/output
Input
Input
P71
P32
P22
P72
Input
Serial data input for asynchronous serial interface
Input
Input
Input
Input
Output
Input
Output
Input
P24
Output Serial data output for asynchronous serial interface
P25
ASCK0
CRXDNote 1
CTXDNote 1
IRX0Note 2
ITX0Note 2
TI000
TI010
TI001
TI011
TI50
Input
Input
Serial clock input for asynchronous serial interface
Data input of DCAN controller (DCAN)
P26
−
Output Data output of DCAN controller (DCAN)
Input Data input of IEBus controller (IEBUS0)
Output Data output of IEBus controller (IEBUS0)
−
−
−
Input
External count clock input to 16-bit timer (TM00)
External count clock input to 16-bit timer (TM00)
External count clock input to 16-bit timer (TM01)
External count clock input to 16-bit timer (TM01)
External count clock input to 8-bit timer (TM50)
External count clock input to 8-bit timer (TM51)
External count clock input to 8-bit timer (TM52)
P35
P36
P74
P75
P76/TO50
P77/TO51
P70/TO52
P34
TI51
TI52
TO00
TO01
TO50
TO51
TO52
PCL
Output 16-bit timer (TM00) output
16-bit timer (TM01) output
8-bit timer (TM50) output
8-bit timer (TM51) output
8-bit timer (TM52) output
Output Clock output
Input
P73
P76/TI50
P77/TI51
P70/TI52
P27
Input
Input
Input
BUZ
Output Buzzer output
P23
ANI0 to ANI7 Input
ANI8 to ANI15
A/D converter (AD3) analog input
P80 to P87
P90 to P97
−
AVREF
AVSS
X1
Input
−
A/D converter (AD3) reference voltage and analog power supply
A/D converter (AD3) ground potential
−
−
−
−
−
Input
−
Connecting crystal resonator for system clock oscillation
−
X2
−
Notes 1. µPD780701Y only
2. µPD780702Y only
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
2.2 Non-port Pins (2/2)
Pin Name
RESET
I/O
Input
−
Function
After Reset Alternate Function
System reset input
Input
−
−
CPUREG
Regulator for CPU power supply. Connect to VSS0 or VSS1 via a
−
0.1-µF capacitor.
VDD0
VDD1
VSS0
VSS1
IC
−
−
−
−
−
Positive power supply for ports
−
−
−
−
−
−
−
−
−
−
Positive power supply (except ports and analog section)
Ground potential for ports
Ground potential (except ports and analog section)
Internally connected. Connect directly to VSS0 or VSS1.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the input/output circuit configuration of each type, refer to Figure 2-1.
Table 2-1. Types of Pin Input/Output Circuits
Pin Name
Input/Output Circuit Type
8-C
I/O
Recommended Connection of Unused Pins
Independently connect to VSS0 via a resistor.
P00/INTP0 to P07/INTP7
P20/SI31
Input/output
Independently connect to VDD0 or VSS0 via a resistor.
P21/SO31
5-H
8-C
5-H
8-C
5-H
8-C
5-H
8-C
5-H
8-C
13-P
5-H
8-C
P22/SCK31
P23/BUZ
P24/RxD0
P25/TxD0
P26/ASCK0
P27/PCL
P30/SI30
P31/SO30
P32/SCK30
P33
Connect to VDD0 via a resistor.
P34/TO00
Independently connect to VDD0 or VSS0 via a resistor.
P35/TI000
P36/TI010
P40 to P47
P50 to P57
P64 to P67
P70/TI52/TO52
P71/SDA0
5-H
5-T
5-H
Independently connect to VDD0 via a resistor.
Independently connect to VDD0 or VSS0 via a resistor.
13-R
Independently connect to VDD0 via a resistor.
P72/SCL0
P73/TO01
5-H
8-C
Independently connect to VDD0 or VSS0 via a resistor.
P74/TI001
P75/TI011
P76/TI50/TO50
P77/TI51/TO51
P80/ANI0 to P87/ANI7
P90/ANI8 to P97/ANI15
CRXDNote 1
CTXDNote 1
IRX0Note 2
ITX0Note 2
RESET
AVREF
AVSS
11-E
2
3-B
2
Input
Connect to VDD0 or VSS0 via a resistor.
Leave open.
Output
Input
Connect to VDD0 or VSS0 via a resistor.
Leave open.
3-B
2
Output
Input
−
−
Connect to VDD0.
−
Connect to VSS0.
IC
Connect directly to VSS0 or VSS1.
Notes 1. µPD780701Y only
2. µPD780702Y only
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 2-1. Pin Input/Output Circuits
Type 2
Type 8-C
VDD0
pullup
enable
P-ch
IN
V
DD0
data
P-ch
IN/OUT
output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
V
SS0
V
DD0
Type 3-B
Type 11-E
data
P-ch
IN/OUT
VDD0
output
disable
N-ch
P-ch
V
SS0
data
OUT
Comparator
P-ch
N-ch
+
_
N-ch
V
SS0
AVSS
VREF
(threshold voltage)
input
enable
Type 13-P
VDD0
Type 5-H
pullup
enable
P-ch
IN/OUT
output data
output disable
VDD0
N-ch
data
P-ch
VSS0
IN/OUT
input
enable
output
disable
N-ch
V
SS0
input
enable
VDD0
Type 5-T
Type 13-R
pullup
enable
P-ch
IN/OUT
VDD0
output data
output disable
N-ch
data
P-ch
V
SS0
IN/OUT
output
disable
N-ch
V
SS0
TTL input
input
enable
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
3. MEMORY SPACE
Figure 3-1 shows the memory map of the µPD780701Y and 780702Y.
Figure 3-1. Memory Map
FFFFH
Special function
registers (SFR)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
32 × 8 bits
FEE0H
FEDFH
Internal high-speed RAM
1024 × 8 bits
FE00H
FDFFH
Reserved
FA20H
FA1FH
EFFFH
Buffer RAM for DCANNote
Program area
CALLF entry area
Program area
288 × 8 bits
F900H
F8FFH
Data
memory
space
1000H
0FFFH
Reserved
F800H
F7FFH
Internal expansion RAM
2048 × 8 bits
0800H
07FFH
F000H
EFFFH
0080H
007FH
Program
memory
space
Internal ROM
61440 × 8 bits
CALLT table area
Vector table area
0040H
003FH
0000H
0000H
Note Buffer RAM for DCAN is incorporated only in the µPD780701Y. It is reserved area in the µPD780702Y.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4. PERIPHERAL HARDWARE FUNCTION FEATURES
4.1 Ports
The following three types of I/O ports are available.
• CMOS input/output (Ports 0, 2 to 4, 7 to 9 (except P33, P71, P72)):
• TTL input/CMOS output (Port 5):
56
8
• N-ch open-drain input/output (P33, P71, P72):
Total:
3
67
Table 4-1. Port Functions
Port Name
Port 0
Pin Name
Function
P00 to P07
Input/output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 2
Port 3
P20 to P27
Input/output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
P30 to P32,
P34 to P36
P33
Input/output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
N-ch open-drain input/output port. Input/output can be specified in 1-bit units. LEDs can
be driven directly.
Port 4
P40 to P47
Input/output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Interrupt request flag KRIF is set to 1 by falling edge detection.
Port 5
Port 6
Port 7
P50 to P57
TTL input/CMOS output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
P64 to P67
Input/output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
P70, P73 to P77
Input/output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
P71, P72
N-ch open-drain input/output port. Input/output can be specified in 1-bit units.
Input/output port. Input/output can be specified in 1-bit units.
Input/output port. Input/output can be specified in 1-bit units.
Port 8
Port 9
P80 to P87
P90 to P97
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
• 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.09 µs (@ 6.29-MHz operation with system clock)
Figure 4-1. Clock Generator Block Diagram
Prescaler
Clock to peripheral
hardware
System
clock
oscillator
X1
X2
Prescaler
f
X
f
2
X
f
X
f
X
f
X
22 23 24
Standby
control
circuit
CPU clock
STOP
(fCPU
)
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4.3 Timer/Counter
Seven timer/counter channels are incorporated.
• 16-bit timer/event counter:
• 8-bit timer/event counter:
• Watch timer:
2 channels
3 channels
1 channel
1 channel
• Watchdog timer:
Table 4-2. Operations of Timer/Event Counters
16-bit timer/event
counters TM00,
TM01
8-bit timer/event
counters TM50,
TM51, TM52
Watch timer
Watchdog timer
Operation
Interval timer
2 channels
2 channels
2 outputs
−
3 channels
1 channelNote 1
1 channelNote 2
mode
External event counter
Timer output
3 channels
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
1
Function
3 outputs
PWM output
3 outputs
PPG output
2 outputs
4 inputs
2 outputs
2 outputs
4
−
Pulse width measurement
Square wave output
One-shot pulse output
Interrupt source
−
3 outputs
−
3
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog
timer by selecting either the watchdog timer function or the interval timer function.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 4-2. Block Diagram of 16-Bit Timer/Event Counter TM00
Internal bus
INTTM000
Noise
elimination
circuit
16-bit capture/compare
register 000 (CR000)
TI010/P36
Match
f
X
/2
/22
/26
f
f
X
16-bit timer/counter
00 (TM00)
X
Clear
Output
control
circuit
TO00/P34
Match
Noise
f
/23
X
elimination
circuit
Noise
elimination
circuit
16-bit capture/compare
register 010 (CR010)
TI000/P35
INTTM010
Internal bus
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 4-3. Block Diagram of 16-Bit Timer/Event Counter TM01
Internal bus
INTTM001
Noise
elimination
circuit
16-bit capture/compare
register 001 (CR001)
TI011/P75
Match
fX/2
f
f
X
X
/22
/26
16-bit timer/counter
01 (TM01)
Clear
Output
control
circuit
TO01/P73
Match
Noise
f
X
/23
elimination
circuit
Noise
elimination
circuit
16-bit capture/compare
register 011 (CR011)
TI001/P74
INTTM011
Internal bus
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 4-4. Block Diagram of 8-Bit Timer/Event Counter TM50
Internal bus
8-bit timer compare
register 50 (CR50)
Selector
S
INTTM50
Match
TI50/TO50/P76
f
f
f
f
f
X
X
X
X
X
/22
/23
/24
/26
/28
8-bit timer/
INV
Q
TO50/TI50/P76
OVF
counter 50
(TM50)
R
f
X
/212
Clear
3
S
R
Level
inversion
Selector
TCL502 TCL501 TCL500
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
Timer clock select
register 50 (TCL50)
8-bit timer mode control
register 50 (TMC50)
Internal bus
Figure 4-5. Block Diagram of 8-Bit Timer/Event Counter TM51
Internal bus
8-bit timer compare
register 51 (CR51)
INTTM51
Selector
S
TI51/TO51/P77
Match
f
f
f
f
X
X
X
X
/22
/23
/26
/28
8-bit timer/
INV
Q
TO51/TI51/P77
OVF
counter 51
f
f
X
X
/210
(TM51)
R
/212
Clear
3
S
R
Level
inversion
Selector
TCL512 TCL511 TCL510
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
Timer clock select
register 51 (TCL51)
8-bit timer mode control
register 51 (TMC51)
Internal bus
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 4-6. Block Diagram of 8-Bit Timer/Event Counter TM52
Internal bus
8-bit timer compare
register 52 (CR52)
Selector
S
INTTM52
TI52/TO52/P70
Match
f
f
f
f
f
X
X
X
X
X
/22
/24
/25
/27
/29
8-bit timer/
INV
Q
TO52/TI52/P70
OVF
counter 52
(TM52)
R
f
X
/211
Clear
3
S
R
Level
inversion
Selector
TCL522 TCL521 TCL520
TCE52 TMC526 TMC524 LVS52 LVR52 TMC521 TOE52
Timer clock select
register 52 (TCL52)
8-bit timer mode control
register 52 (TMC52)
Internal bus
Figure 4-7. Watch Timer Block Diagram
Clear
f
f
X
X
/27
/28
f
W
5-bit prescaler
11-bit prescaler
f
W
29
f
W
f
W
f
W
f
W
f
W
f
W
f
W
24 25 26 27 28 210 211
Clear
INTWTN0
INTWTNI0
3
WTNM07 WTNM06 WTNM05 WTNM04 WTNM03 WTNM02 WTNM01 WTNM00
Watch timer mode
register 0 (WTNM0)
Internal bus
Remark fX: System clock oscillation frequency
fW: Watch timer clock frequency
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 4-8. Watchdog Timer Block Diagram
Divided
clock
select circuit
Clock input
control
INTWDT
RESET
Frequency
divider
f
/28
X
Output
control
circuit
circuit
RUN
Division mode
select circuit
3
WDT mode signal
OSTS2OSTS1OSTS0
Watchdog timer
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Oscillation
stabilization time
Watchdog timer mode
register (WDTM)
clock select register
(WDCS)
select register (OSTS)
Internal bus
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4.4 Clock Output/Buzzer Output Control Circuit
A clock output/buzzer output control circuit (CKU) is incorporated.
Clocks with the following frequencies can be output as clock output.
• 49.2 kHz/98.3 kHz/197 kHz/393 kHz/786 kHz/1.57 MHz/3.15 MHz/6.29 MHz (@ 6.29-MHz operation with
system clock)
Clocks with the following frequencies can be output as buzzer output.
• 768 Hz/1.54 kHz/3.07 kHz/6.14 kHz (@ 6.29-MHz operation with system clock)
Figure 4-9. Block Diagram of Clock Output/Buzzer Output Control Circuit CKU
f
X
Prescaler
8
4
f
X
/210 to f /213
X
BUZ/P23
PCL/P27
BCS0, BCS1
BZOE
Clock
f
X
to f
/27
X
control
circuit
CLOE
BZOE BCS1 BCS0 CLOE CCS2 CCS1 CCS0
Clock output
select register (CKS)
Internal bus
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4.5 A/D Converter
An A/D converter consisting of sixteen 8-bit resolution channels is incorporated.
The A/D converter has the following two functions.
• 8-bit resolution A/D conversion
• Power fail detection function
Figure 4-10. A/D Converter Block Diagram
Series resistor string
ANI0/P80
Sample & hold circuit
ANI1/P81
ANI2/P82
ANI3/P83
ANI4/P84
ANI5/P85
ANI6/P86
ANI7/P87
ANI8/P90
ANI9/P91
ANI10/P92
ANI11/P93
ANI12/P94
ANI13/P95
ANI14/P96
ANI15/P97
Voltage comparator
AVREF
(also used with analog
power supply)
Successive
approximation
register (SAR)
AVSS
Control
circuit
INTAD
A/D conversion result
register (ADCR3)
Internal bus
Figure 4-11. Block Diagram of Power Fail Detection Function
ANI0/P80
ANI1/P81
ANI2/P82
ANI3/P83
ANI4/P84
ANI5/P85
ANI6/P86
ANI7/P87
ANI8/P90
ANI9/P91
ANI10/P92
ANI11/P93
ANI12/P94
ANI13/P95
ANI14/P96
ANI15/P97
INTAD
Comparator
A/D converter
Power fail compare threshold
register 3 (PFT3)
Internal bus
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4.6 Serial Interfaces
Four serial interface channels are incorporated.
• Serial interface UART0
• Serial interfaces SIO30, SIO31
• Serial interface IIC0
(1) Serial interface UART0
The serial interface UART0 has the asynchronous serial interface (UART) mode.
• Asynchronous serial interface (UART) mode
This mode enables full-duplex operation wherein one byte of data is transmitted and received after the start
bit.
The on-chip dedicated UART baud rate generator enables communication using a wide range of selectable
baud rates.
In addition, a baud rate can also be defined by dividing the clock input to the ASCK0 pin.
The dedicated UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25
kbps).
Figure 4-12. Block Diagram of Serial Interface UART0
Internal bus
ASIM0
Receive
buffer
register 0
RXB0
TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0
ASIS0
Receive
shift
register 0
Transmit
shift
register 0
RX0
TXS0
RxD0/P24
TxD0/P25
PE0 FE0 OVE0
Receive
control
parity
Transmit
control
parity
INTSER0
INTST0
INTSR0
check
addition
P26/ASCK0
/22 to f /28
Baud rate
generator
fX
X
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
(2) Serial interfaces SIO30, SIO31
The serial interfaces SIO30 and SIO31 have the 3-wire serial I/O mode.
• 3-wire serial I/O mode (fixed as MSB first)
This is an 8-bit data transfer mode using three lines: serial clock line (SCK3n), serial output line (SO3n), and
serial input line (SI3n).
Since simultaneous transmit and receive operations are available in the 3-wire serial I/O mode, the processing
time for data transfer is reduced.
The first bit in 8-bit data in the serial transfer is fixed as MSB.
The 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clocked serial
interface, a display controller, etc.
Remark n = 0, 1
Figure 4-13. Block Diagram of Serial Interface SIO30
Internal bus
8
Serial I/O shift
register 30 (SIO30)
SI30/P30
SO30/P31
SCK30/P32
Serial
clock counter
Interrupt request
signal generator
INTCSI30
f
f
f
X
X
X
/24
/25
/27
Serial clock
control circuit
Selector
Figure 4-14. Block Diagram of Serial Interface SIO31
Internal bus
8
Serial I/O shift
register 31 (SIO31)
SI31/P20
SO31/P21
Serial
clock counter
Interrupt request
signal generator
SCK31/P22
INTCSI31
f
f
f
X
X
X
/24
/25
/27
Serial clock
control circuit
Selector
Preliminary Product Information U13920EJ1V0PM00
29
µPD780701Y, 780702Y
(3) Serial interface IIC0
The serial interface IIC0 has the I2C (Inter IC) bus mode (multimaster supported).
• I2C bus mode (multimaster supported)
This is an 8-bit data transfer mode between multiple devices using two lines: serial clock line (SCL0) and
serial data bus line (SDA0).
This mode complies with the I2C bus format, and can output “start condition”, “data”, and “stop condition”
during transmission via the serial data bus. These data are automatically detected by hardware during
reception.
Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the
serial data bus line are required.
Figure 4-15. Block Diagram of Serial Interface IIC0
Internal bus
IIC0 status register
(IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC0 control
register (IICC0)
Slave address
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
register 0 (SVA0)
SDA0/P71
Match
CLEAR
SET
Noise
elimination
circuit
signal
SO0
latch
IIC0 shift
register (IIC0)
D
CL01,
CL00
Data hold
time correction
circuit
Acknowledge
detection circuit
N-ch open-drain
output
Wake-up
control circuit
Acknowledge
detection circuit
Start condition
detection circuit
Stop condition
detection circuit
SCL0/P72
Interrupt request
signal generator
Noise
elimination
circuit
INTIIC0
Serial
clock counter
Serial clock wait
control circuit
Serial clock
control circuit
f
X
Prescaler
CLD0 DAD0 SMC0 DFC0 CL01 CL00
IIC0 transfer clock
select register (IICCL0)
Internal bus
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4.7 DCAN Controller (µPD780701Y only)
The µPD780701Y incorporates a DCAN (Direct storage Control Area Network) controller.
Table 4-3. DCAN Controller Functional Outline
Function
Details
CAN2.0-supported extended frame format (Bosch specification 2.0 part B)
Maximum of 390 kbps (@ 6.29 MHz)
Protocol
Baud rate
Bus line control
Clock
CMOS I/O for external transceiver
Selectable by register
Data storage
Capacity of buffer RAM for DCAN: 288 bytes
(if not using for DCAN, it can be used for normal RAM)
Messages received via a message identifier are stored in RAM.
Transmit message buffers: 2
Message configuration
Message number
Message sorting
Maximum of 16 receive messages, including 2 masks
Transmit channels: 2 channels
Can set a separate identifier for the 16 receive messages
Mask identifiers: 2
Can set a global mask for all messages
Transmit interrupt request: 1
Interrupts
Receive interrupt request: 1
Error interrupt request: 1
Time function
A time stamp function is available
Other functions
A separate transmit/receive error counter is available
A flag for checking the bus connection is available
A dedicated receive mode is available (use when detecting the baud rate on the bus)
Low power consumption mode Sleep mode (can be woken up by the DCAN bus)
Stop mode (cannot be woken up by the DCAN bus)
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 4-16. DCAN Controller Block Diagram (µPD780701Y only)
Memory
access
Receive message
Receive message
Receive message
Arbitration
Receive
message
Cycle steal
DMA control
CPU
Buffer RAM
for DCAN
SFR access
Memory
access engine
Interface
management
(including
global register)
Transmit buffer
Transmit
buffer
High-speed
RAM
DCAN
protocol
External bus
transceiver
Time signal
Timer
DCAN interface
CANL
CANH
The DCAN interface section processes all protocol operations by means of the DCAN protocol section hardware.
The memory access engine either fetches the DCAN protocol data transmitted from a specific RAM area and
transfers it to the DCAN protocol section, or compares and sorts the fetched data and then stores it in a predefined
RAM area.
The DCAN allows direct interfacing between the DCAN and the accessible CPU area, as well as between the CPU
and that area without any effect on the CPU. The DCAN section operates with the external bus transceiver that
converts transmit data line and receive data line to the electrical characteristics of DCAN bus.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
4.8 IEBus Controller (µPD780702Y only)
The µPD780702Y incorporates an IEBus controller. The functions of the IEBus interface are limited compared
with those of previous models (i.e., those incorporated in the µPD78098B Subseries).
Table 4-4 shows a comparison of the interfaces in the µPD78098B Subseries and the µPD780702Y.
Table 4-4. IEBus Interface Comparison (µPD78098B Subseries and µPD780702Y)
Item
Communication mode
Internal system clock
Internal buffer size
IEBus Incorporated in µPD78098B Subseries
Mode 0, mode 1, mode 2
IEBus Incorporated in µPD780702Y
Fixed at mode 1
fX = 6.291456 MHzNote
fX = 6.0 (6.29) MHz
Transmit buffers: 33 bytes (FIFO)
Receive buffers: 40 bytes (FIFO)
Up to 4 frames receivable
Transmit buffers: 1 byte
Receive buffers: 1 byte
CPU processing
Processing before start of communication (data
setting)
Processing before start of communication
(data setting)
Setting, controlling each communication status
Writing data to transmit buffers
Setting, controlling each communication
status
Data write processing in one-byte units
Data read processing in one-byte units
Transmission control of slave status, etc.
Reading data from receive buffers
Multiple-frame control, repeat master-
request processing
Hard processing
Bit processing (modem, error detection)
Field processing (generation/control)
Arbitration result detection
Bit processing (modem, error detection)
Field processing (generation/control)
Arbitration result detection
Parity processing (generation/error detection)
ACK/NACK automatic response
Parity processing (generation/error
detection)
ACK/NACK automatic response
Automatic retransmit-of-data processing
Automatic remaster processing
Automatic retransmit-of-data processing
Automatic transmission processing of slave
status, etc.
Multiple-frame reception processing
Note The µPD780702Y only supports an IEBus controller that operates at fX = 6.291456 MHz.
Remark fX: System clock frequency
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 4-17. IEBus Controller Block Diagram (µPD780702Y only)
CPU interface
8
12
12
12
8
8
8
8
8
8
8
8
Internal
registers
BCR0 (8)
UAR (12)
SAR (12)
PAR (12)
CDR (8)
DLR (8)
DR (8)
USR (8)
ISR (8)
SSR (8)
SCR (8)
CCR (8)
8
8
8
8
8
12
12
12
8
8
8
8
Internal bus
8
12
8
IRX0
ITX0
NF
MPX
12-bit latch
Comparator
PSR (8 bits)
Interrupt
control
circuit
INT request
TX/RX
Parity
Contention
detection
Interrupt control
generation/
error detection
MPX
ACK
generation
IEBus interface
Internal bus R/W
5
CLK
Bit processing
Field processing
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
The IEBus is broadly configured from the following 6 blocks.
• CPU interface
• Interrupt control
• Internal registers
• Bit processing
• Field processing
• IEBus interface
<CPU interface>
This is a control block whose purpose is to interface between the CPU (78K/0) and the IEBus main unit.
<Interrupt control>
This is a control block whose purpose is to pass on interrupt request signals from the IEBus main unit to the CPU.
<Internal registers>
This block sets the control registers that control the IEBus and the data of each field.
<Bit processing>
This block performs the bit timing generation and resolution, and is mainly configured from bit sequence ROM, an
8-bit preset timer, and a determiner.
<Field processing>
This block generates each field in the communication frame, and is mainly configured from field sequence ROM, a
4-bit down counter, and a determiner.
<IEBus interface>
This is the external driver/receiver interface block, and is mainly configured from a noise filter, a shift register, a
contention detector, a parity detector, a parity generation circuit, and an ACK/NACK generation circuit.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
5. INTERRUPT FUNCTIONS
A total of 30 interrupt sources are provided in the µPD780701Y, and a total of 29 interrupt sources are provided in
the µPD780702Y, divided into the following three types.
• Non-maskable:
• Maskable:
1
28 (µPD780701Y)
27 (µPD780702Y)
1
• Software:
Table 5-1. Interrupt Source List (1/2)
Basic
Default
PriorityNote 1
Interrupt Source
Trigger
Internal/
External
Vector
Table
Configuration
TypeNote 2
Interrupt Type
Non-maskable
Maskable
Name
Address
−
INTWDT
Watchdog timer overflow (with non-
maskable interrupt selected)
Internal
0004H
(A)
(B)
(C)
0
INTWDT
Watchdog timer overflow (with interval
timer selected)
1
2
INTP0
Pin input edge detection
External
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0024H
INTP1
3
INTP2
4
INTP3
5
INTP4
6
INTP5
7
INTP6
8
INTP7
9
INTSER0
INTSR0
INTST0
INTCSI30
INTCSI31
INTIIC0
INTCENote 3
INTCRNote 3
Occurrence of UART0 reception error
End of UART0 reception
End of UART0 transmission
End of SIO30 transfer
End of SIO31 transfer
End of IIC0 transfer
Internal
(B)
10
11
12
13
14
15
16
DCAN error
/
DCAN reception/
INTIE1Note 4
IEBus data access request
17
INTCTNote 3
INTIE2Note 4
/
DCAN transmission buffer/
IEBus communication error and
start/end of communication
0026H
18
19
INTWTNI0 Reference time interval signal from
watch timer
0028H
002AH
INTTM000 Generation of matching signal of TM00
and CR000 (with compare register
specified)
TI000 valid edge detection (with capture
register specified)
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest order and 28 is the lowest order.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 5-1.
3. µPD780701Y only
4. µPD780702Y only
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Table 5-1. Interrupt Source List (2/2)
Default
PriorityNote 1
Interrupt Source
Trigger
Internal/
External
Vector
Table
Basic
Interrupt Type
Maskable
Configuration
TypeNote 2
Name
Address
20
21
22
INTTM010 Generation of matching signal of TM00
and CR010 (with compare register
specified)
Internal
002CH
002EH
0030H
(B)
TI010 valid edge detection (with capture
register specified)
INTTM001 Generation of matching signal of TM01
and CR001 (with compare register
specified)
TI001 valid edge detection (with capture
register specified)
INTTM011 Generation of matching signal of TM01
and CR011 (with compare register
specified)
TI011 valid edge detection (with capture
register specified)
23
24
25
INTTM50
INTTM51
INTTM52
Generation of matching signal of TM50
and CR50
0032H
0034H
0036H
Generation of matching signal of TM51
and CR51
Generation of matching signal of TM52
and CR52
26
27
28
−
INTAD
INTWTN0
INTKR
BRK
End of conversion by A/D converter
Watch timer overflow
0038H
003AH
003CH
003EH
Port 4 falling edge detection
Execution of BRK instruction
External
(D)
(E)
Software
−
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest order and 28 is the lowest order.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 5-1.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 5-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
Interrupt
request
Priority
control circuit
address
generator
Standby
release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Priority
control circuit
Vector table
address generator
Interrupt
request
IF
Standby
release signal
(C) External maskable interrupt (INTP0 to INTP7)
Internal bus
External interrupt edge
enable register
(EGP, EGN)
MK
IE
PR
ISP
Priority
control circuit
Vector table
address generator
Edge
Interrupt
request
IF
detection
circuit
Standby
release signal
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
Figure 5-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (INTKR)
Internal bus
MK
IE
PR
ISP
Priority
control circuit
Vector table
address generator
Falling edge
detection
circuit
Interrupt
request
IF
Standby
release signal
(E) Software interrupt
Internal bus
Interrupt
request
Priority
control circuit
Vector table
address generator
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specification flag
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
6. STANDBY FUNCTION
The following two standby functions are available for further reduction of system current consumption.
• HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be
reduced by intermittent operation by combining this mode with the normal operation mode.
• STOP mode: In this mode, oscillation of the system clock is stopped. All the operations performed on the
system clock are suspended, resulting in extremely small current consumption.
Figure 6-1. Standby Function
System clock operation
Interrupt
request
HALT instruction
STOP instruction
Interrupt
request
HALT mode
(Clock supply to CPU halted,
oscillation maintained)
STOP mode
(System clock oscillation stopped)
7. RESET FUNCTION
The following two reset methods are available.
• External reset by RESET signal input
• Internal reset by watchdog timer runaway time detection
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
8. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd operand
[HL+byte]
[HL+B]
#byte
A
rNote
sfr
saddr
!addr16
PSW
MOV
[DE]
[HL]
$addr16
1
None
1st operand
A
[HL+C]
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
ROL
RORC
ROLC
ADDC ADDC
SUB
SUBC
AND
OR
SUB
SUBC
AND
OR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
INC
DEC
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL+byte]
[HL+B]
MOV
[HL+C]
X
C
MULU
DIVUW
Note Except r = A
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd operand
#word
ADDW
AX
rpNote
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
1st operand
AX
MOVW
XCHW
MOVW
MOVW
SUBW
CMPW
MOVW
rp
MOVWNote
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd operand
1st operand
A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
MOV1
$addr16
None
BT
SET1
CLR1
BF
BTCLR
sfr.bit
MOV1
MOV1
MOV1
MOV1
BT
SET1
CLR1
BF
BTCLR
saddr.bit
PSW.bit
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
[HL].bit
CY
BT
SET1
CLR1
BF
BTCLR
MOV1
MOV1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
SET1
CLR1
NOT1
AND1
OR1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
1st operand
Basic instruction
BR
CALL
BR
BR, BC, BNC
BZ, BNZ
Compound instruction
BT, BF
BTCLR, DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Conditions
Ratings
Unit
V
Power supply voltage
VDD = AVREF
−0.3 to +6.5
AVREF
AVSS
VI1
−0.3 to +0.3
V
V
Input voltage
P00 to P07, P20 to P27, P30 to P32, P34 to P36,
P40 to P47, P50 to P57, P64 to P67, P70 to P77,
P80 to P87, P90 to P97, CRXD, IRX0, X1, X2,
RESET
−0.3 to VDD + 0.3
VI2
VO
P33
N-ch open drain
−0.3 to +16
V
V
Output voltage
P00 to P07, P20 to P27, P30 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P90 to P97, CTXD, ITX0
−0.3 to VDD + 0.3
Analog input voltage
Output current, high
VAN
P80 to P87, P90 to P97
Analog input pin
AVSS − 0.3 to AVREF + 0.3
and −0.3 to VDD + 0.3
−10
V
IOH
Per pin for P00 to P07, P20 to P27, P30 to P32, P34
to P36, P40 to P47, P50 to P57, P64 to P67, P70,
P73 to P77, P80 to P87, P90 to P97, CRXD, IRX0
mA
Total for all pins
−30
mA
mA
Output current, low
IOLNote
Per pin for P00 to P07, P20 to P27, P30
to P32, P34 to P36, P40 to P47, P50 to
P57, P64 to P67, P70 to P77, P80 to
P87, P90 to P97, CTXD, ITX0
Peak
value
20
rms
10
30
mA
mA
mA
mA
mA
°C
value
P33
Peak
value
rms
15
value
Total for all pins
Peak
value
100
rms
60
value
Operating ambient
temperature
TA
−40 to +85
−65 to +150
Storage temperature
Tstg
°C
Note The rms value should be calculated as follows: [rms value] = [Peak value] × √ Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 3.5 to 5.5 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Crystal
Oscillation frequency
(fX)Note 1
6.29Note 2
MHz
IC
resonator
X2
R1
X1
Oscillation stabilization
timeNote 3
30
ms
C2
C1
Notes 1. Indicates only oscillator characteristics.
2. 6.29 = 6.291456 (MHz)
3. Time required to stabilize oscillation after reset or STOP mode release.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in
the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Preliminary Product Information U13920EJ1V0PM00
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µPD780701Y, 780702Y
DC Characteristics (TA = −40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
VIH1
Conditions
MIN.
TYP.
MAX.
VDD
Unit
V
Input
P21, P23, P25, P27, P31, P34, P40 to P47, P64 to P67,
P73, P80 to P87, P90 to P97
0.7VDD
voltage,
high
VIH2
P00 to P07, P20, P22, P24, P26, P30, P32, P35, P36,
P70 to P72, P74 to P77, CRXD, IRX0, RESET
0.8VDD
VDD
V
VIH3
VIH4
VIH5
VIL1
P50 to P57
2.3
VDD
15
V
V
V
V
P33
N-ch open drain
0.7VDD
X1, X2
V
DD
−
0.5
VDD
Input
P21, P23, P25, P27, P31, P34, P40 to P47, P64 to P67,
P73, P80 to P87, P90 to P97
0
0.3VDD
voltage, low
VIL2
P00 to P07, P20, P22, P24, P26, P30, P32, P35, P36,
P70 to P72, P74 to P77, CRXD, IRX0, RESET
0
0.2VDD
V
VIL3
VIL4
P50 to P57
0
0
0
−
0.75
0.3VDD
0.4
V
V
V
V
P33
N-ch open drain
VIL5
X1, X2
Output
voltage,
high
VOH1
IOH = −1 mA
P00 to P07, P20 to P27, P30 to
P32, P34 to P36, P40 to P47, P50
to P57, P64 to P67, P70, P73 to
P77, P80 to P87, P90 to P97,
CTXD, ITX0
V
DD
DD
1.0
0.5
VDD
VOH2
IOH = −100 µA
V
−
VDD
V
Output
VOL1
VOL2
VOL3
IOL = 15 mA
IOL = 1.6 mA
IOL = 1 mA
P33
0.4
2.0
0.4
1.0
V
V
V
voltage, low
P71, P72
P00 to P07, P20 to P27, P30 to
P32, P34 to P36, P40 to P47, P50
to P57, P64 to P67, P70, P73 to
P77, P80 to P87, P90 to P97,
CTXD, ITX0
VOL4
IOL = 100 µA
0.5
3
V
Input
ILIH1
VIN = VDD
P00 to P07, P20 to P27, P30 to
P32, P34 to P36, P40 to P47, P50
to P57, P64 to P67, P70 to P77,
P80 to P87, P90 to P97, CRXD,
IRX0, RESET
µA
leakage
current,
high
ILIH2
ILIH3
ILIL1
X1, X2
P33
20
80
−3
µA
µA
µA
VIN = 15 V
VIN = 0 V
Input
P00 to P07, P20 to P27, P30 to
P32, P34 to P36, P40 to P47, P50
to P57, P64 to P67, P80 to P87,
P90 to P97, CRXD, IRX0, RESET
leakage
current, low
ILIL2
ILIL3
X1, X2
−20
−3
µA
µA
P33 (except executing input
instructionNote
)
Note During input instruction execution, a low-level input leakage current of −200 µA (MAX.) flows only for 1 clock
(without wait).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Preliminary Product Information U13920EJ1V0PM00
46
µPD780701Y, 780702Y
DC Characteristics (TA = −40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
ILOH
Conditions
MIN.
TYP.
MAX.
3
Unit
Output leakage
current, high
VOUT = VDD
VOUT = 0 V
VIN = 0 V
P00 to P07, P20 to P27, P30 to P36, P40
to P47, P50 to P57, P64 to P67, P70 to
P77, P80 to P87, P90 to P97, CTXD, ITX0
µA
Output leakage
current, low
ILOL
P00 to P07, P20 to P27, P30 to P36, P40
to P47, P50 to P57, P64 to P67, P70 to
P77, P80 to P87, P90 to P97, CTXD, ITX0
−3
µA
kΩ
Software pull-up
resistor
R1
P00 to P07, P20 to P27, P30 to P32, P34
to P36, P40 to P47, P50 to P57, P64 to
P67, P70, P73 to P77
15
30
90
Power supply
currentNote 1
IDD1
IDD2
IDD3
6.29-MHz crystal oscillation operating mode
6.29-MHz crystal oscillation HALT modeNote 2
STOP mode
4.0
500
0.1
20
1000
30
mA
µA
µA
Notes 1. Refers to the current flowing to the VDD1 pin. The current flowing to the A/D converter and on-chip pull-up
resistor is not included.
2. Low-speed mode operation (when processor clock control register (PCC) is set to 04H). The current for
peripheral circuit operation is not included.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Preliminary Product Information U13920EJ1V0PM00
47
µPD780701Y, 780702Y
AC Characteristics
(1) Basic operation (TA = −40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
TCY
Conditions
MIN.
TYP.
MAX.
5.09
Unit
Cycle time (Min.
instruction execution
time)
Operating with system clock (fX = 6.291456 MHz)
0.318
µs
TI000, TI010, TI001,
TI011 input high-/low-
level width
tTIH0
tTIL0
4/fsam +
0.25Note
µs
TI50, TI51, TI52 input
frequency
fTI5
2
MHz
ns
TI50, TI51, TI52 input
high-/low-level width
tTIH5
tTIL5
tINTH
tINTL
tRSL
200
10
Interrupt request input
high-/low-level width
INTP0 to INTP7, P40 to P47
µs
µs
RESET low-level width
10
Note Selection of fsam = fX/2, fX/4, fX/64 is possible with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode register
0n (PRM0n). However, if the TI00n valid edge is selected as the count clock, the value becomes fsam = fX/8 (n
= 0, 1).
T
CY vs VDD (At system clock operation)
10.0
5.09
5.0
2.0
1.0
µ
Guaranteed
operation
range
0.5
0.318
0.1
3.5
5.5
0
1.0
2.0
3.0
4.0
5.0
6.0
Power supply voltage VDD [V]
Preliminary Product Information U13920EJ1V0PM00
48
µPD780701Y, 780702Y
(2) Serial interface (TA = −40 to +85°C, VDD = 3.5 to 5.5 V)
(a) 3-wire serial I/O mode (SCK30 ... Internal clock output)
Parameter
Symbol
tKCY1
tKH1
Conditions
MIN.
1.9
TYP.
MAX.
Unit
µs
SCK30 cycle time
SCK30 high-/low-level
width
tKCY1/
ns
2 − 50
tKL1
SI30 setup time (to
tSIK1
100
ns
ns
ns
SCK30↑)
SI30 hold time (from
tKSI1
400
SCK30↑)
SO30 output delay
tKSO1
C = 100 pFNote
300
time from SCK30↓
Note C is the load capacitance of the SCK30 and SO30 output lines.
(b) 3-wire serial I/O mode (SCK30 ... External clock input)
Parameter
Symbol
tKCY2
tKH2
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
SCK30 cycle time
SCK30 high-/low-level
width
ns
tKL2
SI30 setup time (to
tSIK2
100
400
ns
ns
ns
SCK30↑)
SI30 hold time (from
tKSI2
SCK30↑)
SO30 output delay
tKSO2
C = 100 pFNote
300
time from SCK30↓
Note C is the load capacitance of the SO30 output line.
Preliminary Product Information U13920EJ1V0PM00
49
µPD780701Y, 780702Y
(c) 3-wire serial I/O mode (SCK31 ... Internal clock output)
Parameter
Symbol
tKCY3
tKH3
Conditions
MIN.
1.9
TYP.
MAX.
Unit
µs
SCK31 cycle time
SCK31 high-/low-level
width
tKCY1/
2 − 50
100
ns
tKL3
SI31 setup time (to
tSIK3
ns
SCK31↑)
SI31 hold time (from
tKSI3
400
ns
ns
SCK31↑)
SO31 output delay
tKSO3
C = 100 pFNote
300
time from SCK31↓
Note C is the load capacitance of the SCK31 and SO31 output lines.
(d) 3-wire serial I/O mode (SCK31 ... External clock input)
Parameter
Symbol
tKCY4
tKH4
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
SCK31 cycle time
SCK31 high-/low-level
width
ns
tKL4
SI31 setup time (to
tSIK4
100
400
ns
SCK31↑)
SI31 hold time (from
tKSI4
ns
ns
SCK31↑)
SO31 output delay
tKSO4
C = 100 pFNote
300
time from SCK31↓
Note C is the load capacitance of the SO31 output line.
Preliminary Product Information U13920EJ1V0PM00
50
µPD780701Y, 780702Y
(e) UART mode (Dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
TYP.
MAX.
Unit
bps
38836
(f) UART mode (External clock input)
Parameter
Symbol
tKCY3
Conditions
MIN.
800
400
MAX.
Unit
ns
ASCK0 cycle time
ASCK0 high-/low-level
width
tKH3, tKL3
ns
Transfer rate
39063
bps
(g) I2C bus mode
Parameter
Symbol
Standard Mode
High-speed Mode
Unit
MIN.
0
MAX.
MIN.
0
MAX.
SCL0 clock frequency
fSCL
tBUF
tHD:STA
tLOW
100
−
400
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
pF
Bus free time (between stop and start conditions)
Hold timeNote 1
4.7
4.0
4.7
4.0
4.7
5.0
0Note 2
250
−
1.3
0.6
1.3
0.6
0.6
−
0Note 2
100Note 4
−
−
−
−
SCL0 clock low-level width
SCL0 clock high-level width
Start/restart condition setup time
Data hold time CBUS compatible master
I2C bus
−
−
tHIGH
−
−
tSU:STA
tHD:DAT
−
−
−
−
−
0.9Note 3
Data setup time
tSU:DAT
tR
−
−
SDA0 and SCL0 signal rise time
SDA0 and SCL0 signal fall time
Stop condition setup time
1000
300
−
300
300
−
tF
−
−
tSU:STO
tSP
4.0
−
0.6
0
Spike pulse width controlled by input filter
Capacitive load of each bus line
−
50
400
Cb
−
400
−
Notes 1. On start condition, the first clock pulse is generated after this period.
2. To fulfill undefined area of the SCL0 falling edge, it is necessary for the device to provide internally SDA0
signal (on VIHmin. of SCL0 signal) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT
needs to be fulfilled.
4. The high-speed mode I2C bus is available in the standard mode I2C bus system. At this time, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT =
1000 + 250 = 1250 ns by standard mode I2C bus specification).
Preliminary Product Information U13920EJ1V0PM00
51
µPD780701Y, 780702Y
AC Timing Test Points (excluding X1 input)
0.8VDD
0.2VDD
0.8VDD
Test points
0.2VDD
Clock Timing
1/fX
t
XL
t
XH
V
V
IH5 (MIN.)
IL5 (MAX.)
X1 Input
TI Timing
tTIL0
t
TIH0
TI000, TI010, TI001, TI011
1/fTI5
t
TIL5
t
TIH5
TI50, TI51, TI52
Preliminary Product Information U13920EJ1V0PM00
52
µPD780701Y, 780702Y
Serial Transfer Timing
3-wire serial I/O mode:
tKCYn
t
KLn
t
KHn
SCK30, SCK31
t
SIKn
t
KSIn
SI30, SI31
Input data
t
KSOn
Output data
SO30, SO31
n = 1 to 4
UART mode (external clock input):
t
KCY5
t
KL5
t
KH5
ASCK0
I2C bus mode:
t
LOW
t
R
SCL0
SDA0
t
F
t
HD : DAT
t
HIGH
t
SU : STA
t
HD : STA
t
SP
t
SU : STO
t
SU : DAT
t
HD : STA
t
BUF
Start
condition
Restart
condition
Stop
condition
Stop
condition
Preliminary Product Information U13920EJ1V0PM00
53
µPD780701Y, 780702Y
IEBus0 Controller Characteristics (TA = −40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
fS
Conditions
MIN.
TYP.
6.29
MAX.
Unit
IEBus system clock
frequency
Fixed at mode 1
C = 50 pFNote
MHz
Driver delay time (Bus
line from ITX0 output)
tDTX
1.5
0.7
µs
µs
The µPC2590 is used as a driver/receiver
The µPC2590 is used as a driver/receiver
Receiver delay time
(IRX0 input from bus
line)
tDRX
Propagation delay
time on bus
tDBUS
The µPC2590 is used as a driver/receiver
0.85
µs
Note C is the load capacitance of the ITX0 output line.
Remarks 1. Although the standard system clock frequency for the IEBus is 6.0 MHz, the µPD780702Y guarantees
normal operation of the IEBus controller at 6.29 MHz.
2. fS: IEBus controller system clock frequency
A/D Converter Characteristics (TA = −40 to +85°C, VDD = AVREF = 3.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
%
Resolution
Overall errorNote
±0.6
100
Conversion time
Analog input voltage
AVREF resistance
tCONV
VIAN
14
µs
V
AVSS
T.B.D
AVREF
T.B.D
RAIREF
28
kΩ
Note Excludes quantization error (±0.2%). It is indicated as a ratio to the full-scale value.
Preliminary Product Information U13920EJ1V0PM00
54
µPD780701Y, 780702Y
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter
Symbol
VDDDR
Conditions
MIN.
2.0
TYP.
MAX.
5.5
Unit
V
Data retention power
supply voltage
Data retention power
supply current
IDDDR
VDDDR = 2.0 V
0.1
10
µA
Release signal set time
tSREL
tWAIT
0
µs
ms
ms
Oscillation stabilization
wait time
Release by RESET
217/fX
Release by interrupt request
Note
Note Selection of 212/fX, 214/fX, 219/fX, and 221/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Data Retention Timing (STOP mode release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
t
SREL
STOP instruction
execution
RESET
t
WAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
t
SREL
STOP instruction
execution
Standby release signal
(interrupt request)
t
WAIT
Preliminary Product Information U13920EJ1V0PM00
55
µPD780701Y, 780702Y
Interrupt Request Input Timing
t
INTL
t
INTH
INTP0 to INTP7
RESET Input Timing
t
RSL
RESET
Preliminary Product Information U13920EJ1V0PM00
56
µPD780701Y, 780702Y
10. PACKAGE DRAWING
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
M
G
P
H
I
K
L
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.20±0.20
14.00±0.20
0.677±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
17.20±0.20
–0.008
0.677±0.008
F
0.825
0.825
0.032
0.032
G
+0.002
0.013
H
0.32±0.06
–0.003
I
0.13
0.005
J
K
0.65 (T.P.)
1.60±0.20
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.80±0.20
–0.008
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.10
0.004
1.40±0.10
0.125±0.075
0.055±0.004
0.005±0.003
+7°
3°
+7°
3°
R
S
–3°
–3°
1.70 MAX.
0.067 MAX.
P80GC-65-8BT
Preliminary Product Information U13920EJ1V0PM00
57
µPD780701Y, 780702Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780701Y Subseries. Also
refer to (5) Cautions on Using Development Tools.
(1) Language Processing Software
RA78K/0
Assembler package common to 78K/0 Series
C compiler package common to 78K/0 Series
Device file for µPD780701Y Subseries
CC78K/0
DF780701Note
CC78K/0-L
C compiler library source file common to 78K/0 Series
Note Under development
(2) Flash Memory Writing Tools
Flashpro II (Part No. FL-
PR2), Flashpro III (Part
No. FL-PR3, PG-FP3)
FA-80GC
Dedicated flash programmer for microcomputers incorporating flash memory
Adapter for writing to flash memory for use in an 80-pin plastic QFP (GC-8BT type).
An adjusting connection to the target product is necessary.
Flashpro II controller,
Flashpro III controller
Program that is controlled from a PC and comes together with Flashpro II and Flashpro III. It operates
in environments such as WindowsTM 95.
(3) Debugging Tools
• When IE-78K0-NS in-circuit emulator is used
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
IE-70000-98-IF-C
Power supply unit for IE-78K0-NS
Interface adapter necessary when using PC-9800 series PC (except notebook type) as host machine
(C bus supported)
IE-70000-CD-IF-A
IE-70000-PC-IF-C
PC card and interface cable necessary when using notebook PC as host machine (PCMCIA socket
supported)
Interface adapter necessary when using IBM PC/ATTM compatible as host machine (ISA bus
supported)
IE-70000-PCI-IF
IE-780701-NS-EM1Note
NP-80GC
Adapter necessary when using personal computer incorporating PCI bus as host machine
Emulation board to emulate µPD780701Y Subseries
Emulation probe for 80-pin plastic QFP (GC-8BT type)
EV-9200GC-80
Conversion socket to connect the NP-80GC and a target system board on which an 80-pin plastic QFP
(GC-8BT type) can be mounted
ID78K0-NS
Integrated debugger for IE-78K0-NS
System simulator common to 78K/0 Series
Device file for µPD780701Y Subseries
SM78K0
DF780701Note
Note Under development
Preliminary Product Information U13920EJ1V0PM00
58
µPD780701Y, 780702Y
• When IE-78001-R-A in-circuit emulator is used
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Interface adapter necessary when using PC-9800 series PC (except notebook type) as host
machine (C bus supported)
IE-70000-PC-IF-C
Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus
supported)
IE-70000-PCI-IF
IE-78000-R-SV3
IE-780701-NS-EM1Note
IE-78K0-R-EX1
EP-78230GC-R
EV-9200GC-80
Adapter necessary when using personal computer incorporating PCI bus as host machine
Interface adapter and cable necessary when using EWS as host machine
Emulation board to emulate µPD780701Y Subseries
Emulation probe conversion board necessary when using IE-780701-NS-EM1 on IE-78001-R-A
Emulation probe for 80-pin plastic QFP (GC-8BT type)
Conversion socket to connect the EP-78230GC-R and a target system board on which an 80-pin
plastic QFP (GC-8BT type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
System simulator common to 78K/0 Series
Device file for µPD780701Y Subseries
SM78K0
DF780701Note
Note Under development
(4) Real-time OS
RX78K/0
MX78K0
Real-time OS for 78K/0 Series
OS for 78K/0 Series
(5) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780701.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and DF780701.
• The FL-PR2, FL-PR3, FA-80GC, and NP-80GC are products made by Naitou Densei Machidaseisakusho Co.,
Ltd. (TEL +81-44-822-3813). Contact an NEC distributor regarding the purchase of these products.
• For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
• The host machine and OS suitable for each software are as follows:
Host Machine
[OS]
PC
EWS
PC-9800 series [WindowsTM]
IBM PC/AT and compatibles
[Japanese/English Windows]
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
NEWSTM (RISC) [NEWS-OSTM]
Software
RA78K/0
CC78K/0
ID78K0-NS
ID78K0
Note
√
√
√
−
√
−
√
√
Note
√
√
√
√
SM78K0
RX78K/0
MX78K0
Note
√
Note
√
Note DOS-based software
Preliminary Product Information U13920EJ1V0PM00
59
µPD780701Y, 780702Y
APPENDIX B. RELATED DOCUMENTS
• Documents Related to Devices
Document Name
Document No.
English
Under preparation
This document
U13563E
Japanese
U13781J
µPD780701Y Subseries User’s Manual
µPD780701Y, 780702Y Preliminary Product Information
µPD78F0701Y Preliminary Product Information
78K/0 Series User’s Manual Instructions
U13920J
U13563J
U12326J
U12326E
• Documents Related to Development Tools (User’s Manuals)
Document Name
Document No.
Japanese
English
U11802E
U11801E
RA78K0 Assembler Package
Operation
Language
U11802J
U11801J
Structured Assembly Language U11789E
EEU-1402
U11789J
RA78K Series Structured Assembler Preprocessor
CC78K0 C Compiler
U12323J
Operation
U11517E
U11517J
Language
U11518E
U11518J
CC78K/0 C Compiler Application Note
IE-78K0-NS
Programming Know-How
U13034E
U13034J
To be prepared
To be prepared
To be prepared
To be prepared
EEU-1515
To be prepared
To be prepared
To be prepared
To be prepared
EEU-985
IE-78001-R-A
IE-78K0-R-EX1
IE-780701-NS-EM1
EP-780230
SM78K0 System Simulator Windows Based
SM78K Series System Simulator
Reference
U10181E
U10181J
External Part User Open
Interface Specifications
U10092E
U10092J
ID78K0-NS Integrated Debugger Windows Based
ID78K0 Integrated Debugger EWS Based
ID78K0 Integrated Debugger Windows Based
ID78K0 Integrated Debugger PC Based
Reference
Reference
Guide
U12900E
−
U12900J
U11151J
U11649J
U11539J
U11649E
U11539E
Reference
Preliminary Product Information U13920EJ1V0PM00
60
µPD780701Y, 780702Y
• Documents Related to Embedded Software (User’s Manuals)
Document Name
Document No.
English
U11537E
Japanese
U11537J
78K/0 Series Real-Time OS
Fundamental
Installation
U11536E
U12257E
U11536J
U12257J
78K/0 Series OS MX78K0
Fundamental
• Other Related Documents
Document Name
Document No.
Japanese
English
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
Semiconductor Device Mounting Technology Manual
X13769X
C10535E
C11531E
C10983E
C11892E
C10535J
C11531J
C10983J
C11892J
U11416J
Quality Grades on NEC Semiconductor Devices
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Guide to Microcomputer-Related Products by Third Party
−
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Preliminary Product Information U13920EJ1V0PM00
61
µPD780701Y, 780702Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by
Philips.
FIP, IEBus, and Inter Equipment Bus are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
Preliminary Product Information U13920EJ1V0PM00
62
µPD780701Y, 780702Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Preliminary Product Information U13920EJ1V0PM00
63
µPD780701Y, 780702Y
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
相关型号：
UPD78070AGC-8EU
8-BIT, MROM, 5MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, FINE PITCH, PLASTIC, LQFP-100
RENESAS
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