UPD78F9842GB-8ES-A_技术文档

User’s Manual

µPD789842 Subseries

8-Bit Single-Chip Microcontrollers

µPD789841

µPD789842

µPD78F9842

Document No. U13776EJ3V1UD00 (3rd edition)

Date Published August 2005 N CP(K)

©

Printed in Japan

[MEMO]

2

User’s Manual U13776EJ3V1UD

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

1

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is

fixed, and also in the transition period when the input level passes through the area between V^IL(MAX)

and V^IH(MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor

GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins

must be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

3

User’s Manual U13776EJ3V1UD

FIP and EEPROM are trademarks of NEC Electronics Corporation.

Windows and Windows NT are trademarks or registered trademarks of Microsoft Corporation in the United

States and in other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

•

The information in this document is current as of August, 2005. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

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•

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Descriptions of circuits, software and other related information in this document are provided for illustrative

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•

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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

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determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

4

User’s Manual U13776EJ3V1UD

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

[GLOBAL SUPPORT]

http://www.necel.com/en/support/support.html

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

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Santa Clara, California

Tel: 408-588-6000

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Tel: 0211-65030

800-366-9782

•

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United Kingdom Branch

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Tel: 01908-691-133

J05.6

5

User’s Manual U13776EJ3V1UD

INTRODUCTION

Readers

This manual is intended for user engineers who wish to understand the functions of

the µPD789842 Subseries to design and develop its application systems and

programs.

• µPD789842 Subseries: µPD789841, µPD789842, and µPD78F9842

Purpose

This manual is intended to give users an understanding of the functions described in

the Organization below.

Organization

Two manuals are available for the

µPD789842 Subseries: this manual and the

Instruction Manual (common to the 78K/0S Series).

µPD789842 Subseries

User's Manual

78K/0S Series Instruction

User's Manual

(This manual)

• Pin functions

• CPU function

• Internal block functions

• Interrupts

• Instruction set

• Instruction description

• Other internal peripheral functions

• Electrical specifications

How to Read This Manual

It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

To understand the overall functions of the µPD789842 Subseries

→ Read this manual in the order of the CONTENTS. The mark

revised points.

shows major

How to read register formats

→ The name of a bit whose number is enclosed with < > is reserved in the

assembler and is defined in the C compiler by the header file sfrbit.h.

To learn the detailed functions of a register whose register name is known

→ See APPENDIX C.

To learn the details of the instruction functions of the 78K/0S Series

→ Refer to 78K/0S Series Instruction User's Manual (U11047E) available

separately

To learn the electrical specifications of the µPD789842 Subseries

→ See CHAPTER 19 ELECTRICAL SPECIFICATIONS.

6

User’s Manual U13776EJ3V1UD

Conventions

Data significance:

Active low representation:

Note:

Higher digits on the left and lower digits on the right

××× (Overscore over pin or signal name)

Footnote for item marked with Note in the text

Information requiring particular attention

Supplementary information

Caution:

Remark:

Numerical representation:

Binary ... ×××× or ××××B

Decimal ... ××××

Hexadecimal ... ××××H

Other Related Documents

Document Name

Document No.

X13769X

Note

SEMICONDUCTOR SELECTION GUIDE -Products and Packages-

Semiconductor Device Mount Manual

Quality Grades on NEC Semiconductor Devices

C11531E

C10983E

C11892E

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

8

User’s Manual U13776EJ3V1UD

CONTENTS

CHAPTER 1 GENERAL...........................................................................................................................14

1.1 Features ......................................................................................................................................14

1.2 Applications................................................................................................................................14

1.3 Ordering Information .................................................................................................................14

1.4 Pin Configuration (Top View)....................................................................................................15

1.5 78K/0S Series Lineup.................................................................................................................16

1.6 Block Diagram ............................................................................................................................19

1.7 Outline of Functions ..................................................................................................................20

CHAPTER 2 PIN FUNCTIONS ...............................................................................................................21

2.1 Pin Function List ........................................................................................................................21

2.2 Description of Pin Functions ....................................................................................................23

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

P00 to P07 (Port 0)........................................................................................................................23

P10 to P17 (Port 1)........................................................................................................................23

P20 to P25 (Port 2)........................................................................................................................23

P60 to P67 (Port 6)........................................................................................................................24

TO70 to TO75................................................................................................................................24

RESET...........................................................................................................................................24

X1, X2............................................................................................................................................24

AVDD ..............................................................................................................................................24

AVSS...............................................................................................................................................24

2.2.10 VDD.................................................................................................................................................24

2.2.11 VSS .................................................................................................................................................24

2.2.12 VPP (µPD78F9842 only).................................................................................................................24

2.2.13 IC...................................................................................................................................................25

2.3 Pin I/O Circuits and Handling of Unused Pins ........................................................................26

CHAPTER 3 CPU ARCHITECTURE......................................................................................................28

3.1 Memory Space............................................................................................................................28

3.1.1

3.1.2

3.1.3

3.1.4

Internal program memory space....................................................................................................31

Internal data memory (internal high-speed RAM) space................................................................32

Special function register (SFR) area..............................................................................................32

Data memory addressing...............................................................................................................32

3.2 Processor Registers ..................................................................................................................35

3.2.1

3.2.2

3.2.3

Control registers ............................................................................................................................35

General-purpose registers .............................................................................................................39

Special-function registers (SFRs) ..................................................................................................40

3.3 Instruction Address Addressing ..............................................................................................43

3.3.1

3.3.2

3.3.3

Relative addressing .......................................................................................................................43

Immediate addressing....................................................................................................................44

Table indirect addressing...............................................................................................................45

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User’s Manual U13776EJ3V1UD

3.3.4

Register addressing.......................................................................................................................45

3.4 Operand Address Addressing..................................................................................................46

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

Direct addressing...........................................................................................................................46

Short direct addressing..................................................................................................................47

Special-function register (SFR) addressing ...................................................................................48

Register addressing.......................................................................................................................49

Register indirect addressing ..........................................................................................................50

Based addressing..........................................................................................................................51

Stack addressing ...........................................................................................................................52

CHAPTER 4 PORT FUNCTIONS...........................................................................................................53

4.1 Port Functions............................................................................................................................53

4.2 Port Configuration .....................................................................................................................54

4.2.1

4.2.2

4.2.3

4.2.4

Port 0.............................................................................................................................................54

Port 1.............................................................................................................................................55

Port 2.............................................................................................................................................56

Port 6.............................................................................................................................................58

4.3 Port Function Control Registers ..............................................................................................59

4.4 Operation of Port Functions .....................................................................................................62

4.4.1

4.4.2

4.4.3

Writing to I/O port...........................................................................................................................62

Reading from I/O port ....................................................................................................................62

Arithmetic operation of I/O port......................................................................................................62

CHAPTER 5 CLOCK GENERATOR ......................................................................................................63

5.1 Clock Generator Functions.......................................................................................................63

5.2 Clock Generator Configuration ................................................................................................63

5.3 Register Controlling Clock Generator .....................................................................................64

5.4 System Clock Oscillator............................................................................................................65

5.4.1

5.4.2

System clock oscillator ..................................................................................................................65

Divider ...........................................................................................................................................67

5.5 Clock Generator Operation.......................................................................................................68

5.6 Changing Setting of CPU Clock ...............................................................................................69

5.6.1

5.6.2

Time required for switching CPU clock..........................................................................................69

Switching CPU clock......................................................................................................................69

CHAPTER 6 10-BIT INVERTER CONTROL TIMER............................................................................70

6.1 10-Bit Inverter Control Timer Functions..................................................................................70

6.2 10-Bit Inverter Control Timer Configuration ...........................................................................70

6.3 Registers Controlling 10-Bit Inverter Control Timer ..............................................................74

6.4 10-Bit Inverter Control Timer Operation..................................................................................78

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82 ................................................................84

7.1 Functions of 8-Bit Timer/Event Counters 80, 81, 82...............................................................84

7.2 Configuration of 8-Bit Timer/Event Counters 80, 81, 82 ........................................................85

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User’s Manual U13776EJ3V1UD

7.3 Registers Controlling 8-Bit Timer/Event Counters 80, 81, 82................................................88

7.4 Operation of 8-Bit Timer/Event Counters 80, 81, 82...............................................................92

7.4.1

7.4.2

7.4.3

Operation as interval timer.............................................................................................................92

Operation as external event counter..............................................................................................94

Operation as square-wave output..................................................................................................95

7.5 Notes on Using 8-Bit Timer/Event Counters 80, 81, 82..........................................................97

CHAPTER 8 WATCH TIMER..................................................................................................................99

8.1 Watch Timer Functions .............................................................................................................99

8.2 Watch Timer Configuration.....................................................................................................100

8.3 Register Controlling Watch Timer..........................................................................................101

8.4 Watch Timer Operation............................................................................................................102

8.4.1

8.4.2

Operation as watch timer.............................................................................................................102

Operation as interval timer...........................................................................................................102

CHAPTER 9 WATCHDOG TIMER .......................................................................................................104

9.1 Watchdog Timer Functions.....................................................................................................104

9.2 Watchdog Timer Configuration ..............................................................................................105

9.3 Watchdog Timer Control Registers........................................................................................106

9.4 Watchdog Timer Operation.....................................................................................................108

9.4.1

9.4.2

Operation as watchdog timer.......................................................................................................108

Operation as interval timer...........................................................................................................109

CHAPTER 10 A/D CONVERTER .........................................................................................................110

10.1 A/D Converter Functions.........................................................................................................110

10.2 A/D Converter Configuration ..................................................................................................110

10.3 Registers Controlling A/D Converter .....................................................................................113

10.4 A/D Converter Operation.........................................................................................................115

10.4.1 Basic operation of A/D converter .................................................................................................115

10.4.2 Input voltage and conversion result .............................................................................................116

10.4.3 Operation mode of A/D converter ................................................................................................118

10.5 Notes on Using A/D Converter ...............................................................................................119

CHAPTER 11 SERIAL INTERFACE ....................................................................................................123

11.1 Serial Interface Functions .......................................................................................................123

11.2 Serial Interface Configuration.................................................................................................124

11.3 Registers Controlling Serial Interface....................................................................................125

11.4 Serial Interface Operation .......................................................................................................129

11.4.1 Operation stop mode ...................................................................................................................129

11.4.2 Asynchronous serial interface (UART) mode...............................................................................130

CHAPTER 12 MULTIPLIER...................................................................................................................141

12.1 Multiplier Function ...................................................................................................................141

12.2 Multiplier Configuration...........................................................................................................141

12.3 Register Controlling Multiplier................................................................................................143

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User’s Manual U13776EJ3V1UD

CHAPTER 13 SWAPPING (SWAP) .....................................................................................................144

13.1 SWAP Function ........................................................................................................................144

13.2 SWAP Configuration................................................................................................................144

CHAPTER 14 INTERRUPT FUNCTIONS ............................................................................................146

14.1 Interrupt Function Types.........................................................................................................146

14.2 Interrupt Sources and Configuration.....................................................................................147

14.3 Registers Controlling Interrupt Function ..............................................................................149

14.4 Interrupt Servicing Operation.................................................................................................154

14.4.1 Non-maskable interrupt request acknowledgment.......................................................................154

14.4.2 Maskable interrupt request acknowledgment...............................................................................156

14.4.3 Multiple interrupt servicing ...........................................................................................................159

14.4.4 Interrupt request pending.............................................................................................................160

CHAPTER 15 STANDBY FUNCTION..................................................................................................161

15.1 Standby Function and Configuration.....................................................................................161

15.1.1 Standby function..........................................................................................................................161

15.1.2 Standby function control register .................................................................................................162

15.2 Operation of Standby Function ..............................................................................................163

15.2.1 HALT mode .................................................................................................................................163

15.2.2 STOP mode.................................................................................................................................166

CHAPTER 16 RESET FUNCTION .......................................................................................................169

CHAPTER 17 µPD78F9842...................................................................................................................173

17.1 Flash Memory Characteristics................................................................................................174

17.1.1 Programming environment...........................................................................................................174

17.1.2 Communication mode..................................................................................................................175

17.1.3 On-board pin connections............................................................................................................178

17.1.4 Connection of adapter for flash writing ........................................................................................181

CHAPTER 18 INSTRUCTION SET ......................................................................................................183

18.1 Operation ..................................................................................................................................183

18.1.1 Operand identifiers and description methods...............................................................................183

18.1.2 Description of "Operation" column...............................................................................................184

18.1.3 Description of flag operation column............................................................................................184

18.2 Operation List...........................................................................................................................185

18.3 Instructions Listed by Addressing Type ...............................................................................190

CHAPTER 19 ELECTRICAL SPECIFICATIONS.................................................................................193

CHAPTER 20 PACKAGE DRAWINGS................................................................................................201

CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS...........................................................203

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User’s Manual U13776EJ3V1UD

APPENDIX A DEVELOPMENT TOOLS...............................................................................................204

A.1 Software Package ....................................................................................................................206

A.2 Language Processing Software .............................................................................................206

A.3 Control Software ......................................................................................................................207

A.4 Flash Memory Writing Tools...................................................................................................208

A.5 Debugging Tools (Hardware)..................................................................................................208

A.6 Debugging Tools (Software) ...................................................................................................209

APPENDIX B NOTES ON TARGET SYSTEM DESIGN...................................................................210

APPENDIX C REGISTER INDEX .........................................................................................................212

C.1 Register Name Index (Alphabetic Order)...............................................................................212

C.2 Register Symbol Index (Alphabetic Order)............................................................................214

APPENDIX D REVISION HISTORY .....................................................................................................216

D.1 Major Revisions in This Edition..............................................................................................216

D.2 Revisions up to Previous Edition...........................................................................................217

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User’s Manual U13776EJ3V1UD

CHAPTER 1 GENERAL

1.1 Features

• ROM and RAM capacity

Item

Program Memory

(ROM/Flash Memory)

Data Memory

(High-Speed RAM)

Product Name

µPD789841

µPD789842

µPD78F9842

8 KB

256 bytes

16 KB

• Minimum instruction execution time changeable from high-speed (0.24 µs) to low-speed (0.96 µs) (System clock

8.38 MHz operation)

• I/O port: 30 lines

• Serial interface (UART00): 1 channel

• Timer: 6 channels

•

10-bit inverter control timer: 1 channel

8-bit timer/event counter:

8-bit timer counter:

Watch timer:

2 channels

1 channel

Watchdog timer:

• 8-bit resolution A/D converter: 8 channels

• Multiplier: 10 bits × 10 bits = 20 bits

• SWAP: The contents of the higher four bits of an 8-bit register can be exchanged with the lower four bits

• Vectored interrupt sources: 15

• Supply voltage: V^DD= 4.0 to 5.5 V

1.2 Applications

Inverter-driven air conditioners etc.

1.3 Ordering Information

Part Number

Package

Internal ROM

Mask ROM

µPD789841GB-×××-3BS-MTX

µPD789841GB-×××-8ES

µPD789841GB-×××-8ES-A

µPD789842GB-×××-3BS-MTX

µPD789842GB-×××-8ES

µPD789842GB-×××-8ES-A

µPD78F9842GB-3BS-MTX

µPD78F9842GB-8ES

44-pin plastic QFP (10 × 10)

44-pin plastic LQFP (10 × 10)

44-pin plastic QFP (10 × 10)

44-pin plastic LQFP (10 × 10)

44-pin plastic QFP (10 × 10)

44-pin plastic LQFP (10 × 10)

Mask ROM

Flash memory

µPD78F9842GB-8ES-A

Remarks 1. ××× indicates ROM code suffix.

2. Products that have the part numbers suffixed by "-A" are lead-free products.

14

User’s Manual U13776EJ3V1UD

CHAPTER 1 GENERAL

1.4 Pin Configuration (Top View)

• 44-pin plastic QFP (10 × 10)

• 44-pin plastic LQFP (10 × 10)

44 43 42 41 40 39 38 37 36 35 34

P63/ANI3

P64/ANI4

P65/ANI5

P66/ANI6

P67/ANI7

AV^SS

1

33

TO74

2

32

31

30

29

28

27

26

25

24

23

TO73

3

TO72

4

TO71

5

TO70

6

P25/INTP1/TI81

P24/INTP0/TI80

P23/TO82

P22/RxD

P21/TxD

P20/TOFF7

P00

7

P01

8

P02

9

P03

10

P04

11

12 13 14 15 16 17 18 19 20 21 22

Cautions 1. Connect the IC pin directly to the V^SSpin.

2. Connect the AV^DDpin to the VDD pin.

3. Connect the AV^SSpin to the VSS pin.

Remark Pin connections in parentheses are intended for the µPD78F9842.

ANI0 to ANI7:

AV^DD

Analog input

Analog power supply

Analog ground

Internally connected

External interrupt input

Port 0

RxD:

Receive data

Timer input

:

TI80, TI81:

AV^SS

IC:

:

TO70 to TO75, TO82: Timer output

TOFF7:

TxD:

Timer output off

Transmit data

Power supply

Programming power supply

Ground

INTP0, INTP1:

P00 to P07:

P10 to P17:

P20 to P25:

P60 to P67:

RESET:

V

DD

:

Port 1

PP

SS

:

Port 2

Port 6

X1, X2:

Crystal

Reset

15

User’s Manual U13776EJ3V1UD

CHAPTER 1 GENERAL

1.5 78K/0S Series Lineup

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production

Products under development

Y Subseries products support SMB.

Small-scale package, general-purpose applications

44-pin

42-/44-pin

µ

PD789074 with added subsystem clock

PD789046

µ

PD789014 with enhanced timer and increased ROM, RAM capacity

µ

PD789026

PD789088

PD789074

PD789014

PD789062

PD789052

30-pin

28-pin

20-pin

PD789074 with enhanced timer and increased ROM, RAM capacity

PD789026 with enhanced timer

On-chip UART and capable of low voltage (1.8 V) operation

RC oscillation version of the PD789052

µ

PD789860 without EEPROM^TM, POC, and LVI

Small-scale package, general-purpose applications and A/D converter

PD789177Y

PD789167Y

µ

PD789167 with enhanced A/D converter (10 bits)

PD789104A with enhanced timer

PD789146 with enhanced A/D converter (10 bits)

PD789104A with added EEPROM

44-pin

30-pin

PD789177

PD789167

PD789156

PD789146

PD789134A

PD789124A

PD789114A

PD789104A

µ

PD789124A with enhanced A/D converter (10 bits)

RC oscillation version of the

µ

PD789104A

µ

PD789104A with enhanced A/D converter (10 bits)

PD789026 with added 8-bit A/D converter and multiplier

µ

LCD drive

144-pin

88-pin

80-pin

µ

PD789835

UART, 8-bit A/D, and dot LCD (Total display output pins: 96)

UART and dot LCD (40 16)

SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28

PD789830

PD789488

×

4)

SIO, 8-bit A/D converter, and resistance division type LCD (28

PD789407A with enhanced A/D converter (10 bits)

SIO, 8-bit A/D converter, and resistance division type LCD (28

×

4)

µ

PD789478

PD789417A

PD789407A

PD789456

PD789446

PD789436

PD789426

PD789316

PD789306

PD789467

80-pin

µ

78K/0S

Series

×

4)

80-pin

64-pin

µ

PD789446 with enhanced A/D converter (10 bits)

SIO, 8-bit A/D, and on-chip voltage booster type LCD (15

×

4)

µ

PD789426 with enhanced A/D converter (10 bits)

SIO, 8-bit A/D, and on-chip voltage booster type LCD (5

×

4)

RC oscillation version of the PD789306

64-pin

52-pin

µ

SIO and on-chip voltage booster type LCD (24

× 4)

8-bit A/D and on-chip voltage booster type LCD (23

SIO and resistance division type LCD (24 4)

× 4)

×

PD789327

USB

44-pin

µ

PD789800

For PC keyboard and on-chip USB function

On-chip inverter controller and UART

Inverter control

PD789842

µ

On-chip bus controller

PD789852

44-pin

30-pin

µ

PD789850A with enhanced functions such as timer and A/D converter

µ

PD789850A

µ

On-chip CAN controller

Keyless entry

30-pin

20-pin

µ

PD789862

µPD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity

µ

RC oscillation version of the PD789860

PD789861

PD789860

On-chip POC and key return circuit

VFD drive

µ

52-pin

64-pin

PD789871

Meter control

PD789881

On-chip VFD controller (Total display output pins: 25)

µ

UART and resistance division type LCD (26

× 4)

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP^TM(Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

16

User’s Manual U13776EJ3V1UD

CHAPTER 1 GENERAL

The major functional differences between the subseries are listed below.

Series for general-purpose applications and LCD drive

Function

ROM

Timer

8-Bit 10-Bit

A/D A/D

Serial

I/O

VDD

Remarks

Capacity

Interface

8-Bit 16-Bit Watch WDT

MIN.

Subseries Name

Value

µPD789046

µPD789026

µPD789088

−

Small-scale

package,

general-

16 KB

1 ch 1 ch 1 ch 1 ch

1 ch

34

24

1.8 V

(UART: 1 ch)

−

4 KB to 16 KB

16 KB to

32 KB

3 ch

purpose

applications

µPD789074

µPD789014

µPD789062

2 KB to 8 KB 1 ch

2 KB to 4 KB 2 ch

4 KB

−

22

14

−

RC oscillation

version

µPD789052

µPD789177

µPD789167

µPD789156

µPD789146

µPD789134A

µPD789124A

µPD789114A

µPD789104A

µPD789835

−

8 ch

−

Small-scale

package,

general-

16 KB to

24 KB

3 ch 1 ch 1 ch 1 ch

8 ch 1 ch

31

20

1.8 V

(UART: 1 ch)

−

4 ch

−

8 KB to 16 KB 1 ch

2 KB to 8 KB

On-chip

purpose

EEPROM

applications

and A/D

4 ch

−

4 ch

−

RC oscillation

version

converter

4 ch

−

4 ch

−

4 ch

37 1.8 V^NoteDot LCD

supported

−

LCD drive

24 KB to

60 KB

6 ch

1 ch 1 ch 3 ch

1 ch

(UART: 1 ch)

µPD789830

µPD789488

−

24 KB

1 ch 1 ch

3 ch

30

45

2.7 V

1.8 V

−

32 KB to

48 KB

8 ch 2 ch

(UART: 1 ch)

µPD789478

−

24 KB to

48 KB

8 ch

µPD789417A

µPD789407A

µPD789456

µPD789446

µPD789436

µPD789426

µPD789316

−

7 ch

−

12 KB to

24 KB

7 ch 1 ch

43

30

40

23

(UART: 1 ch)

−

6 ch

−

12 KB to

16 KB

2 ch

6 ch

−

6 ch

−

6 ch

−

8 KB to 16 KB

4 KB to 24 KB

2 ch

RC oscillation

version

(UART: 1 ch)

µPD789306

µPD789467

µPD789327

−

1 ch

18

21

−

1 ch

Note Flash memory version: 3.0 V

17

User’s Manual U13776EJ3V1UD

CHAPTER 1 GENERAL

Series for ASSP

Subseries Name

Function

ROM

Timer

8-Bit 10-Bit

A/D A/D

Serial

I/O

VDD

Remarks

Capacity

Interface

8-Bit 16-Bit Watch WDT

MIN.

Value

µPD789800

µPD789842

µPD789852

µPD789850A

µPD789861

−

USB

8 KB

2 ch

1 ch

2 ch

31

30

31

18

14

4.0 V

(USB: 1 ch)

Inverter

control

8 KB to 16 KB 3 ch

1 ch 1 ch 8 ch

1 ch

Note 1

(UART: 1 ch)

−

4 ch

−

On-chip bus

controller

24 KB to

32 KB

3 ch 1 ch

1 ch

8 ch 3 ch

(UART: 2 ch)

−

16 KB

2 ch

(UART: 1 ch)

−

Keyless

entry

4 KB

2 ch

1 ch

1.8 V RC oscillation

version, on-

chip EEPROM

µPD789860

µPD789862

On-chip

EEPROM

16 KB

1 ch 2 ch

1 ch

22

33

(UART: 1 ch)

µPD789871

µPD789881

−

VFD drive

4 KB to 8 KB 3 ch

1 ch 1 ch

1 ch

2.7 V

28 2.7 V^{Note 2}

−

Meter

16 KB

2 ch 1 ch

1 ch

control

(UART: 1 ch)

Notes 1. 10-bit timer: 1 channel

2. Flash memory version: 3.0 V

18

User’s Manual U13776EJ3V1UD

CHAPTER 1 GENERAL

1.6 Block Diagram

TI80/P24

Port 0

Port 1

P00 to P07

P10 to P17

8-bit timer/event

counter 80

8-bit timer/event

counter 81

TI81/P25

Port 2

Port 6

P20 to P25

P60 to P67

ROM

78K/0S

(Flash

TO82/P23

8-bit timer 82

CPU core

memory)

10-bit inverter

control timer

TO70 to TO75

TOFF7/P20

ANI0/P60 to

ANI7/P67

AVDD

A/D converter

AVSS

Watchdog timer

RESET

X1

X2

System control

Multiplier

SWP

RAM

TxD/P21

RxD/P22

UART00

H/L

L/H

VDD

V

SS IC

(V^PP

INTP0/P24

INTP1/P25

Interrupt control

)

Remark Pin connections in parentheses are intended for the µPD78F9842.

19

User’s Manual U13776EJ3V1UD

CHAPTER 1 GENERAL

1.7 Outline of Functions

µPD789841

µPD789842

µPD78F9842

Flash memory

16 KB

Item

Internal memory

ROM structure

Mask ROM

ROM

RAM

8 KB

16 KB

256 bytes

0.24/0.96 µs (operation with system clock running at 8.38 MHz)

Minimum instruction execution time

Instruction set

• 16-bit operations

• Bit manipulations (such as set, reset, and test)

I/O ports

Total of 30 port pins

22 CMOS I/O pins

8 CMOS input pins

Serial interface

Timers

UART: 1 channel

• 10-bit inverter control timer: 1 channel

• 8-bit timer/event counters: 2 channels

• 8-bit timer: 1 channel

• Watch timer: 1 channel

• Watchdog timer: 1 channel

8-bit resolution × 8 channels

10 bits × 10 bits = 20 bits

A/D converters

Multiplier

SWAP

The contents of the higher four bits of an 8-bit register can be exchanged with the

lower four bits.

Vectored interrupt

sources

Maskable

12 internal and 2 external interrupts

Internal interrupt

Non-maskable

Power supply voltage

VDD = 4.0 to 5.5 V

T^A= −40 to +85°C

Operating ambient temperature

Package

• 44-pin plastic QFP (10 × 10)

• 44-pin plastic LQFP (10 × 10)

The following shows an outline of the timers.

TM7

TM80

TM81

TM82

1 channel

−

WT^{Note 1}

WDT^{Note 2}

Operating

mode

Interval timer

1 channel

−

2

−

2

External event counter

Timer output

1 channel

−

1

−

1

Function

1 output

1

−

Square-wave output

Interrupt source

1

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer provides a watchdog timer function and interval timer function, but only one of the

two functions should be selected.

20

User’s Manual U13776EJ3V1UD

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

(1) Port pins

Pin Name

I/O

Function

After Reset

Input

Alternate Function

−

P00 to P07

Port 0

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors

can be specified by pull-up resistor option register 0 (PU0).

−

P10 to P17

I/O

Port 1

Input

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors

can be specified by pull-up resistor option register 0 (PU0).

P20

Port 2

TOFF7

6-bit I/O port

P21

TXD

Input/output can be specified in 1-bit units.

Use of on-chip pull-up resistors can be specified by pull-up

resistor option register B2 (PUB2).

P22

RXD

P23

TO82

P24

INTP0/TI80

INTP1/TI81

ANI0 to ANI7

P25

P60 to P67

Input

Port 6

Input

8-bit input-only port

21

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CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

Pin Name

INTP0

I/O

Function

After Reset

Input

Alternate Function

Input

External interrupt input for which valid edge (rising and/or

falling edge) can be specified

P24/TI80

INTP1

RxD

P25/TI81

Input

Serial data input to asynchronous serial interface

Serial data output from asynchronous serial interface

10-bit inverter control timer output

Input

Output

Input

P22

TxD

Output

P21

−

TO70 to TO75 Output

TOFF7

TI80

Input

External input to stop timer output (TO70 to TO75)

External count clock input to TM80

External count clock input to TM81

TM82 timer output

P20

P24/INTP0

TI81

P25/INTP1

TO82

ANI0 to ANI7

AVSS

AVDD

X1

Output

Input

−

Input

P23

A/D converter analog input

Input

P60 to P67

−

A/D converter ground potential

−

A/D converter analog power supply

Connection of crystal for system clock oscillation

−

Input

−

X2

RESET

VDD

Input

System reset input

Input

−

Positive supply voltage for ports

Ground potential for ports

VSS

IC

Internally connected. Connect this pin directly to the VSS pin.

VPP

This pin is used to set flash memory programming mode and

applies a high voltage when a program is written or verified.

22

User’s Manual U13776EJ3V1UD

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00 to P07 (Port 0)

These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port

mode register 0 (PM0). When these pins are used as an input port, use of an on-chip pull-up resistor can be

specified by pull-up resistor option register 0 (PU0).

2.2.2 P10 to P17 (Port 1)

These pins constitute an 8-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode

register 1 (PM1). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by

pull-up resistor option register 0 (PU0).

2.2.3 P20 to P25 (Port 2)

These pins constitute a 6-bit I/O port. In addition, these pins provide a function to perform external interrupt input,

timer I/O, and UART data I/O.

Port 2 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In port mode, P20 to P25 function as a 6-bit I/O port. Port 2 can be set to input or output mode in 1-bit units

by using port mode register 2 (PM2). Use of on-chip pull-up resistors for the P20 to P25 pins can be

specified by pull-up resistor option register B2 (PUB2).

(2) Control mode

In this mode, P20 to P25 function as external interrupt inputs, timer I/O, and UART data I/O.

(a) INTP0, INTP1

These are the external interrupt input pins for which the valid edge (rising edge, falling edge, or both rising

and falling edges) can be specified.

(b) TOFF7

This is the external input pin to stop 10-bit inverter control timer output (TO70 to TO75).

(c) TI80, TI81

These are the external count clock input pins of 8-bit timer/event counters 80 and 81.

(d) TO82

This is the timer output pin of 8-bit timer 82.

(e) RxD, TxD

These are the serial data I/O pins of UART.

Caution When using P20 to P25 as UART data I/O pins, the I/O and output latch must be set according to

the function to be used. For details of the setting, see 11.3 (1).

23

User’s Manual U13776EJ3V1UD

CHAPTER 2 PIN FUNCTIONS

2.2.4 P60 to P67 (Port 6)

These pins constitute an 8-bit input-only port. In addition to general-purpose input port pins, they can also

function as A/D converter input pins.

(1) Port mode

In port mode, P60 to P67 function as an 8-bit input-only port.

(2) Control mode

In control mode, P60 to P67 function as A/D converter analog inputs (ANI0 to ANI7).

2.2.5 TO70 to TO75

These are the timer output pins of the 10-bit inverter control timer.

2.2.6 RESET

This pin inputs an active-low system reset signal.

2.2.7 X1, X2

These pins are used to connect a crystal for system clock oscillation.

2.2.8 AV^DD

This is the analog power supply pin of the A/D converter. Always use the same potential as that of the V^DDpin

even when A/D converter is not used.

2.2.9 AV^SS

This is the ground potential pin of the A/D converter. Always use the same potential as that of the V^SSpin even

when the A/D converter is not used.

2.2.10 V^DD

V^DDsupplies positive power.

2.2.11 V^SS

V^SSis the ground potential pin.

2.2.12 VPP (µPD78F9842 only)

A high voltage should be applied to this pin when the flash memory programming mode is set and when the

program is written or verified.

Connect this pin in either of the following ways.

• Independently connect to a 10 kΩ pull-down resistor.

• By using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode

or to V^SSin the normal operation mode.

If the wiring between the V^PPand VSS pins is long or external noise is superimposed on the VPP pin, the user

program may malfunction.

24

User’s Manual U13776EJ3V1UD

CHAPTER 2 PIN FUNCTIONS

2.2.13 IC

The IC (Internally Connected) pin is used to set the µPD789842 Subseries to test mode before shipment. In

normal operation mode, directly connect this pin to the V^SSpin with as short a wiring length as possible.

If a potential difference is generated between the IC pin and V^SSpin due to a long wiring length between the IC pin

and V^SSpin or external noise superimposed on the IC pin, the user program may not run correctly.

• Directly connect the IC pin to the VSS pin.

VSS

IC

Keep as short as possible

25

User’s Manual U13776EJ3V1UD

CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Handling of Unused Pins

Table 2-1 lists the types of I/O circuits for each pin and explains how unused pins are handled.

Figure 2-1 shows the configuration of each type of I/O circuit.

Table 2-1. Type of I/O Circuit for Each Pin and Handling of Unused Pins

Pin Name

I/O Circuit Type

5-A

I/O

Recommended Connection of Unused Pins

Connect to the V^DDor VSS pin via a resistor.

P00 to P07

P10 to P17

P20/TOFF7

P21/TxD

Input:

Output: Leave open.

8-A

P22/RxD

P23/TO82

P24/INTP0/TI80

P25/INTP1/TI81

P60/ANI0 to P67/ANI7

TO70 to TO75

AVDD

9-C

4

Input

Directly connect to the VDD or VSS pin.

Output Independently connect to the VDD or VSS pin via a resistor.

−

Directly connect to the VDD pin.

Directly connect to the VSS pin.

−

AVSS

−

RESET

2

Input

−

IC (mask ROM version)

VPP (flash memory version)

Directly Connect to the VSS pin.

−

Independently connect via a 10 kΩ pull-down resistor or

directly connect to V^SS.

26

User’s Manual U13776EJ3V1UD

CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuits

Type 8-A

V

DD

Type 2

Pull-up

enable

P-ch

V

DD

IN

Data

P-ch

IN/OUT

Output

disable

N-ch

Schmitt-triggered input with hysteresis characteristics

V

SS

Type 4

Type 9-C

IN

Comparator

P-ch

N-ch

V

DD

+

-

Data

P-ch

AV^SS

V

REF

IN/OUT

(Threshold voltage)

Output

disable

N-ch

V

SS

Input

enable

Type 5-A

V

DD

Pull-up

enable

P-ch

V

DD

Data

P-ch

N-ch

IN/OUT

Output

disable

V

SS

Input

enable

27

User’s Manual U13776EJ3V1UD

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Products in the µPD789842 Subseries can each access up to 64 KB of memory space.

Figures 3-1 to 3-3 show the memory maps.

Figure 3-1. Memory Map (µPD789841)

F F F F H

Special-function registers

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

256 × 8 bits

F E 0 0 H

F D F F H

Reserved

Data memory space

1 F F F H

2 0 0 0 H

1 F F F H

Program area

0 0 8 0 H

0 0 7 F H

Program memory

space

Internal ROM

CALLT table area

8,192 × 8 bits

0 0 4 0 H

0 0 3 F H

Program area

0 0 1 E H

0 0 1 D H

Vector table area

0 0 0 0 H

28

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (µPD789842)

F F F F H

Special-function registers

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

256 × 8 bits

F E 0 0 H

F D F F H

Reserved

Data memory space

3 F F F H

4 0 0 0 H

3 F F F H

Program area

0 0 8 0 H

0 0 7 F H

Program memory

space

Internal ROM

CALLT table area

16,384 × 8 bits

0 0 4 0 H

0 0 3 F H

Program area

0 0 1 E H

0 0 1 D H

Vector table area

0 0 0 0 H

29

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-3. Memory Map (µPD78F9842)

F F F F H

Special-function registers

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

256 × 8 bits

F E 0 0 H

F D F F H

Reserved

Data memory space

3 F F F H

4 0 0 0 H

3 F F F H

Program area

0 0 8 0 H

0 0 7 F H

Program memory

space

Internal flash memory

CALLT table area

16,384 × 8 bits

0 0 4 0 H

0 0 3 F H

Program area

0 0 1 E H

0 0 1 D H

Vector table area

0 0 0 0 H

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User’s Manual U13776EJ3V1UD

CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The µPD789842 Subseries provides the following internal ROMs (mask ROM or flash memory) containing the

following capacities.

Table 3-1. Internal ROM Capacity

Internal ROM

Part Number

Structure

Mask ROM

Capacity

8,192 × 8 bits

µPD789841

µPD789842

µPD78F9842

16,384 × 8 bits

Flash memory

The following areas are allocated to the internal program memory space.

(1) Vector table area

A 30-byte area of addresses 0000H to 001DH is reserved as a vector table area. This area stores program

start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit

program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd

address.

Table 3-2. Vector Table

Vector Table Address

0000H

Interrupt Request

RESET input

Vector Table Address

0010H

Interrupt Request

INTST00

0004H

0006H

0008H

000AH

000CH

000EH

INTWDT

INTP0

0012H

0014H

0016H

0018H

001AH

001CH

INTWT

INTWTI

INTTM80

INTTM81

INTTM82

INTAD

INTP1

INTTM7

INTSER00

INTSR00

(2) CALLT instruction table area

The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of

addresses 0040H to 007FH.

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CHAPTER 3 CPU ARCHITECTURE

3.1.2 Internal data memory (internal high-speed RAM) space

The µPD789842 Subseries provides a 256-byte internal high-speed RAM.

The internal high-speed RAM can also be used as a stack memory.

3.1.3 Special function register (SFR) area

Special-function registers (SFRs) of on-chip peripheral hardware are allocated to an area of FF00H to FFFFH

(see Table 3-3).

3.1.4 Data memory addressing

Each product in the µPD789842 Subseries is provided with a wide range of addressing modes to make memory

manipulation as efficient as possible. A data memory area (FE00H to FFFFH) can be accessed using a unique

addressing mode according to its use, such as a special-function register (SFR). Figures 3-4 to 3-6 illustrate the data

memory addressing modes.

Figure 3-4. Data Memory Addressing Modes (µPD789841)

F F F F H

Special-function registers (SFRs)

SFR addressing

256 × 8 bits

F F 2 0 H

F F 1 F H

F F 0 0 H

F E F F H

Short direct addressing

Internal high-speed RAM

256 × 8 bits

F E 2 0 H

F E 1 F H

F E 0 0 H

F D F F H

Direct addressing

Register indirect addressing

Based addressing

Reserved

2 0 0 0 H

1 F F F H

Internal ROM

8,192 × 8 bits

0 0 0 0 H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-5. Data Memory Addressing Modes (µPD789842)

F F F F H

Special-function registers (SFRs)

SFR addressing

256 × 8 bits

F F 2 0 H

F F 1 F H

F F 0 0 H

F E F F H

Short direct addressing

Internal high-speed RAM

256 × 8 bits

F E 2 0 H

F E 1 F H

F E 0 0 H

F D F F H

Direct addressing

Register indirect addressing

Based addressing

Reserved

4 0 0 0 H

3 F F F H

Internal ROM

16,384 × 8 bits

0 0 0 0 H

33

User’s Manual U13776EJ3V1UD

CHAPTER 3 CPU ARCHITECTURE

Figure 3-6. Data Memory Addressing Modes (µPD78F9842)

F F F F H

Special-function registers (SFRs)

SFR addressing

256 × 8 bits

F F 2 0 H

F F 1 F H

F F 0 0 H

F E F F H

Short direct addressing

Internal high-speed RAM

256 × 8 bits

F E 2 0 H

F E 1 F H

F E 0 0 H

F D F F H

Direct addressing

Register indirect addressing

Based addressing

Reserved

4 0 0 0 H

3 F F F H

Internal flash memory

16,384 × 8 bits

0 0 0 0 H

34

User’s Manual U13776EJ3V1UD

CHAPTER 3 CPU ARCHITECTURE

3.2 Processor Registers

The µPD789842 Subseries provides the following on-chip processor registers.

3.2.1 Control registers

The control registers contain special functions to control the program sequence statuses and stack memory. The

program counter, program status word, and stack pointer are the control registers.

(1) Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be

executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction

to be fetched. When a branch instruction is executed, immediate data or register contents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-7. Program Counter Configuration

15

0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set or reset by instruction

execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-8. Program Status Word Configuration

7

0

IE

Z

0

AC

0

1

CY

PSW

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CHAPTER 3 CPU ARCHITECTURE

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledgment operations of CPU.

When IE = 0, the IE flag is set to the interrupt disabled (DI) status. All interrupt requests except non-

maskable interrupts are disabled.

When IE = 1, the IE flag is set to the interrupt enabled (EI) status and interrupt request acknowledgment is

controlled by the interrupt mask flag for each interrupt source.

This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all

other cases.

(d) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out

value upon rotate instruction execution and functions as a bit accumulator during bit manipulation

instruction execution.

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CHAPTER 3 CPU ARCHITECTURE

(3) Stack pointer (SP)

This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-

speed RAM area can be set as the stack area.

Figure 3-9. Stack Pointer Configuration

15

0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)

from the stack memory.

Each stack operation saves and restores data as shown in Figures 3-10 and 3-11.

Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before

instruction execution.

Figure 3-10. Data to Be Saved to Stack Memory

(a) PUSH rp instruction (when SP is FEE0H)

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

Higher register pair

Lower register pair

(b) CALL, CALLT instructions (when SP is FEE0H)

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

(c) Interrupt instruction (when SP is FEE0H)

SP

FEE0H

FEDFH

FEDEH

FEDDH

PSW

PC15 to PC8

PC7 to PC0

FEDDH

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-11. Data to Be Restored from Stack Memory

(a) POP rp instruction (when SP is FEDEH)

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

Higher register pair

Lower register pair

(b) RET instructions (when SP is FEDEH)

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

(c) RETI instruction (when SP is FEDDH)

SP

FEE0H

FEDFH

FEDEH

FEDDH

PSW

PC15 to PC8

PC7 to PC0

FEDDH

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CHAPTER 3 CPU ARCHITECTURE

3.2.2 General-purpose registers

The general-purpose registers consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and two 8-bit registers in pairs can be used as a 16-bit register

(AX, BC, DE, and HL).

The registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and

absolute names (R0 to R7 and RP0 to RP3).

Figure 3-12. General-Purpose Register Configuration

(a) Absolute names

16-bit processing

8-bit processing

R7

RP3

R6

R5

R4

RP2

RP1

RP0

R3

R2

R1

R0

15

0

7

0

(b) Functional names

16-bit processing

HL

8-bit processing

H

L

D

E

DE

BC

AX

B

C

A

X

15

0

7

0

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CHAPTER 3 CPU ARCHITECTURE

3.2.3 Special-function registers (SFRs)

Unlike a general-purpose register, each special-function register has a special function.

The special-function registers are allocated in the 256-byte area FF00H to FFFFH.

The special-function registers can be manipulated, like the general-purpose registers, with operation, transfer, and

bit manipulation instructions. The manipulatable bit unit (1, 8, or 16) differs depending on the special-function register

type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describe a symbol reserved by the assembler as the operand of a 1-bit manipulation instruction (sfr.bit). An

address can also be specified.

• 8-bit manipulation

Describe a symbol reserved by the assembler as the operand of an 8-bit manipulation instruction (sfr). An

address can also be specified.

• 16-bit manipulation

Describe a symbol reserved by the assembler as the operand of a 16-bit manipulation instruction. When

specifying an address, describe an even address.

Table 3-3 lists the special-function registers. The meanings of the symbols in this table are as follows.

• Symbol

Indicates the addresses of the implemented special-function registers. The symbols shown in this column are

reserved words in the assembler, and have already been defined in the header file "sfrbit.h" in the C compiler.

Therefore, these symbols can be used as instruction operands if the assembler or integrated debugger is used.

• R/W

Indicates whether the special-function register in question can be read or written.

R/W:

R:

Read/write

Read only

Write only

W:

• Number of bits manipulated simultaneously

Indicates the bit units (1, 8, and 16) in which the special-function register in question can be manipulated.

• After reset

Indicates the status of the special-function register when the RESET signal is input.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-3. Special-Function Registers (1/2)

Number of Bits Manipulated Simultaneously

Special-Function Register (SFR)

Name

Address

Symbol

R/W

After Reset

00H

1 Bit

√

8 Bits

16 Bits

√

−

√

−

√

−

√

−

√

−

FF00H Port register 0

FF01H Port register 1

FF02H Port register 2

FF06H Port register 6

FF08H 10-bit buffer register 0

FF09H

P0

P1

P2

P6

√

R

Undefined

0000H

BFCM0L

−

R/W

BFCM0

BFCM1

BFCM2

BFCM3

Note

√

−

BFCM1L

−

FF0AH 10-bit buffer register 1

FF0BH

Note

√

−

BFCM2L

−

FF0CH 10-bit buffer register 2

FF0DH

Note

√

−

BFCM3L

−

FF0EH 10-bit buffer register 3

FF0FH

00FFH

Note

√

−

FF11H A/D conversion result register

FF14H 10-bit compare register 0

FF15H

ADCRH

CM0

R

Undefined

0000H

Note

√

−

R/W

Note

−

√

FF16H 10-bit compare register 1

FF17H

CM1

CM2

CM3

Note

√

FF18H 10-bit compare register 2

FF19H

Note

√

FF1AH 10-bit compare register 3

FF1BH

00FFH

FFH

√

−

√

−

√

−

√

−

FF20H Port mode register 0

FF21H Port mode register 1

FF22H Port mode register 2

FF32H Pull-up resistor option register B2

FF42H Timer clock selection register 2

FF4AH Watch timer mode control register

FF50H 8-bit compare register 80

FF51H 8-bit timer counter 80

PM0

PM1

PM2

PUB2

TCL2

WTM

CR80

TM80

00H

W

R

Undefined

00H

FF53H 8-bit timer mode control register 80 TMC80

R/W

W

FF54H 8-bit compare register 81

FF55H 8-bit timer counter 81

CR81

TM81

Undefined

00H

R

FF57H 8-bit timer mode control register 81 TMC81

R/W

Note 16-bit access is allowed only with short direct addressing.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-3. Special-Function Registers (2/2)

Number of Bits Manipulated Simultaneously

Special-Function Register (SFR)

Name

Address

Symbol

R/W

After Reset

1 Bit

8 Bits

16 Bits

−

√

−

FF58H 8-bit compare register 82

FF59H 8-bit timer counter 82

CR82

TM82

W

R

Undefined

00H

FF5BH 8-bit timer mode control register 82 TMC82

R/W

FF70H Asynchronous serial interface mode ASIM00

register 00

√

−

√

−

FF71H Asynchronous serial interface status ASIS00

register 00

R

FF72H Baud rate generator control register BRGC00

00

R/W

−

√

−

√

−

√

−

√

−

√

−

FF73H Transmission shift register 00

Reception buffer register 00

TXS00

RXB00

ADM

W

R

Undefined

FFH

FF80H A/D converter mode register

FF84H A/D input selection register

FFA0H Multiplier control register 1

R/W

00H

ADS

MULC1

FFA1H 10-bit multiplication data register A1 MRA1L

FFA2H MRA1H

FFA3H 10-bit multiplication data register B1 MRB1L

W

Undefined

FFA4H

MRB1H

MUL1LL

MUL1LH

MUL1HL

TMC7

TMM7

DTIME

SWP0

IF0

FFA5H 20-bit multiplication result register

FFA6H

R

FFA7H

FFA8H Inverter timer control register 7

FFA9H Inverter timer mode register 7

FFAAH Dead time reload register

FFABH Swapping function register 0

FFE0H Interrupt request flag register 0

FFE1H Interrupt request flag register 1

FFE4H Interrupt mask flag register 0

FFE5H Interrupt mask flag register 1

FFECH External interrupt mode register 0

FFF7H Pull-up resistor option register 0

FFF9H Watchdog timer mode register

R/W

00H

FFH

Note

00H

IF1

MK0

FFH

00H

MK1

INTM0

PU0

WDTM

OSTS

FFFAH Oscillation stabilization time

selection register

04H

02H

√

−

FFFBH Processor clock control register

PCC

Note The default differs between read mode and write mode. For details, see 13.2.

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CHAPTER 3 CPU ARCHITECTURE

3.3 Instruction Address Addressing

An instruction address is determined by the program counter (PC) contents. The PC contents are normally

incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each

time another instruction is executed. When a branch instruction is executed, the branch destination information is set

to the PC by the addressing described below to branch control. (For details of each instruction, refer to 78K/0S

Series Instructions User's Manual (U11047E).)

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In

other words, the range of branch in relative addressing is between -128 and +127 of the start address of the

following instruction.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15

0

...

PC is the start address of

the next instruction of

a BR instruction.

PC

+

8

7

6

α

S

jdisp8

15

0

PC

When S = 0, α indicates all bits "0".

When S = 1, α indicates all bits "1".

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CHAPTER 3 CPU ARCHITECTURE

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.

The CALL !addr16 and BR !addr16 instructions can make a branch to all the memory spaces.

[Illustration]

In case of CALL !addr16 and BR !addr16 instructions

7

0

CALL or BR

Low Addr.

High Addr.

15

8 7

0

PC

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CHAPTER 3 CPU ARCHITECTURE

3.3.3 Table indirect addressing

[Function]

The table contents (branch destination address) of the particular location to be addressed by the immediate data

of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.

Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can

refer to the address stored in the memory table 40H to 7FH and make a branch to all the memory spaces.

[Illustration]

7

6

1

5

1

0

Instruction code

Effective address

0

ta4-0

15

8

0

7

0

6

1

5

1

0

7

Memory (Table)

Low Addr.

0

High Addr.

Effective address + 1

15

8

7

0

PC

3.3.4 Register addressing

[Function]

The register pair (AX) contents to be specified with an instruction word are transferred to the program counter

(PC) and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7

0

8

7

0

rp

A

X

15

PC

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) to undergo manipulation

during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Opcode

00H

FEH

[Illustration]

7

0

Opcode

addr16 (lower)

addr16 (higher)

Memory

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CHAPTER 3 CPU ARCHITECTURE

3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high-

speed RAM and special-function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,

respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the total SFR area. In this

area, ports which are frequently accessed in a program and a compare register of the timer are mapped, and

these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,

bit 8 is set to 1. See [Illustration].

[Operand format]

Identifier

saddr

Description

Label or immediate data indicating FE20H to FF1FH

Label or immediate data indicating FE20H to FF1FH (even address only)

saddrp

[Description example]

MOV FE30H, A; When transferring register A value to saddr (FE30H)

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

Opcode

30H (saddr-offset)

[Illustration]

7

0

Opcode

saddr-offset

Short direct memory

15

8

0

Effective

address

1

α

When 8-bit immediate data is 20H to FFH, = 0.

α

When 8-bit immediate data is 00H to 1FH, = 1.

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CHAPTER 3 CPU ARCHITECTURE

3.4.3 Special-function register (SFR) addressing

[Function]

A memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs

mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special-function register name

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

[Illustration]

7

0

Opcode

sfr-offset

SFR

15

1

8 7

0

Effective

address

1

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CHAPTER 3 CPU ARCHITECTURE

3.4.4 Register addressing

[Function]

A general-purpose register is accessed as an operand.

The general-purpose register to be accessed is specified with the register specify code and functional name in

the instruction code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with three bits in the instruction code.

[Operand format]

Identifier

Description

r

X, A, C, B, E, D, L, H

AX, BC, DE, HL

rp

'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,

B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code

0

1

0

1

0

1

0

1

Register specify code

INCW DE; When selecting the DE register pair for rp

Instruction code

1

0

1

0

Register specify code

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CHAPTER 3 CPU ARCHITECTURE

3.4.5 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to be

accessed is specified with the register pair specify code in the instruction code. This addressing can be carried

out for all the memory spaces.

[Operand format]

Identifier

Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code

0

1

0

1

0

1

[Illustration]

15

8

7

0

DE

D

E

Memory address specified

by register pair DE

The contents of addressed

memory are transferred

7

0

A

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CHAPTER 3 CPU ARCHITECTURE

3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. Addition is performed by expanding the offset data as a positive number to 16

bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code

0

1

0

1

0

1

0

1

0

[Illustration]

16

8 7

0

HL

H

L

+10

7

Memory

The contents of the

addressed memory

are transferred.

7

0

A

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CHAPTER 3 CPU ARCHITECTURE

3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN

instructions are executed or the register is saved or restored upon generation of an interrupt request.

Stack addressing provides access to the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE (saving DE register)

Instruction code

1

0

1

0

1

0

1

0

[Illustration]

7

Memory

0

SP

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

D

E

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

The µPD789842 Subseries is provided with the ports shown in Figure 4-1. These ports are used to enable

several types of control.

Table 4-1 lists the functions of each port.

These ports, while originally designed as digital I/O ports, can also be used for other functions, as summarized in

2.2.

Figure 4-1. Port Types

P20

P00

Port 2

Port 0

P25

P60

P07

P10

Port 6

Port 1

P67

P17

Table 4-1. Port Functions

Name

Pin Name

P00 to P07

Function

I/O port. Input/output can be specified in 1-bit units.

Port 0

Port 1

Port 2

Port 6

When used as an input port, use of on-chip pull-up resistors can be specified by

pull-up resistor option register 0 (PU0).

P10 to P17

P20 to P25

P60 to P67

I/O port. Input/output can be specified in 1-bit units.

When used as an input port, use of on-chip pull-up resistors can be specified by

pull-up resistor option register 0 (PU0).

I/O port. Input/output can be specified in 1-bit units.

Use of on-chip pull-up resistors can be specified by pull-up resistor option

register B2 (PUB2).

Input-only port

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CHAPTER 4 PORT FUNCTIONS

4.2 Port Configuration

Ports have the following hardware configuration.

Table 4-2. Configuration of Port

Parameter

Configuration

Control registers

Port mode register (PM0 to PM2)

Pull-up resistor option register (PU0, PUB2)

Total: 30 (CMOS I/O: 22, CMOS input: 8)

Total: 22 (software control: 22)

Ports

Pull-up resistors

4.2.1 Port 0

This is an 8-bit I/O port with an output latch. Port 0 can be specified in input or output mode in 1-bit units by using

port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors can be

connected in 8-bit units by using pull-up resistor option register 0 (PU0).

RESET input sets port 0 to input mode.

Figure 4-2 shows a block diagram of port 0.

Figure 4-2. Block Diagram of P00 to P07

V

DD

WR^PU0

PU0

P-ch

RD

WRPORT

WRPM

Output latch

(P00 to P07)

P00 to P07

PM00 to PM07

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 0 read signal

WR: Port 0 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.2 Port 1

This is an 8-bit I/O port with an output latch. Port 1 can be specified in input or output mode in 1-bit units by using

port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull-up resistors can be

connected in 8-bit units by using pull-up resistor option register 0 (PU0).

RESET input sets port 1 to input mode.

Figure 4-3 shows a block diagram of port 1.

Figure 4-3. Block Diagram of P10 to P17

V

DD

WR^PU0

PU0

P-ch

RD

WRPORT

WRPM

Output latch

(P10 to P17)

P10 to P17

PM10 to PM17

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 1 read signal

WR: Port 1 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.3 Port 2

This is a 6-bit I/O port with an output latch. Port 2 can be specified in input or output mode in 1-bit units by using

port mode register 2 (PM2).

The P20 to P25 pins can be connected to on-chip pull-up resistors in 1-bit units by using pull-up resistor option

register B2 (PUB2).

This port is also used as external interrupt inputs, timer I/O, and data I/O to and from the asynchronous serial

interface.

RESET input sets port 2 to input mode.

Figures 4-4 and 4-5 show block diagrams of port 2.

Figure 4-4. Block Diagram of P20, P22, P24, and P25

VDD

WR^PUB2

PUB20, PUB22,

PUB24, PUB25

P-ch

Alternate

function

RD

WRPORT

WRPM

Output latch

(P20, P22, P24, P25)

P20/TOFF7

P22/RxD

P24/INTP0/TI80

P25/INTP1/TI81

PM20, PM22,

PM24, PM25

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-5. Block Diagram of P21 and P23

V

DD

WR^PUB2

PUB21, PUB23

P-ch

RD

WR^PORT

Output latch

(P21, P23)

P21/TxD

P23/TO82

WRPM

PM21, PM23

Alternate

function

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.4 Port 6

This is an 8-bit input-only port.

This port is also used as analog inputs to the A/D converter.

RESET input sets port 6 to input mode.

Figure 4-6 shows a block diagram of port 6.

Figure 4-6. Block Diagram of P60 to P67

RD

+

-

P60/ANI0 to P67/ANI7

A/D converter

V

REF

RD: Port 6 read signal

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CHAPTER 4 PORT FUNCTIONS

4.3 Port Function Control Registers

The following three types of registers are used to control the ports.

• Port mode registers (PM0 to PM2)

• Pull-up resistor option register 0 (PU0)

• Pull-up resistor option register B2 (PUB2)

(1) Port mode registers (PM0 to PM2)

The port mode registers separately specify each port bit as input or output.

Each port mode register is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets the port mode registers to FFH.

When port pins are used for alternate functions, the corresponding port mode register and output latch must

be set or reset as described in Table 4-3.

Caution When port 2 is functioning as an output port and its output level is changed, an interrupt

request flag is set, because this port is also used as the input for an external interrupt. To

use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.

Table 4-3. Port Mode Register and Output Latch Settings for Using Alternate Functions

Alternate Function

PM××

P××

Pin Name

Name

I/O

×

0

×

P20

TOFF7

TO82

INTP0

TI80

Input

Output

Input

1

0

1

P23

P24

P25

INTP1

TI81

Caution When using P21 and P22 as the serial interface, the I/O or output latch must be set according to

the function to be used. For details of the setting, see 11.3 (1).

Remark ×:

Don't care

PM××: Port mode register

P××: Port output latch

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CHAPTER 4 PORT FUNCTIONS

Figure 4-7. Format of Port Mode Register

Symbol

PM0

7

6

5

4

3

2

1

0

Address

FF20H

After reset

FFH

R/W

PM07

PM06

PM05

PM04

PM03

PM02

PM01

PM00

PM1

PM2

PM17

1

PM16

1

PM15

PM25

PM14

PM24

PM13

PM23

PM12

PM22

PM11

PM21

PM10

PM20

FF21H

FF22H

FFH

R/W

Pmn pin I/O mode selection

(m = 0 to 2, n = 0 to 7)

PMmn

0

1

Output mode (output buffer on)

Input mode (output buffer off)

(2) Pull-up resistor option register 0 (PU0)

This register sets whether an on-chip pull-up resistor is used for each of ports 0 and 1. On the port specified

to use an on-chip pull-up resistor by PU0, the pull-up resistor can be internally used only for the bits set to

input mode. No on-chip pull-up resistors can be used for the bits set to output mode regardless of the setting

of PU0. This also applies when the pins are used as alternate-function output pins.

PU0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PU0 to 00H.

Figure 4-8. Format of Pull-Up Resistor Option Register 0

Symbol

PU0

7

0

6

0

5

0

4

0

3

0

2

0

<1>

<0>

Address

FFF7H

After reset

00H

R/W

PU01

PU00

PU0m

Pm on-chip pull-up resistor selection (m = 0, 1)

0

1

On-chip pull-up resistor not connected

On-chip pull-up resistor connected

Caution Be sure to clear bits 2 to 7 to 0.

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CHAPTER 4 PORT FUNCTIONS

(3) Pull-up resistor option register B2 (PUB2)

This register specifies whether an on-chip pull-up resistor is connected to each pin of port 2. The pin

specified by PUB2 to use an on-chip pull-up resistor is connected to the on-chip pull-up resistor regardless of

the setting of the port mode register.

PUB2 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PUB2 to 00H.

Figure 4-9. Format of Pull-Up Resistor Option Register B2

Symbol

PUB2

7

0

6

0

<5>

<4>

<3>

<2>

<1>

<0>

Address

FF32H

After reset

00H

R/W

PUB25

PUB24

PUB23

PUB22

PUB21 PUB20

PUB2m

P2m on-chip pull-up resistor selection (m = 0 to 5)

0

1

On-chip pull-up resistor not connected

On-chip pull-up resistor connected

Caution Be sure to clear bits 6 and 7 to 0.

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CHAPTER 4 PORT FUNCTIONS

4.4 Operation of Port Functions

The operation of a port differs depending on whether the port is set in input or output mode, as described below.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of

the pin that is set in input mode and not subject to manipulation become undefined.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch of a port by using a transfer instruction. The contents of the output

latch can be output from the pins of the port.

Once data is written to the output latch, it is retained until new data is written to the output latch.

Reset input clears the data of the output latch.

(2) In input mode

A value can be written to the output latch by using a transfer instruction. However, the status of the port pin

is not changed because the output buffer is OFF.

Once data is written to the output latch, it is retained until new data is written to the output latch.

4.4.2 Reading from I/O port

(1) In output mode

The contents of the output latch can be read by using a transfer instruction. The contents of the output latch

are not changed.

(2) In input mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not

changed.

4.4.3 Arithmetic operation of I/O port

(1) In output mode

An arithmetic operation can be performed with the contents of the output latch. The result of the operation is

written to the output latch. The contents of the output latch are output from the port pins.

Once data is written to the output latch, it is retained until new data is written to the output latch.

Reset input clears the data of the output latch.

(2) In input mode

The contents of the output latch become undefined. However, the status of the pin is not changed because

the output buffer is off.

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CHAPTER 5 CLOCK GENERATOR

5.1 Clock Generator Functions

The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following

system clock oscillator is used.

• System clock oscillator

This circuit oscillates at 8.0 to 8.5 MHz. Oscillation can be stopped by executing the STOP instruction.

5.2 Clock Generator Configuration

The clock generator consists of the following hardware.

Table 5-1. Configuration of Clock Generator

Item

Control register

Oscillator

Configuration

Processor clock control register (PCC)

System clock oscillator

Figure 5-1. Block Diagram of Clock Generator

Prescaler

Clock for

peripheral

hardware

X1

X2

System clock

oscillator

Prescaler

fX

f

X

2²

Wait

controller

Standby

controller

CPU clock

(f^CPU

)

STOP

PCC1

Processor clock

control register (PCC)

Internal bus

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CHAPTER 5 CLOCK GENERATOR

5.3 Register Controlling Clock Generator

The clock generator is controlled by the following register.

(1) Processor clock control register (PCC)

PCC sets the CPU clock selection and the division ratio.

PCC is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PCC to 02H.

Figure 5-2. Format of Processor Clock Control Register

Symbol

PCC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Address

FFFBH

After reset

02H

R/W

PCC1

CPU clock (fCPU) selection

Minimum instruciton execution time: 2/fCPU

Operation at f = 8.38 MHz

PCC1

X

0

1

f

X

0.24

0.96

µ

s

f

/2²

µ

Caution Be sure to clear bits 0 and 2 to 7 to 0.

Remark f^X: System clock oscillation frequency

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CHAPTER 5 CLOCK GENERATOR

5.4 System Clock Oscillator

5.4.1 System clock oscillator

The system clock oscillator is oscillated by the crystal or ceramic resonator (8.38 MHz TYP.) connected across

the X1 and X2 pins.

Figure 5-3 shows the external circuit of the system clock oscillator.

Figure 5-3. External Circuit of System Clock Oscillator

Crystal or ceramic oscillation

V

SS

X1

X2

Crystal or

ceramic resonator

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken

lines in Figure 5-3 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a

line through which a high fluctuating current flows.

• Always make the ground of the capacitor of the oscillator the same potential as V^SS. Do not

ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Figure 5-4 shows examples of incorrect resonator connection.

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CHAPTER 5 CLOCK GENERATOR

Figure 5-4. Examples of Incorrect Resonator Connection (1/2)

(a) Too long Wiring

(b) Crossed signal line

PORTn

(n = 0 to 2, 6)

VSS

X1

X2

VSS

X1

X2

(c) Wiring near high fluctuating current

(d) Current flowing through ground line of oscillator

(potential at points A, B, and C fluctuates)

V

DD

P

mn

VSS

X1

X2

X1

X2

V

SS

High current

A

B

C

High current

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CHAPTER 5 CLOCK GENERATOR

Figure 5-4. Examples of Incorrect Resonator Connection (2/2)

(e) Signals are fetched

VSS

X1

X2

5.4.2 Divider

The divider generates clocks by dividing the system clock oscillator output (f^X).

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CHAPTER 5 CLOCK GENERATOR

5.5 Clock Generator Operation

The clock generator generates the following clocks and controls the operation modes of the CPU, such as

standby mode.

• System clock

• CPU clock

f^X

f^CPU

• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC), as follows.

(a) The slow mode (0.96 µs: at 8.38 MHz operation) of the system clock is selected when the RESET

signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the

system clock is stopped.

(b) Two types of minimum instruction execution time (0.24 µs and 0.96 µs: at 8.38 MHz operation) can be

selected by setting PCC.

(c) Two standby modes, STOP and HALT, can be used.

(d) The clock pulse for the peripheral hardware is generated by dividing the frequency of the system clock.

Therefore, the peripheral hardware stops when the system clock stops.

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CHAPTER 5 CLOCK GENERATOR

5.6 Changing Setting of CPU Clock

5.6.1 Time required for switching CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).

Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock

is used for the duration of several instructions after that (see Table 5-2).

Table 5-2. Maximum Time Required for Switching CPU Clock

Set Value Before Switching

PCC1

Set Value After Switching

PCC1

1

0

1

4 clocks

2 clocks

Remark Two clocks is the minimum instruction execution time of the CPU clock before switching.

5.6.2 Switching CPU clock

The following figure illustrates how the CPU clock switches.

Figure 5-5. Switching Between System Clock and CPU Clock

V

DD

RESET

CPU Clock

Slow

operation

Fastest operation

Wait (3.91 ms: at 8.38 MHz operation)

Internal reset operation

<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released

when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during

which oscillation stabilizes (2¹⁵/fX) is automatically secured.

After that, the CPU starts instruction execution at the slow speed of the system clock (0.96 µs: at 8.38 MHz

operation).

<2> After the time required for the V^DDvoltage to rise to the level at which the CPU can operate at high speed

has elapsed, the processor clock control register (PCC) is rewritten so that high-speed operation can be

selected.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

6.1 10-Bit Inverter Control Timer Functions

The 10-bit inverter control timer is used to control the inverter.

The 10-bit inverter control timer incorporates an 8-bit dead time generation timer and can output a waveform that

does not overlap the active level. It can output pulses on six channels, both for the positive phase and negative

phase. In addition, it is equipped with an active level change function, and an output off function that is controlled by

an external input and the watchdog timer interrupt request input.

6.2 10-Bit Inverter Control Timer Configuration

The 10-bit inverter control timer consists of the following hardware.

Table 6-1. Configuration of 10-Bit Inverter Control Timer

Item

Configuration

10-bit up/down counter × 1 (TM7)

8-bit down counter × 3 (DTM0 to DTM2)

3-bit up counter × 1 (RTM0)

Timer counters

10-bit compare register × 4 (CM0 to CM3)

Registers

10-bit buffer register × 4 (BFCM0 to BFCM3)

8-bit reload register × 1 (DTIME)

Timer outputs

6 (TO70 to TO75)

Control registers

Inverter timer control register 7 (TMC7)

Inverter timer mode register 7 (TMM7)

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

Figure 6-1. Block Diagram of 10-Bit Inverter Control Timer

f

X

f

X

/2

f

/2²

/2³

/2⁴

/2⁵

INTTM7

RTM0

TM7

10

X

f

X

BFCM3

BFCM0

BFCM1

DTIME

CM3

Output off function controlled by

external input and INTWDT

8

f

X

TO70

(U phase)

CM0

DTM0

TO71

(U phase)

Pulse

generator

DTM1

DTM2

TO72

(V phase)

CM1

CM2

TO73

(V phase)

BFCM2

TO74

(W phase)

TO75

(W phase)

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

(1) 10-bit up/down counter (TM7)

TM7 is a 10-bit up/down counter that counts count pulses.

A count operation is performed in sync with the rising edge of the count clock. Upon being started, TM7

starts counting from 0. When the value of TM7 matches the value preset in compare register 3 (CM3), TM7

stops counting up and starts counting down.

If, while TM7 is counting down, the value reaches 000H, an underflow signal is generated, as is the interrupt

request signal INTTM7. In the event of an underflow, TM7 stops counting down and starts counting up.

INTTM7 is normally generated for every underflow. Depending on the settings of the IDEV0 to IDEV2 bits of

inverter timer control register 7 (TMC7), however, the generator can be divided.

TM7 can be neither read nor written.

The cycle of TM7 is controlled by CM3.

There are six count clocks: f^X, fx/2, fx/2², fx/2³, fx/2⁴, fx/2⁵. Any one of these clocks can be selected.

TM7 is cleared to 000H upon the input of RESET or when the CE7 bit of TMC7 is cleared.

(2) 10-bit compare registers 0 to 2 (CM0 to CM2)

CM0 to CM2 are 10-bit compare registers. Normally, their contents are compared with those of TM7 and,

when they match, they change the contents of the flip-flop.

Also, each of CM0 to CM2 is provided with a buffer register (BFCM0 to BFCM2). The contents of these

buffers are transferred to CM0 to CM2 when the interrupt request signal INTTM7 is generated.

CM0 to CM2 can be written to only while TM7 is stopped.

Set the output timing by writing data to BFCM0 to BFCM2.

CM0 to CM2 are cleared to 000H upon the input of RESET or when the CE7 bit of TMC7 is cleared.

(3) 10-bit compare register 3 (CM3)

CM3 is a 10-bit compare register. It is used to control the maximum value of TM7. When the value of TM7

matches that of CM3 or reaches 0, TM7 stops counting up and starts counting down, or vice versa, at the

next count clock.

Also, CM3 is provided with a buffer register (BFCM3). The contents of this buffer are transferred to CM3

when the interrupt request signal INTTM7 is generated.

CM3 can be written to only while TM7 is stopped.

Set the cycle of TM7 by writing data to BFCM3.

The value of CM3 is cleared to 0FFH upon the input of RESET.

Do not set CM3 to 000H.

(4) 10-bit buffer registers 0 to 3 (BFCM0 to BFCM3)

BFCM0 to BFCM3 are 10-bit registers. Data is transferred from each buffer register to the corresponding

compare register (CM0 to CM3) upon the generation of the interrupt request signal INTTM7.

BFCM0 to BFCM3 can be read/written regardless of whether TM7 is counting or stopped.

Upon the input of RESET, BFCM0 to BFCM2 are set to 000H, while BFCM3 is set to 0FFH.

BFCM0 to BFCM3 can be read/written not only in word units but also in byte units. To perform

reading/writing in units of less than 8 bits, use BFCM0L to BFCM3L.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

(5) Dead time reload register (DTIME)

DTIME is an 8-bit register that is used for setting the dead time. It is used in common by the three dead time

timers (DTM0 to DTM2). Note, however, that data is loaded from DTIME into each of DTM0 to DTM2 at a

different timing.

DTIME can be written only while TM7 is not counting. Even if an instruction is issued to rewrite the contents

of DTIME while counting is being performed, the contents of DTIME will not be changed.

Upon the input of RESET, DTIME is set to FFH.

When DTIME is set to 00H, output is performed using the dead time of count clock fx.

(6) Dead time timers 0 to 2 (DTM0 to DTM2)

DTM0 to DTM2 are 8-bit down-counters that are used to generate dead time.

When the values of CM0 to CM2 and TM7 match, the value of the dead time reload register (DTIME) is

reloaded into DTM0 to DTM2, which then begin counting down again. When each of DTM0 to DTM2

changes from 00H to FFH, an underflow signal is generated and the counters stop at FFH.

The f^Xcount clock is used.

DTM0 to DTM2 can be neither read nor written.

DTM0 to DTM2 are set to FFH upon the input of RESET or when the CE7 bit of TMC7 is cleared.

(7) Buffer transmission control timer (RTM0)

RTM0 is a 3-bit up-counter. It incorporates a function for dividing the interrupt request signal INTTM7.

RTM0 is incremented when TM7 issues an underflow signal. When the value of RTM0 matches that of the

division count set in bits IDEV0 to IDEV2 of TMC7, INTTM7 is generated. RTM0 can be neither read nor

written.

RTM0 is set to 7H upon the input of RESET. RTM0 is also set to 7H upon the issuance of INTTM7, as well

as when the CE7 bit of TMC7 is cleared.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

6.3 Registers Controlling 10-Bit Inverter Control Timer

The following two registers control the 10-bit inverter control timer.

• Inverter timer control register 7 (TMC7)

• Inverter timer mode register 7 (TMM7)

(1) Inverter timer control register 7 (TMC7)

Inverter timer control register 7 (TMC7) is used to control the operation of TM7, DTM0 to DTM2, and RTM0.

It is also used to select the count clock used by the 10-bit inverter control timer, and to select the compare

register transfer cycle.

TMC7 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC7 to 00H.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

Figure 6-2. Format of Inverter Timer Control Register 7

Address After reset R/W

FFA8H 00H R/W

Symbol

TMC7

<7>

6

0

5

4

3

0

2

1

CE7

TCL72

TCL71

TCL70

IDEV2

IDEV1

IDEV0

Control of TM7, DTM0 to DTM2, RTM0

CE7

0

Clear and stop (TO70 to TO75 are Hi-Z)

Count enabled

1

Count clock selection

TCL72

TCL71

TCL70

0

1

0

1

0

1

0

1

0

1

fX

(8.38 MHz)

/2 (4.19 MHz)

/2²(2.1 MHz)

/2³(1.05 MHz)

/2⁴(524 kHz)

/2⁵(262 kHz)

Other than above

Setting prohibited

Selection of INTTM7 generation frequency

IDEV2

IDEV1

IDEV0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Generated upon each TM7 underflow (every time)

Generated upon every second TM7 underflow

Generated upon every third TM7 underflow

Generated upon every fourth TM7 underflow

Generated upon every fifth TM7 underflow

Generated upon every sixth TM7 underflow

Generated upon every seventh TM7 underflow

Generated upon every eighth TM7 underflow

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

(2) Inverter timer mode register 7 (TMM7)

Inverter timer mode register 7 (TMM7) is used to specify the active level of outputs TO70 to TO75, control

the operation, and set the valid edge of TOFF7.

TMM7 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMM7 to 00H.

Figure 6-3. Format of Inverter Timer Mode Register 7

Address After reset R/W

FFA9H 00H R/W

Symbol

TMM7

7

0

6

0

5

0

4

3

0

2

1

PNOFFB

ALV

TOEDG TOSPP TOSPW

PNOFFB^Note

Flag indicating status of TM7 output to TO70 to TO75

0

TM7 output disabled status (TO70 to TO75 are Hi-Z)

TM7 output enabled status

1

ALV

0

Specification of active level of TO70 to TO75 output

Low level

High level

1

TOEDG

0

Specification of valid edge of TOFF7

Falling edge

Rising edge

1

TOSPP

0

Control of TO70 to TO75 output stop at Valid edge

Output is not stopped

1

Output is stopped (TO70 to TO75 are Hi-Z)

TOSPW

0

Control of TO70 to TO75 output stop according to INTWDT

Output is not stopped

Output is stopped (TO70 to TO75 are Hi-Z)

1

Note The PNOFFB bit is used as a flag for reading only. It can neither be set nor reset by software.

When TM7 is stopped (CE7 = 0), or operating (CE7 = 1), PNOFFB is reset when output is stopped by

either TOFF7 or INTWDT.

Caution Be sure to clear bits 5 to 7 to 0.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

Remarks 1. TO70 to TO75 enter the Hi-Z status in the following cases. Note, however, that if CE7 = 1, timers

TM7, DTM0 to DTM2, and RTM0 do not stop.

• When TOSPP = 1, and the valid edge is input to the TOFF7 pin

• When TOSPW = 1, and the specified interrupt request is generated

To restore the outputs of TO70 to TO75, apply the following procedure.

<1> Write 0 to CE7 and then stop each timer.

<2> Write 0 to the flags of those functions whose output is stopped

<3> Re-set each of the registers to their default values.

2. PNOFFB, ALV, CE7, and TO70 to TO75 are related as follows.

PNOFFFB

ALV

0/1

CE7

1

TO70, TO72, TO74

Hi-Z

TO71, TO73, TO75

Hi-Z

Other than below

1

PWM waveform cycle

(positive phase)

PWM waveform cycle

(negative phase)

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

6.4 10-Bit Inverter Control Timer Operation

(1) Setting procedure

<1> Using bits TCL70 to TCL72 of inverter timer control register 7 (TMC7), set the count clock of TM7.

Using bits IDEV0 to IDEV2, set the frequency at which the interrupt request signal INTTM7 is

generated.

<2> Using the ALV bit of inverter timer mode register 7 (TMM7), set the active level for pins TO70 to TO75.

<3> Set the half-cycle width of the first PWM cycle in CM3.

• PWM frequency = CM3 value × 2 × TM7 clock rate

(The TM7 clock rate is set using TMC7.)

<4> Set the half-cycle width of the second PWM cycle in 10-bit buffer register 3 (BFCM3).

<5> Set the dead time width in the dead time reload register (DTIME).

• Dead time width = (DTIME+1) × f^X

fX: internal system clock

<6> Set the flip-flop set/reset timing used for the first cycle in CM0 to CM2.

<7> Set the flip-flop set/reset timing used for the second cycle in BFCM0 to BFCM2.

<8> Set the CE7 bit of TMC7 to 1. This enables the operation of TM7, dead time timers 0 to 2 (DTM0 to

DTM2), and the buffer transmission control timer (RTM0).

Caution A bit manipulation instruction must be used to set the CE7 bit.

<9> While TM7 is operating, set the half-cycle width of the next PWM cycle in BFCM3.

<10> While TM7 is operating, set the flip-flop set/reset timing used for the next frequency in BFCM0 to

BFCM2.

<11> When the operation of TM7 is stopped, clear the CE7 bit of TMC7 to 0.

Caution Note that it is not possible to change the value of another bit while the CE7 bit is

being set.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

(2) Correspondence between of output waveform width and set value

• PWM cycle = CM3 × 2 × T^TM7

• Dead time width TDTM = (DTIME + 1) × fX

• Active width of positive phase (TO70, TO72, TO74 pins)

= { (CM3 - CM^up) + (CM3 - CMdown) } × TTM7 - TDTM

• Active width of negative phase (TO71, TO73, TO75 pins)

= (CM^down+ CMup) × TTM7 - TDTM

f^X:

System clock oscillation frequency

TM7 count clock

T^TM7:

CM^up:

Value set in CM0 to CM2 when TM7 is counting up.

CM^down: Value set in CM0 to CM2 when TM7 is counting down.

Caution When "0" or "minus" is set for the active width of the positive or negative phase, TO70 to TO75

output a fixed inactive level waveform with an active width of "0".

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

(3) Operation timing

Figure 6-4. TM7 Operation Timing (Basic Operation)

Y

X

b

TM7

0

a

c

BFCMn

CMn

b

a

c

b

BFCM3

CM3

Y

X

Z

Y

Z

INTTM7

Flip-flop

DTMn

INTTM7

TO70, TO72,

TO74

TO71, TO73,

TO75

t

Remarks 1. n = 0 to 2

2. t: Dead time = (DTIME + 1) × f^X

(fX: System clock oscillation frequency)

3. The above diagram shows the active-high state when the generation of INTTM7 is not divided.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

Figure 6-5. TM7 Operation Timing (CMn (BFCMn) ≥ CM3 (BFCM3))

Y

X

TM7

0

a

c

BFCMn

CMn

b

a

c

b (≥ Y)

BFCM3

CM3

Y

X

Z

Y

Z

INTTM7

Flip-flop

DTMn

INTTM7

TO70, TO72,

TO74

TO71, TO73,

TO75

t

Remarks 1. n = 0 to 2

2. t: Dead time = (DTIME + 1) × f

(f : System clock oscillation frequency)

3. The above diagram illustrates the active-high state when the generation of INTTM7 is not divided.

X

When BFCMn is set to a larger value than that set in CM3, a low level is output in the positive phase (TO70,

TO72, and TO74 pins), while a high level is output in the negative phase (TO71, TO73, and TO75 pins).

This setting is effective for inverter control, when you wish to output a low width or high width that exceeds

the PWM period.

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CHAPTER 6 10-BIT INVERTER CONTROL TIMER

Figure 6-6. TM7 Operation Timing (CMn (BFCMn) = 000H)

Y

Z

X

c

TM7

0

a

c (> 0)

BFCMn

CMn

b

a

d

c

b = 00H

d

Z

Y

BFCM3

CM3

Y

X

Z

INTTM7

Flip-flop

DTMn

TO70, TO72,

TO74

TO71, TO73,

TO75

t

Remarks 1. n = 0 to 2

2. t: Dead time = (DTIME + 1) × f^X

(f^X: System clock oscillation frequency)

3. The above diagram illustrates the active-high state when the generation of INTTM7 is not divided.

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Figure 6-7. TM7 Operation Timing (CMn (BFCMn) = CM3 - 1/2DTM, CMn (BFCMn) > CM3 - 1/2DTM)

Y

b

X

a

TM7

0

c

BFCMn

CMn

b

a (= X − 1/2DTM)

c

b (> Y − 1/2 DTM)

BFCM3

CM3

Y

X

Z

Y

Z

INTTM7

Flip-flop

DTMn

INTTM7

TO70, TO72,

TO74

"L"

TO71, TO73,

TO75

Remarks 1. n = 0 to 2

2. The above diagram illustrates the active-high state, when the generation of INTTM7 is not divided.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

7.1 Functions of 8-Bit Timer/Event Counters 80, 81, 82

The 8-bit timer/event counters (TM80, TM81, TM82) have the following functions.

• Interval timer (TM80, TM81, TM82)

• External event counter (TM80, TM81 only)

• Square-wave output (TM82 only)

The µPD789842 Subseries features a built-in 2-channel 8-bit timer/event counter (TM80, TM81) and a single-

channel 8-bit timer (TM82). For TM82, therefore, replace all references to "timer event counter" with "timer."

(1) 8-bit interval timer

When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any preset time

interval.

Table 7-1. Interval Time of 8-Bit Timer/Event Counter 80

Minimum Interval Time

2⁶/fX (7.64 µs)

2⁹/fX (61.1 µs)

Maximum Interval Time

2¹⁴/fX (1.96 ms)

2¹⁷/fX (15.6 ms)

Resolution

2⁶/fX (7.64 µs)

2⁹/fX (61.1 µs)

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

Table 7-2. Interval Time of 8-Bit Timer/Event Counter 81

Minimum Interval Time

2⁴/fX (1.91 µs)

2⁸/fX (30.5 µs)

Maximum Interval Time

2¹²/fX (0.49 ms)

2¹⁶/fX (7.82 ms)

Resolution

2⁴/fX (1.91 µs)

2⁸/fX (30.5 µs)

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

Table 7-3. Interval Time of 8-Bit Timer 82

Minimum Interval Time

2³/fX (0.95 µs)

Maximum Interval Time

2¹¹/fX (0.24 ms)

Resolution

2³/fX (0.95 µs)

2⁷/fX (15.3 µs)

2¹⁵/fX (3.91 ms)

2¹⁸/fX (31.3 ms)

2¹⁰/fX (0.12 ms)

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

(2) External event counter

The number of pulses of an externally input signal can be measured.

(3) Square-wave output

A square wave of arbitrary frequency can be output.

Table 7-4. Square-Wave Output Range of 8-Bit Timer 82

Minimum Interval Time

2³/fX (0.95 µs)

Maximum Interval Time

2¹¹/fX (0.24 ms)

Resolution

2³/fX (0.95 µs)

2⁷/fX (15.3 µs)

2¹⁵/fX (3.91 ms)

2¹⁸/fX (31.3 ms)

2¹⁰/fX (0.12 ms)

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

7.2 Configuration of 8-Bit Timer/Event Counters 80, 81, 82

8-bit timer/event counters 80, 81, and 82 consist of the following hardware.

Table 7-5. Configuration of 8-Bit Timer/Event Counters 80, 81, 82

Item

Timer counter

Register

Configuration

8 bits × 3 (TM80 to TM82)

Compare register: 8 bits × 3 (CR80 to CR82)

1 (TO82)

Timer output

Control registers

8-bit timer mode control registers 80 to 82 (TMC80 to TMC82)

Port mode register 2 (PM2)

Port register 2 (P2)

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 80

Internal bus

8-bit compare register 80

(CR80)

Match

INTTM80

f

X

/2⁶

/2⁹

8-bit timer counter 80

(TM80)

Clear

TI80/P24

/INTP0

Selector

2

TCE0 TCL01 TCL00

8-bit timer mode control

register 80 (TMC80)

Internal bus

Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 81

Internal bus

8-bit compare register 81

(CR81)

Match

INTTM81

f

X

/2⁴

/2⁸

8-bit timer counter 81

(TM81)

Clear

TI81/P25

/INTP1

Selector

2

TCL11 TCL10

TCE1

8-bit timer mode control

register 81 (TMC81)

Internal bus

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

Figure 7-3. Block Diagram of 8-Bit Timer 82

Internal bus

8-bit compare register 82

(CR82)

P23

output latch

PM23

Match

INTTM82

TO82/P23

f

X

/2³

/2⁷

8-bit timer counter 82

(TM82)

Flip-

flop

f

/2¹⁰

Clear

Selector

fX

2

TCE2 TCL21 TCL20 TOE2

8-bit timer mode control

register 82 (TMC82)

(1) 8-bit compare register 8n (CR8n)

The value specified by CR8n is compared with the count in 8-bit timer counter 8n (TM8n). If they match, an

interrupt request (INTTM8n) is issued.

CR8n is manipulated with an 8-bit memory manipulation instruction. Any value from 00H to FFH can be set.

RESET input makes CR8n undefined.

Caution Be sure to stop the operation of the timer before rewriting CR8n. If CR8n is rewritten while

the timer is operation-enabled, an interrupt request match signal may be generated at the

time of the rewrite.

Remark n = 0 to 2

(2) 8-bit timer counter 8n (TM8n)

TM8n is used to count the number of pulses.

Its contents are read with an 8-bit memory manipulation instruction.

RESET input clears TM8n to 00H.

Remark n = 0 to 2

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

7.3 Registers Controlling 8-Bit Timer/Event Counters 80, 81, 82

The following three types of registers are used to control 8-bit timer/event counters 80, 81, and 82.

• 8-bit timer mode control registers 80 to 82 (TMC80 to TMC82)

• Port mode register 2 (PM2)

• Port register 2 (P2)

(1) 8-bit timer mode control register 80 (TMC80)

TMC80 determines whether to enable or disable 8-bit timer counter 80 (TM80) and specifies the count clock

for 8-bit timer/event counter 80.

TMC80 is manipulated with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC80 to 00H.

Figure 7-4. Format of 8-Bit Timer Mode Control Register 80

Symbol

TMC80

<7>

6

0

5

0

4

0

3

0

2

1

0

Address

FF53H

After reset

00H

R/W

TCE0

TCL01

TCL00

TCE0

8-bit timer counter 80 operation control

0

1

Operation disabled (TM80 is cleared to 00H)

Operation enabled

TCL01

TCL00

8-bit timer/event counter 80 count clock selection

/2⁶(131 kHz)

/2⁹(16.4 kHz)

0

1

0

1

0

1

f

X

Rising edge of TI80

Falling edge of TI80

Cautions 1. Be sure to clear bits 0 and 3 to 6 to 0.

2. Always stop the timer before setting TMC80.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

(2) 8-bit timer mode control register 81 (TMC81)

TMC81 determines whether to enable or disable 8-bit timer counter 81 (TM81) and specifies the count clock

for 8-bit timer/event counter 81.

TMC81 is manipulated with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC81 to 00H.

Figure 7-5. Format of 8-Bit Timer Mode Control Register 81

Symbol

TMC81

<7>

6

0

5

0

4

0

3

0

2

1

0

Address

FF57H

After reset

00H

R/W

TCE1

TCL11

TCL10

TCE1

8-bit timer counter 81 operation control

0

1

Operation disabled (TM81 is cleared to 00H)

Operation enabled

TCL11

TCL10

8-bit timer/event counter 81 count clock selection

/2⁴(524 kHz)

/2⁸(32.7 kHz)

0

1

0

1

0

1

f

X

Rising edge of TI81

Falling edge of TI81

Cautions 1. Be sure to clear bits 0 and 3 to 6 to 0.

2. Always stop the timer before setting TMC81.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

(3) 8-bit timer mode control register 82 (TMC82)

TMC82 determines whether to enable or disable 8-bit timer counter 82 (TM82) and specifies the count clock

for 8-bit timer counter 82. It also controls the operation of the output controller of 8-bit timer counter 82.

TMC82 is manipulated with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC82 to 00H.

Figure 7-6. Format of 8-Bit Timer Mode Control Register 82

Symbol

TMC82

<7>

6

0

5

0

4

0

3

0

2

1

<0>

Address

FF5BH

After reset

00H

R/W

TCE2

TCL21

TCL20

TOE2

TCE2

8-bit timer counter 82 operation control

0

1

Operation disabled (TM82 is cleared to 00H)

Operation enabled

TCL21

TCL20

8-bit timer counter 82 count clock selection

/2³(1.05 MHz)

/2⁷(65.5 kHz)

/2¹⁰(8.18 kHz)

0

1

0

1

0

1

f

X

Setting prohibited

TOE2

8-bit timer 82 output control

0

1

Operation disabled (port mode)

Output enabled

Cautions 1. Be sure to clear bits 3 to 6 to 0.

2. Always stop the timer before setting TMC82.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

(4) Port mode register 2 (PM2)

PM2 specifies whether each bit of port 2 is used for input or output.

To use the P23/TO82 pin for timer output, the PM23 and P23 output latches must be reset to 0. When using

the P24/TI80/INTP0 and P25/TI81/INTP1 pins as timer inputs, set PM24 and PM25 to 1. At this time, the

output latch of P24 and P25 can be either 1 or 0.

PM2 is manipulated with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM2 to FFH.

Figure 7-7. Format of Port Mode Register 2

Symbol

PM2

7

1

6

1

5

4

3

2

1

0

Address

FF22H

After reset

FFH

R/W

PM25

PM24

PM23

PM22

PM21

PM20

PM2n

P2n pin input/output mode selection (n = 0 to 5)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

7.4 Operation of 8-Bit Timer/Event Counters 80, 81, 82

7.4.1 Operation as interval timer

The interval timer repeatedly generates an interrupt at time intervals specified by the count value preset to 8-bit

compare registers 80, 81, and 82 (CR80, CR08, and CR82).

To operate the 8-bit timer/event counter as an interval timer, make the settings in the following order.

<1> Set 8-bit timer counter 8n (TM8n) to operation-disabled (TCEn (bit 7 of 8-bit timer mode control register 8n

(TMC8n)) = 0)

<2> Select the count clock of the 8-bit timer/event counter (see Tables 7-6 to 7-8)

<3> Set the count value to CR8n

<4> Set TM8n to operation-enabled (TCEn = 1)

When the count value of 8-bit timer counter 8n (TM8n) matches the value set to CR8n, the value of TM8n is

cleared to 00H and TM8n continues counting. At the same time, an interrupt request signal (INTTM8n) is generated.

Tables 7-6 to 7-8 show the interval time, and Figure 7-8 shows the timing of interval timer operation.

Caution When the setting of the count clock using TMC8n and the setting of TM8n to operation-enabled

using an 8-bit memory manipulation instruction are performed at the same time, an error of one

clock or more may occur in the first cycle after the timer is started. Because of this, when the 8-

bit timer/event counter operates as an interval timer, be sure to make the settings in the order

described above.

Remark n = 0 to 2

Table 7-6. Interval Time of 8-Bit Timer/Event Counter 80

TCL01

TCL00

Minimum Interval Time

2⁶/fX (7.64 µs)

Maximum Interval Time

2¹⁴/fX (1.96 ms)

Resolution

2⁶/fX (7.64 µs)

0

1

0

1

0

1

2⁹/fX (61.1 µs)

2¹⁷/fX (15.6 ms)

2⁸× TI80 input cycle

TI80 input cycle

TI80 input edge cycle

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

Table 7-7. Interval Time of 8-Bit Timer/Event Counter 81

TCL11

TCL10

Minimum Interval Time

2⁴/fX (19.1 µs)

Maximum Interval Time

2¹²/fX (0.49 ms)

Resolution

2⁴/fX (1.91 µs)

0

1

0

1

0

1

2⁸/fX (30.5 µs)

2¹⁶/fX (7.82 ms)

2⁸× TI81 input cycle

TI81 input cycle

TI81 input edge cycle

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

Table 7-8. Interval Time of 8-Bit Timer 82

TCL21

TCL20

Minimum Interval Time

2³/fX (0.95 µs)

Maximum Interval Time

2¹¹/fX (0.24 ms)

Resolution

2³/fX (0.95 µs)

0

1

0

1

0

1

2⁷/fX (15.3 µs)

2¹⁵/fX (3.91 ms)

2¹⁰/fX (0.12 ms)

2¹⁸/fX (31.3 ms)

2¹⁰/fX (0.12 ms)

Setting prohibited

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

Figure 7-8. Interval Timer Operation Timing of TM80, TM81, TM82

t

Count clock

TM8n count value

00

01

N

00

01

N

00

01

N

Clear

CR8n

N

TCEn

Count start

INTTM8n

Interrupt acknowledged

Interval time

Interrupt acknowledged

Interval time

Remarks 1. Interval time = (N + 1) × t : N = 00H to FFH

2. n = 0 to 2

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

7.4.2 Operation as external event counter^Note

The external event counter counts the number of external clock pulses input to the TI80/P24/INTP0 and

TI81/P25/INTP1 pins by using 8-bit timer counters 80 and 81 (TM80 and TM81).

To operate the 8-bit timer/event counter as an external event counter, make the settings in the following order.

<1> Set P24 and P25 to input mode (PM24 = 1, PM25 = 1)

<2> Set 8-bit timer counter 8n (TM08) to operation-disabled (TCEn (bit 7 of 8-bit timer mode control register 8n

(TMC8n)) = 0)

<3> Specify the rising edge/falling edge of TI8n (see Figures 7-4 and 7-5)

<4> Set the count value to CR8n

<5> Set TM8n to operation-enabled (TCEn = 1)

Note This function is only for TM80 and TM81.

Each time the valid edge specified by bit 1 (TCLn0) of TMC8n is input, the value of 8-bit timer counter 8n (TM8n)

is incremented.

When the count value of TM8n matches the value set to CR8n, the value of TM8n is cleared to 00H and TM8n

continues counting. At the same time, an interrupt request signal (INTTM8n) is generated.

Figure 7-9 shows the timing of external event counter operation (with rising edge specified).

Caution When the setting of the count clock using TMC8n and the setting of TM8n to operation-enabled

using an 8-bit memory manipulation instruction are performed at the same time, an error of one

clock or more may occur in the first cycle after the timer is started. Because of this, when the 8-

bit timer/event counter operates as an external event counter, be sure to make the settings in

the order described above.

Remark n = 0, 1

Figure 7-9. External Event Counter Operation Timing (with Rising Edge Specified)

TI8n pin input

TM8n count value

CR8n

00

02

04

05

N

00

02

03

01

03

N - 1

01

TCEn

INTTM8n

Remarks 1. N = 00H to FFH

2. n = 0, 1

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

7.4.3 Operation as square-wave output^Note

The 8-bit timer/event counter can generate a square-wave output of any frequency at intervals specified by the

count value preset to 8-bit compare register 82 (CR82).

To operate 8-bit timer counter 82 as a square-wave output, make the settings in the following order.

<1> Set P23 to output mode (PM23 = 0), and set the output latch of P23 to 0

<2> Set 8-bit timer counter 82 (TM82) to operation-disabled (TCE2 (bit 0 of 8-bit timer mode control register 82

(TMC82)) = 1)

<3> Set the count clock of 8-bit timer 82 (see Table 7-9), and set TO82 to output-enabled (TOE2 (bit 0 of

TMC82) = 1)

<4> Set the count value to CR82

<5> Set TM82 to operation-enabled (TCE2 = 1)

Note This function is only for TM82.

When the count value of 8-bit timer counter 82 (TM82) matches the value set in CR82, the TO82/P23 pin output

will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a

match occurs, the TM82 value is cleared to 00H, counting continues, and an interrupt request signal (INTTM82) is

generated.

Setting bit 7 of TMC82 (TCE2) to 0 clears the square-wave output to 0.

Table 7-9 lists the square-wave output range, and Figure 7-10 shows the timing of square-wave output.

Caution When the setting of the count clock using TMC82 and the setting of TM82 to operation-enabled

using an 8-bit memory manipulation instruction are performed at the same time, an error of one

clock or more may occur in the first cycle after the timer is started. Because of this, when the 8-

bit timer/event counter operates as a square-wave output, be sure to make the settings in the

order described above.

Table 7-9. Square-Wave Output Range of 8-Bit Timer 82

TCL21

TCL20

Minimum Pulse Width

2³/fX (0.95 µs)

Maximum Pulse Width

2¹¹/fX (0.24 ms)

Resolution

2³/fX (0.95 µs)

0

1

0

1

0

1

2⁷/fX (15.3 µs)

2¹⁵/fX (3.91 ms)

2¹⁰/fX (0.12 ms)

2¹⁸/fX (31.3 ms)

2¹⁰/fX (0.12 ms)

Setting prohibited

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

Figure 7-10. Square-Wave Output Timing

t

Count clock

TM82 count value

00

01

N

00

01

N

00

01

N

Clear

CR82

N

TCE2

Count start

INTTM82

Interrupt acknowledged

TO82^Note

Interval time

Note The initial value of TO82 when output is enabled (TOE2 = 1) becomes low level.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

7.5 Notes on Using 8-Bit Timer/Event Counters 80, 81, 82

(1) Error on starting timer

An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being

generated. This is because the rising edge is detected and the counter is incremented if the timer is started

while the count clock is high (see Figure 7-11).

Figure 7-11. Case of Error Occurrence of up to 1.5 Clocks

Delay A

Count

pulse

8-bit timer counter 8n

(TM8n)

Selected clock

TCEn

Clear signal

Delay B

Selected clock

TCEn

Clear signal

Count pulse

TM8n count value

00H

01H

02H

03H

Delay A

Delay B

An error of up to 1.5 clocks occurs if the timer is started

when the selected clock is high and delay A > delay B.

Remark n = 0 to 2

(2) Count value if external clock input from TI8n pin is selected

When the rising edge of the external clock signal input from the TI8n pin is selected as the count clock, the

count value may start from 01H if the timer is enabled (TCEn = 0 → 1) while the TI8n pin is high. This is

because the input signal of the TI8n pin is internally ANDed with the TCEn signal. Consequently, the

counter is incremented because the rising edge of the count clock is input to the timer immediately when the

TCEn pin is set. Depending on the delay timing, the count value is incremented by one if the rising edge is

input after the counter is cleared. Counting is not affected if the rising edge is input before the counter is

cleared (the counter operates normally).

Similarly, when the falling edge of the external signal input from the TI8n pin is selected as the count clock,

the count value may start from 01H if the timer is enabled (TCEn = 0 → 1) while the TI8n pin is low.

Use the timer being aware that it has an error of one count, or take either of the following actions A or B.

<Action A> Always start the timer when the TI8n pin is low when the rising edge is selected.

Always start the timer when the TI8n pin is high when the falling edge is selected.

<Action B> Save the count value to a control register when the timer is started, subtract the count value

from the count value saved to the control register when reading the count value, and take the

result as the true count value.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

Figure 7-12. Count Operation if Timer Is Started When TI8n Is High (Rising Edge Selected)

Clear

TCEn flag

TI8n

Increment

Rising edge

detector

Counter

H

Remark n = 0, 1

(3) Setting of 8-bit compare register 8n

8-bit compare register 8n (CR8n) can be set to 00H.

Therefore, one pulse can be counted when the 8-bit timer operates as an event counter.

Figure 7-13. Timing of Count Operation of 1 Pulse

TI80, TI81 input

CR80, CR81

00H

TM80, TM81

count value

Interrupt request flag

Caution Stop the timer operation (TCEn (bit 7 of 8-bit timer mode control register 8n (TMC8n)) = 0)

before rewriting CR8n. If CR8n is rewritten while the timer operation is enabled, a match

interrupt request signal may be generated immediately at the point of rewrite.

Remark n = 0 to 2

(4) Notes on setting STOP mode

Be sure to stop the timer operation (TCEn = 0) before executing the STOP instruction.

Remark n = 0 to 2

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CHAPTER 8 WATCH TIMER

8.1 Watch Timer Functions

The watch timer has the following functions.

• Watch timer

• Interval timer

The watch and interval timers can be used at the same time.

Figure 8-1 shows a block diagram of the watch timer.

Figure 8-1. Block Diagram of Watch Timer

Clear

f

/2⁷

X

5-bit counter

INTWT

INTWTI

9-bit prescaler

f

X

f

X

f

X

f

X

f

X

f

X

2¹⁶

Clear

2¹¹2¹²2¹³2¹⁴2¹⁵

WTM4

0

WTM6 WTM5

0

WTM1

WTM0

Watch timer mode

control register (WTM)

Internal bus

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CHAPTER 8 WATCH TIMER

(1) Watch timer

The 8.38 MHz system clock is used to generate an interrupt request (INTWT) at 0.25-second intervals.

(2) Interval timer

The interval timer is used to generate an interrupt request (INTWTI) at specified intervals.

Table 8-1. Interval Generated Using Interval Timer

Interval

At fX = 8.38 MHz

2¹¹× 1/fX

2¹²× 1/fX

2¹³× 1/fX

2¹⁴× 1/fX

2¹⁵× 1/fX

2¹⁶× 1/fX

244 µs

489 µs

978 µs

1.96 ms

3.91 ms

7.82 ms

Remark f^X: System clock oscillation frequency

8.2 Watch Timer Configuration

The watch timer consists of the following hardware.

Table 8-2. Watch Timer Configuration

Item

Counter

Configuration

5 bits × 1

9 bits × 1

Prescaler

Control register

Watch timer mode control register (WTM)

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CHAPTER 8 WATCH TIMER

8.3 Register Controlling Watch Timer

The following register is used to control the watch timer.

• Watch timer mode control register (WTM)

WTM selects the count clock for the watch timer and specifies whether to enable clocking of the timer. It also

specifies the prescaler interval and how the 5-bit counter is controlled.

WTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WTM to 00H.

Figure 8-2. Format of Watch Timer Mode Control Register

Symbol

WTM

7

0

6

5

4

3

0

2

0

<1>

<0>

Address

FF4AH

After reset

00H

R/W

WTM6

WTM5

WTM4

WTM1

WTM0

WTM6

WTM5

WTM4

Prescaler interval selection

2¹¹/f

X

(244

µ

s)

0

1

0

1

0

1

0

1

0

1

2¹²/f

2¹³/f

2¹⁴/f

2¹⁵/f

2¹⁶/f

(489

(978

(1.96 ms)

(3.91 ms)

(7.82 ms)

Other than above

Setting prohibited

WTM1

Control of 5-bit counter operation

0

1

Cleared after stop

Started

WTM0

Watch timer operation

0

1

Operation disabled (both prescaler and timer cleared)

Operation enabled

Cautions 1. Be sure to clear bits 2, 3 and 7 to 0.

2. Do not change the interval time (using bits 4 to 6 (WTM4 to WTM6) of WTM) while the watch

timer is operating.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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8.4 Watch Timer Operation

8.4.1 Operation as watch timer

The 8.38 MHz system clock is used for watch timer operation at 0.25-second intervals.

The watch timer is used to generate an interrupt request at specified intervals.

By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer

starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.

Only the watch timer can be started from zero seconds by clearing WTM1 to 0 when the interval timer and watch

timer operate at the same time. In this case, however, an error of up to 2¹⁶× 1/fX may occur in the overflow (INTWT)

after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0.

8.4.2 Operation as interval timer

The interval timer is used to repeatedly generate an interrupt request at the interval specified by a count value set

in advance.

The interval can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).

Table 8-3. Interval Generated Using Interval Timer

WTM6

WTM5

WTM4

Interval

2¹¹× 1/fX

At fX = 8.38 MHz

244 µs

0

1

0

1

0

1

0

1

0

1

2¹²× 1/fX

489 µs

2¹³× 1/fX

978 µs

2¹⁴× 1/fX

1.96 ms

3.91 ms

7.82 ms

2¹⁵× 1/fX

2¹⁶× 1/fX

Other than above

Setting prohibited

Remark f^X: System clock oscillation frequency

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Figure 8-3. Watch Timer/Interval Timer Operation Timing

5-bit counter

0H

Overflow

Start

Overflow

Count clock

Watch timer

interrupt

INTWT

Watch timer interrupt time (0.25 s) Watch timer interrupt time (0.25 s)

Interval timer

interrupt

INTWTI

Interval

T

timer (T)

Caution

If the watch timer and 5-bit counter are enabled by the watch timer mode control register

(WTM) (by setting bit 0 (WTM0) of WTM to 1), the time from this setting to the occurrence of

the first interrupt request (INTWT) is not exactly the value set as the watch timer interrupt

time (0.25 s). This is because the 5-bit counter is late by one output cycle of the 9-bit

prescaler in starting counting. The second INTWT signal and those that follow are

generated exactly at the set time.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 9 WATCHDOG TIMER

9.1 Watchdog Timer Functions

The watchdog timer has the following functions.

• Watchdog timer

• Interval timer

Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode

register (WDTM) (the watchdog timer and interval timer cannot be used at the same time).

(1) Watchdog timer

The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a

non-maskable interrupt or the RESET signal can be generated.

Table 9-1. Inadvertent Loop Detection Time of Watchdog Timer

Inadvertent Loop Detection Time

At fX = 8.38 MHz

2¹¹× 1/fX

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

244 µs

977 µs

3.91 ms

15.6 ms

fX: System clock oscillation frequency

(2) Interval timer

The interval timer generates an interrupt at a preset interval.

Table 9-2. Interval Time

Interval

At fX = 8.38 MHz

2¹¹× 1/fX

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

244 µs

977 µs

3.91 ms

15.6 ms

fX: System clock oscillation frequency

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CHAPTER 9 WATCHDOG TIMER

9.2 Watchdog Timer Configuration

The watchdog timer consists of the following hardware.

Table 9-3. Configuration of Watchdog Timer

Item

Configuration

Control registers

Timer clock selection register 2 (TCL2)

Watchdog timer mode register (WDTM)

Figure 9-1. Block Diagram of Watchdog Timer

Internal bus

f

X

2⁴

TMMK4

Prescaler

f

X

2⁶

f

X

2⁸

f

X

2¹⁰

RUN

Clear

7-bit counter

INTWDT

Maskable

TMIF4

interrupt request

Controller

RESET

INTWDT

Non-maskable

interrupt request

2

WDTM4

TCL21

WDTM3

TCL22

Timer clock selection register 2

(TCL2)

Watchdog timer mode register (WDTM)

Internal bus

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CHAPTER 9 WATCHDOG TIMER

9.3 Watchdog Timer Control Registers

The following two registers are used to control the watchdog timer.

• Timer clock selection register 2 (TCL2)

• Watchdog timer mode register (WDTM)

(1) Timer clock selection register 2 (TCL2)

This register sets the watchdog timer count clock.

TCL2 is set with an 8-bit memory manipulation instruction.

RESET input clears TCL2 to 00H.

Figure 9-2. Format of Timer Clock Selection Register 2

Symbol

TCL2

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF42H

After reset

00H

R/W

TCL22

TCL21

TCL22

TCL21

Interval

Watchdog timer count clock selection

/2⁴(524.3 kHz)

2¹¹/f

2¹³/f

2¹⁵/f

2¹⁷/f

X

(244.3 µs)

fX

0

1

0

1

0

1

/2⁶(131.1 kHz)

/2⁸(32.7 kHz)

/2¹⁰(8.18 kHz)

µ

(977.6 s)

(3.91 ms)

(15.6 ms)

Other than above

Setting prohibited

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 9 WATCHDOG TIMER

(2) Watchdog timer mode register (WDTM)

This register sets an operation mode of the watchdog timer, and enables or disables counting of the

watchdog timer.

WDTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WDTM to 00H.

Figure 9-3. Format of Watchdog Timer Mode Register

Symbol

WDTM

<7>

6

0

5

0

4

3

2

0

1

0

Address

FFF9H

After reset

00H

R/W

RUN

WDTM4 WDTM3

Watchdog timer operation selection^{Note 1}

RUN

0

1

Stop counting

Clear counter and start counting

Watchdog timer operation mode selection^{Note 2}

WDTM4 WDTM3

0

1

0

1

0

1

Operation stop

Interval timer mode (overflow and maskable interrupt occur)^{Note 3}

Watchdog timer mode 1 (overflow and non-maskable interrupt occur)

Watchdog timer mode 2 (overflow occurs and reset operation started)

Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is

started, it cannot be stopped by any means other than RESET input.

2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.

3. The watchdog timer starts operations as an interval timer when RUN is set to 1.

Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to

0.8% shorter than the time set by timer clock selection register 2 (TCL2).

2. In watchdog timer mode 1 or 2, set TMMK4 (bit 0 of interrupt mask flag register 0 (MK0)) to 1

after confirming that TMIF4 (bit 0 of interrupt request flag register 0 (IF0)) is set to 0. When

watchdog timer mode 1 or 2 is selected under the condition where TMIF4 is 1, a non-

maskable interrupt request occurs at the completion of rewriting.

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9.4 Watchdog Timer Operation

9.4.1 Operation as watchdog timer

The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode

register (WDTM) is set to 1.

The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 1 and 2

(TCL21 and TCL22) of timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog

timer is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has

been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and

the inadvertent loop detection time is exceeded, the system is reset or a non-maskable interrupt request is generated

by the value of bit 3 (WDTM3) of WDTM.

The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, set RUN to 1 before

entering STOP mode to clear the watchdog timer, and then execute the STOP instruction.

Caution The actual inadvertent loop detection time may be up to 0.8% shorter than the set time.

Table 9-4. Inadvertent Loop Detection Time of Watchdog Timer

TCL22

TCL21

Inadvertent Loop Detection Time

At fX = 8.38 MHz

244 µs

2¹¹× 1/fX

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

0

1

0

1

0

1

977 µs

3.91 ms

15.6 ms

fX: System clock oscillation frequency

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9.4.2 Operation as interval timer

When bits 4 and 3 (WDTM4 and WDTM3) of watching timer mode register (WDTM) are set to 0 and 1,

respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt request at

intervals specified by a count value set in advance.

Select the count clock (or interval) by setting bits 1 and 2 (TCL21 and TCL22) of timer clock selection register 2

(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.

In interval timer mode, the interrupt mask flag (TMMK4: bit 0 of interrupt mask flag register 0 (MK0)) is valid, and

a maskable interrupt request (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the

maskable interrupts.

The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, set RUN to 1 before

entering STOP mode to clear the interval timer, and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), the

interval timer mode is not set unless the RESET signal is input.

2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the

set time.

Table 9-5. Interval Time of Interval Timer

TCL22

TCL21

Interval

At fX = 8.38 MHz

244 µs

2¹¹× 1/fX

2¹³× 1/fX

2¹⁵× 1/fX

2¹⁷× 1/fX

0

1

0

1

0

1

977 µs

3.91 ms

15.6 ms

fX: System clock oscillation frequency

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CHAPTER 10 A/D CONVERTER

10.1 A/D Converter Functions

The A/D converter is an 8-bit resolution converter used to convert an analog input into a digital signal. This

converter can control the analog inputs of up to eight channels (ANI0 to ANI7).

A/D conversion can be started only by software.

One of analog inputs ANI0 to ANI7 is selected for A/D conversion. A/D conversion is performed repeatedly, with

an interrupt request (INTAD) being issued each time an A/D conversion is completed.

10.2 A/D Converter Configuration

The A/D converter consists of the following hardware.

Table 10-1. Configuration of A/D Converter

Item

Analog input

Configuration

8 channels (ANI0 to ANI7)

Registers

Successive approximation register (SAR)

A/D conversion result register (ADCRH)

Control registers

A/D converter mode register (ADM)

A/D input selection register (ADS)

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CHAPTER 10 A/D CONVERTER

Figure 10-1. Block Diagram of A/D Converter

AV^DD

P-ch

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

Sample & hold circuit

Voltage comparator

AVSS

AV^SS

Successive

approximation

register (SAR)

Controller

INTAD

A/D conversion result

register (ADCRH)

3

ADS2 ADS1 ADS0

ADCS FR2

FR1

FR0

A/D input selection

register (ADS)

A/D converter mode

register (ADM)

Internal bus

(1) Successive approximation register (SAR)

SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison

voltage), received from the series resistor string, starting from the most significant bit (MSB).

Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D

conversion, SAR sends its contents to the A/D conversion result register (ADCRH).

(2) A/D conversion result register (ADCRH)

ADCRH holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received

from the successive approximation register is loaded into ADCRH, which is an 8-bit register.

ADCRH can be read with an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

(3) Sample & hold circuit

The sample & hold circuit samples the input signal of the analog input pin that is selected by the selector

when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion.

(4) Voltage comparator

The voltage comparator compares an sampled analog input voltage with the voltage output by the series

resistor string.

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(5) Series resistor string

The series resistor string is configured between AV^DDand AVSS. It generates the reference voltages against

which analog inputs are compared.

(6) ANI0 to ANI7 pins

The ANI0 to ANI7 pins are the 8-channel analog input pins for the A/D converter. They are used to receive

the analog signals for A/D conversion.

Cautions 1. Do not supply the ANI0 to ANI7 pins with voltages that fall outside the rated range. If a

voltage of AV^DDor higher or AVSS or lower (even if within the absolute maximum

ratings) is supplied to any of these pins, the conversion value for the corresponding

channel will be undefined. Furthermore, the conversion values for the other channels

may also be affected.

2. The analog input pins (ANI0 to ANI7) also function as input port pins (P60 to P67).

When A/D conversion is performed with any of the ANI0 to ANI7 pins selected, be sure

not to execute an instruction that inputs data to port 6 while conversion is in progress,

as this may reduce the conversion resolution.

Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D

conversion, the expected A/D conversion value may not be obtained due to coupling

noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D

conversion.

(7) AV^SSpin

The AV^SSpin is the ground potential pin for the A/D converter. This pin must be held at the same potential

as the V^SSpin, even while the A/D converter is not being used.

(8) AV^DDpin

The AV^DDpin is the analog power supply pin for the A/D converter. This pin must be held at the same

potential as the V^DDpin, even while the A/D converter is not being used.

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10.3 Registers Controlling A/D Converter

The following two registers are used to control the A/D converter.

• A/D converter mode register (ADM)

• A/D input selection register (ADS)

(1) A/D converter mode register (ADM)

ADM specifies the conversion time for analog inputs. It also specifies whether to enable conversion.

ADM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ADM to 00H.

Figure 10-2. Format of A/D Converter Mode Register

Symbol

ADM

<7>

6

0

5

4

3

2

0

1

0

Address

FF80H

After reset

00H

R/W

ADCS

FR2

FR1

FR0

ADCS

A/D conversion control

0

1

Conversion disabled

Conversion enabled

A/D conversion time selection^{Note 1}

FR2

0

FR1

0

FR0

0

288/f

X

(34.4

(28.6

(22.9

(17.1

µ

s)

0

1

240/f

192/f

144/f

120/f

0

1

0

1

0

1

0

1

(14.3 s)

µ

(Setting prohibited^{Note 2}

)

1

0

96/f

X

Other than above

Setting prohibited

Notes 1. The specifications of FR2, FR1, and FR0 must be such that the A/D conversion time is at least 14 µs.

2. These bit combinations must not be used, as the A/D conversion time will fall below 14 µs.

Cautions 1. The result of conversion performed immediately after bit 7 (ADCS) is set may be undefined.

2. The conversion result may be undefined after ADCS has been cleared to 0 (For details, see

10.5 (5)).

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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CHAPTER 10 A/D CONVERTER

(2) A/D input selection register (ADS)

ADS specifies the port used to input the analog voltage to be converted to a digital signal.

ADS is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ADS to 00H.

Figure 10-3. Format of A/D Input Selection Register

Symbol

ADS

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF84H

After reset

00H

R/W

ADS2

ADS1

ADS0

Analog input channel specification

ADS2

ADS1

ADS0

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Caution Be sure to clear bits 3 to 7 to 0.

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CHAPTER 10 A/D CONVERTER

10.4 A/D Converter Operation

10.4.1 Basic operation of A/D converter

<1> Select a channel for A/D conversion, using the A/D input selection register (ADS).

<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.

<3> Sampling continues for a certain period of time, after which the sample & hold circuit is put on hold to

keep the input analog voltage until A/D conversion is completed.

<4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string tap voltage at the

tap selector is set to half of AV^DD.

<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage

comparator. If the analog input voltage is higher than half of AV^DD, the MSB of SAR is left set. If it is

lower than half of AV^DD, the MSB is reset.

<6> Bit 6 of SAR is set automatically, and comparison shifts to the next stage. The next tap voltage of the

series resistor string is selected according to bit 7, which reflects the previous comparison result, as

follows.

• Bit 7 = 1: Three quarters of AV^DD

• Bit 7 = 0: One quarter of AV^DD

The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result of

comparison.

• Analog input voltage ≥ tap voltage: Bit 6 = 1

• Analog input voltage < tap voltage: Bit 6 = 0

<7> Comparison is repeated until bit 0 of SAR is reached.

<8> When comparison is completed for all of the eight bits, a significant digital result is left in SAR. This

value is sent to and latched in the A/D conversion result register (ADCRH). At the same time, it is

possible to generate an A/D conversion end interrupt request (INTAD).

Cautions 1. The first A/D conversion value immediately after A/D conversion has been started is

undefined.

2. In standby mode, A/D converter operation is stopped.

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CHAPTER 10 A/D CONVERTER

Figure 10-4. Basic Operation of A/D Converter

Conversion time

Sampling

time

A/D converter

operation

Sampling

A/D conversion

C0H

or

40H

Conversion

result

SAR

ADCRH

INTAD

80H

Undefined

Conversion

result

A/D conversion continues until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset to 0 by software.

If an attempt is made to write to ADM or the A/D input selection register (ADS) during A/D conversion, the A/D

conversion in progress is canceled. In this case, A/D conversion is restarted from the beginning, if ADCS is set to 1.

RESET input makes the A/D conversion result register (ADCRH) undefined.

10.4.2 Input voltage and conversion result

The relationship between the analog input voltage at the analog input pins (ANI0 to ANI7) and the A/D conversion

result (A/D conversion result register (ADCRH)) is represented by:

VIN

AV^DD

ADCRH = INT (

or

× 256 + 0.5)

AVDD

256

AVDD

256

(ADCRH − 0.5) ×

≤ V^IN< (ADCRH + 0.5) ×

INT( ) : Function that returns the integer part of the parenthesized value

V^IN:

Analog input voltage

Voltage of AVDD pin

AV^DD:

ADCRH: Value in the A/D conversion result register (ADCRH)

Figure 10-5 shows the relationship between the analog input voltage and the A/D conversion result.

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Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result

255

254

253

A/D conversion

result (ADCRH)

3

2

1

0

1

3

2

5

3

507 254 509 255 511

512 256 512 256 512

1

512 256 512 256 512 256

Input voltage/AV^DD

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10.4.3 Operation mode of A/D converter

The A/D converter is initially in select mode. In this mode, the A/D input selection register (ADS) is used to select

an analog input channel from ANI0 to ANI7 for A/D conversion.

A/D conversion can be started only by software, that is, by setting the A/D converter mode register (ADM).

The A/D conversion result is saved to the A/D conversion result register (ADCRH). At the same time, an interrupt

request signal (INTAD) is generated.

• Software-started A/D conversion

Setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 triggers A/D conversion for a voltage

applied to the analog input pin specified in the A/D input selection register (ADS). Upon completion of A/D

conversion, the conversion result is saved to the A/D conversion result register (ADCRH). At the same, an

interrupt request signal (INTAD) is generated. Once A/D conversion is activated, and completed, another

session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM. If data

where ADCS is 1 is written to ADM again during A/D conversion, the session of A/D conversion in progress is

discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS is 0 is written

to ADM again during A/D conversion, A/D conversion is completely stopped.

Figure 10-6. Software-Started A/D Conversion

Rewriting ADM

ADCS = 1

Rewriting ADM

ADCS = 1

ADCS = 0

A/D conversion

ANIn

ANIm

Conversion is

discontinued;

Stop

no conversion

result is preserved.

ADCRH

INTAD

ANIn

ANIm

Undefined

Remarks 1. n = 0 to 7

2. m = 0 to 7

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10.5 Notes on Using A/D Converter

(1) Current drain in standby mode

When the A/D converter enters standby mode, it stops operating. Clearing bit 7 (ADCS) of the A/D converter

mode register (ADM) to 0 reduces the current drain.

Figure 10-7 shows how to reduce the current drain in standby mode.

Figure 10-7. How to Reduce Current Drain in Standby Mode

AVDD

ADCS

P-ch

Series resistor string

AVSS

(2) Input range for the ANI0 to ANI7 pins

Be sure to keep the input voltage at ANI0 to ANI7 within the rated range. If a voltage AV^DDor higher or AVSS

or lower (even within the absolute maximum ratings) is input to a conversion channel, the conversion output

of the channel becomes undefined. This may also affect the conversion output of the other channels.

(3) Conflict

<1> Conflict between writing to the A/D conversion result register (ADCRH) at the end of conversion and

reading from ADCRH with an instruction

Reading from ADCRH takes precedence. After reading, the new conversion result is written to ADCRH.

<2> Conflict between writing to ADCRH at the end of conversion and writing to the A/D converter mode

register (ADM) or the A/D input selection register (ADS)

Writing to ADM or ADS takes precedence. A request to write to ADCRH is ignored. No conversion end

interrupt request signal (INTAD) is generated.

(4) Conversion result immediately after start of A/D conversion

The first A/D conversion value immediately after A/D conversion has been started is undefined. Poll the A/D

conversion end interrupt request (INTAD) and discard the first conversion result.

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(5) Timing of undefined A/D conversion result

The A/D conversion value may become undefined if the timing of the completion of A/D conversion and the

timing of stopping the A/D conversion operation conflict. Therefore, read the A/D conversion result while the

A/D conversion operation is in progress. Figure 10-8 shows the timing at which the conversion result is read.

Figure 10-8. Conversion Result Read Timing (if Conversion Result Is Undefined)

End of A/D conversion

ADCRH

Normal conversion result

Undefined value

INTAD

ADCS

Reading normal conversion result

A/D conversion

stops.

Undefined value

is read.

(6) Noise prevention

To maintain a resolution of 8 bits, watch for noise at the AV^DDand ANI0 to ANI7 pins. The higher the output

impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external

capacitor to the relevant pins as shown in Figure 10-9.

Figure 10-9. Analog Input Pin Handling

If noise of AV^DDor higher or AVSS or lower is

likely to come to the AVDD pin, clamp the

voltage at the pin by attaching a diode with

a small V (0.3 V or lower).

F

V

DD

AVDD

C = 100 to 1000 pF

AV^SS

V

SS

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CHAPTER 10 A/D CONVERTER

(7) ANI0 to ANI7

The analog input pins (ANI0 to ANI7) are alternate-function pins. They are also used as port pins (P60 to

P67).

If any of ANI0 to ANI7 has been selected for A/D conversion, do not execute input instructions for the ports;

otherwise, the conversion resolution may become lower.

If a digital pulse is applied to a pin adjacent to the analog input pin in the process of A/D conversion, coupling

noise may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a

digital pulse to pins adjacent to the analog input pin undergoing A/D conversion.

(8) Input impedance of ANI0 to ANI7 pins

This A/D converter executes sampling by charging the internal sampling capacitor for approximately 1/10 of

the conversion time.

Therefore, only the leakage current flows during other than sampling, and the current for charging the

capacitor flows during sampling. The input impedance therefore varies and has no meaning.

To achieve sufficient sampling, it is recommended that the output impedance of the analog input source be

10 kΩ or less, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 10-9).

(9) Interrupt request flag (ADIF)

Changing the contents of the A/D converter mode register (ADM) does not clear ADIF (bit 4 of interrupt

request flag register 1 (IF1)).

If the analog input pins are changed during A/D conversion, therefore, the conversion result and the

conversion end interrupt request flag may reflect the previous analog input immediately before writing to

ADM occurs. In this case, ADIF may appear to be set if it is read-accessed immediately after ADM is write-

accessed, even when A/D conversion has not been completed for the new analog input.

In addition, when A/D conversion is restarted, ADIF must be cleared beforehand.

Figure 10-10. A/D Conversion End Interrupt Request Generation Timing

Rewriting to ADM

(to begin conversion

for ANIn)

Rewriting to ADM

(to begin conversion

for ANIm)

ADIF has been set, but conversion

for ANIm has not been completed.

A/D conversion

ANIn

ANIm

ANIn

ANIm

Undefined

ADCRH

INTAD

Remarks 1. n = 0 to 7

2. m = 0 to 7

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(10) AVDD pin

The AV^DDpin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to

ANI7 input circuit.

If the application is designed to be changed to backup power, the AV^DDpin must be supplied with the same

voltage level as the V^DDpin, as shown in Figure 10-11.

Figure 10-11. AV^DDPin Handling

VDD

AVDD

Backup

Main power

supply

capacitor

V

SS

AVSS

(11) Input impedance of the AV^DDpin

A series resistor string is connected across the AV^DDand AVSS pins.

If the output impedance of the reference voltage source is high, this high impedance is eventually connected

in parallel with the series resistor string across the AV^DDand AVSS pins, leading to a higher reference voltage

error.

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CHAPTER 11 SERIAL INTERFACE

11.1 Serial Interface Functions

The serial interface (UART00) has the following two modes.

•

Operation stop mode

Asynchronous serial interface (UART) mode

(1) Operation stop mode

This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.

(2) Asynchronous serial interface (UART) mode

This mode is used to transmit and receive the one byte of data that follows a start bit. It supports full-duplex

communication.

The serial interface contains a UART-dedicated baud rate generator, enabling communication over a wide

range of baud rates. The UART-dedicated baud rate generator also enables the use of a MIDI standard baud

rate (31.25 kbps).

Figure 11-1 shows a block diagram of the serial interface (UART00).

Figure 11-1. Block Diagram of Serial Interface

Internal bus

Receive buffer

register 00

TXE00 RXE00 PS001 PS000 CL00 SL00 ISRM00

(RXB00)

Asynchronous serial interface

mode register 00 (ASIM00)

Asynchronous serial interface

status register 00 (ASIS00)

Transmit

shift register 00

(TXS00)

Receive shift

register 00

(RXS00)

FE00 OVE00

PE00

P22/RxD

P21/TxD

Reception

controller

(Parity check)

INTSER00

INTSR00

Transmission

controller

INTST00

(Parity addition)

Baud rate

generator

fX X

/2²to f /2⁹

5-bit prescaler

TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000

Internal bus

Baud rate generator control

register 00 (BRGC00)

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11.2 Serial Interface Configuration

The serial interface (UART00) consists of the following hardware.

Table 11-1. Serial Interface Configuration

Item

Configuration

Registers

Transmit shift register 00 (TXS00)

Receive shift register 00 (RXS00)

Receive buffer register 00 (RXB00)

Control registers

Asynchronous serial interface mode register 00 (ASIM00)

Asynchronous serial interface status register 00 (ASIS00)

Baud rate generator control register 00 (BRGC00)

Port mode register 2 (PM2)

Port register 2 (P2)

(1) Transmit shift register 00 (TXS00)

TXS00 is a register in which transmission data is prepared. The transmit data is output from TXS00 bit-

serially.

When the data length is seven bits, bits 0 to 6 of the data in TXS00 will be transmit data. Writing data to

TXS00 triggers transmission.

TXS00 can be write-accessed, using an 8-bit memory manipulation instruction, but cannot be read-

accessed.

RESET input makes TXS00 undefined.

Caution Do not write to TXS00 during transmission.

TXS00 and receive buffer register 00 (RXB00) are mapped at the same address, so any

attempt to read from TXS00 results in a value being read from RXB00.

(2) Receive shift register 00 (RXS00)

RXS00 is a register in which serial data, received at the RxD pin, is converted to parallel data. Once one

entire byte has been received, RXS00 feeds the receive data to receive buffer register 00 (RXB00).

RXS00 cannot be manipulated directly by a program.

(3) Receive buffer register 00 (RXB00)

RXB00 is used to hold receive data. Once receive shift register 00 (RXS00) has received one entire byte of

data, it feeds that data into RXB00.

When the data length is seven bits, the receive data is sent to bits 0 to 6 of RXB00, in which the MSB is fixed

to 0.

RXB00 can be read-accessed, using an 8-bit memory manipulation instruction, but cannot be write-

accessed.

RESET input sets RXB00 to FFH.

Caution RXB00 and transmit shift register 00 (TXS00) are mapped at the same address, so any

attempt to write to RXB00 results in a value being written to TXS00.

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CHAPTER 11 SERIAL INTERFACE

(4) Transmission controller

The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the data

in transmit shift register 00 (TXS00), according to the setting of asynchronous serial interface mode register

00 (ASIM00).

(5) Reception controller

The reception controller controls reception according to the setting of asynchronous serial interface mode

register 00 (ASIM00). It also checks for errors, such as parity errors, during reception. If an error is detected,

asynchronous serial interface status register 00 (ASIS00) is set according to the status of the error.

11.3 Registers Controlling Serial Interface

The following three registers are used to control the serial interface (UART00).

•

Asynchronous serial interface mode register 00 (ASIM00)

Asynchronous serial interface status register 00 (ASIS00)

Baud rate generator control register 00 (BRGC00)

(1) Asynchronous serial interface mode register 00 (ASIM00)

ASIM00 is an 8-bit register that is used to control the serial transfer operation of the serial interface

(UART00).

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Caution When using the serial interface function (UART mode), set the related output latches to 0,

and the port mode registers (PM××) as follows.

• For reception

Set P22 (RxD) to input mode (PM22 = 1).

• For transmission

Set P21 (TxD) to output mode (PM21 = 0).

• For transmission and reception

Set P22 and P21 to input and output mode, respectively.

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Figure 11-2. Format of Asynchronous Serial Interface Mode Register 00

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FF70H

After reset

00H

R/W

TXE00

RXE00

PS001

PS000

CL00

SL00

ISRM00

TXE00

RXE00

Operation mode

Function of RxD/P22 pin

Port function (P22)

Function of TxD/P21 pin

Port function (P21)

0

1

0

1

0

1

Operation disabled

UART mode (reception only)

Serial function (RxD)

UART mode (transmission only) Port function (P22)

Serial function (TxD)

UART mode (transmission and Serial function (RxD)

reception)

PS001

PS000

Parity bit specification

0

1

No parity

At transmission, the parity bit is fixed to 0.

At reception, a parity check is not made; no parity error is reported.

1

0

1

Odd parity

Even parity

CL00

Character length specification

0

1

7 bits

8 bits

SL00

Transmission data stop bit length specification

0

1

1 bit

2 bits

ISRM00

Reception completion interrupt control at error occurrence

0

1

A reception completion interrupt request is generated at error occurrence.

A reception completion interrupt request is not generated at error occurrence.

Cautions 1. Be sure to clear bit 0 to 0.

2. When rewriting ASIM00 to the value other than the same data, stop the operation

before rewriting.

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(2) Asynchronous serial interface status register 00 (ASIS00)

ASIS00 is used to display the type of a receive error, if it occurs while UART mode is set.

ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIS00 to 00H.

Figure 11-3. Format of Asynchronous Serial Interface Status Register 00

Symbol

ASIS00

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF71H

After reset

00H

R/W

R

PE00

FE00

OVE00

PE00

Parity error flag

0

1

Parity error did not occur

Parity error occurred (when the transmission parity and reception parity did not match)

FE00

Framing error flag

Framing error did not occur

0

1

Framing error occurred^{Note 1}(when stop bit was not detected)

OVE00

Overrun error flag

0

1

Overrun error did not occur

Overrun error occurred^{Note 2}(when the next receive operation was completed before the data was read from

receive buffer register 00)

Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial

interface mode register 00 (ASIM00), the stop bit detection in the case of reception is performed

with 1 bit.

2. Until receive buffer register 00 (RXB00) is read when an overrun error occurs, an overrun error

continues to occur.

Caution Be sure to clear bits 3 to 7 to 0.

(3) Baud rate generator control register 00 (BRGC00)

BRGC00 is used to specify the serial clock for the serial interface.

BRGC00 is set with an 8-bit memory manipulation instruction.

RESET input clears BRGC00 to 00H.

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Figure 11-4. Format of Baud Rate Generator Control Register 00

Symbol

7

0

6

5

4

3

2

1

0

Address

FF72H

After reset

00H

R/W

BRGC00

TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000

TPS002 TPS001

Baud rate generator source clock (fSCK) selection

TPS000

/2²(2.10 MHz)

/2³(1.05 MHz)

/2⁴(524 kHz)

/2⁵(262 kHz)

/2⁶(131 kHz)

/2⁷(65.5 kHz)

/2⁸(32.7 kHz)

/2⁹(16.4 kHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX

MDL003 MDL002

Baud rate generator output clock selection

MDL001 MDL000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f

SCK/16

SCK/17

SCK/18

SCK/19

SCK/20

SCK/21

SCK/22

SCK/23

SCK/24

SCK/25

SCK/26

SCK/27

SCK/28

SCK/29

SCK/30

Setting prohibited

Cautions 1. Be sure to clear bit 7 to 0.

2. When writing to BRGC00 is performed during a communication operation, the output of the

baud rate generator is disrupted and communications cannot be performed normally. Be

sure not to write to BRGC00 during a communication operation.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

3. f^SCK: Source clock of the baud rate generator

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11.4 Serial Interface Operation

The serial interface (UART00) provides the following two modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

11.4.1 Operation stop mode

In operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. In this

mode, the pins can be used as normal I/O ports.

(1) Register setting

Operation mode is set by asynchronous serial interface mode register 00 (ASIM00).

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FF70H

After reset

00H

R/W

TXE00

RXE00

PS001

PS000

CL00

SL00

ISRM00

TXE00

RXE00

Operation mode

Operation disabled

UART mode (reception only)

Function of RxD/P22 pin

Port function (P22)

Function of TxD/P21 pin

Port function (P21)

0

1

0

1

0

1

Serial function (RxD)

UART mode (transmission only) Port function (P22)

Serial function (TxD)

UART mode (transmission and Serial function (RxD)

reception)

Caution Switch the operation mode after stopping both serial transmission and reception.

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11.4.2 Asynchronous serial interface (UART) mode

In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is

possible.

The serial interface contains a UART-dedicated baud rate generator that enables communications at the desired

baud rate from many options.

The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the MIDI

standard.

(1) Register setting

UART mode is set by asynchronous serial interface mode register 00 (ASIM00), asynchronous serial

interface status register 00 (ASIS00), baud rate generator control register 00 (BRGC00), port mode register

2 (PM2), and port register 2 (P2).

(a) Asynchronous serial interface mode register 00 (ASIM00)

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Caution When using the asynchronous serial interface function (UART mode), set the related

output latches to 0, and port mode register 2 (PM2) as follows.

• For reception

Set P22 (RxD) to input mode (PM22 = 1).

• For transmission

Set P21 (TxD) to output mode (PM21 = 0).

• For transmission and reception

Set P22 and P21 to input and output mode, respectively.

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Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FF70H

After reset

00H

R/W

TXE00

RXE00

PS001

PS000

CL00

SL00

ISRM00

TXE00

RXE00

Operation mode

Function of RxD/P22 pin

Port function (P22)

Function of TxD/P21 pin

Port function (P21)

0

1

0

1

0

1

Operation disabled

UART mode (reception only)

Serial function (RxD)

UART mode (transmission only) Port function (P22)

Serial function (TxD)

UART mode (transmission and Serial function (RxD)

reception)

PS001

PS000

Parity bit specification

0

1

No parity

At transmission, the parity bit is fixed to 0.

At reception, a parity check is not made; no parity error is reported.

1

0

1

Odd parity

Even parity

CL00

Character length specification

0

1

7 bits

8 bits

SL00

Transmission data stop bit length specification

0

1

1 bit

2 bits

ISRM00

Reception completion interrupt control at error occurrence

0

1

A reception completion interrupt request is generated at error occurrence.

A reception completion interrupt request is not generated at error occurrence.

Cautions 1. Be sure to clear bit 0 to 0.

2. When rewriting ASIM00 to the value other than the same data, stop the operation

before rewriting.

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(b) Asynchronous serial interface status register 00 (ASIS00)

ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIS00 to 00H.

Symbol

ASIS00

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF71H

After reset

00H

R/W

R

PE00

FE00

OVE00

PE00

Parity error flag

0

1

Parity error did not occur

Parity error occurred (when the transmission parity and reception parity did not match)

Framing error flag

FE00

0

1

Framing error did not occur

Framing error occurred^{Note 1}(when stop bit was not detected)

OVE00

Overrun error flag

Overrun error did not occur

0

1

Overrun error occurred^{Note 2}(when the next receive operation was completed before the data was read from

receive buffer register 00)

Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial

interface mode register 00 (ASIM00), the stop bit detection in the case of reception is

performed with 1 bit.

2. Until receive buffer register 00 (RXB00) is read when an overrun error occurs, an overrun

error continues to occur.

Caution Be sure to clear bits 3 to 7 to 0.

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(c) Baud rate generator control register 00 (BRGC00)

BRGC00 is set with an 8-bit memory manipulation instruction.

RESET input clears BRGC00 to 00H.

Symbol

7

0

6

5

4

3

2

1

0

Address

FF72H

After reset

00H

R/W

BRGC00

TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000

TPS002 TPS001

Baud rate generator source clock selection

TPS000

n

0

1

2

3

4

5

6

7

f

X

/2²(2.10 MHz)

/2³(1.05 MHz)

/2⁴(524 kHz)

/2⁵(262 kHz)

/2⁶(131 kHz)

/2⁷(65.5 kHz)

/2⁸(32.7 kHz)

/2⁹(16.4 kHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MDL003 MDL002

Baud rate generator output clock selection

MDL001 MDL000

k

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f

SCK/16

SCK/17

SCK/18

SCK/19

SCK/20

SCK/21

SCK/22

SCK/23

SCK/24

SCK/25

SCK/26

SCK/27

SCK/28

SCK/29

SCK/30

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Setting prohibited

Cautions 1. Be sure to clear bit 7 to 0.

2. When writing to BRGC00 is performed during a communication operation, the

output of the baud rate generator is disrupted and communications cannot be

performed normally. Be sure not to write to BRGC00 during a communication

operation.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

3. f^SCK: Source clock of the baud rate generator

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The baud rate transmit/receive clock to be generated is a divided system clock signal.

•

Generation of baud rate transmit/receive clock by means of system clock

The transmit/receive clock is generated by dividing the system clock. The baud rate generated from the

system clock is estimated by using the following expression.

fX

[Baud rate] =

[bps]

2^{n + 1}(k + 16)

f^X: System clock oscillation frequency

Table 11-2 shows the relationship between the source clock of the baud rate generator assigned to bits 4 to

6 (TPS000 to TPS002) of BRGC00, and value n.

Table 11-2. Relationship Between Source Clock of Baud Rate Generator and Value n

TPS002

TPS001

TPS000

Baud Rate Generator Source Clock Selection

fX/2²(2.10 MHz)

n

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX/2³(1.05 MHz)

fX/2⁴(524 kHz)

fX/2⁵(262 kHz)

fX/2⁶(131 kHz)

fX/2⁷(65.5 kHz)

fX/2⁸(32.7 kHz)

fX/2⁹(16.4 kHz)

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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•

Permissible error range of baud rate

The permissible error range of the baud rate is dependent upon the number of bits of one frame and the

division ratio of the counter [1/(16 + k)]. Table 11-3 shows the relationship between the system clock

and baud rate.

Table 11-3. Example of Relationship Between System Clock and Baud Rate

fX = 8.38 MHz

Error (%)

Baud Rate

[bps]

BRGC00

7BH

6BH

5BH

4BH

3BH

2BH

1BH

11H

n

8

7

6

5

4

3

2

1

k

300

600

1.0

11

1

1,200

2,400

4,800

9,600

19,200

31,250

38,400

−1.4

0BH

1.0

11

Remark f^X: System clock oscillation frequency

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(2) Communication operation

(a) Data format

The transmit/receive data format is as shown in Figure 11-5.

Figure 11-5. Format of Asynchronous Serial Interface Transmit/Receive Data

One data frame

Start

bit

Parity

bit

Stop bit

D0

D1

D3

D2

D4

D7

D5

D6

Character bit

One data frame consists of the following bits:

• Start bit: 1 bit

• Character bits: 7 bits/8 bits

• Parity bits:

• Stop bit(s) :

Even parity/odd parity/0 parity/no parity

1 bit/2 bits

The specification of the character bit length, parity selection, and stop bit length for each data frame is

carried out using asynchronous serial interface mode register 00 (ASIM00).

When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in

transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is

always “0”.

The serial transfer rate is selected by means of baud rate generator control register 00 (BRGC00).

If a serial data receive error is generated, the receive error contents can be determined by reading the

status of asynchronous serial interface status register 00 (ASIS00).

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(b) Parity types and operation

The parity bit is used to detect a bit error in the communication data. Normally, the same parity bit is

used on the transmitting side and the receiving side. With even parity and odd parity, a “1” bit (odd

number) error can be detected. With 0 parity and no parity, an error cannot be detected.

(i) Even parity

• At transmission

The transmit operation is controlled so that the number of character bits with a value of “1” in the

transmit data including parity bit is even. The parity bit value should be as follows.

The number of character bits with a value of “1” is an odd number in transmit data:

The number of character bits with a value of “1” is an even number in transmit data:

1

0

• At reception

The number of character bits with a value of “1” in the reception data including parity bit is

counted, and if the number is odd, a parity error occurs.

(ii) Odd parity

• At transmission

Opposite to even parity, the transmit operation is controlled so that the number of character bits

with a value of “1” in the transmit data including parity bit is odd. The parity bit value should be as

follows.

The number of character bits with a value of “1” is an odd number in transmit data:

The number of character bits with a value of “1” is an even number in transmit data:

0

1

• At reception

The number of character bits with a value of “1” in the receive data including parity bit is counted,

and if the number is even, a parity error occurs.

(iii) 0 parity

When transmitting, the parity bit is set to “0” irrespective of the transmit data.

When receiving, a parity bit check is not performed. Therefore, a parity error does not occur,

irrespective of whether the parity bit is set to “0” or “1”.

(iv) No parity

A parity bit is not added to the transmit data.

At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a

parity error does not occur.

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CHAPTER 11 SERIAL INTERFACE

(c) Transmission

A transmit operation is enabled by setting bit 7 (TXE00) of asynchronous serial interface mode register

00 (ASIM00) to 1, and started by writing transmit data to transmit shift register 00 (TXS00). The start bit,

parity bit, and stop bit(s) are added automatically.

When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a

transmission completion interrupt request (INTST00) is generated.

The transmission completion interrupt timing is shown in Figure 11-6.

Figure 11-6. Asynchronous Serial Interface Transmission Completion Interrupt Request Timing

(i) Stop bit length: 1

STOP

TxD (Output)

INTST00

D0

D1

D2

D6

D7

Parity

START

(ii) Stop bit length: 2

D0

D1

D2

D6

D7

Parity

TxD (Output)

INTST00

STOP

START

Caution Do not rewrite asynchronous serial interface mode register 00 (ASIM00) during a

transmit operation. If the ASIM00 register is written during transmission, subsequent

transmission may not be performed (the normal state is restored by RESET input).

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CHAPTER 11 SERIAL INTERFACE

(d) Reception

A receive operation is performed via level detection.

When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set to 1, the receive

operation is enabled and sampling of the RxD pin input is performed.

RxD pin input sampling is performed using the serial clock specified by BRGC00.

When the RxD pin input becomes low, the 5-bit counter of the baud rate generator starts counting, and

at the time when half the time determined by the specified baud rate has passed, the data sampling start

timing signal is output. If the RxD pin input sampled again as a result of this start timing signal is low, it

is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is

performed. When character data, a parity bit, and one stop bit are detected after the start bit, reception

of one frame of data ends.

When one frame of data has been received, the receive data in the shift register is transferred to receive

buffer register 00 (RXB00), and INTSR00 (reception completion interrupt request) is generated.

If the RXE00 bit is cleared to 0 during the receive operation, the receive operation is stopped

immediately. In this case, the contents of RXB00 and ASIS00 are not changed, and INTSR00 and

INTSER00 (receive error interrupt requests) are not generated.

Figure 11-7 shows the asynchronous serial interface reception completion interrupt request timing.

Figure 11-7. Asynchronous Serial Interface Reception Completion Interrupt Request Timing

STOP

D0

D1

D2

D6

D7

Parity

RxD (Input)

INTSR00

START

Caution If a receive operation is enabled when the RxD pin input is low level, a receive

operation is immediately started. Therefore, be sure to enable a receive operation after

making the RxD pin input high level.

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CHAPTER 11 SERIAL INTERFACE

(e) Receive errors

The following three errors may occur during a receive operation: a parity error, framing error, or overrun

error. If the error flag in asynchronous serial interface status register 00 (ASIS00) is set to 1 as a result

of data reception, a receive error interrupt request (INTSER00) is generated. The receive error interrupt

occurs before the reception completion interrupt request (INTSR00). Receive error causes are shown in

Table 11-4.

It is possible to determine what kind of error occurred during reception by reading the contents of

ASIS00 (see Figure11-3).

The contents of ASIS00 are cleared to 0 by reading receive buffer register 00 (RXB00) or receiving the

next data (if there is an error in the next data, the corresponding error flag is set).

Table 11-4. Receive Error Causes

Receive Errors

Parity error

Cause

Transmission-time parity specification and receive data parity do not match

Stop bit not detected

Framing error

Overrun error

Reception of next data is completed before data is read from receive buffer

register 00

Figure 11-8. Receive Error Timing

STOP

RxD (Input)

INTSR00^Note

START D0

D1

D2

D6

D7

Parity

INTSER00

(Framing error or overrun

error occurs)

INTSER00

(Parity error occurs)

Note If a receive error occurs when the ISRM00 bit is set to 1, INTSR00 is not generated.

Cautions 1. The contents of asynchronous serial interface status register 00 (ASIS00) are

cleared to 0 by reading receive buffer register 00 (RXB00) or receiving the next

data. To ascertain the error contents, read ASIS00 before reading RXB00.

2. Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If

RXB00 is not read, an overrun error will occur when the next data is received, and

the receive error state will continue indefinitely.

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CHAPTER 12 MULTIPLIER

12.1 Multiplier Function

The multiplier has the following function.

• Calculation of 10 bits × 10 bits = 20 bits

12.2 Multiplier Configuration

Figure 12-1. Block Diagram of Multiplier

Internal bus

10-Bit multiplication data

register A (MRA1H, MRA1L)

10-bit multiplication data

register B (MRB1H, MRB1L)

CPU clock

Selector

4-bit counter

Start Clear

20-bit

Adder

20-bit multiplication result storage register

(Master) (MUL1LL, MUL1LH, MUL1HL)

20-bit multiplication result

storage register (Slave)

MULSTA

MULSTS

Reset

Multiplier control

register 1 (MULC1)

Internal bus

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CHAPTER 12 MULTIPLIER

(1) 20-bit multiplication result storage registers (MUL1LL, MUL1LH, and MUL1HL)

These registers store the 20-bit result of multiplication.

MUL1LL, MUL1LH, and MUL1HL are set with an 8-bit memory manipulation instruction.

RESET input makes these registers undefined.

Figure 12-2. Format of 20-Bit Multiplication Result Storage Register

6

5

4

3

2

1

0

Address

FFA5H

After reset

Undefined

R/W

R

Symbol

7

MUL1LL

MUL1LL7 MUL1LL6 MUL1LL5

MUL1LL3 MUL1LL2 MUL1LL1 MUL1LL0

MUL1LH3 MUL1LH2 MUL1LH1 MUL1LH0

MUL1HL3 MUL1HL2 MUL1HL1 MUL1HL0

MUL1LL4

MUL1LH

MUL1HL

FFA6H

FFA7H

Undefined

R

MUL1LH7 MUL1LH6 MUL1LH5

MUL1LH4

0

(2) 10-bit multiplication data registers (MRA1H, MR1L, MRB1H, and MRB1L)

These are 10-bit multiplication data storage registers. The multiplier multiplies the value of MRA1H and

MRA1L by that of MRB1H and MRB1L.

The 10-bit data registers are set with an 8-bit memory manipulation instruction.

RESET input makes these registers undefined.

Figure 12-3. Format of 10-Bit Data Register A

6

5

4

3

2

1

0

Address

FFA1H

MRA1L3 MRA1L2 MRA1L1 MRA1L0

After reset

Undefined

R/W

W

Symbol

MRA1L

7

MRA1L7 MRA1L6 MRA1L5

MRA1L4

MRA1H

FFA2H

Undefined

W

0

MRA1H1 MRA1H0

0

Caution Be sure to clear bits 2 to 7 of MRA1H to 0.

Figure 12-4. Format of 10-Bit Data Register B

6

5

4

3

2

1

0

Address

FFA3H

MRB1L3 MRB1L2 MRB1L1 MRB1L0

After reset

Undefined

R/W

W

Symbol

MRB1L

7

MRB1L7 MRB1L6 MRB1L5

MRB1L4

MRB1H

FFA4H

Undefined

W

0

MRB1H1 MRB1H0

0

Caution Be sure to clear bits 2 to 7 of MRB1H to 0.

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CHAPTER 12 MULTIPLIER

12.3 Register Controlling Multiplier

The multiplier is controlled by the following register.

• Multiplier control register 1 (MULC1)

MULC1 indicates the operating status of the multiplier, as well as controls the multiplier.

The operation of the multiplier ends 20 × f^CPUafter it starts.

MULC1 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 12-5. Format of Multiplier Control Register 1 in Write Mode

6

0

5

0

4

0

3

0

2

0

1

0

Address

After reset

00H

R/W

W

Symbol

MULC1

7

0

MULSTA FFA0H

MULSTA

Multiplier operation start control bit

0

1

Stop operation

Start operation

Figure 12-6. Format of Multiplier Control Register 1 in Read Mode

6

0

5

0

4

0

3

0

2

0

1

0

Address

After reset

00H

R/W

R

Symbol

MULC1

7

0

MULSTS FFA0H

MULSTS

Status of multiplier

0

1

Operation terminated

Operation in progress

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CHAPTER 13 SWAPPING (SWAP)

13.1 SWAP Function

By performing four shift operations, it is possible to switch the contents of the higher four bits of swapping function

register 0 (SWP0) with the lower four bits. Figure 13-1 shows an example of swapping.

Figure 13-1. Example of Swapping

7

6

3

2

5

4

1

0

Before swapping

SWAP00

SWAP07 SWAP06 SWAP05

SWAP02 SWAP01

SWAP04 SWAP03

7

6

3

2

SWAP06

5

4

1

0

SWAP03

SWAP02

SWAP07

SWAP00

After swapping

SWAP01

SWAP05 SWAP04

13.2 SWAP Configuration

SWAP consists of the following hardware.

Table 13-1. SWAP Configuration

Item

Configuration

Register

Swapping function register 0 (SWP0)

Figure 13-2. SWAP Block Diagram

SWAP04 to SWAP07

SWAP00 to SWAP03

Internal bus (L)

Internal bus (H)

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CHAPTER 13 SWAPPING (SWAP)

(1) Swapping function register 0 (SWP0)

By writing data into SWP0 and subsequently reading it back, the contents of the higher four bits and the

lower four bits can be swapped.

SWP0 is set with an 8-bit memory manipulation instruction.

In write mode, RESET input makes SWP0 undefined.

In read mode, RESET input clears SWP0 to 00H.

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CHAPTER 14 INTERRUPT FUNCTIONS

14.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Non-maskable interrupt

This interrupt is acknowledged even when interrupts are disabled. It does not undergo interrupt priority

control and is given top priority over all other interrupt requests.

A standby release signal is generated and HALT mode is released.

The only non-maskable interrupts the interrupt request from the watchdog timer.

(2) Maskable interrupt

These interrupts undergo mask control. If two or more interrupts are simultaneously generated, each

interrupt has a predetermined priority as shown in Table 14-1.

A standby release signal is generated and STOP and HALT modes are released.

Two external interrupt request sources and 11 internal interrupt request sources are available as maskable

interrupts.

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CHAPTER 14 INTERRUPT FUNCTIONS

14.2 Interrupt Sources and Configuration

A total of 14 non-maskable and maskable interrupts are incorporated as interrupt sources.

Table 14-1. Interrupt Sources

Basic

Interrupt Source

Trigger

Vector Table

Address

Interrupt Type

Priority^{Note 1}

Internal/External

Internal

Configuration

Type^{Note 2}

Name

−

Non-maskable

interrupt

INTWDT

Watchdog timer overflow

(when watchdog timer mode 1

is selected)

0004H

(A)

(B)

Maskable

interrupt

0

INTWDT

Watchdog timer overflow

(when interval timer mode is

selected)

1

2

3

INTP0

INTP1

INTTM7

Pin input edge detection

External

Internal

0006H

0008H

000AH

(C)

(B)

Generation of underflow signal

for 10-bit inverter control timer

4

5

6

INTSER00

INTSR00

INTST00

Receive error on serial interface

(UART00)

000CH

000EH

0010H

Completion of serial interface

(UART00) reception

Completion of serial interface

(UART00) transmission

7

8

9

INTWT

Watch timer interrupt

Interval timer interrupt

0012H

0014H

0016H

INTWTI

INTTM80

Generation of match signal for

8-bit timer/event counter 80

10

11

12

INTTM81

INTTM82

INTAD

Generation of match signal for

8-bit timer/event counter 81

0018H

001AH

001CH

Generation of match signal for

8-bit timer 82

A/D conversion completion

signal

Notes 1. The priority regulates which maskable interrupt has priority when two or more maskable interrupts are

requested simultaneously. Zero signifies the highest priority and 12 the lowest.

2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 14-1.

Remark There are two interrupt sources for the watchdog timer (INTWDT): a non-maskable interrupt (internal)

and a maskable interrupt (internal). Either one (but not both) should be selected for actual use.

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CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

Vector table

address generator

Interrupt request

Standby release signal

(B) Internal maskable interrupt

Internal bus

IE

MK

Vector table

address generator

Interrupt request

IF

Standby release signal

(C) External maskable interrupt

Internal bus

INTM0

MK

IE

Vector table

address generator

Interrupt

request

Edge

detector

IF

Standby

release signal

INTM0: External interrupt mode register 0

IF:

Interrupt request flag

Interrupt enable flag

Interrupt mask flag

IE:

MK:

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CHAPTER 14 INTERRUPT FUNCTIONS

14.3 Registers Controlling Interrupt Function

The interrupt functions are controlled by the following registers.

• Interrupt request flag registers 0 and 1 (IF0 and IF1)

• Interrupt mask flag registers 0 and 1 (MK0 and MK1)

• External interrupt mode register 0 (INTM0)

• Program status word (PSW)

Table 14-2 lists the interrupt requests, corresponding interrupt request flags, and interrupt mask flags.

Table 14-2. Interrupt Request Signals and Corresponding Flags

Interrupt Request Signal

INTWDT

Interrupt Request Flag

Interrupt Mask Flag

TMIF4

PIF0

TMMK4

PMK0

INTP0

INTP1

PIF1

PMK1

INTTM7

INTSER00

INTSR00

INTST00

INTWT

TMIF7

SERIF00

SRIF00

STIF00

WTIF

TMMK7

SERMK00

SRMK00

STMK00

WTMK

INTWTI

INTTM80

INTTM81

INTTM82

INTAD

WTIIF

TMIF80

TMIF81

TMIF82

ADIF

WTIMK

TMMK80

TMMK81

TMMK82

ADMK

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CHAPTER 14 INTERRUPT FUNCTIONS

(1) Interrupt request flag registers 0 and 1 (IF0 and IF1)

An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the related

instruction is executed. It is cleared to 0 when the interrupt request is acknowledged, when a RESET signal

is input, or when a related instruction is executed.

IF0 and IF1 are manipulated with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears IF0 and IF1 to 00H.

Figure 14-2. Format of Interrupt Request Flag Register

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Address

FFE0H

After reset

00H

R/W

Symbol

IF0

<7>

TMIF7

PIF1

PIF0

TMIF4

WTIF

STIF00

SERIF00

SRIF00

6

0

5

0

<4>

<3>

<2>

<1>

<0>

7

0

IF1

TMIF82

TMIF81

TMIF80

WTIIF

FFE1H

00H

R/W

ADIF

××IF

Interrupt request flag

0

1

No interrupt request signal has been issued.

An interrupt request signal has been issued; an interrupt request has been made.

Cautions 1. Be sure to clear bits 5 to 7 of IF1 to 0.

2. The TMIF4 flag can be read- and write-accessed only when the watchdog timer is being

used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog

timer mode 1 or 2.

3. When port 2 is being used as an output port, and its output level is changed, an interrupt

request flag is set, because this port is also used as an external interrupt input. To use port

2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.

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CHAPTER 14 INTERRUPT FUNCTIONS

(2) Interrupt mask flag registers 0 and 1 (MK0 and MK1)

The interrupt mask flags are used to enable and disable the corresponding maskable interrupts.

MK0 and MK1 are manipulated with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets MK0 and MK1 to FFH.

Figure 14-3. Format of Interrupt Mask Flag Register

<6>

WTMK STMK00

<5>

<4>

<3>

<2>

<1>

<0>

Address

After reset

FFH

R/W

Symbol

MK0

<7>

TMMK7

PMK1

PMK0

TMMK4 FFE4H

SERMK00

SRMK00

6

1

5

1

<4>

<3>

<2>

<1>

<0>

7

1

MK1

TMMK82 TMMK81 TMMK80 WTIMK FFE5H

FFH

R/W

ADMK

××MK

Interrupt handling control

0

1

Enable interrupt handling

Disable interrupt handling

Cautions 1. Be sure to set bits 5 to 7 of MK1 to 1.

2. The TMMK4 flag can be read- and write-accessed only when the watchdog timer is being

used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog

timer mode 1 or 2.

3. When port 2 is being used as an output port, and its output level is changed, an interrupt

request flag is set, because this port is also used as an external interrupt input. To use port

2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.

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CHAPTER 14 INTERRUPT FUNCTIONS

(3) External interrupt mode register 0 (INTM0)

INTM0 is used to specify a valid edge for INTP0 and INTP1.

INTM0 is manipulated with an 8-bit memory manipulation instruction.

RESET input clears INTM0 to 00H.

Figure 14-4. Format of External Interrupt Mode Register 0

Symbol

INTM0

7

0

6

0

5

4

3

2

1

0

Address

FFECH

After reset

00H

R/W

ES11

ES10

ES01

ES00

INTP1 valid edge selection

ES11

ES10

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

INTP0 valid edge selection

ES01

ES00

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Cautions 1. Be sure to clear bits 0, 1, 6, and 7 to 0.

2. Before setting INTM0, set the corresponding interrupt mask flag register to 1 to disable

interrupts. To enable interrupts, clear to 0 the corresponding interrupt request flag, then the

corresponding interrupt mask flag.

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CHAPTER 14 INTERRUPT FUNCTIONS

(4) Program status word (PSW)

The program status word is used to hold the instruction execution result and the current status of the

interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.

The PSW can be read- and write-accessed in 8-bit units, as well as in 1-bit units when using bit manipulation

instructions and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is

automatically saved to a stack, and the IE flag is reset to 0.

RESET input sets PSW to 02H.

Figure 14-5. Program Status Word Configuration

Symbol

PSW

7

6

Z

5

0

4

3

0

2

0

1

0

After reset

02H

IE

AC

CY

Used in the execution of ordinary instructions

IE

0

Whether to enable/disable interrupt acknowledgement

Disable

Enable

1

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CHAPTER 14 INTERRUPT FUNCTIONS

14.4 Interrupt Servicing Operation

14.4.1 Non-maskable interrupt request acknowledgment

A non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject to

interrupt priority control and takes precedence over all other interrupts.

When a non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order,

the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.

Figure 14-6 shows the flowchart from non-maskable interrupt request generation to acknowledgment. Figure 14-7

shows the timing of non-maskable interrupt request acknowledgment. Figure 14-8 shows the acknowledgment

operation if multiple non-maskable interrupts are generated.

Caution During a non-maskable interrupt servicing program execution, do not input another non-

maskable interrupt request; if it is input, the servicing program will be interrupted and the new

interrupt request will be acknowledged.

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Figure 14-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment

Start

WDTM4 = 1

No

(watchdog timer mode

is selected)

Interval timer

Yes

No

WDT

overflows

Yes

WDTM3 = 0

(non-maskable interrupt

is selected)

Reset processing

Yes

Interrupt request is generated

Interrupt servicing is started

WDTM: Watchdog timer mode register

WDT: Watchdog timer

Figure 14-7. Timing of Non-Maskable Interrupt Request Acknowledgment

Interrupt servicing

program

Save PSW and PC, and

jump to interrupt servicing

CPU processing

TMIF4

Instruction

Figure 14-8. Acknowledging Non-Maskable Interrupt Request

Main routine

First interrupt servicing

NMI request

(second)

NMI request

(first)

Second interrupt servicing

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CHAPTER 14 INTERRUPT FUNCTIONS

14.4.2 Maskable interrupt request acknowledgment

A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding

interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE

flag is set to 1).

The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown

in Table 14-3.

See Figures 14-10 and 14-11 for the interrupt request acknowledgment timing.

Table 14-3. Time from Generation of Maskable Interrupt Request to Servicing

Minimum Time

9 clocks

Maximum Time^Note

19 clocks

Note The wait time is maximum when an interrupt

request is generated immediately before the BT

and BF instructions.

1

f^CPU

Remark 1 clock:

(f^CPU: CPU clock)

When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting

from the interrupt request assigned the highest priority.

A pending interrupt is acknowledged when the status where it can be acknowledged is set.

Figure 14-9 shows the algorithm of acknowledging interrupt requests.

When a maskable interrupt request is acknowledged, the contents of PSW and PC are saved to the stack in that

order, the IE flag is reset to 0, the data in the vector table determined for each interrupt request is loaded to the PC,

and execution branches.

To return from interrupt servicing, use the RETI instruction.

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Figure 14-9. Interrupt Request Acknowledgment Program Algorithm

Start

No

××IF = 1 ?

Yes (Interrupt request generated)

No

××MK = 0 ?

Yes

Interrupt request pending

No

IE = 1 ?

Yes

Vectored interrupt

servicing

××IF:

Interrupt request flag

××MK: Interrupt mask flag

IE:

Flag to control maskable interrupt request acknowledgment (1 = Enable, 0 = Disable)

Figure 14-10. Interrupt Request Acknowledgment Timing (Example of MOV A,r)

8 clocks

Clock

Save PSW and PC, jump

to interrupt servicing

Interrupt servicing program

CPU

MOV A,r

Interrupt

If an interrupt request flag (××IF) is set before instruction clock n (n = 4 to 10) under execution becomes n − 1, the

interrupt is acknowledged after the instruction under execution is complete. Figure 14-10 shows an example of the

interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is

executed for 4 clocks, if an interrupt occurs 3 clocks after the execution starts, the interrupt acknowledgment

processing is performed after the MOV A,r instruction is completed.

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CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-11. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated

at Last Clock During Instruction Execution)

8 clocks

Clock

Interrupt

servicing

program

Save PSW and PC, jump

to interrupt servicing

CPU

NOP

MOV A,r

Interrupt

If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment

processing starts after the next instruction is executed.

Figure 14-11 shows an example of the interrupt acknowledgment timing for an interrupt request flag that is set at

the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is

executed, and then the interrupt acknowledgment processing is performed.

Caution Interrupt requests are held pending while interrupt request flag registers 0 and 1 (IF0 and IF1) or

interrupt mask flag registers 0 and 1 (MK0 and MK1) are being accessed.

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14.4.3 Multiple interrupt servicing

Multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced can be

processed by priority. When two or more interrupts are generated at once, interrupt servicing is performed according

to the priority assigned to each interrupt request in advance (see Table 14-1).

Figure 14-12. Example of Multiple Interrupt Servicing

Example 1. Multiple interrupts are acknowledged

INTxx servicing

INTyy servicing

Main processing

IE = 0

EI

INTxx

INTyy

RETI

During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupt servicing is

performed. The EI instruction is issued before each interrupt request acknowledgment, and the interrupt request

acknowledgment enable state is set.

Example 2. Multiple interrupt servicing is not performed because interrupts are not enabled

INTxx servicing

INTyy servicing

Main processing

EI

IE = 0

INTyy is held pending

INTyy

RETI

INTxx

IE = 0

RETI

Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request

INTyy is not acknowledged, and multiple interrupt servicing is not performed. The INTyy request is held pending and

acknowledged after the INTxx servicing is performed.

Remark IE = 0: Interrupt request acknowledgment disabled

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14.4.4 Interrupt request pending

Some instructions do not acknowledge an interrupt request (maskable interrupt, non-maskable interrupt, and

external interrupt) until the completion of the execution of the next instruction even if the interrupt request is generated

during the execution. The following shows such instructions (interrupt request pending instructions).

• Manipulation instruction for interrupt request flag registers 0 and 1 (IF0 and IF1)

• Manipulation instruction for interrupt mask flag registers 0 and 1 (MK0 and MK1)

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CHAPTER 15 STANDBY FUNCTION

15.1 Standby Function and Configuration

15.1.1 Standby function

The standby function is used to reduce the power consumption of the system and can be effected in the following

two modes.

(1) HALT mode

This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU.

The system clock oscillator continues oscillating. This mode does not reduce the power consumption as

much as STOP mode, but is useful for resuming processing immediately when an interrupt request is

generated, or for intermittent operations.

(2) STOP mode

This mode is set when the STOP instruction is executed. STOP mode stops the system clock oscillator and

stops the entire system. The power consumption of the CPU can be substantially reduced in this mode.

STOP mode can be released by an interrupt request, so that this mode can be used for intermittent

operations. However, some time is required until the system clock oscillator stabilizes after STOP mode has

been released. If processing must be resumed immediately by using an interrupt request, therefore, use

HALT mode.

In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are all

retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.

Caution To set STOP mode, be sure to stop the operations of the peripheral hardware, and then execute

the STOP instruction.

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15.1.2 Standby function control register

The wait time after STOP mode is released upon interrupt request generation until the oscillation stabilizes is

controlled by the oscillation stabilization time selection register (OSTS).

OSTS is set with an 8-bit memory manipulation instruction.

RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 2¹⁵/fX.

Figure 15-1. Format of Oscillation Stabilization Time Selection Register

6

0

5

0

4

0

3

0

2

1

0

Address

After reset

04H

R/W

Symbol

OSTS

7

0

OSTS2

OSTS1

OSTS0 FFFAH

OSTS2 OSTS1

OSTS0

Oscillation stabilization time selection

2¹²/f

2¹⁵/f

2¹⁷/f

X

0

1

0

1

0

µ

(488 s)

X

(3.91 ms)

(15.6 ms)

Other than above

Setting prohibited

Caution The wait time after STOP mode is released does not include the time from STOP mode release

to clock oscillation start (“a” in the figure below), regardless of release by RESET input or by

interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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15.2 Operation of Standby Function

15.2.1 HALT mode

(1) HALT mode

HALT mode is set by executing the HALT instruction.

The operation statuses in HALT mode are shown in the following table.

Table 15-1. Operation Statuses in HALT Mode

Item

HALT Mode Operation Status

System clock

CPU

System clock oscillation enabled

Clock supply to CPU disabled

Operation disabled

Ports (output latches)

Remain in the state existing before the selection of HALT mode

Operation enabled

10-bit inverter control timer

8-bit timer/event

TM80

TM81

TM82

Operation enabled

counters 80, 81, 82

Operation enabled

Watch timer

Operation enabled

Watchdog timer

A/D converter

Serial interface

External interrupt

Operation enabled

Operation disabled

Operation enabled

Operation enabled^Note

Note Maskable interrupt that is not masked

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(2) Releasing HALT mode

HALT mode can be released by the following three sources.

(a) Releasing by unmasked interrupt request

HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is

enabled to be acknowledged, vectored interrupt servicing is performed. If the interrupt is disabled, the

instruction at the next address is executed.

Figure 15-2. Releasing HALT Mode by Interrupt

HALT

instruction

Wait

Standby

release signal

Operating

mode

HALT mode

Operating mode

Oscillation

Clock

Remarks 1. The broken lines indicate the case where the interrupt request that has released standby

mode is acknowledged.

2. The wait time is as follows.

• When vectored interrupt servicing is performed:

• When vectored interrupt servicing is not performed:

9 to 10 clocks

1 to 2 clocks

(b) Releasing by non-maskable interrupt request

HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt

servicing is performed.

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(c) Releasing by RESET input

When HALT mode is released by the RESET signal, execution branches to the reset vector address in

the same manner as the ordinary reset operation, and program execution is started.

Figure 15-3. Releasing HALT Mode by RESET Input

Wait

(3.91 ms)

HALT

instruction

2¹⁵/f

X

RESET

signal

Oscillation

stabilization

wait status

Reset

period

Operating

mode

Operating

mode

HALT mode

Oscillation

stop

Oscillation

Clock

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

Table 15-2. Operation After Release of HALT Mode

MK××

Releasing Source

IE

0

Operation

Maskable interrupt request

0

1

−

Next address instruction executed

Interrupt servicing executed

HALT mode retained

1

×

Non-maskable interrupt request

RESET input

Interrupt servicing executed

Reset processing

−

×: Don’t care

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CHAPTER 15 STANDBY FUNCTION

15.2.2 STOP mode

(1) Setting and operation status of STOP mode

STOP mode is set by executing the STOP instruction.

Caution Because standby mode can be released by an interrupt request signal, standby mode is

released as soon as it is set if there is an interrupt source whose interrupt request flag is

set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT mode is set

immediately after the STOP instruction has been executed, the wait time set by the

oscillation stabilization time selection register (OSTS) elapses, and then the operation

mode is set.

The operation statuses in STOP mode are shown in the following table.

Table 15-3. Operation Statuses in STOP Mode

Item

STOP Mode Operation Status

System clock oscillation disabled

System clock

CPU

Operation disabled

Ports (output latches)

Remain in the state existing before the selection of STOP mode

Operation disabled

10-bit inverter control timer

8-bit timer/event

TM80

TM81

TM82

Operation enabled only when TI80 is selected as the count clock

Operation enabled only when TI81 is selected as the count clock

Operation disabled

counters 80, 81, 82

Watch timer

Operation disabled

Watchdog timer

A/D converter

Serial interface

External interrupt

Operation disabled

Operation enabled^Note

Note Maskable interrupt that is not masked

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(2) Releasing STOP mode

STOP mode can be released by the following two sources.

(a) Releasing by unmasked interrupt request

STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled

to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has

elapsed. If the interrupt acknowledgment is disabled, the instruction at the next address is executed.

Figure 15-4. Releasing STOP Mode by Interrupt

Wait

STOP

instruction

(set time by OSTS)

Standby

release signal

Oscillation stabilization

wait status

Operating

mode

Operating

mode

STOP mode

Oscillation

stop

Oscillation

Clock

Remark The broken lines indicate the case where the interrupt request that has released standby

mode is acknowledged.

(b) Releasing by RESET input

When STOP mode is released by the RESET signal, the reset operation is performed after the

oscillation stabilization time has elapsed.

Figure 15-5. Releasing STOP Mode by RESET Input

Wait

STOP

instruction

2¹⁵/f

(3.91 ms)

X

RESET

signal

Oscillation

stabilization

wait status

Operating

mode

Reset

period

Operating

mode

STOP mode

Oscillation

stop

Oscillation

Clock

Remarks 1. fX: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 8.38 MHz.

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Table 15-4. Operation After Release of STOP Mode

MK××

Releasing Source

IE

0

Operation

Next address instruction executed

Interrupt servicing executed

STOP mode retained

Maskable interrupt request

0

1

−

1

×

−

RESET input

Reset processing

×: Don’t care

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CHAPTER 16 RESET FUNCTION

The following two operations are available to generate reset signals.

(1) External reset input via RESET pin

(2) Internal reset by inadvertent program loop time detected by watchdog timer

External and internal reset have no functional differences. In both cases, program execution starts at the

addresses at 0000H and 0001H by reset signal input.

When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and the hardware

is set to the status shown in Table 16-1. Each pin is high impedance during reset input or during the oscillation

stabilization time just after reset is released.

When a high level is input to the RESET pin, the reset is released and program execution is started after the

oscillation stabilization time (2¹⁵/fX) has elapsed. The reset applied by watchdog timer overflow is automatically

released after reset, and program execution is started after the oscillation stabilization time (2¹⁵/fX) has elapsed (see

Figures 16-2 to 16-4).

Cautions 1. For an external reset, input a low level to the RESET pin for 10 µs or more.

2. When STOP mode is released by reset, STOP mode contents are held during reset input.

However, the port pins become high impedance.

Figure 16-1. Block Diagram of Reset Function

RESET

Reset signal

Reset controller

Over-

flow

Interrupt function

Count clock

Watchdog timer

Stop

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CHAPTER 16 RESET FUNCTION

Figure 16-2. Reset Timing by RESET Input

X1

Reset period

(oscillation

stops)

Oscillation

stabilization

time wait

During normal

operation

Normal operation

(reset processing)

RESET

Internal

reset signal

Delay

Hi-Z

Port pin

Figure 16-3. Reset Timing by Overflow in Watchdog Timer

X1

Reset period

(oscillation

continues)

Oscillation

stabilization

time wait

Normal operation

(reset processing)

During normal operation

Overflow in

watchdog timer

Internal

reset signal

Hi-Z

Port pin

Figure 16-4. Reset Timing by RESET Input in STOP Mode

X1

STOP instruction execution

Oscillation

Stop status

(oscillation

stops)

Reset period

(oscillation

stops)

Normal operation

(reset processing)

stabilization

time wait

During normal operation

RESET

Internal

reset signal

Delay

Hi-Z

Port pin

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CHAPTER 16 RESET FUNCTION

Table 16-1. Statuses of Hardware After Reset (1/2)

Hardware

Status After Reset

Program counter (PC)^{Note 1}

Loaded with the contents of

the reset vector table

(0000H, 0001H)

Stack pointer (SP)

Program status word (PSW)

RAM

Undefined

02H

Data memory

Undefined^{Note 2}

00H

General-purpose registers

Ports (P0 to P2) (output latches)

Port mode registers (PM0 to PM2)

FFH

Pull-up resistor option registers (PU0, PUB2)

Processor clock control register (PCC)

00H

02H

Oscillation stabilization time selection register (OSTS)

04H

10-bit inverter control timer

Compare registers (CM0 to CM2)

0000H

00FFH

0000H

00FFH

FFH

Compare register (CM3)

Buffer registers (BFCM0 to BFCM2)

Buffer register (BFCM3)

Dead time reload register (DTIME)

Control register (TMC7)

00H

Mode register (TMM7)

00H

8-bit timer/event counters 80,

81, 82

Timer counters (TM80 to TM82)

Compare registers (CR80 to CR82)

Mode control registers (TMC80 to TMC82)

Mode control register (WTM)

00H

Undefined

00H

Watch timer

00H

Watchdog timer

Timer clock selection register (TCL2)

Mode register (WDTM)

00H

A/D converter

Serial interface

Mode register (ADM)

00H

Conversion result register (ADCRH)

Input selection register (ADS)

Undefined

00H

Asynchronous serial interface mode register (ASIM00)

Asynchronous serial interface status register (ASIS00)

Baud rate generator control register (BRGC00)

Transmit shift register (TXS00)

Receive buffer register (RXB00)

00H

Undefined

FFH

Notes 1. While a reset signal is being input, and during the oscillation stabilization period, the contents of the PC

will be undefined, while the remainder of the hardware will be the same as after reset.

2. In standby mode, the RAM enters the hold state after a reset.

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Table 16-1. Statuses of Hardware After Reset (2/2)

Hardware

Status After Reset

Undefined

Multiplier

10-bit data registers (MRA1H, MRA1L, MRB1H, MRB1L)

20-bit multiplication result storage registers (MUL1HL,

MUL1LH, MUL1LL)

Undefined

Multiplier control register (MULC1)

00H

Note

00H

FFH

00H

Swapping function register (SWP0)

Interrupts

Request flag registers (IF0, IF1)

Mask flag registers (MK0, MK1)

External interrupt mode register (INTM0)

Note The status set after a reset differs between read mode and write mode. For details, see 13.2 SWAP

Configuration.

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CHAPTER 17 µPD78F9842

The µPD78F9842 features expanded flash memory instead of the internal ROM of the mask ROM versions. The

differences between the µPD78F9842 and the mask ROM versions are shown in Table 17-1.

Table 17-1. Differences Between µPD78F9842 and Mask ROM Versions

Flash Memory

Mask ROM

Item

µPD78F9842

µPD789841

µPD789842

Internal memory

Flash memory/ROM

RAM

16 KB

8 KB

16 KB

256 bytes

Not provided

Provided

IC pin

Provided

VPP pin

Not provided

Electrical characteristics

See CHAPTER 19 ELECTRICAL SPECIFICATIONS.

Caution There are differences in the noise immunity and noise radiation between flash memory and

mask ROM versions. When pre-producing an application set with the flash memory version and

the mass producing it with the mask ROM version, be sure to conduct sufficient evaluations on

the commercial sample (CS), not engineering sample (ES), of the mask ROM version.

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17.1 Flash Memory Characteristics

Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-

PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µPD78F9842 mounted on the

target system (on-board writing). A flash memory program adapter (FA adapter), which is a target board used

exclusively for programming, is also provided.

Remark FL-PR3, FL-PR4, and the program adapter are products made by Naito Densei Machida Mfg. Co., Ltd.

(TEL +81-45-475-4191).

Programming using flash memory has the following advantages.

• Software can be modified after the microcontroller is solder-mounted on the target system.

• Distinguishing software facilities small-quantity, varied model production

• Easy data adjustment when starting mass production

17.1.1 Programming environment

The following shows the environment required for µPD78F9842 flash memory programming.

When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated

flash programmer, a host machine is required to control the dedicated flash programmer. Communication between

the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).

For details, refer to the manuals for Flashpro III/Flashpro IV.

Remark USB is supported by Flashpro IV only.

Figure 17-1. Environment for Writing Program to Flash Memory

VPP

V

DD

SS

RS-232C

USB

V

RESET

UART

Dedicated flash

programmer

µPD78F9842

or pseudo 3-wire

Host machine

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CHAPTER 17 µPD78F9842

17.1.2 Communication mode

Use the communication mode shown in Table 17-2 to perform communication between the dedicated flash

programmer and µPD78F9842.

Table 17-2. Communication Mode List

Communication

Mode

TYPE Setting^{Note 1}

CPU Clock

In Flashpro On Target Board

Pins Used

Number of VPP

Pulses

COMM PORT SIO Clock

Multiple

Rate

5 MHz^{Note 5}

4.91 or

5 MHz^{Note 2}

1.0

RxD/P22

8

UART

UART ch-0

(Async.)

4,800 to

76,800 bps

Notes 2, 4

TxD/P21

Pseudo 3-wire Port A

(Pseudo-

3 wire)

100 Hz to

1 kHz

1, 2, 4, 5

MHz^{Notes 2, 3}

1 to 5 MHz^{Note 2}

1.0

P01

P02

P00

12

Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3,

PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)).

2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 19

ELECTRICAL SPECIFICATIONS.

3. 2 or 4 MHz only for Flashpro III

4. Because signal wave slew also affects UART communication, in addition to the baud rate error,

thoroughly evaluate the slew.

5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on

the board. UART cannot be used with the clock supplied by Flashpro III.

Figure 17-2. Communication Mode Selection Format

10 V

VPP

VDD

1

2

n

V^SS

V^PPpulses

VDD

VSS

RESET

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Figure 17-3. Example of Connection with Dedicated Flash Programmer

(a) UART

Dedicated flash programmer

PD78F9842

µ

VPP1

VDD

V

PP

DD

V

RESET

SO

RESET

RXD

SI

TXD

CLK^{Notes 1, 2}

X1

GND

V

SS

(b) Pseudo 3-wire (when P0 is used)

Dedicated flash programmer

µ

PD78F9842

VPP1

VDD

V

PP

DD

RESET

SCK

RESET

P00 (serial clock)

P02 (serial input)

P01 (serial output)

X1

SO

SI

CLK^{Note 1}

GND

V

SS

Notes 1. When supplying the system clock from a dedicated flash programmer, connect the CLK and X1 pins

and cut off the resonator on the board. When using the clock oscillated by the on-board resonator, do

not connect the CLK pin.

2. When using UART with Flashpro III, the clock of the resonator connected to the X1 pin must be used,

so do not connect the CLK pin.

Caution The V^DDpin, if already connected to the power supply, must be connected to the VDD pin of the

dedicated flash programmer. When using the power supply connected to the V^DDpin, supply

voltage before starting programming.

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CHAPTER 17 µPD78F9842

If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash

programmer, the following signals are generated for the µPD78F9842. For details, refer to the manual of Flashpro

III/Flashpro IV.

Table 17-3. Pin Connection List

Signal Name

VPP1

VPP2

VDD

I/O

Output

−

Pin Function

Pin Name

UART

Pseudo 3-Wire

Write voltage

VPP

×

Note

×

Note

−

I/O

VDD voltage generation/voltage monitoring

Ground

VDD

VSS

X1

−

GND

CLK

Output

Input

Output

Input

Clock output

{

RESET

SI

Reset signal

RESET

TxD, P01

RxD, P02

P00

Receive signal

SO

Transmit signal

×

SCK

Transfer clock

×

−

HS

Handshake signal

Note

VDD voltage must be supplied before programming is started.

Remark

: Pin must be connected.

{: If the signal is supplied on the target board, pin does not need to be connected.

×: Pin does not need to be connected.

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CHAPTER 17 µPD78F9842

17.1.3 On-board pin connections

When programming on the target system, provide a connector on the target system to connect to the dedicated

flash programmer.

There may be cases in which an on-board function that switches from the normal operation mode to flash memory

programming mode is required.

<V^PPpin>

Input 0 V to the V^PPpin in the normal operation mode. A writing voltage of 10.0 V (TYP.) is supplied to the VPP

pin in the flash memory programming mode. Therefore, connect the V^PPpin as follows.

(1) Connect a pull-down resistor of RVPP = 10 kΩ to the VPP pin.

(2) Set the jumper on the board to switch the input of V^PPpin to the programmer side or directly to GND.

The following shows an example of V^PPpin connection.

Figure 17-4. V^PPPin Connection Example

PD78F9842

µ

Connection pin of dedicated flash programmer

VPP

Pull-down resistor (RVPP

)

The following shows the pins used by each serial interface.

Serial Interface

Pins Used

UART

RxD, TxD

P00, P01, P02

Pseudo 3-wire

Note that signal conflict or malfunction of other devices may occur when an on-board serial interface pin that is

connected to another device is connected to the dedicated flash programmer.

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(1) Signal conflict

A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin

(input) connected to another device (output). To prevent this signal conflict, isolate the connection with the

other device or put the other device in the output high impedance status.

Figure 17-5. Signal Conflict (Serial Interface Input Pin)

µ

PD78F9842

Input pin

Connection pin of dedicated flash

programmer

Signal conflict

Other device

Output pin

In the flash memory programming mode, the signal

output by another device and the signal sent by the

dedicated flash programmer conflict. To prevent this,

isolate the signal on the device side.

(2) Malfunction of another device

When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output)

connected to another device (input), a signal may be output to the device, causing a malfunction. To prevent

such malfunction, isolate the connection with other device or set so that the input signal to the device is

ignored.

Figure 17-6. Malfunction of Another Device

µ

PD78F9842

Connection pin of dedicated flash

programmer

Other device

Input pin

If the signal output by the

flash memory programming mode, isolate the signal on the device side.

µ

PD78F9842 affects another device in the

µ

PD78F9842

Connection pin of dedicated flash

programmer

Other device

Input pin

If the signal output by the dedicated flash programmer affects another

device, isolate the signal on the device side.

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When the reset signal of the dedicated flash programmer is connected to the RESET signal connected to the

reset signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the connection

with the reset signal generator.

If a reset signal is input from the user system in the flash memory programming mode, a normal programming

operation will not be performed. Do not input signals other than reset signals from the dedicated flash

programmer during this period.

Figure 17-7. Signal Conflict (RESET Pin)

µ

PD78F9842

RESET

Connection pin of dedicated

flash writer

Signal conflict

Reset signal generator

Output pin

In the flash memory programming mode, the signal output

by the reset signal generator and the signal output by the

dedicated flash writer conflict, therefore, isolate the

signal on the reset signal generator side

Shifting to the flash memory programming mode sets all the pins except those used for flash memory

programming communication to the status immediately after reset.

Therefore, if the external device does not acknowledge an initial status such as the output high impedance

status, connect the external device to V^DDor VSS via a resistor.

When using an on-board clock, connection of X1 and X2 must conform to the methods in the normal operation

mode.

When using the clock output of the flash programmer, directly connect it to the X1 pin with the on-board

oscillator disconnected, and leave the X2 pin open.

To use the power output of the flash programmer, connect the V^DDand VSS pins to VDD and GND of the flash

programmer, respectively.

To use the on-board power supply, connection must conform to that in the normal operation mode. However,

because the voltage is monitored by the flash programmer, therefore, V^DDof the flash programmer must be

connected.

Supply the same power as in normal operation mode for the other power supplies (AV^DD, AVSS).

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CHAPTER 17 µPD78F9842

17.1.4 Connection of adapter for flash writing

The following figures show examples of the recommended connection when the adapter for flash writing is used.

Figure 17-8. Wiring Example for Flash Writing Adapter in UART Mode

VDD (4.0 to 5.5 V)

GND

44 43 42 41 40 39 38 37 36 35 34

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

PD78F9842

µ

26

25

24

23

9

10

11

12 13 14 15 16 17 18 19 20 21 22

GND

VDD

VDD2 (LVDD)

SI

SO SCK CLKOUT RESET VPP RESERVE/HS

FRASHWRITER

INTERFACE

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CHAPTER 17 µPD78F9842

Figure 17-9. Wiring Example for Flash Writing Adapter in Pseudo 3-Wire Mode

VDD (4.0 to 5.5 V)

GND

44 43 42 41 40 39 38 37 36 35 34

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

PD78F9842

µ

26

25

24

23

9

10

11

12 13 14 15 16 17 18 19 20 21 22

GND

VDD

VDD2 (LVDD)

SI

SO SCK CLKOUT RESET VPP RESERVE/HS

FRASHWRITER

INTERFACE

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CHAPTER 18 INSTRUCTION SET

This chapter lists the instruction set of the µPD789842 Subseries. For the details of the operation and machine

language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E).

18.1 Operation

18.1.1 Operand identifiers and description methods

Operands are described in the "Operand" column of each instruction in accordance with the description method of

the instruction operand identifier (refer to the assembler specifications for details). When there are two or more

description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are

described as they are. Each symbol has the following meaning.

• #: Immediate data specification

• !:

Absolute address specification

• $: Relative address specification

• [ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

describe the #, !, $ and [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for description.

Table 18-1. Operand Identifiers and Description Methods

Identifier

Description Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special-function register symbol

rp

sfr

saddr

FE20H to FF1FH Immediate data or labels

saddrp

FE20H to FF1FH Immediate data or labels (even addresses only)

addr16

addr5

0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)

0040H to 007FH Immediate data or labels (even addresses only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

Remark See Table 3-3 for symbols of special-function registers.

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CHAPTER 18 INSTRUCTION SET

18.1.2 Description of "Operation" column

A:

A register; 8-bit accumulator

X:

X register

B:

B register

C:

C register

D:

D register

E:

E register

H:

H register

L:

L register

AX:

BC:

DE:

HL:

PC:

SP:

PSW:

CY:

AC:

Z:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

Program counter

Stack pointer

Program status word

Carry flag

Auxiliary carry flag

Zero flag

IE:

Interrupt request enable flag

NMIS: Flag indicating non-maskable interrupt servicing in progress

( ): Memory contents indicated by address or register contents in parentheses

×^H, ×L: Higher 8 bits and lower 8 bits of 16-bit register

∧:

∨:

Logical product (AND)

Logical sum (OR)

Exclusive logical sum (exclusive OR)

Inverted data

:

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

18.1.3 Description of flag operation column

(Blank): Unchanged

0:

1:

×:

R:

Cleared to 0

Set to 1

Set/cleared according to the result

Previously saved value is stored

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CHAPTER 18 INSTRUCTION SET

18.2 Operation List

Flag

Mnemonic

MOV

Operands

Bytes Clocks

Operation

Z

AC CY

r ← byte

r, #byte

3

2

3

2

1

2

1

2

1

2

6

4

8

6

4

6

4

6

8

(saddr) ← byte

sfr ← byte

A ← r

saddr, #byte

sfr, #byte

A, r ^{Note 1}

r, A ^{Note 1}

r ← A

A ← (saddr)

(saddr) ← A

A ← sfr

A, saddr

saddr, A

A, sfr

sfr ← A

sfr, A

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

PSW ← A

A ← (DE)

(DE) ← A

A ← (HL)

A, !addr16

!addr16, A

PSW, #byte

A, PSW

PSW, A

A, [DE]

×

[DE], A

A, [HL]

(HL) ← A

[HL], A

A ← (HL + byte)

(HL + byte) ← A

A ↔ X

A, [HL + byte]

[HL + byte], A

A, X

XCH

A, r ^{Note 2}

A ↔ r

A ↔ (saddr)

A ↔ sfr

A, saddr

A, sfr

A ↔ (DE)

A ↔ (HL)

A, [DE]

A, [HL]

A ↔ (HL + byte)

A, [HL + byte]

Notes 1. Except r = A.

2. Except r = A, X.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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CHAPTER 18 INSTRUCTION SET

Flag

Mnemonic

MOVW

Operands

Bytes Clocks

Operation

Z

AC CY

rp ← word

rp, #word

3

2

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

6

8

4

8

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

AX ← (saddrp)

(saddrp) ← AX

AX ← rp

AX, saddrp

saddrp, AX

AX, rp ^Note

rp, AX ^Note

AX, rp ^Note

A, #byte

rp ← AX

AX ↔ rp

XCHW

ADD

A, CY ← A + byte

×

(saddr), CY ← (saddr) + byte

A, CY ← A + r

saddr, #byte

A, r

A, CY ← A + (saddr)

A, saddr

A, CY ← A + (addr16)

A, CY ← A + (HL)

A, !addr16

A, [HL]

A, CY ← A + (HL + byte)

A, CY ← A + byte + CY

(saddr), CY ← (saddr) + byte + CY

A, CY ← A + r + CY

A, [HL + byte]

A, #byte

ADDC

saddr, #byte

A, r

A, CY ← A + (saddr) + CY

A, CY ← A + (addr16) + CY

A, CY ← A + (HL) + CY

A, CY ← A + (HL + byte) + CY

A, CY ← A − byte

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte

SUB

(saddr), CY ← (saddr) − byte

A, CY ← A − r

saddr, #byte

A, r

A, CY ← A − (saddr)

A, saddr

A, CY ← A − (addr16)

A, CY ← A − (HL)

A, !addr16

A, [HL]

A, CY ← A − (HL + byte)

A, [HL + byte]

Note Only when rp = BC, DE, or HL.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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CHAPTER 18 INSTRUCTION SET

Flag

Mnemonic

SUBC

Operands

Bytes Clocks

Operation

Z

×

AC CY

A, CY ← A − byte − CY

(saddr), CY ← (saddr) − byte − CY

A, CY ← A − r − CY

A, CY ← A − (saddr) − CY

A, CY ← A − (addr16) − CY

A, CY ← A − (HL) − CY

A, CY ← A − (HL + byte) − CY

A ← A ∧ byte

×

A, #byte

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte

AND

(saddr) ← (saddr) ∧ byte

A ← A ∧ r

saddr, #byte

A, r

A ← A ∧ (saddr)

A, saddr

A, !addr16

A, [HL]

A ← A ∧ (addr16)

A ← A ∧ (HL)

A ← A ∧ (HL + byte)

A ← A ∨ byte

A, [HL + byte]

A, #byte

OR

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

saddr, #byte

A, r

A ← A ∨ (saddr)

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (addr16)

A ← A ∨ (HL)

A ← A ∨ (HL + byte)

A ← A ∨ byte

A, [HL + byte]

A, #byte

XOR

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

saddr, #byte

A, r

A ← A ∨ (saddr)

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (addr16)

A ← A ∨ (HL)

A ← A ∨ (HL + byte)

A, [HL + byte]

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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CHAPTER 18 INSTRUCTION SET

Flag

Mnemonic

CMP

Operands

Bytes Clocks

Operation

Z

×

AC CY

A − byte

×

A, #byte

2

3

2

3

1

2

3

2

1

3

2

3

2

3

2

3

2

1

4

6

4

8

6

4

2

6

4

6

10

6

4

6

10

2

(saddr) − byte

A − r

saddr, #byte

A, r

A − (saddr)

A − (addr16)

A − (HL)

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

AX, #word

r

A − (HL + byte)

AX, CY ← AX + word

AX, CY ← AX − word

AX − word

ADDW

SUBW

CMPW

INC

r ← r + 1

(saddr) ← (saddr) + 1

r ← r − 1

saddr

r

DEC

(saddr) ← (saddr) − 1

rp ← rp + 1

saddr

rp

INCW

DECW

ROR

rp ← rp − 1

rp

(CY, A⁷← A0, Am−1 ← Am) × 1

(CY, A⁰← A7, Am+1 ← Am) × 1

(CY ← A⁰, A7 ← CY, Am−1 ← Am) × 1

(CY ← A⁷, A0 ← CY, Am+1 ← Am) × 1

(saddr.bit) ← 1

sfr.bit ← 1

×

A, 1

ROL

A, 1

RORC

ROLC

SET1

A, 1

saddr.bit

sfr.bit

A.bit ← 1

A.bit

PSW.bit ← 1

×

PSW.bit

[HL].bit

saddr.bit

sfr.bit

(HL).bit ← 1

(saddr.bit) ← 0

sfr.bit ← 0

CLR1

A.bit ← 0

A.bit

PSW.bit ← 0

×

PSW.bit

[HL].bit

CY

(HL).bit ← 0

CY ← 1

SET1

CLR1

NOT1

1

0

×

CY ← 0

CY

CY ← CY

CY

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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CHAPTER 18 INSTRUCTION SET

Flag

Mnemonic

CALL

Operands

Bytes Clocks

Operation

Z

AC CY

(SP − 1) ← (PC + 3)^H, (SP − 2) ← (PC + 3)L,

PC ← addr16, SP ← SP − 2

!addr16

[addr5]

3

1

6

8

(SP − 1) ← (PC + 1)^H, (SP − 2) ← (PC + 1)L,

PC^H← (00000000, addr5 + 1),

CALLT

PC^L← (00000000, addr5), SP ← SP − 2

PC^H← (SP + 1), PCL ← (SP), SP ← SP + 2

RET

1

6

8

PC^H← (SP + 1), PCL ← (SP),

RETI

R

PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0

(SP − 1) ← PSW, SP ← SP − 1

(SP − 1) ← rp^H, (SP − 2) ← rpL, SP ← SP − 2

PSW ← (SP), SP ← SP + 1

PUSH

POP

PSW

1

2

3

2

1

2

4

3

4

3

4

2

3

2

4

rp

PSW

4

rp^H← (SP + 1), rpL ← (SP), SP ← SP + 2

SP ← AX

rp

6

MOVW

BR

SP, AX

AX, SP

!addr16

$addr16

AX

8

AX ← SP

6

PC ← addr16

6

PC ← PC + 2 + jdisp8

6

PC^H← A, PCL ← X

6

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

PC ← PC + 4 + jdisp8 if (saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 4 + jdisp8 if PSW.bit = 1

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 4 + jdisp8 if PSW.bit = 0

B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0

C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0

BC

$saddr16

6

BNC

BZ

6

BNZ

BT

6

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

B, $addr16

10

8

10

8

BF

10

6

DBNZ

C, $addr16

6

(saddr) ← (saddr) − 1, then

saddr, $addr16

8

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP

EI

1

3

1

2

6

2

No Operation

IE ← 1 (Enable Interrupt)

IE ← 0 (Disable Interrupt)

Set HALT Mode

DI

HALT

STOP

Set STOP Mode

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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CHAPTER 18 INSTRUCTION SET

18.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,

POP, DBNZ

2nd Operand

#byte

A

r

sfr

saddr !addr16 PSW

[DE]

[HL]

$addr16

1

None

[HL + byte]

1st Operand

A

ADD

ADDC

SUB

SUBC

AND

OR

MOV^NoteMOV

XCH^NoteXCH

ADD

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

ROR

ROL

ADD

ADDC

SUB

SUBC

AND

OR

RORC

ROLC

ADDC

SUB

SUBC

XOR

CMP

AND

OR

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV

INC

DEC

B, C

sfr

DBNZ

MOV

saddr

MOV

ADD

ADDC

SUB

SUBC

AND

OR

INC

DEC

XOR

CMP

!addr16

PSW

MOV

PUSH

POP

[DE]

MOV

[HL]

[HL + byte]

Note Except r = A.

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CHAPTER 18 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

#word

AX

rp^Note

saddrp

MOVW

SP

MOVW

None

1st Operand

AX

ADDW SUBW

CMPW

MOVW

XCHW

rp

MOVW

MOVW^Note

INCW

DECW

PUSH

POP

saddrp

SP

MOVW

Note Only when rp = BC, DE, or HL.

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd Operand

$addr16

None

SET1

1st Operand

A.bit

BT

BF

CLR1

sfr.bit

BT

BF

SET1

CLR1

saddr.bit

PSW.bit

[HL].bit

CY

BT

BF

SET1

CLR1

BT

BF

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

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CHAPTER 18 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

2nd Operand

AX

!addr16

[addr5]

CALLT

$addr16

1st Operand

Basic instructions

BR

CALL

BR

BC

BNC

BZ

BNZ

Compound instructions

DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter

Symbol

VDD

V^PP

VI

Conditions

Rated Value

−0.3 to +6.5

−0.3 to +10.5

−0.3 to V^DD+ 0.3

–10

Unit

V

Power supply voltage

µPD78F9842 only, Note

V

Input voltage

V

Output voltage

Output current, high

VO

V

IOH

Per pin

mA

°C

Total for all pins

Per pin

–30

Output current, low

IOL

TA

30

Total for all pins

In normal operation

During flash memory programming

160

−40 to +85

10 to 40

Operating ambient temperature

Storage temperature

−65 to +150

Tstg

Note Make sure that the following conditions of the V^PPvoltage application timing are satisfied when the flash

memory is written.

• When supply voltage rises

V^PPmust exceed VDD 10 µs or more after VDD has reached the lower-limit value (4.5 V) of the operating

voltage range (see a in the figure below).

• When supply voltage drops

VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (4.5 V) of the operating

voltage range of VDD (see b in the figure below).

4.5 V

V

DD

0 V

a

b

VPP

4.5 V

0 V

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 4.0 to 5.5 V)

Resonator

Ceramic

Recommended Circuit

Parameter

Conditions

MIN.

8.0

TYP.

8.38

MAX.

8.5

Unit

Oscillator frequency

(fx)^{Note 1}

V^DD= oscillation

voltage range

MHz

V

SS X2

X1

resonator

Oscillation

stabilization time^{Note 2}

Time after the V^DD

has reached the

minimum value in

the oscillation

4

ms

C2

C1

voltage range

V

SS X2

X1

Crystal oscillator

Oscillator frequency

(fx) ^{Note 1}

8.0

8.38

8.5

10

MHz

ms

Oscillation

stabilization time^{Note 2}

C2

C1

Notes 1. Only the characteristics of the oscillator are indicated. See the description of the AC characteristics for

the instruction execution time.

2. Time required for oscillation to stabilize once a reset sequence ends or STOP mode is released. Use a

resonator that will become stable within the oscillation wait time.

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken

lines in the above diagrams to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

•

Do not cross the wiring with any other signal lines.

•

Do not route the wiring in the vicinity of a line through which a high fluctuating current flows.

•

Always make the ground of the capacitor the same potential as VSS

.

•

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

DC Characteristics (TA = −40 to +85°C, VDD = 4.0 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

–1

Unit

mA

V

Output current, high

IOH

Per pin

Total for all pins

Per pin

–15

10

Output current, low

Input voltage, high

IOL

Total for all pins

80

VIH1

VIH2

V^IH3

VIL1

VIL2

V^IL3

VOH

VOL

ILIH1

I^LIH2

IILI1

P00 to P07, P10 to P17, P60 to P67

RESET, P20 to P25

X1, X2

0.7VDD

VDD

0.8VDD

VDD

V

VDD – 0.1

VDD

V

Input voltage, low

P00 to P07, P10 to P17, P60 to P67

RESET, P20 to P25

X1, X2

0

0.3VDD

0.2VDD

0.1

V

0

V

Output voltage, high

Output voltage, low

IOH = –1mA

VDD – 1.0

V

IOL = 10mA

1.0

3

V

µA

kΩ

mA

µA

mA

Input leakage current, high

V^IN= VDD

Pins other than X1 and X2

X1, X2

20

Input leakage current, low

V^IN= 0 V

Pins other than X1 and X2

X1, X2

–3

I^ILI2

–20

3

Output leakage current, high

Output leakage current, low

Software pull-up resistance

Power supply current^{Note 1}

ILOH

ILOL

R

VOUT = VDD

VOUT = 0 V

VIN = 0 V

–3

50

100

5.5

1.2

0.1

6.0

200

16.5

3.6

30

IDD1

IDD2

IDD3

I^DD4

8.38 MHz crystal oscillation operating mode^{Note 2}

8.38 MHz crystal oscillation HALT mode

STOP mode

8.38 MHz crystal oscillation A/D operating mode

18.0

Notes 1. The power supply current does not include the current flowing through the on-chip pull-up resistors.

2. During high-speed mode operation (when the processor clock control register (PCC) is cleared to 00H.)

Remark Unless otherwise specified, the characteristics of alternate function pins are the same as those of port

pins.

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

AC Characteristics

(1) Basic operations (T^A= −40 to +85°C, VDD = 4.0 to 5.5 V)

Parameter

Symbol

Conditions

When PCC is set to 00H

When PCC is set to 02H

MIN.

0.24

0.94

0

TYP.

MAX.

0.25

1.00

4.0

Unit

µs

Cycle time (minimum instruction

execution time)

TCY

µs

TI80, TI81 input frequency

fTI

MHz

µs

TI80, TI81 input high/low-level width fTIH, fTIL

0.1

10

µs

Interrupt input high/low-level width

RESET input low-level width

fINTH, fINTL

fRSL

INTP0, INTP1

µs

10

(2) Serial interface (UART) (T^A= −40 to +85°C, VDD = 4.0 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

bps

Transfer rate

At fx = 8.38 MHz operation

115200

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

AC Timing Measurement Points (Except X1 Input)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Measurement points

Clock Timing

1/f

X

t

XL

t

XH

V

IH4 (MIN.)

X1 input

VIL4 (MAX.)

TI Timing

tTIL

tTIH

TI80, TI81

Interrupt Input Timing

t

INTL

t

INTH

INTP0, INTP1

RESET Input Timing

tRSL

RESET

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

A/D Converter Characteristics (TA = −40 to +85°C, VDD = 4.0 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

8

TYP.

8

MAX.

8

Unit

bit

Resolution

Overall error^Note

1.5

LSB

µs

Conversion time

Analog input voltage

tCONV

VIAN

14

0

VDD

V

Note Excludes quantization error ( 1/2 LSB).

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T^A= −40 to +85°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

4.0

0

TYP.

MAX.

5.5

Unit

V

Data retention supply voltage

Release signal set time

µs

Oscillation stabilization wait time^{Note 1}

tWAIT

Cleared by RESET

Cleared by an interrupt request

2¹⁵/fx

ms

Note 2

Notes 1. The oscillation stabilization time is a period in which the operation of the CPU is stopped in order to

avoid unstable operation at the start of oscillation.

2. The typical (TYP) value can be selected from 2¹²/fx, 2¹⁵/fx, or 2¹⁷/fx by bits 0 to 2 (OSTS0 to OSTS2) of

the oscillation stabilization time selection register.

Remark fx: System clock oscillation frequency

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

Data Retention Timing (STOP Mode Release by RESET)

Internal reset operation

HALT mode

STOP mode

Operation mode

Data hold mode

VDD

V

DDDR

tSREL

Stop instruction execution

RESET

tWAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

HALT mode

STOP mode

Operation mode

Data hold mode

V

DD

V

DDDR

t

SREL

Stop instruction execution

Standby release signal

(interrupt request)

t

WAIT

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CHAPTER 19 ELECTRICAL SPECIFICATIONS

Flash Memory Programming Characteristics

Basic characteristics (T^A= 10 to 40°C, VDD = 4.0 to 5.5 V)

Parameter

Clock frequency

Symbol

Conditions

MIN.

8.0

TYP.

MAX.

8.5

Unit

MHz

V

fX

Power supply voltage

VPPL

VPPH

VPP

During VPP low-level detection

During VPP high-level detection

During VPP high-voltage detection

0

0.2VDD

1.2VDD

10.3

50

0.8VDD

9.7

VDD

V

10.0

V

VDD power supply current

VPP power supply current

Write time

IDD

mA

µs

IPP

VPP = 10 V

1 byte

100

TWRT

CWRT

TERASE

50

6

500

Number of rewrites

Erase time

20

Times

s

200

User’s Manual U13776EJ3V1UD

CHAPTER 20 PACKAGE DRAWINGS

44-PIN PLASTIC QFP (10x10)

A

B

23

22

33

34

detail of lead end

S

C

D

R

Q

12

11

44

1

F

P

J

M

G

H

I

K

M

N

S

L

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.16 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

13.2 0.2

10.0 0.2

13.2 0.2

1.0

G

1.0

+0.08

H

0.37

−0.07

0.16

I

J

0.8 (T.P.)

1.6 0.2

0.8 0.2

K

L

+0.06

M

0.17

−0.05

0.10

N

P

Q

2.7 0.1

0.125 0.075

+7°

3°

R

S

−3°

3.0 MAX.

S44GB-80-3BS-2

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CHAPTER 20 PACKAGE DRAWINGS

44 PIN PLASTIC LQFP (10x10)

A

B

detail of lead end

23

22

33

34

S

P

T

C

D

R

L

12

11

44

U

1

Q

F

J

M

G

H

I

K

M

N

S

ITEM MILLIMETERS

NOTE

Each lead centerline is located within 0.20 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

12.0 0.2

10.0 0.2

12.0 0.2

1.0

G

1.0

+0.08

H

0.37

−0.07

I

0.20

J

K

L

0.8 (T.P.)

1.0 0.2

0.5

+0.03

0.17

M

−0.06

N

P

Q

0.10

1.4 0.05

0.1 0.05

+4°

3°

R

−3°

S

T

1.6 MAX.

0.25 (T.P.)

0.6 0.15

U

S44GB-80-8ES-2

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CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS

The µPD789842 Subseries^Noteshould be soldered and mounted under the following recommended conditions.

For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales

representative.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Note Evaluation of the soldering conditions for the GB-3BS-MTX type is not yet complete.

Table 21-1. Surface Mounting Type Soldering Conditions

(1) µPD789841GB-×××-8ES

µPD789842GB-×××-8ES

µPD78F9842GB-8ES

Soldering Method

Infrared reflow

VPS

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

IR35-00-2

VP15-00-2

WS60-00-1

−

Count: Two times or less

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),

Count: Two times or less

Wave soldering

Partial heating

Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120°C max. (package surface temperature)

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

(2) µPD789841GB-×××-8ES-A

µPD789842GB-×××-8ES-A

µPD78F9842GB-8ES-A

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),

Count: Three times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C

for 20 to 72 hours)

Infrared reflow

IR60-207-3

−

Wave soldering

Partial heating

For details, contact an NEC Electronics sales representative.

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remark Products that have the part numbers suffixed by "-A" are lead-free products.

User’s Manual U13776EJ3V1UD

203

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for development of systems using the µPD789842 Subseries.

Figure A-1 shows development tools.

• Support of PC98-NX series

Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX

series. When using the PC98-NX series, refer to the explanation of IBM PC/AT compatibles.

• Windows

Unless specified otherwise, “Windows” indicates the following operating systems.

• Windows 3.1

• Windows 95, 98, 2000

• Windows NT™ Ver. 4.0

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tools

Software package

·

Software package

Language processing software

Debugging software

·

Assembler package

C compiler package

Device file

·

Integrated debugger

System emulator

C library source file^{Note 1}

Control software

·

Project manager

(Windows version only)^{Note 2}

Host machine

(PC or EWS)

Interface adapter

Power supply unit

Flash memory writing tools

Flash programmer

In-circuit emulator

Emulation board

Flash memory

writing adapter

Flash memory

Emulation probe

Conversion socket or

conversion adapter

Target system

Notes 1. The C library source file is not included in the software package.

2. The project manager is included in the assembler package and is available only for Windows.

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APPENDIX A DEVELOPMENT TOOLS

A.1 Software Package

SP78K0S

Various software tools for 78K/0S development are integrated in one package.

The following tools are included.

Software package

RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files

Part number: µS××××SP78K0S

Remark ×××× in the part number differs depending on the operating system used.

µS×××× SP78K0S

××××

AB17

BB17

Host Machine

PC-9800 series,

IBM PC/AT and compatibles

OS

Supply Medium

CD-ROM

Japanese Windows

English Windows

A.2 Language Processing Software

RA78K0S

Program that converts program written in mnemonic into object codes that can be executed by a

microcontroller.

Assembler package

In addition, automatic functions to generate a symbol table and optimize branch instructions are also

provided.

Used in combination with a device file (DF789842) (sold separately).

The assembler package is a DOS-based application but may be used in the Windows environment

by using the project manager of Windows (included in the package).

Part number: µS××××RA78K0S

CC78K0S

Program that converts program written in C language into object codes that can be executed by a

microcontroller.

C compiler package

Used in combination with an assembler package (RA78K0S) and device file (DF789842) (both sold

separately).

The C compiler package is a DOS-based application but may be used in the Windows environment

by using the project manager of Windows (included in the assembler package).

Part number: µS××××CC78K0S

DF789842^{Note 1}

Device file

File containing the information inherent to the device.

Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold

separately).

Part number: µS××××DF789842

CC78K0S-L^{Note 2}

Source file of functions constituting the object library included in the C compiler package.

Necessary for changing the object library included in the C compiler package according to the

customer’s specifications.

C library source file

Since this is a source file, its working environment does not depend on any particular operating

system.

Part number: µS××××CC78K0S-L

Notes 1. DF789842 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.

2. CC78K0S-L is not included in the software package (SP78K0S).

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APPENDIX A DEVELOPMENT TOOLS

Remark ×××× in the part number differs depending on the host machine and operating system used.

µS××××RA78K0S

µS××××CC78K0S

××××

AB13

Host Machine

PC-9800 series,

OS

Supply Media

3.5” 2HD FD

Japanese Windows

English Windows

Japanese Windows

English Windows

HP-UX^TM(Rel.10.10)

IBM PC/AT and compatibles

BB13

AB17

BB17

3P17

3K17

CD-ROM

HP9000 series 700^TM

SPARCstation^TM

SunOS^TM(Rel.4.1.4),

Solaris^TM(Rel.2.5.1)

µS××××DF789842

µS××××CC78K0S-L

××××

AB13

BB13

3P16

3K13

3K15

Host Machine

OS

Supply Medium

PC-9800 series,

Japanese Windows

English Windows

HP-UX (Rel.10.10)

3.5” 2HD FD

IBM PC/AT and compatibles

HP9000 series 700

SPARCstation

DAT

SunOS (Rel.4.1.4),

Solaris (Rel.2.5.1)

3.5” 2HD FD

1/4” CGMT

A.3 Control Software

Control software provided for efficient user program development in the Windows

environment. The project manager allows a series of tasks required for user program

development to be performed, including starting the editor, building, and starting the

debugger.

Project manager

The project manager is included in the assembler package (RA78K0S).

It cannot be used in an environment other than Windows.

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APPENDIX A DEVELOPMENT TOOLS

A.4 Flash Memory Writing Tools

Flashpro III (FL-PR3, PG-FP3)

Flashpro IV (FL-PR4, PG-FP4)

Flash programmer

Flash programmer dedicated to microcontrollers incorporating flash memory.

FA-44GB

Flash memory writing adapter. Used in connection with Flashpro III or Flashpro IV.

FA-44GB-8ES

FA-44GB:

For 44-pin plastic QFP (GB-3BS type)

Flash memory writing adapter

FA-44GB-8ES: For 44-pin plastic LQFP (GB-8ES type)

Remark FL-PR3, FL-PR4, FA-44GB, and FA-44GB-8ES are products of Naito Densei Machida Mfg. Co., Ltd.

For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)

A.5 Debugging Tools (Hardware)

IE-78K0S-NS

In-circuit emulator for debugging hardware and software of application system using the

78K/0S Series. Can be used with an integrated debugger (ID78K0S-NS). Used in

combination with an AC adapter, emulation probe, and interface adapter for connecting the

host machine.

In-circuit emulator

IE-78K0S-NS-A

In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further

enhanced by adding a coverage function and enhancing the tracer and timer functions.

In-circuit emulator

IE-70000-MC-PS-B

AC adapter

Adapter for supplying power from a 100 to 240 VAC outlet.

IE-70000-98-IF-C

Interface adapter

Adapter required when using a PC-9800 series (except notebook type) as the host machine (C

bus supported).

IE-70000-CD-IF-A

PC card interface

PC card and interface cable required when using a notebook type PC as the host machine

(PCMICA socket supported).

IE-70000-PC-IF-C

Interface adapter

Adapter required when using an IBM PC/AT or compatible as the host machine (ISA bus

supported).

IE-70000-PCI-IF-A

Interface adapter

Adapter required when using a personal computer incorporating the PCI bus as the host

machine.

IE-789842-NS-EM1

Emulation board

Emulation board for emulating the peripheral hardware inherent to the device.

Used in combination with an in-circuit emulator.

NP-44GB-TQ

Probe for connecting the in-circuit emulator and target system.

Used in combination with TGB-044SAP.

NP-H44GB-TQ

Emulation probe

TGB-044SAP

Conversion adapter

Conversion adapter used to connect a target system board designed to allow mounting a 44-

pin plastic QFP (GB-3BS type) or 44-pin plastic LQFP (GB-8ES type) and the NP-44GB-

TQ/NP-H44GB-TQ.

Remarks 1. NP-44GB-TQ and NP-H44GB-TQ are products of Naito Densei Machida Mfg. Co., Ltd.

For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)

2. TGB-044SAP is a product made by TOKYO ELETECH CORPORATION.

For further information, contact: Daimaru Kogyo, Ltd.

Tokyo Electronics Department (TEL +81-3-3820-7112)

Osaka Electronics Department (TEL +81-6-6244-6672)

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APPENDIX A DEVELOPMENT TOOLS

A.6 Debugging Tools (Software)

ID78K0S-NS

This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the

78K/0S Series. The ID78K0S-NS is Windows-based software.

Integrated debugger

It has improved C-compatible debugging functions and can display the results of tracing with the

source program using an integrating window function that associates the source program,

disassemble display, and memory display with the trace result.

Used in combination with a device file (DF789842) (sold separately).

Part number: µS××××ID78K0S-NS

SM78K0S

This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.

It can be used to debug the target system at C source level of assembler level while simulating

the operation of the target system on the host machine.

System simulator

Using SM78K0S, the logic and performance of the application can be verified independently of

hardware development. Therefore, the development efficiency can be enhanced and the

software quality can be improved.

Used in combination with a device file (DF789842) (sold separately).

Part number: µS××××SM78K0S

DF789842^Note

Device file

File containing the information inherent to the device.

Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold

separately).

Part number: µS××××DF789842

Note DF789842 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.

Remark ×××× in the part number differs depending on the operating system used and the supply medium.

µS××××ID78K0S-NS

µS××××SM78K0S

××××

AB13

Host Machine

PC-9800 series,

IBM PC/AT and compatibles

OS

Supply Medium

3.5” 2HD FD

Japanese Windows

English Windows

Japanese Windows

English Windows

BB13

AB17

BB17

CD-ROM

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APPENDIX B NOTES ON TARGET SYSTEM DESIGN

The following shows the conditions when connecting the emulation probe and conversion adapter. Consider the

shape of the components to be mounted on the target system and follow the configurations below when designing the

system.

Among the products described in this appendix, NP-44GB-TQ and NP-H44GB-TQ are products of Naito Densei

Machida Mfg. Co., Ltd. and TGB-044SAP is a product of TOKYO ELETECH CORPORATION.

Table B-1. Distance Between IE System and Conversion Adapter

Emulation Probe

NP-44GB-TQ

NP-H44GB-TQ

Conversion Adapter

TGB-044SAP

Distance Between IE System and Conversion Adapter

170 mm

370 mm

Figure B-1. Distance Between IE System and Conversion Adapter

In-circuit emulator

IE-78K0S-NS or IE-78K0S-NS-A

Target system

Emulation board

IE-789842-NS-EM1

170 mm^Note

Emulation probe

NP-44GB-TQ

Conversion adapter: TGB-044SAP

NP-H44GB-TQ

Note The above distance shows when the NP-44GB-TQ is used. When the NP-H44GB-TQ is used, the

distance is 370 mm.

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APPENDIX B NOTES ON TARGET SYSTEM DESIGN

Figure B-2. Connection Conditions of Target System (NP-44GB-TQ)

Emulation board

IE-789842-NS-EM1

Emulation probe

NP-44GB-TQ

24.8 mm

Conversion adapter

TGB-044SAP

10.95 mm

25 mm

16.65 mm

Pin 1

16.65 mm

40 mm

34 mm

Target system

Figure B-3. Connection Conditions of Target System (NP-H44GB-TQ)

Emulation board

IE-789842-NS-EM1

Emulation probe

NP-H44GB-TQ

23 mm

Conversion adapter

TGB-044SAP

10.95 mm

16.65 mm

10 mm

Pin 1

16.65 mm

42 mm

45 mm

Target system

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User’s Manual U13776EJ3V1UD

APPENDIX C REGISTER INDEX

C.1 Register Name Index (Alphabetic Order)

10-bit buffer register 0 (BFCM0).............................................................................................................................72

10-bit buffer register 1 (BFCM1).............................................................................................................................72

10-bit buffer register 2 (BFCM2).............................................................................................................................72

10-bit buffer register 3 (BFCM3).............................................................................................................................72

10-bit compare register 0 (CM0).............................................................................................................................72

10-bit compare register 1 (CM1).............................................................................................................................72

10-bit compare register 2 (CM2).............................................................................................................................72

10-bit compare register 3 (CM3).............................................................................................................................72

10-bit multiplication data register A1 (MRA1H, MRA1L).......................................................................................142

10-bit multiplication data register B1 (MRB1H, MRB1L).......................................................................................142

20-bit multiplication result registers (MUL1HL, MUL1LH, MUL1LL) .....................................................................142

8-bit compare register 80 (CR80) ...........................................................................................................................87

8-bit compare register 81 (CR81) ...........................................................................................................................87

8-bit compare register 82 (CR82) ...........................................................................................................................87

8-bit timer mode control register 80 (TMC80).........................................................................................................88

8-bit timer mode control register 81 (TMC81).........................................................................................................89

8-bit timer mode control register 82 (TMC82).........................................................................................................90

8-bit timer counter 80 (TM80).................................................................................................................................87

8-bit timer counter 81 (TM81).................................................................................................................................87

8-bit timer counter 82 (TM82).................................................................................................................................87

[A]

A/D conversion result register (ADCRH) ..............................................................................................................111

A/D converter mode register (ADM) .....................................................................................................................113

A/D input selection register (ADS)........................................................................................................................114

Asynchronous serial interface mode register 00 (ASIM00)...................................................................125, 129, 130

Asynchronous serial interface status register 00 (ASIS00)...........................................................................127, 132

[B]

[D]

[E]

[I]

Baud rate generator control register 00 (BRGC00) ......................................................................................127, 133

Dead time reload register (DTIME).........................................................................................................................73

External interrupt mode register 0 (INTM0) ..........................................................................................................152

Interrupt mask flag register 0 (MK0) .....................................................................................................................151

Interrupt mask flag register 1 (MK1) .....................................................................................................................151

Interrupt request flag register 0 (IF0)....................................................................................................................150

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APPENDIX C REGISTER INDEX

Interrupt request flag register 1 (IF1)....................................................................................................................150

Inverter timer control register 7 (TMC7)..................................................................................................................74

Inverter timer mode register 7 (TMM7)...................................................................................................................76

[M]

Multiplier control register 1 (MULC1)....................................................................................................................143

[O]

Oscillation settling time selection register (OSTS)................................................................................................162

[P]

Port 0 (P0)..............................................................................................................................................................54

Port 1 (P1)..............................................................................................................................................................55

Port 2 (P2)..............................................................................................................................................................56

Port 6 (P6)..............................................................................................................................................................58

Port mode register 0 (PM0) ....................................................................................................................................59

Port mode register 1 (PM1) ....................................................................................................................................59

Port mode register 2 (PM2) ..............................................................................................................................59, 91

Processor clock control register (PCC)...................................................................................................................64

Pull-up resistor option register 0 (PU0)...................................................................................................................60

Pull-up resistor option register B2 (PUB2)..............................................................................................................61

[R]

[S]

[T]

Receive buffer register 00 (RXB00)......................................................................................................................124

Swapping function register 0 (SWP0)...................................................................................................................145

Timer clock selection register 2 (TCL2)................................................................................................................106

Transmit shift register 00 (TXS00)........................................................................................................................124

[W]

Watch timer mode control register (WTM)............................................................................................................101

Watchdog timer mode register (WDTM)...............................................................................................................107

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APPENDIX C REGISTER INDEX

C.2 Register Symbol Index (Alphabetic Order)

[A]

[B]

[C]

ADCRH:

ADM:

A/D conversion result register...........................................................................................................111

A/D converter mode register.............................................................................................................113

A/D input selection register...............................................................................................................114

Asynchronous serial interface mode register 00...............................................................125, 129, 130

Asynchronous serial interface status register 00 ......................................................................127, 132

ADS:

ASIM00:

ASIS00:

BFCM0:

BFCM1:

BFCM2:

BFCM3:

10-bit buffer register 0.........................................................................................................................72

10-bit buffer register 1.........................................................................................................................72

10-bit buffer register 2.........................................................................................................................72

10-bit buffer register 3.........................................................................................................................72

BRGC00: Baud rate generator control register 00 ....................................................................................127, 133

CM0:

CM1:

CM2:

CM3:

CR80:

CR81:

CR82:

10-bit compare register 0....................................................................................................................72

10-bit compare register 1....................................................................................................................72

10-bit compare register 2....................................................................................................................72

10-bit compare register 3....................................................................................................................72

8-bit compare register 80....................................................................................................................87

8-bit compare register 81....................................................................................................................87

8-bit compare register 82....................................................................................................................87

[D]

[I]

DTIME:

Dead time reload register....................................................................................................................73

IF0:

Interrupt request flag register 0.........................................................................................................150

Interrupt request flag register 1.........................................................................................................150

External interrupt mode register 0.....................................................................................................152

IF1:

INTM0:

[M]

MK0:

MK1:

Interrupt mask flag register 0 ............................................................................................................151

Interrupt mask flag register 1 ............................................................................................................151

MRA1H, MRA1L: 10-bit multiplication data register A1 .......................................................................................142

MRB1H, MRB1L: 10-bit multiplication data register B1 .......................................................................................142

MUL1HL, MUL1LH, MUL1LL: 20-bit multiplication result registers......................................................................142

MULC1:

Multiplier control register 1................................................................................................................143

[O]

[P]

OSTS:

Oscillation settling time selection register .........................................................................................162

P0:

P1:

P2:

Port 0..................................................................................................................................................54

Port 1..................................................................................................................................................55

Port 2..................................................................................................................................................56

214

User’s Manual U13776EJ3V1UD

APPENDIX C REGISTER INDEX

P6:

Port 6 ..................................................................................................................................................58

Processor clock control register..........................................................................................................64

Port mode register 0 ...........................................................................................................................59

Port mode register 1 ...........................................................................................................................59

Port mode register 2 .....................................................................................................................59, 91

Pull-up resistor option register 0 .........................................................................................................60

Pull-up resistor option register B2.......................................................................................................61

Receive buffer register 00.................................................................................................................124

PCC:

PM0:

PM1:

PM2:

PU0:

PUB2:

RXB00:

[S]

[T]

SWP0:

Swapping function register 0.............................................................................................................145

TCL2:

Timer clock selection register 2.........................................................................................................106

8-bit timer counter 80..........................................................................................................................87

8-bit timer counter 81..........................................................................................................................87

8-bit timer counter 82..........................................................................................................................87

Inverter timer control register 7...........................................................................................................74

8-bit timer mode control register 80 ....................................................................................................88

8-bit timer mode control register 81 ....................................................................................................89

8-bit timer mode control register 82 ....................................................................................................90

Inverter timer mode register 7.............................................................................................................76

Transmit shift register 00 ..................................................................................................................124

TM80:

TM81:

TM82:

TMC7:

TMC80:

TMC81:

TMC82:

TMM7:

TXS00:

[W]

WDTM:

WTM:

Watchdog timer mode register..........................................................................................................107

Watch timer mode control register ....................................................................................................101

215

User’s Manual U13776EJ3V1UD

APPENDIX D REVISION HISTORY

D.1 Major Revisions in This Edition

Page

Description

U13776JJ2V0UD00 → U13776JJ3V0UD00

p.24

CHAPTER 2 PIN FUNCTIONS

• Modification of description in 2.2.12 V^PP(µPD78F9842 only)

pp.37, 38, 47, 51, 52

CHAPTER 3 CPU ARCHITECTURE

• Modification of Figure 3-10 Data to Be Saved to Stack Memory

• Modification of Figure 3-11 Data to Be Restored from Stack Memory

• Modification of [Description example] in 3.4.2 Short direct addressing

• Addition of [Illustration] in 3.4.6 Based addressing

• Addition of [Illustration] in 3.4.7 Stack addressing

pp.64, 68

CHAPTER 5 CLOCK GENERATOR

• Modification of Figure 5-2 Format of Processor Clock Control Register

• Modification of description in 5.5 Clock Generator Operation

pp.91, 97

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 80, 81, 82

• Addition of description in 7.3 (4) Port mode register 2 (PM2)

• Modification of description in 7.5 Notes on Using 8-Bit Timer/Event Counters 80, 81, 82

pp.101, 103

pp.118, 121

CHAPTER 8 WATCH TIMER

• Addition of Caution 2 in Figure 8-2 Format of Watch Timer Mode Control Register

• Addition of Caution in Figure 8-3 Watch Timer/Interval Timer Operation Timing

CHAPTER 10 A/D CONVERTER

• Modification of Figure 10-6 Software-Started A/D Conversion

• Addition of (8) Input impedance of ANI0 to ANI7 pins in 10.5 Notes on Using A/D Converter

p.139

CHAPTER 11 SERIAL INTERFACE

• Modification of Caution in 11.4.2 (2) (d) Reception

pp.146, 147

CHAPTER 14 INTERRUPT FUNCTIONS

• Addition of description in 14.1 Interrupt Function Types

• Addition of Remark in Table 14-1 Interrupt Sources

Total revision of CHAPTER 17 µPD78F9842

p.173

p.193

Addition of CHAPTER 19 ELECTRICAL SPECIFICATIONS

Addition of CHAPTER 20 PACKAGE DRAWINGS

p.201

p.203

Addition of CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS

Total revision of description in APPENDIX A DEVELOPMENT TOOLS

Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN

Deletion of APPENDIX B EMBEDDED SOFTWARE

p.204

p.210

p.201 in 2nd edition

U13776JJ3V0UD00 → U13776JJ3V1UD00

Addition of lead-free products to 1.3 Ordering Information

p.14

Addition of lead-free products to CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS

p.203

216

User’s Manual U13776EJ3V1UD

APPENDIX D RIVISION HISTORY

D.2 Revisions up to Previous Edition

The revision history is described below. The “Applied to” column indicates the chapter in each edition.

Edition

2nd edition

Major Revisions from Previous Edition

Applied to

Throughout

Change of µPD789841, 789842, and 78F9842 status from under

development to development completed

Deletion of flash programmer Flashpro II

Addition of handling of AVDD and AVSS pins to Table 2-1 Type of I/O

CHAPTER 2 PIN

FUNCTIONS

Circuit for Each Pin and Handling of Unused Pins

Addition of caution description on rewriting CR8n in 7.2 (1) 8-bit compare

CHAPTER 7 8-BIT

TIMER/EVENT

COUNTER

register 8n (CR8n)

Modification of description of operations in 7.4.1 Operation as interval

timer

Modification of description of operations in 7.4.2 Operation as external

event counter

Modification of description of operations in 7.4.3 Operation as square-

wave output

Addition of 17.1.4 Example of settings for Flashpro III (PG-FP3)

Revision of APPENDIX A DEVELOPMENT TOOLS

CHAPTER 17

µPD78F9842

APPENDIX A

DEVELOPMENT

TOOLS

217

User’s Manual U13776EJ3V1UD


型号：	UPD78F9842GB-8ES-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	8-bit Microcontrollers (Non Promotion), LQFP, / 微控制器
文件：	总219页 (文件大小：1186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD78F9842GB-8ES-A [RENESAS]

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