UPD800261F1-523-HN2-A [RENESAS]
IC,LAN NODE CONTROLLER,MOS,BGA,304PIN;
| 型号： | UPD800261F1-523-HN2-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,LAN NODE CONTROLLER,MOS,BGA,304PIN 局域网 |
| 文件： | 总49页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD800261
ERTEC 200
Enhanced Real-Time Ethernet Controller
with 32-bit RISC CPU Core
DESCRIPTION
ERTEC 200 is a powerful communication block for development of industrial Ethernet devices. ERTEC
200 contains a 32-bit RISC processor, an external memory interface with SDRAM and SRAM control-
ler, an LBU interface, a 2-channel real-time Ethernet interface with integrated PHYs, synchronous and
asynchronous serial ports, and general purpose I/Os. Its robust construction, specific automation func-
tions, and openness to the IT world are distinguishing features. The ERTEC 200 is housed in a 304-pin
plastic FBGA package (19 mm × 19 mm).
Detailed functions are described in the following user’s manual. Be sure to read this manual
when you design your systems.
Preliminary User’s Manual ERTEC 200
: A17988EE1V0UM00
FEATURES
•
ARM946E-S core with max. 150 MHz
•
•
Local bus unit (LBU) with 16-bit data bus to
connect external host with access to internal
ERTEC 200 resources
IRT switch block with 2 Ethernet ports
(10/100 Mbps) supporting RT and IRT traffic
- integrated Ethernet PHYs
- autonegotiation, broadcast filter
- 64 kBytes internal communication SRAM
one UART (16550 like) and one SPI interface
two 32-bit timers with prescaler, one 16-bit
timer, one 32-bit F-timer and two watchdog
timers
Max. 45 GPIOs, partly usable as interrupts
- Max. 32 GPIOs, if LBU interface is used
Various configuration options selectable during
reset
- 8 kBytes of instruction cache
- 4 kBytes of data cache
- 4 kBytes of D-TCM
- Memory protection unit
- On-chip debug and trace functionality via
JTAG interface
- ETM9 embedded trace macrocell
- Interrupt controller for 16 IRQs and 8 FIQs
Internal Multilayer AHB bus running at 50 MHz
External memory interface (EMIF) supports up
to 128 MBytes of SDRAM and up to 64 MBytes
for static memories and I/O with 4 chip selects
Single-channel DMA controller for high-speed
memory-to-memory transfers and for serial
interface support
•
•
•
•
•
•
•
•
•
•
1.5 V (logic) and 3.3 V (I/O) power supply
Temperature range: TA = -40 to 85°C
Compact 304-pin plastic FBGA package
•
•
Integrated PLL to generate internal clocks for
ARM946E-S, AHB, APB and IRT switch
Predefined Boot ROM content supporting
different download sources
ORDERING INFORMATION
Device
Part Number
Package
µPD800261F1-523-HN2
µPD800261F1-523-HN2-A
ERTEC 200
P-FBGA304, 19 × 19 mm
Remark: Products with -A at the end of the part number are lead-free products.
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative
for availability and additional information.
© NEC Electronics Corporation 2007
Document No. A17989EE1V1DS00
Data Published: May 2007
µPD800261
INTERNAL BLOCK DIAGRAM
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Preliminary Data Sheet A17989EE1V1DS00
2
µPD800261
PIN IDENTIFICATION
(1/2)
A(23:0)
: Address bus
SPI1_SSPRXD
SPI1_SSPTXD
SPI1_SCLKOUT
SPI1_SFRMOUT
SPI1_SFRMIN
SPI1_SCLKIN
: SPI receive data
D(31:0)
: Data bus
: SPI transmit data
: SPI clock out
WR_N
: Write strobe
: Read strobe
: Clock to SDRAM
RD_N
: SPI serial frame output
: SPI serial frame input
: SPI clock in
CLK_SDRAM
BE(3:0)_DQM(3:0)_N : Byte enable
CS_SDRAM_N
RAS_SDRAM_N
CAS_SDRAM_N
: Chip select to SDRAM
SPI1_SSPCTLOE
: SPI clock and serial frame
output enable
: Row address strobe to
SDRAM
SPI1_SSPOE
TXD_P(2:1) 0
: SPI output enable
: Column address strobe to
SDRAM
: MII transmit data bit 0
WE_SDRAM_N
CS_PER(3:0)_N
RDY_PER_N
DTR_N
: RD/WR SDRAM
: Chip select
TXD_P(2:1) 1
TXD_P(2:1) 2
TXD_P(2:1) 3
RXD_P(2:1) 0
: MII transmit data bit 1
: MII transmit data bit 2
: MII transmit data bit 3
: MII receive data bit 0
: Ready signal
: Direction signal for external
driver or scan clock
OE_DRIVER_N
: Enable signal for external
driver or scan clock
RXD_P(2:1) 1
: MII receive data bit 1
BOOT(3:0)
CONFIG(6:1)
GPIO(44:0)
UART-TXD
: Boot mode
RXD_P(2:1) 2
RXD_P(2:1) 3
TX_EN_P(2:1)
TX_ERR_P(2:1)
RX_ER_P(2:1)
CRS_P(2:1)
: MII receive data bit 2
: MII receive data bit 3
: MII transmit enable
: MII transmit error
: MII receive error
: System configuration
: GPIO pins
: UART transmit data output
: UART receive data input
UART-RXD
UART-DCD_N
: UART carrier detection
signal
: MII carrier sense
UART-DSR_N
UART-CTS_N
: UART data set ready signal
RX_DV_P(2:1)
COL_P(2:1)
: MII receive data valid
: MII collision
: UART transmit enable
signal
LBU_A(20:0)
LBU_D(15:0)
LBU_WR_N
: LBU address bus
: LBU data bus
RX_CLK_P(2:1)
TX_CLK_P(2:1)
SMI_MDC
: MII receive clock
: MII transmit clock
: LBU write control
: LBU read control
: LBU byte enable
: LBU page selection
: LBU interrupt request
: LBU ready signal
: MII SMI clock
LBU_RD_N
SMI_MDIO
RES_PHY_N
P(2:1)TxP
: MII SMI input/output
: Reset to PHY
LBU_BE(1:0)_N
LBU_SEG_(1:0)
LBU_IRQ_(1:0)_N
LBU_RDY_N
LBU_CS_M_N
: Differential transmit output
: Differential transmit output
: Differential receive input
: Differential receive input
P(2:1)TxN
P(2:1)RxP
: LBU chip select to ERTEC
200 internal resources
P(2:1)RxN
LBU_CS_R_N
: LBU chip select to page
configuration registers
P(2:1)TDxP
: FX differential transmit out-
put
Preliminary Data Sheet A17989EE1V1DS00
3
µPD800261
(2/2)
: Debug request to ARM9
P(2:1)TDxN
: FX differential transmit out-
put
DBGREQ
P(2:1)RDxP
: FX differential receive input
: FX differential receive input
: FX differential SD input
: FX differential SD input
: Reference resistor 12.4 kΩ
: PHY LED
DBGACK
TAP_SEL
CLKP_A
: Debug acknowledge
: Select TAP controller
: Quartz connection
: Quartz connection
: Reference clock output
: Clock for F-counter
: Power On reset
P(2:1)RDxN
P(2:1)SDxP
P(2:1)SDxN
CLKP_B
EXTRES
REF_CLK
F_CLK
P(2:1)DUPLEX-LED_N
P(2:1)LINK-LED_N
: PHY LED
RESET_N
WD_WDOUT0_N
P(2:1)-SPEED-100LED_N
(TX/FX)
: PHY LED
: Watchdog output
: PHY LED
VDD Core
: Power supply for core,
1.5 V
P(2:1)-SPEED-10LED_N
P(2:1)-RX-LED_N
P(2:1)-TX-LED_N
P(2:1)-ACTIVE-LED_N
PLL_EXT_IN_N
: PHY LED
GND Core
VDD IO
: GND for core
: PHY LED
: Power supply for IO, 3.3 V
: GND for IO
: PHY LED
GND IO
: MC_PLL input signal
PLL_AVDD
: Analog power supply for
PLL, 1.5 V
TGEN_OUT1_N
TRACEPKT(7:0)
: MC_PLL output signal
: Trace pins of ETM
PLL_AGND
: Analog GND for PLL
VDDQ (PECL)
: Power supply for PECL
buffers, 3.3 V
ETMEXTOUT
ETMEXTIN1
: ETM output signal
: ETM input signal
GND (PECL)
DVDD(4:1)
: GND for PECL buffers
: Digital power supply for
PHYs, 1.5 V
PIPESTA(2:0)
TRACESYNC
: Trace pipeline status
: Trace sync signal
DGND(4:1)
: Digital GND for PHYs
P(2:1)VDDARXTX
: Analog port Tx/Rx power
supply, 1.5 V
TRACECLK
TRST_N
TCK
: ETM trace or scan clock
: JTAG reset
P(2:1)VSSARX
: Analog port GND
P(2:1)VSSATX(2:1) : Analog port GND
: JTAG clock
VDDAPLL
: Analog central power sup-
ply, 1.5 V
TDI
: JTAG data in
VDDACB
: Analog central power sup-
ply, 3.3 V
TMS
TDO
: JTAG test mode select
: JTAG data out
VSSAPLLCB
VDD33ESD
: Analog central GND
: Analog test power supply,
3.3 V
SRST_N
: Hardware reset for debug
usage
GND33ESD
: Analog test GND
Preliminary Data Sheet A17989EE1V1DS00
4
µPD800261
PIN CONFIGURATION
•
304-Pin Plastic FBGA (19 mm × 19 mm)
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AA W U R N L J G E C A
AB Y V T P M K H F D B
INDEX MARK
(1/5)
Pin
Number
Pin
Pin Name
Pin Name
Number
A2
VDD IO
A21
B1
GND Core
A3
A1
GND IO
A4
WR_N
B2
A3
A5
CS_PER1_N
CS_PER2_N
GPIO26
B3
A2
A6
B4
A0
A7
B5
RD_N
A8
GND IO
B6
CS_PER3_N
RESET_N
A9
VDD IO
B7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
VDD IO
B8
GPIO30
GPIO21/SPI1_SFRMOUT
GND IO
B9
GPIO25/TGEN_OUT1_N
GPIO27
B10
B11
B12
B13
B14
B15
B16
B17
B18
GPIO16/SPI1_SSPCTLOE
VDD IO
GPIO24/PLL_EXT_IN_N
GPIO18/SPI1_SSPRXD
F_CLK
REF_CLK
GPIO12/UART-CTS-N
GPIO9/UART-RXD
VDD IO
CLKP_A
GPIO13
GPIO10/UART-DCD-N
GPIO8/UART-TXD
GPIO4/P1-LINK-LED_N
GND IO
GPIO6/P1-RX-LED_N/P1-TX-LED_N/P1-ACTIVE-LED_N
Preliminary Data Sheet A17989EE1V1DS00
5
µPD800261
(2/5)
Pin
Number
Pin
Number
Pin Name
Pin Name
B19
B20
B21
B22
C1
GPIO3/P2-SPEED-100LED_N/P2-SPEED-10LED_N
E13
E14
E15
E16
E17
E18
VDD Core
GPIO1/P2 -DUPLEX-LED_N
GPIO15/WD_WDOUT0_N
GPIO14/DBGACK
GPIO11/UART-DSR-N
GND Core
GND IO
VDD IO
A6
C2
A5
VDD Core
C21
C22
D1
P1TDxP
E19
E21
E22
F1
GNDNote
P1TDxN
P1RDxN
A8
P1RDxP
D2
A7
A12
D4
A4
F2
A11
D5
CS_PER0_N
F4
A20/CONFIG3
GND Core
VDD Core
D6
VDD Core
F5
D7
RDY_PER_N
F6
D8
OE_DRIVER_N
VDD Core
F7
GND Core
GND IO
D9
F8
D10
D11
D12
D13
D14
D15
D16
D17
D18
GPIO23/SPI1_SCLKIN
GPIO20/SPI1_SCLKOUT
VDD Core
F9
GPIO28
F10
F13
F14
F15
F16
F17
F18
F19
GPIO22/SPI1_SFRMIN/DBGACK
PLL_AGND
GPIO17/SPI1_SSPOE
GND IO
GPIO19/SPI1_SSPTXD
CLKP_B
GPIO7/P2-RX-LED_N/P2-TX-LED_N/P2-ACTIVE-LED_N
GPIO5/P2-LINK-LED_N
GPIO2/P1-SPEED-100LED_N/P1-SPEED-10LED_N
VDD Core
GND Core
VDD Core
GND (PECL)
P1SDxN
D19
D21
D22
E1
GPIO0/P1-DUPLEX-LED_N
VDDQ (PECL)
VDDQ (PECL)
A10
F21
F22
G1
GNDNote
VDD33ESD
A14
G2
A13
E2
A9
G4
A21/CONFIG4
GND IO
GND Core
DGND2
DVDD1
E4
A19/CONFIG2
VDD Core
G5
E5
G6
E6
GND Core
G17
G18
G19
G21
G22
H1
E7
DTR_N/BOOT0
GPIO31/DBGREQ
GPIO29
E8
P1SDxP
P1RxP
E9
E10
E11
E12
GND IO
P1RxN
GND Core
VDD IO
PLL_AVDD
H2
A15/BOOT1
Note: Connect to GND to improve heat dissipation; pins may as well be left open.
Preliminary Data Sheet A17989EE1V1DS00
6
µPD800261
(3/5)
Pin
Number
Pin
Number
Pin Name
Pin Name
H4
H5
H6
A23/CONFIG6
A22/CONFIG5
GND IO
M4
WE_SDRAM_N
RAS_SDRAM_N
P2VSSATX1
M5
M18
H17
H18
H19
H21
H22
J1
GNDNote
GND33ESD
DVDD2
M19
M21
M22
N1
GNDNote
P2TxN
P2TxP
DGND1
VDD IO
D1
VDDACB
GND IO
N2
N4
BE0_DQM0_N
D20
J2
A16/BOOT2
BE2_DQM2_N
leave open
D18
N5
J4
N6
D21
J5
N17
N18
P2VSSARX
P2VDDARXTX
J6
J17
J18
P1VSSARX
GNDNote
N19
N21
GNDNote
GNDNote
J19
J21
J22
K1
P1VDDARXTX
P1TxN
N22
P1
P2
P4
P5
P6
GNDNote
D2
P1TxP
D3
A18/CONFIG1
A17/BOOT3
D16
D25
K2
BE3_DQM3_N
D22
K4
K5
K6
D17
D19
P17
P18
GNDNote
GNDNote
K17
K18
K19
P1VSSATX1
P1VSSATX2
VDDAPLL
P19
P21
P22
GNDNote
P2RxP
P2RxN
K21
GNDNote
R1
D4
K22
L1
GNDNote
R2
R4
R5
R6
R17
VDD Core
D26
CS_SDRAM_N
CAS_SDRAM_N
VDD Core
L2
D23
L4
D24
L5
GND Core
DGND3
L18
L19
L21
L22
M1
VSSAPLLCB
P2VSSATX2
EXTRES
R18
R19
R21
R22
T1
GNDNote
VDDQ (PECL)
DVDD4
DVDD3
GND IO
D5
leave open
CLK_SDRAM
D0
M2
T2
Note: Connect to GND to improve heat dissipation; pins may as well be left open.
Preliminary Data Sheet A17989EE1V1DS00
7
µPD800261
(4/5)
Pin
Number
Pin
Number
Pin Name
Pin Name
LBU_D13/SMI_MDIO
T4
D27
V15
V16
V17
V18
V19
V21
T5
leave open
GND Core
DGND4
LBU_D14/RES_PHY_N
GND IO
T6
T17
T18
T19
VDD Core
GND (PECL)
GND (PECL)
P2SDxP
VDDQ (PECL)
T21
VDD Core
V22
GNDNote
T22
U1
GNDNote
D6
W1
D9
W2
D10
U2
D7
W4
D29
U4
D28
W5
D30
U5
GND IO
VDD Core
GND IO
VDD Core
TDI
W6
D31
U6
W7
TCK
U7
W8
TAP_SEL
U8
W9
LBU_A16/GPIO32
LBU_A17/GPIO33
LBU_A15/COL_P2
LBU_A19/GPIO35
VDD Core
U9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W21
W22
Y1
U10
U13
U14
U15
U16
U17
U18
U19
U21
U22
V1
TRST_N
LBU_SEG_1/GPIO38
LBU_CS_M_N/GPIO40
GND IO
LBU_D12/SMI_MDC
LBU_D1/TXD_P11
LBU_D15/GPIO41
VDD Core
GND Core
VDD Core
P2SDxN
leave open
P2RDxN
LBU_IRQ1_N/GPIO44
LBU_RDY_N/GPIO42
P2TDxN
P2RDxP
BE1_DQM1_N
D8
VDD IO
V2
VDD IO
V4
VDD Core
Y2
D11
V5
VDD Core
Y21
Y22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
P2TDxP
V6
GND Core
VDD IO
V7
TMS
D12
V8
SRST_N
D13
V9
TDO
D15
V10
V11
V12
V13
V14
LBU_A18/GPIO34
GND Core
LBU_A1/RXD_P11/ETMEXTIN1
LBU_A2/RXD_P12/TRACEPKT7
LBU_A4/CRS_P1/TRACEPKT5
LBU_A6/RX_DV_P1/TRACEPKT3
LBU_A8/RXD_P20/TRACEPKT1
LBU_A20/GPIO36
LBU_SEG_0/GPIO37
GND Core
Note: Connect to GND to improve heat dissipation; pins may as well be left open.
Preliminary Data Sheet A17989EE1V1DS00
8
µPD800261
(5/5)
Pin
Number
Pin
Number
Pin Name
Pin Name
AA9
LBU_A10/RXD_P22/TRACESYNC
AB5
AB6
AB7
AB8
AB9
LBU_A3/RXD_P13/TRACEPKT6
LBU_A5/RX_ER_P1/TRACEPKT4
LBU_A7/COL_P1/TRACEPKT2
LBU_A9/RXD_P21/TRACEPKT0
VDD IO
AA10 LBU_A11/RXD_P23/PIPESTA2
AA11 LBU_A13/RX_ER_P2/PIPESTA0
AA12 LBU_WR_N/TX_CLK_P1
AA13 LBU_BE1_N/RX_CLK_P2
AA14 LBU_D0/TXD_P10
AA15 VDD Core
AB10 LBU_A12/CRS_P2/PIPESTA1
AB11 LBU_A14/RX_DV_P2
AB12 LBU_CS_R_N/GPIO39
AB13 LBU_RD_N/TX_CLK_P2
AB14 LBU_BE0_N/RX_CLK_P1
AB15 VDD IO
AA16 LBU_D3/TXD_P13
AA17 LBU_D5/TX_ERR_P1
AA18 LBU_D7/TXD_P21
AA19 LBU_D9/TXD_P23
AA20 LBU_D10/TX_EN_P2
AA21 LBU_IRQ0_N/GPIO43
AA22 GND Core
AB16 LBU_D2/TXD_P12
AB17 LBU_D4/TX_EN_P1
AB18 LBU_D6/TXD_P20
AB19 LBU_D8/TXD_P22
AB20 VDD IO
AB2
AB3
AB4
D14
LBU_A0/RXD_P10/ETMEXTOUT
TRACECLK
AB21 LBU_D11/TX_ERR_P2
Preliminary Data Sheet A17989EE1V1DS00
9
µPD800261
Table of Contents
1.
2.
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin Status and Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1
1.2
1.3
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1
2.2
2.3
2.4
2.4.1
Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I/O timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LBU timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.4.2
2.4.3
2.4.4
2.4.5
3.
4.
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Preliminary Data Sheet A17989EE1V1DS00
10
µPD800261
List of Figures
Figure 2-1:
Figure 2-2:
Figure 2-3:
Figure 2-4:
Figure 2-5:
Figure 2-6:
Figure 2-7:
Figure 2-8:
Figure 2-9:
Figure 3-1:
Clock Waveforms ........................................................................................................ 34
Input Setup and Hold Waveforms ............................................................................... 37
Output Delay Waveforms ............................................................................................ 37
LBU Read from ERTEC 200 with Separate Read/Write line....................................... 39
LBU Write to ERTEC 200 with Separate Read/Write line ........................................... 40
LBU Read from ERTEC 200 with Common Read/Write line....................................... 41
LBU Write to ERTEC 200 with Common Read/Write line ........................................... 42
Power-Up Sequence Timing Diagram......................................................................... 43
Reset Timing Diagram................................................................................................. 44
Package Drawing ........................................................................................................ 45
Preliminary Data Sheet A17989EE1V1DS00
11
µPD800261
List of Tables
Table 1-1:
Table 1-2:
Table 1-3:
Table 1-4:
Table 1-5:
Table 1-6:
Table 1-7:
Table 1-8:
Table 1-9:
External Memory Interface Pin Functions....................................................................... 13
Local Bus Interface Pin Functions.................................................................................. 14
MII Diagnosis Interface Pin Functions............................................................................ 16
PHY Interface Pin Functions .......................................................................................... 17
General Purpose I/O Pin Functions................................................................................ 18
UART Pin Functions....................................................................................................... 19
SPI1 Pin Functions......................................................................................................... 19
MC_PLL Pin Functions................................................................................................... 19
Clock and Reset Pin Functions ...................................................................................... 20
Table 1-10: JTAG and Debug Interface Pin Functions...................................................................... 20
Table 1-11: Trace Port Pin Functions................................................................................................ 21
Table 1-12: Power Supply Pin Functions........................................................................................... 21
Table 1-13: Alternative Functions of GPIO(31:0) Pins....................................................................... 22
Table 1-14: Pin Characteristics.......................................................................................................... 23
Table 1-15: Pin Status During Reset and Recommended Connections............................................ 25
Table 1-16: Alternative Functions of LBU Interface Pins................................................................... 27
Table 2-1:
Table 2-2:
Table 2-3:
Table 2-4:
Table 2-5:
Table 2-6:
Table 2-7:
Table 2-8:
Table 2-9:
Table 4-1:
Table 4-2:
Absolute Maximum Ratings............................................................................................ 29
Recommended Operating Conditions ............................................................................ 30
Thermal Characteristics of Package............................................................................... 32
Clock AC Characteristics................................................................................................ 33
I/O Timing Specifications................................................................................................ 35
LBU Read from ERTEC 200 with Separate Read/Write line.......................................... 39
LBU Write to ERTEC 200 with Separate Read/Write line .............................................. 40
LBU Read from ERTEC 200 with Common Read/Write line.......................................... 41
LBU Write to ERTEC 200 with Common Read/Write line .............................................. 42
Soldering Conditions for Non-lead-free Device .............................................................. 46
Soldering Conditions for Lead-free Device..................................................................... 46
Preliminary Data Sheet A17989EE1V1DS00
12
µPD800261
1. Pin Functions
1.1 List of Pin Functions
Table 1-1: External Memory Interface Pin Functions
I/O Function
Pin Name
A(23:18)
Alternate Function
I/ONote External memory address bus (23:18)
I/ONote External memory address bus (17:15)
CONFIG(6:1)Note
A(17:15)
BOOT(3:1)Note
A(14:0)
O
I/O
O
O
O
O
O
O
O
O
O
I
External memory address bus (14:0)
External memory data bus (31:0)
Write strobe signal
-
-
-
-
-
-
-
-
-
-
-
-
D(31:0)
WR_N
RD_N
Read strobe signal
CLK_SDRAM
CS_SDRAM_N
RAS_SDRAM_N
CAS_SDRAM_N
WE_SDRAM_N
CS_PER(3:0)_N
BE(3:0)_DQM(3:0)_N
RDY_PER_N
DTR_N
Clock to SDRAM
Chip select to SDRAM
Row address strobe SDRAM
Column address strobe to SDRAM
RD/WR signal to SDRAM
Chip select to static memories and peripherals
Byte enable signal
Ready signal
I/ONote
O
BOOT0Note
-
Direction signal for external driver or scan clock
Enable signal for external driver or scan clock
OE_DRIVER_N
Note: The BOOT(3:0) and CONFIG(6:1) pins are used as inputs and read into the BOOT_REG respectively
CONFIG_REG system configuration registers during the active Power On reset phase. After a reset,
these pins are available as normal function pins and used as outputs.
Preliminary Data Sheet A17989EE1V1DS00
13
µPD800261
Table 1-2: Local Bus Interface Pin Functions (1/2)
I/ONote
Alternate FunctionNote
Pin Name
LBU_A(20:16)
LBU_A15
LBU_A14
LBU_A13
LBU_A12
LBU_A11
LBU_A10
LBU_A9
Function
I
LBU address bits
LBU address bit 15
LBU address bit 14
LBU address bits 13
LBU address bit 12
LBU address bit 11
LBU address bit 10
LBU address bit 9
LBU address bit 8
LBU address bit 7
LBU address bit 6
LBU address bit 5
LBU address bit 4
LBU address bit 3
LBU address bit 2
LBU address bit 1
LBU address bit 0
LBU data bit 15
GPIO(36:32)
I
COL_P2
I
RX_DV_P2
I
I
RX_ER_P2/PIPESTA0
CRS_P2/PIPESTA1
RXD_P23/PIPESTA2
RXD_P22/TRACESYNC
RXD_P21/TRACEPKT0
RXD_P20/TRACEPKT1
COL_P1/TRACEPKT2
RX_DV_P1/TRACEPKT3
RX_ER_P1/TRACEPKT4
CRS_P1/TRACEPKT5
RXD_P13/TRACEPKT6
RXD_P12/TRACEPKT7
RXD_P11/ETMEXTIN1
RXD_P10/ETMEXTOUT
GPIO41
I
I
I
LBU_A8
I
LBU_A7
I
LBU_A6
I
LBU_A5
I
LBU_A4
I
LBU_A3
I
LBU_A2
I
LBU_A1
I
LBU_A0
I
LBU_D15
LBU_D14
LBU_D13
LBU_D12
LBU_D11
LBU_D10
LBU_D9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
LBU data bit 14
RES_PHY_N
LBU data bit 13
SMI_MDIO
LBU data bit 12
SMI_MDC
LBU data bit 11
TX_ERR_P2
LBU data bit 10
TX_EN_P2
LBU data bit 9
TXD_P23
LBU_D8
LBU data bit 8
TXD_P22
LBU_D7
LBU data bit 7
TXD_P21
LBU_D6
LBU data bit 6
TXD_P20
LBU_D5
LBU data bit 5
TX_ERR_P1
LBU_D4
LBU data bit 4
TX_EN_P1
LBU_D3
LBU data bit 3
TXD_P13
LBU_D2
LBU data bit 2
TXD_P12
LBU_D1
LBU data bit 1
TXD_P11
LBU_D0
LBU data bit 0
TXD_P10
LBU_WR_N
LBU_RD_N
LBU_BE(1:0)_N
LBU_SEG_1
LBU_SEG_0
LBU_IRQ_1_N
LBU_IRQ_0_N
LBU write control signal
LBU read control signal
LBU byte enable
LBU page selection signal
LBU page selection signal
LBU interrupt request signal
LBU interrupt request signal
TX_CLK_P1
I
TX_CLK_P2
I
RX_CLK_P(2:1)
GPIO38
I
I
GPIO37
O
O
GPIO44
GPIO43
Preliminary Data Sheet A17989EE1V1DS00
14
µPD800261
Table 1-2: Local Bus Interface Pin Functions (2/2)
I/ONote
Alternate FunctionNote
GPIO42
LBU chip select for ERTEC 200 internal resources GPIO40
LBU chip select for page configuration registers GPIO39
Pin Name
LBU_RDY_N
LBU_CS_M_N
LBU_CS_R_N
Function
O
I
LBU ready signal
I
Note: Local bus interface pins are alternatively used as MII diagnosis, trace or GPIO pins; in this table the I/O
type is listed for the local bus function.
Preliminary Data Sheet A17989EE1V1DS00
15
µPD800261
Table 1-3: MII Diagnosis Interface Pin Functions
Pin NameNote
SMI_MDC
SMI_MDIO
RES_PHY_N
TXD_P2(3:0)
RXD_P23
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function
Serial management interface clock
Serial management interface data input/output
Reset signal to PHYs
Alternate FunctionNote
LBU_D12
LBU_D13
LBU_D14
Transmit data port 2 bits
Receive data port 2 bit 3
Receive data port 2 bit 2
Receive data port 2 bit 1
Receive data port 2 bit 0
Transmit enable port 2
Carrier sense port 2
LBU_D(9:6)
LBU_A11/PIPESTA2
LBU_A10/TRACESYNC
LBU_A9/TRACEPKT0
LBU_A8/TRACEPKT1
LBU_D10
RXD_P22
RXD_P21
RXD_P20
TX_EN_P2
CRS_P2
LBU_A12
RX_ER_P2
TX_ERR_P2
RX_DV_P2
COL_P2
Receive error port 2
PIPESTA0
Transmit error port 2
LBU_D11
Receive data valid port 2
Collision port 2
LBU_A14
LBU_A15
RX_CLK_P2
TX_CLK_P2
TXD_P1(3:0)
RXD_P13
Receive clock port 2
LBU_BE1_N
Transmit clock port 2
LBU_RD_N
Transmit data port 1 bits
Receive data port 1 bit 3
Receive data port 1 bit 2
Receive data port 1 bit 1
Receive data port 1 bit 0
Transmit enable port 1
Carrier sense port 1
LBU_D(3:0)
LBU_A3/TRACEPKT6
LBU_A2/TRACEPKT7
LBU_A1/ETMEXTIN1
LBU_A0/ETMEXTOUT
LBU_D4
RXD_P12
RXD_P11
RXD_P10
TX_EN_P1
CRS_P1
LBU_A4/TRACEPKT5
LBU_A5/TRACEPKT4
LBU_D5
RX_ER_P1
TX_ERR_P1
RX_DV_P1
COL_P1
Receive error port 1
Transmit error port 1
Receive data valid port 1
Collision port 1
LBU_A6/TRACEPKT3
LBU_A7/TRACEPKT2
LBU_BE0_N
RX_CLK_P1
TX_CLK_P1
Receive clock port 1
Transmit clock port 1
LBU_WR_N
Note: MII diagnosis interface pins are alternatively used as local bus interface or trace pins; in this table the
I/O type is listed for the MII diagnosis function
Preliminary Data Sheet A17989EE1V1DS00
16
µPD800261
Table 1-4: PHY Interface Pin Functions
Pin Name
P(2:1)TxN
I/O
O
O
O
O
I
Function
Alternate Function
Differential transmit data output
Differential transmit data output
Differential FX transmit data output
Differential FX transmit data output
Differential receive data input
Differential receive data input
Differential FX receive data input
Differential FX receive data input
Differential FX signal detect input
Differential FX signal detect input
-
-
-
-
-
-
-
-
-
-
P(2:1)TxP
P(2:1)TDxN
P(2:1)TDxP
P(2:1)RxN
P(2:1)RxP
P(2:1)RDxN
P(2:1)RDxP
P(2:1)SDxN
P(2:1)SDxP
I
I
I
I
I
EXTRES
I/O
External reference resistor (12.4 kΩ) Note
Digital power supply, 1.5 V
Digital GND
-
-
-
-
-
-
-
-
-
-
-
DVDD(4:1)
I
I
I
I
I
I
I
I
I
I
DGND(4:1)
P(2:1)VSSATX(2:1)
P(2:1)VDDARXTX
P(2:1)VSSARX
VDDAPLL
Analog port GND
Analog port RX/TX power supply, 1.5 V
Analog port GND
Analog central power supply, 1.5 V
Analog central power supply, 3.3 V
Analog central GND
VDDACB
VSSAPLLCB
VDD33ESD
VSS33ESD
Analog test power supply, 3.3 V
Analog test GND
Note: The external resistor must have a maximum tolerance of 1%.
Preliminary Data Sheet A17989EE1V1DS00
17
µPD800261
Table 1-5: General Purpose I/O Pin Functions
Pin Name
GPIO(44:43)
GPIO42
GPIO41
GPIO40
GPIO39
GPIO(38:37)
GPIO(36:32)
GPIO31
GPIO(30:26)
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
I/ONote
Function
Alternate FunctionNote
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
General purpose I/O signal
LBU_IRQ(1:0)_N
LBU_RDY_N
LBU_D15
LBU_CS_M_N
LBU_CS_R_N
LBU_SEG(1:0)_N
LBU_A(20:16)
DBGREQ
-
TGEN_OUT1_N
PLL_EXT_IN_N
SPI1_SCLKIN
SPI1_SFRMIN/DBGACK
SPI1_SFRMOUT
SPI1_CLKOUT
SPI1_SSPTXD
SPI1_SSPRXD
SPI1_SSPOE
SPI1_SSPCTLOE
WD_WDOUT0_N
DBGACK
-
UART-CTS_N
UART-DSR_N
UART-DCD_N
UART-RXD
GPIO8
UART-TXD
GPIO7
P2-RX-LED_N/P2-TX-LED_N/P2-ACTIVE-LED_N
P1-RX-LED_N/P1-TX-LED_N/P1-ACTIVE-LED_N
P2-LINK-LED_N
GPIO6
GPIO5
GPIO4
P1-LINK-LED_N
GPIO3
P2-SPEED-100LED_N (TX/FX)/P2-SPEED-10LED_N
P1-SPEED-100LED_N (TX/FX)/P1-SPEED-10LED_N
P2-DUPLEX-LED_N
GPIO2
GPIO1
GPIO0
P1-DUPLEX-LED_N
Note: Primary and alternative functions for GPIO(31:0) are selected with the GPIO_PORT_MODE_H and
GPIO_PORT_MODE_L registers; primary and alternative functions for GPIO(44:32) are selected with
the configuration pins. In this table the I/O types are listed for the GPIO function.
Preliminary Data Sheet A17989EE1V1DS00
18
µPD800261
Table 1-6: UART Pin Functions
I/ONote
Alternate FunctionNote
GPIO8
Pin Name
UART-TXD
Function
UART transmit data output
UART receive data input
O
I
UART-RXD
GPIO9
UART-DCD_N
UART-DSR_N
UART-CTS_N
I
UART carrier detection signal
UART data set ready signal
UART transmit enable signal
GPIO10
GPIO11
GPIO12
I
I
Note: Primary and alternative functions are selected with the GPIO_PORT_MODE_H and
GPIO_PORT_MODE_L registers. In this table the I/O types are listed for the UART function.
Table 1-7: SPI1 Pin Functions
Pin Name
SPI1_SSPRXD
SPI1_SSPTXD
SPI1_SCLKOUT
SPI1_SFRMOUT
SPI1_SFRMIN
SPI1_SCLKIN
SPI1_SSPCTLOE
SPI1_SSPOE
I/ONote
Function
SPI1 receive data input
Alternate FunctionNote
GPIO18
I
O
O
O
I
SPI1 transmit data output
SPI1 clock output
GPIO19
GPIO20
SPI1 serial frame input signal
SPI1 serial frame output signal
SPI1 clock input
GPIO21
GPIO22, DBGACK
GPIO23
I
O
O
SPI1 clock and serial frame output enable GPIO16
SPI1 output enable GPIO17
Note: Function and alternative functions are selected with the GPIO_PORT_MODE_H and
GPIO_PORT_MODE_L registers. In this table the I/O types are listed for the SPI1 function.
Table 1-8: MC_PLL Pin Functions
Pin Name
I/ONote 1
Function
MC_PLL input signal
MC_PLL output signalNote 2
Alternate FunctionNote 1
GPIO24
GPIO25
PLL_EXT_IN_N
I
TGEN_OUT1_N
O
Notes: 1. Function and alternative functions are selected with the GPIO_PORT_MODE_H register. In this table
the I/O types are listed for the MC_PLL function.
2. For a PROFINET IRT application, GPIO25 must be configured as TGEN_OUT1_N output pin. A syn-
chronous clock signal is then output at this pin; during certification of a PROFINET IO device with
IRT support this signal must be accessible from the outside.
Preliminary Data Sheet A17989EE1V1DS00
19
µPD800261
Table 1-9: Clock and Reset Pin Functions
Pin Name
TRACECLK
CLKP_A
I/O
O
I
Function
ETM trace or scan clock
Quartz connection
Alternate Function
CLKP_B
O
I
Quartz connection
F_CLK
F_CLK for F-counter
Reference clock
REF_CLK
RESET_N
I/O
I
Power On reset
Table 1-10: JTAG and Debug Interface Pin Functions
Pin Name
TRST_N
TCK
I/ONote
Function
JTAG reset signal
Alternate FunctionNote
I
I
JTAG clock signal
TDI
I
JTAG data input signal
TMS
I
JTAG test mode select signal
JTAG data output signal
Hardware reset for debug usage
Debug request signal
TDO
O
I/O
I
SRST_N
DBGREQ
DBGACK
TAP_SEL
GPIO31
GPIO14/GPIO22/SPI1_SFRMIN
O
I
Debug acknowledge signal
TAP controller select signal
Note: The DBGREQ (DBGACK) pin is alternatively used as GPIO (GPIO or SPI1) pin; the function is selected
with the GPIO_PORT_MODE_H and GPIO_PORT_MODE_L registers. In this table the I/O type is listed
for the DBGREQ (DBGACK) function.
Preliminary Data Sheet A17989EE1V1DS00
20
µPD800261
Table 1-11: Trace Port Pin Functions
I/ONote
Pin Name
TRACEPKT7
Function
Trace packet bit 7
Alternate FunctionNote
O
O
O
O
O
O
O
O
O
O
O
O
I
LBU_A2, RXD_P12
LBU_A3, RXD_P13
LBU_A4, CRS_P1
LBU_A5, RX_ER_P1
LBU_A6, RX_DV_P1
LBU_A7, COL_P1
LBU_A8, RXD_P20
LBU_A9, RXD_P21
LBU_A11, RXD_P23
LBU_A12, CRS_P2
LBU_A13, RX_ER_P2
LBU_A10, RXD_P22
LBU_A1, RXD_P11
LBU_A0, RXD_P10
TRACEPKT6
TRACEPKT5
TRACEPKT4
TRACEPKT3
TRACEPKT2
TRACEPKT1
TRACEPKT0
PIPESTA2
Trace packet bit 6
Trace packet bit 5
Trace packet bit 4
Trace packet bit 3
Trace packet bit 2
Trace packet bit 1
Trace packet bit 0
CPU pipeline status, bit 2
CPU pipeline status, bit 1
CPU pipeline status, bit 0
Trace sync signal
PIPESTA1
PIPESTA0
TRACESYNC
ETMEXTIN1
ETMEXTOUT
External input to the ETM
Output signal from the ETM
O
Note: Trace port pins are alternatively used as local bus or MII diagnosis pins; the function is selected with the
GPIO_PORT_MODE_H and GPIO_PORT_MODE_L registers. In this table the I/O types are listed for
the trace port pin functions.
Table 1-12: Power Supply Pin Functions
Pin Name
VDD Core
Function
Power supply for core, 1.5 V
GND CORE
GND Core
VDD IO
Power supply for IO, 3.3 V
GND for IO
GND IO
PLL_AVDD
PLL_AGND
VDDQ (PECL)
GND (PECL)
Analog power supply for PLL, 1.5 V
Analog GND for PLL
Power supply for PECL buffers, 3.3 V
GND for PECL buffers
Preliminary Data Sheet A17989EE1V1DS00
21
µPD800261
Table 1-13: Alternative Functions of GPIO(31:0) Pins
FunctionNote
GPIO pin
0
1
2
-
3
-
-
-
-
-
-
after Reset
GPIO0
GPIO0
GPIO0
GPIO1
P1-DUPLEX-LED_N
P2-DUPLEX-LED_N
GPIO1
-
GPIO1
GPIO2
GPIO2
P1-SPEED-100LED_N (TX/FX) P1-SPEED-10LED_N
P2-SPEED-100LED_N (TX/FX) P2-SPEED-10LED_N
GPIO2
GPIO3
GPIO3
GPIO3
GPIO4
GPIO4
P1-LINK-LED_N
P2-LINK-LED_N
P1-RX-LED_N
P2-RX-LED_N
UART-TXD
-
GPIO4
GPIO5
GPIO5
-
GPIO5
GPIO6
GPIO6
P1-TX-LED_N
P1-ACTIVE-LED_N GPIO6
P2-ACTIVE-LED_N GPIO7
GPIO7
GPIO7
P2-TX-LED_N
GPIO8
GPIO8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GPIO8
GPIO9
GPIO9
UART-RXD
-
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
UART-DCD_N
UART-DSR_N
UART-CTS_N
Reserved
-
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO(30:24)
GPIO31
-
-
-
DBGACK
-
WD_WDOUT_N
SPI1_SSPCTLOE
SPI1_SSPOE
SPI1_SSPRXD
SPI1_SSPTXD
SPI1_SCLKOUT
SPI1_SFRMOUT
SPI1_SFRMIN
SPI1_SCLKIN
-
-
-
-
-
-
-
DBGACK
Reserved
GPIO(30:24) GPIO(30:24) Reserved
GPIO31 GPIO31 DBGREQ
-
-
Note: Alternative functions are software configurable using the GPIO_PORT_MODE_L/H registers.
Preliminary Data Sheet A17989EE1V1DS00
22
µPD800261
1.2 Pin Characteristics
Table 1-14: Pin Characteristics (1/2)
Drive capability
Internal pull
up/down
Pin Name
I/O
Input type
Output type
IOH
IOL
A23
I/ONote 1
I/ONote 1
I/ONote 1
I/ONote 1
I/ONote 1
SchmittNote 1
SchmittNote 1
SchmittNote 1
SchmittNote 1
SchmittNote 1
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
50 kΩ pull up
50 kΩ pull down
50 kΩ pull up
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
A22
A21
A20
50 kΩ pull down
50 kΩ pull up
A(19:17)
A(16:15)
I/ONote 1
SchmittNote 1
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
-
50 kΩ pull down
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
6 mA
9 mA
-
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
9 mA
6 mA
9 mA
-
A(14:0)
O
I/O
O
O
O
O
O
O
O
O
O
I
-
-
D(31:0)
Schmitt
50 kΩ pull up
WR_N
-
-
RD_N
-
-
CLK_SDRAM
CS_SDRAM_N
RAS_SDRAM_N
CAS_SDRAM_N
WE_SDRAM_N
CS_PER(3:0)_N
BE(3:0)_DQM(3:0)_N
RDY_PER_N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Schmitt
50 kΩ pull up
DTR_N
I/ONote 1
O
SchmittNote 1
-
3.3 V CMOS
3.3 V CMOS
50 kΩ pull up
9 mA
9 mA
9 mA
9 mA
OE_DRIVER_N
-
LBU_A(20:0)Note 2
LBU_D(15:0) Note 2
LBU_WR_N Note 2
LBU_RD_N Note 2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
6 mA
9 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
24 mA
6 mA
6 mA
9 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
6 mA
24 mA
6 mA
LBU_BE(1:0)_NNote 2
LBU_SEG_(1:0) Note 2
LBU_IRQ_(1:0)_N Note 2
LBU_RDY_N Note 2
LBU_CS_M_N Note 2
LBU_CS_R_N Note 2
GPIO(31:30) Note 2
GPIO(29:27) Note 2
GPIO(28:8) Note 2
GPIO(7:0) Note 2
CLKP_A
I/O
I
Schmitt
3.3 V CMOS
-
50 kΩ pull up
9 mA
-
9 mA
-
Osc. in
-
-
-
CLKP_B
O
O
-
-
Osc. out
3.3 V CMOS
6 mA
18 mA
6 mA
18 mA
TRACECLK
Preliminary Data Sheet A17989EE1V1DS00
23
µPD800261
Table 1-14: Pin Characteristics (2/2)
Drive capability
Internal pull
up/down
Pin Name
I/O
Input type
Output type
IOH
IOL
F_CLK
I
3.3 V CMOS
-
-
3.3 V CMOS
-
-
-
-
REF_CLK
RESET_N
P(2:1)TxN
P(2:1)TxP
O
-
6 mA
6 mA
I
Schmitt
Analog
Analog
50 kΩ pull up
-
-
-
-
-
-
I/O
I/O
Analog
Analog
-
-
P(2:1)TDxN Note 3
O
-
3.3 V CMOS
-
12 mA
12 mA
P(2:1)TDxP Note 3
P(2:1)RxN
P(2:1)RxP
P(2:1)RDxN
P(2:1)RDxP
P(2:1)SDxN
P(2:1)SDxP
EXTRES
TRST_N
TCK
O
-
3.3 V CMOS
-
12 mA
12 mA
I/O
Analog
Analog
PECL
PECL
PECL
PECL
Analog
Schmitt
Schmitt
Schmitt
Schmitt
-
Analog
-
-
-
I/O
Analog
-
-
-
I
-
-
-
-
I
-
-
-
-
I
-
-
-
-
I
-
-
-
-
I/O
Analog
-
-
-
I
-
-
-
-
I
I
-
50 kΩ pull up
50 kΩ pull up
50 kΩ pull up
-
-
-
TDI
-
-
-
TMS
I
-
-
-
TDO
O
I/O
I
3.3 V CMOS
3.3 V CMOS
-
6 mA
6 mA
-
6 mA
6 mA
-
SRST_N
TAP_SEL
Schmitt
Schmitt
50 kΩ pull up
50 kΩ pull up
Notes: 1. The address pins A(23:15) and the DTR_N pin are used as inputs only during the active reset phase.
2. These pins have alternative functions, to which the pin characteristics apply as well. Note that the I/O
type given in Table 1-14 applies to the pin. I/O types that apply to one of the shared functions of a
specific pin are found in Tables 1-1 to 1-12.
3. These pins require external circuitry in order to provide PECL compliant output levels.
Remark: Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-11 for possible
pin names first, before looking up pin characteristics in Table 1-14.
Preliminary Data Sheet A17989EE1V1DS00
24
µPD800261
1.3 Pin Status and Drive Characteristics
Table 1-15: Pin Status During Reset and Recommended Connections (1/2)
Internal pull
up/down
I/O during
reset
Level
External pull
Pin Name
I/O
during reset up/down required
I/ONote 1
I/ONote 1
I/ONote 1
I/ONote 1
I/ONote 1
50 kΩ pull up
50 kΩ pull down
50 kΩ pull up
INote 1
INote 1
INote 1
INote 1
INote 1
HNote 1
Note 1
A23
A22
A21
A20
LNote 1
Note 1
HNote 1
Note 1
LNote 1
Note 1
50 kΩ pull down
50 kΩ pull up
HNote 1
Note 1
A(19:17)
I/ONote 1
50 kΩ pull down
INote 1
LNote 1
Note 1
A(16:15)
A(14:0)
O
I/O
O
O
O
O
O
O
O
O
O
I
-
O
I
-
-
-
-
-
-
-
-
-
-
-
-
-
D(31:0)
50 kΩpull up
H
H
H
L
WR_N
-
O
O
O
O
O
O
O
O
O
I
RD_N
-
CLK_SDRAM
CS_SDRAM_N
RAS_SDRAM_N
CAS_SDRAM_N
WE_SDRAM_N
CS_PER(3:0)_N
BE(3:0)_DQM(3:0)_N
RDY_PER_N
-
-
H
H
H
H
H
H
H
-
-
-
-
-
50 kΩpull up
DTR_N
I/ONote 1
O
50 kΩpull up
INote 1
HNote 1
H
Note 1
-
OE_DRIVER_N
-
ETMEXTOUTNote 2
ETMEXTIN1Note 2
TRACEPKT(7:0)Note 2
PIPESTA(2:0)Note 2
GPIO(44:32)Note 2
GPIO(31:30)Note 2
GPIO(29:27)Note 2
GPIO(28:8)Note 2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
50 kΩpull up
50 kΩpull up
50 kΩpull up
50 kΩpull up
50 kΩpull up
50 kΩpull up
50 kΩpull up
50 kΩpull up
INote 7
H
H
H
H
H
H
H
H
-
-
-
-
-
-
-
-
I
INote 7
INote 7
I
I
I
I
GPIO(7:0)Note 2
CLKP_A
I/O
I
50 kΩpull up
I
I
H
-
-
-
-
-
-
-
-
CLKP_B
O
O
I
O
O
I
-
TRACECLK
F_CLK
L
-
-
REF_CLK
RESET_N
TRST_N
I/O
-
tri-stateNote 3
-
LNote 4
HNote 5
H
-
I
I
I
I
I
50 kΩpull up
-
I
I
I
I
I
-
Pull up
TCKNote 6
TDINote 6
TMSNote 6
50 kΩpull up
50 kΩpull up
50 kΩpull up
-
-
-
H
H
Preliminary Data Sheet A17989EE1V1DS00
25
µPD800261
Table 1-15: Pin Status During Reset and Recommended Connections (2/2)
Internal pull
up/down
I/O during
reset
Level
External pull
Pin Name
I/O
during reset up/down required
TDONote 6
SRST_N
TAP_SEL
O
I/O
I
-
O
O
I
L
L
-
-
-
50 kΩ pull up
50 kΩ pull up
H
Notes: 1. These pins are used as inputs only during the active reset phase. The levels during reset shown in
Table 1-15 refer to the default configuration without external pull-up/down resistors connected to
BOOT(3:0) and CONFIG(6:1)
2. These pins have alternative functions, to which the pin characteristics apply as well. Note that the I/O
type given in Table 1-14 applies to the pin. I/O types that apply to one of the shared functions of a
specific pin are found in Tables 1-1 to 1-12.
3. The reset behaviour of this pin is determined by the CONFIG1 signal.
4. RESET_N must be externally driven low in order to reset the device.
5. High level is generated from external pull up resistor and not by internal device circuitry.
6. The reset signal, that affects these signals, is TRST_N.
7. All trace interface pins are configured as inputs in the default configuration that is determined by the
internal pull-up/down resistors at the CONFIG(6:5) and CONFIG1 pins.
Remarks: 1. Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-11 for possible
pin names first, before looking up reset characteristics and recommended connections in
Table 1-15.
Remarks: 2. I/O and level during reset are given for the default configuration that is determined by the internal
pull-up/down resistors at the CONFIG(6:5) and CONFIG1 pins.
Preliminary Data Sheet A17989EE1V1DS00
26
µPD800261
Table 1-16: Alternative Functions of LBU Interface Pins (1/2)
LBU active
MII diagnosis mode
Trace interface active
CONFIG(6:5) = 10b
CONFIG2= 1b
Function 3 during reset
GPIO36
CONFIG(6:5) = xxb
CONFIG2= 0b
CONFIG(6:5) = 01b
CONFIG2= 1b
Function 1
LBU_A20
during reset
Function 2
GPIO36
during reset
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBU_A19
LBU_A18
LBU_A17
LBU_A16
LBU_A15
LBU_A14
LBU_A13
LBU_A12
LBU_A11
LBU_A10
LBU_A9
LBU_A8
LBU_A7
LBU_A6
LBU_A5
LBU_A4
LBU_A3
LBU_A2
LBU_A1
LBU_A0
LBU_D15
LBU_D14
LBU_D13
LBU_D12
LBU_D11
LBU_D10
LBU_D9
LBU_D8
LBU_D7
LBU_D6
LBU_D5
LBU_D4
LBU_D3
LBU_D2
LBU_D1
LBU_D0
GPIO35
I
GPIO35
GPIO34
I
GPIO34
GPIO33
I
GPIO33
GPIO32
I
GPIO32
COL_P2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
-
RX_DV_P2
RX_ER_P2
CRS_P2
-
PIPESTA0
PIPESTA1
RXD_P23
RXD_P22
RXD_P21
RXD_P20
COL_P1
PIPESTA2
TRACESYNC
TRACEPKT0
TRACEPKT1
TRACEPKT2
RX_DV_P1
RX_ER_P1
CRS_P1
TRACEPKT3
TRACEPKT4
TRACEPKT5
RXD_P13
RXD_P12
RXD_P11
RXD_P10
GPIO41
TRACEPKT6
TRACEPKT7
ETMEXTIN1
ETMEXTOUT
GPIO41
RES_PHY_N
SMI_MDIO
SMI_MDC
TX_ERR_P2
TX_EN_P2
TXD_P23
TXD_P22
TXD_P21
TXD_P20
TX_ERR_P1
TX_EN_P1
TXD_P13
TXD_P12
TXD_P11
TXD_P10
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Preliminary Data Sheet A17989EE1V1DS00
27
µPD800261
Table 1-16: Alternative Functions of LBU Interface Pins (2/2)
LBU active
CONFIG(6:5) = xxb
CONFIG2= 0b
Function 1 during reset
LBU_WR_N
MII diagnosis mode
Trace interface active
CONFIG(6:5) = 01b
CONFIG2= 1b
CONFIG(6:5) = 10b
CONFIG2= 1b
Function 2
TX_CLK_P1
during reset
Function 3
during reset
I
I
O
O
O
O
I
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
LBU_RD_N
TX_CLK_P2
RX_CLK_P2
RX_CLK_P1
GPIO38
LBU_BE1_N
LBU_BE0_N
LBU_SEG_1
LBU_SEG_0
LBU_IRQ_1_N
LBU_IRQ_0_N
LBU_RDY_N
LBU_CS_M_N
LBU_CS_R_N
I
I
I
GPIO38
GPIO37
GPIO44
GPIO43
GPIO42
GPIO40
GPIO39
I
GPIO37
I
O
O
O
I
GPIO44
I
GPIO43
I
GPIO42
I
GPIO40
I
I
GPIO39
I
Preliminary Data Sheet A17989EE1V1DS00
28
µPD800261
2. Electrical Specifications
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Symbol
VDD Core
Parameter
Power supply for core
Ratings
Unit
V
-0.5 to +2.0
-0.5 to +4.6
-0.5 to +2.0
-0.5 to +2.0
-0.5 to +4.6
-0.5 to +2.0
-0.5 to +2.0
-0.5 to +4.6
-0.5 to +4.6
Power supply for IO
VDD IO
V
Analog power supply for PLL
Digital power supply for PHYs
Analog central 3.3 V supply for PHYs
Analog central 1.5 V supply for PHYs
Analog Rx/Tx port power supply
PECL buffer power supply
Analog test supply
PLL_AVDD
DVVD
V
V
VDDACB
V
VDDAPLL
P(2:1)VDDARXTX
VDDQ (PECL)
VDD33ESD
V
V
V
V
3.3 V CMOS,
VI < VDD + 0.5 V
VI
Input voltage
-0.5 to+ 4.6
V
TJ
Junction temperature
Storage temperature
-40 to +120
-65 to +150
°C
°C
TSTG
Caution: Product quality may suffer if the absolute maximum rating is exceeded even momen-
tarily for any parameter. That is, the absolute maximum ratings are rated values at
which the product is on the verge of suffering physical damage, and therefore the
product must be used under conditions that ensure that the absolute maximum rat-
ings are not exceeded. The ratings and conditions indicated for DC characteristics
and AC characteristics represent the quality assurance range during normal opera-
tion.
Remark: 3.3 V must be applied to the I/O pins only after applying the power supply voltage.
Preliminary Data Sheet A17989EE1V1DS00
29
µPD800261
2.2 Operating Conditions
Table 2-2: Recommended Operating Conditions (1/2)
Test
Conditions
Parameter
Power supply for core
Symbol
MIN.
TYP.
MAX.
Unit
VDD Core
VDD IO
1.35
3.0
1.5
3.3
1.5
1.5
3.3
1.5
1.5
3.3
3.3
1.65
3.6
V
V
Power supply for IO
Analog power supply for PLL
Digital power supply for PHYs
Analog central 3.3 V supply for PHYs
Analog central 1.5 V supply for PHYs
Analog Rx/Tx port power supply
PECL buffer power supply
Analog test supply
PLL_AVDD
DVVD
1.35
1.35
3.0
1.65
1.65
3.6
V
V
VDDACB
V
VDDAPLL
P(2:1)VDDARXTX
VDDQ (PECL)
VDD33ESD
TA
1.35
1.35
3.0
1.65
1.65
3.6
V
V
V
3.0
3.6
V
Ambient temperature
-40
+85
°C
VDD IO-
0.1 V
IOH = 0 mA
V
VOH
Output voltage high
3.3 V CMOS
3.3 V CMOS
nominal
output
current
2.4
V
V
V
V
V
V
V
IOL = 0 mA
0.1
0.4
nominal
output
current
VOL
VIH
VIL
Output voltage low
Input voltage high
3.3 V CMOS
3.3 V PECL
3.3 CMOS
2
VDD IO
1.165
0.8
difference
to VDDQ
level
-0.880
0
difference
to VDDQ
level
Input voltage low
3.3 V PECL
-1.475
-1.880
VP
VN
Positive trigger voltage
1.2
0.6
2.4
1.8
V
V
Negative trigger volt-
age
Schmitt
input
VH
tRI
tFI
tRI
tFI
Hysteresis voltage
Input rise time
Input fall time
0.3
0
1.5
200
200
10
V
ns
ns
ms
ms
3.3 V CMOS
0
Input rise time
Input fall time
0
Schmitt
input
0
10
Preliminary Data Sheet A17989EE1V1DS00
30
µPD800261
Table 2-2: Recommended Operating Conditions (2/2)
Test
Conditions
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
CPU clock frequencyNote 1
Oscillator clock frequencyNote 2
PFC
150
25
MHz
MHz
25
- 50 ppm
25
+ 50 ppm
PLL_FC
25
- 50 ppm
25
+ 50 ppm
Reference clock frequencyNote 3
Reference clock stability
REF_Clk_FC
25
MHz
ns
REF_Clk_TCS
-0.2
0.2
MII transmit/receive clock
frequencyNote 4
PHY_Tx/
Rx_M_FC
2.5
25
MHz
1.5 V supply
IDD Core
IDD IO
450
235
535
175
435
85
mA
mA
10Base-TX
mode
Supply currentNote 5, 6
Supply currentNote 5, 6
Supply currentNote 5, 6
3.3 V supply
1.5 V supply
3.3 V supply
1.5 V supply
3.3 V supply
1.5 V supply
3.3 V supply
total
IDD Core
IDD IO
400
100
mA
100 Base-
TX mode
mA
IDD Core
IDD IO
mA
100 Base-
FX mode
mA
PDD Core
PDD IO
PDD
670
770
1440
800
570
1370
650
280
930
mW
mW
mW
mW
mW
mW
mW
mW
mW
Power
consumptionNote 5, 6
10Base-TX
mode
1.5 V supply
3.3 V supply
total
PDD Core
PDD IO
PDD
600
330
990
Power
consumptionNote 5, 6
100 Base-
TX mode
1.5 V supply
3.3 V supply
total
PDD Core
PDD IO
PDD
Power
consumptionNote 5, 6
100 Base-
FX mode
Notes: 1. The CPU clock is an internal signal. Different CPU core operation frequencies can be selected via
hardware settings during reset; possible settings are 50/100/150 MHz.
2. The oscillator clock is present at the CLKP_A and CLKP_B pins.
3. The reference clock is available at the REF_CLK pin, if the CONFIG1 pin was pulled low during the
active reset phase.
4. The MII transmit/receive clock needs only to be applied to the RX_CLK_P(1:0) and TX_CLK_P(1:0)
pins, if ERTEC 200 is operated in MII mode. It is not required, when the internal PHYs are used.
5. Typical values for supply currents and power consumption have been measured under the following
conditions:
•
Nominal operating voltages and temperature (VDD IO = 3.3 V, VDD Core = 1.5 V, TA = 25°C
•
•
•
Operation of ERTEC 200 on the EB200 evaluation board with 150 MHz core clock frequency
SDRAM test program and Ethernet traffic running; internal PHYs set to 100 Base-TX mode
No activity on LBU interface
6. Maximum values for supply currents and power consumption have been calculated for
VDD IO = 3.6 V and VDD Core = 1.65 V at TA = 85°C.
Preliminary Data Sheet A17989EE1V1DS00
31
µPD800261
2.3 Thermal Characteristics
Table 2-3: Thermal Characteristics of Package
Airflow (m/s)
Parameter
Symbol
Unit
0
0.2
1
2
Thermal resistance junction to ambientNote 1
30
27
23
21
K/W
K/W
Θ
ja
Thermal resistance junction to top center of
the package surfaceNote 1
Ψ
0.2
0.3
0.6
0.8
jt
Thermal resistance top center of the package
surface to ambientNote 1
Ψ
29.8
5.2
26.7
5.2
22.4
5.2
20.2
5.2
K/W
ta
Thermal resistance junction to caseNote 2
Maximum case temperature
K/W
°C
Θ
jc
Tcmax
105
Notes: 1. The parameters are valid, if no heat sink is used and at least a 4-layer PCB with massive ground
and power planes.
2. The parameter is valid, if a heat sink is used.
Preliminary Data Sheet A17989EE1V1DS00
32
µPD800261
2.4 AC Characteristics
2.4.1 Clock timing
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V
Table 2-4: Clock AC Characteristics
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
50/100/
150
Processor clock frequencyNote 1
PFC
PTC
MHz
20/10/
6.66
Processor clock periodNote 1
Oscillator clock frequency
Reference clock frequency
ns
25
- 50 ppm
25
+ 50 ppm
PLL_FC
25
25
MHz
MHz
25
- 50 ppm
25
+ 50 ppm
REF_PLL_FC
JTAGClk frequency
JTAGClk period
JTAG_FC
JTAG_TC
10
MHz
ns
100
2.5
40
MII transmit clock frequencyNote 2
MII transmit clock periodNote 2
PHY_Tx_M_FC
PHY_Tx_M_TC
25
400
65
MHz
ns
MII transmit clock input high timeNote 2,3 PHY_Tx_M_TCH
MII transmit clock input low timeNote 2,3 PHY_Tx_M_TCL
35
%
35
65
%
MII receive clock frequencyNote 2
MII receive clock periodNote 2
PHY_Rx_M_FC
PHY_Rx_M_TC
2.5
40
25
MHz
ns
400
65
MII receive clock input high timeNote 2,3 PHY_Rx_M_TCH
35
%
MII receive clock input low timeNote 2,3
CLK_SDRAM frequency
PHY_Rx_M_TCL
SDRAM_FC
35
65
50
%
MHz
ns
CLK_SDRAM period
SDRAM_TC
20
CLK_SDRAM clock stability
SDRAM_TCS
+/- 0.2
60
ns
CLK_SDRAM input high timeNote 2
CLK_SDRAM input low timeNote 2
SDRAM_TCH
SDRAM_TCL
40
40
%
%
60
Notes: 1. The actually permitted maximum clock frequency respectively minimum clock period is given by the
CONFIG(4:3) pin setting during reset and depends additionally on the accuracy of the oscillator
clock.
2. MII transmit/receive clock timings are only relevant, if ERTEC 200 is operated in MII mode.
3. High time and low time are specified in per cent of the nominal clock period.
Preliminary Data Sheet A17989EE1V1DS00
33
µPD800261
Figure 2-1: Clock Waveforms
2.0 V
1.5 V
0.8 V
TCH
TCL
TC
Preliminary Data Sheet A17989EE1V1DS00
34
µPD800261
2.4.2 I/O timing specifications
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V
Table 2-5: I/O Timing Specifications (1/2)
Input
Output
Signal
Unit
Clock
Notes
Setup time Hold time Valid delay Hold time
TIS min.
TIH min.
TOV max.
TOHmin.
D(31:0)
A(23:0)
10
0
12.5
11
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK_SDRAM
CLK_SDRAM
CLK_SDRAM
CLK_SDRAM
CLK_SDRAM
CLK_SDRAM
CLK_SDRAM
CLK_SDRAM
CLK_SDRAM
50 MHz
4
4
BE(3:0)_DQM_N(3:0)
CAS_SDRAM_N
RAS_SDRAM_N
WE_SDRAM_N
CS_SDRAM_N
WR_N
11
4
11
5
11
5
11
5
11
5
11
4
RD_N
11
4
LBU_D(15:0)
LBU_A(20:16)
LBU_A(15:0)
LBU_RDY_N
LBU_IRQ(1:0)_N
LBU_SEG(1:0)_N
LBU_CS_M_N
LBU_CS_R_N
LBU_WR_N
LBU_RD_N
LBU_BE(1:0)_N
TDI
10.4
10.4
10.4
10.4
10.4
10.4
10.4
10.4
10.4
10.4
10.4
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0
9.2
9.2
9.2
9.2
9.2
9.2
9.2
9.2
9.2
9.2
9.2
4
50 MHz
2
50 MHz
3
50 MHz
5
50 MHz
5
50 MHz
2
50 MHz
2
50 MHz
2
50 MHz
3
50 MHz
3
50 MHz
3
TCK
-
TMS
8
0
TCK
-
TDI
8
0
TCK
-
TMS
8
0
TCK
-
TDO
10
2
2
TCK
5
TRACESYNC
PIPESTA(2:0)
TRACEPKT
MDIO
Tc - 3
Tc - 3
Tc - 3
10
TRACECLK
TRACECLK
TRACECLK
MDC
1, 3
1, 3
1, 3
4
2
2
300
10
10
Notes: 1. If the trace interface is operated in half rate mode, Tc corresponds to the distance between a rising
and the subsequent falling edge of TRACECLK; if the trace interface is operated in full rate mode, Tc
corresponds to a full period of the trace clock TRACECLK.
2. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 25 pF
load.
3. Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 10 pF
load.
4. Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 50 pF
load.
5. Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 30 pF
load.
6. Minimum hold time is measured with 0 pF load and maximum valid Delay is measured with 30 pF
load.
Preliminary Data Sheet A17989EE1V1DS00
35
µPD800261
Table 2-5: I/O Timing Specifications (2/2)
Input Output
Setup time Hold time Valid delay Hold time
Signal
Unit
Clock
MDC
Notes
TIS min.
TIH min.
TOV max.
TOHmin.
RES_PHY_N
RXD(3:0)
RX_DV
10
10
ns
ns
ns
ns
ns
ns
ns
4
-
4
4
4
1
1
1
RX_CLK
RX_CLK
RX_CLK
TX_CLK
TX_CLK
TX_CLK
-
RX_ER
-
TXD(3:0)
TX_EN
14
14
14
2
2
2
4
4
4
TX_ER
Notes: 1. If the trace interface is operated in half rate mode, Tc corresponds to the distance between a rising
and the subsequent falling edge of TRACECLK; if the trace interface is operated in full rate mode, Tc
corresponds to a full period of the trace clock TRACECLK.
2. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 25 pF
load.
3. Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 41 pF
load.
4. Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 10 pF
load.
5. Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 50 pF
load.
6. Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 30 pF
load.
7. Minimum hold time is measured with 0 pF load and maximum valid Delay is measured with 30 pF
load.
Preliminary Data Sheet A17989EE1V1DS00
36
µPD800261
Figure 2-2: Input Setup and Hold Waveforms
Clock
Inputs
TIH min.
TIS min.
Valid
Figure 2-3: Output Delay Waveforms
Clock
TOV max.
TOV max.
TOH min.
TOH min.
Outputs
High (Drive)
Float (High-Z)
Low (Drive)
Valid
Valid
Preliminary Data Sheet A17989EE1V1DS00
37
µPD800261
2.4.3 LBU timing specifications
Remarks: 1. The polarity of the LBU_RDY_N signal can be configured using the CONFIG6 pin.
LBU_POL_RDY signal. LBU_RDY_N must be pulled to its "ready" level by an external
pull-down or the internal pull-up resistor.
CONFIG6 = 0b
CONFIG6 = 1b
LBU_RDY_N active low use external pull-down resistor
LBU_RDY_N active high use internal pull-up resistor (default
setting)
2. The CONFIG5 signal is used to select access control through separate read/write lines
or a common read/write line.
CONFIG5 = 0b
CONFIG5 = 1b
use separate read/write lines LBU_RD_N and LBU_WR_N (default
setting)
use common read/write line LBU_WR_N
In case of a common read/write line, LBU_WR_N must be high for a read access and
low for a write access. The unused LBU_RD_N input can then be left open because it is
pulled to inactive (high) level by an internal pull-up resistor.
3. ERTEC 200 responds to a read or write access by first driving LBU_RDY_N to "not
ready" level. Then LBU_RDY_N is driven to "ready" level for tRAP.. The length of the "not
ready" phase of LBU_RDY_N varies strongly on the internal states of ERTEC 200 and
the currently ongoing internal communication processes. Therefore no upper limit for
the length of the "not ready" period is specified.
4. ERTEC 200 has two LBU chip select inputs; one for access to the page configuration
registers (LBU_CS_R_N) and one to access to the ERTEC 200 memory addess space
(LBU_CS_M_N). Only one of these chip select signals may be active at a time and it is
not allowed to change the chip select during the complete access.
Preliminary Data Sheet A17989EE1V1DS00
38
µPD800261
(1) LBU Read from ERTEC 200 with Separate Read/Write line (LBU_RDY_N active low)
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V
Table 2-6: LBU Read from ERTEC 200 with Separate Read/Write line
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Chip select asserted to read pulse
asserted delay
tCSRS
-
0
-
ns
Address valid to read pulse asserted
setup time
tARS
tRRE
tRDE
-
-
-
0
5
5
-
ns
ns
ns
Read pulse asserted to ready enabled
delay
12
12
Read pulse asserted to data enable
delay
tRAP
tRTD
Ready active pulse width
-
-
17
-
23
5
ns
ns
Ready asserted to data valid delay
Read pulse deasserted to chip select
deasserted delay
tRCSH
tRAH
tRDH
tRR
-
-
0
0
-
-
ns
ns
Address valid to read pulse deasserted
hold time
Data valid/enabled to read pulse deas-
serted hold time
-
-
0
12
-
ns
ns
Read recovery time
25
Figure 2-4: LBU Read from ERTEC 200 with Separate Read/Write line
LBU_CS_R_N/
LBU_CS_M_N
tRCSH
tCSRS
LBU_RD_N
tRR
tARS
LBU_A(20:0)/
LBU_SEG(1:0)/
LBU_BE(1:0)_N
tRAH
tRRE
tRAP
LBU_RDY_N
LBU_D(15:0)
tRDH
tRDE
tRTD
Preliminary Data Sheet A17989EE1V1DS00
39
µPD800261
(2) LBU Write to ERTEC 200 with separate Read/Write line (LBU_RDY_N active low)
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V
Table 2-7: LBU Write to ERTEC 200 with Separate Read/Write line
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Chip select asserted to write pulse
asserted delay
tCSWS
-
0
-
ns
Address valid to write pulse asserted
setup time
tAWS
tWRE
-
-
0
5
-
ns
ns
Write pulse asserted to ready enabled
delay
12
tWDV
tRAP
Write pulse asserted to data valid delay
Ready active pulse width
-
-
-
40
23
ns
ns
17
Write pulse deasserted to chip select
deasserted delay
tWCSH
tWAH
tRTW
-
-
-
0
0
0
-
-
-
ns
ns
ns
Address hold time after write strobe
deasserted
Ready asserted to write pulse deas-
serted delay
Data hold time after write pulse deas-
serted
tWDH
tWR
-
-
0
-
-
ns
ns
Write recovery time
25
Figure 2-5: LBU Write to ERTEC 200 with Separate Read/Write line
LBU_CS_R_N/
LBU_CD_M_N
tCSWS
tWCSH
LBU_WR_N
tWR
tAWS
LBU_A(20:0)/
LBU_SEG(1:0)
LBU_BE(1:0)_N
tRTW
tWAH
tWRE
LBU_RDY_N
LBU_D(15:0)
tRAP
tWDH
tWDV
Preliminary Data Sheet A17989EE1V1DS00
40
µPD800261
(3) LBU Read from ERTEC 200 with Common Read/Write line (LBU_RDY_N active low)
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V
Table 2-8: LBU Read from ERTEC 200 with Common Read/Write line
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Write signal deasserted to chip select
asserted setup time
tWCS
-
2
-
ns
Address valid to chip select asserted
setup time
tACS
tCRE
tCDE
-
-
-
0
5
5
-
ns
ns
ns
Chip select asserted to ready enabled
delay
12
12
Chip select asserted to data enable
delay
tRAP
tRTD
Ready active pulse width
-
-
17
-
23
5
ns
ns
Ready asserted to data valid delay
Write signal inactive to chip select deas-
serted hold time
tCWH
tCAH
tCDH
tRR
-
-
0
0
-
-
ns
ns
Address valid to chip select deasserted
hold time
Data valid/enabled to chip select deas-
serted hold time
-
-
0
12
-
ns
ns
Read recovery time
25
Figure 2-6: LBU Read from ERTEC 200 with Common Read/Write line
LBU_CS_R_N/
LBU_CS_M_N
tRR
tWCS
LBU_WR_N
tCWH
tACS
LBU_A(20:0)/
LBU_SEG(1:0)/
LBU_BE(1:0)_N
tCRE
tCAH
tRAP
LBU_RDY_N
LBU_D(15:0)
tCDH
tCDE
tRTD
Preliminary Data Sheet A17989EE1V1DS00
41
µPD800261
(4) LBU Write to ERTEC 200 with Common Read/Write line (LBU_RDY_N active low)
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V
Table 2-9: LBU Write to ERTEC 200 with Common Read/Write line
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Write signal asserted to chip select
setup time
tWCS
-
2
-
ns
Address valid to chip select asserted
setup time
tACS
tCRE
-
-
0
5
-
ns
ns
Chip select asserted to ready enabled
delay
12
tCDV
tRAP
Chip select asserted to data valid delay
Ready active pulse width
-
-
-
40
23
ns
ns
17
Write signal deasserted to chip select
deasserted hold time
tCWH
tCAH
tRTC
-
-
-
0
0
0
-
-
-
ns
ns
ns
Address hold time after chip select deas-
serted
Ready asserted to chip select deas-
serted delay
Data valid/enabled to chip select deas-
serted hold time
tCDH
tWR
-
-
0
-
-
ns
ns
Write recovery time
25
Figure 2-7: LBU Write to ERTEC 200 with Common Read/Write line
LBU_CS_R_N/
LBU_CS_M_N
tWR
tWCS
LBU_WR_N
tCWH
tACS
LBU_A(20:0)/
LBU_SEG(1:0)/
LBU_BE(1:0)_N
tRTC
tCRE
tCAH
LBU_RDY_N
LBU_D(15:0)
tCDH
tCDV
tRAP
Preliminary Data Sheet A17989EE1V1DS00
42
µPD800261
2.4.4 Power-up sequence
Figure 2-8: Power-Up Sequence Timing Diagram
VDD
RESET_N
min. 35 µs
CLKP_A
Unstable
min. 2 µs
Preliminary Data Sheet A17989EE1V1DS00
43
µPD800261
2.4.5 Reset timing
Figure 2-9: Reset Timing Diagram
CLKP_A
(25 MHz)
~16384 TCLKP_A
~16 TCLK_50
CLK_50
(internal clock)
CLK_100
(internal clock for IRT)
CLK_ARM
(internal clock for CPU)
RESET_N
XRES_ERTEC/
XRES_CNTRL
(internal signal)
Preliminary Data Sheet A17989EE1V1DS00
44
µPD800261
3. Package Drawing
Figure 3-1: Package Drawing
304-PIN PLASTIC FBGA (19x19)
ZE
A
D
w
S
A
ZD
22
21
20
19
18
17
16
15
14
13
12
11
10
9
B
E
8
7
5
3
6
4
2
1
AA W U R N L J G E C A
AB Y V T P M K H F D B
w
S B
INDEX MARK
A
A2
A1
y1
S
(UNIT:mm)
ITEM DIMENSIONS
S
D
E
19.00 0.10
19.00 0.10
0.20
y
w
e
S
e
0.80
A
1.48 0.10
0.35 0.06
1.13
M
b
x
S A B
A1
A2
0.05
0.50
b
0.10
x
0.08
0.10
0.20
1.10
y
y1
ZD
ZE
1.10
P304F1-80-HN2
Preliminary Data Sheet A17989EE1V1DS00
45
µPD800261
4. Recommended Soldering Conditions
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor
Device:
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended please consult NEC.
(a) for µPD800261F1-523-HN2 (non-lead free device)
Table 4-1: Soldering Conditions for Non-lead-free Device
Symbol of Recommended Soldering
Soldering Method
Soldering Condition
Condition
Package peak temperature: 235°C,
Time: 30 seconds max. (210°C min.),
Number of times: 3 max.,
Infrared reflow
IR35-107-3
Number of days: 7 Note
Note: The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been
opened.
After that, prebaking is necessary at 125 °C for 10 to 72 hours.
(b) for µPD800261F1-523-HN2-A (lead free device)
Table 4-2: Soldering Conditions for Lead-free Device
Symbol of Recommended Soldering
Soldering Method
Soldering Condition
Condition
Package peak temperature: 260°C,
Time: 60 seconds max. (220°C min.),
Number of times: 3 max.,
Infrared reflow
IR60-107-3
Number of days: 7 Note
Note: The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been
opened.
After that, prebaking is necessary at 125 °C for 10 to 72 hours.
Preliminary Data Sheet A17989EE1V1DS00
46
µPD800261
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ꢃ
ꢄ
0OWERꢃON DOES NOT NECESSARILY DEFINE THE INITIAL STATUS OF A -/3 DEVICEꢎ )MMEDIATELY AFTER THE POWER
SOURCE IS TURNED /.ꢍ DEVICES WITH RESET FUNCTIONS HAVE NOT YET BEEN INITIALIZEDꢎ (ENCEꢍ POWERꢃON DOES
NOT GUARANTEE OUTPUT PIN LEVELSꢍ )ꢉ/ SETTINGS OR CONTENTS OF REGISTERSꢎ ! DEVICE IS NOT INITIALIZED UNTIL THE
RESET SIGNAL IS RECEIVEDꢎ ! RESET OPERATION MUST BE EXECUTED IMMEDIATELY AFTER POWERꢃON FOR DEVICES
WITH RESET FUNCTIONSꢎ
).054 /& 3)'.!, $52).' 0/7%2 /&& 34!4%
$O NOT INPUT SIGNALS OR AN )ꢉ/ PULLꢃUP POWER SUPPLY WHILE THE DEVICE IS NOT POWEREDꢎ 4HE CURRENT
INJECTION THAT RESULTS FROM INPUT OF SUCH A SIGNAL OR )ꢉ/ PULLꢃUP POWER SUPPLY MAY CAUSE MALFUNCTION AND
THE ABNORMAL CURRENT THAT PASSES IN THE DEVICE AT THIS TIME MAY CAUSE DEGRADATION OF INTERNAL ELEMENTSꢎ
)NPUT OF SIGNALS DURING THE POWER OFF STATE MUST BE JUDGED SEPARATELY FOR EACH DEVICE AND ACCORDING TO
RELATED SPECIFICATIONS GOVERNING THE DEVICEꢎ
All other product, brand, or trade names used in this publication are the trademarks
or registered trademarks of their respective trademark owners.
Product specifications are subject to change without notice. To ensure that you have the latest
product data, please contact your local NEC Electronics sales office.
Preliminary Data Sheet A17989EE1V1DS00
47
µPD800261
v
4HE INFORMATION IN THIS DOCUMENT IS CURRENT AS OF -AYꢅ ꢁꢆꢆꢇꢈ 4HE INFORMATION IS SUBJECT TO CHANGE
WITHOUT NOTICEꢈ &OR ACTUAL DESIGNꢉINꢅ REFER TO THE LATEST PUBLICATIONS OF .%# %LECTRONICS DATA SHEETS OR
DATA BOOKSꢅ ETCꢈꢅ FOR THE MOST UPꢉTOꢉDATE SPECIFICATIONS OF .%# %LECTRONICS PRODUCTSꢈ .OT ALL
PRODUCTS ANDꢊOR TYPES ARE AVAILABLE IN EVERY COUNTRYꢈ 0LEASE CHECK WITH AN .%# %LECTRONICS SALES
REPRESENTATIVE FOR AVAILABILITY AND ADDITIONAL INFORMATIONꢈ
.O PART OF THIS DOCUMENT MAY BE COPIED OR REPRODUCED IN ANY FORM OR BY ANY MEANS WITHOUT THE PRIOR
WRITTEN CONSENT OF .%# %LECTRONICSꢎ .%# %LECTRONICS ASSUMES NO RESPONSIBILITY FOR ANY ERRORS THAT MAY
APPEAR IN THIS DOCUMENTꢎ
v
v .%# %LECTRONICS DOES NOT ASSUME ANY LIABILITY FOR INFRINGEMENT OF PATENTSꢍ COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY
RIGHTS OF THIRD PARTIES BY OR ARISING FROM THE USE OF .%# %LECTRONICS PRODUCTS LISTED IN THIS DOCUMENT OR ANY
OTHER LIABILITY ARISING FROM THE USE OF SUCH PRODUCTSꢎ .O LICENSEꢍ EXPRESSꢍ IMPLIED OR OTHERWISEꢍ IS GRANTED UNDER
ANY PATENTSꢍ COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS OF .%# %LECTRONICS OR OTHERSꢎ
$ESCRIPTIONS OF CIRCUITSꢍ SOFTWARE AND OTHER RELATED INFORMATION IN THIS DOCUMENT ARE PROVIDED FOR ILLUSTRATIVE
PURPOSES IN SEMICONDUCTOR PRODUCT OPERATION AND APPLICATION EXAMPLESꢎ 4HE INCORPORATION OF THESE
CIRCUITSꢍ SOFTWARE AND INFORMATION IN THE DESIGN OF A CUSTOMERgS EQUIPMENT SHALL BE DONE UNDER THE FULL
RESPONSIBILITY OF THE CUSTOMERꢎ .%# %LECTRONICS ASSUMES NO RESPONSIBILITY FOR ANY LOSSES INCURRED BY
CUSTOMERS OR THIRD PARTIES ARISING FROM THE USE OF THESE CIRCUITSꢍ SOFTWARE AND INFORMATIONꢎ
7HILE .%# %LECTRONICS ENDEAVORS TO ENHANCE THE QUALITYꢍ RELIABILITY AND SAFETY OF .%# %LECTRONICS PRODUCTSꢍ
CUSTOMERS AGREE AND ACKNOWLEDGE THAT THE POSSIBILITY OF DEFECTS THEREOF CANNOT BE ELIMINATED ENTIRELYꢎ 4O
MINIMIZE RISKS OF DAMAGE TO PROPERTY OR INJURY ꢄINCLUDING DEATHꢆ TO PERSONS ARISING FROM DEFECTS IN .%#
%LECTRONICS PRODUCTSꢍ CUSTOMERS MUST INCORPORATE SUFFICIENT SAFETY MEASURES IN THEIR DESIGNꢍ SUCH AS
REDUNDANCYꢍ FIREꢃCONTAINMENT AND ANTIꢃFAILURE FEATURESꢎ
v
v
v
.%# %LECTRONICS PRODUCTS ARE CLASSIFIED INTO THE FOLLOWING THREE QUALITY GRADESꢐ ꢑ3TANDARDꢑꢍ ꢑ3PECIALꢑ AND
ꢑ3PECIFICꢑꢎ
4HE ꢑ3PECIFICꢑ QUALITY GRADE APPLIES ONLY TO .%# %LECTRONICS PRODUCTS DEVELOPED BASED ON
A
CUSTOMERꢃDESIGNATED ꢑQUALITY ASSURANCE PROGRAMꢑ FOR A SPECIFIC APPLICATIONꢎ 4HE RECOMMENDED APPLICATIONS OF
AN .%# %LECTRONICS PRODUCT DEPEND ON ITS QUALITY GRADEꢍ AS INDICATED BELOWꢎ #USTOMERS MUST CHECK THE QUALITY
GRADE OF EACH .%# %LECTRONICS PRODUCT BEFORE USING IT IN A PARTICULAR APPLICATIONꢎ
ꢑ3TANDARDꢑꢐ #OMPUTERSꢍ OFFICE EQUIPMENTꢍ COMMUNICATIONS EQUIPMENTꢍ TEST AND MEASUREMENT EQUIPMENTꢍ AUDIO
AND VISUAL EQUIPMENTꢍ HOME ELECTRONIC APPLIANCESꢍ MACHINE TOOLSꢍ PERSONAL ELECTRONIC EQUIPMENT
AND INDUSTRIAL ROBOTSꢎ
ꢑ3PECIALꢑꢐ 4RANSPORTATION EQUIPMENT ꢄAUTOMOBILESꢍ TRAINSꢍ SHIPSꢍ ETCꢎꢆꢍ TRAFFIC CONTROL SYSTEMSꢍ ANTIꢃDISASTER
SYSTEMSꢍ ANTIꢃCRIME SYSTEMSꢍ SAFETY EQUIPMENT AND MEDICAL EQUIPMENT ꢄNOT SPECIFICALLY DESIGNED
FOR LIFE SUPPORTꢆꢎ
ꢑ3PECIFICꢑꢐ !IRCRAFTꢍ AEROSPACE EQUIPMENTꢍ SUBMERSIBLE REPEATERSꢍ NUCLEAR REACTOR CONTROL SYSTEMSꢍ LIFE
SUPPORT SYSTEMS AND MEDICAL EQUIPMENT FOR LIFE SUPPORTꢍ ETCꢎ
4HE QUALITY GRADE OF .%# %LECTRONICS PRODUCTS IS ꢑ3TANDARDꢑ UNLESS OTHERWISE EXPRESSLY SPECIFIED IN .%#
%LECTRONICS DATA SHEETS OR DATA BOOKSꢍ ETCꢎ )F CUSTOMERS WISH TO USE .%# %LECTRONICS PRODUCTS IN APPLICATIONS
NOT INTENDED BY .%# %LECTRONICSꢍ THEY MUST CONTACT AN .%# %LECTRONICS SALES REPRESENTATIVE IN ADVANCE TO
DETERMINE .%# %LECTRONICSg WILLINGNESS TO SUPPORT A GIVEN APPLICATIONꢎ
ꢄ.OTEꢆ
ꢄꢊꢆ ꢑ.%# %LECTRONICSꢑ AS USED IN THIS STATEMENT MEANS .%# %LECTRONICS #ORPORATION AND ALSO INCLUDES ITS
MAJORITYꢃOWNED SUBSIDIARIESꢎ
ꢄꢌꢆ ꢑ.%# %LECTRONICS PRODUCTSꢑ MEANS ANY PRODUCT DEVELOPED OR MANUFACTURED BY OR FOR .%# %LECTRONICS ꢄAS
DEFINED ABOVEꢆꢎ
-ꢅ% ꢈꢌꢎꢊꢊꢃꢊ
Preliminary Data Sheet A17989EE1V1DS00
48
µPD800261
For further information,
please contact:
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111
http://www.necel.com/
[Asia & Oceania]
[America]
[Europe]
NEC Electronics (China) Co., Ltd
NEC Electronics America, Inc.
2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Arcadiastrasse 10
40472 Düsseldorf, Germany
Tel: 0211-65030
7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian
District, Beijing 100083, P.R.China
Tel: 010-8235-1155
http://www.cn.necel.com/
800-366-9782
http://www.eu.necel.com/
http://www.am.necel.com/
NEC Electronics Shanghai Ltd.
Room 2511-2512, Bank of China Tower,
200 Yincheng Road Central,
Pudong New Area, Shanghai P.R. China P.C:200120
Tel: 021-5888-5400
Hanover Office
Podbielskistrasse 166 B
30177 Hannover
Tel: 0 511 33 40 2-0
Munich Office
Werner-Eckert-Strasse 9
http://www.cn.necel.com/
81829 München
Tel: 0 89 92 10 03-0
NEC Electronics Hong Kong Ltd.
Unit 1601-1613, 16/F., Tower 2, Grand Century Place,
193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: 2886-9318
Stuttgart Office
Industriestrasse 3
70565 Stuttgart
http://www.hk.necel.com/
Tel: 0 711 99 01 0-0
NEC Electronics Taiwan Ltd.
7F, No. 363 Fu Shing North Road
Taipei, Taiwan, R. O. C.
Tel: 02-8175-9600
http://www.tw.necel.com/
United Kingdom Branch
Cygnus House, Sunrise Parkway
Linford Wood, Milton Keynes
MK14 6NP, U.K.
Tel: 01908-691-133
NEC Electronics Singapore Pte. Ltd.
238A Thomson Road,
#12-08 Novena Square,
Singapore 307684
Tel: 6253-8311
http://www.sg.necel.com/
Succursale Française
9, rue Paul Dautier, B.P. 52
78142 Velizy-Villacoublay Cédex
France
Tel: 01-3067-5800
Sucursal en España
Juan Esplandiu, 15
28007 Madrid, Spain
Tel: 091-504-2787
NEC Electronics Korea Ltd.
11F., Samik Lavied’or Bldg., 720-2,
Yeoksam-Dong, Kangnam-Ku,
Seoul, 135-080, Korea
Tyskland Filial
Täby Centrum
Tel: 02-558-3737
Entrance S (7th floor)
18322 Täby, Sweden
Tel: 08 638 72 00
http://www.kr.necel.com/
Filiale Italiana
Via Fabio Filzi, 25/A
20124 Milano, Italy
Tel: 02-667541
Branch The Netherlands
Steijgerweg 6
5616 HS Eindhoven
The Netherlands
Tel: 040 265 40 10
G07.1
Preliminary Data Sheet A17989EE1V1DS00
49
相关型号：
UPD800261F1-816-HN2-A
32-BIT, 150MHz, RISC PROCESSOR, PBGA304, 19 X 19 MM, PLASTIC, LEAD FREE, FBGA-304
RENESAS
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