X1286V14ZT1 [RENESAS]
1 TIMER(S), REAL TIME CLOCK, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14;
| 型号： | X1286V14ZT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14 时钟 光电二极管 外围集成电路 |
| 文件： | 总25页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X1286
®
2-Wire™ RTC, 256k (32k x 8)
Data Sheet
April 14, 2006
FN8101.1
• Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
Intersil Real Time Clock/Calendar/CPU
Supervisor with EEPROM
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
FEATURES
• Real Time Clock/Calendar
—8 Ld EIAJ SOIC and 14 Ld TSSOP
• Repetitive Alarms
—Tracks time in Hours, Minutes, Seconds and
Hundredths of a Second
• Temperature Compensation
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
APPLICATIONS
• Utility Meters
• HVAC Equipment
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 32K x 8 Bits of EEPROM
• POS Equipment
• Test Meters/Fixtures
—128-Byte Page Write Mode
• Office Automation (Copiers, Fax)
• Home Appliances
—8 modes of Block Lock™ Protection
—Single Byte Write Capability
• High Reliability
• Computer Products
• Other Industrial/Medical/Automotive
—Data Retention: 100 years
—Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
—400kHz data transfer rate
BLOCK DIAGRAM
OSC
Compensation
X1
Timer
Calendar
Logic
Battery
Switch
Time
VCC
Frequency
Divider
1Hz
Oscillator
32.768kHz
Keeping
Registers
VBACK
Circuitry
X2
Select
(SRAM)
PHZ/IRQ
Status
Control/
Control
Decode
Logic
Compare
Serial
Registers
SCL
SDA
Registers
Alarm
Interface
Decoder
(EEPROM)
(SRAM)
Alarm Regs
(EEPROM)
8
256K
EEPROM
ARRAY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X1286
PIN DESCRIPTIONS
8 LD EIAJ SOIC
14 LD TSSOP
8
7
6
5
X1
X2
1
2
VCC
VCC
VBACK
NC
X1
1
2
14
13
12
11
10
9
VBACK
SCL
X2
PHZ/IRQ
VSS
NC
NC
3
4
3
4
5
6
NC
SDA
NC
NC
PHZ/IRQ
SCL
SDA
VSS
7
8
Ordering Information
PART NUMBER
PART MARKING
VCC RANGE (V)
TEMP. RANGE (°C)
0 to 70
PACKAGE
PKG. DWG. #
X1286A8*
X1286A
2.7 to 5.5
8 Ld EIAJ SOIC
X1286A8I*
X1286A I
-40 to 85
8 Ld EIAJ SOIC
X1286V14*
X1286 V
0 to 70
14 Ld TSSOP (4.4mm)
MDP0044
MDP0044
X1286V14Z* (Note)
X1286 VZ
0 to 70
14 Ld TSSOP (4.4mm)
(Pb-free)
X1286V14I*
X1286 VI
-40 to 85
-40 to 85
14 Ld TSSOP (4.4mm)
MDP0044
MDP0044
X1286V14IZ* (Note)
X1286 VIZ
14 Ld TSSOP (4.4mm)
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8101.1
2
April 14, 2006
X1286
PIN ASSIGNMENTS
Pin Number
EIAJ SOIC TSSOP
Symbol
Brief Description
1
2
3
1
2
6
X1
X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1286 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation
circuitry is included to form a complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit. Plenty of ground plane around
the device and short traces to X1 are highly recommended. See Application section
for more recommendations.
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz
quartz crystal is used with the X1286 to supply a timebase for the real time clock.
The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation
circuitry is included to form a complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit. Plenty of ground plane around
the device and short traces to X2 are highly recommended. See Application section
for more recommendations.
X2
PHZ/IRQ Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an
output from the internal oscillator or an interrupt signal output. It is a CMOS
output.
When used as frequency output, this signal has a frequency of 32.768kHz,
100Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm
has occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address
0011h of the Clock Control Memory map. See “Programmable Frequency Output
Bits—FO1, FO0” on page 13.
4
5
7
8
VSS
SDA
VSS.
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire ORed with other open
drain or open collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry
controls the fall time of the output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire interface speed.
6
7
9
SCL
Serial Clock (SCL). The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not gated).
13
VBACK
VBACK. This input provides a backup supply voltage to the device. VBACK
supplies power to the device in the event the VCC supply fails. This pin can be
connected to a battery, a Supercap or tied to ground if not used.
8
14
VCC
VCC.
FN8101.1
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April 14, 2006
X1286
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature......................... -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may
affect device reliability.
Voltage on V , V
and PHZ/IRQ
CC BACK
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V or V
(whichever is higher)
BACK
CC
DC Output Current ..............................................5 mA
Lead Temperature (Soldering, 10s)................... 300°C
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
VCC
VBACK
VCB
Parameter
Conditions
Min
2.7
1.8
Typ
Max
5.5
5.5
Unit
V
V
V
V
Notes
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
VBACK -0.2
VBACK
VBACK -0.1
VBACK +0.2
VBC
OPERATING CHARACTERISTICS
Symbol
ICC1
Parameter
Read Active Supply Cur-
Conditions
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VBACK = 1.8V
VBACK = 3.3V
Min
Typ
Max
400
800
2.5
3.0
10
Unit
µA
µA
mA
mA
µA
µA
µA
µA
Notes
1, 5, 7, 14
rent
ICC2
ICC3
Program Supply Current
(nonvolatile)
2, 5, 7, 14
Main Timekeeping
Current
3, 7, 8, 14, 15
20
IBACK
Timekeeping Current
1.25
1.5
3, 6, 9, 14, 15
“See Perfor-
mance Data”
ILI
ILO
VIL
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
10
10
13
-0.5
VCC x 0.2 or
VBACK x 0.2
VIH
Input HIGH Voltage
VCC x 0.7 or
VCC + 0.5 or
V
V
V
13
13
11
VBACK x 0.7
V
BACK + 0.5
VHYS
VOL1
Schmitt Trigger Input
Hysteresis
VCC related level .05 x VCC or
.05 x VBACK
Output LOW Voltage for
VCC = 2.7V
VCC = 5.5V
VCC = 2.7V
VCC = 5.5V
VCC = 2.7V
VCC = 5.5V
0.4
0.4
VCC x 0.3
VCC x 0.3
SDA
VOL2
VOH2
Output LOW Voltage for
PHZ/IRQ
V
V
11
12
Output HIGH Voltage for
PHZ/IRQ
VCC x 0.7
VCC x 0.7
FN8101.1
April 14, 2006
4
X1286
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10)VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC
(11)IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12)
IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15)Typical values are for TA = 25°C
Capacitance T = 25°C, f = 1.0 MHz, V = 5V
A
CC
Symbol
Parameter
Max.
10
Units
pF
Test Conditions
VOUT = 0V
(1)
COUT
Output Capacitance (SDA, PHZ/IRQ)
Input Capacitance (SCL)
(1)
CIN
10
pF
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
10ns
Input Rise and Fall Times
Input and Output Timing
Levels
VCC x 0.5
Output Load
Standard Output Load
Figure 1. Standard Output Load for testing the device with V = 5.0V
CC
Equivalent AC Output Load Circuit for V = 5V
CC
5.0V
5.0V
For VOL= 0.4V
and IOL = 3 mA
1316Ω
806Ω
1533Ω
PHZ/IRQ
SDA
100pF
100pF
FN8101.1
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April 14, 2006
X1286
AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
A
Symbol
Parameter
Min.
Max. Units
fSCL
tIN
SCL Clock Frequency
400
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
50(1)
tAA
0.9
tBUF
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
Data In Hold Time
0
0.6
Stop Condition Setup Time
Data Output Hold Time
50
tR
SDA and SCL Rise Time
20 +.1Cb(1)(2)
20 +.1Cb(1)(2)
300
300
400
tF
SDA and SCL Fall Time
Cb
Capacitive load for each bus line
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA tDH
tBUF
SDA OUT
FN8101.1
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April 14, 2006
X1286
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
tWC
Stop
Condition
Start
Condition
Power-up Timing
(2)
Symbol
Parameter
Min.
Typ.
Max.
Units
ms
(1)
tPUR
Time from Power-up to Read
1
5
(1)
tPUW
Time from Power-uppower-up to Write
ms
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested.
V
CC slew rate should be between 0.2mV/µsec and 50mV/µsec.
(2) Typical values are for TA = 25°C and VCC = 5.0V
Nonvolatile Write Cycle Timing
(1)
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
Units
(1)
tWC
5
10
ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8101.1
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April 14, 2006
X1286
DESCRIPTION
The X1286 device is a Real Time Clock with clock/calendar,
two polled alarms with integrated 32kx8 EEPROM, oscillator
compensation, and battery backup switch.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving board
area and component cost.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds and 1/100 of a
second. The Calendar has separate registers for Date,
Month, Year and Day-of-week. The calendar is correct
through 2099, with automatic leap year correction.
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speed.
The powerful Dual Alarms can be set to any
Clock/Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
V
BACK
This input provides a backup supply voltage to the
device. V
supplies power to the device in the
BACK
CC
event the V supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 100 Hz, or 32,768 Hz.
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
The device offers a backup power input pin. This
interrupt signal output. It is a CMOS output.
V
pin allows the device to be backed up by
BACK
When used as frequency output, this signal has a fre-
quency of 32.768kHz, 100Hz, 1Hz or inactive.
battery or SuperCap. The entire X1286 device is fully
operational from 2.7 to 5.5 volts and the
clock/calendar portion of the X1286 device remains
fully operational down to 1.8 volts (Standby Mode).
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
The X1286 device provides 256K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. See “Programmable Frequency Output
Bits—FO1, FO0” on page 13.
PIN DESCRIPTIONS
X1, X2
X1286
8-pin EIAJ SOIC
14- pin TSSOP
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1286 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
V
V
NC
NC
NC
X1
X2
NC
NC
1
2
V
V
CC
X1
X2
PHZ/IRQ
8
7
6
5
1
2
14
13
12
11
10
9
CC
BACK
BACK
3
4
5
6
3
4
SCL
SDA
V
SS
NC
PHZ/IRQ
SCL
SDA
V
SS
7
8
FN8101.1
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April 14, 2006
X1286
Figure 2. Recommended Crystal connection
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the SSEC register reset to “0” at the
next sub-second update after the stop bit is written.
The 1Hz frequency output from the PHZ/IRQ pin will
be reset to restart after the stop bit is written. The RTC
continues to update the time while an RTC register
write is in progress and the RTC continues to run dur-
ing any nonvolatile write sequences. A single byte may
be written to the RTC without affecting the other bytes.
X1
X2
POWER CONTROL OPERATION
The power control circuit accepts a V and a V
CC
BACK
input. The power control circuit powers the clock from
V
when V < V
- 0.2V. It will switch back to
BACK
CC
BACK
power the device from V when V exceeds V .
BACK
CC
CC
Figure 3. Power Control
Accuracy of the Real Time Clock
V
CC
Voltage
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC performance
will also be dependent upon temperature. The frequency
deviation of the crystal is a function of the turnover
temperature of the crystal from the crystal’s nominal
frequency. For example, a >20ppm frequency deviation
translates into an accuracy of >1 minute per month.
these parameters are available from the crystal
manufacturer. Intersil’s RTC family provides on-chip
crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116 ppm
to -37 ppm when using a 12.5 pF load crystal. For more
detail information see the Application section.
On
V
BACK
In
Off
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate inter-
nal representation of the 1/100 of a second, second,
minute, hour, day, date, month, and year. The RTC
has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that
controls 24 hour or AM/PM format. When the X1286
powers up after the loss of both V
and V
, the
BACK
CC
clock will not operate until at least one byte is written
to the clock register.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
FN8101.1
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April 14, 2006
X1286
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Bit
Reg
0
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
Type
Name
7
BAT
SS23
0
6
AL1
SS22
0
5
AL0
SS21
0
4
0
3
0
2
1
(optional) Range
Status
SR
RWEL
SS12
DY2
Y12
WEL
SS11
DY1
Y11
RTCF
01h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
00h
00h
20h
00h
RTC
(SRAM)
SSEC
DW
SS20
0
SS13
0
SS10
DY0
Y10
0-99
0-6
YR
Y23
0
Y22
0
Y21
0
Y20
G20
D20
H20
M20
S20
0
Y13
G13
D13
H13
M13
S13
0
0-99
1-12
1-31
0-23
0-59
0-59
MO
G12
G11
D11
G10
D10
DT
0
0
D21
H21
M21
S21
0
D12
HR
MIL
0
0
H12
H11
H10
MN
M22
S22
0
M12
S12
M11
S11
M10
S10
SC
0
Control
(EEPROM)
DTR
ATR
INT
0
DTR2
ATR2
DTR1
ATR1
DTR0
ATR0
0
0
ATR5
AL0E
BP0
ATR4
FO1
WD1
ATR3
FO0
WD0
IM
BP2
AL1E
BP1
Read Only Read Only Read Only
Read Only Read Only Read Only
BL
Alarm1
(EEPROM)
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Read-only - Default = 20h
20
EDW1
0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO1
EDT1
EHR1
EMN1
ESC1
0
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
A1G11
A1D11
A1H11
A1M11
A1S11
A1G10
A1D10
A1H10
A1M10
A1S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
A1D21
A1H21
A1M21
A1S21
0
A1M22
A1S22
FN8101.1
April 14, 2006
10
X1286
Table 1. Clock/Control Memory Map (Continued)
Bit
Reg
Name
0
Addr.
Type
7
6
5
4
3
2
1
(optional) Range
0007
Alarm0
(EEPROM)
Y2K0
Read-only - Default = 20h
20
20h
00h
0006
0005
0004
0003
0002
0001
0000
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
EDW0
0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value (No EEPROM) – Future expansion
EMO0
EDT0
EHR0
EMN0
ESC0
0
0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
A0D21
A0H21
A0M21
A0S21
0
A0M22
A0S22
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Leap Years
– The user can set the X1286 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible
by 100 are not leap years, unless they are also divisi-
ble by 400. This means that the year 2000 is a leap
year, the year 2100 is not. The X1286 does not correct
for the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SSEC, SC, MN, HR, DT,
MO, YR)
These registers depict BCD representations of the
time. As such, SSEC (1/100 Second) range from 00 to
99, SC (Seconds) and MN (Minutes) range from 00 to
59, HR (Hour) is 1 to 12 with an AM or PM indicator
(H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31,
MO (Month) is 1 to 12, YR (Year) is 0 to 99. The SSEC
register is read-only.
Table 2. Status Register (SR)
Addr
003Fh BAT AL1 AL0
Default
7
6
5
4
3
2
1
0
0
0
0
0
RWEL WEL RTCF
0
0
0
0
0
1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V , not V . It is a read-only bit and is set/reset
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
BACK
CC
by hardware (X1286 interally). Once the device begins
operating from V , the device sets this bit to “0”.
CC
FN8101.1
April 14, 2006
11
X1286
AL1, AL0: Alarm bits—Volatile
Unused Bits:
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
RWEL: Register Write Enable Latch—Volatile
Block Protect Bits—BP2, BP1, BP0
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so
the device is ready for the next operation immediately
after the stop condition. A write to the CCR requires
both the RWEL and WEL bits to be set in a specific
sequence.
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Protected
Addresses
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do not
cause a nonvolatile write cycle, so the device is ready for
the next operation immediately after the stop condition.
X1286
Array Lock
None (default)
Upper 1/4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
6000h - 7FFFh
4000h - 7FFFh
0000h - 7FFFh
0000h - 007Fh
0000h - 00FFh
0000h - 01FFh
0000h - 03FFh
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 Pgs
Watchdog Timer Control Bits—WD1, WD0
RTCF: Real Time Clock Fail Bit—Volatile
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
This bit is set to a “1” after a total power failure. This is
a read only bit that is set by hardware (X1286 inter-
nally) when the device powers up after having lost all
Table 4. Watchdog Timer Time-Out Options
power to the device (both V
and V
go to 0V).
BACK
CC
CC
Watchdog Time-Out Period
WD1 WD0
The bit is set regardless of whether V
or V
is
BACK
applied first. The loss of only one of the supplies does
not set the RTCF bit to “1”. On power up after a total
power failure, all registers are set to their default
states and the clock will not increment until at least
one byte is written to the clock register. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is suffi-
cient).
0
0
1
1
0
1
0
1
1.75 seconds (default)
750 milliseconds
250 milliseconds
Disabled
FN8101.1
April 14, 2006
12
X1286
INTERRUPT CONTROL AND FREQUENCY
OUTPUT REGISTER (INT)
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either
AL1E and AL0E are set to ‘1’, respectively.
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
Two volatile bits (AL1 and AL0), associated with the
two alarms respectively, indicate if an alarm has hap-
pened. These bits are set on an alarm condition
regardless of whether the IRQ interrupt is enabled.
The AL1 and AL0 bits in the status register are reset
by the falling edge of the eighth clock of a read of the
register containing the bits.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 6. Digital Trimming Registers
Pulse Interrupt Mode
DTR Register
The pulsed interrupt mode allows for repetitive or
Estimated frequency
DTR2
DTR1
DTR0
PPM
recurring alarm functionality. Hence an repetitive or
th
th
recurring alarm can be set for every n second, or n
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
th
th
minute, or n hour, or n date, or for the same day of
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.
+10
+20
+30
0
The Pulse Interrupt Mode is enabled when the IM bit is
set.
-10
-20
-30
IM Bit
Interrupt/Alarm Frequency
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
0
1
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capacitance
adjustment. Using a Citizen CFS-206 crystal with differ-
ent ATR bit combinations provides an estimated ppm
range from +116ppm to -37ppm to the nominal fre-
quency compensation. The combination of digital and
analog trimming can give up to +146ppm adjustment.
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
Programmable Frequency Output Bits—FO1, FO0
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 5 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
The on-chip capacitance can be calculated as follows:
C
= [(ATR value, decimal) x 0.25pF] + 11.0pF
ATR
Table 5. Programmable Frequency Output Bits
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
Output Frequency
FO1 FO0
(average of 100 samples)
0
0
1
1
0
1
0
1
Alarm IRQ output
32.768kHz
100Hz
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
1Hz
See Application section and Intersil’s application Note
AN154 for more information.
FN8101.1
13
April 14, 2006
X1286
WRITING TO THE CLOCK/CONTROL REGISTERS
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 5.
Changing any of the nonvolatile bits of the clock/
control register requires the following steps:
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
Stop Condition
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 5.
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 6.
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
SERIAL COMMUNICATION
Interface Conventions
– The 2nd Data Byte of a Status Register Write Opera-
tion (only 1 data byte is allowed)
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 4.
FN8101.1
14
April 14, 2006
X1286
Figure 4. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 5. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 6. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
DEVICE ADDRESSING
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master must supply the 2 Word Address
Bytes as shown in Figure 7.
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 7.
After loading the entire Slave Address Byte from the
SDA bus, the X1286 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
FN8101.1
15
April 14, 2006
X1286
Figure 7. Slave Address, Word Address, and Data Bytes (128 Byte pages)
Device Identifier
Slave Address Byte
Byte 0
Array
CCR
1
1
0
1
1
0
0
1
1
1
1
R/W
A8
Word Address 1
Byte 1
0
A14
A13
A12
A11
A10
A9
Word Address 0
Byte 2
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Data Byte
Byte 3
Write Operations
Byte Write
to the status register in two preceding operations to
enable the write operation. See “Writing to the
Clock/Control Registers.”
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1286 responds with
an acknowledge. After receiving both address bytes
the X1286 awaits the eight bits of data. After receiving
the 8 data bits, the X1286 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1286 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 8.
After the receipt of each byte, the X1286 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 128 bytes to a memory array page or
8 bytes to a CCR section starting at any location on
that page. For example, if the master begins writing at
location 105 of the memory and loads 30 bytes, then
the first 23 bytes are written to addresses 105 through
127, and the last 7 bytes are written to columns 0
through 6. Afterwards, the address counter would
point to location 7 on the page that was just written. If
the master supplies more than the maximum bytes in
a page, then the previously loaded data is over written
by the new data, one byte at a time. Refer to Figure 9.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1286 to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1286 will not initiate an internal
write cycle, and will continue to ACK commands.
Page Write
Stops and Write Modes
The X1286 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 127
more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1286 resets itself without per-
forming the write. The contents of the array are not
affected.
FN8101.1
16
April 14, 2006
X1286
Figure 8. Byte Write Sequence
S
t
Signals from
the Master
S
t
a
r
Word
Address 1
Word
Address 0
Slave
Address
o
p
t
Data
SDA Bus
1
1 1 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 9. Writing 30 bytes to a 128-byte memory page starting at address 105.
7 Bytes
23 Bytes
Address Pointer
Ends Here
Addr = 7
Address
105
Address
= 6
Address
127
Figure 10. Page Write Sequence
1 ≤ n ≤ 128 for EEPROM array
1 ≤ n ≤ 8 for CCR
S
t
a
r
Signals from
the Master
S
t
Word
Address 1
Slave
Address
Word
Address 0
Data
(1)
Data
(n)
o
p
t
SDA Bus
1
1 1 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
FN8101.1
17
April 14, 2006
X1286
Acknowledge Polling
clock and issuing a stop condition. Refer to Figure 11
for the address, acknowledge, and data transfer
sequence.
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1286 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1286 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1286 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 12.
Figure 12. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave
Issue STOP
Address Byte
Read Operations
(Read or Write)
There are three basic read operations: Current
NO
Address Read, Random Read, and Sequential Read.
ACK
returned?
Current Address Read
YES
Internally the X1286 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power-onpower-on
reset can download the entire contents of memory
starting at the first location.Upon receipt of the Slave
Address Byte with the R/W bit set to one, the X1286
issues an acknowledge, then transmits eight data bits.
The master terminates the read operation by not
responding with an acknowledge during the ninth
NO
nonvolatile write
Cycle complete. Continue
command sequence?
Issue STOP
YES
Continue normal
Read or Write
command
sequence
PROCEED
Figure 11. Current Address Read Sequence
S
t
S
t
Signals from
a
Slave
Address
o
p
the Master
r
t
SDA Bus
1
1 1 1 1
A
C
K
Signals from
the Slave
Data
FN8101.1
April 14, 2006
18
X1286
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Random Read
Sequential Read
Random read operations allows the master to access
any location in the X1286. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received. The
master terminates the read operation by not responding
with an acknowledge and then issuing a stop condition.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt
of each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 13 for the
address, acknowledge, and data transfer sequence.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to the start of the address space and the
X1286 continues to output data for each acknowledge
received. Refer to Figure 14 for the acknowledge and
data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 13. The X1286 then
goes into standby mode after the stop and all bus
Figure 13. Random Address Read Sequence
S
S
t
S
t
t
a
r
Signals from
the Master
Slave
Address
Word
Address 0
a
r
Slave
Address
Word
Address 1
o
p
t
t
SDA Bus
1
1 1 1 1
1
1 1 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 14. Sequential Read Sequence
S
t
Slave
Address
A
C
K
A
A
C
K
Signals from
the Master
C
K
o
p
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
FN8101.1
19
April 14, 2006
X1286
APPLICATION SECTION
the temperature extremes of -40 and +85 deg C. It is
possible to address this variable drift by adjusting the
load capacitance of the crystal, which will result in pre-
dictable change to the crystal frequency. The Intersil
RTC family allows this adjustment over temperature
since the devices include on-chip load capacitor trim-
ming. This control is handled by the Analog Trimming
Register, or ATR, which has 6 bits of control . The load
capacitance range covered by the ATR circuit is
approximately 3.25pF to 18.75pF, in 0.25pf incre-
ments. Note that actual capacitance would also
include about 2pF of package related capacitance. In-
circuit tests with commercially available crystals dem-
onstrate that this range of capacitance allows fre-
quency control from +116ppm to -37ppm, using a
12.5pF load crystal.
CRYSTAL OSCILLATOR AND TEMPERATURE
COMPENSATION
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external
components and adjust for crystal drift over tempera-
ture and enable very high accuracy time keeping
(<5ppm drift).
The Intersil RTC family uses an oscillator circuit with
on-chip crystal compensation network, including
adjustable load-capacitance. The only external com-
ponent required is the crystal. The compensation net-
work is optimized for operation with certain crystal
parameters which are common in many of the surface
mount or tuning-fork crystals available today. Table 6
summarizes these parameters.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation
feature is available for the Intersil RTC family. There
are three bits known as the Digital Trimming Register
or DTR, and they operate by adding or skipping pulses
in the clock signal. The range provided is ±30ppm in
increments of 10ppm. The default setting is 0ppm. The
DTR control can be used for coarse adjustments of
frequency drift over temperature or for crystal initial
accuracy correction.
Table 7 contains some crystal manufacturers and part
numbers that meet the requirements for the Intersil
RTC products.
The turnover temperature in Table 7 describes the
temperature where the apex of the of the drift vs. tem-
perature curve occurs. This curve is parabolic with the
2
drift increasing as (T-T0) . For an Epson MC-405
device, for example, the turnover temperature is typi-
cally 25 deg C, and a peak drift of >110ppm occurs at
Table 7. Crystal Parameters Required for Intersil RTC’s
Parameter
Min
Typ
Max
Units
kHz
ppm
°C
Notes
Frequency
32.768
Freq. Tolerance
±100
30
Down to 20ppm if desired
Turnover Temperature
20
25
Typically the value used for most
crystals
Operating Temperature Range
Parallel Load Capacitance
Equivalent Series Resistance
-40
85
50
°C
pF
kΩ
12.5
For best oscillator performance
Table 8. Crystal Manufacturers
Manufacturer
Citizen
Part Number
CM201, CM202, CM200S
MC-405, MC-406
RSM-200S-A or B
32S12A or B
Temp Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-10 to +60°C
-10 to +60°C
-40 to +85°C
+25°C Freq Toler.
±20ppm
Epson
Raltron
SaRonix
Ecliptek
ECS
±20ppm
±20ppm
±20ppm
ECPSM29T-32.768K
ECX-306/ECX-306I
FSM-327
±20ppm
±20ppm
Fox
±20ppm
FN8101.1
April 14, 2006
20
X1286
A final application for the ATR control is in-circuit cali-
bration for high accuracy applications, along with a
temperature sensor chip. Once the RTC circuit is pow-
ered up with battery backup, the PHZ output is set at
32.768kHz and frequency drift is measured. The ATR
control is then adjusted to a setting which minimizes
drift. Once adjusted at a particular temperature, it is
possible to adjust at other discrete temperatures for
minimal overall drift, and store the resulting settings in
the EEPROM. Extremely low overall temperature drift
is possible with this method. The Intersil evaluation
board contains the circuitry necessary to implement
this control.
frequency, noise can couple to the X1 or X2 pins and
cause double-clocking. The layout in figure 15 can
help minimize this by running the PHZ output away
from the X1 and X2 pins. Also, minimizing the switch-
ing current at this pin by careful selection of the pullup
resistor value will reduce noise. Intersil suggests a
minimum value of 5.1k for 32.768kHz, and higher val-
ues (i.e. 20kΩ) for lower frequency PHZ outputs.
For other RTC products, the same rules stated above
should be observed, but adjusted slightly since the
packages and pinouts are slightly different.
Assembly
For more detailed operation see Intersil’s application
note AN154 on Intersil’s website at www.Intersil.com.
Most electronic circuits do not have to deal with
assembly issues, but with the RTC devices assembly
includes insertion or soldering of a live battery into an
unpowered circuit. If a socket is soldered to the board,
and a battery is inserted in final assembly, then there
are no issues with operation of the RTC. If the battery
is soldered to the board directly, then the RTC device
Vback pin will see some transient upset from either
soldering tools or intermittent battery connections
which can stop the circuit from oscillating. Once the
battery is soldered to the board, the only way to assure
the circuit will start up is to momentarily (very short
period of time!) short the Vback pin to ground and the
circuit will begin to oscillate.
Layout Considerations
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits on
the board. Since the X2 pin is tied to the other side of
the crystal, it is also a sensitive node. These signals can
couple into the oscillator circuit and produce double
clocking or mis-clocking, seriously affecting the accu-
racy of the RTC. Care needs to be taken in layout of the
RTC circuit to avoid noise pickup. Below in Figure 15 is
a suggested layout for the X1286 or X1288 devices.
Figure 15. Suggested Layout for Intersil RTC in SO-8
Oscillator Measurements
C1
When a proper crystal is selected and the layout guide-
lines above are observed, the oscillator should start up
in most circuits in less than one second. Some circuits
may take slightly longer, but startup should definitely
occur in less than 5 seconds. When testing RTC cir-
cuits, the most common impulse is to apply a scope
probe to the circuit at the X2 pin (oscillator output) and
observe the waveform. DO NOT DO THIS! Although in
some cases you may see a useable waveform, due to
the parasitics (usually 10pF to ground) applied with the
scope probe, there will be no useful information in that
waveform other than the fact that the circuit is oscillat-
ing. The X2 output is sensitive to capacitive impedance
so the voltage levels and the frequency will be affected
by the parasitic elements in the scope probe. Applying a
scope probe can possibly cause a faulty oscillator to
start up, hiding other issues (although in the Intersil
RTC’s, the internal circuitry assures startup when using
the proper crystal and layout).
0.1µF
R1 10k
U1
XTAL1
X1286/X1288
32.768kGz
The X1 and X2 connections to the crystal are to be
kept as short as possible. A thick ground trace around
the crystal is advised to minimize noise intrusion, but
ground near the X1 and X2 pins should be avoided as
it will add to the load capacitance at those pins. Keep
in mind these guidelines for other PCB layers in the
vicinity of the RTC device. A small decoupling capaci-
tor at the Vcc pin of the chip is mandatory, with a solid
connection to ground.
The best way to analyze the RTC circuit is to power it
up and read the real time clock as time advances, or if
the chip has the PHZ output, look at the output of that
pin on an oscilloscope (after enabling it with the con-
trol register, and using a pullup resistor for an open-
drain output). Alternatively, the X1226/X1286/1288
The X1286 product has a special consideration. The
PHZ/IRQ- pin on the 8 Ld SOIC package is located
next to the X2 pin. When this pin is used as a fre-
quency output (PHZ) and is set to 32.768kHz output
FN8101.1
21
April 14, 2006
X1286
devices have an IRQ- output which can be checked by
setting an alarm for each minute. Using the pulse
interrupt mode setting, the once-per-minute interrupt
functions as an indication of proper oscillation.
Figure 16. Supercapactor charging circuit
2.7-5.5V
VCC
Vback
Backup Battery Operation
Supercapacitor
Many types of batteries can be used with the Intersil
RTC products. 3.0V or 3.6V Lithium batteries are
appropriate, and sizes are available that can power a
Intersil RTC device for up to 10 years. Another option
is to use a supercapacitor for applications where Vcc
may disappear intermittently for short periods of time.
Depending on the value of supercapacitor used,
backup time can last from a few days to two weeks
(with >1F). A simple silicon or Schottky barrier diode
can be used in series with Vcc to charge the superca-
pacitor, which is connected to the Vback pin. Do not
use the diode to charge a battery (especially lithium
batteries!).
VSS
Since the battery switchover occurs at Vcc=Vback-
0.1V (see Figure 16), the battery voltage must always
be lower than the Vcc voltage during normal operation
or the battery will be drained.
The summary of conditions for backup battery opera-
tion is given in Table 9:
Table 9. Battery Backup Operation
1. Example Application, Vcc = 5V, Vback = 3.0V
Condition
a. Normal Operation
Vcc
5.00
5.00
0-1.8
Vback
3.00
Vtrip
4.38
4.38
4.38
Iback
<<1µA
0
Notes
b. Vcc on with no battery
c. Backup Mode
0
1.8-3.0
<2µA
Timekeeping only
2. Example Application, Vcc = 3.3V,Vback = 3.0V
Condition
a. Normal Operation
Vcc
3.30
Vback
3.00
Vtrip
2.65
2.65
2.65
2.65
Iback
<<1µA
0
b. Vcc on with no battery
c. Backup Mode
3.30
0
0-1.8
1.8-3.0*
> Vcc
<2µA*
up to 3mA
Timekeeping only
d. UNWANTED - Vcc ON, Vback
powering
2.65 - 3.30
Internal Vcc=Vback
*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device
FN8101.1
22
April 14, 2006
X1286
Referring to Figure 16, Vtrip applies to the “Internal
Vcc” node which powers the entire device. This means
that if Vcc is powered down and the battery voltage at
Vback is higher than the Vtrip voltage, then the entire
chip will be running from the battery. If Vback falls to
lower than Vtrip, then the chip shuts down and all out-
puts are disabled except for the oscillator and time-
keeping circuitry. The fact that the chip can be
powered from Vback is not necessarily an issue since
standby current for the RTC devices is <2µA for this
mode (called “main timekeeping current” in the data
sheet). Only when the serial interface is active is there
an increase in supply current, and with Vcc powered
down, the serial interface will most likely be inactive.
PERFORMANCE DATA
Performance
I
BACK
IBACK vs. Temperature
Multi-Lot Process Variation Data
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3.3V
1.8V
One way to prevent operation in battery backup mode
above the Vtrip level is to add a diode drop (silicon
diode preferred) to the battery to insure it is below
Vtrip. This will also provide reverse leakage protection
which may be needed to get safety agency approval.
-40
25
60
85
Temperature °C
One mode that should always be avoided is the opera-
tion of the RTC device with Vback greater than both Vcc
and Vtrip (Condition 2d in Table 9). This will cause the
battery to drain quickly as serial bus communication and
non-volatile writes will require higher supplier current.
FN8101.1
April 14, 2006
23
X1286
TSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
FN8101.1
April 14, 2006
24
X1286
8-Lead Plastic, EIAJ SOIC, Package Code A8
0.020 (.508)
0.012 (.305)
.330 (8.38)
.300 (7.62)
.213 (5.41)
.205 (5.21)
Pin 1 ID
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
.010 (.254)
.007 (.178)
0° - 8° Ref.
.035 (.889)
.020 (.508)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8101.1
25
April 14, 2006
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