X28C010EM-25 [RENESAS]
IC,EEPROM,128KX8,CMOS,LLCC,32PIN,CERAMIC;
| 型号： | X28C010EM-25 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,EEPROM,128KX8,CMOS,LLCC,32PIN,CERAMIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1M
128K x 8 Bit
X28C010
5 Volt, Byte Alterable E2PROM
FEATURES
DESCRIPTION
2
• Access Time: 120ns
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control Cir-
cuits
—Self-Timed
• No Erase Before Write
• No Complex Programming Algorithms
• No Overerase Problem
• Low Power CMOS:
—Active: 50mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100Years
• Early End of Write Detection
—DATA Polling
The Xicor X28C010 is a 128K x 8 E PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and enabling
the entire memory to be typically written in less than 2.5
seconds. The X28C010 also features DATA Polling and
Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C010 supports Software Data Protection
option.
2
Xicor E PROMs are designed and tested for applications
requiring extended endurance. Data retention is specified
to be greater than 100 years.
—Toggle Bit Polling
PIN CONFIGURATIONS
EXTENDED LCC
PLCC
CERDIP
FLAT PACK
SOIC (R)
LCC
PGA
4
3
2
32 31 30
30
29
I/O
15
I/O
17
I/O
19
I/O
21
I/O
22
1
0
2
3
5
6
4
3
2
32 31
A
NC
1
32
V
A
5
6
7
5
29
A
14
7
A
7
CC
14
1
A
A
6
7
28
27
26
25
24
23
22
21
A
A
8
28
27
26
25
24
23
22
A
A
6
6
13
13
A
2
3
31
30
WE
CE
24
A
13
A
I/O
V
I/O
I/O
A
A
16
1
0
1
SS
4
7
5
5
8
14
16
18
20
23
A
A
A
A
A
8
9
8
9
NC
4
9
4
9
15
X28C010
(TOP VIEW)
X28C010
(TOP VIEW)
A
A
A
A
11
A
A
A
10
OE
26
3
11
3
2
3
A
4
5
29
28
A
A
10
11
OE
A
A
10
11
OE
12
14
12
11
25
2
2
A
A
A
A
1
10
1
10
A
7
13
A
A
A
A
4
5
X28C010
(BOTTOM VIEW)
11
9
A
12
13
CE
I/O
A
12
13
CE
0
0
10
9
7
27
28
A
6
6
27
A
8
I/O
I/O
0
I/O
0
15 1617 18 1920
7
7
21
14
A
A
A
A
13
A
7
8
26
25
A
6
7
8
14 15 1617 18 1920
5
9
8
6
29
30
A
4
A
11
X28C010
A
A
NC
NC
V
NC
34
NC
32
A
14
31
12
15
CC
A
9
24
23
OE
3
5
4
2
3
36
TSOP
A
2
10
A
10
A
NC
NC
33
WE
35
16
1
2
3
4
5
6
7
8
40
39
A11
A9
A8
A
11
12
13
14
15
16
22
21
20
19
18
17
CE
1
OE
A10
CE
1
38
37
36
A
0
I/O
7
I/O
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
A13
A14
NC
I/O
0
6
35
34
NC
NC
WE
I/O
I/O
5
I/O
1
33
32
31
9
I/O
2
4
X28C010
10
11
12
13
14
15
16
17
18
19
20
VCC
NC
NC
30
29
28
V
I/O
3
SS
NC
A16
A15
NC
I/O2
I/O1
I/O0
A0
A1
A2
27
26
25
A12
A7
A6
24
23
22
21
A5
A4
A3
????-1.0 2/12/99 ??/??/?? EP
Characteristics subject to change without notice
1
X28C010
PIN DESCRIPTIONS
Addresses (A0–A16)
PIN NAMES
Symbol
Description
The Address inputs select an 8-bit memory location
during a read or write operation.
A –A
Address Inputs
0
16
I/O –I/O
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
7
Chip Enable (CE)
WE
CE
OE
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
V
Output Enable (OE)
CC
The Output Enable input controls the data output buffers
and is used to initiate read operations.
V
Ground
SS
NC
No Connect
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C010 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010.
FUNCTIONAL DIAGRAM
1M-BIT
X BUFFERS
LATCHES AND
DECODER
2
A –A
E PROM
ARRAY
8
16
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
A –A
0
7
I/O –I/O
DATA INPUTS/OUTPUTS
0
7
CE
OE
CONTROL
LOGIC AND
TIMING
WE
V
CC
V
SS
2
X28C010
DEVICE OPERATION
Read
Write Operation Status Bits
The X28C010 provides the user two write operation
status bits.These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus
as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture
eliminates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Figure 1. Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH.The X28C010 supports both a
CE and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
RESERVED
TOGGLE BIT
DATA POLLING
DATA Polling (I/O7)
The X28C010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C010,
eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data. Note: If the
X28C010 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows two
to two hundred fifty-six bytes of data to be consecutively
written to the X28C010 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A8 through A16) for each subsequent valid
write cycle to the part during this operation must be the
same as the initial page address.
Toggle Bit (I/O6)
The X28C010 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
3
X28C010
DATA Polling I/O7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28C010
READY
A –A
0
14
An
An
An
An
An
An
An
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28C010. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implement-
ing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
NO
COMPARE?
YES
X28C010
READY
4
X28C010
The Toggle Bit I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28C010
READY
* Beginning and ending state of I/O will vary.
6
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
READY
5
X28C010
HARDWARE DATA PROTECTION
The X28C010 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the
software algorithm. This circuit is nonvolatile and will
remain set for the life of the device unless the reset
command is issued.
The X28C010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
• Default VCC Sense—All functions are inhibited when
VCC is £3.5V.
• Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Once the software protection is enabled, the X28C010 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE DATA PROTECTION
The X28C010 offers a software controlled data protection
feature. The X28C010 is shipped from Xicor with the
software data protection NOT ENABLED: that is the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the
host system to precede data write operations by a series
of three write operations to three specific addresses.
Refer to Figures 6 and 7 for the sequence.The three byte
sequence opens the page write window enabling the
host to write from one to two hundred fifty-six bytes of
data. Once the page load cycle has been completed, the
device will automatically be returned to the data
protected state.
6
X28C010
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
V
(V
)
CC
CC
0V
DATA
ADDR
AA
5555
55
2AAA
A0
5555
t
WRITE
PROTECTED
WC
WRITES
OK
CE
£t
BYTE
OR
PAGE
BLC MAX
WE
Figure 7. Write Sequence for
Software Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28C010 will automatically disable further writes unless
another command is issued to cancel it. If no further
commands are issued the X28C010 will be write
protected during power-down and after any subsequent
power-up. The state of A15 and A16 while executing the
algorithm is don’t care.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE/PAGE
LOAD OPERATION
WRITE LAST
BYTE TO
LASTADDRESS
AFTER t
WC
RE-ENTERS DATA
PROTECTED STATE
7
X28C010
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
DATA
AA
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
STANDARD
OPERATING
MODE
³t
ADDR 5555
WC
CE
WE
Figure 9. Software Sequence to Deactivate
Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in an
E PROM programmer, the following six step algorithm
will reset the internal protection circuit. After tWC, the
X28C010 will be in standard operating mode.
WRITE DATA AA
TO ADDRESS
5555
2
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
8
X28C010
SYSTEM CONSIDERATIONS
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency
ceramic capacitor be used between VCC and VSS at each
device. Depending on the size of the array, the value of
the capacitor may have to be larger.
Because the X28C010 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where multiple
I/O pins share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array.This bulk capacitor is
employed to overcome the voltage drop caused by the
inductive effects of the PC board traces.
Because the X28C010 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
Active Supply Current vs. Ambient Temperature
ICC (RD) by Temperature over Frequency
18
60
VCC = 5V
5.0 VCC
50
16
14
12
10
–55°C
+25°C
40
30
20
10
+125°C
–55
–10
+35
+80
+125
0
3
6
9
12
15
AMBIENT TEMPERATURE (° C)
FREQUENCY (MHz)
Standby Supply Current vs. Ambient Temperature
0.3
VCC = 5V
0.25
0.2
0.15
0.1
0.05
–55
–10
+35
+80
+125
AMBIENT TEMPERATURE (° C)
9
X28C010
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
X28C010............................................–10°C to +85°C
X28C010I.........................................–65°C to +135°C
X28C010M ......................................–65°C to +135°C
Storage Temperature..............................–65°C to +150°C
Voltage on any Pin with
Respect to VSS.......................................... –1V to +7V
D.C. Output Current ....................................................5mA
Lead Temperature
(Soldering, 10 seconds) ................................... 300°C
RECOMMEND OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
Limits
X28C010
5V ±10%
–40°C
–55°C
Military
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
CE = OE = VIL, WE = VIH,
VCC Current (Active)
(TTL Inputs)
ICC
50
mA
All I/O’s = Open, Address Inputs =
.4V/2.4V Levels @ f = 5MHz
CE = VIH, OE = VIL
VCC Current (Standby)
(TTL Inputs)
ISB1
3
mA
µA
All I/O’s = Open, Other Inputs = VIH
CE = VCC – 0.3V, OE = VIL
VCC Current (Standby)
(CMOS Inputs)
ISB2
500
All I/O’s = Open, Other Inputs = VCC
ILI
V
IN = VSS to VCC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
ILO
VOUT = VSS to VCC, CE = VIH
(1)
VlL
–1
2
0.8
(1)
V
CC + 1
VIH
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
VOL
VOH
IOL = 2.1mA
0.4
V
IOH = –400µA
2.4
V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
10
X28C010
POWER-UP TIMING
Symbol
Parameter
Max.
100
5
Units
µs
(2)
tPUR
Power-up to Read Operation
Power-up to Write Operation
(2)
tPUW
ms
CAPACITANCE TA = +25°C, f = 1MHZ, VCC = 5V
Symbol
Parameter
Max.
10
Units
pF
Test Conditions
(2)
VI/O = 0V
CI/O
Input/Output Capacitance
Input Capacitance
(2)
VIN = 0V
CIN
10
pF
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Min.
10,000
100,000
100
Max.
Units
Cycles Per Byte
Cycles Per Page
Years
Endurance
Data Retention
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
0V to 3V
10ns
CE
L
OE
L
WE
Mode
I/O
DOUT
DIN
Power
Active
Active
Input Rise and
Fall Times
H
L
Read
Write
L
H
Input and Output
Timing Levels
Standby and
Write Inhibit
1.5V
H
X
X
High Z
Standby
X
X
L
X
H
Write Inhibit
Write Inhibit
—
—
—
—
X
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
5V
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
1.92KW
OUTPUT
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
1.37KW
100pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Notes: (2) This parameter is periodically sampled and not 100%
tested.
11
X28C010
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C010-12 X28C010-15 X28C010-20 X28C010-25
Symbol
tRC
Parameter
Read Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Units
120
150
200
250
ns
ns
ns
ns
ns
ns
ns
ns
tCE
Chip Enable Access Time
Address Access Time
120
120
50
150
150
50
200
200
50
250
250
50
tAA
tOE
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
(3)
tLZ
0
0
0
0
0
0
0
0
(3)
tOLZ
(3)
tHZ
50
50
50
50
50
50
50
50
(3)
tOHZ
Output Hold from
Address Change
tOH
0
0
0
0
ns
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
t
LZ
OH
AA
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
Notes: (3) tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
12
X28C010
Write Cycle Limits
Symbol
Parameter
Write Cycle Time
Address Setup Time
Min.
Max.
Units
ms
ns
(4)
tWC
tAS
10
0
50
0
tAH
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
ns
tCS
ns
tCH
0
ns
tCW
tOES
tOEH
tWP
tWPH
tDV
100
10
10
100
100
ns
ns
ns
ns
ns
1
µs
tDS
Data Setup
50
0
ns
tDH
Data Hold
ns
tDW
tBLC
Delay to Next Write
Byte Load Cycle
10
0.2
µs
100
µs
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
t
OEH
t
WP
WE
t
WPH
DV
DATA IN
DATA OUT
DATA VALID
t
t
DS
DH
HIGH Z
Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the
device requires to complete internal write operation.
13
X28C010
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
CW
CE
t
WPH
t
OES
OE
t
OEH
t
CS
t
t
CH
DH
WE
t
DV
DATA VALID
DATA IN
t
DS
HIGH Z
DATA OUT
Page Write Cycle
(5)
OE
CE
t
t
WP
BLC
WE
t
WPH
(6)
ADDRESS *
I/O
LASTBYTE
BYTE n+2
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
16
8
writes to an unknown address could occur.
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to
fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a poll-
ing operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
14
X28C010
(7)
DATA Polling Timing Diagram
ADDRESS
CE
An
An
An
WE
t
t
OEH
OES
OE
t
DW
D
=X
D
=X
I/O
D
=X
OUT
OUT
IN
7
t
WC
Toggle Bit Timing Diagram
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
I/O
*
6
*
t
WC
* I/O beginning and ending state will vary.
6
Notes: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
X28C010
PACKAGING INFORMATION
32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.690 (42.95)
MAX.
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.13) MIN.
0.100 (2.54) MAX.
SEATING
PLANE
0.232 (5.90) MAX.
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) MIN.
0.200 (5.08)
0.125 (3.18)
0.065 (1.65)
0.033 (0.84)
0.023 (0.58)
0.014 (0.36)
0.110 (2.79)
0.090 (2.29)
TYP.0.055 (1.40)
TYP.0.018 (0.46)
TYP. 0.100 (2.54)
0.620 (15.75)
0.590 (14.99)
TYP.0.614 (15.60)
0°
0.015 (0.38)
0.008 (0.20)
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F09
16
X28C010
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
0.200 (5.08)
BSC
0.015 (0.38)
TYP. (4) PLCS.
MIN.
0.028 (0.71)
0.022 (0.56)
(32) PLCS.
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.088 (2.24)
0.050 (1.27)
0.442 (11.22)
0.458 (11.63)
––
0.120 (3.05)
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
PIN 1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
17
X28C010
PACKAGING INFORMATION
32-LEAD CERAMIC FLAT PACK TYPE F
1.228 (31.19)
1.000 (25.40)
PIN 1 INDEX
0.019 (0.48)
0.015 (0.38)
1
32
0.050 (1.27) BSC
0.830 (21.08) MAX.
0.045 (1.14) MAX.
0.005 (0.13) MIN.
0.488
0.120 (3.05)
0.090 (2.29)
0.007 (0.18)
0.004 (0.10)
0.430 (10.93)
0.370 (9.40)
0.270 (6.86)
0.045 (1.14)
0.026 (0.66)
0.347 (8.82)
0.330 (8.38)
0.030 (0.76)
MIN
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F20
18
X28C010
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.030" TYPICAL
32 PLACES
0.050"
0.420 (10.67)
TYPICAL
0.050"
TYPICAL
0.510"
TYPICAL
0.400"
0.050 (1.27) TYP.
0.300"
REF
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
TYP.0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.495 (12.57)
0.015 (0.38)
0.095 (2.41)
0.485 (12.32)
TYP.0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP.0.136 (3.45)
0.447 (11.35)
TYP.0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP.0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP.0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
19
X28C010
PACKAGING INFORMATION
36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
15
14
11
9
17
16
19
18
21
20
22
23
25
27
29
32
33
A
0.008 (0.20)
0.050 (1.27)
13
12
10
8
24
26
A
28
30
31
NOTE: LEADS 5, 14, 23, & 32
7
TYP.0.100 (2.54)
ALL LEADS
6
5
2
3
36
1
34
35
TYP.0.180 (.010)
(4.57 ± .25)
4 CORNERS
4
TYP.0.180 (.010)
(4.57 ± .25)
4 CORNERS
0.120 (3.05)
0.100 (2.54)
0.072 (1.83)
0.062 (1.57)
PIN 1 INDEX
0.770 (19.56)
0.750 (19.05)
SQ
0.020 (0.51)
0.016 (0.41)
A
A
0.185 (4.70)
0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F21
20
X28C010
PACKAGING INFORMATION
32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R
0.060 NOM.
SEE DETAIL “A”
FOR LEAD
INFORMATION
0.020 MIN.
0.165 TYP
0.035 TYP
0.340
±0.007
0.015 R TYP.
0.015 R
TY. P
.
0.035 MIN.
DETAIL “A”
0.050"
TYPICAL
0.0192
0.0138
0.050"
TYPICAL
0.560"
TYPICAL
0.840
MAX.
0.750
±0.005
0.030" TYPICAL
32 PLACES
0.050
FOOTPRINT
0.440 MAX.
0.560 NOM.
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F27
21
X28C010
PACKAGING INFORMATION
32-PAD STRETCHED CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE N
0.300 BSC
0.035 x 45° REF.
DETAIL A
0.005/0.015
0.006/0.022
0.085 ± 0.010
DETAIL A
PIN 1
0.025 ± 0.003
0.400 BSC
0.050 ± 0.005
0.020 (1.02) x 45° REF.
TYP. (3) PLCS.
0.050 BSC
0.450 ± 0.008
0.458 MAX.
0.060/0.120
0.700 ± 0.010
0.708 MAX.
PIN #1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT±0.005 (0.127)
3926 FHD F35
22
X28C010
PACKAGING INFORMATION
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
0.493 (12.522)
0.483 (12.268)
0.045 (1.143)
0.035 (0.889)
(0.038)
0.965
PIN #1 IDENT.
O 0.040 (1.016) 0.005 (0.127) DP.
X
0.048 (1.219)
0.0197 (0.500)
O 0.030 (0.762) 0.003 (0.076) DP.
1
0.396 (10.058)
0.392 (9.957)
0.007 (0.178)
15° TYP.
SEATING
PLANE
0.010 (0.254)
0.006 (0.152)
A
0.0025 (0.065)
0.040 (1.016)
SEATING
PLANE
DETAIL A
0.032 (0.813) TYP.
0.017 (0.432)
0.557 (14.148)
0.547 (13.894)
0.006 (0.152)
TYP.
4° TYP.
0.017 (0.432)
0.020 (0.508) TYP.
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
SOLDER PADS
TYPICAL
40 PLACES
15 EQ.SPC.@ 0.50 ± 0.04
0.0197 ± 0.016 = 9.50± 0.06
(0.374± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE: 1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
23
X28C010
ORDERING INFORMATION
X
X28C010
X
-X
AccessTime
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Device
Temperature Range
Blank = Commercial = 0°C to 70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
D = 32-Lead Cerdip
E = 32-Pad LCC
F = 32-Lead Flat Pack
J = 32-Lead PLCC
K = 36-Lead Pin Grid Array
R = 32-Lead Ceramic SOIC (Gull Wing)
N = 32-Lead Extended LCC
T = 40-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
24
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