X40035V14Z-AT1T1 [RENESAS]
3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14;
| 型号： | X40035V14Z-AT1T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14 输入元件 光电二极管 |
| 文件： | 总24页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X40030, X40031, X40034, X40035
®
Data Sheet
May 25, 2006
FN8114.1
PRELIMINARY
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Computers
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Standard reset threshold settings
see selection table on page 5.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Network servers
DESCRIPTION
The X40030, X40031, X40034, X40035 combine
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision, and
manual reset, in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
—Reset signal valid to V = 1V
CC
—Monitor three seperate voltages
• Fault detection register
• Selectable power on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
Applying voltage to V activates the power on reset cir-
CC
cuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available in 14 Ld SOIC, TSSOP packages
• Monitor voltages: 5V to 0.9V
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third voltage
monitor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be reprogrammed
to meet specific system level requirements or to fine-tune
the threshold for applications requiring higher precision.
• Independent core voltage monitor
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communication equipment
—Routers, hubs, switches
—Disk arrays, network storage
BLOCK DIAGRAM
+
-
V3MON
V3FAIL
VTRIP3
V3 Monitor
Logic
V
or
CC
V2MON*
+
-
V2MON
V2FAIL
V2 Monitor
VTRIP2
Logic
Watchdog
and
Fault Detection
Register
Data
WDO
MR
Reset Logic
SDA
WP
Register
Status
Register
Command
Decode Test
& Control
Logic
SCL
RESET
Power on,
Manual Reset
Low Voltage
Reset
X40030/34
RESET
+
VCC
(V1MON)
X40031/35
VTRIP1
Generation
VCC Monitor
Logic
-
LOWLINE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40030, X40031, X40034, X40035
Ordering Information
PART
MARKING
MONITORED
VCC RANGE
VTRIP1
RANGE
VTRIP2
RANGE
VTRIP3
RANGE
TEMP.
RANGE (°C)
PKG.
DWG. #
PART NUMBER
PACKAGE
PART NUMBER WITH RESET
X40034S14-A
X40034S A
1.3 to 5.5
4.6V ±50mV 1.3V ±50mV 3.1V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40034S14Z-A
(Note)
X40034S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14-B
X40034S B
2.9V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40034S14Z-B
(Note)
X40034S ZB
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14-C
X40034S14I-A
X40034S C
X40034S IA
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
0 to 70
14 Ld SOIC (150 mil) M14.15
1.3V ±50mV 3.1V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40034S14IZ-A X40034S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14I-B
X40034S IB
2.9V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40034S14IZ-B X40034S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14I-C
X40034V14-A
X40034S IC
X4003 4VA
X4003 4VZA
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
1.3V ±50mV 3.1V ±50mV
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
X40034V14Z-A
(Note)
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14-B
X4003 4VB
2.9V ±50mV
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
X40034V14Z-B
(Note)
X4003 4VZB
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14-C
X40034V14I-A
X4003 4VC
X4003 4VIA
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
0 to 70
14 Ld TSSOP (4.4mm) M14.173
1.3V ±50mV 3.1V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40034V14IZ-A X4003 4VZIA
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14I-B
X4003 4VIB
2.9V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40034V14IZ-B X4003 4VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14I-C
X40030S14-C
X40030S14I-C
X40030V14-C
X40030V14I-C
X40030S14-B
X4003 4VIC
X40030S C
X40030S IC
X4003 0VC
X4003 0VIC
X40030S B
X40030S ZB
1.0 to 3.6
1.7 to 3.6
1.0V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
2.9V ±50mV 2.2V ±50mV 1.7V ±50mV
0 to 70
-40 to +85 14 Ld SOIC (150 mil) M14.15
0 to 70 14 Ld TSSOP (4.4mm) M14.173
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
14 Ld SOIC (150 mil) M14.15
1.7 to 5.5
4.4V ±50mV 2.6V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40030S14Z-B
(Note)
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030S14I-B
X40030S IB
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40030S14IZ-B X40030S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030V14-B
X4003 0VB
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
X40030V14Z-B
(Note)
X4003 0VZB
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
FN8114.1
May 25, 2006
2
X40030, X40031, X40034, X40035
Ordering Information (Continued)
PART
MARKING
MONITORED
VCC RANGE
VTRIP1
RANGE
VTRIP2
RANGE
VTRIP3
RANGE
TEMP.
RANGE (°C)
PKG.
DWG. #
PART NUMBER
PACKAGE
X40030V14I-B
X4003 0VIB
1.7 to 5.5
4.4V ±50mV 2.6V ±50mV 1.7V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40030V14IZ-B X4003 0VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40030S14-A
X40030S A
4.6V ±50mV 2.9V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40030S14Z-A
(Note)
X40030S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030S14I-A
X40030S IA
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40030S14IZ-A X40030S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030V14-A
X4003 0VA
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
X40030V14Z-A
(Note)
X4003 0VZA
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40030V14I-A
X4003 0VIA
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40030V14IZ-A X4003 0VZIA
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
PART NUMBER WITH RESET
X40035S14-A
X40035S A
1.3 to 5.5
4.6V ±50mV 1.3V ±50mV 3.1V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40035S14Z-A
(Note)
X40035S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40035S14-B
X40035S B
2.9V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40035S14Z-B
(Note)
X40035S ZB
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40035S14-C
X40035S14I-A
X40035S C
X40035S IA
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
0 to 70
14 Ld SOIC (150 mil) M14.15
1.3V ±50mV 3.1V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40035S14IZ-A X40035S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40035S14I-B
X40035S IB
2.9V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40035S14IZ-B X40035S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40035S14I-C
X40035V14-A
X40035V14-B
X40035S IC
X4003 5VA
X4003 5VB
X4003 5VZB
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to 70
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
X40035V14Z-B
(Note)
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40035V14-C
X4003 5VC
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
X40035V14Z-AT1 X4003 5VZA
(Note)
1.3V ±50mV 3.1V ±50mV
14 Ld TSSOP
M14.173
Tape and Reel
(4.4mm) (Pb-free)
X40035V14I-A
X4003 5VIA
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40035V14IZ-A X4003 5VZIA
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40035V14I-B
X4003 5VIB
2.9V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40035V14IZ-B X4003 5VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40035V14I-C
X4003 5VIC
1.0 to 3.6
1.0V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
FN8114.1
May 25, 2006
3
X40030, X40031, X40034, X40035
Ordering Information (Continued)
PART
MARKING
MONITORED
VCC RANGE
VTRIP1
RANGE
VTRIP2
RANGE
VTRIP3
RANGE
TEMP.
RANGE (°C)
PKG.
DWG. #
PART NUMBER
X40031S14-C
X40031S14I-C
X40031V14-C
X40031V14I-C
X40031S14-B
PACKAGE
X40031S C
X40031S IC
X4003 1VC
X4003 1VIC
X40031S B
X40031S ZB
1.7 to 3.6
2.9V ±50mV 2.2V ±50mV 1.7V ±50mV
0 to 70
14 Ld SOIC (150 mil) M14.15
-40 to +85 14 Ld SOIC (150 mil) M14.15
0 to 70 14 Ld TSSOP (4.4mm) M14.173
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
1.7 to 5.5
4.4V ±50mV 2.6V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40031S14Z-B
(Note)
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031S14I-B
X40031S IB
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40031S14IZ-B X40031S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031V14-B
X4003 1VB
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
X40031V14Z-B
(Note)
X4003 1VZB
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40031V14I-B
X4003 1VIB
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40031V14IZ-B X4003 1VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40031S14-A
X40031S A
4.6V ±50mV 2.9V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40031S14Z-A
(Note)
X40031S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031S14I-A
X40031S IA
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40031S14IZ-A X40031S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031V14-A
X4003 1VA
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
X40031V14Z-A
(Note)
X4003 1VZA
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40031V14I-A
X4003 1VIA
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40031V14IZ-A X4003 1VZIA
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8114.1
May 25, 2006
4
X40030, X40031, X40034, X40035
A manual reset input provides debounce circuitry for
minimum reset component count.
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
Expected System
Voltages
V
V
V
trip3
(V)
POR
(system)
trip1
trip2
Device
(V)
(V)
X40030, X40031
2.0-4.75*
4.55-4.65*
4.35-4.45*
2.95-3.05*
1.70-4.75
2.85-2.95
2.55-2.65
2.15-2.25
1.70-4.75
1.65-1.75
1.65-1.75
1.65-1.75
-A
-B
-C
5V; 3V or 3.3V; 1.8V
5V; 3V; 1.8V
3.3V; 2.5V; 1.8V
RESET = X40030
RESET = X40031
X40034, X40035
2.0-4.75*
4.55-4.65*
4.55-4.65*
4.55-4.65*
0.90-3.50
1.25-1.35
1.25-1.35
0.95-1.05
1.70-4.75
3.05-3.15
2.85-2.95
2.85-2.95
-A
-B
-C
5V; 3.3V; 1.5V
5V; 3V or 3.3V; 1.5V
5V; 3V or 3.3V; 1.2V
RESET = X40030
RESET = X40031
*Voltage monitor requires V to operate. Others are independent of V
CC
CC
PIN CONFIGURATION
X40031, X40035
14-Pin SOIC, TSSOP
X40030, X40034
14-Pin SOIC, TSSOP
VCC
WDO
V3FAIL
V3MON
WP
SCL
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
VSS
VCC
WDO
V3FAIL
V3MON
WP
V2FAIL
V2MON
1
2
3
4
14
13
12
11
1
2
3
4
14
13
12
11
LOWLINE
NC
MR
RESET
VSS
5
6
7
10
9
8
5
6
7
10
9
8
SCL
SDA
SDA
PIN DESCRIPTION
Pin
Name
Function
1
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin.
2
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or V when
CC
not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the VCC input
(X40034, X40035).
3
LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when V
< VTRIP1 and goes high
CC
when V > VTRIP1
.
CC
4
5
NC
MR
No connect.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the tPURST thereafter.
6
RESET/
RESET
RESET Output. (X40031, X40035) This open drain pin is an active LOW output which goes LOW
whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (tPURST) on power up. It will also stay active until manual reset is
released and for tPURST thereafter.
RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH
whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (tPURST) on power up. It will also stay active until manual reset is
released and for tPURST thereafter.
FN8114.1
May 25, 2006
5
X40030, X40031, X40034, X40035
PIN DESCRIPTION (Continued)
Pin
7
Name
VSS
Function
Ground
8
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
Write Protect. WP HIGH prevents writes to any location in the device (includung all the registers).
It has an internal pull down resistor. (>10MΩ typical)
11
V3MON
V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to VSS or V when
CC
not used. The V3MON comparator is supplied by the V3MON input.
12
13
14
V3FAIL
WDO
VCC
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and
goes HIGH when V3MON exceeds VTRIP3. There is no power up reset delay circuitry on this pin.
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
Supply Voltage.
PRINCIPLES OF OPERATION
Power On Reset
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t
after.
Applying power to the X40030, X40031, X40034,
X40035 activates a Power On Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
there-
PURST
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
Low Voltage V (V1 Monitoring)
CC
During operation, the X40030, X40031, X40034,
X40035 monitors the level and asserts
RESET/RESET if supply voltage falls below a preset
minimum V . The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
V
CC
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
TRIP1
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
remains active until V
returns and exceeds V
When V exceeds the device V
threshold value
CC
TRIP1
CC
TRIP1
for tPURST
.
for t
(selectable) the circuit releases the RESET
PURST
(X40031, X40035) and RESET (X40030, X40034) pin
allowing the system to begin operation.
Low Voltage V2 Monitoring
The X40030 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
Figure 1. Connecting a Manual Reset Push-Button
mum V
. The V2FAIL signal is either ORed with
TRIP2
VCC
X40030/34
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.
System
RESET
Reset
MR
For the X40030 and X40031 the V2FAIL signal
remains active until the V2MON drops below 1V
(V2MON falling). It also remains active until V2MON
Manual
Reset
FN8114.1
May 25, 2006
6
X40030, X40031, X40034, X40035
returns and exceeds V
.This voltage sense cir-
Figure 2. Two Uses of Multiple Voltage Monitoring
TRIP2
cuitry monitors the power supply connected to V2MON
pin. If V = 0, V2MON can still be monitored.
CC
VCC
For the X40034 and X40035, the V2FAIL signal
X40031-A
remains active until V drops below 1V and remains
CC
6-10V
5V
VCC
RESET
V2FAIL
active until V2MON returns and exceeds V
.This
TRIP2
System
Reset
sense circuitry is powered by V . If V = 0, V2MON
CC
CC
V2MON
3.3V
1M
cannot be monitored.
V3MON
(1.7V)
Power
Fail
V3FAIL
390K
Low Voltage V3 Monitoring
Interrupt
The X40030, X40031, X40034, X40035 also monitors
a third voltage level and asserts V3FAIL if the voltage
falls below a preset minimum V
. The V3FAIL sig-
TRIP3
nal is either ORed with RESET to prevent the micro-
processor from operating in a power fail or brownout
condition or used to interrupt the microprocessor with
notification of an impending power failure. The V3FAIL
signal remains active until the V3MON drops below 1V
(V3MON falling). It also remains active until V3MON
VCC
X40031-B
Unreg.
Supply
5V
VCC
Reg
System
Reset
RESET
V2MON
3.0V
Reg
returns and exceeds V
.
TRIP3
V2FAIL
V3FAIL
This voltage sense circuitry monitors the power supply
1.8V
Reg
connected to V3MON pin. If V = 0, V3MON can still
V3MON
CC
be monitored.
Notice: No external components required to monitor three voltages.
Early Low V Detection (LOWLINE)
CC
This CMOS output goes LOW earlier than
RESET/RESET whenever V
falls below the V
CC
TRIP1
voltage and returns high when V
exceeds the
CC
V
voltage. There is no power up delay circuitry
) on this pin.
TRIP1
(t
PURST
Figure 3. V
Set/Reset Conditions
TRIPX
VTRIPX
(X = 1, 2, 3)
VCC/V2MON/V3MON
VP
WDO
SCL
7
0
0
7
0
7
SDA
tWC
A0h
00h
FN8114.1
May 25, 2006
7
X40030, X40031, X40034, X40035
WATCHDOG TIMER
A0h, followed by the Byte Address 01h for V
, 09h
TRIP1
for V
order to program V
write operation initiates the programming sequence. Pin
WDO must then be brought LOW to complete the oper-
ation. To check if the V
, and 0Dh for V
, and a 00h Data Byte in
TRIP2
TRIP3
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal going active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40030, X40031, X40034,
X40035 control register (also refer to page 21).
. The STOP bit following a valid
TRIPx
has been set, set VXMON
TRIPX
to a value slightly greater than V
(that was previ-
TRIPX
ously set). Slowly ramp down VXMON and observe
when the corresponding outputs (LOWLINE, V2FAIL
and V3FAIL) switch. The voltage at which this occurs is
the V
(actual).
TRIPX
CASE A
Now if the desired V
(actual), then add the difference between V
(desired) – V (actual) to the original V
desired. This is your new V
applied to VXMON and the whole sequence should be
repeated again (see Figure 5).
is greater than the V
TRIPX
TRIPX
TRIPX
TRIPX
Figure 4. Watchdog Restart
TRIPX
.6µs
1.3µs
that should be
TRIPX
SCL
SDA
CASE B
Now if the V
(actual), is higher than the V
TRIPX
Start
Stop
TRIPX
WDT Reset
(desired), perform the reset sequence as described in
the next section. The new V
to VXMON will now be: V
voltage to be applied
TRIPX
TRIPX
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)
(desired) – (V
TRIPX
(actual) – V
(desired)).
TRIPX
The X40030 is shipped with standard V1, V2 and V3
threshold (V ) voltages. These
Note: This operation does not corrupt the memory array.
V
V
TRIP3
TRIP1,
TRIP2,
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40030,
X40031, X40034, X40035 trip points may be adjusted.
The procedure is described below, and uses the appli-
cation of a high voltage control signal.
Setting a Lower V
Voltage (x=1, 2, 3)
TRIPx
In order to set V
to a lower voltage than the
TRIPx
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
must first be “reset” accord-
TRIPx
TRIPx
can be set to the desired
TRIPx
voltage using the procedure described in “Setting a
Higher V Voltage”.
TRIPx
Setting a V
Voltage (x=1, 2, 3)
TRIPx
Resetting the V
Voltage
TRIPx
There are two procedures used to set the threshold
voltages (V ), depending if the threshold voltage to
To reset a V
voltage, apply the programming volt-
TRIPx
TRIPx
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
be stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIPx
V
is 3.2 V, the new voltage can be stored directly
TRIPx
V
, 0Bh for V
, and 0Fh for V
, followed
TRIP1
TRIP2
TRIP3
into the V
cell. If however, the new setting is to be
TRIPx
by 00h for the Data Byte in order to reset V
. The
TRIPx
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
TRIPx
Setting a Higher V
Voltage (x=1, 2, 3)
TRIPx
After being reset, the value of V
nal value of 1.7V or lesser.
becomes a nomi-
To set a V
threshold to a new voltage which is
TRIPx
TRIPx
higher than the present threshold, the user must apply
the desired V threshold voltage to the corre-
sponding input pin (Vcc(V1MON), V2MON or V3MON).
Then, a programming voltage (Vp) must be applied to
the WDO pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address
TRIPx
Notes: 1.This operation does not corrupt the memory
array.
2. Set V ≅ 1.5(V2MON or V3MON), when
CC
setting V
or V
respectively
TRIP2
TRIP3
FN8114.1
May 25, 2006
8
X40030, X40031, X40034, X40035
CONTROL REGISTER
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0 and BP. The X40030,
X40031, X40034, X40035 will not acknowledge any
data bytes written after the first byte is entered.
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write opera-
tion. Prior to writing to the Control Register, the WEL
and RWEL bits must be set using a two step process,
with the whole sequence requiring 3 steps. See "Writing
to the Control Registers" on page 11.
7
6
5
4
3
2
1
0
PUP1 WD1 WD0 BP
0
RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample V
Reset Circuit
TRIP
VP
Adjust
V2FAIL
µC
1
6
2
7
14
RESET
13
X40030
Run
9
8
VTRIP1
Adj.
SCL
SDA
VTRIP2
Adj.
FN8114.1
May 25, 2006
9
X40030, X40031, X40034, X40035
Figure 6. V
Set/Reset Sequence (X = 1, 2, 3)
TRIPX
Vx = VCC, VxMON
Note: X = 1, 2, 3
VTRIPX Programming
Let: MDE = Maximum Desired Error
Desired
No
VTRIPX
<
MDE+
Acceptable
Present Value
Desired Value
YES
Error Range
MDE–
Execute
TRIPX Reset Sequence
V
Error = Actual - Desired
Set VX = desired VTRIPX
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
Execute Reset VTRIPX
Sequence
> Desired VTRIPX to
VX
NO
Decrease
VX
Output Switches?
YES
V
Error < MDE–
Error > MDE+
Actual
TRIPX -
VTRIPX
Desired
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
PUP1, PUP0: Power Up Bits (Nonvolatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
The Power Up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power up times are
shown in the following table.
PUP1 PUP0
Power on Reset Delay (tPURST)
0
0
1
1
0
1
0
1
50ms
200ms (factory setting)
400ms
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
800ms
FN8114.1
May 25, 2006
10
X40030, X40031, X40034, X40035
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, or
power cycling the device or attempting a write to a
write protected block.
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
200 milliseconds
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
25 milliseconds
disabled (factory setting)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
Notes: 1. t
is set to 200ms as factory default.
PURST
2. Watch Dog Timer bits are shipped
disabled.
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
FAULT DETECTION REGISTER (FDR)
The Fault Detection Register provides the user the
status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
7
6
5
4
3
2
1
0
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Con-
trol register can be represented as qxys 001r in
binary, where xy are the WD bits, s is the BP bit and
qr are the power up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
nonvolatile write cycle it will take up to 10ms (max.)
to complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
LV1F LV2F LV3F WDF MRF
0
0
0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
FN8114.1
May 25, 2006
11
X40030, X40031, X40034, X40035
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the FDR is defaulted to all “0”. The sys-
tem needs to initialize this register to all “1” before the
actual monitoring can take place. In the event of any
one of the monitored sources fail. The corresponding
bit in the register will change from a “1” to a “0” to indi-
cate the failure. At this moment, the system should
perform a read to the register and note the cause of
the reset. After reading the register the system should
reset the register back to all “1” again. The state of the
FDR can be read at any time by performing a random
read at address 0FFh, using the special preamble.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one
byte of data is read by the register read operation.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
MRF: Manual Reset Fail Bit (Volatile)
The MRF bit will be set to “0” when Manual Reset
input goes active.
Serial Start Condition
WDF: Watchdog Timer Fail Bit (Volatile)
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 8.
The WDF bit will be set to “0” when the WDO goes
active.
LV1F: Low V Reset Fail Bit (Volatile)
CC
The LV1F bit will be set to “0” when V
(V1MON)
CC
falls below V
.
TRIP1
Serial Stop Condition
LV2F: Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below V
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
.
TRIP2
LV3F: Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to “0” when the V3MON falls
below V
.
TRIP3
FN8114.1
May 25, 2006
12
X40030, X40031, X40034, X40035
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. See Figure 9.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits the
next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. During this internal write cycle, the device
inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high
impedance. See Figure 10.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
A write to a protected block of memory will supress the
acknowledge bit.
Figure 9. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output from
Transmitter
Data Output
from Receiver
Start
Acknowledge
FN8114.1
May 25, 2006
13
X40030, X40031, X40034, X40035
Stops and Write Modes
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 11 for the
address, acknowledge, and data transfer sequence.
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Figure 10. Acknowledge Polling Sequence
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 10.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Issue STOP
Byte (Read or Write)
NO
ACK
Returned?
Serial Read Operations
YES
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
YES
Read Operation
Continue Normal
Read or Write
Command Sequence
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start con-
PROCEED
Figure 11. Random Address Read Sequence
S
S
t
S
t
a
r
Slave
Address
Byte
Address
Slave
Address
Signals from
the Master
t
a
r
o
p
t
t
SDA Bus
1 0 1 1 0 0
0
1 1 1 1 1 1 1 1
1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
FN8114.1
May 25, 2006
14
X40030, X40031, X40034, X40035
SERIAL DEVICE ADDRESSING
Slave Address Byte
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
Operational Notes
– a device type identifier that is always ‘1011’.
The device powers-up in the following state:
– one bit (AS) that provides the device select bit. AS
bit is set-to “0” as factory default.
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– next bit is ‘0’.
Figure 12. X40030, X40031, X40034, X40035
Addressing
– SDA pin is the input mode.
– RESET/RESET Signal is active for tPURST
.
Slave Byte
Control Register
1
1
0
0
1
1
1
1
0
0
0
0
1
0
R/W
R/W
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
Fault Detection Register
– The WEL bit must be set to allow write operations.
Word Address
Control Register
1
1
1
1
1
1
1
1
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
1
1
1
1
1
1
1
1
Fault Detection Register
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
FN8114.1
May 25, 2006
15
X40030, X40031, X40034, X40035
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Chip Supply
Voltage
Moitored*
Voltages
Version
X40030, X40031
X40034, X40035
2.7V to 5.5V
2.7V to 5.5V
1.7V to 5.5V
1.0V to 5.5V
-40°C
+85°C
*See Ordering Info
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
(4)
Symbol
Parameter
Active Supply Current (V ) Read
Min.
Typ.
Max.
1.5
Unit
Test Conditions
(1)
ICC1
mA VIL = V x 0.1
CC
CC
VIH = V x 0.9,
(1)
CC
ICC2
Active Supply Current (V ) Write
3.0
mA
CC
fSCL = 400kHz
(1)
ISB1
Standby Current (V ) AC (WDT off)
6
10
30
µA VIL = V x 0.1
CC
CC
VIH = V x 0.9
CC
fSCL, fSDA = 400kHz
(2)
ISB2
Standby Current (V ) DC (WDT on)
25
µA VSDA = VSCL = VCC
Others = GND or VCC
CC
ILI
Input Leakage Current (SCL, MR, WP)
10
10
µA VIL = GND to V
CC
ILO
Output Leakage Current (SDA, V2FAIL,
V3FAIL, WDO, RESET)
µA
VSDA = GND to V
CC
Device is in Standby(2)
(3)
VIL
Input LOW Voltage (SDA, SCL, MR, WP)
Input HIGH Voltage (SDA, SCL, MR, WP)
-0.5
V
V
x 0.3
V
V
CC
(3)
VIH
V
x 0.7
+ 0.5
CC
CC
(6)
VHYS
Schmitt Trigger Input Hysteresis
• Fixed input level
0.2
.05 x V
V
V
• V related level
CC
CC
VOL
VOH
Output LOW Voltage (SDA, RESET/RE-
SET, LOWLINE, V2FAIL, V3FAIL, WDO)
0.4
V
I
OL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.7-3.6V)
IOH = -1.0mA (2.7-5.5V)
Output (RESET, LOWLINE) HIGH Volt-
age
V
V
– 0.8
– 0.4
V
CC
CC
IOH = -0.4mA (2.7-3.6V)
VCC Supply
(5)
VTRIP1
V
Trip Point Voltage Range
2.0
4.75
4.65
V
V
CC
4.55
4.6
X40030, X40031-A,
X40034, X40035
4.35
2.85
4.4
2.9
4.45
2.95
V
V
X40030, X40031-B
X40030, X40031-C
Second Supply Monitor
IV2 V2MON Current
15
µA
FN8114.1
May 25, 2006
16
X40030, X40031, X40034, X40035
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
(4)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
(5)
VTRIP2
V2MON Trip Point Voltage Range
1.7
0.9
4.75
3.5
V
V
X40030, X40031
X40034, X40035
2.85
2.55
2.15
1.25
0.95
2.9
2.6
2.2
1.3
1.0
2.95
2.65
2.25
1.35
1.05
5
V
V
X40030, X40031-A
X40030, X40031-B
X40030, X40031-C
X40034, X40035-A&B
X40034, X40035-C
V
V
V
(6)
tRPD2
VTRIP2 to V2FAIL
µs
Third Supply Monitor
IV3
V3MON Current
V3MON Trip Point Voltage Range
15
4.75
1.75
3.15
2.95
5
µA
V
(5)
VTRIP3
1.7
1.65
3.05
2.85
1.7
3.1
2.9
V
X40030, X40031
V
X40034, X40035-A
X40034, X40035-B&C
V
(6)
tRPD3
VTRIP3 to V3FAIL
µs
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high
voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
(4) At 25°C, VCC = 3V
(5) See ordering information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3)
R
∆V = 100mV
VxMON
∆V
Vref
+
–
Output Pin
VREF
C
tRPDX = 5µs worst case
CAPACITANCE
Symbol
Parameter
Max.
Unit
Test Conditions
OUT = 0V
(1)
COUT
Output Capacitance (SDA, RESET/RESET, LOWLINE,
V2FAIL,V3FAIL, WDO)
8
pF
V
(1)
CIN
Input Capacitance (SCL, WP, MR)
6
pF
VIN = 0V
Note: (1) This parameter is not 100% tested.
FN8114.1
May 25, 2006
17
X40030, X40031, X40034, X40035
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
SYMBOL TABLE
V
= 5V
CC
WAVEFORM
INPUTS
OUTPUTS
VCC
5V
V2MON, V3MON
Must be
steady
Will be
steady
4.6kΩ
4.6kΩ
2.06kΩ
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
RESET
WDO
V2FAIL,
V3FAIL
SDA
30pF
30pF
30pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
A.C. TEST CONDITIONS
N/A
Center Line
is High
Impedance
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
10ns
Input and output timing levels
Output load
V
x 0.5
CC
Standard output load
A.C. CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
fSCL
tIN
SCL Clock Frequency
400
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
tAA
0.1
0.9
tBUF
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
Data In Hold Time
0
Stop Condition Setup Time
Data Output Hold Time
0.6
50
20 +.1Cb(1)
20 +.1Cb(1)
0.6
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
300
300
tF
tSU:WP
tHD:WP
Cb
WP Hold Time
0
Capacitive load for each bus line
400
Note: (1) Cb = total capacitance of one bus line in pF
FN8114.1
May 25, 2006
18
X40030, X40031, X40034, X40035
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA IN
tSU:DAT
tHD:DAT
tSU:STO
tHD:STA
tAA tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
WP
tSU:WP
tHD:WP
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
(1)
tWC
Write Cycle Time
5
10
ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8114.1
May 25, 2006
19
X40030, X40031, X40034, X40035
Power Fail Timings
VTRIPX
tRPDL
tRPDL
tRPDX
VCC
[
[
tRPDX
V2MON or
[
tRPDL
tRPDX
V3MON
tF
LOWLINE or
tR
V2FAIL or
[
VRVALID
V3FAIL
X = 2, 3
RESET/RESET/MR Timings
VTRIP1
VCC
tPURST
tPURST
tRPD1
tF
tR
RESET
VRVALID
RESET
MR
tMD
tIN1
FN8114.1
May 25, 2006
20
X40030, X40031, X40034, X40035
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, V = 5V)
CC
Symbol
Parameters
Min. Typ.(1) Max.
Unit
(2)
tRPD1
VTRIP1 to RESET/RESET (Power down only)
VTRIP1 to LOWLINE
5
µs
tRPDL
t LR
LOWLINE to RESET/RESET delay (Power down only) [= tRPD1-tRPDL
]
500
ns
µs
(2)
tRPDX
VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3)
5
tPURST
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
50(2)
200
400(2)
800(2)
ms
ms
ms
ms
PUP1=1, PUP0=1
tF
VCC, V2MON, V3MON, Fall Time
VCC, V2MON, V3MON, Rise Time
20
20
1
mV/µs
mV/µs
V
tR
VRVALID Reset Valid VCC
tMD MR to RESET/ RESET delay (activation only)
tin1
500
5
ns
Pulse width for MR
µs
tWDO
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
1.4(2)
200(2)
25
s
ms
ms
WD1=1, WD0=0
WD1 = 1, WD0 = 1 (factory setting)
OFF
tRST1
Watchdog Reset Time Out Delay
WD1=0, WD0=0
100
200
300
ms
WD1=0, WD0=1
tRST2
tRSP
Watchdog Reset Time Out Delay WD1=1, WD0=0
Watchdog timer restart pulse width
12.5
1
25
37.5
ms
µs
Notes: (1) VCC = 5V at 25°C.
(2) Values based on characterization data only.
Watchdog Time Out for 2-Wire Interface
Start
Start
Clockin (0 or 1)
tRSP
< tWDO
SCL
SDA
tRST
tWDO
tRST
WDO
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
FN8114.1
May 25, 2006
21
X40030, X40031, X40034, X40035
V
Set/Reset Conditions
TRIPX
(VTRIPX
)
VCC/V2MON/V3MON
tTHD
VP
tTSU
WDO
tVPS
tVPO
tVPH
7
SCL
SDA
0
0
7
0
7
*
tWC
A0h
00h
Start
resets VTRIP1
resets VTRIP2
0Fh* resets VTRIP3
01h*
09h*
0Dh*
03h*
0Bh*
sets VTRIP1
sets VTRIP2
sets VTRIP3
* all others reserved
V
, V
, V
Programming Specifications: V = 2.0–5.5V; Temperature = 25°C
TRIP3 CC
TRIP1
TRIP2
Parameter
tVPS
Description
Min. Max. Unit
WDO Program Voltage Setup time
WDO Program Voltage Hold time
VTRIPX Level Setup time
10
10
10
10
10
1
µs
µs
µs
µs
ms
ms
V
tVPH
tTSU
tTHD
VTRIPX Level Hold (stable) time
tWC
VTRIPX Program Cycle
tVPO
Program Voltage Off time before next cycle
Programming Voltage
VP
15
2.0
1.7
0.9
1.7
-25
10
18
VTRAN1
VTRAN2
VTRAN2A
VTRAN3
Vtv
VTRIP1 Set Voltage Range
4.75
4.75
3.5
V
VTRIP2 Set Voltage Range - X40030, X40031
VTRIP2 Set Voltage Range - X40034, X40035
VTRIP3 Set Voltage Range
V
V
4.75
+25
V
VTRIPX Set Voltage variation after programming (-40 to +85°C).
WDO Program Voltage Setup time
mV
µs
tVPS
FN8114.1
May 25, 2006
22
X40030, X40031, X40034, X40035
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8114.1
May 25, 2006
23
X40030, X40031, X40034, X40035
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
0o
8o
0o
8o
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8114.1
May 25, 2006
24
相关型号：
X40035V14Z-BT1
3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14
RENESAS
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