X40233S16I-B_技术文档

DATASHEET

X40231, X40233, X40235, X40237, X40239

Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM

Memory, and Single/Dual DCP

FN8115

Rev 0.00

April 11, 2005

FEATURES

DESCRIPTION

The X4023x family of Integrated System Manage-

ment ICs combine CPU Supervisor functions (V

• Triple Voltage Monitors

—User Programmable Threshold Voltage

—Power-on Reset (POR) Circuitry

—Software Selectable Reset timeout

—Manual Reset Input

• 2-Wire industry standard Serial Interface

• 2 kbit EEPROM with Write Protect & Block Lock

• Digitally Controlled Potentiometers (DCP)

CC

Power-onpower-on Reset (POR) circuitry, two addi-

tional programmable voltage monitor inputs with soft-

ware and hardware indicators), integrated EEPROM

TM

with Block Lock protection and one or two Intersil

TM

Digitally Controlled Potentiometers (XDCP). All func-

tions of the X4023x are accessed by an industry

standard 2-Wire serial interface.

X4023X Family Selector Guide

X= 256 tap 100 tap 64 Tap

APPLICATIONS

1

3

5

7

9

1

The DCP of the X4023x may be utilized to software

control analog voltages for:

1

– LCD contrast, LCD purity, or Backlight control.

– Power Supply settings such as PWM frequency,

Voltage Trimming or Margining (temperature offset

control).

1

– Reference voltage setting (e.g. DDR-SDRAM SSTL-2)

—Total Resistance

The 2 kbit integrated EEPROM may be used to store

ID, manufacturer data, maintenance data and module

definition data.

256 Tap = 100k100 Tap or 64 Tap = 10k

—Nonvolatile wiper position

—Write Protect Function

• Single Supply Operation

—2.7V to 5.5V

The programmable POR circuit insures V

is stable

CC

before RESET is removed and protects against

brown-outs and power failures. The programmable

voltage monitors have on-chip independent reference

alarm levels. With separate outputs, the voltage moni-

tors can be used for power-on sequencing.

• 16 Pin SOIC (300) package

—SOIC

BLOCK DIAGRAM

8

R

H

WIPER

COUNTER

REGISTER

WP

256 Tap DCP

PROTECT LOGIC

W

CR

REGISTER

8 - BIT

NONVOLATILE

MEMORY

DATA

REGISTER

4

SDA

SCL

COMMAND

DECODE &

CONTROL

LOGIC

R

H

WIPER

Optional

2 kbit

EEPROM

ARRAY

COUNTER

REGISTER

W

64 or 100 Tap DCP

THRESHOLD

RESET LOGIC

8 - BIT

NONVOLATILE

MEMORY

Manual Reset (MR)

V3MON

2

V3FAIL

V2FAIL

RESET

-

+

VTRIP

3

-

+

V2MON

VTRIP

2

1

POWER-ON /

V

CC

+

–

LOW VOLTAGE

RESET

GENERATION

V

SS

are user programmable)

1,2,3

FN8115 Rev 0.00

April 11, 2005

Page 1 of 36

X40231, X40233, X40235, X40237, X40239

PIN CONFIGURATION

SINGLE XDCP

X40233

X40231

X40235

16 Pin SOIC

V_CC

NC

16

1

R_H2

16

1

16

1

RESET

NC

R_W2

15

14

13

15

14

13

2

3

15

14

13

2

3

2

3

V3MON

V3FAIL

MR

V3MON

V3FAIL

MR

V3MON

V3FAIL

MR

V2FAIL

V2MON

NC

V2FAIL

V2MON

R_W0

V2FAIL

V2MON

NC

4

5

6

4

5

6

4

5

6

12

11

10

9

12

11

10

9

12

11

10

9

WP

SCL

SDA

WP

SCL

SDA

WP

SCL

SDA

R_H1

R_H0

NC

7

8

7

8

7

8

R_W1

VSS

NC

VSS

DUAL XDCP

X40237

X40239

16 Pin SOIC

V_CC

R_H2

16

15

14

13

16

15

14

13

1

2

3

1

2

3

RESET

R_W2

V3MON

V3FAIL

MR

V3MON

V3FAIL

MR

V2FAIL

V2MON

R_W0

V2FAIL

V2MON

NC

4

5

6

4

5

6

12

11

10

9

12

11

10

9

WP

SCL

SDA

WP

SCL

SDA

R_H0

R_H1

7

8

7

8

NC

R_W1

VSS

FN8115 Rev 0.00

April 11, 2005

Page 2 of 36

X40231, X40233, X40235, X40237, X40239

X40231 PIN ASSIGNMENT

SOIC

Name

NC

Function

1

2

No Connect

NC

No Connect

V3MON Voltage Monitor Input.

V3MON i s the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than

the V_TRIP3threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V_SSwhen

not used.

3

4

V3MON

V3FAIL

V3MON RESET Output.

This open drain output makes a transition to a HIGH level when V3MON is greater than V_TRIP3and goes

LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires

the use of an external “pull-up” resistor.

Manual Reset.

MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET

pin (V_CCRESET Output pin). RESET will remain HIGH for time t_PURSTafter MR has returned to it’s

normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The

MR pin requires the use of an external “pull-down” resistor.

5

6

MR

WP

Write Protect Control Pin.

WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled

state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and

the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or

nonvolatile) operations can be performed in the device (including the wiper position of any of the

integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,

thus if left floating the write protection feature is disabled.

Serial Clock.

7

8

SCL

SDA

This is a TTL level compatible input pin used to control the serial bus timing for data input and output.

Serial Data.

SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA

pin input buffer is always active (not gated). This pin requires an external pull up resistor.

9

VSS

NC

Ground.

10

11

No Connect

R_H0

Connection to end of resistor array for (the 64 Tap) DCP.

R_W0

12

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.

V2MON Voltage Monitor Input.

V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than

the V_TRIP2threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V_SSwhen

not used.

13

V2MON

V2MON RESET Output.

This open drain output makes a transition to a HIGH level when V2MON is greater than V_TRIP2, and goes

LOW when V2MON is less than V_TRIP2. There is no power-up reset delay circuitry on this pin. The V2FAIL

pin requires the use of an external “pull-up” resistor.

14

V2FAIL

V_CCRESET Output.

This is an active HIGH, open drain output which becomes active whenever V_CCfalls below V_TRIP1. RESET

becomes active on power-up and remains active for a time t_PURSTafter the power supply stabilizes

(t_PURSTcan be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET

pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active (HIGH) using

the manual reset (MR) input pin.

15

16

RESET

V_CC

Supply Voltage.

FN8115 Rev 0.00

April 11, 2005

Page 3 of 36

X40231, X40233, X40235, X40237, X40239

X40233 PIN ASSIGNMENT

SOIC

Name

NC

Function

1

2

No Connect

NC

No Connect

V3MON Voltage Monitor Input.

V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than

the V_TRIP3threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V_SSwhen

not used.

3

4

V3MON

V3FAIL

V3MON RESET Output.

This open drain output makes a transition to a HIGH level when V3MON is greater than V_TRIP3and goes

LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires

the use of an external “pull-up” resistor.

Manual Reset.

MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET

pin (V_CCRESET Output pin). RESET will remain HIGH for time t_PURSTafter MR has returned to it’s

normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The

MR pin requires the use of an external “pull-down” resistor.

5

6

MR

WP

Write Protect Control Pin.

WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled

state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and

the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile

or nonvolatile) operations can be performed in the device (including the wiper position of any of the

integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,

thus if left floating the write protection feature is disabled.

Serial Clock.

7

8

SCL

SDA

This is a TTL level compatible input pin used to control the serial bus timing for data input and output.

Serial Data.

SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA

pin input buffer is always active (not gated). This pin requires an external pull up resistor.

9

VSS

R_W1

Ground.

10

11

12

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.

Connection to end of resistor array for (the 100 Tap) DCP.

No Connect

R_H1

NC

V2MON Voltage Monitor Input.

V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than

the V_TRIP2threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V_SSwhen

not used.

13

14

V2MON

V2FAIL

V2MON RESET Output.

This open drain output makes a transition to a HIGH level when V2MON is greater than V_TRIP2, and goes

LOW when V2MON is less than V_TRIP2. There is no power-up reset delay circuitry on this pin. The

V2FAIL pin requires the use of an external “pull-up” resistor.

V_CCRESET Output.

This is an active HIGH, open drain output which becomes active whenever V_CCfalls below V_TRIP1

.

RESET becomes active on power-up and remains active for a time t_PURSTafter the power supply

stabilizes (t_PURSTcan be changed by varying the PUP0 and PUP1 bits of the internal control register).

The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active

(HIGH) using the manual reset (MR) input pin.

15

16

RESET

V

Supply Voltage.

CC

FN8115 Rev 0.00

April 11, 2005

Page 4 of 36

X40231, X40233, X40235, X40237, X40239

X40235 PIN ASSIGNMENT

SOIC

Name

Function

R_H2

1

2

Connection to end of resistor array for (the 256 Tap) DCP.

R_W2

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.

V3MON Voltage Monitor Input.

V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than

the V_TRIP3threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V_SSwhen

not used.

3

4

V3MON

V3MON RESET Output.

This open drain output makes a transition to a HIGH level when V3MON is greater than V_TRIP3and goes

LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires

the use of an external “pull-up” resistor.

V3FAIL

MR

Manual Reset.

MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET

pin (V_CCRESET Output pin). RESET will remain HIGH for time t_PURSTafter MR has returned to it’s

normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The

MR pin requires the use of an external “pull-down” resistor.

5

6

Write Protect Control Pin.

WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled

state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and

the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile

or nonvolatile) operations can be performed in the device (including the wiper position of any of the

integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,

thus if left floating the write protection feature is disabled.

WP

Serial Clock.

7

8

SCL

SDA

This is a TTL level compatible input pin used to control the serial bus timing for data input and output.

Serial Data.

SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA

pin input buffer is always active (not gated). This pin requires an external pull up resistor.

9

VSS

NC

Ground.

10

11

12

No Connect

V2MON Voltage Monitor Input.

V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than

the V_TRIP2threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V_SSwhen

not used.

13

14

V2MON

V2FAIL

V2MON RESET Output.

This open drain output makes a transition to a HIGH level when V2MON is greater than V_TRIP2, and goes

LOW when V2MON is less than V_TRIP2. There is no power-uppower-up reset delay circuitry on this pin.

The V2FAIL pin requires the use of an external “pull-up” resistor.

V_CCRESET Output.

This is an active HIGH, open drain output which becomes active whenever V_CCfalls below V_TRIP1

.

RESET becomes active on power-up and remains active for a time t_PURSTafter the power supply

stabilizes (t_PURSTcan be changed by varying the PUP0 and PUP1 bits of the internal control register).

The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active

(HIGH) using the manual reset (MR) input pin.

15

16

RESET

V

Supply Voltage.

CC

FN8115 Rev 0.00

April 11, 2005

Page 5 of 36

X40231, X40233, X40235, X40237, X40239

X40237 PIN ASSIGNMENT

SOIC

Name

Function

R_H2

1

2

Connection to end of resistor array for (the 256 Tap) DCP2.

R_W2

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP2.

V3MON Voltage Monitor Input.

V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than

the V_TRIP3threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V_SSwhen

not used.

3

4

V3MON

V3MON RESET Output.

This open drain output makes a transition to a HIGH level when V3MON is greater than V_TRIP3and goes

LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires

the use of an external “pull-up” resistor.

V3FAIL

MR

Manual Reset. MR is a TTL level compatible input.

Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (V_CCRESET Output pin).

RESET will remain HIGH for time t_PURSTafter MR has returned to it’s normally LOW state. The reset

time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an

external “pull-down” resistor.

5

6

Write Protect Control Pin.

WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled

state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and

the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile

or nonvolatile) operations can be performed in the device (including the wiper position of any of the

integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,

thus if left floating the write protection feature is disabled.

WP

Serial Clock.

7

8

SCL

SDA

This is a TTL level compatible input pin used to control the serial bus timing for data input and output.

Serial Data.

SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA

pin input buffer is always active (not gated). This pin requires an external pull up resistor.

9

VSS

NC

Ground.

10

11

No Connect

R_H0

Connection to end of resistor array for (the 64 Tap) DCP0.

R_W0

12

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP0.

V2MON Voltage Monitor Input.

V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than

the V_TRIP2threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V_SSwhen

not used.

13

V2MON

V2MON RESET Output.

This open drain output makes a transition to a HIGH level when V2MON is greater than V_TRIP2, and goes

LOW when V2MON is less than V_TRIP2. There is no power-uppower-up reset delay circuitry on this pin.

The V2FAIL pin requires the use of an external “pull-up” resistor.

14

V2FAIL

RESET

V_CCRESET Output.

This is an active HIGH, open drain output which becomes active whenever V_CCfalls below V_TRIP1

.

RESET becomes active on power-up and remains active for a time t_PURSTafter the power supply

stabilizes (t_PURSTcan be changed by varying the PUP0 and PUP1 bits of the internal control register).

The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active

(HIGH) using the manual reset (MR) input pin.

15

16

V

Supply Voltage.

CC

FN8115 Rev 0.00

April 11, 2005

Page 6 of 36

X40231, X40233, X40235, X40237, X40239

X40239 PIN ASSIGNMENT

SOIC

Name

Function

R_H2

1

2

Connection to end of resistor array for (the 256 Tap) DCP2.

R_W2

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP2.

V3MON Voltage Monitor Input.

V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than

the V_TRIP3threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V_SSwhen

not used.

3

4

V3MON

V3MON RESET Output.

This open drain output makes a transition to a HIGH level when V3MON is greater than V_TRIP3and goes

LOW when V3MON is less than V_TRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires

the use of an external “pull-up” resistor.

V3FAIL

MR

Manual Reset. MR is a TTL level compatible input.

Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (V_CCRESET Output pin).

RESET will remain HIGH for time t_PURSTafter MR has returned to it’s normally LOW state. The reset

time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an

external “pull-down” resistor.

5

6

Write Protect Control Pin.

WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled

state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and

the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile

or nonvolatile) operations can be performed in the device (including the wiper position of any of the

integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,

thus if left floating the write protection feature is disabled.

WP

Serial Clock.

7

8

SCL

SDA

This is a TTL level compatible input pin used to control the serial bus timing for data input and output.

Serial Data.

SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA

pin input buffer is always active (not gated). This pin requires an external pull up resistor.

9

VSS

R_W1

Ground.

10

11

12

Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP1.

Connection to end of resistor array for (the 100 Tap) DCP1.

No Connect

R_H1

NC

V2MON Voltage Monitor Input.

V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than

the V_TRIP2threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V_SSwhen

not used.

13

14

V2MON

V2FAIL

V2MON RESET Output.

This open drain output makes a transition to a HIGH level when V2MON is greater than V_TRIP2, and goes

LOW when V2MON is less than V_TRIP2. There is no power-up reset delay circuitry on this pin. The

V2FAIL pin requires the use of an external “pull-up” resistor.

V_CCRESET Output.

This is an active HIGH, open drain output which becomes active whenever V_CCfalls below V_TRIP1

.

RESET becomes active on power-up and remains active for a time t_PURSTafter the power supply

stabilizes (t_PURSTcan be changed by varying the PUP0 and PUP1 bits of the internal control register).

The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active

(HIGH) using the manual reset (MR) input pin.

15

16

RESET

V

Supply Voltage.

CC

FN8115 Rev 0.00

April 11, 2005

Page 7 of 36

X40231, X40233, X40235, X40237, X40239

SCL

SDA

Data Stable

Data Change

Data Stable

Figure 1. Valid Data Changes on the SDA Bus

DETAILED DEVICE DESCRIPTION

Intersil’s unique circuits allow for all internal trip voltages

to be individually programmed with high accuracy,

either by Intersil at final test or by the user during their

The X4023x combines One or Two Intersil Digitally

Controlled Potentiometer (XDCP) devices,

V

CC

production process. Some distributors offer V

TRIP

power-on reset control, V low voltage reset control,

CC

reprogramming as a value added service. This gives

the designer great flexibility in changing system param-

eters, either at the time of manufacture, or in the field.

two supplementary voltage monitors with independent

outputs, and integrated EEPROM with Block Lock™

protection, in one package. The integrated functional-

ity of the X4023x lowers system cost, increases reli-

ability, and reduces board space requirements.

The memory portion of the device is a CMOS serial

TM

EEPROM array with Intersil’s Block Lock protection.

This memory may be used to store module manufactur-

ing data, serial numbers, or various other system

parameters. The EEPROM array is internally organized

DCPs allow for the “set-and-forget” adjustment during

production test or in-system updating via the industry

standard 2-wire interface.

TM

as x 8, and utilizes Intersil’s proprietary Direct Write

cells providing a minimum endurance of 1,000,000

cycles and a minimum data retention of 100 years.

Applying voltage to V activates the Power-on Reset

CC

circuit which sets the RESET output HIGH, until the

supply voltage stabilizes for a period of time (50-300

msec selectable via software). The RESET output then

goes LOW. The Low Voltage Reset circuit sets the

The device features a 2-Wire interface.

PRINCIPLES OF OPERATION

SERIAL INTERFACE

RESET output HIGH when V

falls below the mini-

CC

mum V

trip point. RESET remains HIGH until V

CC

returns to proper operating level and stabilizes for a

period of time (t . A Manual Reset (MR) input

PURST)

Serial Interface Conventions

allows the user to externally activate the RESET output.

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. The X4023x operates as a slave in

all applications.

Two supplementary Voltage Monitor circuits, V2MON

and V3MON, continuously compare their inputs to

individual trip voltages (independent on-chip voltage

references factory set and user programmable). When

an input voltage exceeds it’s associated trip level, the

corresponding output (V3FAIL, V2FAIL) goes HIGH.

When the input voltage becomes lower than it’s asso-

ciated trip level, the corresponding output is driven

LOW. A corresponding binary representation of the

two monitor circuit outputs (V2FAIL and V3FAIL) are

also stored in latched, volatile (CR) register bits. The

status of these two monitor outputs can be read out via

the 2-wire serial port. The bits will remain SET, even

after the alarm condition is removed, allowing

advanced recovery algorithms to be implemented.

Serial Clock and Data

Data states on the SDA line can change only while

SCL is LOW (see Figure 1). SDA state changes while

SCL is HIGH are reserved for indicating START and

STOP conditions. See Figure 1. On power-up of the

X4023x, the SDA pin is in the input mode.

FN8115 Rev 0.00

April 11, 2005

Page 8 of 36

X40231, X40233, X40235, X40237, X40239

SCL

SDA

Start

Figure 2. Valid Start and Stop Conditions

Stop

The device will respond with an ACKNOWLEDGE after

recognition of a START condition if the correct Device

Identifier bits are contained in the Slave Address Byte. If

a write operation is selected, the device will respond with

an ACKNOWLEDGE after the receipt of each subse-

quent eight bit word.

Serial Start Condition

All commands are preceded by the START condition,

which is a HIGH to LOW transition of SDA while SCL is

HIGH. The device continuously monitors the SDA and

SCL lines for the START condition and does not

respond to any command until this condition has been

met. See Figure 2.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

ACKNOWLEDGE. If an ACKNOWLEDGE is detected

and no STOP condition is generated by the master, the

device will continue to transmit data. The device will ter-

minate further data transmissions if an ACKNOWL-

EDGE is not detected. The master must then issue a

STOP condition to place the device into a known state.

Serial Stop Condition

All communications must be terminated by a STOP con-

dition, which is a LOW to HIGH transition of SDA while

SCL is HIGH. The STOP condition is also used to place

the device into the Standby power mode after a read

sequence. A STOP condition can only be issued after

the transmitting device has released the bus. See Figure

2.

DEVICE INTERNAL ADDRESSING

Addressing Protocol Overview

Serial Acknowledge

An ACKNOWLEDGE (ACK) is a software convention

used to indicate a successful data transfer. The transmit-

ting device, either master or slave, will release the bus

after transmitting eight bits. During the ninth clock cycle,

the receiver will pull the SDA line LOW to ACKNOWL-

EDGE that it received the eight bits of data. Refer to Fig-

ure 3

The user addressable internal components of the

X4023x can be split up into three main parts:

—One or Two Digitally Controlled Potentiometers (DCPs)

—EEPROM array

—Control and Status (CR) Register

SCL from

Master

1

8

9

Data Output from

Transmitter

Data Output

from Receiver

Start

Acknowledge

Figure 3. Acknowledge Response From Receiver

FN8115 Rev 0.00

April 11, 2005

Page 9 of 36

X40231, X40233, X40235, X40237, X40239

Depending upon the operation to be performed on each

of these individual parts, a 1, 2 or 3 Byte protocol is

used. All operations however must begin with the Slave

Address Byte being issued on the SDA pin. The Slave

address selects the part of the X4023x to be addressed,

and specifies if a Read or Write operation is to be per-

formed.

SA7 SA6

SA3 SA2

SA5 SA4

SA1

SA0

R/W

1 0 1 0

READ /

WRITE

INTERNAL

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESS

It should be noted that in order to perform a write opera-

tion to either a DCP or the EEPROM array, the Write

Enable Latch (WEL) bit must first be set (See “BL1, BL0:

Block Lock protection bits - (Nonvolatile)” on page 18.)

Internally Addressed

Device

Internal Address

(SA3 - SA1)

000

010

111

EEPROM Array

CR Register

DCP

Slave Address Byte

Following a START condition, the master must output a

Slave Address Byte (Refer to Figure 4). This byte con-

sists of three parts:

Bit SA0

Operation

WRITE

—The Device Type Identifier which consists of the most

significant four bits of the Slave Address (SA7 - SA4).

The Device Type Identifier must always be set to 1010 in

order to select the X4023x.

0

1

READ

Figure 4. Slave Address Format

—The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 000 internally selects

the EEPROM array, while setting these bits to 111

selects the DCP structures in the X4023x. The CR Reg-

ister may be selected using the Internal Device Address

010.

To perform acknowledge polling, the master issues a

START condition followed by a Slave Address Byte. The

Slave Address issued must contain a valid Internal

Device Address. The LSB of the Slave Address (R/W)

can be set to either 1 or 0 in this case. If the device is still

busy with the high voltage cycle then no ACKNOWL-

EDGE will be returned. If the device has completed the

write operation, an ACKNOWLEDGE will be returned

and the host can then proceed with a read or write oper-

ation. (Refer to Figure 5)

—The Least Significant Bit of the Slave Address (SA0)

Byte is the R/W bit. This bit defines the operation to be

performed on the device being addressed (as defined in

the bits SA3 - SA1). When the R/W bit is “1”, then a

READ operation is selected. A “0” selects a WRITE oper-

ation (Refer to Figure 4)

DIGITALLY CONTROLLED POTENTIOMETERS

Nonvolatile Write Acknowledge Polling

After a nonvolatile write command sequence (for either

the EEPROM array, the Non Volatile Memory of a DCP

(NVM), or the CR Register) has been correctly issued

(including the final STOP condition), the X4023x initiates

an internal high voltage write cycle. This cycle typically

requires 5 ms. During this time, no further Read or Write

commands can be issued to the device. Write Acknowl-

edge Polling is used to determine when this high voltage

write cycle has been completed.

DCP Functionality

The X4023x includes one or two independent resistor

arrays. For the 64, 100 or 256 tap XDCPs, these arrays

respectively contain 63, 99 discrete resistive segments

that are connected in series. (the 256 tap resistor

achieves an equivalent end to end resistance.) The

physical ends of each array are equivalent to the fixed

terminals of a mechanical potentiometer. At one end of

the resistor array the terminal connects to the R pin (x

Hx

= 0,1,2).The other end of the resistor array is connected

to V inside the package.

SS

FN8115 Rev 0.00

April 11, 2005

Page 10 of 36

X40231, X40233, X40235, X40237, X40239

At both ends of each array and between each resistor

segment there is a CMOS switch connected between

the resistor array and the wiper (R ) output. Within

each individual array, only one switch may be turned on

at any one time. These switches are controlled by the

Wiper Counter Register (WCR) (See Figure 6). The

WCR is a volatile register.

Byte load completed

by issuing STOP.

Enter ACK Polling

x

w

Issue START

On power-up of the X4023x, wiper position data is auto-

matically loaded into the WCR from its associated Non

Volatile Memory (NVM) Register. The Table below shows

the Initial Values of the DCP WCR’s before the contents

of the NVM is loaded into the WCR.

Issue Slave Address

Byte (Read or Write)

Issue STOP

NO

ACK

returned?

DCP

Initial Values Before Recall

R₀(64 TAP)

V_H(TAP = 63)

YES

R₁(100 TAP)

R₂(256 TAP)

V_L(TAP = 0)

High Voltage Cycle

complete. Continue

command sequence?

NO

V_H(TAP = 255)

Issue STOP

The data in the WCR is then decoded to select and

enable one of the respective FET switches. A “make

before break” sequence is used internally for the FET

switches when the wiper is moved from one tap position

to another.

YES

Continue normal

Read or Write

command sequence

Hot Pluggability

Figure 7 shows a typical waveform that the X4023x

might experience in a Hot Pluggable situation. On

PROCEED

power-up, V applied to the X4023x may exhibit some

CC

amount of ringing, before it settles to the required value.

Figure 5.

Acknowledge Polling Sequence

The device is designed such that the wiper terminal

(R ) is recalled to the correct position (as per the last

Wx

stored in the DCP NVM), when the voltage applied to

R_Hx

N

V

exceeds V

for a time exceeding t

(the

CC

PURST

TRIP1

Power-on Reset time, set in the CR Register - See

“CONTROL AND STATUS REGISTER” on page 18.).

WIPER

COUNTER

REGISTER

(WCR)

Therefore, if t_transis defined as the time taken for V to

CC

settle above V

(Figure 7): then the desired wiper

TRIP1

terminal position is recalled by (a maximum) time: t_trans

+ t_PURST. It should be noted that t_transis determined by

system hot plug conditions.

“WIPER”

RESISTOR

ARRAY

DECODER

FET

SWITCHES

2

NON

VOLATILE

MEMORY

DCP Operations

In total there are three operations that can be performed

on any internal DCP structure:

1

0

(NVM)

—DCP Nonvolatile Write

—DCP Volatile Write

—DCP Read

R_Wx

Figure 6. DCP Internal Structure

FN8115 Rev 0.00

April 11, 2005

Page 11 of 36

X40231, X40233, X40235, X40237, X40239

V

CC

V_CC

(Max.)

V

TRIP1

t

TRANS

t

PURST

t

0

Maximum Wiper Recall time

Figure 7. DCP Power-up

A nonvolatile write to a DCP will change the “wiper posi-

tion” by simultaneously writing new data to the associated

WCR and NVM. Therefore, the new “wiper position” setting

I7

I6

0

I5

0

I4

0

I3

0

I2

0

I1

P1

I0

P0

WT

is recalled into the WCR after V of the X4023x is pow-

CC

ered down and then powered back up.

WRITE TYPE

DCP SELECT

A volatile write operation to a DCP however, changes

the “wiper position” by writing new data to the associated

WCR only. The contents of the associated NVM register

WT^†

Description

remains unchanged. Therefore, when V to the device

CC

Select a Volatile Write operation to be performed

on the DCP pointed to by bits P1 and P0

0

is powered down then back up, the “wiper position”

reverts to that last position written to the DCP using a

nonvolatile write operation.

Select a Nonvolatile Write operation to be per-

formed on the DCP pointed to by bits P1 and P0

1

Both volatile and nonvolatile write operations are exe-

cuted using a three byte command sequence: (DCP)

Slave Address Byte, Instruction Byte, followed by a Data

Byte (See Figure 9)

†

This bit has no effect when a Read operation is being performed.

Figure 8. Instruction Byte Format

A DCP Read operation allows the user to “read out” the

current “wiper position” of the DCP, as stored in the

associated WCR. This operation is executed using the

Random Address Read command sequence, consisting

of the (DCP) Slave Address Byte followed by an Instruc-

tion Byte and the Slave Address Byte again (Refer to

Figure 10).

LSB of the Slave Address is 0), the Most Significant Bit

of the Instruction Byte (I7), determines the Write Type

(WT) performed.

If WT is “1”, then a Nonvolatile Write to the DCP occurs. In

this case, the “wiper position” of the DCP is changed by

simultaneously writing new data to the associated WCR

and NVM. Therefore, the new “wiper position” setting is

recalled into the WCR after V of the X4023x has been

powered down then powered back up.

CC

Instruction Byte

While the Slave Address Byte is used to select the DCP

devices, an Instruction Byte is used to determine which

DCP is being addressed.

If WT is “0” then a DCP Volatile Write is performed.

This operation changes the DCP “wiper position” by

writing new data to the associated WCR only. The con-

tents of the associated NVM register remains

The Instruction Byte (Figure 8) is valid only when the

Device Type Identifier and the Internal Device Address

bits of the Slave Address are set to 1010111. In this

case, the two Least Significant Bit’s (I1 - I0) of the

Instruction Byte are used to select the particular DCP (0

- 2). In the case of a Write to any of the DCPs (i.e. the

unchanged. Therefore, when V

to the device is pow-

CC

ered down then back up, the “wiper position” reverts to

that last written to the DCP using a nonvolatile write

operation.

FN8115 Rev 0.00

April 11, 2005

Page 12 of 36

X40231, X40233, X40235, X40237, X40239

1

0

1

0

1

0

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

S

T

A

R

T

A

C

K

WT

0

P1 P0

A

C

K

A

C

K

S

T

O

P

SLAVE ADDRESS BYTE

INSTRUCTION BYTE

Figure 9. DCP Write Command Sequence

Using a Data Byte larger than the values specified

above results in the “wiper terminal” being set to the

highest tap position. The “wiper position” does NOT roll-

over to the lowest tap position.

DCP Write Operation

A write to DCPx (x=0,1,2) can be performed using the

three byte command sequence shown in Figure 9.

In order to perform a write operation on a particular

DCP, the Write Enable Latch (WEL) bit of the CR Regis-

ter must first be set (See “BL1, BL0: Block Lock protec-

tion bits - (Nonvolatile)” on page 18.)

For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte

maps one to one to the “wiper position” of the DCP

“wiper terminal”. Therefore, the Data Byte 00001111

(15 ) corresponds to setting the “wiper terminal” to tap

10

The Slave Address Byte 10101110 specifies that a Write

to a DCP is to be conducted. An ACKNOWLEDGE is

returned by the X4023x after the Slave Address, if it has

been received correctly.

position 15. Similarly, the Data Byte 00011100 (28

)

10

corresponds to setting the “wiper terminal” to tap posi-

tion 28. The mapping of the Data Byte to “wiper position”

data for DCP1 (100 Tap), is shown in “APPENDIX 1” .

An example of a simple C language function which

“translates” between the tap position (decimal) and the

Data Byte (binary) for DCP1, is given in “APPENDIX 2” .

Next, an Instruction Byte is issued on SDA. Bits P1 and

P0 of the Instruction Byte determine which WCR is to be

written, while the WT bit determines if the Write is to be

volatile or nonvolatile. If the Instruction Byte format is

valid, another ACKNOWLEDGE is then returned by the

X4023x.

It should be noted that all writes to any DCP of the

X4023x are random in nature. Therefore, the Data Byte

of consecutive write operations to any DCP can differ by

an arbitrary number of bits. Also, setting the bits P1 = 1,

P0 = 1 is a reserved sequence, and will result in no

ACKNOWLEDGE after sending an Instruction Byte on

SDA.

Following the Instruction Byte, a Data Byte is issued to

the X4023x over SDA. The Data Byte contents is latched

into the WCR of the DCP on the first rising edge of the

clock signal, after the LSB of the Data Byte (D0) has

been issued on SDA (See Figure 34).

The factory default setting of all “wiper position” settings

is with 00h stored in the NVM of the DCPs. This corre-

sponds to having the “wiper terminal” R_WX(x = 0,1,2) at

the “lowest” tap position, Therefore, the resistance

between R_WXand R_LXis a minimum (essentially only the

Wiper Resistance, R_W).

The Data Byte determines the “wiper position” (which

FET switch of the DCP resistive array is switched ON) of

the DCP. The maximum value for the Data Byte

depends upon which DCP is being addressed (see fol-

lowing table).

P1- P0

DCPx

x = 0

x = 1

x = 2

# Taps

64

Max. Data Byte

0

1

0

1

0

1

3Fh

Refer to Appendix 1

FFh

100

256

Reserved

FN8115 Rev 0.00

April 11, 2005

Page 13 of 36

X40231, X40233, X40235, X40237, X40239

WRITE Operation

READ Operation

Data Byte

S

t

S

t

Signals from

the Master

Instruction

Byte

Slave

Address

S

t

o

p

Slave

Address

a

r

a

r

t

SDA Bus

P

0

P

W

T

1 0 1 0 1 1 1 0

0 0 0 0 0

1 0 1 0 1 1 1 1

1

A

C

K

A

C

K

A

C

K

DCPx

x = 0

Signals from

the Slave

- -

-

x = 1

x = 2

“Dummy” write

LSB

MSB

“-” = DON’T CARE

Figure 10. DCP Read Sequence

Byte read in this operation, corresponds to the “wiper

position” (value of the WCR) of the DCP pointed to by

bits P1 and P0.

DCP Read Operation

A read of DCPx (x = 0,1,2) can be performed using the

three byte random read command sequence shown in

Figure 10.

It should be noted that when reading out the data byte

for DCP0 (64 Tap), the upper two most significant bits

are “unknown” bits. For DCP1 (100 Tap), the upper most

significant bit is an “unknown”. For DCP2 (256 Tap)

however, all bits of the data byte are relevant (See Fig-

ure 10).

The master issues the START condition and the Slave

Address Byte 10101110 which specifies that a “dummy”

write” is to be conducted. This “dummy” write operation

sets which DCP is to be read (in the preceding Read

operation). An ACKNOWLEDGE is returned by the

X4023x after the Slave Address if received correctly.

Next, an Instruction Byte is issued on SDA. Bits P1-P0 of

the Instruction Byte determine which DCP “wiper posi-

tion” is to be read. In this case, the state of the WT bit is

“don’t care”. If the Instruction Byte format is valid, then

another ACKNOWLEDGE is returned by the X4023x.

2 kbit EEPROM ARRAY

Operations on the 2 kbit EEPROM Array, consist of

either 1, 2 or 3 byte command sequences. All operations

on the EEPROM must begin with the Device Type Iden-

tifier of the Slave Address set to 1010000. A Read or

Write to the EEPROM is selected by setting the LSB of

the Slave Address to the appropriate value R/W

(Read = “1”, Write = ”0”).

Following this ACKNOWLEDGE, the master immedi-

ately issues another START condition and a valid Slave

address byte with the R/W bit set to 1. Then the X4023x

issues an ACKNOWLEDGE followed by Data Byte, and

finally, the master issues a STOP condition. The Data

In some cases when performing a Read or Write to the

EEPROM, an Address Byte may also need to be speci-

fied. This Address Byte can contain the values 00h to

FFh.

WRITE Operation

S

t

Signals from

the Master

S

Address

Byte

Slave

Address

Data

Byte

t

a

r

o

p

t

SDA Bus

0 1

0 0

0

1

0 0

A

C

K

A

C

K

A

C

K

Signals from

the Slave

Internal

Device

Address

Figure 11. EEPROM Byte Write Sequence

FN8115 Rev 0.00

April 11, 2005

Page 14 of 36

X40231, X40233, X40235, X40237, X40239

S

(2 < n < 16)

Signals from

the Master

t

a

r

S

t

o

p

Address

Byte

Slave

Address

Data

(1)

Data

(n)

t

SDA Bus

1 0 1 0 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

Signals from

the Slave

Figure 12. EEPROM Page Write Operation

EEPROM Byte Write

For example, if the master writes 12 bytes to the page

starting at location 11 (decimal), the first 5 bytes are writ-

ten to locations 11 through 15, while the last 7 bytes are

written to locations 0 through 6. Afterwards, the address

counter would point to location 7. If the master supplies

more than 16 bytes of data, then new data overwrites

the previous data, one byte at a time (See Figure 13).

In order to perform an EEPROM Byte Write operation to

the EEPROM array, the Write Enable Latch (WEL) bit of

the CR Register must first be set (See “BL1, BL0: Block

Lock protection bits - (Nonvolatile)” on page 18.)

For a write operation, the X4023x requires the Slave

Address Byte and an Address Byte. This gives the mas-

ter access to any one of the words in the array. After

receipt of the Address Byte, the X4023x responds with

an ACKNOWLEDGE, and awaits the next eight bits of

data. After receiving the 8 bits of the Data Byte, it again

responds with an ACKNOWLEDGE. The master then

terminates the transfer by generating a STOP condition,

at which time the X4023x begins the internal write cycle

to the nonvolatile memory (See Figure 11). During this

internal write cycle, the X4023x inputs are disabled, so it

does not respond to any requests from the master. The

SDA output is at high impedance. A write to a region of

EEPROM memory which has been protected with the

Block-Lock feature (See “BL1, BL0: Block Lock protec-

tion bits - (Nonvolatile)” on page 18.), suppresses the

ACKNOWLEDGE bit after the Address Byte.

The master terminates the Data Byte loading by issuing

a STOP condition, which causes the X4023x to begin

the nonvolatile write cycle. As with the byte write opera-

tion, all inputs are disabled until completion of the inter-

nal write cycle. See Figure 12 for the address,

ACKNOWLEDGE, and data transfer sequence.

Stops and EEPROM Write Modes

Stop conditions that terminate write operations must be

sent by the master after sending at least 1 full data byte

and receiving the subsequent ACKNOWLEDGE signal.

If the master issues a STOP within a Data Byte, or

before the X4023x issues a corresponding ACKNOWL-

EDGE, the X4023x cancels the write operation. There-

fore, the contents of the EEPROM array does not

change.

EEPROM Page Write

EEPROM Array Read Operations

In order to perform an EEPROM Page Write operation to

the EEPROM array, the Write Enable Latch (WEL) bit of

the CR Register must first be set (See “BL1, BL0: Block

Lock protection bits - (Nonvolatile)” on page 18.)

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of

the Slave Address Byte is set to one. There are three

basic read operations: Current EEPROM Address Read,

Random EEPROM Read, and Sequential EEPROM

Read.

The X4023x is capable of a page write operation. It is ini-

tiated in the same manner as the byte write operation;

but instead of terminating the write cycle after the first

data byte is transferred, the master can transmit an

unlimited number of 8-bit bytes. After the receipt of each

byte, the X4023x responds with an ACKNOWLEDGE,

and the address is internally incremented by one. The

page address remains constant. When the counter

reaches the end of the page, it “rolls over” and goes

back to ‘0’ on the same page.

Current EEPROM Address Read

Internally the device contains an address counter that

maintains the address of the last word read incremented

by one. Therefore, if the last read was to address n, the

next read operation would access data from address

FN8115 Rev 0.00

April 11, 2005

Page 15 of 36

X40231, X40233, X40235, X40237, X40239

5 bytes

7 bytes

address

11₁₀

address

15₁₀

address

= 6₁₀

address pointer

ends here

Addr = 7₁₀

Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.

Signals from

the Master

S

t

S

t

o

p

Slave

Address

a

r

t

SDA Bus

1 0 1 0 0 0 0 1

A

C

K

Signals from

the Slave

Data

Figure 14. Current EEPROM Address Read Sequence

n+1. On power-up, the address of the address counter is

undefined, requiring a read or write operation for initial-

ization.

“Current EEPROM Address Read” or “Sequential

EEPROM Read” is once again available (assuming that

no access to a DCP or CR Register occur in the interim).

Upon receipt of the Slave Address Byte with the R/W bit

set to one, the device issues an ACKNOWLEDGE and

then transmits the eight bits of the Data Byte. The mas-

ter terminates the read operation when it does not

respond with an ACKNOWLEDGE during the ninth clock

and then issues a STOP condition (See Figure 14 for the

address, ACKNOWLEDGE, and data transfer

sequence).

Random EEPROM Read

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master

must first perform a “dummy” write operation. The mas-

ter issues the START condition and the Slave Address

Byte, receives an ACKNOWLEDGE, then issues an

Address Byte. This “dummy” Write operation sets the

address pointer to the address from which to begin the

random EEPROM read operation.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read oper-

ation, the master must either issue a STOP condition

during the ninth cycle or hold SDA HIGH during the ninth

clock cycle and then issue a STOP condition.

After the X4023x acknowledges the receipt of the

Address Byte, the master immediately issues another

START condition and the Slave Address Byte with the

R/W bit set to one. This is followed by an ACKNOWL-

EDGE from the X4023x and then by the eight bit word.

Another important point to note regarding the “Current

EEPROM Address Read” , is that this operation is not

available if the last executed operation was an access to

a DCP or the CR Register (i.e.: an operation using the

Device Type Identifier 1010111 or 1010010). Immedi-

ately after an operation to a DCP or CR Register is per-

formed, only a “Random EEPROM Read” is available.

Immediately following a “Random EEPROM Read” , a

FN8115 Rev 0.00

April 11, 2005

Page 16 of 36

X40231, X40233, X40235, X40237, X40239

READ Operation

WRITE Operation

Signals from

the Master

S

t

S

t

o

p

Slave

Address

t

a

r

Slave

Address

Address Byte

a

r

t

SDA Bus

1 0 1 0 0 0 0

0

1 0 1 0 0 0 0

1

A

C

K

A

C

K

A

C

K

Signalsfrom

the Slave

Data

“Dummy” Write

Figure 15. Random EEPROM Address Read Sequence

The master terminates the read operation by not

responding with an ACKNOWLEDGE and instead

issuing a STOP condition (Refer to Figure 15).

the master now responds with an ACKNOWLEDGE,

indicating it requires additional data. The X4023x con-

tinues to output a Data Byte for each ACKNOWL-

EDGE received. The master terminates the read

operation by not responding with an ACKNOWLEDGE

and instead issuing a STOP condition.

A similar operation called “Set Current Address” also

exists. This operation is performed if a STOP is issued

instead of the second START shown in Figure 15. In

this case, the device sets the address pointer to that of

the Address Byte, and then goes into standby mode

after the STOP bit. All bus activity will be ignored until

another START is detected.

The data output is sequential, with the data from

address n followed by the data from address n + 1.

The address counter for read operations increments

through the entire memory contents to be serially read

during one operation. At the end of the address space

the counter “rolls over” to address 00h and the device

continues to output data for each ACKNOWLEDGE

received (Refer to Figure 16).

Sequential EEPROM Read

Sequential reads can be initiated as either a current

address read or random address read. The first Data

Byte is transmitted as with the other modes; however,

Slave

Address

Signals from

the Master

S

A

C

K

A

C

K

A

C

K

t

o

p

SDA Bus

0 0 0 1

A

C

K

Signals from

the Slave

Data

(2)

Data

(n-1)

Data

(1)

Data

(n)

(n is any integer greater than 1)

Figure 16. Sequential EEPROM Read Sequence

FN8115 Rev 0.00

April 11, 2005

Page 17 of 36

X40231, X40233, X40235, X40237, X40239

RWEL: Register Write Enable Latch (Volatile)

CS3

BL0

CS7 CS6

CS4

BL1

CS5

CS2 CS1 CS0

The RWEL bit controls the (CR) Register Write Enable

status of the X4023x. Therefore, in order to write to any

of the bits of the CR Register (except WEL), the RWEL

bit must first be set to “1”. The RWEL bit is a volatile bit

that powers up in the disabled, LOW (“0”) state.

PUP1

NV

V2FS V3FS

RWEL

WEL

PUP0

NV

Bit(s)

Description

Write Enable Latch bit

It must be noted that the RWEL bit can only be set, once

the WEL bit has first been enabled (See "CR Register

Write Operation").

WEL

RWEL

Register Write Enable Latch bit

V2MON Output Flag Status

V3MON Output Flag Status

Sets the Block Lock partition

Sets the Power-on Reset time

V2FS

The RWEL bit will reset itself to the default “0” state, in

one of three cases:

V3FS

BL1 - BL0

—After a successful write operation to any bits of the CR

register has been completed (See Figure 18).

PUP1 - PUP0

NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).

—When the X4023x is powered down.

Figure 17. CR Register Format

—When attempting to write to a Block Lock protected

region of the EEPROM memory (See "BL1, BL0: Block

Lock protection bits - (Nonvolatile)", below).

CONTROL AND STATUS REGISTER

The Control and Status (CR) Register provides the user

with a mechanism for changing and reading the status of

various parameters of the X4023x (See Figure 17).

BL1, BL0: Block Lock protection bits - (Nonvolatile)

The Block Lock protection bits (BL1 and BL0) are used

to:

The CR register is a combination of both volatile and

nonvolatile bits. The nonvolatile bits of the CR register

—Inhibit a write operation from being performed to certain

addresses of the EEPROM memory array

retain their stored values even when V

is powered

CC

down, then powered back up. The volatile bits however,

will always power-up to a known logic state “0” (irrespec-

tive of their value at power-down).

—Inhibit a DCP write operation (changing the “wiper posi-

tion”).

The region of EEPROM memory which is protected /

locked is determined by the combination of the BL1 and

BL0 bits written to the CR register. It is possible to lock

the regions of EEPROM memory shown in the table

below:

A detailed description of the function of each of the CR

register bits follows:

WEL: Write Enable Latch (Volatile)

The WEL bit controls the Write Enable status of the

entire X4023x device. This bit must first be enabled

before ANY write operation (to DCPs, EEPROM mem-

ory array, or the CR register). If the WEL bit is not first

enabled, then ANY proceeding (volatile or nonvolatile)

write operation to DCPs, EEPROM array, as well as the

CR register, is aborted and no ACKNOWLEDGE is

issued after a Data Byte.

Protected Addresses

(Size)

Partition of array

locked

BL1 BL0

0

1

0

1

0

1

None (Default)

Upper 1/4

Upper 1/2

All

C0_h- FF_h(64 bytes)

80_h- FF_h(128 bytes)

00_h- FF_h(256 bytes)

The WEL bit is a volatile latch that powers up in the dis-

abled, LOW (0) state. The WEL bit is enabled / set by

writing 00000010 to the CR register. Once enabled, the

WEL bit remains set to “1” until either it is reset to “0” (by

writing 00000000 to the CR register) or until the X4023x

powers down, and then up again.

If the user attempts to perform a write operation on a

protected region of EEPROM memory, the operation is

aborted without changing any data in the array.

Writes to the WEL bit do not cause an internal high volt-

age write cycle. Therefore, the device is ready for

another operation immediately after a STOP condition is

executed in the CR Write command sequence (See Fig-

ure 18).

FN8115 Rev 0.00

April 11, 2005

Page 18 of 36

X40231, X40233, X40235, X40237, X40239

When the Block Lock bits of the CR register are set to

something other than BL1 = 0 and BL0 = 0, then the

“wiper position” of the DCPs cannot be changed - i.e.

DCP write operations cannot be conducted:

Power-on Reset delay (t_PURESET

)

PUP1

PUP0

0

1

0

1

0

1

50ms

100ms (Default)

200ms

BL1 BL0

DCP Write Operation Permissible

300ms

0

1

0

1

0

1

YES (Default)

The default for these bits are PUP1 = 0, PUP0 = 1.

NO

V2FS, V3FS: Voltage Monitor Status Bits (Volatile)

Bits V2FS and V3FS of the CR register are latched, vol-

atile flag bits which indicate the status of the Voltage

Monitor reset output pins V2FAIL and V3FAIL.

The factory default setting for these bits are BL1 = 0,

BL0 = 0.

IMPORTANT NOTE: If the Write Protect (WP) pin of the

X4023x is active (HIGH), then all nonvolatile write opera-

tions to both the EEPROM memory and DCPs are inhib-

ited, irrespective of the Block Lock bit settings (See "WP:

Write Protection Pin").

At power-up the VxFS (x=2,3) bits default to the value

“0”. These bits can be set to a “1” by writing the appropri-

ate value to the CR register. To provide consistency

between the VxFAIL and V

however, the status of the

xFS

V

bits can only be set to a “1” when the correspond-

xFS

ing VxFAIL output is HIGH.

PUP1, PUP0: Power-on Reset bits – (Nonvolatile)

Once the VxFS bits have been set to “1”, they will be

reset to “0” if:

Applying voltage to V

circuit which holds RESET output HIGH, until the supply

voltage stabilizes above the V threshold for a

activates the Power-on Reset

CC

—The device is powered down, then back up,

TRIP1

period of time, t

(See Figure 30).

PURST

—The corresponding V

output becomes LOW.

xFAIL

The Power-on Reset bits, PUP1 and PUP0 of the CR

register determine the t delay time of the Power-

CR Register Write Operation

PURST

on Reset circuitry (See "VOLTAGE MONITORING

FUNCTIONS"). These bits of the CR register are nonvol-

atile, and therefore power-up to the last written state.

The CR register is accessed using the Slave Address

set to 1010010 (Refer to Figure 4). Following the Slave

Address Byte, access to the CR register requires an

Address Byte which must be set to FFh. Only one data

byte is allowed to be written for each CR register Write

operation. The user must issue a STOP, after sending

this byte to the register, to initiate the nonvolatile cycle

that stores the BP1, BP0, PUP1 and PUP0 bits. The

X4023x will not ACKNOWLEDGE any data bytes written

after the first byte is entered (Refer to Figure 18).

The nominal Power-on Reset delay time can be selected

from the following table, by writing the appropriate bits to

the CR register:

SCL

SDA

CS0

CS2CS1

CS5 CS4 CS3

1

CS7 CS6

S

T

A

R

T

1

0

1

0

1

0

R/W A

1

A

C

K

A

C

K

S

T

O

P

C

K

SLAVE ADDRESS BYTE

ADDRESS BYTE

CR REGISTER DATA IN

Figure 18. CR Register Write Command Sequence

FN8115 Rev 0.00

April 11, 2005

Page 19 of 36

X40231, X40233, X40235, X40237, X40239

Prior to writing to the CR register, the WEL and RWEL

bits must be set using a two step process, with the whole

sequence requiring 3 steps

to the CR register itself, further requires the setting of the

RWEL bit. Block Lock protection of the device enables

the user to inhibit writes to certain regions of the

EEPROM memory, as well as to all the DCPs. One fur-

ther level of data protection in the X4023x, is incorpo-

rated in the form of the Write Protection pin.

—Write a 02H to the CR Register to set the Write Enable

Latch (WEL). This is a volatile operation, so there is no

delay after the write. (Operation preceded by a START

and ended with a STOP).

WP: Write Protection Pin

—Write a 06H to the CR Register to set the Register Write

Enable Latch (RWEL) AND the WEL bit. This is also a

volatile cycle. The zeros in the data byte are required.

(Operation preceded by a START and ended with a

STOP).

When the Write Protection (WP) pin is active (HIGH), it

disables nonvolatile write operations to the X4023x.

The table below (X4023x Write Permission Status) sum-

marizes the effect of the WP pin (and Block Lock), on

the write permission status of the device.

—Write a one byte value to the CR Register that has all the

bits set to the desired state. The CR register can be rep-

resented as qxyst01r in binary, where xy are the Voltage

Monitor Output Status (V2FS and V3FS) bits, st are the

Block Lock Protection (BL1 and BL0) bits, and qr are the

Additional Data Protection Features

In addition to the preceding features, the X4023x also

incorporates the following data protection functionality:

Power-on Reset delay time (t

) control bits (PUP1 -

PURST

—The proper clock count and data bit sequence is required

prior to the STOP bit in order to start a nonvolatile write

cycle.

PUP0). This operation is proceeded by a START and

ended with a STOP bit. Since this is a nonvolatile write

cycle, it will typically take 5ms to complete. The RWEL bit

is reset by this cycle and the sequence must be repeated

to change the nonvolatile bits again. If bit 2 is set to ‘1’ in

this third step (qxys t11r) then the RWEL bit is set, but

the V2FS, V3FS, PUP1, PUP0, BL1 and BL0 bits remain

unchanged. Writing a second byte to the control register

is not allowed. Doing so aborts the write operation and

the X4023x does not return an ACKNOWLEDGE.

VOLTAGE MONITORING FUNCTIONS

V_CCMonitoring

The X4023x monitors the supply voltage and drives the

RESET output HIGH (using an external “pull up” resistor)

if V is lower than V

threshold. The RESET output

CC

TRIP1

will remain HIGH until V exceeds V

for a minimum

CC

TRIP1

For example, a sequence of writes to the device CR reg-

ister consisting of [02H, 06H, 02H] will reset all of the

nonvolatile bits in the CR Register to “0”.

time of t

. After this time, the RESET pin is driven to

PURST

a LOW state. See Figure 30.

For the Power-on / Low Voltage Reset function of the

X4023x, the RESET output may be driven HIGH down to

It should be noted that a write to any nonvolatile bit of

CR register will be ignored if the Write Protect pin of the

X4023x is active (HIGH) (See "WP: Write Protection

Pin").

a V of 1V (V

). See Figure 30. Another feature of

CC

RVALID

the X4023x, is that the value of t

may be selected

PURST

in software via the CR register (See “PUP1, PUP0:

Power-on Reset bits – (Nonvolatile)” on page 19.).

CR (Control) Register Read Operation

It is recommended to stop communication to the device

while RESET is HIGH. Also, setting the Manual Reset

(MR) pin HIGH overrides the Power-on / Low Voltage

circuitry and forces the RESET output pin HIGH (See

"MR: Manual Reset").

The contents of the CR Register can be read at any time

by performing a random read (See Figure 18). Using the

Slave Address Byte set to 10100101, and an Address

Byte of FFh. Only one byte is read by each register read

operation. The X4023x resets itself after the first byte is

read. The master should supply a STOP condition to be

consistent with the bus protocol.

After setting the WEL and / or the RWEL bit(s) to a “1”, a

CR register read operation may o ur, without interrupt-

CC

ing a proceeding CR register write operation.

DATA PROTECTION

There are a number of levels of data protection features

designed into the X4023x. Any write to the device first

requires setting of the WEL bit in the CR register. A write

FN8115 Rev 0.00

April 11, 2005

Page 20 of 36

X40231, X40233, X40235, X40237, X40239

MR: Manual Reset

V_CC

V_TRIP1

The RESET output can be forced HIGH externally using

the Manual Reset (MR) input. MR is a de-bounced, TTL

compatible input, and so it may be operated by connect-

0 Volts

ing a push-button directly from V to the MR pin.

CC

MR

RESET remains HIGH for time t

after MR has

PURST

returned to its LOW state (See Figure 19). An external

“pull down” resistor is required to hold this pin (nor-

mally) LOW.

RESET

0 Volts

t_PURST

Figure 19. Manual Reset Response

READ Operation

WRITE Operation

Signals from the

Master

S

t

S

t

o

p

t

a

r

Slave

Address

Slave

Address

Address Byte

a

r

t

CS7

… CS0

SDA Bus

1 0 1 0 0 1 0

0

1 0 1 0 0 1 0

1

A

C

K

A

C

K

A

C

K

Signals from the

Slave

Data

“Dummy” Write

Figure 20. CR Register Read Command Sequence

X4023x Write Permission Status

Block Lock

Bits

Write to CR Register

Permitted

DCP Volatile Write

Permitted

DCP Nonvolatile

Write Permitted

Write to EEPROM

Permitted

BL0 BL1 WP

Volatile Bits

YES

Nonvolatile Bits

NO

x

1

0

x

1

0

1

x

0

1

x

0

1

NO

YES

NO

YES

NO

YES

NO

0

Not in locked region

Yes (All Array)

YES

0

NO

YES

FN8115 Rev 0.00

April 11, 2005

Page 21 of 36

X40231, X40233, X40235, X40237, X40239

V2MON Monitoring

The X4023x asserts the V2FAIL output HIGH if the volt-

age V2MON exceeds the corresponding V

V_TRIPx

0V

Vx

thresh-

TRIP2

old (See Figure 21). The bit V2FS in the CR register is

then set to a “0” (assuming that it has been set to “1”

after system initialization).

VxFAIL

V_CC

0V

The V2FAIL output may remain active HIGH with V

down to 1V. (See Figure 21)

CC

V_TRIP1

V3MON Monitoring

The X4023x asserts the V3FAIL output HIGH if the volt-

age V3MON exceeds the corresponding V thresh-

0 Volts

(x = 2,3)

TRIP3

Figure 21. Voltage Monitor Response

old (See Figure 21). The bit V3FS in the CR register is

then set to a “0” (assuming that it has been set to “1”

after system initialization).

Setting a V_TRIPxVoltage (x = 1,2,3)

There are two procedures used to set the threshold volt-

ages (V ), depending if the threshold voltage to be

The V3FAIL output may remain active HIGH with V

CC

down to 1V. V

Thresholds (x = 1,2,3)

TRIPx

stored is higher or lower than the present value. For

example, if the present V is 2.9 V and the new

The X4023x is shipped with pre-programmed threshold

(V ) voltages. In applications where the required

thresholds are different from the default values, or if a

higher precision / tolerance is required, the X4023x trip

points may be adjusted by the user, using the steps

detailed below.

TRIPx

V

is 3.2 V, the new voltage can be stored directly

TRIPx

into the V

cell. If however, the new setting is to be

TRIPx

lower than the present setting, then it is necessary to

“reset” the V voltage before setting the new value.

TRIPx

V_TRIPx

V_CC

V2MON,

V3MON

V_P

WP

0

1 2 3 4 5 6 7

0

1 2 3 4 5 6 7

0

1 2 3 4 5 6 7

SCL

00h

Data Byte ^†

SDA

†

01h^†sets V_TRIP1

09h^†sets V_TRIP2

0Dh^†sets V_TRIP3

A0h

S

T

A

R

T

^†All others Reserved.

Figure 22. Setting V

to a higher level (x = 1,2,3).

TRIPx

FN8115 Rev 0.00

April 11, 2005

Page 22 of 36

X40231, X40233, X40235, X40237, X40239

After being reset, the value of V

value of 1.7V.

becomes a nominal

thresholds are set,

Setting a Higher V_TRIPxVoltage (x = 1,2,3)

TRIPx

To set a V

threshold to a new voltage which is higher

TRIPx

than the present threshold, the user must apply the

desired V threshold voltage to the corresponding

V_TRIPxAccuracy (x = 1,2,3).

The accuracy with which the V

TRIPx

input pin (V , V2MON or V3MON). Then, a program-

CC

TRIPx

ming voltage (Vp) must be applied to the WP pin before a

START condition is set up on SDA. Next, issue on the

SDA pin the Slave Address A0h, followed by the Byte

can be controlled using the iterative process shown in

Figure 24.

If the desired threshold is less that the present threshold

voltage, then it must first be “reset” (See "Resetting the

Address 01h for V

, 09h for V

, and 0Dh for

TRIP1

TRIP2

V

, and a 00h Data Byte in order to program V

.

TRIP3

TRIPx

V

Voltage (x = 1,2,3).").

TRIPx

The STOP bit following a valid write operation initiates the

programming sequence. Pin WP must then be brought

LOW to complete the operation (See Figure 23). The user

does not have to set the WEL bit in the CR register before

performing this write sequence.

The desired threshold voltage is then applied to the

appropriate input pin (V , V2MON or V3MON) and the

CC

procedure described in Section “Setting a Higher V

Voltage“ must be followed.

TRIPx

Setting a Lower V

Voltage (x = 1,2,3).

TRIPx

Once the desired V

threshold has been set, the

TRIPx

error between the desired and (new) actual set threshold

In order to set V

to a lower voltage than the present

must first be “reset” according to the

TRIPx

can be determined. This is achieved by applying V to

CC

value, then V

TRIPx

the device, and then applying a test voltage higher than

the desired threshold voltage, to the input pin of the volt-

procedure described below. Once V

has been

TRIPx

“reset”, then V

can be set to the desired voltage

TRIPx

age monitor circuit whose V

was programmed. For

TRIPx

using the procedure described in “Setting a Higher

Voltage”.

example, if V

was set to a desired level of 3.0 V,

TRIP2

V

TRIPx

then a test voltage of 3.4 V may be applied to the voltage

monitor input pin V2MON. In the case of setting of

Resetting the V_TRIPxVoltage (x = 1,2,3).

V

then only V need be applied. In all cases, care

TRIP1

CC

To reset a V

voltage, apply the programming volt-

TRIPx

should be taken not to exceed the maximum input volt-

age limits.

age (Vp) to the WP pin before a START condition is set

up on SDA. Next, issue on the SDA pin the Slave

Address A0h followed by the Byte Address 03h for

After applying the test voltage to the voltage monitor

input pin, the test voltage can be decreased (either in

discrete steps, or continuously) until the output of the

voltage monitor circuit changes state. At this point, the

error between the actual/measured, and desired thresh-

old levels is calculated.

V

, 0Bh for V

, and 0Fh for V

, followed by

TRIP1

TRIP2

TRIP3

00h for the Data Byte in order to reset V

. The STOP

TRIPx

bit following a valid write operation initiates the program-

ming sequence. Pin WP must then be brought LOW to

complete the operation (See Figure 23). The user does

not have to set the WEL bit in the CR register before per-

forming this write sequence.

V_P

WP

0

1

2 3

4

5 6

7

0

1 2 3 4 5 6 7

0

1 2 3 4 5 6 7

SCL

00h ^†

Data Byte

SDA

A0h^†

03h^†Resets VTRIP1

0Bh^†Resets VTRIP2

0Fh^†Resets VTRIP3

S

T

A

R

T

^†All others Reserved.

Figure 23. Resetting the V

Level

TRIPx

FN8115 Rev 0.00

April 11, 2005

Page 23 of 36

X40231, X40233, X40235, X40237, X40239

For example, the desired threshold for V

is set to 3.0

culated error. If it is the case that the error is less than

zero, then the V must be programmed to a value

TRIP2

V, and a test voltage of 3.4 V was applied to the input pin

TRIPx

V2MON (after applying power to V ). The input voltage is

equal to the previously set V

plus the absolute

CC

TRIPx

decreased, and found to trip the associated output level of

pin V2FAIL from a LOW to a HIGH, when V2MON reaches

3.09 V. From this, it can be calculated that the program-

ming error is 3.09 - 3.0 = 0.09 V.

value of the calculated error.

Continuing the previous example, we see that the calcu-

lated error was 0.09V. Since this is greater than zero, we

must first “reset” the V

threshold, then apply a volt-

TRIP2

If the error between the desired and measured V

is

age equal to the last previously programmed voltage,

minus the last previously calculated error. Therefore, we

TRIPx

less than the maximum desired error, then the program-

ming process may be terminated. If however, the error is

greater than the maximum desired error, then another

must apply V

= 2.91 V to pin V2MON and execute

TRIP2

the programming sequence (See "Setting a Higher

V Voltage (x = 1,2,3)").

TRIPx

iteration of the V

programming sequence can be per-

TRIPx

formed (using the calculated error) in order to further

increase the accuracy of the threshold voltage.

Using this process, the desired accuracy for a particular

threshold may be attained using a successive

V

TRIPx

If the calculated error is greater than zero, then the

number of iterations.

V

must first be “reset”, and then programmed to the

TRIPx

a value equal to the previously set V

minus the cal-

TRIPx

Note: X = 1,2,3.

V_TRIPxProgramming

Let: MDE = Maximum Desired Error

NO

MDE⁺

Desired V_TRIPx

present value?

<

Acceptable

Desired Value

Error Range

MDE^–

YES

Execute

V_TRIPxReset

Sequence

Error = Actual – Desired

Set Vx = desired V_TRIPx

Execute

Set Higher V_TRIPx

Sequence

New Vx applied =

Old Vx applied + | Error |

Old Vx applied - | Error |

Execute

Reset V_TRIPx

Sequence

Power-down

Ramp up Vx

NO

Output

switches?

YES

Error < MDE^–

Error >MDE⁺

Actual V_TRIPx

- Desired V_TRIPx

= Error

| Error | < | MDE |

DONE

Figure 24. V

Setting / Reset Sequence (x = 1,2,3)

TRIPx

FN8115 Rev 0.00

April 11, 2005

Page 24 of 36

X40231, X40233, X40235, X40237, X40239

ABSOLUTE MAXIMUM RATINGS

Parameter

Min.

-65

Max.

+135

+150

+15

+7

Units

°C

V

Temperature under Bias

Storage Temperature

-65

Voltage on WP pin (With respect to VSS)

Voltage on other pins (With respect to VSS)

-1.0

V

Voltage on R

- Voltage on R (x = 0,1,2. Referenced to V

Lx

)

V_CC

5

V

Hx

SS

D.C. Output Current (SDA,RESETRESET,V2FAIL,V3FAIL)

Lead Temperature (Soldering, 10 seconds)

0

mA

°C

V

300

7

Supply Voltage Limits (Applied V_CCvoltage, referenced to V_SS

)

2.7

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Units

Industrial

-40

+85

°C

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only

and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specifica-

tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 25. Equivalent A.C. Circuit

V_CC= 5V

2300

SDA

V2FAIL

V3FAIL

RESET

100pF

Figure 26. DCP SPICE Macromodel

R_TOTAL

R_Hx

R_Lx

C_L

C_H

10pF

R_W

C_W

10pF

25pF

(x = 0,1,2)

R_Wx

FN8115 Rev 0.00

April 11, 2005

Page 25 of 36

X40231, X40233, X40235, X40237, X40239

TIMING DIAGRAMS

Figure 27. Bus Timing

t_F

t_HIGH

t_LOW

t_R

SCL

t_SU:DAT

t_SU:STA

t_HD:DAT

t_SU:STO

t_HD:STA

SDA IN

t_AAt_DH

t_BUF

SDA OUT

Figure 28. WP Pin Timing

START

SCL

Clk 1

Clk 9

SDA IN

WP

t_SU:WP

t_HD:WP

Figure 29. Write Cycle Timing

SCL

8th bit of last byte

ACK

SDA

t_WC

Stop

Condition

Start

Condition

FN8115 Rev 0.00

April 11, 2005

Page 26 of 36

X40231, X40233, X40235, X40237, X40239

Figure 30. Power-Up and Power-Down Timing

t_F

t_R

V_CC

V_TRIP1

0 Volts

t_PURST

t_RPD

RESET

0 Volts

MR

0 Volts

Figure 31. Manual Reset Timing Diagram

MR

t_MRPW

0 Volts

t_PURST

t_MRD

RESET

0 Volts

V_CC

V_TRIP1

V

CC

Figure 32. V2MON, V3MON Timing Diagram

t_Rx

t_Fx

Vx

V_TRIPx

t_RPDx

0 Volts

t_RPDx

VxFAIL

0 Volts

V_TRIP1

V_CC

V_RVALID

0 Volts

Note : x = 2,3.

FN8115 Rev 0.00

April 11, 2005

Page 27 of 36

X40231, X40233, X40235, X40237, X40239

Figure 33. V

Programming Timing Diagram (x=1,2,3).

TRIPX

V_CC, V2MON, V3MON

V_TRIPx

t_TSU

t_THD

V_P

WP

t

VPS

t_VPO

SCL

SDA

t_WC

00h

t_VPH

NOTE : V1/V_CCmust be greater than V2MON, V3MON when programming.

Figure 34. DCP “Wiper Position” Timing

Rwx (x=0,1,2)

R_WX(n+1)

R_WX(n-1)

R_WX(n)

t_WR

Time

n = tap position

SCL

SDA

1

0

1

0

1

0

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

S

T

A

R

T

A WT

0

P1 P0

A

C

K

A

C

K

S

T

C

K

O

P

SLAVE ADDRESS BYTE

INSTRUCTION BYTE

FN8115 Rev 0.00

April 11, 2005

Page 28 of 36

X40231, X40233, X40235, X40237, X40239

D.C. OPERATING CHARACTERISTICS

Symbol

Parameter

Min Typ

Max

Unit

Test Conditions / Notes

Requires V_CC> V_TRIP1or chip will

not operate.

V_CC

2.7

5.5

V

Current into V

Read memory array ⁽³⁾

Pin (X4023x: Active)

CC

(1)

I

f

_SCL= 400KHz

V_SDA= V

1

2

CC

0.4

1.5

mA

Write nonvolatile memory V_CC= 3.5V

CC

Current into V

Pin (X4023x:Standby)

CC

MR = VSS

With 2-Wire bus activity ⁽³⁾

No 2-Wire bus activity

V_CC= 3.5V

(2)

A

WP = VSS or Open/Floating

CC

50.0

V_SCL= V (when no bus

CC

activity else f_SCL= 400kHz)

Input Leakage Current (SCL, SDA, MR)

Input Leakage Current (WP)

0.1

10

A

V_IN⁽⁴⁾= GND to V

.

CC

I_LI

V_OUT⁽⁵⁾= GND to V

X4023x is in Standby⁽²⁾

Output Leakage Current (SDA, RESET,

V2FAIL, V3FAIL)

.

CC

I_LO

10

A

V_TRIP1PR

V_TRIP1Programming Range

2.75

1.75

4.70

3.50

V

Programming Range (x = 2,3)

PR

TRIPx

Factory shipped default option A

Factory shipped default option B

2.8

4.3

2.95

4.45

3.00

4.50

(6)

V_TRIP1

Pre - programmed V_TRIP1threshold

Pre - programmed V_TRIP2threshold

Pre - programmed V_TRIP3threshold

V

Factory shipped default option A

Factory shipped default option B

2.05 2.20

2.8 2.95

2.25

3.00

V_TRIP2

V_TRIP3

Factory shipped default option A

Factory shipped default option B

1.60 1.75

1.80

V

, V2MON, V3MON to RESET,

CC

See ⁽⁸⁾

t_RPDx

V2FAIL, V3FAIL propagation

delay (respectively)

20

s

V2MON Input leakage current

V3MON Input leakage current

V_SDA= V_SCL= V

CC

1

I_Vx

A

V

Others = GND or V

CC

(7)

V_IL

Input LOW Voltage (SCL, SDA, WP, MR)

-0.5

2.0

0.8

V

CC

+0.5

(7)

V_IH

Input HIGH Voltage (SCL,SDA, WP, MR)

V

RESET, V2FAIL, V3FAIL, SDA Output

Low Voltage

V_OLx

0.4

V

I_SINK= 2.0mA

Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200nS after a STOP ending a read operation; or t_WCafter a STOP ending a write operation.

Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t_WCafter a STOP that initiates

a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.

Notes: 3. Current through external pull up resistor not included.

Notes: 4. V_IN= Voltage applied to input pin.

Notes: 5. V_OUT= Voltage applied to output pin.

Notes: 6. See “ORDERING INFORMATION” on page 36.

Notes: 7. V_ILMin. and V_IHMax. are for reference only and are not tested

Notes: 8. Equivalent input circuit for V_XMON

V

XMON

+

–

V

REF

FN8115 Rev 0.00

April 11, 2005

Page 29 of 36

X40231, X40233, X40235, X40237, X40239

A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29)

400kHz

Symbol

f_SCL

Parameter

Min

0

Max

Units

kHz

ns

SCL Clock Frequency

400

(5)

t_IN

Pulse width Suppression Time at inputs

SCL LOW to SDA Data Out Valid

Time the bus free before start of new transmission

Clock LOW Time

50

t_AA

0.1

1.3

0.6

100

0

0.9

s

t_BUF

s

t_LOW

s

t_HIGH

Clock HIGH Time

s

t_SU:STA

t_HD:STA

t_SU:DAT

t_HD:DAT

t_SU:STO

t_DH

Start Condition Setup Time

Start Condition Hold Time

Data In Setup Time

s

ns

Data In Hold Time

s

Stop Condition Setup Time

Data Output Hold Time

0.6

50

s

ns

(5)

20 +.1Cb⁽²⁾

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

WP Setup Time

300

ns

(5)

20 +.1Cb⁽²⁾

t_F

ns

s

pF

t_SU:WP

t_HD:WP

Cb

0.6

0

WP Hold Time

Capacitive load for each bus line

400

A.C. TEST CONDITIONS

Input Pulse Levels

0.1V

to 0.9V

CC

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

10ns

0.5V

CC

See Figure 25

NONVOLATILE WRITE CYCLE TIMING

Symbol

Parameter

Nonvolatile Write Cycle Time

Min.

Typ.⁽¹⁾

Max.

Units

(4)

t_WC

5

10

ms

CAPACITANCE (T = 25°C, F = 1.0 MHZ, V = 5V)

A

CC

Symbol

Parameter

Max

8

Units

Test Conditions

(5)

V_OUT= 0V

C_OUT

Output Capacitance (SDA, RESET, V2FAIL, V3FAIL)

Input Capacitance (SCL, WP, MR)

pF

(5)

V_IN= 0V

C_IN

6

Notes: 1. Typical values are for T_A= 25°C and V_CC= 5.0V

Notes: 2. Cb = total capacitance of one bus line in pF.

Notes: 3. Over recommended operating conditions, unless otherwise specified

Notes: 4. t_WCis the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Notes: 5. This parameter is not 100% tested.

FN8115 Rev 0.00

April 11, 2005

Page 30 of 36

X40231, X40233, X40235, X40237, X40239

POTENTIOMETER CHARACTERISTICS

Limits

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions/Notes

In a ratiometric circuit, R_TOTAL

divides out of the equation and

accuracy is determined by XDCP

resolution.

R_TOL

End to End Resistance Tolerance

-20

+20

%

V

V_RHx

V_RLx

R_HTerminal Voltage (x = 0,1,2)

R_LTerminal Voltage (x = 0,1,2)

VSS

V

CC

VSS

10

V

R_LTerminal internally tied to gnd.

R_TOTAL= 10kDCP0, DCP1)

R_TOTAL= 100kDCP2)

mW

P_R

Power Rating⁽¹⁾

5

V

= 5 V, V_RHx= V

_RLx= VSS (x = 0,1,2),

,

CC

200

400



I

_W= 50 uA /500 uA (100/10k.

R_W

DCP Wiper Resistance

V

= 2.7 V, V_RHx= V

,

CC

_RLx= VSS (x = 0,1,2),

1200

4.4



I_W= 27 uA /270 uA (100/10 k.

I_W

Wiper Current

Noise

mA

mV

(Hz)

R_TOTAL= 10kDCP0, DCP1)

mV

(Hz)

R_TOTAL= 100kDCP2)

Absolute Linearity⁽²⁾

Relative Linearity⁽³⁾

-1

+1

R_w(n)(actual)- R_{w(n)(expected)}

MI⁽⁴⁾

R_w(n+1)- [R_{w(n) + MI}

]

±300

ppm/°C

R_TOTAL= 10kDCP0, DCP1)

R_TOTAL= 100kDCP2)

R_TOTALTemperature Coefficient

Ratiometric Temperature

Coefficient

±30

200

ppm/°C

pF

(Voltage divider configuration)

Potentiometer Capacitances

C_H/C_L/

C_W

10/10/25

See Figure 26.

See Figure 34.

t_wr

Wiper Response time

s

Notes: 1. Power Rating between the wiper terminal R

and the end terminals R

V_SS- for ANY tap position n, (x = 0,1,2).

HX

WX(n)

Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R

(actual) - R (expected)) = ±1

wx(n) wx(n)

Ml Maximum (x = 0,1,2).

Notes: 3. Relative Linearity is a measure of the error in step size between taps = R

- [R

+ Ml] = ±0.2 Ml (x = 0,1,2)

wx(n)

Wx(n+1)

Notes: 4. 1 Ml = Minimum Increment = R

TOT

/ (Number of taps in DCP - 1).

Notes: 5. Typical values are for T_A= 25°C and nominal supply voltage.

Notes: 6. This parameter is periodically sampled and not 100% tested.

FN8115 Rev 0.00

April 11, 2005

Page 31 of 36

X40231, X40233, X40235, X40237, X40239

(X = 1,2,3) PROGRAMMING PARAMETERS (See Figure 33)

V

TRIPX

Parameter

Description

V_TRIPxProgram Enable Voltage Setup time

V_TRIPxProgram Enable Voltage Hold time

V_TRIPxSetup time

Min

10

Typ

Max

Units

s

t_VPS

t_VPH

t_TSU

t_THD

10

s

10

s

V_TRIPxHold (stable) time

10

s

V_TRIPxProgram Enable Voltage Off time

(Between successive adjustments)

t_VPO

1

ms

t_WC

V_P

V_TRIPxWrite Cycle time

Programming Voltage

5

10

15

ms

V

10

V_TRIPxProgram Voltage accuracy

Programmed at 25°C.)

V_ta

V_tv

-100

+100

+25

mV

V_TRIPProgram variation after programming (-40 - 85°C).

(Programmed at 25°C.)

-25

+10

Notes:

100% tested.

RESET, V2FAIL, V3FAIL OUTPUT TIMING. (See Figure 30, Figure 31, Figure 32)

Symbol

Description

Condition

Min.

25

Typ.

50

Max.

Units

ms

s

PUP1 = 0, PUP0 = 0

PUP1 = 0, PUP0 = 1

PUP1 = 1, PUP0 = 0

PUP1 = 1, PUP0 = 1

75

150

300

450

5

50

100

200

300

t_PURST

Power-on Reset delay time

100

150

(31)(2)

See ^(1)(2)(4)

t_MRD

t_MRDPW

MR to RESET propagation delay

MR pulse width

500

ns

V

, V2MON, V3MON to RESET,

CC

See ⁽⁵⁾

t_RPDx

V2FAIL, V3FAIL propagation

delay (respectively)

20

s

t_Fx

t_Rx

V

, V2MON, V3MON Fall Time

, V2MON, V3MON Rise Time

for RESET, V2FAIL, V3FAIL

20

mV/s

CC

V_RVALID

1

V

Valid⁽³⁾

.

Notes: 1. See Figure 31 for timing diagram.

Notes: 2. See Figure 25 for equivalent load.

Notes: 3. This parameter describes the lowest possible V_CClevel for which the outputs RESET, V2FAIL, and V3FAIL will be correct with respect to

their inputs (V_CC, V2MON, V3MON).

Notes: 4. From MR rising edge crossing V_IH, to RESET rising edge crossing V_OH

Notes: 5. Equivalent input circuit for V_XMON

.

V

XMON

+

–

OUTPUT

V

REF

t

= 20µs worst case

RPDX

FN8115 Rev 0.00

April 11, 2005

Page 32 of 36

X40231, X40233, X40235, X40237, X40239

APPENDIX 1

DCP1 (100 Tap) Tap position to Data Byte translation Table

Data Byte

Tap

Position

Decimal

Binary

0

1

0

1

0000 0000

0000 0001

.

23

24

25

26

23

24

56

55

0001 0111

0001 1000

0011 1000

0011 0111

.

48

49

50

51

33

32

64

65

0010 0001

0010 0000

0100 0000

0100 0001

.

73

74

75

76

87

88

0101 0111

0101 1000

0111 1000

0111 0111

120

119

.

98

99

97

96

0110 0001

0110 0000

FN8115 Rev 0.00

April 11, 2005

Page 33 of 36

X40231, X40233, X40235, X40237, X40239

APPENDIX 2

DCP1 (100 Tap) tap position to Data Byte translation algorithm example.

unsigned DCP1_TAP_Position(int tap_pos)

{

int block;

int i;

int offset;

int wcr_val;

offset = 0;

block = tap_pos / 25;

if (block < 0) return ((unsigned)0);

else if (block <= 3)

{

switch(block)

{ case (0): return ((unsigned)tap_pos) ;

case (1):

{

wcr_val = 56;

offset = tap_pos - 25;

for (i=0; i<= offset; i++) wcr_val-- ;

return ((unsigned) wcr_val);

}

case (2):

{

wcr_val = 64;

offset = tap_pos - 50;

for (i=0; i<= offset; i++) wcr_val++ ;

return ((unsigned) wcr_val);

}

case (3):

{

wcr_val = 120;

offset = tap_pos - 75;

for (i=0; i<= offset; i++) wcr_val-- ;

return ((unsigned) wcr_val);

}

return((unsigned)01100000);

}

FN8115 Rev 0.00

April 11, 2005

Page 34 of 36

X40231, X40233, X40235, X40237, X40239

16-Lead Plastic, SOIC (300-mil body), Package Code S16

0.290 (7.37)

0.299 (7.60)

0.393 (10.00)

0.420 (10.65)

PIN 1 INDEX

PIN 1

0.014 (0.35)

0.020 (0.51)

0.403 (10.2 )

0.413 ( 10.5)

(4X) 7°

0.092 (2.35)

0.105 (2.65)

0.003 (0.10)

0.012 (0.30)

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

0.050" Typical

X 45

0 - 8 

0.050"

Typical

0.0075 (0.19)

0.010 (0.25)

0.420"

0.015 (0.40)

0.050 (1.27)

0.030" Typical

16 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8115 Rev 0.00

April 11, 2005

Page 35 of 36

X40231, X40233, X40235, X40237, X40239

ORDERING INFORMATION

X4023x

y

-

P

T

Preset (Factory Shipped) V

Levels (x = 1,2,3)

A = Optimized for 3.3 V system monitoring

3.3 ±10%, 2.5 ±10%, 1.8 V +10%/-0%

B = Optimized for 5 V system monitoring

5.0 ±10%, 3.3 ±10%, 1.8 V +10%/-0%

Temperature Range

Threshold

TRIPx

Device

†

x

1

3

5

7

9

DEVICE

X40231

X40233

X40235

X40237

X40239

†

I = Industrial -40C to +85C

Package

S16 = 16-Lead Widebody SOIC (300 mil)

†

For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8115 Rev 0.00

April 11, 2005

Page 36 of 36


型号：	X40233S16I-B
厂家：	RENESAS TECHNOLOGY CORP
描述：	3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, 0.300 INCH, PLASTIC, SOIC-16 光电二极管
文件：	总36页 (文件大小：1292K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X40233S16I-B [RENESAS]

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