X40431V14-CT1 [RENESAS]
3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, PLASTIC, MO-153AC, TSSOP-14;
| 型号： | X40431V14-CT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, PLASTIC, MO-153AC, TSSOP-14 输入元件 光电二极管 |
| 文件： | 总26页 (文件大小：992K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X40430, X40431, X40434, X40435
4Kbit EEPROM Triple Voltage Monitor with Integrated CPU Superviso
FN8251
Rev 1.00
May 24, 2006
FEATURES
DESCRIPTION
• Monitoring voltages: 5V to 9V
The X40430, X40431, X40434, X40435 combines
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision,
• Independent core voltage monitor
• Triple voltage detection and reset assertion
—Standard reset threshold settings. See selec-
tion table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
™
manual reset, and Block Lock protect serial EEPROM
in one package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
—Reset signal valid to V = 1V
CC
Applying voltage to V
activates the power-on reset
CC
—Monitor three separate voltages
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• Memory security
Low V detection circuitry protects the user’s system
from low voltage conditions, resetting the system
CC
when V
falls below the minimum V
point.
CC
TRIP1
RESET/RESET is active until V
returns to proper
CC
operating level and stabilizes. A second and third volt-
age monitor circuit tracks the unregulated supply to
provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available. However, Intersil’s unique
circuits allows the threshold for either voltage monitor
to be reprogrammed to meet specific system level
requirements or to fine-tune the threshold for applica-
tions requiring higher precision.
• 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14 Ld SOIC, TSSOP
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communication equipment
—Routers, hubs, switches
—Disk arrays, network storage
• Industrial systems
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
—Process control
—Intelligent instrumentation
• Computer systems
—Computers
—Network servers
2
allowing operation on an I C bus.
™
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
FN8251 Rev 1.00
May 24, 2006
Page 1 of 26
X40430, X40431, X40434, X40435
BLOCK DIAGRAM
+
-
V3MON
V2MON
V3FAIL
V2FAIL
VTRIP3
V3 Monitor
Logic
V
or
CC
V2MON*
+
-
V2 Monitor
Logic
VTRIP2
Watchdog
and
Fault Detection
Register
Data
SDA
WDO
MR
Reset Logic
Register
Status
Register
WP
Command
Decode Test
& Control
Logic
EEPROM
Array
SCL
RESET
Power-on,
Manual Reset
Low Voltage
Reset
X40430/34
RESET
+
V
CC
X40431/35
VTRIP1
Generation
(V1MON)
V
Monitor
*X40430, X40431=
V2MON
X40434, X40435 =
CC
-
LOWLINE
Logic
V
CC
Expected System
Voltages
POR
(system)
Device
Vtrip1(V)
Vtrip2(V)
Vtrip3(V)
X40430, X40431
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.95–3.05*
1.70–4.75
2.85–2.95
2.55–2.65
2.15–2.25
1.70–4.75
1.65–1.75
1.65–1.75
1.65–1.75
-A
-B
-C
5V; 3V or 3.3V; 1.8V
5V; 3V; 1.8V
3.3V; 2.5V; 1.8V
RESET = X40430
RESET = X40431
X40434, X40435
2.0–4.75*
4.55–4.65*
4.55–4.65*
4.55–4.65*
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
1.70–4.75
3.05–3.15
2.85–2.95
2.85–2.95
-A
-B
-C
5V; 3.3V; 1.5V
5V; 3V or 3.3V; 1.5V
5V; 3 or 3.3V; 1.2V
RESET = X40434
RESET = X40435
*Voltage monitor requires Vcc to operate. Others are independent of Vcc.
FN8251 Rev 1.00
May 24, 2006
Page 2 of 26
X40430, X40431, X40434, X40435
Ordering Information
PART
MONITORED
VTRIP1
VTRIP2
VTRIP3
TEMP.
PKG.
PART NUMBER*
MARKING
VCC RANGE
RANGE
RANGE
RANGE
RANGE (°C)
PACKAGE
DWG. #
PART NUMBER WITH RESET
X40430S14-C
X40430S14I-C
X40430V14-C
X40430S C
X40430S IC
X4043 0VC
1.7 to 3.6
2.9V ±50mV 2.2V ±50mV 1.7V ±50mV
0 to 70
14 Ld SOIC (150 mil) M14.15
-40 to +85 14 Ld SOIC (150 mil) M14.15
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
X40430V14I-C
X40430S14-B
X4043 0VIC
-40 to +85 14 Ld TSSOP
(4.4mm)
M14.173
X40430S B
1.7 to 5.5
4.4V ±50mV 2.6V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40430S14Z-B
(Note)
X40430S ZB
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40430S14I-B
X40430S IB
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40430S14IZ-B
(Note)
X40430S ZIB
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40430V14-B
X4043 0VB
X40430V ZB
X4043 0VIB
X40430V ZIB
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
M14.173
X40430V14Z-B
(Note)
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
X40430V14I-B
-40 to +85 14 Ld TSSOP
(4.4mm)
X40430V14IZ-B
(Note)
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
X40434S14-C
X40434S14I-C
X40434V14-C
X40434S C
X40434S IC
X40434V C
1.0 to 5.5
4.6V ±50mV 1.0V ±50mV 2.9V ±50mV
0 to 70
14 Ld SOIC (150 mil) M14.15
-40 to +85 14 Ld SOIC (150 mil) M14.15
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
X40434V14I-C
X40434V IC
-40 to +85 14 Ld TSSOP
(4.4mm)
X40434S14-B
X40434S B
1.3 to 5.5
1.3 to 5.5
1.3V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40434S14Z-B
(Note)
X40434S ZB
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40434S14I-B
X40434S IB
1.3 to 5.5
1.3 to 5.5
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40434S14IZ-B
(Note)
X40434S ZIB
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40434V14-B
X40434V B
1.3 to 5.5
1.3 to 5.5
1.3 to 5.5
1.3 to 5.5
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
M14.173
X40434V14Z-B
(Note)
X40434V ZB
X40434V IB
X4043 4V ZIB
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
X40434V14I-B
-40 to +85 14 Ld TSSOP
(4.4mm)
X40434V14IZ-B
(Note)
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
X40434S14-A
X40434S A
1.3 to 5.5
1.3 to 5.5
3.1V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40434S14Z-A
(Note)
X40434S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40434S14I-A
X40434S IA
1.3 to 5.5
1.3 to 5.5
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40434S14IZ-A
(Note)
X40434S ZIA
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
FN8251 Rev 1.00
May 24, 2006
Page 3 of 26
X40430, X40431, X40434, X40435
Ordering Information (Continued)
PART
MONITORED
VTRIP1
VTRIP2
VTRIP3
TEMP.
PKG.
PART NUMBER*
MARKING
V
CC RANGE
RANGE
RANGE
RANGE
RANGE (°C)
PACKAGE
DWG. #
X40434V14-A
X40434V A
X40434V ZA
X40434V IA
X40434VZIA
1.3 to 5.5
4.6V ±50mV 1.3V ±50mV 3.1V ±50mV
0 to 70
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
M14.173
X40434V14Z-A
(Note)
14 Ld TSSOP
(4.4mm) (Pb-free)
X40434V14I-A
-40 to +85 14 Ld TSSOP
(4.4mm)
X40434V14IZ-A
(Note)
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
X40430S14-A
X40430S A
1.7 to 5.5
2.9V ±50mV 1.7V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40430S14Z-A
(Note)
X40430S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40430S14I-A
X40430S IA
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40430S14IZ-A
(Note)
X40430S ZIA
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40430V14-A
X4043 0VA
X40430V ZA
X4043 0VIA
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
X40430V14Z-A
(Note)
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
X40430V14I-A
-40 to +85 14 Ld TSSOP
(4.4mm)
X40430V14IZ-AT1 X4043 0VZIA
(Note)
-40 to +85 14 Ld TSSOP Tape M14.173
and Reel (4.4mm)
(Pb-free)
PART NUMBER WITH RESET
X40431S14-C
X40431S14I-C
X40431V14-C
X40431S C
X40431S IC
X40431V C
1.7 to 3.6
2.9V ±50mV 2.2V ±50mV 1.7V ±50mV
0 to 70
14 Ld SOIC (150 mil) M14.15
-40 to +85 14 Ld SOIC (150 mil) M14.15
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
X40431V14I-C
X40431S14-B
X40431 IC
-40 to +85 14 Ld TSSOP
(4.4mm)
X40431S B
1.7 to 5.5
4.4V ±50mV 2.6V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40431S14Z-B
(Note)
X40431S ZB
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40431S14I-B
X40431S IB
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40431S14IZ-B
(Note)
X40431S ZIB
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40431V14-B
X40431V B
X40431V ZB
X40431V IB
X40431V ZIB
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
M14.173
X40431V14Z-B
(Note)
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
X40431V14I-B
-40 to +85 14 Ld TSSOP
(4.4mm)
X40431V14IZ-B
(Note)
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
X40435S14-C
X40435S14I-C
X40435V14-C
X40435 C
X40435 IC
X40435 C
1.0 to 5.5
4.6V ±50mV 1.0V ±50mV 2.9V ±50mV
0 to 70
14 Ld SOIC (150 mil) M14.15
-40 to +85 14 Ld SOIC (150 mil) M14.15
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
X40435V14I-C
X40435 IC
-40 to +85 14 Ld TSSOP
(4.4mm)
FN8251 Rev 1.00
May 24, 2006
Page 4 of 26
X40430, X40431, X40434, X40435
Ordering Information (Continued)
PART
MONITORED
VTRIP1
VTRIP2
VTRIP3
TEMP.
PKG.
PART NUMBER*
MARKING
V
CC RANGE
RANGE
RANGE
RANGE
RANGE (°C)
PACKAGE
DWG. #
X40435S14-B
X40435 B
1.3 to 5.5
4.6V ±50mV 1.3V ±50mV 2.9V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40435S14Z-B
(Note)
X40435S ZB
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40435S14I-B
X40435 IB
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40435S14IZ-B
(Note)
X40435S ZIB
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40435V14-B
X40435 B
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
M14.173
X40435V14Z-B
(Note)
X40435V ZB
X40435 IB
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
X40435V14I-B
-40 to +85 14 Ld TSSOP
(4.4mm)
X40435V14IZ-B
(Note)
X40435V ZIB
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
X40435S14-A
X40435 A
3.1V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40435S14Z-A
(Note)
X40435S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40435S14I-A
X40435 IA
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40435S14IZ-A
(Note)
X40435S ZIA
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40435V14-A
X40435 A
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
M14.173
X40435V14Z-A
(Note)
X40435V ZA
X40435 IA
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
X40435V14I-A
-40 to +85 14 Ld TSSOP
(4.4mm)
X40435V14IZ-A
(Note)
X40435V ZIA
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
X40431S14-A
X40431S A
1.7 to 5.5
2.9V ±50mV 1.7V ±50mV
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
X40431S14Z-A
(Note)
X40431S ZA
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40431S14I-A
X40431S IA
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40431S14IZ-A
(Note)
X40431S ZIA
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40431V14-A
X40431V A
X40431V ZA
X40431V IA
X40431V ZIA
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
M14.173
M14.173
X40431V14Z-A
(Note)
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
X40431V14I-A
-40 to +85 14 Ld TSSOP
(4.4mm)
X40431V14IZ-A
(Note)
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8251 Rev 1.00
May 24, 2006
Page 5 of 26
X40430, X40431, X40434, X40435
PIN CONFIGURATION
X40431, X40435
14 Ld SOIC, TSSOP
X40430, X40434
14 Ld SOIC, TSSOP
VCC
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
VSS
VCC
V2FAIL
V2MON
1
2
3
4
14
13
12
11
1
2
3
4
14
13
12
11
WDO
V3FAIL
V3MON
WP
SCL
SDA
WDO
V3FAIL
V3MON
WP
SCL
SDA
LOWLINE
NC
MR
RESET
VSS
5
6
7
10
9
8
5
6
7
10
9
8
PIN DESCRIPTION
Pin Name
Function
1
V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes
HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2
V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to VSS or V when not used. The
CC
V2MON comparator is supplied by V2MON (X40430, X40431) or by the VCC input (X40434, X40435).
3
LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when V < VTRIP1 and goes high when
CC
V
> VTRIP1.
CC
4
5
NC
MR
No connect.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the tPURST thereafter.
6
RESET/ RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for
tPURST thereafter.
RESET
RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for
tPURST thereafter.
7
8
VSS
SDA
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
9
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10M typical).
11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to VSS or V when not used. The
CC
V3MON comparator is supplied by the V3MON input.
12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes
HIGH when V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin.
13
14
WDO
VCC
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Supply Voltage
FN8251 Rev 1.00
May 24, 2006
Page 6 of 26
X40430, X40431, X40434, X40435
PRINCIPLES OF OPERATION
Power-on Reset
a power fail or brownout condition or used to interrupt
the microprocessor with notification of an impending
power failure.
Applying power to the X40430, X40431, X40434,
X40435 activates a Power-on Reset Circuit that pulls the
RESET/RESET pins active. This signal provides several
benefits.
For the X40430 and X40431 the V2FAIL signal remains
active until the V2MON drops below 1V (V2MON falling).
It also remains active until V2MON returns and exceeds
V
. This voltage sense circuitry monitors the power
TRIP2
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
supply connected to V2MON pin. If V
can still be monitored.
= 0, V2MON
CC
– It prevents the processor from operating prior to stabi-
lization of the oscillator.
For the X40434 and X40435, the V2FAIL signal remains
active until V drops below 1V and remains active until
CC
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
V2MON returns and exceeds V
. This sense cir-
TRIP2
cuitry is powered by V . If V = 0, V2MON cannot be
CC
CC
monitored.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
Low Voltage V3 Monitoring
When V
exceeds the device V
threshold value
TRIP1
CC
The X40430, X40431, X40434, X40435 also monitors a
third voltage level and asserts V3FAIL if the voltage falls
for t
(selectable) the circuit releases the RESET
PURST
(X40431, X40435) and RESET (X40430, X40434) pin
allowing the system to begin operation.
below a preset minimum V
. The V3FAIL signal is
TRIP3
either ORed with RESET to prevent the microprocessor
from operating in a power fail or brownout condition or
used to interrupt the microprocessor with notification of
an impending power failure. The V3FAIL signal remains
active until the V3MON drops below 1V (V3MON falling).
It also remains active until V3MON returns and exceeds
Figure 1. Connecting a Manual Reset Push-Button
VCC
X40430, X40434
System
Reset
RESET
V
.
TRIP3
MR
This voltage sense circuitry monitors the power supply
Manual
Reset
connected to V3MON pin. If V = 0, V3MON can still be
CC
monitored.
Early Low V Detection (LOWLINE)
CC
Manual Reset
This CMOS output goes LOW earlier than
By connecting a push-button directly from MR to ground,
the designer adds manual system reset capability. The MR
pin is LOW while the push-button is closed and
RESET/RESET pin remains HIGH/LOW until the push-but-
RESET/RESET whenever V
voltage and returns high when V
voltage. There is no power-up delay circuitry (t
this pin.
falls below the V
CC
TRIP1
exceeds the V
TRIP1
CC
) on
PURST
ton is released and for t
thereafter.
PURST
Low Voltage V (V1 Monitoring)
CC
During operation, the X40430, X40431, X40434, X40435
monitors the V level and asserts RESET/RESET if sup-
CC
ply voltage falls below a preset minimum V
. The
TRIP1
RESET/RESET signal prevents the microprocessor from
operating in a power fail or brownout condition. The
RESET/RESET signal remains active until the voltage
drops below 1V. It also remains active until V
returns
CC
and exceeds V
for tPURST.
TRIP1
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
. The V2FAIL signal is either ORed with
TRIP2
RESET to prevent the microprocessor from operating in
FN8251 Rev 1.00
May 24, 2006
Page 7 of 26
X40430, X40431, X40434, X40435
Figure 2. Two Uses of Multiple Voltage Monitoring
VCC
VCC
X40431-B
X40431-A
Unreg.
Supply
5V
VCC
Reg
VCC
RESET
V2FAIL
5V
6-10V
1M
System
Reset
RESET
3.0V
Reg
V2MON
System
Reset
3.3V
V2MON
V2FAIL
V3FAIL
V3MON
(1.7V)
1.8V
Reg
V3MON
V3FAIL
Power
Fail
Interrupt
390K
Notice: No external components required to monitor three voltages.
Figure 3. V
Set/Reset Conditions
TRIPX
VTRIPX
(X = 1, 2, 3)
VCC/V2MON/V3MON
VP
WDO
SCL
7
0
0
7
0
7
SDA
tWC
A0h
00h
WATCHDOG TIMER
Figure 4. Watchdog Restart
.6µs
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A stan-
dard read or write sequence to any slave address byte
restarts the watchdog timer and prevents the WDO sig-
nal going active. A minimum sequence to reset the
watchdog timer requires four microprocessor instruc-
tions namely, a Start, Clock Low, Clock High and Stop.
The state of two nonvolatile control bits in the Status
Register determine the watchdog timer period. The
microprocessor can change these watchdog bits by writ-
ing to the X40430, X40431, X40434, X40435 control
register (also refer to page 20).
1.3µs
SCL
SDA
Start
Stop
WDT Reset
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)
The X40430 is shipped with standard V1, V2 and V3
threshold (V ) voltages. These
V
V
TRIP3
TRIP1,
TRIP2,
values will not change over normal operating and stor-
age conditions. However, in applications where the stan-
dard thresholds are not exactly right, or if higher precision
is needed in the threshold value, the X40430, X40431,
X40434, X40435 trip points may be adjusted. The proce-
dure is described in the following situation, and uses the
application of a high voltage control signal.
FN8251 Rev 1.00
May 24, 2006
Page 8 of 26
X40430, X40431, X40434, X40435
Setting a V Voltage (x = 1, 2, 3)
Resetting the V
Voltage
TRIPx
TRIPx
There are two procedures used to set the threshold volt-
ages (V ), depending if the threshold voltage to be
To reset a V
voltage, apply the programming volt-
TRIPx
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
TRIPx
stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIPx
V
is 3.2 V, the new voltage can be stored directly
V
, 0Bh for V
, and 0Fh for V
, followed by
TRIPx
TRIP1
TRIP2
TRIP3
into the V
cell. If however, the new setting is to be
00h for the Data Byte in order to reset V
. The STOP
TRIPx
TRIPx
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
bit following a valid write operation initiates the program-
ming sequence. Pin WDO must then be brought LOW to
complete the operation.
TRIPx
Setting a Higher V
Voltage (x = 1, 2, 3)
TRIPx
After being reset, the value of V
nal value of 1.7V or lesser.
becomes a nomi-
TRIPx
To set a V
threshold to a new voltage which is higher
TRIPx
than the present threshold, the user must apply the desired
threshold voltage to the corresponding input pin
Notes: 1. This operation does not corrupt the memory array.
2. Set VCC 1.5(V2MON or V3MON), when setting
VTRIP2 or VTRIP3 respectively.
V
TRIPx
Vcc(V1MON), V2MON or V3MON. Then, a programming
voltage (Vp) must be applied to the WDO pin before a
START condition is set up on SDA. Next, issue on the SDA
pin the Slave Address A0h, followed by the Byte Address
CONTROL REGISTER
01h for V
, 09h for V
, and 0Dh for V
, and a
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
TRIP1
TRIP2
TRIP3
00h Data Byte in order to program V
following a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to com-
. The STOP bit
TRIPx
plete the operation. To check if the V
has been set,
TRIPX
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 11.
set VXMON to a value slightly greater than V
(that
TRIPX
was previously set). Slowly ramp down VXMON and
observe when the corresponding outputs (LOWLINE,
V2FAIL and V3FAIL) switch. The voltage at which this
occurs is the V
(actual).
TRIPX
CASE A
Now if the desired V
is greater than the V
TRIPX
TRIPX
TRIPX
desired.
(actual), then add the difference between V
(desired) – V (actual) to the original V
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, and BP. The X40430, X40431,
X40434, X40435 will not acknowledge any data bytes
written after the first byte is entered.
TRIPX
TRIPX
This is your new V
that should be applied to
TRIPX
VXMON and the whole sequence should be repeated
again (see Figure 5).
CASE B
The state of the Control Register can be read at any time
by performing a random read at address 1FFh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop
condition to be consistent with the bus protocol.
Now if the V
(actual), is higher than the V
TRIPX
TRIPX
(desired), perform the reset sequence as described in
the next section. The new V voltage to be applied
to VXMON will now be: V
TRIPX
(desired) – (V
TRIPX
TRIPX
(actual) – V
(desired)).
TRIPX
7
6
5
4
3
2
1
0
Note: This operation does not corrupt the memory array.
PUP1 WD1 WD0
BP
0
RWEL WEL PUP0
Setting a Lower V Voltage (x = 1, 2, 3)
TRIPx
RWEL: Register Write Enable Latch (Volatile)
In order to set V
to a lower voltage than the present
TRIPx
The RWEL bit must be set to “1” prior to a write to the
Control Register.
value, then V
must first be “reset” according to the
TRIPx
procedure described below. Once V
has been
TRIPx
“reset”, then V
can be set to the desired voltage
TRIPx
using the procedure described in “Setting a Higher
Voltage”.
V
TRIPx
FN8251 Rev 1.00
May 24, 2006
Page 9 of 26
X40430, X40431, X40434, X40435
Figure 5. Sample V
Reset Circuit
TRIP
VP
Adjust
Run
V2FAIL
µC
1
6
2
7
14
13
9
RESET
X4043X
VTRIP1
Adj.
8
SCL
SDA
VTRIP2
Adj.
Figure 6. V
Set/Reset Sequence (X = 1, 2, 3)
TRIPX
Vx = VCC, VxMON
Note: X = 1, 2, 3
VTRIPX Programming
Let: MDE = Maximum Desired Error
Desired
No
VTRIPX
<
MDE+
Acceptable
Present Value
Desired Value
YES
Error Range
MDE–
Execute
TRIPX Reset Sequence
V
Error = Actual - Desired
Set VX = desired VTRIPX
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
Execute Reset VTRIPX
Sequence
> Desired VTRIPX to
VX
NO
Decrease
VX
Output Switches?
YES
V
Error < MDE–
Error > MDE+
Actual
TRIPX -
VTRIPX
Desired
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
control registers will be ignored (no acknowledge will be
issued after the Data Byte). The WEL bit is set by writing
a “1” to the WEL bit and zeroes to the other bits of the
control register.
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to any address, including any
FN8251 Rev 1.00
May 24, 2006
Page 10 of 26
X40430, X40431, X40434, X40435
Once set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up again.
Writes to the WEL bit do not cause a high voltage write
cycle, so the device is ready for the next operation
immediately after the stop condition.
– Write one byte value to the Control Register that has all
the control bits set to the desired state. The Control regis-
ter can be represented as qxys 001r in binary, where xy
are the WD bits, s is the BP bit and qr are the power-up
bits. This operation proceeded by a start and ended with
a stop bit. Since this is a nonvolatile write cycle it will take
up to 10ms (max.) to complete. The RWEL bit is reset by
this cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this third
step (qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and returns
a NACK.
BP: Block Protect Bits (Nonvolatile)
The Block Protect Bit BP, determines which blocks of
the array are write protected. A write to a protected block
of memory is ignored. The block protect bit will prevent
write operations to half or none of the array.
Protected Addresses
(Size)
Memory Array
Lock
BP
0
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write oper-
ation.
None
None
1
100h – 1FFh (256 bytes)
Upper Half of
Memory Array
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write pro-
tected block.
PUP1, PUP0: Power-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power-up times are
shown in the following table.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile bits
in the Control Register to 0. A sequence of [02H, 06H,
06H] will leave the nonvolatile bits unchanged and the
RWEL bit remains set.
PUP1 PUP0
Power-on Reset Delay (tPURST)
0
0
1
1
0
1
0
1
50ms
200ms (factory setting)
400ms
Notes: 1. tPURST is set to 200ms as factory default.
2. Watch Dog Timer bits are shipped disabled.
800ms
FAULT DETECTION REGISTER
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three Low
Voltage Fail bits are volatile
The bits WD1 and WD0 control the period of the Watch-
dog Timer. The options are shown below.
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
7
6
5
4
3
2
1
0
200 milliseconds
LV1F LV2F LV3F WDF MRF
0
0
0
25 milliseconds
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It can
only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation.
disabled (factory setting)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
There is no need to set the WEL or RWEL in the control
register to access this FDR.
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
– Write a 06H to the Control Register to set the Register
Write Enable Latch (RWEL) and the WEL bit. This is
also a volatile cycle. The zeros in the data byte are
required. (Operation proceeded by a start and ended
with a stop).
FN8251 Rev 1.00
May 24, 2006
Page 11 of 26
X40430, X40431, X40434, X40435
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the FDR is defaulted to all “0”. The system
needs to initialize this register to all “1” before the actual
monitoring can take place. In the event that any one of
the monitored sources fail, the corresponding bit in the
register will change from a “1” to a “0” to indicate the fail-
ure. At this moment, the system should perform a read
to the register and note the cause of the reset. After
reading the register the system should reset the register
back to all “1” again. The state of the FDR can be read at
any time by performing a random read at address 0FFh,
using the special preamble.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and receive
operations. Therefore, the devices in this family operate
as slaves in all applications.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one byte
of data is read by the register read operation.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
MRF, Manual Reset Fail Bit (Volatile)
The MRF bit will be set to “0” when Manual Reset input
goes active.
Serial Start Condition
WDF, Watchdog Timer Fail Bit (Volatile)
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. See Figure
8.
The WDF bit will be set to “0” when the WDO goes
active.
LV1F, Low V Reset Fail Bit (Volatile)
CC
The LV1F bit will be set to “0” when V (V1MON) falls
CC
below V
.
TRIP1
Serial Stop Condition
LV2F, Low V2MON Reset Fail Bit (Volatile)
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition is also used to place the
device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
The LV2F bit will be set to “0” when V2MON falls below
V
.
TRIP2
LV3F, Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to “0” when the V3MON falls
below V
.
TRIP3
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
FN8251 Rev 1.00
May 24, 2006
Page 12 of 26
X40430, X40431, X40434, X40435
Serial Acknowledge
The master must then issue a stop condition to return
the device to Standby mode and place the device into a
known state.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 9.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array. After
receipt of the Word Address Byte, the device responds
with an acknowledge, and awaits the next eight bits of
data. After receiving the 8 bits of the Data Byte, the
device again responds with an acknowledge. The mas-
ter then terminates the transfer by generating a stop
condition, at which time the device begins the internal
write cycle to the nonvolatile memory. During this internal
write cycle, the device inputs are disabled, so the device
will not respond to any requests from the master. The SDA
output is at high impedance. See Figure 10.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the device
will respond with an acknowledge after the receipt of
each subsequent eight bit word. The device will
acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will con-
tinue to transmit data. The device will terminate further
data transmissions if an acknowledge is not detected.
A write to a protected block of memory will suppress the
acknowledge bit.
Figure 9. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output from
Transmitter
Data Output
from Receiver
Start
Acknowledge
Figure 10. Byte Write Sequence
S
t
S
t
o
p
Signals from
Byte
Address
Slave
a
the Master
Address
Data
r
t
SDA Bus
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Page Write
ated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
The device is capable of a page write operation. It is initi-
FN8251 Rev 1.00
May 24, 2006
Page 13 of 26
X40430, X40431, X40434, X40435
number of 8-bit bytes. After the receipt of each byte, the
device will respond with an acknowledge, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to ‘0’ on
the same page.
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array
will not be effected.
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the device
initiates the internal high voltage cycle. Acknowledge
polling can be initiated immediately. To do this, the mas-
ter issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device
is still busy with the high voltage cycle then no ACK will
be returned. If the device has completed the write opera-
tion, an ACK will be returned and the host can then pro-
ceed with the read or write operation. See Figure 13.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the master
begins writing at location 10, and loads 12 bytes, then
the first 6 bytes are written to locations 10 through 15,
and the last 6 bytes are written to locations 0 through 5.
Afterwards, the address counter would point to location
6 of the page that was just written. If the master supplies
more than 16 bytes of data, then new data overwrites
the previous data, one byte at a time.
The master terminates the Data Byte loading by issuing a
stop condition, which causes the device to begin the non-
volatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 11 for the address, acknowledge, and
data transfer sequence.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random
Reads, and Sequential Reads.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in the
Figure 11. Page Write Operation
(1 n 16)
S
S
t
o
p
t
a
r
Signals from
the Master
Byte
Address
Slave
Address
Data
(1)
Data
(n)
t
SDA Bus
1 0 1 0 0 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes
5 Bytes
address pointer
ends here
Addr = 7
address
10
address
= 6
address
n-1
Current Address Read
next read operation would access data from address
n+1. On power-up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
FN8251 Rev 1.00
May 24, 2006
Page 14 of 26
X40430, X40431, X40434, X40435
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. See figure 15 for the address,
acknowledge, and data transfer sequence.
lowed by an acknowledge from the device and then by the
eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
stop condition. See Figure 16 for the address, acknowl-
edge, and data transfer sequence.
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start is shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Figure 13. Acknowledge Polling Sequence
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Sequential Read
Issue Slave Address
Issue STOP
Sequential reads can be initiated as either a current
address read or random address read. The first Data Byte
is transmitted as with the other modes; however, the mas-
ter now responds with an acknowledge, indicating it
requires additional data. The device continues to output
data for each acknowledge received. The master termi-
nates the read operation by not responding with an
acknowledge and then issuing a stop condition.
Byte (Read or Write)
NO
ACK
Returned?
YES
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
0000h and the device continues to output data for each
acknowledge received. See Figure 17 for the acknowl-
edge and data transfer sequence.
High Voltage Cycle
Complete. Continue
Issue STOP
Command Sequence?
NO
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is fol-
FN8251 Rev 1.00
May 24, 2006
Page 15 of 26
X40430, X40431, X40434, X40435
SERIAL DEVICE ADDRESSING
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation.
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
Word Address
hex
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power-up condition.
General Purpose Memory Organization, A8:A0
Address: 000h to 1FFh
General Purpose Memory Array Configuration
Operational Notes
Memory Address
A8:A0
The device powers-up in the following state:
000h
– The device is in the low power standby state.
Lower 256 bytes
0FFh
100h
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
Upper 256 bytes
Block Protect Option
1FFh
– SDA pin is the input mode.
– RESET/RESET Signal is active for tPURST
.
Slave Address Byte
Data Protection
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
The following circuitry has been included to prevent
inadvertent writes:
– a device type identifier that is always ‘101x’. Where x =
0 is for Array, x = 1 is for Control Register or Fault
Detection Register.
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
Figure 14. X40430, X40431, X40434, X40435
Addressing
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Slave Byte
General Purpose Memory
Control Register
1
1
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
R/W
R/W
R/W
A8
1
Fault Detection Register
0
Word Address
General Purpose Memory
Control Register
A0
1
A7 A6 A5 A4 A3 A2 A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Fault Detection Register
1
Figure 15. Current Address Read Sequence
.
S
Slave
Address
t
S
t
o
p
Signals from
the Master
a
r
t
SDA Bus
1 0 1 0 0 0
1
A
Signals from
the Slave
C
Data
K
FN8251 Rev 1.00
May 24, 2006
Page 16 of 26
X40430, X40431, X40434, X40435
Figure 16. Random Address Read Sequence
S
S
t
S
t
o
p
t
a
r
Slave
Address
Byte
Address
Slave
Address
Signals from
the Master
a
r
t
t
SDA Bus
1 0 1 0 0
0
1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 17. Sequential Read Sequence
S
t
o
p
Slave
Address
Signals from
the Master
A
C
K
A
C
K
A
C
K
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
FN8251 Rev 1.00
May 24, 2006
Page 17 of 26
X40430, X40431, X40434, X40435
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Chip Supply
Voltage
Monitored*
Voltages
Version
X40430, X40431
X40434, X40435
2.7V to 5.5V
2.7V to 5.5V
1.7V to 5.5V
1.0V to 5.5V
-40°C
+85°C
*See Ordering Info
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
(4)
Symbol
Parameter
Min
Typ
Max
1.5
Unit
Test Conditions
(1)
ICC1
Active Supply Current (V ) Read
mA VIL = V x 0.1
CC
CC
(1)
VIH = V x 0.9,
fSCL = 400kHz
ICC2
Active Supply Current (V ) Write
3.0
mA
CC
CC
(1)(6)
ISB1
Standby Current (V ) AC (WDT off)
6
10
µA VIL = V x 0.1
CC
CC
VIH = V x 0.9
CC
fSCL, fSDA = 400kHz
(2)(6)
ISB2
Standby Current (V ) DC (WDT on)
25
30
10
10
µA VSDA = VSCL = VCC
Others = GND or VCC
CC
ILI
Input Leakage Current (SCL, MR,
WP)
µA VIL = GND to V
CC
ILO
Output Leakage Current (SDA, V2-
FAIL, V3FAIL, WDO, RESET)
µA
VSDA = GND to V
CC
Device is in Standby(2)
(3)
VIL
Input LOW Voltage (SDA, SCL, MR,
WP)
-0.5
V
x 0.3
V
V
CC
(3)
VIH
Input HIGH Voltage (SDA, SCL, MR,
WP)
V
x 0.7
V
+ 0.5
CC
CC
(6)
VHYS
Schmitt Trigger Input Hysteresis
• Fixed input level
0.2
.05 x V
V
V
• V related level
CC
CC
VOL
Output LOW Voltage (SDA, RE-
SET/RESET, LOWLINE, V2FAIL,
V3FAIL, WDO)
0.4
V
I
OL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.7-3.6V)
VOH
Output (RESET, LOWLINE) HIGH
Voltage
V
V
– 0.8
– 0.4
V
I
OH = -1.0mA (2.7-5.5V)
CC
CC
IOH = -0.4mA (2.7-3.6V)
FN8251 Rev 1.00
May 24, 2006
Page 18 of 26
X40430, X40431, X40434, X40435
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
(4)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VCC Supply
(5)
VTRIP1
V
Trip Point Voltage Range
2.0
4.75
4.65
V
V
CC
4.55
4.6
X40430, X40431-A, X40434,
X40435
4.35
2.85
4.4
2.9
4.45
2.95
V
V
X40430, X40431-B
X40430, X40431-C
Second Supply Monitor
IV2
V2MON Current
15
µA
(5)
VTRIP2
V2MON Trip Point Voltage Range
1.7
0.9
4.75
3.5
V
V
x40430, X40431
x40434, X40435
2.85
2.55
2.15
1.25
0.95
2.9
2.6
2.2
1.3
1.0
2.95
2.65
2.25
1.35
1.05
5
V
V
X40430, X40431-A
X40430, X40431-B
X40430, X40431-C
X40434, X40435-A&B
X40434, X40435-C
V
V
V
(6)
tRPD2
VTRIP2 to V2FAIL
µs
Third Supply Monitor
IV3
V3MON Current
V3MON Trip Point Voltage Range
15
4.75
1.75
3.15
2.95
5
µA
V
(5)
VTRIP3
1.7
1.65
3.05
2.85
1.7
3.1
2.9
V
X40430, X40431
V
X40434, X40435-A
X40434, X40435-B&C
V
(6)
tRPD3
VTRIP3 to V3FAIL
µs
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high
voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
(4) At 25°C, VCC = 3V
(5) See ordering information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3)
R
V = 100mV
VxMON
V
Vref
+
–
Output Pin
VREF
C
tRPDX = 5µs worst case
CAPACITANCE
Symbol
Parameter
Max
Unit
Test Conditions
(1)
COUT
Output Capacitance (SDA, RESET/RESET, LOWLINE,
V2FAIL,V3FAIL, WDO)
8
pF
VOUT = 0V
(1)
CIN
Input Capacitance (SCL, WP, MR)
6
pF
VIN = 0V
Note: (1) This parameter is not 100% tested.
FN8251 Rev 1.00
May 24, 2006
Page 19 of 26
X40430, X40431, X40434, X40435
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR V
= 5V
SYMBOL TABLE
CC
WAVEFORM
INPUTS
OUTPUTS
VCC
5V
V2MON, V3MON
Must be
steady
Will be
steady
4.6k
4.6k
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
2.06k
RESET
WDO
V2FAIL,
V3FAIL
SDA
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
30pF
30pF
30pF
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
A.C. TEST CONDITIONS
N/A
Center Line
is High
Input pulse levels
V
x 0.1 to V x 0.9
Impedance
CC
CC
Input rise and fall times
10ns
Input and output timing levels
Output load
V
x 0.5
CC
Standard output load
A.C. CHARACTERISTICS
Symbol
Parameter
Min
Max
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
fSCL
tIN
SCL Clock Frequency
400
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
50
tAA
0.1
0.9
tBUF
Time the bus free before start of new transmission
Clock LOW Time
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
Data In Hold Time
0
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
0.6
50
20 +.1Cb(1)
20 +.1Cb(1)
0.6
tR
300
300
tF
tSU:WP
tHD:WP
Cb
WP Hold Time
0
Capacitive load for each bus line
400
Note: (1) Cb = total capacitance of one bus line in pF.
FN8251 Rev 1.00
May 24, 2006
Page 20 of 26
X40430, X40431, X40434, X40435
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
tSU:WP
tHD:WP
WP
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min
Typ
Max
10
Unit
(1)
tWC
Write Cycle Time
5
ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8251 Rev 1.00
May 24, 2006
Page 21 of 26
X40430, X40431, X40434, X40435
Power Fail Timings
tR
VTRIPX
VCC
tRPDL
tRPDX
tRPDL
tRPDX
V2MON or
[ ]
V3MON
tRPDL
tRPDX
tF
LOWLINE or
V2FAIL or
[ ]
VRVALID
V3FAIL
X = 2, 3
RESET/RESET/MR Timings
VTRIP1
VCC
tPURST
tPURST
tRPD1
tF
tR
RESET
VRVALID
RESET
MR
tMD
tIN1
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, V = 5V)
CC
Symbol
Parameters
Min Typ (1)
Max
Unit
(2)
tRPD1
VTRIP1 to RESET/RESET (Power-down only)
VTRIP1 to LOWLINE
5
µs
tRPDL
t LR
LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL
]
500
ns
µs
(2)
tRPDX
VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3)
5
tPURST
Power-on Reset delay:
PUP1 = 0, PUP0 = 0
PUP1 = 0, PUP0 = 1 (factory setting)
PUP1 = 1, PUP0 = 0
50(2)
200
ms
ms
ms
ms
400(2)
800(2)
PUP1 = 1, PUP0 = 1
tF
VCC, V2MON, V3MON, Fall Time
VCC, V2MON, V3MON, Rise Time
20
20
1
mVµs
mVµs
V
tR
VRVALID Reset Valid VCC
(2)
tMD
MR to RESET/ RESET delay (activation only)
500
ns
FN8251 Rev 1.00
May 24, 2006
Page 22 of 26
X40430, X40431, X40434, X40435
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, V
= 5V) (CONTINUED)
CC
Symbol
tin1
Parameters
Min Typ (1)
Max
Unit
Pulse width for MR
5
µs
tWDO
Watchdog Timer Period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
1.4(2)
200(2)
25
s
ms
ms
WD1 = 1, WD0 = 1 (factory setting)
OFF
tRST1
Watchdog Reset Time Out Delay
WD1 = 0, WD0 = 0
100
200
300
ms
WD1 = 0, WD0 = 1
tRST2
tRSP
Watchdog Reset Time Out Delay WD1 = 1, WD0 = 0
Watchdog timer restart pulse width
12.5
1
25
37.5
ms
µs
Notes: (1) VCC = 5V at 25°C.
(2) Values based on characterization data only.
Watchdog Time Out For 2-Wire Interface
Start
Start
Clockin (0 or 1)
tRSP
< tWDO
SCL
SDA
tRST
tWDO
tRST
WDO
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
FN8251 Rev 1.00
May 24, 2006
Page 23 of 26
X40430, X40431, X40434, X40435
V
Set/Reset Conditions
TRIPX
(VTRIPX
)
VCC/V2MON/V3MON
tTHD
VP
tTSU
WDO
tVPS
tVPO
tVPH
7
SCL
SDA
0
0
7
0
7
*
tWC
A0h
00h
Start
resets VTRIP1
resets VTRIP2
*0Fh resets VTRIP3
*01h
*09h
*0Dh
*03h
*0Bh
sets VTRIP1
sets VTRIP2
sets VTRIP3
* all others reserved
V
, V
, V
Programming Specifications: V = 2.0 - 5.5V; Temperature = 25°C
TRIP1
TRIP2
TRIP3
CC
Parameter
tVPS
Description
Min.
Max. Unit
WDO Program Voltage Setup time
WDO Program Voltage Hold time
VTRIPX Level Setup time
10
10
10
10
10
1
µs
µs
tVPH
tTSU
µs
tTHD
VTRIPX Level Hold (stable) time
µs
tWC
VTRIPX Program Cycle
ms
ms
tVPO
Program Voltage Off time before next cycle
Programming Voltage
VP
15
2.0
1.7
0.9
1.7
-25
10
18
V
V
VTRAN1
VTRAN2
VTRAN2A
VTRAN3
Vtv
VTRIP1 Set Voltage Range
4.75
4.75
3.5
VTRIP2 Set Voltage Range – X40430, X40431
VTRIP2 Set to Voltage Range – X40434, X40435
VTRIP3 Set Voltage Range
V
V
4.75
+25
V
VTRIPX Set Voltage variation after programming (-40 to +85°C).
WDO Program Voltage Setup time
mV
µs
tVPS
FN8251 Rev 1.00
May 24, 2006
Page 24 of 26
X40430, X40431, X40434, X40435
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8251 Rev 1.00
May 24, 2006
Page 25 of 26
X40430, X40431, X40434, X40435
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
0o
8o
0o
8o
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8251 Rev 1.00
May 24, 2006
Page 26 of 26
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X40431V14IZ-A
3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14
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X40431V14IZ-B
3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14
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X40431V14IZ-BT1
3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14
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