X5001V8IZ-4.5A [RENESAS]
CPU Supervisor;
| 型号： | X5001V8IZ-4.5A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | CPU Supervisor 光电二极管 |
| 文件： | 总20页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X5001
CPU Supervisor
FN8125
Rev 1.00
May 30, 2006
FEATURES
DESCRIPTION
• 200ms power-on reset delay
This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
• Low V detection and reset assertion
CC
—Five standard reset threshold voltages
—Adjust low V reset threshold voltage using
CC
special programming sequence
—Reset signal valid to V = 1V
• Selectable nonvolatile watchdog timer
—0.2, 0.6, 1.4 seconds
CC
The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
—Off selection
—Select settings through software
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
• 2.7V to 5.5V operation
The user’s system is protected from low voltage condi-
tions by the device’s low V detection circuitry. When
CC
• SPI mode 0 interface
V
falls below the minimum V trip point, the system
CC
CC
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Watchdog change latch
• High reliability
• Available packages
—8 Ld TSSOP
—8 Ld SOIC
—8 Ld PDIP
is reset. RESET is asserted until V returns to proper
operating levels and stabilizes. Five industry standard
CC
V
thresholds are available, however, Intersil’s
TRIP
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
™
The device utilizes Intersil’s proprietary Direct Write
cell for the watchdog timer control bits and the V
TRIP
• Pb-free plus anneal available (RoHS compliant)
storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
BLOCK DIAGRAM
RESET
Watchdog
Transition
Detector
Watchdog
Timer
SI
Data
Register
Reset &
Watchdog
Timebase
SO
Command
Decode &
Control
SCK
CS/WDI
Logic
Power-on/
Low Voltage
REset
VCC
+
-
Generation
V
TRIP
FN8125 Rev 1.00
May 30, 2006
Page 1 of 20
X5001
Ordering Information
TEMP. RANGE
(°C)
PART NUMBER
PART MARKING VCC RANGE (V)
X5001P F 2.7 to 5.5
VTRIP RANGE
PACKAGE
8 Ld PDIP
PKG. DWG. #
MDP0031
X5001P-2.7
2.55 to 2.7
0 to 70
0 to 70
X5001PZ-2.7 (Note) X5001P ZF
8 Ld PDIP (300 mil)
(Pb-free)
MDP0031
X5001PI-2.7
X5001P G
-40 to 85
-40 to 85
8 Ld PDIP
MDP0031
MDP0031
X5001PIZ-2.7 (Note) X5001P ZG
8 Ld PDIP (300 mil)
(Pb-free)
X5001S8-2.7
X5001 F
0 to 70
0 to 70
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8Z-2.7
(Note)
X5001 ZF
8 Ld SOIC (150 mil)
(Pb-free)
X5001S8I-2.7
X5001 G
-40 to 85
-40 to 85
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8IZ-2.7
(Note)
X5001 ZG
8 Ld SOIC (150 mil)
(Pb-free)
X5001V8-2.7
501 F
0 to 70
0 to 70
8 Ld TSSOP (4.4mm)
M8.173
M8.173
X5001V8Z-2.7
(Note)
5001 FZ
8 Ld TSSOP (4.4mm)
(Pb-free)
X5001V8I-2.7
501 G
-40 to 85
-40 to 85
8 Ld TSSOP (4.4mm)
M8.173
M8.173
X5001V8IZ-2.7
(Note)
5001 GZ
8 Ld TSSOP (4.4mm)
(Pb-free)
X5001P-2.7A
X5001P AN
2.85 to 3.0
0 to 70
0 to 70
8 Ld PDIP
MDP0031
MDP0031
X5001PZ-2.7A
(Note)
X5001P ZAN
8 Ld PDIP (300 mil)
(Pb-free)
X5001PI-2.7A
X5001P AP
-40 to 85
-40 to 85
8 Ld PDIP
MDP0031
MDP0031
X5001PIZ-2.7A
(Note)
X5001P ZAP
8 Ld PDIP (300 mil)
(Pb-free)
X5001S8-2.7A
X5001 AN
0 to 70
0 to 70
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8Z-2.7A
(Note)
X5001 ZAN
8 Ld SOIC (150 mil)
(Pb-free)
X5001S8I-2.7A
X5001 AP
-40 to 85
-40 to 85
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8IZ-2.7A
(Note)
X5001 ZAP
8 Ld SOIC (150 mil)
(Pb-free)
X5001V8-2.7A
501 AN
0 to 70
0 to 70
8 Ld TSSOP (4.4mm)
M8.173
M8.173
X5001V8Z-2.7A
(Note)
5001 ANZ
8 Ld TSSOP (4.4mm)
(Pb-free)
X5001V8I-2.7A
501 AP
-40 to 85
-40 to 85
8 Ld TSSOP (4.4mm)
M8.173
M8.173
X5001V8IZ-2.7A
(Note)
5001 APZ
8 Ld TSSOP (4.4mm)
(Pb-free)
X5001PI
X5001P I
4.5 to 5.5
4.25 to 4.5
-40 to 85
-40 to 85
8 Ld PDIP
MDP0031
MDP0031
X5001PIZ (Note)
X5001P ZI
8 Ld PDIP (300 mil)
(Pb-free)
X5001S8
X5001
0 to 70
0 to 70
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8Z (Note)
X5001 Z
8 Ld SOIC (150 mil)
(Pb-free)
X5001S8I
X5001 I
-40 to 85
-40 to 85
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8IZ (Note)
X5001 ZI
8 Ld SOIC (150 mil)
(Pb-free)
FN8125 Rev 1.00
May 30, 2006
Page 2 of 20
X5001
Ordering Information (Continued)
TEMP. RANGE
(°C)
PART NUMBER
X5001V8
PART MARKING VCC RANGE (V)
VTRIP RANGE
PACKAGE
PKG. DWG. #
M8.173
501
4.5 to 5.5
4.25 to 4.5
0 to 70
0 to 70
8 Ld TSSOP (4.4mm)
X5001V8Z (Note)
5001 Z
8 Ld TSSOP (4.4mm)
(Pb-free)
M8.173
X5001V8I
501 I
-40 to 85
-40 to 85
8 Ld TSSOP (4.4mm)
M8.173
M8.173
X5001V8IZ (Note)
5001 IZ
8 Ld TSSOP (4.4mm)
(Pb-free)
X5001PI-4.5A
X5001P AM
4.5 to 5.5
4.5 to 4.75
-40 to 85
-40 to 85
8 Ld PDIP
MDP0031
MDP0031
X5001PIZ-4.5A
(Note)
X5001P ZAM
8 Ld PDIP (300 mil)
(Pb-free)
X5001S8-4.5A
X5001 AL
0 to 70
0 to 70
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8Z-4.5A
(Note)
X5001 ZAL
8 Ld SOIC (150 mil)
(Pb-free)
X5001S8I-4.5A
X5001 AM
-40 to 85
-40 to 85
8 Ld SOIC (150 mil)
MDP0027
MDP0027
X5001S8IZ-4.5A
(Note)
X5001 ZAM
8 Ld SOIC (150 mil)
(Pb-free)
X5001V8-4.5A
501 AL
0 to 70
0 to 70
8 Ld TSSOP (4.4mm)
M8.173
M8.173
X5001V8Z-4.5A
(Note)
5001 ALZ
8 Ld TSSOP (4.4mm)
(Pb-free)
X5001V8I-4.5A
501 AM
-40 to 85
-40 to 85
8 Ld TSSOP (4.4mm)
M8.173
M8.173
X5001V8IZ-4.5A
(Note)
5001 AMZ
8 Ld TSSOP (4.4mm)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8125 Rev 1.00
May 30, 2006
Page 3 of 20
X5001
PIN CONFIGURATION
8 Ld TSSOP
8 Ld SOIC/PDIP
RESET
SCK
SI
VCC
1
8
7
6
5
1
2
3
4
8
CS/WDI
SO
VCC
CS/WDI
SO
2
7
6
5
RESET
SCK
SI
X5001
X5001
VSS
VPE
VPE
3
4
VSS
PIN DESCRIPTION
Pin
(SOIC/PDIP)
Pin
TSSOP
Name
Function
1
1
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
2
5
2
8
SO
SI
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
6
3
9
6
SCK
VPE
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or watchdog bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last
valid programmed level. To readjust the VTRIP level, requires that the VPE pin be
pulled to a high voltage (15-18V).
4
8
7
7
VSS
VCC
Ground
14
13
Supply Voltage
RESET Reset Output. RESET is an active LOW, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active un-
til VCC rises above the minimum VCC sense level for 200ms. RESET goes active
if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW lon-
ger than the selectable watchdog time out period. A falling edge of CS/WDI will
reset the watchdog timer. RESET goes active on power-up at 1V and remains
active for 200ms after the power supply stabilizes.
3-5,10-12
NC
No internal connections
FN8125 Rev 1.00
May 30, 2006
Page 4 of 20
X5001
PRINCIPLES OF OPERATION
Setting the V
Voltage
TRIP
This procedure is used to set the V
voltage value. For example, if the current V
to a higher
TRIP
Power-on Reset
is 4.4V
TRIP
Application of power to the X5001 activates a power-
on reset circuit. This circuit goes active at 1V and pulls
the RESET/RESET pin active. This signal prevents
the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the
and the new V
is 4.6V, this procedure will directly
TRIP
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
To set the new V
threshold voltage to the V pin and tie the W pin to
the programming voltage V . Then a V
command sequence is sent to the device over the SPI
interface. This V programming sequence consists of
pulling CS LOW, then clocking in data 03h, 00h and 01h.
This is followed by bringing CS HIGH then LOW and
clocking in data 02h, 00h, and 01h (in order) and bringing
voltage, apply the desired V
TRIP
TRIP
oscillator. When V
exceeds the device V
value
CC
TRIP
CC
PE
for 200ms (nominal) the circuit releases RESET,
allowing the processor to begin executing code.
programming
P
TRIP
TRIP
Low Voltage Monitoring
During operation, the X5001 monitors the V
level
CC
and asserts RESET if supply voltage falls below a pre-
set minimum V . The RESET signal prevents the
TRIP
CS HIGH. This initiates the V
programming
TRIP
microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
sequence. V is brought LOW to end the operation.
P
Resetting the V
Voltage
TRIP
until V returns and exceeds V
for 200ms.
CC
TRIP
This procedure is used to set the V
to a “native”
TRIP
voltage level. For example, if the current V
is 4.4V
TRIP
Watchdog Timer
and the new V
must be 4.0V, then the V
must
TRIP
TRIP
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microproces-
sor must toggle the CS/WDI pin periodically to prevent
a RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watch-
dog time out period. The state of two nonvolatile control
bits in the watchdog register determine the watchdog
timer period.
be reset. When V
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
is reset, the new V
is some-
TRIP
TRIP
To reset the V
voltage, apply greater than 3V to
TRIP
the V
pin and tie the W pin to the programming
CC
PE
voltage V . Then a V
command sequence is sent
TRIP
P
to the device over the SPI interface. This V
pro-
TRIP
gramming sequence consists of pulling CS LOW, then
clocking in data 03h, 00h and 01h. This is followed by
bringing CS HIGH then LOW and clocking in data 02h,
00h, and 03h (in order) and bringing CS HIGH. This
Vcc Threshold Reset Procedure
The X5001 is shipped with a standard V
threshold
CC
(V
) voltage. This value will not change over normal
TRIP
initiates the V
programming sequence. V is
TRIP
P
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
brought LOW to end the operation.
TRIP
higher precision is needed in the V
value, the
TRIP
X5001 threshold may be adjusted. The procedure is
described in the following sections, and requires the
application of a high voltage control signal.
FN8125 Rev 1.00
May 30, 2006
Page 5 of 20
X5001
Figure 1. Sample V
Reset Circuit
TRIP
4.7K
VP
RESET
µC
1
2
3
4
8
7
6
5
Adjust
X5001
SCK
SI
VTRIP
Adj.
Run
SO
CS
Figure 2. Set V
Level Sequence (V = desired V
value)
TRIP
CC
TRIP
VPE = 15-18V
VPE
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
SCK
SI
16 Bits
16 Bits
03h
0001h
02h
0001h
Figure 3. Reset V
Level Sequence (V > 3V)
CC
TRIP
VPE = 15-18V
VPE
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
SCK
SI
16 Bits
6Bits
03h
0001h
02h
0003h
FN8125 Rev 1.00
May 30, 2006
Page 6 of 20
X5001
Figure 4. V
Programming Sequence
TRIP
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied - Error
New VCC Applied =
Execute
Set VTRIP
Sequence
Old VCC Applied + Error
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC - 50mV)
NO
RESET pin
goes active?
YES
Error < 0
Error > 0
Measured VTRIP
Desired VTRIP
-
Error = 0
DONE
SPI INTERFACE
All instructions (Table 1) and data are transferred MSB
first. Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allow-
ing the user to stop the clock and then start it again to
resume operations where left off.
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many pop-
ular microcontroller families.
The device monitors the CS/WDI line and asserts
RESET output if there is no activity within user select-
able timeout period. The device also monitors the V
CC
supply and asserts the RESET if V
falls below a
CC
preset minimum (V
). The device contains an 8-bit
TRIP
watchdog timer register to control the watchdog time out
period. The current settings are accessed via the SI and
SO pins.
FN8125 Rev 1.00
May 30, 2006
Page 7 of 20
X5001
Watchdog Timer Register
Read Watchdog Timer Register Operation
If there is not a nonvolatile write in progress, the read
watchdog timer instruction returns the setting of the
watchdog timer control bits. The other bits are reserved
and will return’0’ when read. See Figure 3.
7
6
5
4
3
2
1
0
0
0
0
WD1 WD0
0
0
0
Watchdog Timer Control Bits
The watchdog timer control bits, WD and WD , select
the watchdog time out period. These nonvolatile bits
are programmed with the set watchdog timer (SWDT)
instruction.
If a nonvolatile write is in progress, the read watchdog timer
register Instruction returns a HIGH on SO. When the non-
volatile write cycle is completed, a separate read watchdog
timer instruction should be used to determine the current
status of the watchdog control bits.
0
1
Watchdog Control Bits
Watchdog Time Out
RESET Operation
WD1
WD0
(Typical)
The RESET (X5001) output is designed to go LOW
0
0
1
1
0
1
0
1
1.4 seconds
whenever V
has dropped below the minimum trip
CC
600 milliseconds
200 milliseconds
disabled
point and/or the watchdog timer has reached its pro-
grammable time out limit.
The RESET output is an open drain output and requires
a pull-up resistor.
Write Watchdog Register Operation
Operational Notes
Changing the watchdog timer register is a two step pro-
cess. First, the change must be enabled by setting the
watchdog change latch (see below). This instruction is
followed by the set watchdog timer (SWDT) instruction,
which includes the data to be written (Figure 5). Data
bits 3 and 4 contain the watchdog settings and data bits
0, 1, 2, 5, 6 and 7 must be “0”.
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The watchdog change latch is reset.
Watchdog Change Latch
– The RESET signal is active for t
.
PURST
The watchdog change latch must be SET before a Write
watchdog timer operation is initiated. The Enable Watch-
dog Change (EWDC) instruction will set the latch and
the Disable Watchdog Change (DWDC) instruction will
reset the latch (Figure 6). This latch is automatically
reset upon a power-up condition and after the comple-
tion of a valid nonvolatile write cycle.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A EWDC instruction must be issued to enable a
change to the watchdog timeout setting.
– CS must come HIGH at the proper clock count in order
to implement the requested changes to the watchdog
timeout setting.
Table 1. Instruction Set Definition
Instruction Format
Instruction Name and Operation
0000 0110
0000 0100
0000 0001
EWDC: Enable Watchdog Change Operation
DWDC: Disable Watchdog Change Operation
SWDT: Set Watchdog Timer control bits:
Instruction followed by contents of register: 000(WD1) (WD0)000
See Watchdog Timer Settings and Figure 7.
0000 0101
RWDT: Read Watchdog Timer Control Bits
Note: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
FN8125 Rev 1.00
May 30, 2006
Page 8 of 20
X5001
Figure 5. Read Watchdog Timer Setting
CS
0
1
2
3
4
5
6
7
...
...
...
SCK
SI
RWDT
Instruction
W
D
1
W
D
0
SO
Figure 6. Enable Watchdog Change/Disable Watchdog Change Sequence
CS
0
1
2
3
4
5
6
7
SCK
Instruction
(1 Byte)
SI
High Impedance
SO
Figure 7. Write Watchdog Timer Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
Instruction
Data Byte
4
6
5
3
SI
W
D
0
W
D
1
High Impedance
SO
FN8125 Rev 1.00
May 30, 2006
Page 9 of 20
X5001
Figure 8. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation)
CS
0
1
2
3
4
5
6
7
SCK
SI
RWDT
Instruction
Nonvolatile Write in Progress
SO
SO HIGH During 1st Bit While
in the Nonvolatile Write Cycle
Figure 9. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation)
CS
0
1
2
3
4
5
6
7
SCK
SI
RWDT
Instruction
Nonvolatile Write in Progress
SO
SO HIGH During
Nonvolatile Write Cycle
FN8125 Rev 1.00
May 30, 2006
Page 10 of 20
X5001
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to+135°C
Storage temperature ........................ -65°C to+150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above those
listed in the operational sections of this datasheet) is not
implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Voltage Option
-1.8
Supply Voltage Limits
1.8V to 3.6V
Commercial
0°C
+70°C
-2.7 or -2.7A
-4.5 or -4.5A
2.7V to 5.5V
4.5V to 5.5V
Note: PT= Package, Temperature
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Limits
Symbol
Parameter
Unit
Test Conditions
Min.
Typ
Max.
ICC1
VCC write current
(Active)
5
mA
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,
SO = Open
ICC2
ISB1
ISB2
ISB3
VCC read current
(Active)
0.4
1
mA
µA
µA
µA
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,
SO = Open
VCC standby current
WDT=OFF
CS = VCC, VIN = VSS or VCC, VCC = 5.5V
CS = VCC, VIN = VSS or VCC, VCC = 5.5V
CS = VCC, VIN = VSS or VCC, VCC = 3.6V
VCC standby current
WDT=ON
50
20
VCC standby current
WDT=ON
ILI
Input leakage current
Output leakage current
Input LOW voltage
0.1
0.1
10
10
µA
µA
V
VIN = VSS to VCC
ILO
VOUT = VSS to VCC
(1)
VIL
-0.5
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
Input HIGH voltage
Output LOW voltage
Output LOW voltage
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
VCC x 0.7
V
VOL1
VOL2
VOL3
VOH1
VOH2
VOH3
VOLRS
V
VCC > 3.3V, IOL = 2.1mA
2V < VCC < 3.3V, IOL = 1mA
VCC 2V, IOL = 0.5mA
VCC > 3.3V, IOH = -1.0mA
2V < VCC 3.3V, IOH = -0.4mA
VCC 2V, IOH = -0.25mA
0.4
V
0.4
V
VCC-0.8
VCC-0.4
VCC-0.2
V
V
V
Reset output LOW
voltage
0.4
V
IOL = 1mA
FN8125 Rev 1.00
May 30, 2006
Page 11 of 20
X5001
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Unit
ms
(2)
tPUR
Power-up to read operation
Power-up to write operation
1
5
(2)
tPUW
ms
CAPACITANCE (T = +25°C, f = 1MHz, V = 5V)
A
CC
Symbol
Test
Max.
Unit
pF
Conditions
VOUT = 0V
VIN = 0V
(2)
COUT
Output capacitance (SO, RESET)
Input capacitance (SCK, SI, CS)
8
6
(2)
CIN
pF
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
3V
5V
Input rise and fall times
Input and output timing level
VCC x0.5
3.3k
1.64k
Output
1.64k
RESET
30pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
1.8V-3.6V
2.7V-5.5V
SymboL
fSCK
tCYC
tLEAD
tLAG
tWH
Parameter
Clock frequency
Min.
Max.
Min.
Max.
Unit
MHz
ns
0
1
0
2
Cycle time
1000
400
400
400
400
100
100
500
200
200
200
200
50
CS lead time
ns
CS lag time
ns
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
Write cycle time
ns
tWL
ns
tSU
ns
tH
50
ns
(3)
tRI
2
2
2
2
µs
(3)
tFI
µs
tCS
250
150
ns
(4)
tWC
10
10
ms
FN8125 Rev 1.00
May 30, 2006
Page 12 of 20
X5001
Data Output Timing
1.8V-3.6V
2.7V-5.5V
Symbol
Parameter
Clock frequency
Output disable time
Min.
Max.
1
Min.
Max.
2
Unit
MHz
ns
fSCK
tDIS
tV
0
0
400
400
200
200
Output valid from clock low
Output hold time
ns
tHO
0
0
ns
(3)
tRO
Output rise time
300
300
150
150
ns
(3)
tFO
Output fall time
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Figure 10. Data Output Timing
CS
tCYC
tWH
tLAG
SCK
SO
SI
tV
tHO
tWL
tDIS
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
Figure 11. Data Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB In
LSB In
High Impedance
SO
FN8125 Rev 1.00
May 30, 2006
Page 13 of 20
X5001
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Figure 12. Power-Up and Power-Down Timing
VTRIP
VTRIP
VCC
tPURST
0 Volts
tF
tPURST
tRPD
tR
RESET (X5001)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset trip point voltage, X5001PT-4.5A
Reset trip point voltage, X5001PT-4.5
Reset trip point voltage, X5001PT-2.7A
Reset trip point voltage, X5001PT-2.7
Reset trip point voltage, X5001PT-1.8
4.50
4.25
2.85
2.55
1.70
4.63
4.38
2.92
2.63
1.75
4.75
4.50
3.00
2.70
1.80
V
tPURST
Power-up reset timeout
VCC detect to reset/output
VCC fall time
100
200
280
500
ms
ns
ns
ns
V
(5)
tRPD
(5)
tF
0.1
0.1
1
(5)
tR
VCC rise time
VRVALID
Reset valid VCC
Note: (5) This parameter is periodically sampled and not 100% tested.
PT = Package, Temperature
FN8125 Rev 1.00
May 30, 2006
Page 14 of 20
X5001
Figure 13. CS vs. RESET Timing
CS
tCST
RESET
tWDO
tRST
tWDO
tRST
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
tWDO
Watchdog timeout period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
tCST
tRST
CS pulse width to reset the watchdog
Reset Timeout
400
100
ns
200
300
ms
V
Programming Timing Diagram
TRIP
VCC
(VTRIP
VTRIP
)
tTHD
tTSU
VP
VPE
tVPH
tVPS
tVPO
tPCS
CS
tRP
SCK
SI
0001h or
0003h
03h
0001h
02h
FN8125 Rev 1.00
May 30, 2006
Page 15 of 20
X5001
Programming Parameters
V
TRIP
Parameter
tVPS
Description
VTRIP program enable voltage setup time
Min. Max. Unit
1
1
µs
µs
µs
µs
ms
ms
µs
ms
V
tVPH
tPCS
tTSU
VTRIP program enable voltage hold time
VTRIP programming CS inactive time
1
VTRIP setup time
1
tTHD
tWC
tVPO
tRP
VTRIP hold (stable) time
10
VTRIP write cycle time
10
VTRIP program enable voltage Off time (between successive adjustments)
VTRIP program recovery period (between successive adjustments)
Programming voltage
0
10
VP
15
18
5.0
VTRAN
Vta1
VTRIP programmed voltage range
1.7
-0.1
-25
V
Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C)
+0.4
+25
V
Vta2
Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP
Programmed at 25°C.]
.
mV
Vtr
VTRIP program voltage repeatability (Successive program operations. Programmed at
25°C.)
-25
-25
+25
+25
mV
mV
Vtv
VTRIP program variation after programming (0-75°C). (programmed at 25°C)
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8125 Rev 1.00
May 30, 2006
Page 16 of 20
X5001
V
Supply Current vs. Temperature (I
)
t
vs. Voltage/Temperature (WD1, 0 = 1, 1)
CC
SB
WDO
1.85
20
18
Watchdog Timer On (VCC = 5V)
17
1.80
1.75
1.70
1.65
1.60
14
15
-40°C
Watchdog Timer On (VCC = 3V)
11
1.55
1.50
1.45
1.40
25°C
90°C
Watchdog Timer Off (VCC = 3V, 5V)
1.0
90C
0.55
0.35
1.7
3.1
Voltage
4.5
-40C
25C
Temp (c)
V
vs. Temperature (programmed at 25°C)
t
vs. Voltage/Temperature (WD1, 0 = 1, 0)
WDO
TRIP
5.025
0.85
V
TRIP = 5V
5.000
0.80
4.975
3.525
3.500
-40°C
0.75
V
TRIP = 3.5V
25°C
0.70
3.475
90°C
2.525
2.500
2.475
0.65
0.60
VTRIP = 2.5V
1.7
3.1
4.5
0
25
85
Voltage
Temperature
t
vs. Temperature
t
vs. Voltage/Temperature (WD1, 0 0 = 0, 1)
WDO
PURST
280
275
270
265
260
255
250
245
240
0.30
0.29
0.28
0.27
-40°C
0.26
0.25
0.24
0.23
0.22
0.21
0.20
25°C
90°C
235
-40
1.7
3.1
4.5
25
90
Voltage
Degrees °C
FN8125 Rev 1.00
May 30, 2006
Page 17 of 20
X5001
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8125 Rev 1.00
May 30, 2006
Page 18 of 20
X5001
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
FN8125 Rev 1.00
May 30, 2006
Page 19 of 20
X5001
Thin Shrink Small Outline Plastic Packages (TSSOP)
M8.173
N
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.120
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
3.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.116
0.169
0.05
0.80
0.19
0.09
2.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
8
8
7
NOTES:
0o
8o
0o
8o
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 1 12/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
© Copyright Intersil Americas LLC 2005-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8125 Rev 1.00
May 30, 2006
Page 20 of 20
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