X5045S8-T1 [RENESAS]
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8;
| 型号： | X5045S8-T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8 光电二极管 |
| 文件： | 总26页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X5043, X5045
®
4K, 512 x 8 Bit
Data Sheet
March 16, 2006
FN8126.2
CPU Supervisor with 4K SPI EEPROM
Features
• Low VCC Detection and Reset Assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence.
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
- Reset signal valid to VCC = 1V
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor executes code.
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <10µA max standby current, watchdog off
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
• 4Kbits of EEPROM–1M Write Cycle Endurance
• Save Critical Data with Block Lock™ Memory
- Protect 1/4, 1/2, all or none of EEPROM array
• Built-in Inadvertent Write Protection
- Write enable latch
- Write protect pin
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Four industry standard VTRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time
- 16-byte page write mode
- 5ms write cycle time (typical)
• Available Packages
- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP
- 14 Ld TSSOP
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as 512 x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5043, X5045
Typical Application
2.7-5.0V
VCC
uC
VCC
10K
X5043
RESET
CS
SCK
SI
RESET
SPI
SO
WP
VSS
VSS
Block Diagram
POR and Low
Voltage Reset
Generation
RESET (X5043)
RESET (X5045)
VCC
+
V
-
TRIP
Reset & Watchdog
Timebase
X5043, X5045
STANDARD VTRIP LEVEL
SUFFIX
-4.5A
-4.5
Watchdog
Timer
Reset
Watchdog
Transition
Detector
4.63V (+/-2.5%)
4.38V (+/-2.5%)
2.93V (+/-2.5%)
-2.7A
-2.7
CS/WDI
SI
Status
Register
Command
Decode &
Control
2.63V (+/-2.5%)
SO
SCK
WP
See “Ordering Information” on page 3. for
more details
For Custom Settings, call Intersil.
EEPROM
Array
4Kbits
Logic
Protect Logic
FN8126.2
March 16, 2006
2
X5043, X5045
Ordering Information
PART NUMBER
PART NUMBER
RESET
TEMP
RANGE
(°C)
RESET
PART
PART
VCC
VTRIP
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKING
RANGE
RANGE
PACKAGE
8 Ld PDIP
X5043P-4.5A
X5043P AL
X5045P-4.5A
X5045P AL
4.5-5.5V
4.5-4.75
0 to 70
0 to 70
X5043PZ-4.5A (Note) X5043P Z AL X5045PZ-4.5A (Note) X5045P Z AL
X5043PI-4.5A X5043P AM X5045PI-4.5A X5045P AM
X5043PIZ-4.5A (Note) X5043P Z AM X5045PIZ-4.5A (Note) X5045P Z AM
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld SOIC
X5043S8-4.5A
X5043 AL
X5045S8-4.5A
X5045 AL
X5043S8Z-4.5A (Note) X5043 Z AL X5045S8Z-4.5A
(Note)
X5045 Z AL
0 to 70
8 Ld SOIC (Pb-free)
X5043S8I-4.5A*
X5043 AM
X5045S8I-4.5A*
X5045 AM
-40 to 85
-40 to 85
8 Ld SOIC
X5043S8IZ-4.5A*
(Note)
X5043 Z AM X5045S8IZ-4.5A*
(Note)
X5045 Z AM
8 Ld SOIC (Pb-free)
X5043M8-4.5A
AEM
DBS
X5045M8-4.5A
AEV
DCB
0 to 70
0 to 70
8 Ld MSOP
X5043M8Z-4.5A
(Note)
X5045M8Z-4.5A
(Note)
8 Ld MSOP (Pb-free)
X5043M8I-4.5A
AEN
DBM
X5045M8I-4.5A
AEW
DBX
-40 to 85
-40 to 85
8 Ld MSOP
X5043M8IZ-4.5A
(Note)
X5045M8IZ-4.5A
(Note)
8 Ld MSOP (Pb-free)
X5043V14I-4.5A
X5043V AM X5045V14I-4.5A
X5045V AM
-40 to 85
-40 to 85
14 Ld TSSOP
X5043V14IZ-4.5A
(Note)
X5043V Z AM X5045V14IZ-4.5A
(Note)
X5045V Z AM
14 Ld TSSOP
(Pb-free)
X5043P
X5043P
X5043P Z
X5043P I
X5043P Z I
X5043
X5045P
X5045P
X5045P Z
X5045P I
X5045P Z I
X5045
4.25-4.5
0 to 70
0 to 70
8 Ld PDIP
X5043PZ (Note)
X5043PI
X5045PZ (Note)
X5045PI
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X5043PIZ (Note)
X5043S8*
X5045PIZ (Note)
X5045S8*
8 Ld PDIP (Pb-free)
8 Ld SOIC
X5043S8Z* (Note)
X5043S8I*
X5043 Z
X5043 I
X5043 Z I
AEO
X5045S8Z* (Note)
X5045S8I*
X5045 Z
X5045 I
X5045 Z I
AEX
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X5043S8IZ* (Note)
X5043M8
X5045S8IZ* (Note)
X5045M8
8 Ld SOIC (Pb-free)
8 Ld MSOP
X5043M8Z (Note)
X5043M8I
DBN
X5045M8Z (Note)
X5045M8I
DBY
0 to 70
8 Ld MSOP (Pb-free)
8 Ld MSOP
AEP
AEY
-40 to 85
-40 to 85
-40 to 85
-40 to 85
X5043M8IZ (Note)
X5043V14I
DBJ
X5045M8IZ (Note)
X5045V14I
DBT
8 Ld MSOP (Pb-free)
14 Ld TSSOP
X5043V I
X5043V Z I
X5045V I
X5045V Z I
X5043V14IZ (Note)
X5045V14IZ (Note)
14 Ld TSSOP
(Pb-free)
FN8126.2
3
March 16, 2006
X5043, X5045
Ordering Information (Continued)
PART NUMBER
RESET
PART NUMBER
TEMP
RANGE
(°C)
PART
RESET
PART
VCC
VTRIP
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKING
RANGE
RANGE
PACKAGE
8 Ld PDIP
X5043P-2.7A
X5043P AN X5045P-2.7A
X5045P AN
2.7-5.5V
2.85-3.0
0 to 70
0 to 70
X5043PZ-2.7A (Note) X5043P Z AN X5045PZ-2.7A (Note) X5045P Z AN
X5043PI-2.7A X5043P AP X5045PI-2.7A X5045P AP
X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5045P Z AP
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld SOIC
X5043S8-2.7A*
X5043 AN
X5045S8-2.7A
X5045 AN
X5043S8Z-2.7A*
(Note)
X5043 Z AN X5045S8Z-2.7A
(Note)
X5045 Z AN
0 to 70
8 Ld SOIC (Pb-free)
X5043S8I-2.7A*
X5043 AP
X5045S8I-2.7A
X5045 AP
-40 to 85
-40 to 85
8 Ld SOIC
X5043S8IZ-2.7A*
(Note)
X5043 Z AP X5045S8IZ-2.7A
(Note)
X5045 Z AP
8 Ld SOIC
(Pb-free)
X5043M8-2.7A*
AEQ
DBR
X5045M8-2.7A
AEZ
DCA
0 to 70
0 to 70
8 Ld MSOP
X5043M8Z-2.7A
(Note)
X5045M8Z-2.7A
(Note)
8 Ld MSOP (Pb-free)
X5043M8I-2.7A*
AER
DBL
X5045M8I-2.7A
AFA
-40 to 85
-40 to 85
8 Ld MSOP
X5043M8IZ-2.7A*
(Note)
X5045M8IZ-2.7A
(Note)
DBW
8 Ld MSOP (Pb-free)
X5043V14I-2.7A
X5043V AP
X5045V14I-2.7A
X5045V AP
-40 to 85
-40 to 85
14 Ld TSSOP
X5043V14IZ-2.7A
(Note)
X5043V Z AP X5045V14IZ-2.7A
(Note)
X5045V Z AP
14 Ld TSSOP
(Pb-free)
X5043P-2.7
X5043P F
X5043P Z F X5045PZ-2.7 (Note)
X5043P G X5045PI-2.7
X5045P-2.7
X5045P F
X5045P Z F
X5045P G
2.55-2.7
0 to 70
0 to 70
8 Ld PDIP
X5043PZ-2.7 (Note)
X5043PI-2.7
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X5043PIZ-2.7 (Note)
X5043S8-2.7*
X5043P Z G X5045PIZ-2.7 (Note) X5045P Z G
X5043 F X5045S8-2.7* X5045 F
X5045S8Z-2.7* (Note) X5045 Z F
8 Ld PDIP (Pb-free)
8 Ld SOIC
X5043S8Z-2.7* (Note) X5043 Z F
X5043S8I-2.7* X5043 G
X5043S8IZ-2.7* (Note) X5043 Z G
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
X5045S8I-2.7*
X5045 G
-40 to 85
-40 to 85
X5045S8IZ-2.7*
(Note)
X5045 Z G
8 Ld SOIC (Pb-free)
X5043M8-2.7
AES
X5045M8-2.7
AFB
0 to 70
0 to 70
8 Ld MSOP
X5043M8Z-2.7 (Note) DBP
X5045M8Z-2.7 (Note) DBZ
X5045M8I-2.7 AFC
X5045M8IZ-2.7 (Note) DBU
8 Ld MSOP (Pb-free)
8 Ld MSOP
X5043M8I-2.7*
AET
DBK
-40 to 85
-40 to 85
X5043M8IZ-2.7*
(Note)
8 Ld MSOP (Pb-free)
X5043V14I-2.7
X5043V G
X5045V14I-2.7
X5045V G
X5045V Z G
-40 to 85
-40 to 85
14 Ld TSSOP
X5043V14IZ-2.7
(Note)
X5043V Z G X5045V14IZ-2.7
(Note)
14 Ld TSSOP
(Pb-free)
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8126.2
4
March 16, 2006
X5043, X5045
cycle has already been initiated, WP going low will have no
affect on a write.
Pin Configuration
8 Ld SOIC/PDIP/MSOP
Reset (RESET, RESET)
X5043, X5045, RESET/RESET is an active low/HIGH, open
drain output which goes active whenever VCC falls below the
minimum VCC sense level. It will remain active until VCC
rises above the minimum VCC sense level for 200ms.
RESET/RESET also goes active if the Watchdog timer is
enabled and CS remains either high or low longer than the
Watchdog time out period. A falling edge of CS will reset the
watchdog timer.
V
1
8
CS/WDI
SO
CC
2
3
4
7
6
5
RESET/RESET
X5043, X5045
WP
SCK
SI
V
SS
14 Ld TSSOP
1
V
14
CS
SO
NC
Pin Names
CC
2
3
4
5
6
7
13
12
RESET/RESET
SYMBOL
DESCRIPTION
Chip Select Input
Serial Output
NC
NC
CS/WDI
X5043, X5045
11
10
9
NC
NC
SO
NC
SCK
SI
SI
SCK
Serial Input
WP
Serial Clock Input
Write Protect Input
Ground
V
8
SS
WP
VSS
Pin Descriptions
Serial Output (SO)
VCC
Supply Voltage
Reset Output
RESET/RESET
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
Principles of Operation
Power-on Reset
Serial Input (SI)
Application of power to the X5043, X5045 activate a Power-
on Reset Circuit. This circuit pulls the RESET/RESET pin
active. RESET/RESET prevents the system microprocessor
from starting to operate with insufficient voltage or prior to
stabilization of the oscillator. When VCC exceeds the device
SI is the serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
VTRIP value for 200ms (nominal) the circuit releases
The Serial Clock controls the serial bus timing for data input
and output. Opcodes, addresses, or data present on the SI
pin is latched on the rising edge of the clock input, while data
on the SO pin changes after the falling edge of the clock
input.
RESET/RESET, allowing the processor to begin executing
code.
Low Voltage Monitoring
During operation, the X5043, X5045 monitor the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
Chip Select (CS/WDI)
When CS is high, the X5043, X5045 are deselected and the
SO output pin is at high impedance and, unless an internal
write operation is underway, the X5043, X5045 will be in the
standby power mode. CS low enables the X5043, X5045,
placing it in the active power mode. It should be noted that
after power-up, a high to low transition on CS is required prior
to the start of any operation.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent an active
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determines the watchdog timer period.
The microprocessor can change these watchdog bits. With
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043, X5045 are
disabled, but the part otherwise functions normally. When
WP is held high, all functions, including non volatile writes
operate normally. WP going low while CS is still low will
interrupt a write to the X5043, X5045. If the internal write
FN8126.2
5
March 16, 2006
X5043, X5045
no microprocessor action, the watchdog timer control bits
remain unchanged, even during total power failure.
address 03h. CS going HIGH on the write operation initiates
the VTRIP programming sequence. Bring WP LOW to
complete the operation.
V
Threshold Reset Procedure
CC
Note: This operation also writes 00h to array address 03h.
The X5043, X5045 are shipped with a standard VCC
threshold (VTRIP) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard VTRIP is not exactly right, or
if higher precision is needed in the VTRIP value, the X5043,
X5045 threshold may be adjusted. The procedure is
described below, and uses the application of a high voltage
control signal.
Setting the V
Voltage
TRIP
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
V
TRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 01h.
Resetting the V
Voltage
TRIP
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
V
TRIP must be 4.0V, then the VTRIP must be reset. When
TRIP is reset, the new VTRIP is something less than 1.7V.
V
This procedure must be used to set the voltage to a lower
value.
To reset the VTRIP voltage, apply at least 3V to the VCC pin
and tie the WP pin to the programming voltage VP. Then
send a WREN command, followed by a write of Data 00h to
VP = 15-18V
WP
CS
0
1 2 3 4 5 6 7
0
1
2 3
4
5 6 7 8 9 10 11 12 13 14 15
SCK
8 Bits
SI
06h
02h
00h
01h
WREN
Write
Address
Data
FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE.)
FN8126.2
6
March 16, 2006
X5043, X5045
VP = 15-18V
WP
CS
0
1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
8 Bits
SCK
SI
06h
WREN
02h
00h
03h
Write
Address
Data
FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15–18V)
4.7K
VP
µC
RESET
1
2
3
4
8
7
6
5
Adjust
Run
X5043
X5045
SCK
SI
VTRIP
Adj.
SO
CS
FIGURE 3. SAMPLE VTRIP RESET CIRCUIT
FN8126.2
7
March 16, 2006
X5043, X5045
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The array
is internally organized as 512 x 8 bits. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
VTRIP Programming
Execute
Reset VTRIP
Sequence
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
Set VCC = VCC Applied =
Desired VTRIP
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
New VCC Applied
New VCC Applied
Execute
Set VTRIP
Sequence
=
=
Old VCC Applied
Old VCC Applied
- Error
- Error
The device contains an 8-bit instruction register that controls
the operation of the device. The instruction code is written to
the device via the SI input. There are two write operations
that requires only the instruction byte. There are two read
operations that use the instruction byte to initiate the output
of data. The remainder of the operations require an
instruction byte, an 8-bit address, then data bytes. All
instruction, address and data bits are clocked by the SCK
input. All instructions (Table 1), addresses and data are
transferred MSB first.
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC–10mV)
NO
RESET pin
goes active?
Clock and Data Timing
YES
Data input on the SI line is latched on the first rising edge of
SCK after CS goes LOW. Data is output on the SO line by
the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
where left off. CS must be LOW during the entire operation.
Measured VTRIP
-Desired VTRIP
Error ≤ -Emax
Error ≥ Emax
-Emax < Error < Emax
DONE
Emax = Maximum Desired Error
FIGURE 4. VTRIP PROGRAMMING SEQUENCE
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
INSTRUCTION FORMAT*
0000 0110
OPERATION
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
WREN
WRDI
0000 0100
RSDR
WRSR
READ
WRITE
0000 0101
0000 0001
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
0000 A8011
0000 A8010
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
FN8126.2
8
March 16, 2006
X5043, X5045
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
Write Enable Latch
The device contains a Write Enable Latch. This latch must be
SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will reset
the latch (Figure 5). This latch is automatically reset upon a
power-up condition and after the completion of a valid byte,
page, or status register write cycle. The latch is also reset if WP
is brought LOW.
STATUS REG BITS
ARRAY ADDRESSES PROTECTED
BL1
0
BL0
0
X5043, X5045
None
0
1
$180–$1FF
$100–$1FF
$000–$1FF
When issuing a WREN, WRDI or RDSR commands, it is not
necessary to send a byte address or data.
1
0
1
1
CS
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
0
1
2
3
4
5
6
7
STATUS REGISTER BITS
WATCHDOG TIME OUT
SCK
WD1
WD0
(TYPICAL)
1.4 seconds
0
0
1
1
0
1
0
1
SI
600 milliseconds
200 milliseconds
disabled (factory default)
High Impedance
SO
FIGURE 5. WRITE ENABLE/DISABLE LATCH SEQUENCE
(WREN/WRDI INSTRUCTION)
Read Status Register
To read the Status Register, pull CS low to select the device,
then send the 8-bit RDSR instruction. Then the contents of
the Status Register are shifted out on the SO line, clocked by
CLK. Refer to the Read Status Register Sequence (Figure
6). The Status Register may be read at any time, even during
a Write Cycle.
Status Register
The Status Register contains four nonvolatile control bits and
two volatile status bits. The control bits set the operation of
the watchdog timer and the memory block lock protection.
The Status Register is formatted as shown in “Status
Register”.
Write Status Register
Prior to any attempt to write data into the status register, the
“Write Enable” Latch (WEL) must be set by issuing the
WREN instruction (Figure 5). First pull CS LOW, then clock
the WREN instruction into the device and pull CS HIGH.
Then bring CS LOW again and enter the WRSR instruction
followed by 8 bits of data. These 8 bits of data correspond to
the contents of the status register. The operation ends with
CS going HIGH. If CS does not go HIGH between WREN
and WRSR, the WRSR instruction is ignored.
Status Register: (Default = 30H)
7
6
5
4
3
2
1
0
0
0
WD1 WD0
BL1
BL0
WEL
WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The Write Enable Latch (WEL) bit indicates the status of the
“write enable” latch. When WEL = 1, the latch is set and
when WEL = 0 the latch is reset. The WEL bit is a volatile,
read only bit. The WREN instruction sets the WEL bit and the
WRDS instruction resets the WEL bit.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
FN8126.2
9
March 16, 2006
X5043, X5045
TABLE 2. DEVICE PROTECT MATRIX
MEMORY BLOCK
STATUS REGISTER
(BL0, BL1, WD0, WD1)
Protected
WREN CMD
(WEL)
DEVICE PIN (WP)
PROTECTED AREA
UNPROTECTED AREA
0
x
1
x
0
1
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
CS
SCK
SI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15
Instruction
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
Data Byte
Instruction
5
4
3
2
1
0
SI
High Impedance
FIGURE 7. WRITE STATUS REGISTER SEQUENCE
SO
FN8126.2
March 16, 2006
10
X5043, X5045
For the write operation (byte or page write) to be completed,
Read Memory Array
CS must be brought HIGH after bit 0 of the last complete
data byte to be written is clocked in. If it is brought HIGH at
any other time, the write operation will not be completed
(Figure 9).
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 8-bit address. Bit 3
of the READ instruction selects the upper or lower half of the
device. After the READ opcode and address are sent, the
data stored in the memory at the selected address is shifted
out on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address 000h allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS high. Refer to the Read EEPROM Array
While the write is in progress following a status register or
memory array write sequence, the Status Register may be
read to check the WIP bit. WIP is HIGH while the nonvolatile
write is in progress.
Sequence (Figure 8).
Write Memory Array
Prior to any attempt to write data into the memory array, the
“Write Enable” Latch (WEL) must be set by issuing the
WREN instruction (Figure 5). First pull CS LOW, then clock
the WREN instruction into the device and pull CS HIGH.
Then bring CS LOW again and enter the WRITE instruction
followed by the 8-bit address and then the data to be written.
Bit 3 of the WRITE instruction contains address bit A8, which
selects the upper or lower half of the array. If CS does not go
HIGH between WREN and WRITE, the WRITE instruction is
ignored.
The WRITE operation requires at least 16 clocks. CS must
go low and remain low for the duration of the operation. The
host may continue to write up to 16 bytes of data. The only
restriction is that the 16 bytes must reside within the same
page. A page address begins with address [x xxxx 0000] and
ends with [x xxxx 1111]. If the byte address reaches the last
byte on the page and the clock continues, the counter will roll
back to the first address of the page and overwrite any data
that has been previously written.
CS
0
1
2
3
4
5
6
7
8
9
6
10
12 13 14 15 16 17 18 19 20 21 22
SCK
SI
Instruction
8 Bit Address
7
5
3
2
1
0
8
9th Bit of Address
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
FIGURE 8. READ EEPROM ARRAY SEQUENCE
FN8126.2
11
March 16, 2006
X5043, X5045
CS
0
1
2
3
4
8
5
6
7
8
9
10
12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
8 Bit Address
Data Byte 1
7
6
5
3
2
1
0
7
6
5
4
3
2
1
0
SI
9th Bit of Address
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
Data Byte 3
Data Byte N
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FIGURE 9. WRITE MEMORY SEQUENCE
Operational Notes
The device powers-up in the following state:
1. The device is in the low power standby state.
2. A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
3. SO pin is high impedance.
4. The Write Enable Latch is reset.
5. The Flag Bit is reset.
6. Reset Signal is active for tPURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
• Block Protect bits provide additional level of write
protection for the memory array.
• The WP pin LOW blocks nonvolatile write operations.
FN8126.2
12
March 16, 2006
X5043, X5045
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature:
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with
respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage:
-2.7, -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank, -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
ICC1
PARAMETER
VCC Write Current (Active)
VCC Read Current (Active)
TEST CONDITIONS/COMMENTS
SCK = 3.3MHz(3); SO, RESET, RESET = Open
MIN
TYP(2)
MAX
UNIT
mA
3
2
ICC2
SCK = 3.3MHz(3); SI = VSS, RESET, RESET =
Open
mA
ISB1
ISB2
ILI
VCC Standby Current WDT = OFF CS = VCC, SCK, SI = VSS, VCC = 5.5V
VCC Standby Current WDT = ON CS = VCC, SCK, SI = VSS, VCC = 5.5V
10
50
µA
µA
µA
µA
V
Input Leakage Current
Output Leakage Current
Input LOW Voltage
SCK, SI, WP = VSS to VCC
SO, RESET, RESET = VSS to VCC
SCK, SI, WP, CS
0.1
0.1
10
ILO
10
(1)
VIL
-0.5
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
Input HIGH Voltage
SCK, SI, WP, CS
VCC x 0.7
V
VOL
Output LOW Voltage (SO)
IOL = 2mA @ VCC = 2.7V
V
I
OL = 0.5mA @ VCC = 1.8V
VOH1
VOH2
VOH3
VOLRS
Output HIGH Voltage (SO)
Output HIGH Voltage (SO)
Output HIGH Voltage (SO)
VCC > 3.3V, IOH = –1.0mA
VCC - 0.8
VCC - 0.4
VCC - 0.2
V
V
V
V
2V < VCC ≤ 3.3V, IOH = –0.4mA
V
CC ≤ 2V, IOH = –0.25mA
Output LOW Voltage (RESET,
RESET)
IOL = 1mA
0.4
Capacitance TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
TEST
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
CONDITIONS
MAX
UNIT
(2)
COUT
VOUT = 0V
VIN = 0V
8
6
pF
pF
(2)
CIN
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
3. SCK frequency measured from VCC x 0.1/VCC x 0.9
FN8126.2
13
March 16, 2006
X5043, X5045
Equivalent A.C. Load Circuit at 5V V
A.C. Test Conditions
CC
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
5V
5V
Input rise and fall times
Input and output timing level
V
CC x 0.5
4.6kΩ
1.64kΩ
Output
1.64kΩ
RESET/RESET
30pF
30pF
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)
2.7V–5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
DATA INPUT TIMING
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
Clock Frequency
0
3.3
MHz
ns
Cycle Time
300
150
150
130
130
30
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
ns
tSU
ns
tH
30
ns
(4)
tRI
2
2
µs
µs
ns
(4)
tFI
tCS
100
(5)
tWC
10
ms
Data Output Timing
2.7–5.5V
SYMBOL
PARAMETER
MIN
MAX
3.3
UNIT
MHz
ns
fSCK
tDIS
tV
Clock Frequency
0
Output Disable Time
Output Valid from Clock Low
Output Hold Time
150
120
ns
tHO
0
ns
(4)
tRO
Output Rise Time
50
50
ns
(4)
tFO
Output Fall Time
ns
NOTES:
4. This parameter is periodically sampled and not 100% tested.
5. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
FN8126.2
14
March 16, 2006
X5043, X5045
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
SO
tV
tHO
tWL
tDIS
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
Serial Input Timing
tCS
CS
SCK
SI
tLEAD
tLAG
tSU
tH
tRI
tFI
MSB In
LSB In
High Impedance
SO
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8126.2
15
March 16, 2006
X5043, X5045
Power-Up and Power-Down Timing
VTRIP
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tRPD
tR
RESET (X5043)
RESET (X5045)
RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset Trip Point Voltage, (-4.5A)
4.5
4.62
4.38
2.92
2.62
4.75
4.5
V
Reset Trip Point Voltage, (Blank)
4.25
2.85
2.55
Reset Trip Point Voltage, (-2.7A)
Reset Trip Point Voltage, (-2.7)
3.0
2.7
tPURST
Power-up Reset Time Out
VCC Detect to Reset/Output
VCC Fall Time
100
200
400
500
ms
ns
µs
ns
V
(6)
tRPD
(6)
tF
10
0.1
1
(6)
tR
VCC Rise Time
VRVALID
Reset Valid VCC
NOTE:
6. This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
tCST
RESET
(5043)
tWDO
tRST
tWDO
tRST
RESET
(5045)
RESET/RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tWDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (default)
WD1 = 1, WD0 = 0
OFF
200
600
1.4
100
450
1
300
800
2
ms
ms
sec
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
tCST
tRST
CS Pulse Width to Reset the Watchdog
Reset Time Out
400
100
ns
200
400
ms
FN8126.2
March 16, 2006
16
X5043, X5045
V
Programming Timing Diagram
TRIP
VCC
(VTRIP
VTRIP
)
tTHD
tTSU
VP
WP
tVPH
tVPS
tVPO
tPCS
CS
tRP
SCK
SI
06h
02h
01h or
03h
V
Programming Parameters
TRIP
PARAMETER
DESCRIPTION
MIN
1
MAX
UNIT
µs
tVPS
VTRIP Program Enable Voltage Setup time
VTRIP Program Enable Voltage Hold time
VTRIP Programming CS inactive time
VTRIP Setup time
tVPH
1
µs
tPCS
1
µs
tTSU
1
µs
tTHD
VTRIP Hold (stable) time
10
ms
ms
µs
tWC
VTRIP Write Cycle Time
10
tVPO
VTRIP Program Enable Voltage Off time (Between successive adjustments)
VTRIP Program Recovery Period (Between successive adjustments)
Programming Voltage
0
tRP
10
15
1.7
-25
ms
V
VP
18
VTRAN
Vtv
VTRIP Programmed Voltage Range
4.75
+25
V
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8126.2
17
March 16, 2006
X5043, X5045
Packaging Information
8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
0.0256 (0.65) Typ.
(0.30 + 0.15 / -0.05)
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
7° Typ.
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.0256" Typical
0.025"
Typical
0.150 (3.81)
0.007 (0.18)
0.005 (0.13)
Ref.
0.193 (4.90)
Ref.
0.220"
0.020"
Typical
8 Places
FOOTPRINT
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
FN8126.2
18
March 16, 2006
X5043, X5045
Packaging Information
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
FN8126.2
19
March 16, 2006
X5043, X5045
Packaging Information
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.050 (1.27)
0.010 (0.25)
0.010 (0.25)
0.020 (0.50)
0.050"Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8126.2
20
March 16, 2006
X5043, X5045
Packaging Information
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8126.2
21
March 16, 2006
P r i n t e r F r i e n d l y V e r s i o n
X 5 0 4 3
CP U S u pe r vis or wi th 4 k SP I E EP R OM
D a t a s h e e t s ,
R e l a t e d D o c s
& S i m u l a t i o n s
D e s c r i p t i o n
K ey
F e a t u r e s
P a r a m e t r i c
D a t a
A p p l i c a t i o n
D i a g r a m s
R e l a t e d
D e v i c e s
Or d er in g I nf o r m at io n
De s ig n - In
P r i c e
Pa r t N o.
S t a t u s
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
Te m p.
C o m m
C o m m
C o m m
P a c k a g e
8 L d M SO P
8 L d M SO P
8 L d M SO P
M SL US $
X5 0 4 3 M8
1
1
1
1
1
1
1
1
1
1
1
1
2 . 4 6
2 . 4 6
2 . 4 6
2 . 4 6
2 . 4 6
2 . 5 5
2 . 5 5
2 . 5 5
2 . 5 5
2 . 5 5
2 . 5 5
2 . 5 5
X5 0 4 3 M8 -2 . 7
X5 04 3M 8 - 2. 7A
X 50 43M 8-2 .7A T 1
X5 04 3M 8 - 4. 5A
X5 0 4 3 M8 I
C o m m 8 L d M S OP T +R
C o m m
I n d
8 L d M SO P
8 L d M SO P
X 50 43 M8I - 2.7
X5 0 4 3 M8 I -2 . 7 A
X 5043 M8I- 2.7A T1
X5 0 4 3 M8 I -2 . 7 T1
X5 0 4 3 M8 I -2 . 7 T2
X5 0 4 3 M8 I -4 . 5 A
I n d
8 L d M SO P
I n d
8 L d M SO P
I n d
8 L d M S OP T +R
8 L d M S OP T +R
8 L d M S OP T +R
8 L d M SO P
I n d
I n d
I
n
d
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
A ct i v e
I n d
I n d
8 L d M SO P
8 L d M SO P
2
2
2
2
2
2
2
2
2
2
2 . 5 5
2 . 5 5
2 . 5 5
2 . 5 5
2 . 5 5
2 . 5 5
2 . 4 6
2 . 4 6
2 . 4 6
2 . 4 6
X5 0 4 3 M8 IZ
X 5043M8IZ -2. 7
X5 0 43 M 8 I Z- 2. 7 A
X 504 3M8 IZ -2 .7A T1
X 5 043 M 8I Z- 2 .7 T1
X5 0 43 M 8 I Z- 4. 5 A
X5043M 8Z
I n d
8
L
d
M
S
O
P
I n d
8 L d M S OP T +R
8 L d M S OP T +R
8 L d M SO P
I n d
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T h e p r ic e li st e d i s t h e m an uf a ct ur e r 's sugg ested r et ail pr i ce f or q uant it i es bet w ee n 1 00 a n d
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MS L = M o i s t u r e S e n s i t i v i t y L e v e l - p e r I P C / J E D E C J - S T D - 0 2 0
SMD = S t a n d a r d M i c r o c i r c u i t D r a w i n g
D esc rip ti on
T h e s e d e v i c e s c o m b i n e f o u r p o p u l a r f u n c t i o n s , P o w e r o n R e s e t C o n t r o l , W a t c h d o g T i m e r , S u p p l y
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c o m b i n a t i o n l o w e r s s y s t e m c o s t , r e d u c e s b o a r d s p a c e r e q u i r e m e n t s , a n d i n c r e a s e s r e l i a b i l i t y .
A p p l y i n g p o w e r t o t h e d e v i c e a c t i v a t e s t h e p o w e r - o n r e s e t c i r c u i t w h i c h h o l d s RE S E T /R E S E T ac ti v e
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e x e c u t e s c o d e .
T h e W a t c h d o g T i m e r p r o v i d e s a n i n d e p e n d e n t p r o t e c t i o n m e c h a n i s m f o r m i c r o c o n t r o l l e r s . W h e n
t h e m i c r o c o n t r o l l e r f a i l s t o r e s t a r t a t i m e r w i t h i n a s e l e c t a b l e t i m e o u t i n t e r v a l , t h e d e v i c e a c t i v a t e s
th e RE S E T / R E S E T s i g n a l . T h e u s e r s e l e c t s t h e i n t e r v a l f r o m t h r e e p r e s e t v a l u e s . O n c e s e l e c t e d ,
t h e i n t e r v a l d o e s n o t c h a n g e , e v e n a f t e r c y c l i n g t h e p o w e r .
T h e d e v i c e ’ s l o w V d e t e c t i o n c i r c u i t r y p r o t e c t s t h e u s e r ’ s s y s t e m f r o m l o w v o l t a g e c o n d i t i o n s ,
C C
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a r e a v a i l a b l e , h o w e v e r , I n t e r s i l ’ s u n i q u e c i r c u i t s a l l o w t h e t h r e s h o l d t o b e r e p r o g r a m m e d t o m e e t
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T h e m e m o r y p o r t i o n o f t h e d e v i c e i s a C M O S S e r i a l E E P R O M a r r a y w i t h I n t e r s i l ’ s b l o c k l o c k
p r o t e c t i o n . T h e a r r a y i s i n t e r n a l l y o r g a n i z e d a s 5 1 2 x 8 . T h e d e v i c e f e a t u r e s a S e r i a l P e r i p h e r a l
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T h e d e v i c e u t i l i z e s I n t e r s i l ’ s p r o p r i e t a r y D i r e c t W r i t e ™ c e l l , p r o v i d i n g a m i n i m u m e n d u r a n c e o f
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K ey Fe a t u r e s
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P a r a m e t r i c D a t a
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S
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C P U S u p e r v i s o r w i t h 1 6 K b i t S P I E E P R O M
C P U S u p e r v i s o r w i t h 1 6 K b i t S P I E E P R O M
C P U S u p e r v i s o r w i t h 1 6 K b i t S P I E E P R O M
C P U S u p e r v i s o r w i t h 1 6 K b i t S P I E E P R O M
C P U S u p e r v i s o r w i t h 3 2 K b S P I E E P R O M
C P U S u p e r v i s o r w i t h 3 2 K b S P I E E P R O M
C P U S u p e r v i s o r w i t h 3 2 K b i t S P I E E P R O M
C P U S u p e r v i s o r w i t h 3 2 K b i t S P I E E P R O M
A b o u t U s | C a r e e r s | C o n t a c t U s | I n v e s t o r s | L e g a l | Pr iv a c y | S ite M ap | S u b s c r i b e | I n t r a n e t
© 2 0 0 7 . A l l r i g h t s r e s e r v e d .
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X5045S8I
暂无描述Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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XICOR
X5045S8I-4.5A-T1
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