X9241AYVIT1 [RENESAS]
QUAD 2K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, TSSOP-20;
| 型号： | X9241AYVIT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | QUAD 2K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, TSSOP-20 光电二极管 转换器 电阻器 |
| 文件： | 总17页 (文件大小：754K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X9241A
FN8164
Rev 7.00
August 17, 2015
Quad Digital Controlled Potentionmeters (XDCP™) Non-Volatile/Low
Power/2-Wire/64 Taps
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
Features
• Four potentiometers in one package
• 2-wire serial interface
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power up
recalls the contents of DR0 to the WCR.
• Register oriented format
- Direct read/write/transfer of wiper positions
- Store as many as four positions per potentiometer
• Terminal Voltages: +5V, -3.0V
• Cascade resistor arrays
• Low power CMOS
• High Reliability
- Endurance–100,000 data changes per bit per register
- Register data retention–100 years
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 16-bytes of nonvolatile memory
• 3 resistor array values
- 2k10k50kor combination
- Cascadable for values of 4kto 200k
• Resolution: 64 taps each pot
• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC
packages
• Pb-free available (RoHS compliant)
Block Diagram
V
V
CC
SS
V
R
/
H2
R0
R2
V
V
/R
R0
R2
R1
R3
R1
R3
H0 H0
WIPER
COUNTER
REGISTER
H2
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 2
(WCR)
/R
V
V
/R
L2 L2
L0 L0
/R
V
/R
W2 W2
W0 W0
SCL
SDA
INTERFACE
AND
CONTROL
CIRCUITRY
A0
A1
A2
A3
8
DATA
V
/R
H1 H1
V
/R
H3 H3
R0
R2
R1
R3
R0
R2
R1
R3
WIPER
COUNTER
REGISTER
(WCR)
WIPER
COUNTER
REGISTER
(WCR)
REGISTER
ARRAY
POT 3
REGISTER
ARRAY
POT 1
V
V
/R
L1 L1
V
V
/R
L3 L3
/R
W1 W1
/R
W3 W3
FN8164 Rev 7.00
August 17, 2015
Page 1 of 17
X9241A
Ordering Information
POTENTIOMETER
ORGANIZATION
(k)
V
LIMITS
(V)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
CC
PART NUMBER
PART MARKING
X9241AMPZ (Note)
(No longer available,
recommended
X9241AMPZ
5 ±10%
2/10/50
0 to +70
20 Ld PDIP***
Pot 0 = 2k
replacement:
X9241AMSZT1)
Pot 1 = 10k
Pot 2 = 10k
X9241AMPIZ (Note)
(No longer available,
recommended
X9241AMPIZ
-40 to +85
20 Ld PDIP***
Pot 3 = 50k
replacement:
X9241AMSZT1)
X9241AMSZ* (Note)
X9241AMSIZ* (Note)
X9241AMVZ (Note)
X9241AMVIZ* (Note)
X9241AWPIZ (Note)
X9241AWSZ* (Note)
X9241AWSIZ* (Note)
X9241AWVZ* (Note)
X9241AWVIZ* (Note)
X9241AMS Z
X9241AMSI Z
X9241AM VZ
X9241AM VIZ
X9241AWPIZ
X9241AWS Z
X9241AWSI Z
X9241AW VZ
X9241AW VIZ
0 to +70
-40 to +85
0 to +70
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
20 Ld TSSOP
20 Ld PDIP
-40 to +85
0 to +70
10
0 to +70
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
20 Ld TSSOP
Pot 0 = 10k
Pot 1 = 10k
-40 to +85
0 to +70
Pot 2 = 10k
Pot 3 = 10k
-40 to +85
X9241AYPZ (Note)
X9241AYPZ
2
0 to +70
20 Ld PDIP***
(No longer available,
recommended
replacement: X9241AYSIZ)
Pot 0 = 2k
Pot 1 = 2k
Pot 2 = 2k
X9241AYSZ* (Note)
X9241AYSIZ* (Note)
X9241AYS Z
X9241AYSI Z
X9241AY VZ
0 to +70
-40 to +85
0 to +70
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
Pot 3 = 2k
X9241AYVZ (Note)
(No longer available,
recommended
replacement: X9241AYVIZ)
X9241AYVIZ* (Note)
X9241AUPZ (Note)
X9241AUPIZ (Note)
X9241AUSZ* (Note)
X9241AUSIZ* (Note)
X9241AY VIZ
X9241AUPZ
X9241AUPIZ
X9241AUS Z
X9241AUSI Z
X9241AU VZ
-40 to +85
0 to +70
20 Ld TSSOP
20 Ld PDIP***
20 Ld PDIP***
20 Ld SOIC
5 ±10%
50
-40 to +85
0 to +70
Pot 0 = 50k
Pot 1 = 50k
Pot 2 = 50k
-40 to +85
0 to +70
20 Ld SOIC
X9241AUVZ* (Note)
(No longer available,
recommended
20 Ld TSSOP
Pot 3 = 50k
replacement:
X9241AUSZT1)
X9241AUVIZ* (Note)
X9241AU VIZ
-40 to +85
20 Ld TSSOP
*Add "T1" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN8164 Rev 7.00
August 17, 2015
Page 2 of 17
X9241A
Pin Descriptions
Host Interface Pins
Serial Clock (SCL)
Pin Names
SYMBOL
DESCRIPTION
V
/R to V /R
,
Potentiometer Pins (terminal equivalent)
H0 H0 H3 H3
V
/R to V /R
L0 L0 L3 L3
The SCL input is used to clock data into and out of the
X9241A.
V
/R
to V /R
Potentiometer Pins (wiper equivalent)
W0 W0 W3 W3
Principles of Operation
Serial Data (SDA)
The X9241A is a highly integrated microcircuit incorporating
four resistor arrays, their associated registers and counters
and the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
Serial Interface
The X9241A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9241A will be considered a slave
device in all applications.
Address
The Address inputs are used to set the least significant
4-bits of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9241A.
Potentiometer Pins
V /R (V /R TO V /R ), V /R (V /R TO V /R
)
H
H
H0 H0 H3 H3 L0 L0 L3 L3
L
L
Clock and Data Conventions
The R and R inputs are equivalent to the terminal
H
L
Data states on the SDA line can change only during SCL LOW
connections on either end of a mechanical potentiometer.
periods (t
). SDA state changes during SCL HIGH are
LOW
reserved for indicating start and stop conditions.
V /R (V /R TO V /R
)
W
W
W0 W0 W3 W3
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Start Condition
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA while SCL
Pinout
is HIGH (t
). The X9241A continuously monitors the SDA
HIGH
X9241A
(20 LD DIP, SOIC, TSSOP)
TOP VIEW
and SCL lines for the start condition and will not respond to any
command until this condition is met.
Stop Condition
V
/R
W0 W0
1
20
19
18
17
16
15
14
13
12
11
V
CC
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH.
V
/R
L0 L0
2
V
V
/R
W3 W3
V
/R
H0 H0
3
/R
L3 L3
Acknowledge
A0
A2
4
V
/R
H3 H3
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices on
the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will release
the SDA bus after transmitting 8-bits. The master generates a
ninth clock cycle and during this period the receiver pulls the
SDA line LOW to acknowledge that it successfully received the
8-bits of data. See Figure 7.
5
A1
X9241A
V
/R
W1 W1
6
A3
SCL
V
V
/R
L1 L1
7
V
/R
8
/R
H1 H1
W2 W2
SDA
9
V
/R
L2 L2
V
/R
H2 H2
V
10
SS
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address and once
again after successful receipt of the command byte. If the
command is followed by a data byte the X9241A will respond
with a final acknowledge.
Pin Names
SYMBOL
DESCRIPTION
SCL
Serial Clock
Serial Data
Address
SDA
Array Description
A0 to A3
The X9241A is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
FN8164 Rev 7.00
August 17, 2015
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X9241A
series. The physical ends of each array are equivalent to the
Flow 1. ACK Polling Sequence
fixed terminals of a mechanical potentiometer (V /R and
H
H
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
V /R inputs).
L
L
At both ends of each array and between each resistor segment
is a FET switch connected to the wiper (V /R ) output. Within
W
W
each individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper Counter
Register (WCR). The 6 least significant bits of the WCR are
decoded to select, and enable, 1 of 64 switches.
ISSUE
START
ISSUE SLAVE
ADDRESS
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
ISSUE STOP
ACK
NO
RETURNED?
Device Addressing
Following a start condition the master must output the address
of the slave it is accessing. The most significant
YES
4-bits of the slave address are the device type identifier (refer
to Figure 1). For the X9241A, this is fixed as 0101[B].
NO
FURTHER
OPERATION?
DEVICE TYPE
IDENTIFIER
YES
ISSUE
ISSUE STOP
PROCEED
INSTRUCTION
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
PROCEED
FIGURE 1. SLAVE ADDRESS
Instruction Structure
The next 4-bits of the slave address are the device address.
The physical device address is defined by the state of the A0 to
A3 inputs. The X9241A compares the serial data stream with
the address input state; a successful compare of all 4 address
bits is required for the X9241A to respond with an
acknowledge.
The next byte sent to the X9241A contains the instruction and
register pointer information. The 4 most significant bits are the
instruction. The next 4-bits point to one of four pots and when
applicable they point to one of four associated registers. The
format is in Figure 2.
POTENTIOMETER
SELECT
Acknowledge Polling
The disabling of the inputs, during the internal nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command, the X9241A
initiates the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition followed
by the device slave address. If the X9241A is still busy with the
write operation, no ACK will be returned. If the X9241A has
completed the write operation, an ACK will be returned and the
master can then proceed with the next operation.
I3
I2
I1
I0
P1
P0
R1
R0
INSTRUCTIONS
REGISTER
SELECT
FIGURE 2. INSTRUCTION BYTE FORMAT
The 4 high order bits define the instruction. The next 2-bits (P1
and P0) select which one of the four potentiometers is to be
affected by the instruction. The last 2-bits (R1 and R0) select
one of the four registers that are to be acted upon when a
register oriented instruction is issued.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure 3.
These two-byte instructions exchange data between the WCR
and one of the data registers. A transfer from a Data Register to
a WCR is essentially a write to a static RAM. The response of
FN8164 Rev 7.00
August 17, 2015
Page 4 of 17
X9241A
the wiper to this action will be delayed t
WCR current wiper position to a Data Register is a write to
nonvolatile memory and takes a minimum of t to complete.
The transfer can occur between one of the four potentiometers
and one of its associated registers; or it may occur globally,
wherein the transfer occurs between all four of the
. A transfer from
value to the selected Data Register. The sequence of
operations is shown in Figure 4.
STPWV
WR
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9241A has
responded with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL
potentiometers and one of their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position of
the selected pot; Write WCR, change current wiper position of
the selected pot; Read Data Register, read the contents of the
selected nonvolatile register; Write Data Register, write a new
clock pulse (t
) while SDA is HIGH, the selected wiper will
HIGH
move one resistor segment towards the V /R terminal.
Similarly, for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards the
H
H
V /R terminal. A detailed illustration of the sequence and
L
L
timing for this operation is shown in Figures 5 and 6
respectively.
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3
I2
I1 I0
P1 P0 R1 R0
A
C
K
S
T
O
P
A
C
K
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0
P1 P0 R1 R0
DW D5 D4 D3 D2
S
T
O
P
A
C
K
A
C
K
CM
D1 D0
A
C
K
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
X
X
A
C
K
S
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0
P1 P0 R1 R0
A
C
K
I
I
I
D
E
C
1
D
S
T
N
C
1
N
C
2
N
C
n
E
C
n
T
O
P
A
R
T
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
FN8164 Rev 7.00
August 17, 2015
Page 5 of 17
X9241A
INC/DEC
CMD
ISSUED
t
CLWV
SCL
SDA
VOLTAGE OUT
V
/R
W
W
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
TABLE 1. INSTRUCTION SET
INSTRUCTION FORMAT
INSTRUCTION
I
I
I
I
P
P
R
R
0
OPERATION
Read the contents of the Wiper Counter Register pointed to by P to P
3
2
1
0
1
0
1
Read WCR
1
0
0
1
1/0
1/0
X
X
1
0
(Note 1)
(Note 2)
Write WCR
1
1
0
0
1
1
0
1
1/0
1/0
1/0
1/0
X
X
Write new value to the Wiper Counter Register pointed to by P to P
1 0
Read Data
Register
1/0
1/0 Read the contents of the Register pointed to by P to P and R to R
1 0 1 0
Write Data
Register
1
1
1
0
1
1
1
0
0
0
1
0
0
1
0
1
1/0
1/0
1/0
X
1/0
1/0
1/0
X
1/0
1/0
1/0
1/0
1/0 Write new value to the Register pointed to by P to P and R to R
1 0 1 0
XFR Data
Register to WCR
1/0 Transfer the contents of the Register pointed to by P to P and R to
1 0 1
R to its associated WCR
0
XFR WCR to
Data Register
1/0 Transfer the contents of the WCR pointed to by P to P to the Register
1 0
pointed to by R to R
1
0
Global XFR
Data Register to
WCR
1/0 Transfer the contents of the Data Registers pointed to by R to R of all
1 0
four pots to their respective WCR
Global XFR
WCR to Data
Register
1
0
0
0
0
1
0
0
X
X
1/0
X
1/0 Transfer the contents of all WCRs to their respective data Registers
pointed to by R to R of all four pots
1
0
Increment/
Decrement
Wiper
1/0
1/0
X
Enable Increment/decrement of the WCR pointed to by P to P
1 0
NOTES:
1. 1/0 = data is one or zero
2. X = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical).
FN8164 Rev 7.00
August 17, 2015
Page 6 of 17
X9241A
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8164 Rev 7.00
August 17, 2015
Page 7 of 17
X9241A
The WCR is a volatile register; that is, its contents are lost
when the X9241A is powered-down. Although the register is
automatically loaded with the value in DR0 upon power-up, it
should be noted this may be different from the value present at
power-down.
Detailed Operation
All four XDCP potentiometers share the serial interface and
share a common architecture. Each potentiometer is
comprised of a resistor array, a Wiper Counter Register and
four Data Registers. A detailed discussion of the register
organization and array operation follows.
Data Registers
Each potentiometer has four nonvolatile Data Registers. These
can be read or written directly by the host and data can be
transferred between any of the four Data Registers and the
WCR. It should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take a
maximum of 10ms.
Wiper Counter Register
The X9241A contains four volatile Wiper Counter Registers
(WCR), one for each XDCP potentiometer. The WCR can be
envisioned as a 6-bit parallel and serial load counter with its
outputs decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered in four
ways: it may be written directly by the host via the Write WCR
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction (parallel load);
it can be modified one step at a time by the
If the application does not require storage of multiple settings
for the potentiometer, these registers can be used as regular
memory locations that could possibly store system parameters
or user preference data.
increment/decrement instruction; finally, it is loaded with the
contents of its Data Register zero (DR0) upon power-up.
SERIAL DATA PATH
SERIAL
BUS
INPUT
V /R
H
H
FROM INTERFACE
CIRCUITRY
REGISTER 0
REGISTER 1
PARALLEL
BUS
INPUT
8
6
C
O
U
N
T
WIPER
COUNTER
REGISTER
E
R
REGISTER 2
REGISTER 3
D
E
C
O
D
E
2
INC/DEC
LOGIC
UP/DN
IF WCR = 00[H] THEN V /R = V /R
W
W
L
L
UP/DN
IF WCR = 3F[H] THEN V /R = V /R
V /R
W
W
H
H
MODIFIED SCL
L
L
CLK
DW
CASCADE
CONTROL
LOGIC
V
/R
W
W
CM
FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM
FN8164 Rev 7.00
August 17, 2015
Page 8 of 17
X9241A
When operating in cascade mode V /R , V /R and the wiper
Cascade Mode
H
H
L
L
terminals of the cascaded arrays must be electrically
connected externally. All but one of the wipers must be
disabled. The user can alter the wiper position by writing
directly to the WCR or indirectly by transferring the contents of
the Data Registers to the WCR or by using the
Increment/Decrement command.
The X9241A provides a mechanism for cascading the arrays.
That is, the sixty-three resistor elements of one array may be
cascaded (linked) with the resistor elements of an adjacent
array. The V /R of the higher order array must be connected
L
L
to the V /R of the lower order array (See Figure 9).
H
H
Cascade Control Bits
When using the Increment/Decrement command the wiper
position will automatically transition between arrays. The
current position of the wiper can be determined by reading the
WCR registers; if the DW bit is “0”, the wiper in that array is
active. If the current wiper position is to be maintained on
power-down a global XFR WCR to Data Register command
must be issued to store the position in NV memory before
power-down.
The data byte, for the three-byte commands, contains 6-bits
(LSBs) for defining the wiper position plus 2 high order bits, CM
(Cascade Mode) and DW (Disable Wiper, normal operation).
The state of the CM bit (bit 7 of WCR) enables or disables
cascade mode. When the CM bit of the WCR is set to “0” the
potentiometer is in the normal operation mode. When the CM
bit of the WCR is set to “1” the potentiometer is cascaded with
its adjacent higher order potentiometer. For example; if bit 7 of
WCR2 is set to “1”, pot 2 will be cascaded to pot 3.
It is possible to connect three or all four potentiometers in
cascade mode. It is also possible to connect POT 3 to POT 0
as a cascade. The requirements for external connections of
The state of DW enables or disables the wiper. When the DW
bit (bit 6 of the WCR) is set to “0” the wiper is enabled; when
set to “1” the wiper is disabled. If the wiper is disabled, the
wiper terminal will be electrically isolated and float.
V /R , V /R and the wipers are the same in these cases.
L
L
H
H
V
/R
L0 L0
POT 0
WCR0
V
/R
H0 H0
V /R
W0 W0
V
/R
L1 L1
POT 1
WCR1
V
/R
H1 H1
V /R
W1 W1
V
/R
L2 L2
POT 2
WCR2
V
/R
H2 H2
V /R
W2 W2
V
/R
L3 L3
POT 3
WCR3
V /R
H3 H3
EXTERNAL
=
V /R
W3 W3
CONNECTION
FIGURE 9. CASCADING ARRAYS
FN8164 Rev 7.00
August 17, 2015
Page 9 of 17
X9241A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V ) Limits
CC
X9241A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Temperature under bias. . . . . . . . . . . . . . . . . . . . . . . .-65 to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Max Wiper Current for 2k R
. . . . . . . . . . . . . . . . . . . . . . ±4mA
. . . . . . . . . . . . . . ±3mA
TOTAL
Max Wiper Current for 10k and 50k R
Voltage on SCK, SCL or any address
TOTAL
input with respect to V
. . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
Voltage on any V /R , V /R or V /R
L
Recommended Operating Conditions
H
H
W
W
L
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
referenced to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V/-4V
SS
V = |V /R - V /R |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
H
H
L
L
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Analog Specifications (Over recommended operating conditions unless otherwise stated).
LIMITS
MIN
MAX
SYMBOL
PARAMETER
End to end resistance
Wiper resistance
TEST CONDITION
(Note 11)
TYP
(Note 11)
UNIT
R
-20
+20
130
+5
%
TOTAL
R
Wiper Current = (V - V )/R
TOTAL
40
V
W
H
L
V
Voltage on any V /R , V /R or V /R Pin
-3.0
TERM
H
H
W
W
L
L
Noise
Ref: 1kHz (Note 7)
(Note 7)
120
dBV
Resolution
1.6
%
Absolute linearity (Note 3)
Relative linearity (Note 4)
Temperature coefficient of R
R
R
- R
±1
MI (Note 5)
MI (Note 5)
ppm/°C
ppm/C
pF
w(n)(actual)
w(n)(expected)
- [R ]
w(n) + MI
±0.2
w(n + 1)
(Note 7)
(Note 7)
±300
±20
TOTAL
Ratiometric temperature coefficient
Potentiometer capacitances
C /C /C
See Circuit #3 and (Note 7)
= V . Device is in stand-by mode.
15/15/25
0.1
H
L
W
l
R , R , R leakage current
V
1
µA
AL
H
I
W
IN
TERM
DC Electrical Specifications (Over recommended operating conditions unless otherwise stated.)
LIMITS
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITION
(Note 11)
TYP
(Note 11)
UNIT
l
Supply current (active)
f
= 100kHz, Write/Read to WCR,
SCL
3
mA
CC
Other Inputs = V
SS
SCL = SDA = V , Addr. = V
SS
I
V
current (standby)
200
500
10
µA
µA
µA
V
SB
CC
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
V
V
= V to V
SS
LI
IN
CC
CC
I
= V to V
SS
10
LO
OUT
V
2
IH
V
0.8
0.4
V
IL
V
I
= 3mA
OL
V
OL
NOTES:
3. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
4. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
5. MI = RTOT/63 or (R – R )/63, single pot
H
L
6. Max = all four arrays cascaded together, Typical = individual array resolutions.
FN8164 Rev 7.00
August 17, 2015
Page 10 of 17
X9241A
Endurance and Data Retention
PARAMETER
MIN
100,000
100
UNIT
Data changes per bit per register
Years
Minimum endurance
Data retention
Capacitance
SYMBOL
PARAMETER
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
TEST CONDITION
TYP
19
UNIT
pF
C
(Note 7)
(Note 7)
V
= 0V
= 0V
I/O
I/O
C
V
12
pF
IN
IN
Power-up Timing
MIN
MAX
SYMBOL
PARAMETER
Power-up to initiation of read operation
(Note 8) Power-up to initiation of write operation
(Note 11)
TYP
(Note 11)
UNIT
t
(Note 8)
1
5
ms
ms
PUR
t
PUW
t V
V Power up ramp rate
CC
0.2
50
V/ms
R
CC
Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V , then the potentiometer pins. It is suggested that Vcc reach 90% of its
CC
final value before power is applied to the potentiometer pins. The V
ramp rate specification should be met, and any glitches or
CC
line should be held to <100mV if possible. Also, V
slope changes in the V
should not reverse polarity by more than 0.5V.
CC
CC
NOTES:
7. Limits should be considered typical and are not production tested.
8. Limits established by characterization and are not production tested.
9. Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
10. T value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse width that
i
is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device.
11. Parts are 100% tested at either +70°C or +85°C. Over temperature limits established by characterization and are not production tested.
Symbol Table
AC Conditions of Test
Input pulse levels
WAVEFORM
INPUTS
OUTPUTS
V
x 0.1 to V
x 0.9
x 0.9
CC
CC
CC
Must be
steady
Will be
steady
Input rise and fall times
Input and output timing levels
Input pulse levels
10ns
V
V
x 0.5
CC
CC
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
x 0.1 to V
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8164 Rev 7.00
August 17, 2015
Page 11 of 17
X9241A
Equivalent AC Test Circuit
Guidelines for Calculating
Typical Values of Bus Pull-Up Resistors
5V
120
V
CC MAX
R
=
=1.8k
MIN
1533
100
80
I
OL MIN
T
R
R
=
MAX
SDA OUTPUT
C
BUS
MAXIMUM
RESISTANCE
60
40
20
0
100pF
MIN.
RESISTANCE
0
20
40
60
80
100
120
BUS CAPACITANCE (pF)
Circuit #3 SPICE Macro Model
DCP Wiper Current De-rating Curve
7
6
MACRO MODEL
R
TOTAL
R
R
H
L
5
4
3
2
1
0
C
C
L
H
15pF
C
W
15pF
25pF
R
W
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE (°C)
t
t
F
t
t
LOW
R
HIGH
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA
(DATA IN)
t
BUF
FIGURE 10. INPUT BUS TIMING
AC Electrical Specifications (Over recommended operating conditions unless otherwise stated).
LIMITS
REFERENCE
FIGURE
MIN
MAX
SYMBOL
PARAMETER
(Note 11)
(Note 11)
UNIT
kHz
ns
NUMBER(S)
f
SCL clock frequency
Clock LOW period
0
100
10
SCL
t
4700
4000
10
10
LOW
t
Clock HIGH period
SCL and SDA rise time
SCL and SDA fall time
ns
HIGH
t
1000
300
20
ns
10
R
t
ns
10
F
,
T (Note 11)
Noise suppression time constant (glitch filter)
Start condition setup time (for a repeated start condition)
Start condition hold time
ns
10
i
t
4000
4000
ns
10 and 12
10 and 12
SU:STA
t
ns
HD:STA
FN8164 Rev 7.00
August 17, 2015
Page 12 of 17
X9241A
AC Electrical Specifications (Over recommended operating conditions unless otherwise stated). (Continued)
LIMITS
REFERENCE
FIGURE
MIN
MAX
SYMBOL
PARAMETER
(Note 11)
(Note 11)
UNIT
ns
NUMBER(S)
t
Data in setup time
Data in hold time
250
0
10
SU:DAT
t
ns
10
HD:DAT
t
SCL LOW to SDA data out valid
Data out hold time
3500
ns
11
AA
t
30
ns
11
DH
t
t
Stop condition setup time
4000
4700
ns
10 and 12
SU:STO
t
Bus free time prior to new transmission
Write cycle time (nonvolatile write operation)
Wiper response time from stop generation
Wiper response from SCL LOW
ns
10
13
13
6
BUF
t
10
ms
µs
WR
STPWV
500
t
1000
µs
CLWV
SCL
t
t
DH
AA
SDA
(ACK)
SDA
OUT
SDA
OUT
SDA
OUT
FIGURE 11. OUTPUT BUS TIMING
START CONDITION
STOP CONDITION
SCL
SDA
t
t
t
HD:STA
SU:STO
SU:STA
(DATA IN)
FIGURE 12. START STOP TIMING
SCL
SDA
CLOCK 8
CLOCK 9
ACK
STOP
START
t
WR
t
STPWV
SDA
IN
WIPER
OUTPUT
FIGURE 13. WRITE CYCLE AND WIPER RESPONSE TIMING
FN8164 Rev 7.00
August 17, 2015
Page 13 of 17
X9241A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
August 17, 2015
FN8164.7
- Ordering Information Table on page 2.
- Added Revision History beginning with Rev 1.
- Added About Intersil Verbiage.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at
www.intersil.com/support
FN8164 Rev 7.00
August 17, 2015
Page 14 of 17
X9241A
Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
D
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
E
E1
B
±0.05
0.20 C B A
+0.05/-0.06
+0.05/-0.06
±0.10
2X
1
(N/2)
N/2 LEAD TIPS
c
TOP VIEW
D
E
Basic
E1
e
±0.10
0.05
H
Basic
e
C
L
±0.15
L1
Reference
Rev. F 2/07
SEATING
PLANE
0.10 M C A B
b
NOTES:
0.10 C
N LEADS
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN8164 Rev 7.00
August 17, 2015
Page 15 of 17
X9241A
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8164 Rev 7.00
August 17, 2015
Page 16 of 17
X9241A
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
© Copyright Intersil Americas LLC 2005-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8164 Rev 7.00
August 17, 2015
Page 17 of 17
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