X9317TM8Z-2.7-T1_技术文档

X9317

Low Noise, Low Power, 100 Taps

Data Sheet

March 7, 2012

FN8183.7

Digitally Controlled Potentiometer

(XDCP™)

Features

• Solid-State Potentiometer

• 3-Wire Serial Up/Down Interface

• 100 Wiper Tap Points

The Intersil X9317 is a digitally controlled potentiometer

(XDCP™). The device consists of a resistor array, wiper

switches, a control section, and nonvolatile memory. The

wiper position is controlled by a 3-wire interface.

- Wiper Position Stored in Nonvolatile Memory and

Recalled on Power-up

The potentiometer is implemented by a resistor array

composed of 99 resistive elements and a wiper switching

network. Between each element and at either end are tap

points accessible to the wiper terminal. The position of the

wiper element is controlled by the CS, U/D, and INC inputs.

The position of the wiper can be stored in nonvolatile

memory and then be recalled upon a subsequent power-up

operation.

• 99 Resistive Elements

- Temperature Compensated

- End-to-end Resistance Range ±20%

• Low Power CMOS

- V

CC

= 2.7V to 5.5V, and 5V ±10%

- Standby Current <5µA

• High Reliability

The device can be used as a three-terminal potentiometer

for voltage control or as a two-terminal variable resistor for

current control in a wide variety of applications.

- Endurance, 100,000 Data Changes per Bit

- Register Data Retention, 100 years

• R

TOTAL

Values = 1kΩ, 10kΩ, 50kΩ, 100kΩ

Pinouts

• Packages

- 8 Ld SOIC, PDIP, TSSOP, and MSOP

X9317

(8 LD TSSOP)

TOP VIEW

• Pb-Free Available (RoHS Compliant)

Applications

R

CS

1

2

3

4

8

7

6

5

L

• LCD Bias Control

V

R

V

CC

INC

U/D

W

X9317

• DC Bias Adjustment

• Gain and Offset Trim

• Laser Diode Bias Control

• Voltage Regulator Output Control

SS

R

H

X9317

(8 LD PDIP, 8 LD SOIC, 8 LD MSOP)

TOP VIEW

V

INC

U/D

1

2

3

4

8

7

6

5

CC

CS

X9317

R

L

R

H

V

R

SS

W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

1

All other trademarks mentioned are the property of their respective owners.

X9317

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

V

LIMITS

(V)

R

TEMPERATURE

RANGE (°C)

PKG.

DWG. #

CC

TOTAL

(kΩ)

PART MARKING

DDA

PACKAGE

8 Ld MSOP

X9317ZM8Z

5 ±10%

1

0 to +70

-40 to +85

0 to +70

M8.118

X9317ZM8IZ

DCY

8 Ld MSOP

8 Ld SOIC

M8.118

M8.15E

M8.173

M8.118

M8.15E

M8.173

M8.118

M8.15E

M8.173

M8.118

M8.15E

M8.173

M8.118

M8.15E

M8.173

M8.118

M8.15E

M8.173

M8.118

M8.15E

M8.173

X9317ZS8Z

X9317Z Z

X9317Z Z I

9317Z Z

9317Z IZ

DCW

X9317ZS8IZ

-40 to +85

0 to +70

8 Ld SOIC

X9317ZV8Z

8 Ld TSSOP

8 Ld MSOP

8 Ld SOIC

X9317ZV8IZ

-40 to +85

0 to +70

X9317WM8Z

X9317WM8IZ

X9317WS8Z

10

DCT

-40 to +85

0 to +70

X9317W Z

X9317W ZI

9317W Z

9317W IZ

DCS

X9317WS8IZ

X9317WV8Z

-40 to +85

0 to +70

8 Ld SOIC

8 Ld TSSOP

8 Ld MSOP

8 Ld SOIC

X9317WV8IZ

X9317UM8Z

-40 to +85

0 to +70

X9317UM8IZ

X9317US8Z

DCR

-40 to +85

0 to +70

X9317U Z

X9317U ZI

9317U Z

9317U IZ

DCN

50

X9317US8IZ

-40 to +85

0 to +70

8 Ld SOIC

X9317UV8Z

8 Ld TSSOP

8 Ld MSOP

8 Ld SOIC

X9317UV8IZ

-40 to +85

0 to +70

X9317TM8Z

100

X9317TM8IZ

DCL

-40 to +85

0 to +70

X9317TS8Z

X9317T Z

X9317T ZI

9317T Z

9317T IZ

AOA

X9317TS8IZ

-40 to +85

0 to +70

8 Ld SOIC

X9317TV8Z

8 Ld TSSOP

8 Ld MSOP

8 Ld SOIC

X9317TV8IZ

-40 to +85

0 to +70

X9317ZM8Z-2.7

X9317ZM8IZ-2.7

X9317ZS8Z-2.7

X9317ZS8IZ-2.7

X9317ZV8Z-2.7

X9317ZV8IZ-2.7

X9317WM8Z-2.7

X9317WM8IZ-2.7

X9317WS8Z-2.7

X9317WS8IZ-2.7

X9317WV8Z-2.7

X9317WV8IZ-2.7

X9317UM8Z-2.7

X9317UM8IZ-2.7

X9317US8Z-2.7

X9317US8IZ-2.7

X9317UV8Z-2.7

X9317UV8IZ-2.7

2.7 to 5.5

1

DCZ

-40 to +85

0 to +70

X9317Z ZF

X9317Z ZG

9317Z FZ

9317Z GZ

DCX

-40 to +85

0 to +70

8 Ld SOIC

8 Ld TSSOP

8 Ld MSOP

8 Ld SOIC

-40 to +85

0 to +70

10

DCU

-40 to +85

0 to +70

X9317W ZF

X9317W ZG

9317W FZ

AKZ

-40 to +85

0 to +70

8 Ld SOIC

8 Ld TSSOP

8 Ld MSOP

8 Ld SOIC

-40 to +85

0 to +70

AOB

AOH

-40 to +85

0 to +70

X9317U ZF

X9317U ZG

9317U FZ

9317U GZ

-40 to +85

0 to +70

8 Ld SOIC

8 Ld TSSOP

-40 to +85

FN8183.7

March 7, 2012

2

X9317

Ordering Information (Continued)

PART NUMBER

(Notes 1, 2, 3)

V

LIMITS

(V)

R

TEMPERATURE

RANGE (°C)

PKG.

DWG. #

CC

TOTAL

(kΩ)

PART MARKING

DCP

PACKAGE

8 Ld MSOP

X9317TM8Z-2.7

2.7 to 5.5

100

0 to +70

-40 to +85

0 to +70

M8.118

X9317TM8IZ-2.7

X9317TS8Z-2.7

X9317TS8IZ-2.7

X9317TV8Z-2.7

X9317TV8IZ-2.7

NOTES:

DCM

8 Ld MSOP

8 Ld SOIC

M8.118

M8.15E

M8.173

X9317T ZF

X9317T ZG

9317T FZ

9317T GZ

-40 to +85

0 to +70

8 Ld SOIC

8 Ld TSSOP

-40 to +85

1. Add “-T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for X9317. For more information on MSL please see tech brief TB363.

Block Diagram

U/D

INC

CS

R

99

H

UP/DOWN

COUNTER

V

(SUPPLY VOLTAGE)

CC

98

97

96

R

UP/DOWN

(U/D)

H

7-BIT

NONVOLATILE

MEMORY

ONE

OF

ONE

CONTROL

AND

MEMORY

INCREMENT

W

(

INC)

WIPER

SWITCHES

RESISTOR

ARRAY

HUNDRED

DECODER

DEVICE SELECT

CS)

(

R

L

2

STORE AND

RECALL

CONTROL

CIRCUITRY

V

(GROUND)

1

0

SS

V

CC

SS

GENERAL

R

L

W

DETAILED

Pin Descriptions

PDIP/SOIC/MSOP

TSSOP

SYMBOL

INC

BRIEF DESCRIPTION

1

2

3

4

5

6

7

3

4

5

6

7

8

1

Increment Toggling INC while CS is low moves the wiper either up or down.

Up/Down The U/D input controls the direction of the wiper movement.

U/D

R

The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.

Ground

H

V

SS

R

The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.

The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.

W

R

L

CS

Chip Select The device is selected when the CS input is LOW, and de-selected when CS is

high.

8

2

V

Supply Voltage

CC

FN8183.7

March 7, 2012

3

X9317

Absolute Maximum Ratings

Thermal Information

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA

Junction Temperature Under Bias . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

W

R , R , R to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V

Voltage on CS, INC, U/D and V

H

W

L

CC

with Respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

Potentiometer SpecificationsV = Full Range, T = Full Operating Temperature Range, unless otherwise stated.

CC

A

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS/NOTES

(Note 11) (Note 7) (Note 11)

UNIT

R

End-to-end Resistance Tolerance

See “Ordering Information” beginning on

page 2 for values

-20 +20

%

TOTAL

V

/

R /R Terminal Voltage

V

= 0V

V

CC

V

mW

Ω

RH RL

H

L

SS

Power Rating

R

≥ 10kΩ

10

25

TOTAL

R

= 1kΩ

R

Wiper Resistance

I

= [V(R ) - V(R )]/ R

, V

= 5V

200

400

1000

+4.4

W

H

L

TOTAL CC

= [V(R ) - V(R )]/ R

, V

= 2.7V

Ω

H

L

TOTAL CC

I

Wiper Current (Note 8)

Noise (Note 10)

See “Test Circuit” on page 5

Ref: 1kHz

-4.4

mA

dBV

%

W

-120

1

Resolution

Absolute Linearity (Note 4)

V(R ) = V , V(R ) = 0V

CC

-1

+1

MI

H

L

(Note 6)

Relative Linearity (Note 5)

V(R ) = V , V(R ) = 0V

CC

-0.2

+0.2

MI

H

L

(Note 6)

R

Temperature Coefficient (Note 8) V(R ) = V , V(R ) = 0V

CC

±300

±20

ppm/°C

TOTAL

H

L

Ratiometric Temperature Coefficient

(Notes 8, 9)

C /C /C

W

Potentiometer Capacitances

See “Equivalent Circuit” on page 5

10/10/25

pF

H

L

(Note 8)

V

Supply Voltage

X9317

4.5

2.7

5.5

V

CC

X9317-2.7

DC Electrical Specifications

V

= 5V ±10%, T = Full Operating Temperature Range, unless otherwise stated.

CC A

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 11) (Note 7) (Note 11) UNIT

I

V

Active Current (Increment)

CS = V , U/D = V or V and

80

µA

CC1

CC

IL

IH

INC = V /V @ min. t

IL IH

CYC

R , R , R not connected

L

H

W

I

Active Current (Store)

CS = V , U/D = V or V and INC = V

IH IL IH

400

5

µA

CC2

CC

IL

(non-volatile write)

or V . R , R , R not connected

IH

L

H

W

I

Standby Supply Current

CS ≥ V , U/D and INC = V

IH

SB

IL

R , R , R not connected

L

H

W

I

CS, INC, U/D Input Leakage Current

CS, INC, U/D Input HIGH Voltage

CS, INC, U/D Input LOW Voltage

V

= V to V

SS CC

-10

+10

µA

V

LI

IN

V

x 0.7

V

+ 0.5

CC

IH

CC

V

-0.5

V

x 0.1

CC

V

IL

C

(Note 8) CS, INC, U/D Input Capacitance

V

= 5V, V = V , T = +25°C,

IN SS

10

pF

IN

CC

A

f = 1MHz

FN8183.7

March 7, 2012

4

X9317

Endurance and Data Retention V = 5V ±10%, T = Full Operating Temperature Range.

CC

A

PARAMETER

Minimum Endurance

Data Retention

MIN

100,000

100

UNIT

Data changes per bit

Years

NOTES:

4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R

)-V(R

)]/MI

W(n)(actual)

) - MI)]/MI.

W(n)(expected)

V(R

) = n(V(R )-V(R ))/99 + V(R ), with n from 0 to 99.

W(n)(expected)

H L L

5. Relative linearity is a measure of the error in step size between taps = [V(R

)-(V(R

W(n)

W(n+1)

6. 1 Ml = Minimum Increment = [V(R )-V(R )]/99.

H

L

7. Typical values are for T = +25°C and nominal supply voltage.

A

8. This parameter is not 100% tested.

6

9. Ratiometric temperature coefficient = (V(R

to 99.

)

-V(R

)

)/[V(R (T1-T2) x 10 ], with T1 and T2 being 2 temperatures, and n from 0

)

W T1(n)

W T2(n)

W T1(n)

10. Measured with wiper at tap position 99, R grounded, using test circuit.

L

11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Test Circuit

Equivalent Circuit

AC Conditions of Test

Input pulse levels

0V to 3V

10ns

R

TOTAL

TEST POINT

R

Input rise and fall times

Input reference levels

R

L

H

C

L

C

W

C

1.5V

H

10pF

R

W

FORCE

CURRENT

25pF

10pF

R

W

AC Electrical Specifications

V

= 5V ±10%, T = Full Operating Temperature Range, unless otherwise stated.

CC A

MIN

TYP

MAX

SYMBOL

PARAMETER

(Note 11)

(Note 7)

(Note 11)

UNIT

ns

t

CS to INC Setup

50

100

1

Cl

t

(Note 8)

INC HIGH to U/D Change

U/D to INC Setup

ns

lD

t

µs

DI

t

INC LOW Period

960

1

ns

lL

t

INC HIGH Period

ns

lH

lC

INC Inactive to CS Inactive

CS Deselect Time (STORE)

CS Deselect Time (NO STORE)

µs

t

10

ms

ns

CPHS

t

100

CPHNS

(Note 8)

t

INC to R Change

W

1

5

µs

IW

t

INC Cycle Time

2

CYC

t

INC Input Rise and Fall Time

500

R, F

(Note 8)

t

(Note 8)

Power-up to Wiper Stable

5

µs

PU

t

V

V Power-up Rate

CC

0.2

50

V/ms

R

CC

(Note 8)

t

Store Cycle

5

10

ms

WR

FN8183.7

March 7, 2012

5

X9317

1ms after V

CC

reaches its final value. The V ramp spec is

CC

Power-up and Down Requirements

The recommended power-up sequence is to apply V /V

first, then the potentiometer voltages. During power-up, the

data sheet parameters for the DCP do not fully apply until

always in effect. In order to prevent unwanted tap position

changes, or an inadvertent store, bring the CS and INC high

before or concurrently with the V

CC

CC SS

pin on power-up.

AC Timing

CS

t

CYC

t

CPHNS

t

CPHS

CI

IL

IH

IC

90%

10%

90%

INC

U/D

t

R

ID

DI

F

t

IW

(3)

MI

R

W

Typical Performance Characteristic

0

-50

-100

-150

-200

-250

-300

-350

-55-45-35-25-15 -5

5

15 25 35 45 55 65 75 85 95 105115125

TEMPERATURE (°C)

FIGURE 1. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT

FN8183.7

March 7, 2012

6

X9317

Pin Descriptions

Pin Names

R

AND R

L

SYMBOL

DESCRIPTION

H

The high (R ) and low (R ) terminals of the X9317 are

H

L

R

High terminal

Wiper terminal

Low terminal

Ground

H

equivalent to the fixed terminals of a mechanical

potentiometer. The terminology of R and R references the

R

W

L

H

R

relative position of the terminal in relation to wiper movement

direction selected by the U/D input and not the voltage

potential on the terminal.

L

V

SS

CC

V

Supply voltage

R_W

U/D

INC

CS

Up/Down control input

Increment control input

Chip select control input

R

is the wiper terminal and is equivalent to the movable

w

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the control inputs.

The wiper terminal series resistance is typically 200Ω.

Principles of Operation

UP/DOWN (U/D)

There are three sections of the X9317: the control section,

the nonvolatile memory, and the resistor array. The control

section operates just like an up/down counter. The output of

this counter is decoded to turn on a single electronic switch

connecting a point on the resistor array to the wiper output.

The contents of the counter can be stored in nonvolatile

memory and retained for future use. The resistor array is

comprised of 99 individual resistors connected in series.

Electronic switches at either end of the array and between

each resistor provide an electrical connection to the wiper

The U/D input controls the direction of the wiper movement

and whether the counter is incremented or decremented.

INCREMENT (INC)

The INC input is negative-edge triggered. Toggling INC will

move the wiper and either increment or decrement the

counter in the direction indicated by the logic level on the

U/D input.

CHIP SELECT (CS)

pin, R .

W

The device is selected when the CS input is LOW. The

current counter value is stored in nonvolatile memory when

CS is returned HIGH while the INC input is also HIGH. After

the store operation is complete, the X9317 will be placed in

the low power standby mode until the device is selected

once again.

The wiper acts like its mechanical equivalent and does not

move beyond the first or last position. That is, the counter

does not wrap around when clocked to either extreme.

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions. If

the wiper is moved several positions, multiple taps are

Pin Configuration

connected to the wiper for t (INC to V change). The

IW

W

DIP/SOIC/MSOP

R

value for the device can temporarily be reduced by

TOTAL

a significant amount if the wiper is moved several positions.

V

INC

U/D

1

2

3

4

8

7

6

5

CC

CS

When the device is powered-down, the last wiper position

stored will be maintained in the nonvolatile memory. When

power is restored, the contents of the memory are recalled

and the wiper is set to the value last stored.

X9317

R

L

R

H

V

R

SS

W

Instructions and Programming

TSSOP

The INC, U/D and CS inputs control the movement of the

wiper along the resistor array. With CS set LOW, the device

is selected and enabled to respond to the U/D and INC

inputs. HIGH to LOW transitions on INC will increment or

decrement (depending on the state of the U/D input) a 7-bit

counter. The output of this counter is decoded to select one

of one hundred wiper positions along the resistive array.

R

CS

1

2

3

4

8

7

6

5

L

V

R

V

CC

W

X9317

INC

U/D

SS

R

H

The value of the counter is stored in nonvolatile memory

whenever CS transitions HIGH while the INC input is also

HIGH.

FN8183.7

March 7, 2012

7

X9317

The system may select the X9317, move the wiper and

deselect the device without having to store the latest wiper

position in nonvolatile memory. After the wiper movement is

performed as previously described and once the new

position is reached, the system must keep INC LOW while

taking CS HIGH. The new wiper position will be maintained

until changed by the system or until a power-up/down cycle

recalls the previously stored data.

This procedure allows the system to always power-up to a

preset value stored in nonvolatile memory; then during

system operation minor adjustments could be made. The

adjustments might be based on user preference, system

parameter changes due to temperature drift, etc.

The state of U/D may be changed while CS remains LOW.

This allows the host system to enable the device and then

move the wiper up and down until the proper trim is attained.

Mode Selection

CS

INC

U/D

MODE

L

H

Wiper up

L

Wiper down

H

X

Store wiper position to nonvolatile

memory

H

X

L

X

H

L

Standby

No store, return to standby

Wiper Up (not recommended)

Wiper Down (not recommended)

Applications Information

Electronic digitally controlled (XDCP) potentiometers provide

three powerful application advantages:

1. the variability and reliability of a solid-state potentiometer,

2. the flexibility of computer-based digital controls, and

3. the retentivity of nonvolatile memory used for the storage

of multiple potentiometer settings or data.

FN8183.7

March 7, 2012

8

X9317

Basic Configurations of Electronic Potentiometers

V

REF

R

H

R

W

R

L

I

THREE TERMINAL POTENTIOMETER;

VARIABLE VOLTAGE DIVIDER

TWO TERMINAL VARIABLE RESISTOR;

VARIABLE CURRENT

Basic Circuits

SINGLE SUPPLY INVERTING AMPLIFIER

BUFFERED REFERENCE VOLTAGE

CASCADING TECHNIQUES

R

1

+V

+5V

+V

R

2

1

+5V

V

S

R

LMC7101

V

W

+

-

V

REF

X

OUT

R

W

-

100k

V

O

+V

+

+5V

LMC7101

100k

R

V

= V /R

W W

W

OUT

(a)

(b)

V = (R2/R1)V

O S

VOLTAGE REGULATOR

317

OFFSET VOLTAGE ADJUSTMENT

COMPARATOR WITH HYSTERESIS

LT311A

R

2

1

V

(REG)

O

IN

V

-

S

V

O

+5V

R

1

100kΩ

+

-

V

O

+

I

adj

R

2

LMC7101

10kΩ

R

2

1

10kΩ

V

= {R /(R +R )} V (max)

1 1 2 O

UL

LL

V

(REG) = 1.25V (1+R /R )+I

R

adj 2

= {R /(R +R )} V (min)

O

2

1

1 1 2 O

+5V

FN8183.7

March 7, 2012

9

X9317

Package Outline Drawing

M8.118

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 7/11

5

3.0±0.05

A

DETAIL "X"

D

8

1.10 MAX

SIDE VIEW 2

0.09 - 0.20

4.9±0.15

3.0±0.05

5

0.95 REF

PIN# 1 ID

1

2

B

0.65 BSC

GAUGE

PLANE

TOP VIEW

0.25

3°±3°

0.55 ± 0.15

DETAIL "X"

0.85±010

H

C

SEATING PLANE

0.10 C

0.25 - 0.36

0.10 ± 0.05

0.08

C A-B D

M

SIDE VIEW 1

(5.80)

NOTES:

1. Dimensions are in millimeters.

(4.40)

(3.00)

2. Dimensioning and tolerancing conform to JEDEC MO-187-AA

and AMSEY14.5m-1994.

3. Plastic or metal protrusions of 0.15mm max per side are not

included.

(0.65)

4. Plastic interlead protrusions of 0.15mm max per side are not

included.

(0.40)

(1.40)

5. Dimensions are measured at Datum Plane "H".

6. Dimensions in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

FN8183.7

March 7, 2012

10

X9317

Package Outline Drawing

M8.173

8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 2, 01/10

A

2

4

3.0 ±0.5

SEE DETAIL "X"

8

5

6.40

C

4.40 ±0.10

L

3

4

PIN 1

ID MARK

1

4

0.20 CBA

B

0.09-0.20

0.65

TOP VIEW

END VIEW

1.00 REF

0.05

H

C

0.90 +0.15/-0.10

1.20 MAX

6

SEATING

PLANE

GAUGE

PLANE

0.25

0.25 +0.05/-0.06

0.10 C B A

0.10 C

0°-8°

0.60 ±0.15

0.05 MIN

0.15 MAX

DETAIL "X"

SIDE VIEW

(1.45)

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimension does not include mold flash, protrusions or

gate burrs. Mold flash, protrusions or gate burrs shall

not exceed 0.15 per side.

(5.65)

PACKAGE BODY

OUTLINE

3. Dimension does not include interlead flash or protrusion.

Interlead flash or protrusion shall not exceed 0.15 per side.

4. Dimensions are measured at datum plane H.

5. Dimensioning and tolerancing per ASME Y14.5M-1994.

6. Dimension on lead width does not include dambar protrusion.

Allowable protrusion shall be 0.08 mm total in excess of

dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm.

(0.35 TYP)

(0.65 TYP)

TYPICAL RECOMMENDED LAND PATTERN

7. Conforms to JEDEC MO-153, variation AC. Issue E

FN8183.7

March 7, 2012

11

X9317

Package Outline Drawing

M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09

4

4.90 ± 0.10

A

DETAIL "A"

0.22 ± 0.03

B

6.0 ± 0.20

3.90 ± 0.10

4

PIN NO.1

ID MARK

5

(0.35) x 45°

4° ± 4°

0.43 ± 0.076

1.27

0.25 M C A B

SIDE VIEW “B”

TOP VIEW

1.75 MAX

1.45 ± 0.1

0.25

GAUGE PLANE

C

SEATING PLANE

0.175 ± 0.075

SIDE VIEW “A

0.10 C

0.63 ±0.23

DETAIL "A"

(0.60)

(1.27)

NOTES:

(1.50)

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

(5.40)

4. Dimension does not include interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25mm per side.

The pin #1 identifier may be either a mold or mark feature.

Reference to JEDEC MS-012.

5.

6.

TYPICAL RECOMMENDED LAND PATTERN

FN8183.7

March 7, 2012

12

X9317

Plastic Dual-In-Line Packages (PDIP)

E

N

1

D

PIN #1

INDEX

A2

A

E1

SEATING

PLANE

L

c

A1

NOTE 5

2

N/2

eA

eB

e

b

b2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

INCHES

SYMBOL

PDIP8

0.210

0.015

0.130

0.018

0.060

0.010

0.375

0.310

0.250

0.100

0.300

0.345

0.125

8

PDIP14

0.210

0.015

0.130

0.018

0.060

0.010

0.750

0.310

0.250

0.100

0.300

0.345

0.125

14

PDIP16

0.210

0.015

0.130

0.018

0.060

0.010

0.750

0.310

0.250

0.100

0.300

0.345

0.125

16

PDIP18

PDIP20

0.210

0.015

0.130

0.018

0.060

0.010

1.020

0.310

0.250

0.100

0.300

0.345

0.125

20

TOLERANCE

MAX

NOTES

A

A1

A2

b

0.210

0.015

0.130

0.018

0.060

0.010

0.890

0.310

0.250

0.100

0.300

0.345

0.125

18

MIN

±0.005

±0.002

b2

c

+0.010/-0.015

+0.004/-0.002

±0.010

D

1

2

E

+0.015/-0.010

±0.005

E1

e

Basic

eA

eB

L

Basic

±0.025

±0.010

N

Reference

Rev. C 2/07

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8183.7

March 7, 2012

13


型号：	X9317TM8Z-2.7-T1
厂家：	RENESAS TECHNOLOGY CORP
描述：	IC DIGITAL POTENTIOMETER, Digital Potentiometer 转换器
文件：	总13页 (文件大小：426K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9317TM8Z-2.7-T1 [RENESAS]

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