X9409WV24-2.7 [RENESAS]
QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, TSSOP-24;
| 型号： | X9409WV24-2.7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, TSSOP-24 光电二极管 转换器 电阻器 |
| 文件： | 总19页 (文件大小：1363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE PRODUCT
DATASHEET
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
X9409
FN8192
Rev.6.00
Sep 3, 2015
Low Noise/Low Power/2-Wire Bus Quad Digitally Controlled Potentiometers
(XDCP)
The X9409 integrates 4 digitally controlled potentiometers
Features
(XDCP) on a monolithic CMOS integrated microcircuit.
• Four potentiometers per package
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled by
the user through the 2-wire bus interface. Each potentiometer
has associated with it a volatile Wiper Counter Register (WCR)
and 4 nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of DR0 to
the WCR.
• 64 resistor taps
• 2-wire serial interface for write, read and transfer operations
of the potentiometer
• 50Ω wiper resistance, typical at 5V
• Four nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on power-up
standby current < 1µA typical
• System V : 2.7V operation
CC
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments and
signal processing.
• 10kΩ end-to-end resistance
• 100 year data retention
• Endurance: 100,000 data changes per bit per register
• Low power CMOS
• 24 Ld TSSOP
• Pb-free (RoHS compliant)
POT 0
V
CC
R
R
R
R
V
/R
H0 HO
R
R
R
R
V
0
2
1
3
0
2
1
3
SS
WIPER
COUNTER
REGISTER
(WCR)
WIPER
COUNTER
REGISTER
(WCR)
V
/R
H2 H2
RESISTOR
ARRAY
POT 2
V
/
L0
R
WP
LO
V
/R
L2 L2
V
R
/
W0
SCL
SDA
V
/R
W2 W2
WO
INTERFACE
AND
CONTROL
CIRCUITRY
A0
A1
8
A2
A3
V
/
W1
DATA
V
/R
W3 W3
R
W1
R
R
R
R
0
2
1
3
R
R
R
V
R
/
WIPER
COUNTER
REGISTER
(WCR)
0
2
1
3
H1
V
/R
WIPER
COUNTER
REGISTER
(WCR)
H3 H3
RESISTOR
ARRAY
POT 1
H1
RESISTOR
ARRAY
Pot 3
R
V /R
L1 L1
V
/R
L3 L3
FIGURE 1. BLOCK DIAGRAM
FN8192 Rev.6.00
Sep 3, 2015
Page 1 of 19
X9409
Ordering Information
POTENTIOMETER
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
V
LIMITS ORGANIZATION
TEMP
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
CC
(V)
(kΩ)
X9409WV24IZ (No longer available,
X9409WV ZI
2.7 to 5.5
10
-40 to +85 24 Ld TSSOP (4.4mm) M24.173
recommended replacement: X9409WV24IZ-2.7)
X9409WV24IZ-2.7
X9409WV ZG 2.7 to 5.5
10
10
-40 to +85 24 Ld TSSOP (4.4mm) M24.173
-40 to +85 24 Ld TSSOP (4.4mm) M24.173
X9409WV24Z (No longer available,
X9409WV Z
2.7 to 5.5
recommended replacement: X9409WV24IZ-2.7)
X9409WV24Z-2.7 (No longer available,
X9409WV ZF
2.7 to 5.5
10
0 to +70 24 Ld TSSOP (4.4mm) M24.173
recommended replacement: X9409WV24IZ-2.7)
NOTES:
1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9409. For more information on MSL, please see tech brief TB363.
Pin Configuration
X9409
(24 LD TSSOP)
TOP VIEW
WP
SDA
1
24
A
2
A
1
2
3
23
22
V
V
V
V
/R
W0 W0
V
/R
L1 L1
V
/R
/R
H1 H1
H0 H0
4
5
21
20
V
/R
W1 W1
/R
L0 L0
V
SS
6
7
19
18
CC
NC
/R
NC
V
V
/R
W2 W2
/R
8
9
17
16
L3 L3
V
V
V
/R
H2 H2
H3 H3
V
/R
/R
L2 L2
10
15
14
13
W3 W3
A
SCL
0
11
12
A
3
NC
Pin Descriptions
PIN #
SYMBOL
DESCRIPTION
11
1
SCL
SDA
Serial Clock
Serial Data
14, 2, 23, 12
21, 4, 9, 16, 20, 3, 10, 17
A , A , A , A
3
Device Address
0
1
2
V
V
/R , V /R , V /R , V /R , V /R , V /R
H0 H0 H1 H1 H2 H2 H3 H3 L0 L0 L1 L1
,
Potentiometer Pin (terminal equivalent)
/R , V /R
L2 L2 L3 L3
22, 5, 8, 15
V
/R , V /R , V /R , V /R
W0 W0 W1 W1 W2 W2 W3 W3
Potentiometer Pin (wiper equivalent)
Hardware Write Protection
System Supply Voltage
System Ground (Digital)
No Connection
24
19
WP
V
V
CC
6
SS
7, 13, 18
NC
FN8192 Rev.6.00
Sep 3, 2015
Page 2 of 19
X9409
START CONDITION
Host Interface Pins
Serial Clock (SCL)
All commands to the X9409 are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH
(t
). The X9409 continuously monitors the SDA and SCL lines
HIGH
The SCL input is used to clock data into and out of the X9409.
for the start condition and will not respond to any command until
this condition is met.
SERIAL DATA (SDA)
The SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-O Red
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is HIGH.
ACKNOWLEDGE
Acknowledge is a software convention used to provide a positive
handshake between the master and slave devices on the bus to
indicate the successful receipt of data. The transmitting device,
either the master or the slave, will release the SDA bus after
transmitting eight bits. The master generates a ninth clock cycle
and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of data.
DEVICE ADDRESS (A , A , A )
0
2
3
The address inputs are used to set the least significant 4 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9409. A maximum of 16 devices may
occupy the 2-wire serial bus.
The X9409 will respond with an acknowledge after recognition of
a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9409 will respond with a final
acknowledge.
Potentiometer Pins
V
/R - V /R , V /R - V /R
H0 H0 H3 H3 L0 L0 L3 L3
The V /R and V /R inputs are equivalent to the terminal
H
H
L
L
connections on either end of a mechanical potentiometer.
ARRAY DESCRIPTION
V
/R /R
V
W0 W0 - W3 W3
The X9409 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to the fixed
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
terminals of a mechanical potentiometer (V /R and V /R
inputs).
H
H
L
L
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (V /R ) output. Within
W
W
each individual array only one switch may be turned on at a time.
These switches are controlled by the Wiper Counter Register
(WCR). The 6 bits of the WCR are decoded to select and enable,
one of sixty-four switches.
PRINCIPLES OF OPERATION
The X9409 is a highly integrated microcircuit incorporating four
resistor arrays and their associated registers and counters and the
serial interface logic providing direct communication between the
host and the XDCP potentiometers.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR can
be read and written by the host system.
Serial Interface
The X9409 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (t
). The SDA state changes during SCL HIGH are
LOW
reserved for indicating start and stop conditions.
FN8192 Rev.6.00
Sep 3, 2015
Page 3 of 19
X9409
Symbol Table
Guidelines for Calculating
Typical Values of Bus Pull-Up
Resistors
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
120
May change
from Low to
High
Will change
from Low to
High
100
80
V
CC MAX
R
R
MIN =
= 1.8kΩ
I
OL MIN
R
May change
from High to
Low
Will change
from High to
Low
t
MAX =
C
BUS
60
40
20
0
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
MAX.
RESISTANCE
N/A
Center Line
is High
Impedance
MIN.
RESISTANCE
0
20
40
60
80
100
120
BUS CAPACITANCE (pF)
FN8192 Rev.6.00
Sep 3, 2015
Page 4 of 19
X9409
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Thermal Resistance
24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
JA (°C/W)
71
JC (°C/W)
19
Voltage on SDA, SCL or any address input with respect to V .-1V to +7V
SS
V = |V - V | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
ESD Rating
H
L
Recommended Operating Conditions
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . 300V
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is taken at the package top center.
JC
Analog Characteristics Across the recommended operating conditions unless otherwise specified.
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6) TYP (Note 6)
UNITS
End-to-end Resistance Tolerance
Power Rating
±20
15
%
+25°C, each pot at 5V, 2.5k
mW
I
Wiper Current
-3
+3
mA
W
R
Wiper Resistance
I
= ±3mA, V = 3V to 5V
W CC
50
150
Ω
V
W
V
Voltage On Any V /R or V /R pin
V
= 0V
V
V
CC
TERM
H
H
L
L
SS
SS
Noise
Resolution (Note 10)
Ref: 1kHz
-
dBV
1.6
%
Absolute Linearity (Note 7)
Relative Linearity (Note 8)
V
V
- V
w(n)(actual) w(n)(expected)
-1
+1
MI (Note 9)
MI (Note 9)
ppm/°C
ppm/°C
pF
- [V
]
w(n) + MI
-0.2
+0.2
w(n + 1)
Temperature Coefficient Of R
30
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitances
20
10
C /C /C
See macro model
10/
0.1
H
L
W
I
R , R , R Leakage Current
V
= V to V . Device is in stand-by mode.
SS CC
µA
AL
H
L
W
IN
D.C. OPERATING CHARACTERISTICS
I
I
V
V
V
Supply Current (Active)
Supply Current (Nonvolatile Write)
Current (Standby)
f
f
= 400kHz, SDA = open, other inputs = V
= 400kHz, SDA = open, other inputs = V
100
1
µA
mA
µA
µA
µA
V
CC1
CC2
CC
CC
CC
SCL
SS
SS
SCL
I
SCL = SDA = V , addr. = V
CC
3
SB
SS
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
= V to V
SS CC
10
10
LI
IN
I
V
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
IH
CC
CC
V
-0.5
V
x 0.1
V
IL
CC
V
Output LOW Voltage
I
= 3mA
0.4
V
OL
OL
ENDURANCE AND DATA RETENTION
Minimum Endurance
100,000
100
Data
changesper
bit per
register
Data Retention
Years
FN8192 Rev.6.00
Sep 3, 2015
Page 5 of 19
X9409
Analog Characteristics Across the recommended operating conditions unless otherwise specified.
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6) TYP (Note 6)
UNITS
CAPACITANCE
C
Input/Output Capacitance (SDA)
V
= 0V
I/O
8
6
pF
pF
I/O
(Note 10)
C
Input Capacitance (A0, A1, A2, A3 and SCL)
V
= 0V
IN
IN
(Note 10)
POWER-UP TIMING
t V Power-Up Rate
V
CC
0.2
50
V/ms
r
CC
(Note 11)
A.C. TEST CONDITIONS
Input Pulse Levels
V
x 0.1 to
CC
V
x 0.9
CC
Input Rise and Fall Times
10ns
Input and Output Timing Level
V
x 0.5
CC
5V
R
TOTAL
1533Ω
R
R
L
H
C
L
C
H
C
W
SDA Output
10pF
10pF
100pF
25pF
R
W
FIGURE 3. CIRCUIT #3 SPICE MACRO MODEL
FIGURE 2. EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING Across recommended operating conditions.
SYMBOL PARAMETER
MIN
(Note 6)
MAX
(Note 6)
UNITS
kHz
ns
f
Clock Frequency
Clock Cycle Time
Clock High Time
Clock Low Time
400
SCL
CYC
t
2500
600
1300
600
600
600
100
30
t
ns
HIGH
t
ns
LOW
t
Start Setup Time
Start Hold Time
ns
SU:STA
t
ns
HD:STA
t
t
Stop Setup Time
SDA Data Input Setup Time
ns
SU:STO
SU:DAT
HD:DAT
ns
t
SDA Data Input Hold Time (Note 12)
SCL and SDA Rise Time
ns
t
300
300
900
ns
R
t
SCL and SDA Fall Time
ns
F
t
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
ns
AA
DH
t
50
50
ns
T
Noise Suppression Time Constant At SCL and SDA Inputs
Bus Free Time (Prior To Any Transmission)
ns
I
t
1300
ns
BUF
FN8192 Rev.6.00
Sep 3, 2015
Page 6 of 19
X9409
AC TIMING Across recommended operating conditions. (Continued)
MIN
MAX
SYMBOL
PARAMETER
WP, A0, A1, A2 and A3 Setup Time
WP, A0, A1, A2 and A3 Hold Time
(Note 6)
(Note 6)
UNITS
ns
t
0
SU:WPA
t
0
HD:WPA
HIGH-VOLTAGE WRITE CYCLE TIMING
MAX
SYMBOL
PARAMETER
TYP
5
(Note 6)
UNIT
ms
t
High-Voltage Write Cycle Time (Store Instructions)
10
WR
XDCP TIMING
MIN
(Note 6)
MAX
(Note 6) UNITS
SYMBOL
PARAMETER
TYP
2
t
Wiper Response Time After The Third (Last) Power Supply Is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
10
10
10
µs
µs
µs
WRPO
t
2
WRL
t
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction)
2
WRID
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
8. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a
measure of the error in step size.
9. MI = RTOT/63 or (V - V )/63, single pot.
H
L
10. This parameter is periodically sampled and not 100% tested.
11. Sample tested only.
12. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
FN8192 Rev.6.00
Sep 3, 2015
Page 7 of 19
X9409
TIMING DIAGRAMS
START and STOP Timing
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
Device Addressing
Power-up Requirements
(Power-up sequencing can affect correct recall of the wiper
registers)
Following a start condition the master must output the address
of the slave it is accessing. The most significant four bits of the
slave address are the device type identifier (see Figure 4). For the
X9409 this is fixed as 0101[B].
The preferred power-on sequence is as follows: First V , then
CC
the potentiometer pins, R , R and R . The V ramp rate
specification should be met and any glitches or slope changes in
H
L
W
CC
DEVICE TYPE
IDENTIFIER
the V line should be held to <100mV if possible. If V powers
CC CC
down, it should be held below 0.1V for more than 1 second
before powering up again in order for proper wiper register recall.
0
1
0
1
A3
A2
A1
A0
Also, V should not reverse polarity by more than 0.5V. Recall of
CC
wiper position will not be complete until V reaches its final
CC
value.
DEVICE ADDRESS
FIGURE 4. SLAVE ADDRESS
FN8192 Rev.6.00
Sep 3, 2015
Page 8 of 19
X9409
The next 4 bits of the slave address are the device address. The
physical device address is defined by the state of the A0 through
A3 inputs. The X9409 compares the serial data stream with the
address input state; a successful compare of all four address bits
is required for the X9409 to respond with an acknowledge. The
A0 through A3 inputs can be actively driven by CMOS input
REGISTER
SELECT
I3
I2
I1
I0
R1
R0
P1
P0
signals or tied to V or V
.
CC SS
POT SELECT
INSTRUCTIONS
Acknowledge Polling
FIGURE 6. INSTRUCTION BYTE FORMAT
The disabling of the inputs, during the internal nonvolatile write
operation, can be used to take advantage of the typical
nonvolatile write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9409
initiates the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition followed by
the device slave address. If the X9409 is still busy with the write
operation no ACK will be returned. If the X9409 has completed
the write operation an ACK will be returned and the master can
then proceed with the next operation.
Instruction Structure
The next byte sent to the X9409 contains the instruction and
register pointer information. The format is shown in Figure 6.
The four high order bits define the instruction. The next 2 bits (R1
and R0) select one of the four registers that is to be acted upon
when a register oriented instruction is issued. The last bits (P1,
P0) select, which one of the four potentiometers is to be affected
by the instruction.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure 7.
These two-byte instructions exchange data between the Wiper
Counter Register and one of the data registers. A transfer from a
Data Register to a Wiper Counter Register is essentially a write to
a static RAM.
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
The response of the wiper to this action will be delayed t
. A
WRL
transfer from the Wiper Counter Register (current wiper position),
to a Data Register is a write to nonvolatile memory and takes a
ISSUE SLAVE
ISSUE STOP
minimum of t
to complete. The transfer can occur between
WR
ADDRESS
one of the four potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer occurs
between all of the potentiometers and one of their associated
registers.
ACK
NO
RETURNED?
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9409; either between the host and one of the data registers or
directly between the host and the Wiper Counter Register. These
instructions are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper Counter Register
(change current wiper position of the selected pot), Read Data
Register (read the contents of the selected nonvolatile register)
and Write Data Register (write a new value to the selected Data
Register). The sequence of operations is shown in Table 1.
YES
FURTHER
OPERATION?
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9409 has
responded with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL clock
PROCEED
pulse (t
) while SDA is HIGH, the selected wiper will move one
resistor segment towards the V /R terminal. Similarly, for each
FIGURE 5. ACK POLLING SEQUENCE
HIGH
H
H
SCL clock pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the V /R terminal. A detailed
L
L
illustration of the sequence and timing for this operation are
shown in Figures 9 and 10 respectively.
FN8192 Rev.6.00
Sep 3, 2015
Page 9 of 19
X9409
TABLE 1. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I
I
I
I
R
R
P
P
OPERATION
3
2
1
0
1
0
1
0
Read Wiper Counter
Register
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
P
P
P
P
P
P
P
P
P
P
P
P
Read the contents of the Wiper Counter Register pointed to by
1
0
P
- P
1
0
Write Wiper Counter
Register
0
0
Write new value to the Wiper Counter Register pointed to by P -
1
1
1
1
1
1
0
0
0
0
0
P
0
Read Data Register
R
R
Read the contents of the Data Register pointed to by P - P and
1 0
1
1
1
1
1
0
0
0
0
0
R
- R
1
0
Write Data Register
R
R
R
R
R
R
R
R
Write new value to the Data Register pointed to by P - P and
1 0
R
- R
1
0
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register pointed to by P - P
1 0
and R - R to its associated Wiper Counter Register
1 0
XFR Wiper Counter
Register to Data Register
Transfer the contents of the Wiper Counter Register pointed to
by P - P to the Data Register pointed to by R - R
1
0
1
0
Global XFR Data Registers
to Wiper Counter
Registers
0
0
Transfer the contents of the Data Registers pointed to by
- R of all four pots to their respective Wiper Counter
R
1
0
Registers
Global XFR Wiper Counter
Registers to Data Register
1
0
0
0
0
1
0
0
R
R
0
0
Transfer the contents of both Wiper Counter Registers to their
1
0
respective Data Registers pointed to by R - R of all four pots
1
0
Increment/Decrement
Wiper Counter Register
0
0
P
P
Enable Increment/decrement of the WCR Latch pointed to by
1
0
P
P
1 -
0
NOTE:
13. 1/0 = data is one or zero
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1 I0
R1 R0 P1 P0
A
C
K
S
T
O
P
FIGURE 7. 2-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0 P1 P0
A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
FIGURE 8. 10-BYTE INSTRUCTION SEQUENCE
FN8192 Rev.6.00
Sep 3, 2015
Page 10 of 19
X9409
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0 R1 R0 P1 P0
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
E
C
n
N
C
1
N
C
2
N
C
n
FIGURE 9. INCREMENT/ DECREMENT INSTRUCTION SEQUENCE
INC/DEC
CMD
ISSUED
t
WRID
SCL
SDA
VOLTAGE OUT
V
/R
W
W
FIGURE 10. INCREMENT/ DECREMENT TIMING LIMITS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8192 Rev.6.00
Sep 3, 2015
Page 11 of 19
X9409
SERIAL DATA PATH
SERIAL
BUS
INPUT
V /R
H H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
REGISTER 2
REGISTER 1
REGISTER 3
8
6
PARALLEL
BUS
INPUT
E
R
WIPER
COUNTER
REGISTER
(WCR)
D
E
C
O
D
E
INC/DEC
LOGIC
If WCR = 00[H] then V /R = V /R
L
UP/DN
W
W
L
UP/DN
CLK
If WCR = 3F[H] then V /R = V /R
W
W
H
H
V /R
MODIFIED SCL
L
L
V
/R
W
W
FIGURE 12. DETAILED POTENTIOMETER BLOCK DIAGRAM
Register Descriptions
Detailed Operation
All XDCP potentiometers share the serial interface and share a
common architecture. Each potentiometer has a Wiper Counter
Register and 4 Data Registers. A detailed discussion of the register
organization and array operation follows.
TABLE 2. DATA REGISTERS, (6-BIT), NONVOLATILE
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
D0
NV
(MSB)
(LSB)
Wiper Counter Register
The X9409 contains four Wiper Counter Registers, one for each
XDCP potentiometer. The Wiper Counter Register can be envisioned
as a 6-bit parallel and serial load counter with its outputs decoded to
select one of sixty-four switches along its resistor array. The contents
of the WCR can be altered in four ways: it may be written directly by
the host via the Write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the contents of one
of the four associated Data Registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a time by
the Increment/ Decrement instruction. Finally, it is loaded with the
contents of its Data Register zero (DR0) upon power-up.
Four 6-bit Data Registers for each XDCP. (sixteen 6-bit registers in
total).
{D5~D0}: These bits are for general purpose not volatile data
storage or for storage of up to four different wiper values. The
contents of Data Register 0 are automatically moved to the wiper
counter register on power-up.
TABLE 3. WIPER COUNTER REGISTER, (6-BIT), VOLATILE
WP5
V
WP4
V
WP3
V
WP2
V
WP1
V
WP0
V
The WCR is a volatile register; that is, its contents are lost when the
X9409 is powered down. Although the register is automatically
loaded with the value in DR0 upon power-up, it should be noted this
may be different from the value present at power-down.
(MSB)
(LSB)
One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit registers
in total).
Data Registers
{D5~D0}: These bits specify the wiper position of the respective
XDCP. The Wiper Counter Register is loaded on power-up by the
Each potentiometer has four nonvolatile Data Registers. These
can be read or written directly by the host and data can be
transferred between any of the four Data Registers and the Wiper
Counter Register. It should be noted all operations changing data
in one of these registers is a nonvolatile operation and will take a
maximum of 10ms.
value in Data Register R . The contents of the WCR can be loaded
0
from any of the other Data Register or directly by command. The
contents of the WCR can be saved in a DR.
If the application does not require storage of multiple settings for
the potentiometer, these registers can be used as regular memory
locations that could possibly store system parameters or user
preference data.
FN8192 Rev.6.00
Sep 3, 2015
Page 12 of 19
X9409
Read Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
WCR
ADDRESSES
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
A
C
K
S
A
C
K
M
A
C
S
T
O
P
W
W
W
W
W
W
0
1
0
1
A3 A2 A1 A0
1
0
0
1
0
0
P1 P0
0
0
K
P5 P4 P3 P2 P1 P0
Write Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
WCR
ADDRESSES
WIPER POSITION
(SENT BY MASTER ON SDA)
S
A
C
K
S
S
A
C
K
S
T
O
P
A
C
K
W
W
W
W
W
W
0
1
0
1
A3 A2 A1 A0
1
0
1
0
0
0
P1 P0
0
0
P5 P4 P3 P2 P1 P0
Read Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DR AND WCR
ADDRESSES
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
S
M
A
C
S
T
O
P
A
C
K
A
C
K
W
W
W
W
W
W
0
1
0
1
A3 A2 A1 A0
1
0
1
1
R1 R0 P1 P0
0
0
K
P5 P4 P3 P2 P1 P0
Write Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DR AND WCR
ADDRESSES
WIPER POSITION
(SENT BY MASTER ON SDA)
S
A
C
K
S
A
C
K
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
W
W
W
W
W
W
0
1
0
1
A3 A2 A1 A0
1
1
0
0
R1 R0 P1 P0
0
0
P5 P4 P3 P2 P1 P0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DR AND WCR
ADDRESSES
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
A3 A2 A1 A0
1
1
0
1
R1
R0
P1
P0
Write Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DR AND WCR
ADDRESSES
S
A
C
K
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
A3 A2 A1 A0
1
1
1
0
R1 R0 P1 P0
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
WCR
ADDRESSES
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
S
A
C
K
S
A
C
K
S
T
O
0
1
0
1
A3 A2 A1 A0
0
0
1
0
0
0
P1 P0
I/D I/D
.
.
.
.
I/D I/D
P
FN8192 Rev.6.00
Sep 3, 2015
Page 13 of 19
X9409
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DR
S
A
C
K
S
A
C
K
S
T
O
P
ADDRESSES
0
1
0
1
A3
A2
A1
A0
0
0
0
1
R1
R0
0
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DR
S
A
C
K
S
A
C
K
S
T
O
P
ADDRESSES
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
A3 A2 A1 A0
1
0
0
0
R1 R0
0
0
Instruction Format
NOTES:
14. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
15. “A3 ~ A0”: stands for the device addresses sent by the master.
16. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
17. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
18. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
FN8192 Rev.6.00
Sep 3, 2015
Page 14 of 19
X9409
Applications Information
Basic Configurations of Electronic Potentiometers
V
+V
R
R
V
/R
W
W
I
FIGURE 13. THREE TERMINAL POTENTIOMETER; VARIABLE
VOLTAGE DIVIDER
FIGURE 14. TWO TERMINAL VARIABLE RESISTOR; VARIABLE
CURRENT
Application Circuits
V
+
–
S
V
V
V
(REG)
317
O
IN
O
R
1
R
2
I
adj
R
R
1
2
V (REG) = 1.25V (1+R /R )+I
R
V
= (1+R /R )V
2 1 S
O
2
1
adj
2
O
FIGURE 15. NONINVERTING AMPLIFIER
FIGURE 16. VOLTAGE REGULATOR
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10kΩ
= {R /(R +R )} V (min)
1 1 2 O
V
S
FIGURE 17. OFFSET VOLTAGE ADJUSTMENT
FIGURE 18. COMPARATOR WITH HYSTERESIS
FN8192 Rev.6.00
Sep 3, 2015
Page 15 of 19
X9409
Application Circuits(Continued)
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
O
O
S
fc = 1/(2RC)
-1/2 G +1/2
FIGURE 20. FILTER
FIGURE 19. ATTENUATOR
R
2
C
R
R
2
1
1
V
+
–
S
V
S
–
+
R
R
1
3
V
O
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
FIGURE 22. EQUIVALENT L-R CIRCUIT
FIGURE 21. INVERTING AMPLIFIER
C
R
R
1
2
–
+
–
+
R
}
}
A
B
R
frequency R , R , C
1
2
amplitude R , R
A
B
FIGURE 23. FUNCTION GENERATOR
FN8192 Rev.6.00
Sep 3, 2015
Page 16 of 19
X9409
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
t
SDA
VWx
WRL
XDCP Timing (for Increment/Decrement Instruction)
SCL
WIPER REGISTER ADDRESS
INC/DEC
INC/DEC
SDA
t
WRID
V
/R
W
W
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(ANY INSTRUCTION)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
A2, A3
FN8192 Rev.6.00
Sep 3, 2015
Page 17 of 19
X9409
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN8192.6
FN8192.5
CHANGE
September 3, 2015
April 20, 2015
Updated Ordering Information table on page 2.
Updated Template.
Added revision history.
Removed part numbers X9409WS24I-2.7 and X9409WS24IZ-2.7 from ordering information table.
Analog Characteristics table on page 5, in ISB section: Changed max value from 1µ to 3µ.
Removed 24 Ld SOIC throughout the document.
Removed POD M24.3.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
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All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8192 Rev.6.00
Sep 3, 2015
Page 18 of 19
X9409
Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
1
3
7.80 ±0.10
SEE DETAIL "X"
13
24
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
12
+0.05
-0.06
0.15
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
-
0.05
C
+0.15
-0.10
0.90
1.20 MAX
GAUGE
PLANE
SEATING PLANE
0.10 C
0.25
+0.05
-0.06
C B A
0.25
0.10
5
0°-8°
0.60± 0.15
0.05 MIN
0.15 MAX
M
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN8192 Rev.6.00
Sep 3, 2015
Page 19 of 19
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