ZL2004ALNNT1-01 [RENESAS]
Adaptive Digital DC/DC Controller with Current Sharing;
| 型号： | ZL2004ALNNT1-01 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Adaptive Digital DC/DC Controller with Current Sharing 开关 |
| 文件： | 总8页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ZL2004-01
Adaptive Digital DC/DC Controller with Current Sharing
FN6847
Rev 2.00
May 23, 2011
The ZL2004-01 is specialized version of the ZL2004 DC/DC
controller that has been optimized for high output accuracy
within a given set of operating conditions. The ZL2004-01 is
otherwise identical to the ZL2004 in features and
functionality. The ZL2004-01 has been optimized for use with
the ZL1505 MOSFET driver and discrete MOSFETs.
Features
• Power Conversion
• Efficient synchronous buck controller
• ± 0.2% VOUT set-point accuracy
• 8.0V to 10.0V input range
The ZL2004-01 integrates a proprietary Digital-DC
communication bus for current sharing and inter device
communication. Adaptive algorithms improve light load
efficiency. All operating features can be configured by simple
pin-strap selection, resistor selection or through the on-board
serial port. The PMBus™-compliant ZL2004-01 uses the
SMBus™ serial interface for communication with other Digital-
DC products or a host controller.
• 0.9V to 1.1V output range
• Adaptive performance optimization algorithms
• Fast load transient response
• Active current sharing
• DCR current sensing with digitally adjustable current sense
range
• RoHS compliant (5mmx5mm) QFN package
• Power Management
Related Literature
• See FN6846, ZL2004 “Adaptive Digital DC-DC Controller
with Current Sharing”
• Digital soft-start/stop
• Precision delay and ramp-up
• Power-good/enable
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• SMBus communication (PMBus compliant)
• Output voltage and current protection
• Internal non-volatile memory (NVM)
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
PG SS FC ILIM CFG FLEX V25 VR VDD
EN
V (0,1)
VMON
MGN
LDO
POWER
SYNC
MANAGEMENT
DDC
LEVEL
SHIFTER
PWMH
PWML
NON-
VOLATILE
MEMORY
PWM
CONTROLLER
ISENA
ISENB
CURRENT
SENSE
SCL
SDA
SALRT
MONITOR
ADC
TEMP
SENSOR
I2 C
VTRK
VSEN+/-
SA (0,1)
XTEMP
SGND DGND
FIGURE 1. BLOCK DIAGRAM
FN6847 Rev 2.00
May 23, 2011
Page 1 of 8
ZL2004-01
Ordering Information
PACKAGE
Tape & Reel
(Pb-free)
PART NUMBER
(Notes 1, 4)
PART
MARKING
TEMP RANGE
(°C)
SHIPPING CONTAINER
490 pieces
PKG. DWG. #
L32.5x5D
L32.5x5D
L32.5x5D
L32.5x5G
L32.5x5G
L32.5x5G
ZL2004ALNN-01 (Note 2)
ZL2004ALNNT-01 (Note 2)
ZL2004ALNNT1-01 (Note 2)
ZL2004ALNF-01 (Note 3)
ZL2004ALNFT-01 (Note 3)
ZL2004ALNFT1-01 (Note 3)
NOTES:
2004-01
2004-01
0 to +65
0 to +65
0 to +65
0 to +65
0 to +65
0 to +65
32 Ld QFN
32 Ld QFN
32 Ld QFN
32 Ld QFN
32 Ld QFN
32 Ld QFN
100 pieces
2004-01
2004-01
2004-01
2004-01
1000 pieces
490 pieces
100 pieces
1000 pieces
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate -
e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ZL2004-01. For more information on MSL please see techbrief TB363.
Pin Configuration
ZL2004-01
(32 LD QFN)
TOP VIEW
32 31 30 29 28 27 26 25
DGND
SYNC
SA0
VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VR
PWMH
SGND
PWML
ISENA
ISENB
NC
SA1
EXPOSED PADDLE
CONNECT TO SGND
ILIM
SCL
SDA
SALRT
9
10 11 12 13 14 15 16
FN6847 Rev 2.00
May 23, 2011
Page 2 of 8
ZL2004-01
Pin Descriptions
TYPE
PIN
1
SYMBOL
DGND
SYNC
(Note 5)
DESCRIPTION
Digital ground. Connect to low impedance ground plane.
Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external
PWR
2
I/O, M
(Note 6) clock or to output internal clock.
3
4
SA0
SA1
I, M
Serial address select pins. Used to assign unique address for each individual device or to enable certain
management features.
5
ILIM
I, M
I/O
I/O
O
Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
Serial clock. Connect to external host and/or to other ZL devices.
Serial data. Connect to external host and/or to other ZL devices.
Serial alert. Connect to external host if desired.
6
SCL
7
SDA
8
SALRT
FC
9
I
Loop compensation selection pin.
10
11
12
13, 17
14
15
16
18
19
20
21
22
23
24
V0
I, M
Output voltage selection pins. Used to set V
OUT
set-point and V max.
OUT
V1
VMON
NC
I, M
External voltage monitoring (Can be used for external driver bias monitoring for Power-good).
No Connect.
VTRK
VSEN+
VSEN-
ISENB
ISENA
PWML
SGND
PWMH
VR
I
Tracking sense input. Used to track an external voltage source.
Differential Output voltage sense feedback. Connect to positive output regulation point.
Differential Output voltage sense feedback. Connect to negative output regulation point.
Differential voltage input for current sensing.
I
I
I
I
Differential voltage input for current sensing. High voltage (DCR).
PWM Gate low signal.
O
PWR
O
Connect to low impedance ground plane. Internal connection to SGND.
PWM Gate High signal.
PWR
PWR
Internal 5V reference used to power internal drivers.
Supply voltage.
VDD
(Note 7)
25
26
27
28
29
30
31
V25
XTEMP
DDC
MGN
CFG
PWR
Internal 2.5V reference used to power internal circuitry.
I
External temperature sensor input. Connect to external 2N3904 (Base Emitter junction).
Single wire DDC bus (Current sharing, interdevice communication).
I
I
V
margin control.
OUT
M
I
Configuration pin. Used to control the switching phase offset, sequencing and other management features.
Enable. Active signal enables PWM switching.
EN
SS
I, M
Soft-start delay and ramp select. Sets the delay from when EN is asserted until the output voltage starts to
ramp and the ramp time.
32
PG
O
Power-good output.
EPAD
SGND
PWR
Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.
NOTES:
5. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins.
6. The SYNC pin can be used as a logic pin, a clock input or a clock output.
7. V is measured internally and the value is used to modify the PWM loop gain.
DD
FN6847 Rev 2.00
May 23, 2011
Page 3 of 8
ZL2004-01
Absolute Maximum Ratings (Note 8)
DC Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic I/O Voltage
Thermal Information
Thermal Resistance (Typical)
JA (°C/W)
35
JC (°C/W)
32 Ld QFN Package (Notes 9, 10) . . . . . . .
5
CFG, DDC, EN, FC, FLEX, ILIM, MGN, PG, SA (0,1)
SALRT, SCL, SDA, SS, SYNC, VMON, V (0,1) . . . . . . . . . . . . -0.3V to 6.5V
Analog Input Voltages
VSEN+, VSEN-, VTRK, XTEMP . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ISENA, ISENB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
MOSFET Drive Reference (VR). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Logic reference (V25). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ground Voltage Differential (V
DGND, SGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
- V )
Input Supply Voltage Range, (V ). . . . . . . . . . . . . . . . . . . . . . . . . 8V to 10V
DGND SGND
DD
Output Voltage Range (V
) . . . . . . . . . . . . . . . . . 0.9V to 1.1V, 1.0V (Typ)
OUT
Operating Frequency (F ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400kHz Typ
SW
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . 0°C to +65°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
8. All voltages are measured with respect to SGND.
9. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
10. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= 8.6 V, V = 1.0 V, T = 0°C to +65°C unless otherwise noted. Typical values are at T = +25°C. The
OUT A A
DD
following specifications describe the ZL2004-01 electrical specifications that differ from the ZL2004. Please refer to the ZL2004 data sheet for the full
operating specification limits for the remaining functions not described herein. Boldface limits apply over the operating temperature range, 0°C to
+65°C.
MIN
MAX
PARAMETER
CONDITIONS
(Note 11)
TYP
16
(Note 11)
UNIT
mA
INPUT AND SUPPLY CHARACTERISTICS
I
Supply Current at F
SW
= 400kHz
GH no load, GL no load,
–
30
DD
MISC_CONFIG[7] = 1
2
I
Shutdown Current
EN = 0V No I C/SMBus activity
–
2
5
mA
V
DDS
VR Reference Output Voltage
V
V
> 6V, I < 50mA
VR
4.5
5.2
2.5
5.7
DD
V25 Reference Output Voltage
OUTPUT CHARACTERISTICS
> 3V, I
< 50mA
V25
2.25
2.75
V
R
Output Voltage Adjustment Range
Output Voltage Setpoint Accuracy (Note 12)
V
V
> V
OUT
0.9
–
–
1.1
0.2
V
IN
= 8.6V, V
OUT
= 1V
-0.2
%
IN
T
= 0°C to + 65°C,
A
I
= 0A to 40A
LOAD
PMBus READ_VOUT Accuracy
-1.0
-
1.0
%
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency (Note 13)
SYNC pin floating or NVM configured for
400kHz
–
400
–
–
5
kHz
%
Switching Frequency Set-point Accuracy
FAULT PROTECTION CHARACTERISTICS
UVLO Threshold Range
- 5
2
Configurable via I C/SMBus
2.85
–
16
V
NOTES:
11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
12. V set-point measured at the termination of the VSEN+ and VSEN- sense points.
OUT
13. The ZL2004-01 has been optimized for operation at 400kHz only. Please consult the factory for requirements at other operating frequencies.
FN6847 Rev 2.00
May 23, 2011
Page 4 of 8
ZL2004-01
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN6847.2
CHANGE
5/11/11
On page 1:
Added “Related Literature”
On page 2:
Added following parts to “Ordering Information”:
ZL2004ALNN-01
ZL2004ALNF-01
ZL2004ALNFT-01
ZL2004ALNFT1-01
Added lead finish Note 3 for ALNF parts.
On page 4:
Updated note in Min Max column of “Electrical Specifications” table from "Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested." to "Compliance to datasheet limits is assured by one or more
methods: production test, characterization and/or design."
On page 8:
Added “Package Outline Drawing” L32.5x5G for ALNF parts.
4/9/10
FN6847.1
On page 4, changed max value from 5.5 to 5.7 for “VR Reference Output Voltage”.
3/23/10
Converted to New Intersil Template. Added spec to existing parameter on the device in Electrical Specifications
Table “Output Characteristics”: PMBus READ_VOUT Accuracy -1.0 (MIN), 1.0 (MAX) %. Changed Temp Range in
ordering information from “-40°C to +85°C” to “0°C to +65°C” matching information in Thermal Information.
Added over-temp note and reference Electrical spec table Min and Max columns. Added ordering information
table, Pin Configuration and Pin Description Table, POD, Revision History and Products Information.
Updated POD L32.5x5D to latest released version. Change to POD is as follows:
Updated POD to new standards by adding land pattern and moving dimensions from table onto drawing.
2/19/09
FN6847.0
Assigned file number FN6847 to datasheet as this will be the first release with an Intersil file number. Replaced
header and footer with Intersil header and footer. Updated disclaimer information to read "Intersil and it's
subsidiaries including Zilker Labs, Inc." No changes to datasheet content.
FN6847 Rev 2.00
May 23, 2011
Page 5 of 8
ZL2004-01
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ZL2004-01
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
© Copyright Intersil Americas LLC 2009-2011. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries. This product is subject to a license from Power One, Inc. related to digital power
technology as set forth in U.S. Patent No. 7,000,125 and other related patents owned by Power One, Inc. These license rights do not extend to stand-alone POL
regulators unless a royalty is paid to Power One, Inc.
FN6847 Rev 2.00
May 23, 2011
Page 6 of 8
ZL2004-01
Package Outline Drawing
L32.5x5D
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
4X 3.5
0.50
28X
5.00
A
6
B
PIN #1
INDEX AREA
25
32
6
1
24
PIN 1
INDEX AREA
3 .50
EXP. DAP
17
8
(4X)
0.15
16
9
TOP VIEW
32X 0.40 ± 0.10
BOTTOM VIEW
4
32X 0.23
0.10M C A B
SEE DETAIL "X"
0.10 C
C
SEATING PLANE
MAX 0.90
0.08 C
( 4. 80 TYP )
SIDE VIEW
( 28X 0 . 5 )
(
3.50 )
(32X 0 . 23 )
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
( 32X 0 . 60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6847 Rev 2.00
May 23, 2011
Page 7 of 8
ZL2004-01
Package Outline Drawing
L32.5x5G
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 3.5
28X 0.50
5.00
A
6
B
PIN #1
INDEX AREA
25
32
6
1
24
PIN 1
INDEX AREA
3 .50
EXP. DAP
17
8
(4X)
0.15
16
9
TOP VIEW
32X 0.40 ± 0.10
BOTTOM VIEW
4
32X 0.23
0.10M C A B
SEE DETAIL "X"
0.10
C
C
MAX 1.00
SEATING PLANE
0.08 C
( 4. 80 TYP )
3.50 )
( 28X 0 . 5 )
SIDE VIEW
(
(32X 0 . 23 )
( 32X 0 . 60)
5
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6847 Rev 2.00
May 23, 2011
Page 8 of 8
相关型号：
ZL2005ALNFT
Digital-DC™ Integrated Power Management and Conversion IC; QFN36; Temp Range: -40° to 85°C
RENESAS
ZL2005ALNFT1
Digital-DC™ Integrated Power Management and Conversion IC; QFN36; Temp Range: -40° to 85°C
RENESAS
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