ZL2005PALRFT1 [INTERSIL]
Digital-DC⢠Controller with Drivers and POLA/DOSA Trim;
| 型号： | ZL2005PALRFT1 |
| 厂家： | 
Intersil |
| 描述： | Digital-DC⢠Controller with Drivers and POLA/DOSA Trim 开关 输出元件 |
| 文件： | 总41页 (文件大小：1611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL2005P
ta Sheet
December 16, 2011
FN6849.3
Dgital-DC™ Controller with Drivers and POLA/DOSA Trim
Description
Features Power Conversion
The ZL2005P is an innovative mixed-signal power
conversion and management IC that combines a com-
pact, efficient, synchronous DC-DC buck controller,
adaptive drivers and key power and thermal manage-
ment functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs Digital-DC tech-
nology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associ-
ated with providing multiple low-voltage power
domains on a single PCB.
•
•
•
•
•
•
•
•
•
Efficient synchronous buck controller
3 V to 14 V input range
0.54 V to 5.5 V output range (with margin)
Optional output voltage setting with VADJ pin
± 1% output accuracy
Internal 3 A drivers support >40 A power stage
Fast load transient response
Phase interleaving
RoHS compliant (6 x 6 mm) QFN package
Power Management
•
•
•
•
Digital soft start/stop
Precision delay and ramp-up
Voltage tracking, sequencing and margining
Voltage/current/temperature monitoring
I2C/SMBus communication
Output overvoltage and overcurrent protection
Internal non-voltatile memory (NVM)
PMBus compliant
The ZL2005P is designed to be configured either as a
standard ZL2005 or as POLA/DOSA compatible
device.
•
•
•
•
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005P uses the SMBus™ serial interface for com-
munication with other Digital-DC products or a host
controller.
Applications
•
•
•
Servers/storage equipment
Telecom/datacom equipment
Power supplies (memory, DSP, ASIC, FPGA)
DLY FC ILIM
(0,1) (0,1) (0,1)
EN PG
CFG UVLO V25 VR VDD
LDO
SS (0,1)
VTRK
MGN
SYNC
VADJ
POWER
MANAGEMENT
BST
GH
DRIVER
SW
GL
NON-
VOLATILE
MEMORY
PWM
CONTROLLER
CURRENT
SENSE
ISENA
ISENB
SCL
SDA
SALRT
TEMP
SENSOR
MONITOR
ADC
I2C
VSEN
XTEMP
SA (0,1)
PGND SGND DGND
Figure 1. Block Diagram
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ZL2005P
Table of Contents
1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
7
9
4 ZL2005P Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
4.4
4.5
Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ZL2005 - ZL2005P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Conversion Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . 14
High-side Driver Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Start-up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Soft Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Selecting Power Train Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Current Limit Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.10 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.11 Non-Linear Response Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.12 Efficiency Optimized Driver Dead-time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Power Management Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Input Undervoltage Lockout (UVLO) Standard Mode . . . . . . . . . . . . . . . . . . . . . . . . 30
Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
I C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
I C/SMBus Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.10 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.11 Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
6.12 Monitoring via I C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.13 Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.14 Non-volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . 37
7 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1
8.2
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FN6849.3
December 16, 2011
2
ZL2005P
1
Electrical Characteristics
Table 1. Absolute Maximum Ratings
Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may
adversely impact product reliability and result in failures not covered by warranty. Unless otherwise specified, all
voltages are measured with respect to SGND.
Parameter
Pin(s)
Value
Unit
DC supply voltage
VDD
-0.3 to 17
V
DLY(0,1), EN, ILIM(0,1),
MGN, PG, SA(0,1), SALRT,
SCL, SDA, SS(0,1), SYNC,
VADJ, UVLO, V(0,1)
Logic I/O voltage
-0.3 to 6.5
V
ISENB, VSEN, VTRK,
ISENA, XTEMP
Analog input voltages
-0.3 to 6.5
V
MOSFET drive reference
Logic reference
VR
V25
BST
GH
-0.3 to 6.5
-0.3 to 3
V
V
V
V
V
High-side supply voltage
High-side drive voltage
Low-side drive voltage
Boost to switch differential voltage
-0.3 to +30
(VSW - 0.3) to (VBST+0.3)
(PGND-0.3) to (VR+0.3+PGND)
GL
BST, SW
SW
-0.3 to 8
V
V
V
(VBST - VSW
)
Switch node continuous
(PGND-0.3) to 30
(PGND-5) to 30
Switch node transient
(<100 ns)
SW
Ground voltage differential
(VDGND-VSGND), (VPGND-VSGND
DGND, SGND, PGND
-0.3 to +0.3
V
)
Junction temperature
–
–
-55 to 150
-55 to 150
oC
oC
Storage temperature range
Lead temperature
(soldering, 10s)
–
300
oC
FN6849.3
December 16, 2011
3
ZL2005P
Table 2. Recommended Operating Conditions and Thermal Information
Parameter
Symbol
Min
Typ
Max
Unit
VR tied to VDD (Figure 9)
3.0
–
5.5
V
Input Supply Voltage Range, VDD
VR floating (Figure 9)
VOUT (RDSON sensing)
4.5
0.54
0.6
–
14
V
V
Output Voltage Range
5.5
Output Voltage Range
VOUT (DCR sensing)
TJ
3.63
125
V
Operating Junction Temperature Range
-40
–
35
5
°C
Junction to Ambient Thermal
Impedance1
Junction to Case Thermal Impedance2
ΘJA
ΘJC
–
–
–
–
°C/W
°C/W
NOTES:
1. ΘJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief
TB379.
2. For ΘJC, the “case” temperature is measured at the center of the exposed metal pad.
3. With margin
o
o
Table 3. Electrical Specifications Unless otherwise specified V = 12 V, T = -40 C to +85 C. Typical values are at
DD
A
o
T = 25 C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
A
Parameter
Condition
Min
Typ
Max
Unit
(Note 6)
(Note 6)
Input and Supply Characteristics
fSW = 200 kHz
fSW = 1,000 kHz
EN = Low
–
–
16
25
30
50
mA
mA
Supply current (IDD
(No load on GH and GL)
)
Standby supply current (IDD
)
–
2
5
mA
V
no I2C/SMBus activity
VDD ≥ 6 V
VR reference voltage (VR)
4.5
5.2
2.5
5.5
I
VR < 50 mA
VR ≥ 3 V
IV25 < 50 mA
V25 reference voltage (V25)
2.25
2.75
V
Output Characteristics
Output voltage adjustment range
Output voltage setpoint resolution
0.6
–
5.5
V
Set using resistors on V(0,1)
Set using resistor on VADJ
–
10
Table 8
±0.025
–
mV
–
–
% of
F.S.1
Set using I2C/SMBus
Output voltage accuracy
VSEN input bias current
Over line and load
VSEN = 5.5 V
-1
–
1
%
110
–
200
µA
Current sense differential input voltage
(ground referenced)
VISENA - VISENB
VISENA - VISENB
-100
-50
100
50
mV
mV
Current sense differential input voltage
(VOUT referenced)
–
Current sense input bias current
Ground referenced
ISENA
-100
-1
–
–
100
1
µA
µA
Current sense input bias current
(VOUT referenced,
VOUT <= 3.6V)
Soft start delay duration range5
ISENB
-100
–
–
100
500
µA
s
Configurable via I2C/SMBus
0.007
FN6849.3
December 16, 2011
4
ZL2005P
o
o
Table 3. Electrical Specifications Unless otherwise specified V = 12 V, T = -40 C to +85 C. Typical values are at
DD
A
o
T = 25 C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
A
Parameter
Condition
Min
Typ
Max
Unit
(Note 6)
(Note 6)
Soft start delay duration accuracy
Soft start ramp duration range5
Soft start ramp duration accuracy
Logic Input/Output Characteristics
–
0
–
6
–
–
200
–
ms
ms
µs
Configurable via I2C/SMBus
100
Logic input leakage current
Push-pull logic
-250
–
–
250
0.8
–
nA
V
Logic input low threshold (VIL)
–
–
2
Logic input OPEN (N/C)
Logic input high threshold (VIH)
1.4
–
V
Multi-mode logic pins
–
V
Logic output low (VOL
)
IOL <= 4 mA
IOH >= - 2 mA
–
–
–
0.4
V
V
Logic output high (VOH
)
2.25
–
Oscillator and Switching Characteristics
Switching frequency range
200
-5
–
–
1400
5
kHz
%
Predefined settings
(See Table 13)
Switching frequency setpoint
accuracy
Maximum PWM duty cycle
Minimum SYNC pulse width5
Factory default
95
150
-13
–
–
–
–
–
%
ns
%
Input clock frequency drift tolerance
External clock signal
13
Gate Drivers
High-side driver voltage
–
2
–
–
–
–
–
–
4.5
3
–
–
2
2
–
–
2
2
V
A
Ω
Ω
A
A
Ω
Ω
(VBST - VSW
)
High-side driver peak gate drive
current (pull down)5
(VBST - VSW) = 4.5 V
(VBST - VSW) = 4.5 V,
(VBST - VGH) = 50 mV
(VBST - VSW) = 4.5 V,
(VGH - VSW) = 50 mV
High-side driver pull-up resistance5
0.8
0.5
2.5
1.8
1.2
0.5
High-side driver pull-down
resistance5
Low-side driver peak gate drive
current (pull-up)5
VR = 5 V
VR = 5 V
Low-side driver peak gate drive
current (pull-down)5
VR = 5 V,
(VR - VGL) = 50 mV
VR = 5 V,
Low-side driver pull-up resistance5
Low-side driver pull-down resistance5
Switching timing
(VGL - PGND) = 50 mV
(VBST - VSW) = 4.5 V,
GH rise and fall time5
–
–
5
5
20
20
ns
ns
CLOAD = 2.2 nF
VR = 5 V,
GL rise and fall time5
CLOAD = 2.2 nF
Tracking
VTRK input bias current
VTRK = 5.5 V
–
110
200
µA
FN6849.3
December 16, 2011
5
ZL2005P
o
o
Table 3. Electrical Specifications Unless otherwise specified V = 12 V, T = -40 C to +85 C. Typical values are at
DD
A
o
T = 25 C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
A
Parameter
Condition
Min
Typ
Max
Unit
(Note 6)
(Note 6)
VTRK tracking threshold5
VTRK >= 0.3 V
– 100
100
mV
Fault Protection Characteristics
UVLO threshold range
UVLO setpoint accuracy
UVLO hysteresis
2.85
-3
–
–
–
3
–
–
16
3
V
%
%
%
µs
ZL2005P configuration
Factory default
Configurable via I2C/SMBus
–
0
100
2.5
UVLO delay
–
%
VOUT
Power good VOUT low threshold
Factory default
Factory default
–
–
90
–
–
%
VOUT
Power good VOUT high threshold
115
Power good VOUT hysteresis
Power good delay range5
Factory default
Configurable via I2C/SMBus
–
5
–
–
%
s
0
500
%
VOUT
Factory default
Configurable via I2C/SMBus5
Factory default
85
–
–
VSEN undervoltage threshold
VSEN overvoltage threshold
%
VOUT
0
110
–
%
VOUT
115
–
%
VOUT
Configurable via I2C/SMBus5
0
115
Factory default
Configurable via I2C/SMBus5
–
16
–
–
µs
µs
VSEN undervoltage/overvoltage fault
response time
5
60
Current limit setpoint accuracy
(VOUT referenced)
Current limit setpoint accuracy2
(Ground referenced)
–
–
±10
±10
–
–
% F.S.1
|VISENA - VISENB|> 12 mV
% F.S.
Factory default
Configurable via I2C/SMBus5
Factory default
–
1
5
–
–
32
3
Current limit protection delay
tSW
–
4400
–
–
Temperature compensation of current
limit protection threshold
ppm/°C
Configurable via I2C/SMBus5
100
–
12700
–
Factory default
Configurable via I2C/SMBus5
125
–
°C
°C
°C
Thermal protection threshold
- 40
–
125
–
Thermal protection hysteresis
15
NOTES:
1. Percentage of Full Scale (F.S.) with temperature compensation applied.
2. TA = 0oC to +85oC
3. tSW = 1/fSW, fSW switching frequency
4. Automatically set to same value as soft start ramp time.
5. Limits established by characterization and not production tested.
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6849.3
December 16, 2011
6
ZL2005P
2
Pin Descriptions
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
DGND
SYNC
SA0
VDD
BST
GH
36-Pin QFN
6 x 6 mm
SA1
SW
ILIM0
ILIM1
SCL
PGND
GL
Exposed Paddle
Connect to SGND
VR
SDA
ISENA
ISENB
SALRT
Figure 2. Pin Assignments (top view)
Table 4. Pin Descriptions
1
Pin
Label
Description
Type
1
DGND
PWR
Digital ground. Connect to low impedance ground plane.
Clock synchronization input. Used to set the frequency of the internal switch
clock, to sync to an external clock or to output internal clock.
2
SYNC
I/O, M2
3
4
SA0
SA1
Serial address select pins. Used to assign unique address for each individual
device or to enable certain management features.
I, M
I, M
5
ILIM0
ILIM1
SCL
Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
6
7
I/O
I/O
O
Serial clock. Connect to external host and/or to other ZL2005s.
Serial data. Connect to external host and/or to other ZL2005s.
Serial alert. Connect to external host if desired.
8
SDA
SALRT
FC0
9
10
11
12
13
I
Loop compensation selection pins.
FC1
I
V0
I, M
I, M
Output voltage selection pins. Used to set VOUT setpoint and VOUT max.
Undervoltage lockout selection. Sets the minimum value for VDD voltage to
V1
14
UVLO
enable VOUT
.
15
16
SS0
SS1
I, M
I
Soft start pins. Set the output voltage ramp time during turn-on and turn-off.
Tracking sense input. Used to track an external voltage source.
17
VTRK
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pin (refer to Section 4.5, “Multi-mode Pins,” )
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. VDD is measured internally and the value is used to modify the PWM loop gain.
FN6849.3
December 16, 2011
7
ZL2005P
Table 4. Pin Descriptions (Continued)
1
Pin
18
19
20
21
22
23
24
25
26
27
28
Label
VSEN
ISENB
ISENA
VR
Description
Type
I
Output voltage feedback. Connect to output regulation point.
Differential voltage input for current limit.
Differential voltage input for current limit. High voltage tolerant.
Internal 5V reference used to power internal drivers.
Low side FET gate drive.
I
I
PWR
O
GL
PGND
SW
PWR
PWR
O
Power ground. Connect to low impedance ground plane.
Drive train switch node.
GH
High-side FET gate drive.
BST
VDD3
PWR
PWR
PWR
High-side drive boost voltage.
Supply voltage.
V25
Internal 2.5 V reference used to power internal circuitry.
External temperature sensor input. Connect to external 2N3904 diode connected
transistor.
29
XTEMP
I
30
31
VADJ
MGN
I
I
Output voltage setting pin (POLA/DOSA mapping)
Digital VOUT margin control
Configuration pin. Used to control the switching phase offset, sequencing and
other management features.
32
CFG
I
I
33
34
35
36
EN
DLY0
DLY1
PG
Enable. Active signal enables PWM switching.
Softstart delay select. Sets the delay from when EN is asserted until the output
voltage starts to ramp.
I, M
O
Power good output.
Exposed thermal pad. Connect to low impedance ground plane. Internal
connection to SGND.
ePad
SGND
PWR
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pin (refer to Section 4.5, “Multi-mode Pins,” )
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. VDD is measured internally and the value is used to modify the PWM loop gain.
FN6849.3
December 16, 2011
8
ZL2005P
3
Typical Application Example
VIN 12V
11.5 kOhm
CIN
3 x 10 µF
25 V
VR
POWER
GOOD
10
µF
4 V
10
CV25
kOhm
QH
Si7114
DB
BAT54
1 µF
16 V
DGND
SYNC
SA0
VDD
BST
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
V25
CB
GH
VOUT
LOUT
SA1
SW
0.56
µH
ILIM0
ILIM1
SCL
PGND
GL
ZL2005P
COUT
2 x 47 µF
6.3 V
VR
I2C/SMBus
OPTIONAL
SDA
ISENA
ISENB
SALRT
QL
NTMSF4108
EPAD
CVR
RTN
EN/
INHIBIT
110
4.7 µF 6.3 V
kOhm
1.5 kOhm
9.09
kOhm
Notes:
1. Conditions: VIN = 12 V, VOUT = 1.2 V, Freq = 400 kHz, IOUT = 20 A
2. The I2C/SMBus requires pullup resistors. Please refer to the I2C/SMBus specifications for more details.
Figure 3. Typical Application Circuit POLA
100
VOUT = 3.3V
VOUT = 1.5V
95
90
85
80
75
70
65
60
55
50
VIN = 12V
fSW = 400kHz
Circuit of Figure 3
0
4
10
14 16 18 20
2
6
8
12
Load Current (A)
Figure 4. Typical Efficiency Curves
FN6849.3
December 16, 2011
9
ZL2005P
4
ZL2005P Overview
Zilker Labs provides a comprehensive set of on-line
4.1 Digital-DC Architecture
tools and application notes to assist with power supply
design and simulation. An evaluation board is also
available to help the user become familiar with the
device. This board can be evaluated as a stand-alone
platform using pin configuration settings. Addition-
ally, a Windows™-based GUI is provided to enable
full configuration and monitoring capability via the
I2C/SMBus interface using an available computer and
the included USB cable.
The ZL2005P is an innovative mixed-signal power
conversion and power management IC based on Zilker
Labs’ patented Digital-DC technology that provides
an integrated, high performance step-down converter
for a wide variety of power supply applications. Its
unique digital PWM loop utilizes an innovative
mixed-signal topology to enable precise control of the
power conversion process with no software required,
resulting in a very flexible device that is also easy to
use. An extensive set of power management functions
is fully integrated and can be configured using simple
pin connections or via the I2C/SMBus hardware inter-
face using standard PMBus commands. The user con-
figuration can be saved in an on-chip non-volatile
memory (NVM), allowing ultimate flexibility.
Please refer to www.intersil.com/zilkerlabs/ for access
to the most up-to-date documentation and the Power-
PilotTM simulation tool, or call your local Zilker Labs’
sales office to order an evaluation kit.
4.2 ZL2005 - ZL2005P
By default, the ZL2005P is configured as a standard
ZL2005 device.
Once enabled, the ZL2005P is immediately ready to
regulate power and perform power management tasks
with no programming required. The ZL2005P can be
configured by simply connecting its pins according to
the tables provided in this document. Advanced con-
figuration options and real-time configuration changes
are available via the I2C/SMBus interface if desired,
and continuous monitoring of multiple operating
parameters is possible with minimal interaction from a
host controller. Integrated sub-regulation circuitry
enables single supply operation from any supply
between 3V and 14V with no secondary bias supplies
needed.
The main differences between the ZL2005P config-
ured as a ZL2005P and the initial ZL2005 are the fol-
lowing:
•
•
•
•
TACH pin is not used (reserved for ZL2005P
POLA configuration).
VADJ pin to adjust voltage through an external
resistor, similar to POLA method.
Additional configuration option for Synchroniza-
tion.
DEFAULT STORE only
FN6849.3
December 16, 2011
10
ZL2005P
4.3 Power Conversion Overview
INPUT VOLTAGE BUS
VDD
PG EN
V(0,1)
VADJ
NVM
VR
VR LDO
VTRK
SYNC
POWER MANAGEMENT
BST
GH
SW
GL
VOUT
MOSFET
DRIVERS
DIGITAL
COMPENSATOR
SYNC
GEN
D-PWM
NLR
PLL
-
VSEN
VDD
ADC
Σ
+
REFCN
DAC
ISENB
ISENA
ADC
ADC
SALRT
SDA
VSEN
SMBUS
{
COMMUNICATION
SCL
MUX
XTEMP
SA(0,1)
TEMP
SENSOR
Figure 5. ZL2005P Detailed Block Diagram
The ZL2005P operates as a voltage-mode, synchro-
nous buck converter with a selectable, constant fre-
quency Pulse Width Modulator (PWM) control
scheme that uses external MOSFETs, inductor and
capacitors to perform power conversion.
QH is on as a fraction of the total switching period is
known as the duty cycle D, which is described by the
following equation:
VOUT
---------------
D ≈
VIN
Figure 6 illustrates the basic synchronous buck con-
verter topology showing the primary power train com-
ponents. This converter is also called a step-down
converter, as the output voltage must always be lower
than the input voltage.
During time D, QH is on and VIN –VOUT is applied
across the inductor. The current ramps up as shown in
Figure 7.
VIN
VIN – VOUT
DB
ILpk
CIN
VR
BST
QH
QL
GH
SW
L1
CB
ZL
0
Io
VOUT
COUT
GL
ILv
-VOUT
Figure 6. Synchronous Buck Converter
D
1-D
In its most simple configuration, the ZL2005P requires
two external N-channel power MOSFETs, one for the
top control MOSFET (QH) and one for the bottom
synchronous MOSFET (QL). The amount of time that
Time
Figure 7. Inductor Waveform
FN6849.3
December 16, 2011
11
ZL2005P
When QH turns off (time 1-D), the current flowing in
high-side and low-side MOSFETs to optimize the
overall efficiency of the power supply.
the inductor must continue to flow from the ground up
through QL, during which the current ramps down.
Since the output capacitor COUT exhibits a low imped-
ance at the switching frequency, the AC component of
the inductor current is filtered from the output voltage
so the load sees nearly a DC voltage.
4.4 Power Management Overview
The ZL2005P incorporates a wide range of configu-
rable power management features that are simple to
implement with no external components. Addition-
ally, the ZL2005P includes circuit protection features
that continuously safeguard the load from damage due
to unexpected system faults. The ZL2005P can contin-
uously monitor input voltage, output voltage/current,
internal temperature, and the temperature of an exter-
nal thermal diode. A Power Good output signal is pro-
vided to enable power-on reset functionality for an
external processor.
Typically, buck converters specify a maximum duty
cycle that effectively limits the maximum output volt-
age that can be realized for a given input voltage. This
duty cycle limit ensures that the low-side MOSFET is
allowed to turn on for a minimum amount of time dur-
ing each switching cycle, which enables the bootstrap
capacitor (CB in Figure 6) to be charged up and pro-
vide adequate gate drive voltage for the high-side
MOSFET. See Section 5.2, “High-side Driver Boost
Circuit,” for more details.
All power management functions can be configured
using either simple pin configuration techniques (Fig-
ure 8) or via the I2C/SMBus interface. Monitoring
parameters can be pre-configured to provide alerts for
specific conditions. See Application Note AN2013 for
more details on SMBus monitoring.
In general, the size of components L1 and COUT as
well as the overall efficiency of the circuit are
inversely proportional to the switching frequency, fSW
.
Therefore, the highest efficiency circuit may be real-
ized by switching the MOSFETs at the lowest possible
frequency; however, this will result in the largest com-
ponent size. Conversely, the smallest possible foot-
print may be realized by switching at the fastest
possible frequency but this gives a somewhat lower
efficiency. Each user should determine the optimal
combination of size and efficiency when determining
the switching frequency for each application.
4.5 Multi-mode Pins
In order to simplify circuit design, the ZL2005P incor-
porates patented multi-mode pins that allow the user to
easily configure many aspects of the device without
requiring the user to program the IC. For the ZL2005P
only a few of the power management features can be
configured using these pins. The multi-mode pins can
respond to four different connections as shown in
Table 5. Any combination of connections is allowed
among the multi-mode pins. These pins are sampled
when power is applied or by issuing a PMBus Restore
command (See Application Note AN2013).
The block diagram for the ZL2005P is illustrated in
Figure 5. In this circuit, the target output voltage is
regulated by connecting the VSEN pin directly to the
output regulation point. The VSEN signal is then com-
pared to a reference voltage that has been set to the
desired output voltage level by the user. The error sig-
nal derived from this comparison is converted to a dig-
ital value with a low-resolution analog to digital (A/D)
converter. The digital signal is applied to an adjustable
digital compensation filter, and the compensated sig-
nal is used to derive the appropriate PWM duty cycle
for driving the external MOSFETs in a way that pro-
duces the desired output.
Table 5. Multi-mode Pin Configuration
Pin Tied To
Value
GND
(Logic low)
< 0.8 VDC
OPEN
(N/C)
No connection
The ZL2005P also incorporates a non-linear response
(NLR) loop to reduce the response time and output
deviation in response to a load transient. The ZL2005P
has an efficiency optimization circuit that continu-
ously monitors the power converter’s operating condi-
tions and adjusts the turn-on and turn-off timing of the
HIGH
(Logic high)
> 2.0 VDC
Resistor to SGND
Set by resistor value
FN6849.3
December 16, 2011
12
ZL2005P
Resistor Settings: This method allows a greater range
of adjustability when connecting a finite valued resis-
tor (in a specified range) between the multi-mode pin
and SGND. Standard 1% resistor values are used, and
only every fourth E96 resistor value is used so that the
device can reliably recognize the value of resistance
connected to the pin while eliminating the errors asso-
ciated with the resistor accuracy. A total of 25 unique
selections are available using a single resistor.
Logic
high
ZL
ZL
Open
Multi-mode Pin
Multi-mode Pin
RSET
Logic
low
Pin-strap
Settings
Resistor
Settings
Figure 8. Pin-strap and Resistor Setting
Examples
I2C/SMBus Settings: Almost any ZL2005P function
can be configured via the I2C/SMBus interface using
standard PMBus commands. Additionally, any value
that has been configured using the pin-strap or resistor
setting methods can also be re-configured and/or veri-
fied via the I2C/SMBus. See Application Note
AN2013 for details.
Pin-strap Settings: This is the simplest implementa-
tion method, as no external components are required.
Using this method, each pin can take on one of three
possible states: GND, OPEN, or HIGH. These pins
can be connected to the VR or V25 pins for logic
HIGH settings, as either pin provides a regulated volt-
age greater than 2V. Using a single pin, the user can
select one of three settings, and using two pins, the
user can select one of nine settings.
The SMBus device address and VOUT_MAX are the
only parameters that must be set by external pins. All
other device parameters can be set via the I2C/SMBus.
the device address is set using the SA0 and SA1 pins.
The VOUT_MAX is determined as 10% greater than
the voltage set by the V0/V1 pins or VADJ pin.
FN6849.3
December 16, 2011
13
ZL2005P
5
Power Conversion Functional Description
5.1 Internal Bias Regulators and Input
Supply Connections
5.2 High-side Driver Boost Circuit
The gate drive voltage for the upper MOSFET driver
is generated by a floating bootstrap capacitor, CB (see
Figure 3). When the lower MOSFET (QL) is turned
on, the SW node is pulled to ground and the capacitor
is charged from the internal VR bias regulator through
diode DB. When QL turns off and the upper MOSFET
(QH) turns on, the SW node is pulled up to VDD and
the voltage on the BST pin is boosted approximately
5V above VIN to provide the necessary voltage for the
high-side driver. A Schottky diode should be used for
DB to maximize the high-side drive voltage.
The ZL2005P employs two internal low dropout
(LDO) regulators to supply bias voltages for internal
circuitry, allowing it to operate from a single input
supply. The internal bias regulators are as follows:
VR: The VR LDO provides a regulated 5V bias supply
for the MOSFET driver circuits. It is powered
from the VDD pin and can supply up to 100 mA
output current. A 4.7 µF filter capacitor is
required at the VR pin.
V25: The V25 LDO provides a regulated 2.5V bias
supply for the main controller circuitry. It is
powered from an internal 5V node and can sup-
ply up to 50 mA output current. A 10 µF filter
capacitor is required at the V25 pin.
5.3 Output Voltage Selection
Standard Mode (ZL2005)
The output voltage may be set to any voltage between
0.6V and 5.0V provided that the input voltage is
higher than the desired output voltage by an amount
sufficient to prevent the device from exceeding its
maximum duty cycle specification. By connecting the
V0 and V1 pins to logic high, logic low, or leaving
them floating, VOUT can be set to any of nine standard
voltages as shown in Table 6.
Note: The internal bias regulators are designed for
powering internal circuitry only. Do not attach exter-
nal loads to any of these pins. The multi-mode pins
may be connected to the VR or V25 pins for logic
HIGH settings.
When the input supply (VDD) is higher than 5.5V, the
VR pin should not be connected to any other pin. It
should only have a filter capacitor attached as shown
in Figure 9. Due to the dropout voltage associated with
the VR bias regulator, the VDD pin must be connected
to the VR pin for designs operating from a VDD sup-
ply from 3.0V to 5.5V. Figure 9 illustrates the required
connections for both cases. For input supplies between
4.5V and 5.5V, either method can be used.
Table 6. Pin-strap Output Voltage Settings
V0
LOW
0.6V
1.2V
2.5V
OPEN
0.8V
1.5V
3.3V
HIGH
1.0V
1.8V
5.0V
LOW
OPEN
HIGH
V1
If an output voltage other than those in Table 6 is
desired, the resistor setting method can be used. Using
this method, resistors R0 and R1 are selected to pro-
duce a specific voltage between 0.6V and 5.0V in 10
mV steps. Resistor R1 provides a coarse setting and
R0 a fine adjustment, thus eliminating the additional
errors associated with using two 1% resistors in a stan-
dard analog implementation (this typically adds 1.4%
error using two 1% resistors).
To set VOUT using resistors, follow the steps below to
calculate an index value and then use Table 7 to select
the resistor that corresponds to the calculated index
value as follows:
Figure 9. Input Supply Connections
FN6849.3
December 16, 2011
14
ZL2005P
1. Calculate Index1:
Index1 = 4 x VOUT
2. Round the result down to the nearest whole num-
ber.
3. Select the value for R1 from Table 7 using the
Index1 rounded value from step 2.
4. Calculate Index0 using equation
Index0 = 100 x VOUT - 25 x Index1...
5. Select the value for R0 from Table 7 using Index0
from step 4.
Figure 10. Output Voltage Resistor Setting
Table 7. Resistors for Setting Output Voltage
The output voltage may also be set to any value
between 0.6V and 5.0V using the I2C/SMBus inter-
face. The maximum voltage that can be set is limited
to 110% of the pin-strap value. See Application Note
AN2013 for details.
Index
R0 or R1
Index
13
R0 or R1
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
0
1
10 kΩ
11 kΩ
14
2
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
15
POLA/DOSA Trim Method
3
16
The output voltage can also be set using the VADJ pin
to map the standard analog resistor method. This mode
is activated by setting the PMBus private command
POLA_VADJ_CONFIG to 1.
4
17
5
18
6
19
7
20
The POLA/DOSA mode can also be set up by pinstrap
using a resistor on V0.
8
21
9
22
82.5 kΩ
90.9 kΩ
100 kΩ
A 110 kΩ resistor on V0 will set to POLA mode 1.
A 120 kΩ resistor on V0 will set to POLA mode 2.
10
11
12
23
24
In POLA mode 1 and 2, V0 and V1 pins are inactive,
and the ZL2005P uses the following table to set the
output voltage with the VADJ pin.
Example:
For VOUT = 1.33V:
Index1 = 4 x 1.33V = 5.32 (5);
From Table 7, using Index = 5
R1 = 16.2 kΩ
Index0 = (100 x 1.33V) - (25 x 5) = 8;
From Table 7; R0 = 21.5 kΩ
FN6849.3
December 16, 2011
15
ZL2005P
DOSA Voltage Trim Method
Table 8. Resistors for Setting POLA Output
Voltage with VADJ
For DOSA output voltage selection, a 8.66 kΩ resistor
needs to be used in place of the 10 kΩ resistor. This
will allow setting the output voltage with resistor val-
ues close to the DOSA equation result:
V
V
OUT
R
SET (kΩ)
RSET (kΩ)
OUT
Min / Typ / Max
Min / Typ / Max
0.700V
155 / 159 / 169
0.991V
1.000V
1.100V
1.158V
1.200V
1.250V
1.500V
1.669V
1.800V
2.295V
2.506V
3.300V
5.000V
21.38 / 21.6 / 21.82
Rset = 6900/(VOUT – 0.69V).
0.752V 109.89 / 111 / 112.11
18.51 / 18.7 / 18.89
15.94 / 16.1 / 16.26
13.56 / 13.7 / 13.84
11.39 / 11.5 / 11.62
9.5 / 9.6 / 9.7
0.758V
0.765V
0.772V
0.790V
0.800V
0.821V
0.848V
0.880V
0.899V
0.919V
0.965V
99 / 100 / 101
Table 9. Resistors for Setting DOSA Output
Voltage with VADJ
89.1 / 90 / 90.9
80.09 / 80.9 / 81.71
64.35 / 72.5 / 73.23
57.52 / 58.1 / 58.68
51.38 / 51.9 / 52.42
40.69 / 41.1 / 41.51
36.04 / 36.4 / 36.76
31.88 / 32.2 / 32.52
28.02 / 28.3 / 28.58
24.55 / 24.8 / 25.05
V
V
OUT
R
SET (kΩ)
RSET (kΩ)
Min / Typ / Max
OUT
Min / Typ / Max
7.72 / 7.8 / 7.88
6.14 / 6.2 / 6.26
4.65 / 4.7 / 4.75
3.27 / 3.3 / 3.33
2.08 / 2.1 / 2.12
0.99 / 1 / 1.01
0.700V
156 / 160 / 170
0.991V 22.71 / 22.94 / 23.17
1.000V 19.84 / 20.04 / 20.24
1.100V 17.27 / 17.44 / 17.61
1.158V 14.89 / 15.04 / 15.19
1.200V 12.71 / 12.84 / 12.97
1.250V 10.83 / 10.94 / 11.05
0.752V 111.22 / 112.34 / 113.46
0.758V 100.33 / 101.34 / 102.35
0.765V
0.772V
0.790V
0.800V
0.821V
0.848V
0.880V
0.899V
0.919V
0.965V
90.43 / 91.34 / 92.25
81.42 / 82.24 / 83.06
65.68 / 73.84 / 74.58
58.85 / 59.44 / 60.03
52.71 / 53.24 / 53.77
42.02 / 42.44 / 42.86
37.36 / 37.74 / 38.12
33.20 / 33.54 / 33.88
29.34 / 29.64 / 29.94
25.88 / 26.14 / 26.40
0 / 0 / 0.05
1.500V
1.669V
1.800V
2.295V
2.506V
3.300V
5.000V
9.05 / 9.14 / 9.23
7.46 / 7.54 / 7.62
5.98 / 6.04 / 6.10
4.59 / 4.64 / 4.69
3.41 / 3.44 / 3.47
2.32 / 2.34 / 2.36
1.33 / 1.34 / 1.35
The standard method for adjusting output voltage used
in a POLA module is defined by the below equation:
R
= 10kΩ x 0.69V/(V
– 0.69V) – 1.43kΩ
OUT
set
Rset is an external resistor.
POLA Module
0.69V
+
UVLO (POLA Mode)
ZL2005P
MODULE
In POLA mode 1 and 2, undervoltage threshold
(UVLO) is set following POLA standard methodol-
ogy.
VOUT
-
VADJ
10
kOhm
10
kOhm
1.43
kOhm
In the POLA standard, a resistor on the UVLO pin sets
the corresponding voltage value.
RSET
RSET
For a module supplier, a 1.5 kΩ 1% pull-up resistor
from EN to UVLO is required to be compatible with
the POLA Inhibit/UVLO features (Figure 12). EN
must be driven by an open collector/drain driver, and
will default to Enabled unless pulled low. The driver
must remain open after a transition for a minimum of 1
ms to allow the measurement of the resistor on the
UVLO pin.
Figure 11. Output Voltage Resistor Setting
POLA - ZL2005P
To stay compatible with existing methods for adjusting
output voltage, the module manufacturer can add a 10
kΩ resistor on the module.
RVADJ = RSET +10 kΩ
By adding this additional resistor, the resistor values
shown in Table 8 can be used to set the output voltage
of a ZL2005P module. These values are close to the
analog POLA values and are compatible with the pin-
strap resistor detection methodology of the ZL2005P.
By default UVLO is set to 4.5V.
FN6849.3
December 16, 2011
16
ZL2005P
ZL2005P
MODULE
ZL2005P
MODULE
UVLO
EN
UVLO
EN
1.5 kOhm
1.5 kOhm
Inhibit/
UVLO
1 = Inhibit
Q1
Inhibit/
UVLO
RUVLO
RUVLO
Figure 12. UVLO Circuit
Figure 12 shows how to select UVLO based on an
external resistor RSET
Figure 13. INHIBIT Circuit
Figure 13 shows the typical application of the Inhibit
function. The inhibit input has its own internal pull-up.
An open-drain transistor is recommended for control.
.
RUVLO maps the POLA equation to set the UVLO
threshold:
Flexible pin
RUVLO = (9690 - (137*VIN))/(137*VIN-585) in kΩ
When POLA_VADJ_CONFIG is set to mode 2, the
ZL2005P uses the VADJ pin for output voltage setting
and it also disables the SYNC pin. In this mode, the
ZL2005P is not checking the SYNC pin for synchroni-
zation to an external signal. Otherwise the resistor
measurement may not be accurate. This configuration
allows a module supplier to connect both VADJ and
SYNC pin to a common pin on the module (Flex pin).
A single module pin can then be used for one or the
other function.
Table 10 shows a chart of standard resistor values for
RUVLO
:
Table 10. Resistors for Setting UVLO with
RUVLO
R
R
UVLO
UVLO
UVLO
UVLO
in series with
in series with
1.5 kΩ
1.5 kΩ
resistor
resistor
4.3V
4.5V
162 kΩ
121 kΩ
110 kΩ
100 kΩ
90.9 kΩ
82.5 kΩ
75.0 kΩ
68.1 kΩ
61.9 kΩ
56.2 kΩ
51.1 kΩ
46.4 kΩ
42.2 kΩ
6.20V
6.60V
6.96V
7.22V
7.50V
7.81V
8.13V
8.50V
8.92V
9.34V
9.81V
10.86V
11.46V
38.3 kΩ
28.7 kΩ
23.7 kΩ
21.5 kΩ
19.6 kΩ
17.8 kΩ
16.2 kΩ
14.7 kΩ
13.3 kΩ
12.1 kΩ
11.0 kΩ
9.09 kΩ
8.25 kΩ
In this mode UVLO will also follow the POLA
method.
4.87V
4.93V
4.99V
5.07V
5.15V
5.23V
5.33V
5.43V
5.55V
5.67V
5.81V
FLEX PIN
10kO
SYNC
VADJ
ZL2005P
MODULE
Figure 14. Output Voltage Resistor Setting
Example
For a POLA module, the Inhibit feature is combined
with UVLO.
FN6849.3
December 16, 2011
17
ZL2005P
Once this process is completed, the device is ready to
5.4 Start-up Procedure
accept commands via the I2C/SMBus interface and the
device is ready to be enabled. Once enabled, the
device requires approximately 6 ms before its output
voltage may be allowed to start its ramp-up process. If
a soft start delay period less than 6 ms has been con-
figured (using the DLY (0,1) pins), the device will
default to a 6 ms delay period. If a delay period of 6
ms or higher is configured, the device will wait for the
configured delay period before starting to ramp its out-
put.
The ZL2005P follows a specific internal start-up pro-
cedure after power is applied to the VDD pin. Table 11
describes the start-up sequence.
If the device is to be synchronized to an external clock
source, the clock must be stable prior to asserting the
EN pin. The device requires approximately 10-20 ms
to check for specific values stored in its internal mem-
ory.
After the delay period has expired, the output will
begin to ramp towards its target voltage according to
the pre-configured soft-start ramp time.
If the user has stored values in memory, those values
will be loaded. The device will then check the status of
all multi-mode pins and load the values associated
with the pin settings.
Table 11. ZL2005P Start-up Sequence
Step #
Step Name
Description
Time Duration
Depends on input supply
ramp time
1
Power Applied Input voltage is applied to the ZL2005P’s VDD pin
The device will check for values stored in its internal
memory. This step is also performed after a Restore
command.
Internal Memory
Approx 10-20 ms (device
will ignore an enable signal
or PMBus traffic during this
period)
2
Check
Multi-mode
Pin Check
The device loads values configured by multi-mode
pins.
3
4
Device Ready The device is ready to accept an ENABLE signal.
—
The device requires approximately 6 ms following an
enable signal and prior to ramping its output.
Pre-ramp Delay
5
Approx. 6 ms
Additional pre-ramp delay may be configured using
the Delay pins.
FN6849.3
December 16, 2011
18
ZL2005P
5.5 Soft Start Delay and Ramp Times
Table 13. Soft Start Ramp Settings
SS0
OPEN
1 ms
In some system applications, it may be necessary to set
a delay from when an enable signal is received until
the output voltage starts to ramp to its nominal value.
In addition, the designer may wish to precisely set the
time required for VOUT to ramp to its nominal value
after the delay period has expired. The ZL2005P gives
the system designer several options for precisely and
independently controlling both the delay and ramp
time periods for VOUT. These features may be used as
part of an overall in-rush current management strategy
or to precisely control how fast a load IC is turned on.
LOW
HIGH
1
LOW
2 ms
0 ms
SS1
5 ms
10 ms
20 ms
OPEN
HIGH
50 ms
100 ms
200 ms
NOTE:
1. When the soft start ramp is set to zero, the device will ramp up as
quickly as the internal circuitry and output load capacitance will
allow.
If the desired soft start delay and ramp times are not
one of the values listed in Table 11 and Table 12, the
times can be set to a custom value by connecting a
resistor from the DLY0 or SS0 pin to SGND using the
appropriate resistor value from Table 14. The value of
this resistor is measured upon start-up or Restore and
will not change if this resistor is varied after power has
been applied to the ZL2005. See Figure 15 for typical
connections using resistors.
The soft start delay period begins when the Enable pin
is asserted and ends when the delay time expires. The
soft-start delay period is set via the I2C/SMBus inter-
face.The soft start ramp enables a controlled ramp to
the nominal VOUT value that begins once the delay
period has timed out. The ramp-up is guaranteed
monotonic and its slope may be precisely set by set-
ting the soft-start ramp time using the SS (0,1) pins.
Note: Do not connect a resistor to the DLY1 or SS1
pin. These pins are not utilized for setting soft-start
delay and ramp times. Connecting an external resistor
to these pins may cause conflicts with other device set-
tings.
The soft start delay and ramp times can be set to stan-
dard values according to Table 12 and Table 13
respectively.
Table 12. Soft Start Delay Settings
DLY0
RDLY
N/C
LOW
OPEN
HIGH
1
LOW
OPEN
HIGH
0 ms
Reserved
DLY1
1
ZL2005P
10 ms
20 ms
5 ms
50 ms
100 ms
200 ms
NOTE:
1. When the device is set to 0 ms or 5 ms delay, it will begin its ramp up
after the internal circuitry has initialized (approx. 6 ms).
N/C
RSS
Figure 15. DLY and SS Pin Resistor
Connections
FN6849.3
December 16, 2011
19
ZL2005P
A PG delay period is defined as the time from when all
Table 14. DLY and SS Resistor Values
conditions within the ZL2005P for asserting PG are
met to when the PG pin is actually asserted. This fea-
ture is commonly used instead of using an external
reset controller to control external digital logic. By
default, the ZL2005P PG delay is set equal to the soft-
start ramp time setting. Therefore, if the soft-start
ramp time is set to 10 ms, the PG delay will be set to
10 ms. The PG delay may be set independently of the
soft-start ramp using the I2C/SMBus as described in
Application Note AN2013.
R
or
R
or
DLY
DLY or
SS
DLY or
SS
DLY
R
R
SS
SS
0 ms
10 ms
20 ms
30 ms
40 ms
50 ms
60 ms
70 ms
80 ms
90 ms
100 ms
10 kΩ
11 kΩ
110 ms
120 ms
130 ms
140 ms
150 ms
160 ms
170 ms
180 ms
190 ms
200 ms
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
5.7 Switching Frequency and PLL
The ZL2005P incorporates an internal phase locked
loop (PLL) to clock the internal circuitry. The PLL can
be driven by an internal oscillator or driven from an
external clock source connected to the SYNC pin.
When using the internal oscillator, the SYNC pin can
be configured as a clock output for use by other
devices. The SYNC pin is a unique pin that can per-
form multiple functions depending on how it is config-
ured. The CFG pin is used to select the operating mode
of the SYNC pin as shown in Table 15. Figure 16
illustrates the typical connections for each mode.
The soft start delay and ramp period can be set to cus-
tom values via the I2C/SMBus interface. When the
soft start delay is set to 0 ms, the device will begin its
ramp up after the internal circuitry has initialized
(approx. 6ms).
5.6 Power Good
Table 15. SYNC Pin Function Selection
The ZL2005P provides a Power Good (PG) signal that
indicates the output voltage is within a specified toler-
ance of its target level and no fault condition exists. By
default, the PG pin will assert if the output is within -
10% to +15% of the target voltage These limits may
be changed via the I2C/SMBus interface. See Applica-
tion Note AN2013 for details.
CFG Pin
SYNC Pin Function
SYNC is configured as an input
Auto Detect mode
LOW
OPEN
SYNC is configured as an output
fSW = 400 kHz (default)
HIGH
FN6849.3
December 16, 2011
20
ZL2005P
Logic
high
SYNC
SYNC
200 kHz – 1.4 MHz
200 kHz – 1.4 MHz
ZL
ZL
A) SYNC = output
B) SYNC = input
N/C
N/C
N/C
Logic
high
Open
SYNC
SYNC
SYNC
200 kHz – 1.4 MHz
OR
OR
RSYNC
ZL
ZL
ZL
Logic
low
C) SYNC = Auto Detect
Figure 16. SYNC Pin Configurations
Configuration A: SYNC OUTPUT
Configuration C: SYNC AUTO DETECT
When the SYNC pin is configured as an output (CFG
pin is tied HIGH), the device will operate from its
internal oscillator and will drive the resulting internal
oscillator signal (preset to 400 kHz) onto the SYNC
pin so other devices can be synchronized to it. The
SYNC pin will not be checked for an incoming clock
signal while in this configuration.
When the SYNC pin is configured in auto detect mode
(CFG pin is left OPEN), the device will automatically
check for a clock signal on the SYNC pin after enable
is asserted.
If a clock signal is present, The ZL2005P’s oscillator
will then synchronize the rising edge of the external
clock. Refer to SYNC INPUT description.
Configuration B: SYNC INPUT
If no incoming clock signal is present, the ZL2005P
will configure the switching frequency according to
the state of the SYNC pin as listed in Table 16. In this
mode, the ZL2005P will only read the SYNC pin con-
nection during the start-up sequence. Changes to
SYNC pin connections will not affect fSW until the
power (VDD) is cycled off and on.
When the SYNC pin is configured as an input (CFG
pin is tied LOW), the device will automatically check
for a clock signal on the SYNC pin each time EN is
asserted. The ZL2005P’s oscillator will then synchro-
nize with the rising edge of external clock.
The incoming clock signal must be in the range of 200
kHz to 1.4 MHz and must be stable when the enable
pin is asserted. The clock signal must also exhibit the
necessary performance requirements (see Table 3). In
the event of a loss of the external clock signal, the out-
put voltage may show transient over/undershoot.
Table 16. Switching Frequency Selection
SYNC Pin Setting
LOW
Frequency
200 kHz
OPEN
400 kHz
HIGH
1 MHz
Resistor
See Table 17
If this happens, the ZL2005P will turn off the power
FETs (QH and QL in Figure 4) typically within 10 μS.
Users are discouraged from removing an external
SYNC clock while the ZL2005P is operating with
Enable asserted.
If the user wishes to run the ZL2005P at a frequency
other than those listed in Table 16, the switching fre-
quency can be set using an external resistor, RSYNC
,
connected between SYNC and SGND using Table 17.
FN6849.3
December 16, 2011
21
ZL2005P
To select the appropriate power stage components for
a set of desired performance goals, the power supply
requirements listed in Table 18 must be known.
Table 17. RSYNC Resistor Values
R
R
SYNC
fSW
fSW
SYNC
200 kHz
222 kHz
242 kHz
267 kHz
296 kHz
320 kHz
364 kHz
400 kHz
421 kHz
471 kHz
10 kΩ
11 kΩ
533 kHz
571 kHz
615 kHz
667 kHz
727 kHz
889 kHz
1000 kHz
1143 kHz
1333 kHz
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
68.1 kΩ
Table 18. Power Supply Requirements
Example
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
Example
Parameter
Range
Value
12 V
1.2 V
20 A
Input voltage (VIN)
3.0 – 14.0 V
0.6 – 5.0 V
0 to ~25 A
Output voltage (VOUT
)
Output current (IOUT
Output voltage ripple
(Vorip
)
< 3% of
VOUT
1% of
VOUT
)
Output load step (Iostep
Output load step rate
Allowable output
deviation due to load step
Maximum PCB temp.
Desired efficiency
)
< Io
—
50% of Io
10 A/µS
The switching frequency can also be set to any value
between 200 kHz and 1.4 MHz using the I2C/SMBus
interface. The available frequencies are bounded by
the relation fsw = 8 MHz/N, (with 6<= N <= 40). See
Application Note AN2013 for details on configuring
the switching frequency using the I2C/SMBus inter-
face.
—
± 50 mV
120°C
—
85°C
85%
Optimize
for small
size
Other considerations
Various
If multiple ZL2005Ps are used together, connecting
the SYNC pins together will force all devices to syn-
chronize to one another. The CFG pin of one device
must have its SYNC pin set as an output and the
remaining devices must have their SYNC pins set as
an input or all devices must be driven by the same
external clock source.
Design Trade-offs
The design of a switching regulator power stage
requires the user to consider trade-offs between cost,
size and performance. For example, size can be opti-
mized at the expense of efficiency. Additionally, cost
can be optimized at the expense of size. For a detailed
description of circuit trade-offs, refer to Application
Note AN2011.
Note: The switching frequency read back using the
appropriate PMBus command will differ slightly from
the selected value in Table 17. The difference is due to
hardware quantization.
To start a design, select a switching frequency (fSW
based on Table 19. This frequency is a starting point
and may be adjusted as the design progresses.
)
5.8 Selecting Power Train Components
Table 19. Circuit Design Considerations
Frequency
The ZL2005P is a synchronous buck controller that
uses external MOSFETs, inductor and capacitors to
perform the power conversion process. The proper
selection of the external components is critical for
optimized performance. Zilker Labs offers an online
circuit design and simulation tool, PowerPilot, to
assist designers in this task.
Efficiency
Circuit Size
Range
200 – 400 kHz
400 – 800 kHz
800 – 1400 kHz
Highest
Moderate
Lower
Larger
Smaller
Smallest
Inductor Selection
The output inductor selection process will include sev-
eral trade-offs. A high inductance value will result in a
low ripple current (Iopp), which will reduce the output
capacitance requirement and produce a low output rip-
ple voltage, but may also compromise output transient
load performance. Therefore, a balance must be
Please visit www.intersil.com/zilkerlabs/ to access
PowerPilot. For more detailed guidelines regarding
component selection, please refer to Application Note
AN2011.
FN6849.3
December 16, 2011
22
ZL2005P
struck between output ripple and optimal load tran-
to the maximum power dissipation recommendation in
the inductor datasheet.
sient performance. A good starting point is to select
the output inductor ripple current (Iopp) equal to the
expected load transient step magnitude (Iostep):
Output Capacitor Selection
Several trade-offs also must be considered when
selecting an output capacitor. Low ESR values are
needed to have a small output deviation during tran-
sient load steps (Vosag) and low output voltage ripple
(Vorip). However, capacitors with low ESR, such as
semi-stable (X5R and X7R) dielectric ceramic capaci-
tors, also have relatively low capacitance values.
Many designs can use a combination of high capaci-
tance devices and low ESR devices in parallel.
(3)
I opp = I ostep
Now the output inductance can be calculated using the
following equation:
1− VV
OUT
VOUT
×
INM
(4)
LOUT
=
fsw × Iopp
For high ripple currents, a low capacitance value can
cause a significant amount of output voltage ripple.
Likewise, in high transient load steps, a relatively
large amount of capacitance is needed to minimize the
output voltage deviation while the inductor current
ramps up to the new steady state output current value.
where VINM is the maximum input voltage.
The average inductor current is equal to the maximum
output current. The peak inductor current (ILpk) is cal-
culated using the following equation where IOUT is the
maximum output current:
As a starting point, allocate one-half of the output volt-
age ripple to the capacitor ESR and the other half to its
capacitance, as shown in the following equations:
Iopp
ILpk = IOUT
+
(5)
2
Iopp
8× fsw × V
Select an inductor rated for the average DC current
with a peak current rating above the peak current com-
puted above.
(8)
COUT
=
orip
2
In over-current or short-circuit conditions, the inductor
may have currents greater than 2X the normal maxi-
mum rated output current. It is desirable to use an
inductor that is not saturated at these conditions to pro-
tect the load and the power supply MOSFETs from
damaging currents.
Vorip
(9)
ESR =
2× Iopp
Use these values to make an initial capacitor selection,
using a single capacitor or several capacitors in paral-
lel.
Once an inductor is selected, the DCR and core losses
in the inductor are calculated. Use the DCR specified
in the inductor manufacturer’s datasheet.
After a capacitor has been selected, the resulting out-
put voltage ripple can be calculated using the follow-
ing equation:
2
(6)
P
= DCR× ILrms
LDCR
(10)
Iopp
ILrms is given by:
Vorip = Iopp × ESR +
8× fsw ×COUT
2
Iopp
2
(7)
ILrms = IOUT
+
12
Because each part of this equation was made to be less
than or equal to half of the allowed output ripple volt-
age, the Vorip should be less than the desired maximum
output ripple.
where IOUT is the maximum output current. Next, cal-
culate the core loss of the selected inductor. Since this
calculation is specific to each inductor and manufac-
turer, refer to the chosen inductor’s datasheet. Add the
core loss and the DCR loss and compare the total loss
For more information on the performance of the power
supply in response to a transient load, refer to Applica-
tion Note AN2011.
FN6849.3
December 16, 2011
23
ZL2005P
Input Capacitor
Calculate the desired maximum RDS(ON) as follows:
It is highly recommended that dedicated input
capacitors be used in any point-of-load design, even
when the supply is powered from a heavily filtered 5
or 12 V “bulk” supply. This is because of the high
RMS ripple current that is drawn by the buck
converter topology. This input ripple (ICINrms) can be
determined from the following equation:
2
(14)
R
DS(ON) = PQL/Ibotrms
Note that the RDS(ON) given in the manufacturer’s
datasheet is measured at 25°C. The actual RDS(ON) in
the end-use application will be much higher. For
example, a Vishay Si7114 MOSFET with a junction
temperature of 125°C has an RDS(ON) 1.4 times higher
than the value at 25°C.
(11)
ICINrms = IOUT × D×
(
1− D
)
Select a candidate MOSFET, and calculate the
required gate drive current as follows:
Please refer to Application Note AN2011 for detailed
derivation including efficiency and ripple current.
(15)
Ig = fsw ×Qg
Keep in mind that the total allowed gate drive current
for both QH and QL is 80 mA.
Without capacitive filtering near the power supply
input circuit, this current would flow through the sup-
ply bus and return planes, coupling noise into other
system circuitry. The input capacitors should be rated
at 1.2X the ripple current calculated above to avoid
overheating of the capacitors due to the high ripple
current, which can cause premature failure. Ceramic
capacitors with X7R or X5R dielectric with low ESR
and 1.1X the maximum expected input voltage are rec-
ommended.
MOSFETs with lower RDS(ON) tend to have higher
gate charge requirements, which increases the current
and resulting power required to turn them on and off.
Since the MOSFET gate drive circuits are integrated
in the ZL2005P, this power is dissipated in the
ZL2005P according to the following equation:
P
= fsw ×Qg ×VINM
(16)
QL
Bootstrap Circuit Component Selection
QH Selection
The high-side driver boost circuit utilizes an external
Schottky diode (DB) and an external bootstrap capaci-
tor (CB) to supply sufficient gate drive for the high-
side MOSFET driver. DB should be a 20 mA, 30 V
Schottky diode or equivalent device and CB should be
a 1 µF ceramic type rated for at least 6.3V.
In addition to the RDS(ON) loss and gate charge loss,
QH also has switching loss. The procedure to select
QH is similar to the procedure for QL. First, assign 2–
5% of the output power to be dissipated in the RDS(ON)
of QH using the equation for QL above. As was done
with QL, calculate the RMS current as follows:
QL Selection
The bottom MOSFET should be selected primarily
based on the device’s RDS(ON) and secondarily based
on its gate charge. To choose QL, use the following
equation and allow 2–5% of the output power to be
dissipated in the RDS(ON) of QL (lower output voltages
and higher step-down ratios will be closer to 5%):
Itoprms = ILrms × D
(17)
Calculate a starting RDS(ON) as follows, in this exam-
ple using 5%:
PQH = 0 .05 × V OUT × I OUT
(18)
(12)
PQL = 0 .05 × V OUT × I OUT
2
Calculate the RMS current in QL as follows:
R
DS(ON) = PQH / Itoprms
(19)
Ibotrms = ILrms × 1− D
(13)
Select a MOSFET and calculate the resulting gate
drive current. Verify that the combined gate drive cur-
rent from QL and QH does not exceed 80 mA.
FN6849.3
December 16, 2011
24
ZL2005P
Next, calculate the switching time using:
VIN
GH
SW
Q
g
(20)
t
=
sw
VOUT
I
gdr
ZL
GL
CL
R1
R2
where Qg is the gate charge of the selected QH and
Igdr is the peak gate drive current available from the
ZL2005P.
ISENA
ISENB
Figure 17. DCR Current Sensing
Although the ZL2005P has a typical gate drive current
of 3 A, use the minimum guaranteed current of 2 A for
a conservative design. Using the calculated switching
time, calculate the switching power loss in QH using
These components should be selected according to the
following equation:
τ
RC = L / DCR-------------------------- (24)
P
=VINM ×tsw × IOUT × fsw
R1 should be in the range of 500 Ω to 5 kΩ in order to
minimize the power dissipation through it. The user
should make sure the resistor package size is appropri-
ate for the power dissipated. Once R1 has been calcu-
lated, the value of R2 should be selected based on the
following equation:
(21)
swtop
The total power dissipated by QH is given by the fol-
lowing equation:
(22)
PQHtot = PQH + Pswtop
R2 = 5 x R1 -----------------------------(25)
MOSFET Thermal Check
If RDS(ON) is being used the external low side MOS-
FET will act as the sensing element as indicated in
Figure 18.
Once the power dissipations for QH and QL have been
calculated, the MOSFET’s junction temperature can
be estimated. Using the junction-to-case thermal resis-
tance (Rth) given in the MOSFET manufacturer’s data-
sheet and the expected maximum printed circuit board
temperature, calculate the junction temperature as fol-
lows:
5.9 Current Limit Threshold Selection
It is recommended that the user include a current limit-
ing mechanism in their design to protect the power
supply from damage and prevent excessive current
from being drawn from the input supply in the event
that the output is shorted to ground or an overload con-
dition is imposed on the output. Current limiting is
accomplished by sensing the current flowing through
the circuit during a portion of the duty cycle.
(23)
T
j max = Tpcb + P × Rth
Q
Current Sensing Components
Once the current sense method has been selected
(Refer to Section 5.9, “Current Limit Threshold Selec-
tion,” ), the procedure to select the component is the
following:
Output current sensing can be accomplished by mea-
suring the voltage across a series resistive sensing ele-
ment according to equation 26.
When using the inductor DCR sensing method, the
user must also select an R/C network comprised of R1
and CL (see Figure 17).
V
LIM = ILIM x RSENSE ---------- -------(26)
Where:
I
LIM is the desired maximum current that should
flow in the circuit
RSENSE is the resistance of the sensing element
VLIM is the voltage across the sensing element at
the point the circuit should start limiting the out-
put current.
FN6849.3
December 16, 2011
25
ZL2005P
The ZL2005P supports “lossless” current sensing, by
The current sensing method can be selected using the
ILIM1 pin using Table 20. The ILIM0 pin must have a
finite resistor connected to ground in order for
Table 20 to be valid. If no resistor is connected
between ILIM0 and ground, the default method is
MOSFET RDS(ON) sensing. The current sensing
method can be modified via the I2C/SMBus interface.
Please refer to Application note AN2013 for details.
measuring the voltage across a resistive element that is
already present in the circuit. This eliminates addi-
tional efficiency losses incurred by devices that must
use an additional series resistance in the circuit.
To set the current limit threshold, the user must first
select a current sensing method. The ZL2005P incor-
porates two methods for current sensing, synchronous
MOSFET RDS(ON) sensing and inductor DC resistance
(DCR) sensing; Figure 18 shows a simplified sche-
matic for each method.
In addition to selecting the current sensing method, the
ZL2005P gives the power supply designer several
choices for the fault response during over or under
current condition. The user can select the number of
violations allowed before declaring fault, a blanking
time and the action taken when a fault is detected.
VIN
GH
SW
The blanking time represents the time when no current
measurement is taken. This is to avoid taking a reading
just after a current load step (Less accurate due to
potential ringing). It is a configurable parameter.
VOUT
ZL
ISENA
GL
ISENB
MOSFET RDS,ON Sensing
Table 20 includes default parameters for the number of
violations and the blanking time using pin-strap.
VIN
GH
SW
VOUT
ZL
GL
ISENA
ISENB
Inductor DCR Sensing
Figure 18. Current Sensing Methods
Table 20. Current Sensing Method Selection
Number of
1
ILIM1 Pin
Current Limiting Configuration
Comments
ILIM0 Pin
2
Violations Allowed
Ground-referenced (RDS,ON) sensing
Blanking time: 672 ns
Best for low duty
cycle and low fSW
RILIM0
LOW
4
Output-referenced, down-slope sensing
(Inductor DCR sensing)
Best for low duty
cycle and high fSW
RILIM0
OPEN
4
Blanking time: 352 ns
Output-referenced, up-slope sensing
(Inductor DCR sensing)
Best for high duty
cycle
RILIM0
HIGH
4
Blanking time: 352 ns
Resistor
Depends on resistor value used; see Table 21
NOTES:
1. 10 kΩ < RILIM0 < 100 kΩ
2. The number of violations allowed prior to issuing a fault response.
FN6849.3
December 16, 2011
26
ZL2005P
Table 21. Resistor Configured Current Sensing Method Selection
Number of Violations
R
Current Sensing Method
ILIM1
1
Allowed
10 kΩ
11 kΩ
1
3
Ground-referenced (RDS,ON) sensing
Best for low duty cycle and low fSW
Blanking time: 672 ns
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
5
7
9
11
13
15
1
3
Output-referenced, down-slope sensing (Inductor DCR sensing)
Best for low duty cycle and high fSW
5
7
9
11
13
15
1
Blanking time: 352 ns
3
Output-referenced, up-slope sensing (Inductor DCR sensing)
Best for high duty cycle
5
7
9
11
13
15
Blanking time: 352 ns
82.5 kΩ
90.9 kΩ
NOTES:
1. The number of violations allowed prior to issuing a fault response.
Once the sensing method has been selected, the user
must select the voltage threshold (VLIM) based on
equation 26, the desired current limit threshold, and
the resistance of the sensing element.
The current limit threshold can be selected by simply
connecting the ILIM0 and ILIM1 pins as shown in
Table 22. The ground-referenced sensing method is
being used in this mode.
Table 22. Current Limit Threshold Voltage
Settings
ILIM0
LOW
20 mV
50 mV
80 mV
OPEN
30 mV
60 mV
90 mV
HIGH
40 mV
70 mV
100 mV
LOW
OPEN
HIGH
ILIM1
The threshold voltage can also be selected in 5 mV
increments by connecting a resistor, RLIM0, between
the ILIM0 pin and ground according to Table 23. This
FN6849.3
December 16, 2011
27
ZL2005P
method is preferred if the user does not desire to use or
VIN
does not have access to the I2C/SMBus interface and
the desired threshold value is contained in Table 23.
D
L
Table 23. Current Limit Threshold Voltage
Settings
DPWM
VOUT
1-D
C
RO
V
R
V
R
LIM0
LIM
LIM0
LIM
RC
0 mV
5 mV
55 mV
60 mV
65 mV
70 mV
75 mV
80 mV
85 mV
90 mV
95 mV
100 mV
10 kΩ
11 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
Compensation
10 mV
15 mV
20 mV
25 mV
30 mV
35 mV
40 mV
45 mV
50 mV
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
Figure 19. Control Loop Block Diagram
In the ZL2005P, the compensation zeros are set by
configuring the FC0 pin or via the I2C/SMBus inter-
face once the user has calculated the required settings.
Most applications can be served by using the pin-strap
compensation settings listed in Table 24. These set-
tings will yield a conservative crossover frequency.
The parameters of the feedback compensation can also
be set using the I2C/SMBus interface. A sofware
(CompZLTM) is also available from Zilker Labs to cal-
culate automatically the compensation parameters.
The current limit threshold can be set via the I2C/
SMBus interface. Please refer to Application Note
AN2013 for further details on setting current limit
parameters.
FC1 pin is not used in the ZL2005P.
Table 24. Pin-Strap Setting for Loop
Compensation
5.10 Loop Compensation
FC0 Pin
HIGH
OPEN
LOW
Description
High Q, Low Bandwidth
Real zeros, High Bandwidth
Low Q, Low Bandwidth
The ZL2005P operates as a voltage-mode synchro-
nous buck controller with a fixed frequency PWM
scheme. Although the ZL2005P uses a digital control
loop, it operates much like a traditional analog PWM
controller. See Figure 19 for a simplified block dia-
gram of the ZL2005P control loop, which differs from
an analog control loop by the constants in the PWM
and compensation blocks. As in the analog controller
case, the compensation block compares the output
voltage to the desired voltage reference and compen-
sation zeros are added to keep the loop stable. The
resulting integrated error signal is used to drive the
PWM logic, converting the error signal into a duty
cycle value to drive the external MOSFETs.
5.11 Non-Linear Response Settings
The ZL2005P incorporates a non-linear response
(NLR) loop that decreases the response time and the
output voltage deviation in the event of a sudden out-
put load current step. The NLR loop incorporates a
secondary error signal processing path that bypasses
the primary error loop when the output begins to tran-
sition outside of the standard regulation limits. This
scheme results in a higher equivalent loop bandwidth
than is possible using a traditional linear loop.
When a load current step function imposed on the out-
put causes the output voltage to drop below the lower
regulation limit, the NLR circuitry will force a positive
correction signal that will turn on the upper MOSFET
and quickly force the output to increase. A negative
load step will cause the NLR circuitry to force a nega-
FN6849.3
December 16, 2011
28
ZL2005P
tive correction signal that will turn on the lower MOS-
FET and quickly force the output to decrease.
It is therefore advantageous to minimize this dead-
time to provide optimum circuit efficiency. In the first
order model of a buck converter, the duty cycle is
determined by the equation:
5.12 Efficiency Optimized Driver Dead-
time Control
D = VOUT/VIN -------------------- (29)
However, non-idealities exist that cause the real duty
cycle to extend beyond the ideal. Deadtime is one of
those non-idealities that can be manipulated to
improve efficiency. The ZL2005P has an internal algo-
rithm that constantly adjusts deadtime non-overlap to
minimize duty cycle, thus maximizing efficiency. This
circuit will null out deadtime differences due to com-
ponent variation, temperature and loading effects.
The ZL2005P utilizes a closed loop algorithm to opti-
mize the dead-time applied between the gate drive sig-
nals for the top and bottom FETs. In a synchronous
buck converter, the MOSFET drive circuitry must be
designed such that the top and bottom MOSFETs are
never in the conducting state at the same time. (Poten-
tially damaging currents flow in the circuit if both top
and bottom MOSFETs are simultaneously on for peri-
ods of time exceeding a few nanoseconds.) Con-
versely, long periods of time in which both MOSFETs
are off reduce overall circuit efficiency by allowing
current to flow in their parasitic body diodes.
This algorithm is independent of application circuit
parameters such as MOSFET type, gate driver delays,
rise and fall times and circuit layout. In addition, it
does not require drive or MOSFET voltage or current
waveform measurements.
FN6849.3
December 16, 2011
29
ZL2005P
6
Power Management Functional Description
end of the delay period. The device will remain in
shutdown until permitted to restart.
6.1 Input Undervoltage Lockout (UVLO)
Standard Mode
3. Initiate an immediate shutdown until the fault has
been cleared. The user can select a specific num-
ber of retry attempts.
The input undervoltage lockout (UVLO) prevents the
ZL2005P from operating when the input falls below a
preset threshold, indicating the input supply is out of its
specified range. The UVLO threshold (VUVLO) can be
set between 2.85 V and 16 V using the UVLO pin. The
simplest implementation is to connect the UVLO pin as
shown in Table 25. If the UVLO pin is left uncon-
nected, the UVLO threshold will default to 4.5 V.
The default response from a UVLO fault is an imme-
diate shutdown of the device. The device will continu-
ously check for the presence of the fault condition. If
the fault condition is no longer present, the ZL2005P
will be re-enabled.
Please refer to Application Note AN2013 for details
on how to configure the UVLO threshold or to select
specific UVLO fault response options via the I2C/
SMBus interface.
Table 25. UVLO Threshold Settings
Pin Setting
LOW
UVLO Threshold
3 V
OPEN
4.5 V
10.8 V
6.2 Output Overvoltage Protection
HIGH
The ZL2005P offers an internal output overvoltage
protection circuit that can be used to protect sensitive
load circuitry from being subjected to a voltage higher
than its prescribed limits. This feature is especially
useful in protecting expensive processors, FPGAs, and
ASICs from excessive voltages.
If the desired UVLO threshold is not one of the listed
choices, the user can configure a threshold between
2.85 V and 16 V by connecting a resistor between the
UVLO pin and GND by selecting the appropriate
resistor from Table 26.
Table 26. UVLO Resistor Values
A hardware comparator is used to compare the actual
output voltage (seen at the VSEN pin) to a threshold set
to 15% higher than the target output voltage by default.
If the voltage at the VSEN pin exceeds this upper
threshold level, the PG pin will de-assert. The device
can then respond in a number of ways as follows:
UVLO
2.85 V
3.14 V
3.44 V
3.79 V
4.18 V
4.59 V
5.06 V
5.57 V
6.13 V
6.75 V
R
UVLO
7.42 V
8.18 V
8.99 V
9.9 V
R
UVLO
UVLO
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
82.5 kΩ
90.9 kΩ
100 kΩ
10.9 V
12 V
1. Initiate an immediate shutdown until the fault has
been cleared. The user can select a specific num-
ber of retry attempts.
13.2 V
14.54 V
16 V
2. Turn off the high-side MOSFET and turn on the
low-side MOSFET. The low-side MOSFET
remains ON until the device attempts a restart.
The default response from an overvoltage fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault condi-
tion. If the fault condition is no longer present, the
ZL2005P will be re-enabled.
VUVLO can also be set to any value between 2.85 V
and 16 V via I2C/SMBus.
Once an input undervoltage fault condition occurs, the
device can respond in a number of ways as follows:
Please refer to Application Note AN2013 for details
on how to select specific overvoltage fault response
options via the I2C/SMBus interface.
1. Continue operating without interruption.
2. Continue operating for a given delay time, fol-
lowed by shutdown if the fault still persists at the
FN6849.3
December 16, 2011
30
ZL2005P
If the pre-bias voltage is higher than the target voltage
6.3 Output Pre-Bias Protection
exists after the pre-configured delay period has
expired, the target voltage is set to match the existing
pre-bias voltage and both drivers are enabled with a
PWM duty cycle that would ideally create the pre-bias
voltage. Once the pre-configured soft-start ramp
period has expired, the Power Good pin will be
asserted (assuming the pre-bias voltage is not higher
than the overvoltage limit). The PWM will then adjust
its duty cycle to match the original target voltage and
the output will ramp down to the pre-configured out-
put voltage.
An output pre-bias condition exists when an externally
applied voltage is present on a power supply’s output
before the power supply’s control IC is enabled. Cer-
tain applications require that the converter not be
allowed to sink current during start up if a pre-bias
condition exists at the output. The ZL2005P provides
pre-bias protection by sampling the output voltage
prior to initiating an output ramp.
If a pre-bias voltage lower than the target voltage
exists after the pre-configured delay period has
expired, the target voltage is set to match the existing
pre-bias voltage and both drivers are enabled. The out-
put voltage is then ramped to the final regulation value
at the ramp rate set by the SS (0,1) pins. The actual
time the output will take to ramp from the pre-bias
voltage to the target voltage will vary depending on
the pre-bias voltage but the total time elapsed from
when the delay period expires and when the output
reaches its target value will match the pre-configured
ramp time. See Figure 20.
If a pre-bias voltage higher than the overvoltage limit,
the device will not initiate a turn-on sequence and will
declare an overvoltage fault condition to exist. In this
case, the device will respond based on the output over-
voltage fault response method that has been selected.
See Section 6.2, “Output Overvoltage Protection,” for
response options due to an overvoltage condition.
6.4 Output Overcurrent Protection
The ZL2005P can protect the power supply from dam-
age if the output is shorted to ground or if an overload
condition is imposed on the output. Once the current
limit threshold has been selected (see Section 5.9,
“Current Limit Threshold Selection,” ), the user may
determine the desired course of action to be taken
when an overload condition exists.
I
VOUT
Target
voltage
Pre-bias
voltage
The following overcurrent protection response options
are available:
Time
SS
SS
Delay
Ramp
1. Initiate a shutdown and attempt to restart an infi-
nite number of times with a preset delay time.
VPREBIAS < VTARGET
2. Initiate a shutdown and attempt to restart the
power supply a preset number of times with a pre-
set delay between attempts.
VOUT
Pre-bias
voltage
Target
voltage
3. Continue operating throughout a specific delay
time, followed by shutdown.
4. Continue operating throughout the fault (this
could result in permanent damage to the power
supply).
Time
SS
Delay
SS
Ramp
PG
Delay
5. Initiate an immediate shutdown.
The default response from an overcurrent fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault condi-
tion. If the fault condition is no longer present, the
ZL2005P will be re-enabled.
VPREBIAS > VTARGET
Figure 20. Output Response to Pre-Bias
Voltages
FN6849.3
December 16, 2011
31
ZL2005P
Please refer to Application Note AN2015 for details
6.6 Voltage Tracking
on how to select specific overcurrent fault response
options via the I2C/SMBus interface.
Numerous high performance systems place stringent
demands on the order in which the power supply volt-
ages are turned on. This is particularly true when
powering FPGAs, ASICs, and other advanced proces-
sor devices that require multiple supply voltages to
power a single die. In most cases, the I/O operates at a
higher voltage than the Core and therefore the Core
supply voltage, must not exceed the I/O supply voltage
by some amount (typically 300 mV).
6.5 Thermal Protection
The ZL2005P includes an on-chip thermal sensor that
continuously measures the internal temperature of the
die and will shut down the device when the tempera-
ture exceeds the preset limit. The default temperature
limit is set to 125°C in the factory, but the user may set
the limit to a different value if desired. See Applica-
tion Note AN2013 for details. Note that setting a
higher thermal limit via the I2C/SMBus interface may
result in permanent damage to the device. Once the
device has been disabled due to an internal tempera-
ture fault, the user may select one of several fault
response options as follows:
Voltage tracking protects these sensitive ICs by limit-
ing the differential voltage between multiple power
supplies during the power-up and power down
sequence. The ZL2005P integrates a lossless tracking
scheme that allows its output to track a voltage that is
applied to the VTRK pin with no external components
required. The VTRK pin is an analog input that, when
tracking mode is enabled, configures the voltage
applied to the VTRK pin to act as a reference for the
device’s output regulation.
1. Initiate a shutdown and attempt to restart an infi-
nite number of times with a preset delay time.
2. Initiate a shutdown and attempt to restart the
power supply a preset number of times with a pre-
set delay between attempts.
The ZL2005P offers two modes of tracking:
1. Coincident. This mode configures the ZL2005P to
ramp its output voltage at the same rate as the volt-
age applied to the VTRK pin.
3. Continue operating throughout a specific delay
time, followed by shutdown.
4. Continue operating throughout the fault (this
could result in permanent damage to the power
supply).
2. Ratiometric. This mode configures the ZL2005P
to ramp its output voltage at a rate that is a per-
centage of the voltage applied to the VTRK pin.
The default setting is 50%, but an external resistor
string may be used to configure a different track-
ing ratio.
5. Initiate an immediate shutdown.
If the user has configured the device to restart, the
device will wait the preset delay period (if configured
to do so) and will then check the temperature. If the
temperature has dropped below a value that is approx-
imately 15°C lower than the selected temperature limit
(the over-temperature warning threshold), the device
will attempt to re-start. If the temperature is still
above the over-temperature warning threshold, the
device will wait the preset delay period and retry
again.
Figure 21 illustrates the typical connection and the two
tracking modes.
The Tracking feature is not supported for ZL2005P
devices in a current sharing group.
The default response from a temperature fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault condi-
tion. If the fault condition is no longer present, the
ZL2005P will be re-enabled.
Please refer to Application Note AN2013 for details
on how to select specific temperature fault response
options via the I2C/SMBus interface.
FN6849.3
December 16, 2011
32
ZL2005P
6.7 Voltage Margining
VIN
Q1
GH
SW
GL
The ZL2005P offers a simple means to vary its output
higher or lower than its nominal voltage setting in
order to determine whether the load device is capable
of operating over its specified supply voltage range.
The MGN pin is a TTL-compatible input that is con-
tinuously monitored and can be driven directly by a
processor I/O pin or other logic-level output.
ZL
VOUT
L1
C1
Q2
VTRK
VOUT
VTRK
The ZL2005P output will be forced higher than its
nominal setpoint when the MGN pin is driven HIGH,
and the output will be forced lower than its nominal
setpoint when the MGN pin is driven LOW. When the
MGN pin is left floating (high impedance), the
ZL2005P output voltage will be set to its nominal volt-
age setpoint determined by the V0 and V1 pins and/or
the I2C/SMBus settings that configure the nominal
output voltage. Default margin limits of VNOM ±5%
are pre-loaded in the factory, but the margin limits can
be modified through the I2C/SMBus interface to as
high as VNOM + 10% or as low as 0V, where VNOM is
the nominal output voltage setpoint determined by the
V0 and V1 pins.
VOUT
Time
Coincident
VOUT
VTRK
VOUT
Time
Ratiometric
The margin limits and the MGN command can both be
set individually through the I2C/SMBus interface.
Additionally, the transition rate between the nominal
output voltage and either margin limit can be config-
ured through the I2C/SMBus interface. Please refer to
Application Note AN2013 for detailed instructions on
modifying the margining configurations.
Figure 21. Tracking Modes
The master ZL2005P device in a tracking group is
defined as the device that has the highest target output
voltage within the group. This master device will con-
trol the ramp rate of all tracking devices and is not
configured for tracking mode. A delay of at least 10
ms must be configured into the master device, and the
user may also configure a specific ramp rate using
PMBus.
2
6.8 I C/SMBus Communications
The ZL2005P provides an I2C/SMBus digital interface
that enables the user to configure all aspects of the
device operation as well as monitor the input and out-
put parameters. The ZL2005P can be used with any
standard 2-wire I2C host device. In addition, the
device is compatible with SMBus version 2.0 and
includes an SALRT line to help mitigate bandwidth
limitations related to continuous fault monitoring. The
ZL2005P accepts most standard PMBus commands.
Any device that is configured for tracking mode will
ignore its soft-start delay and ramp time settings and
its output will take on the turn-on/turn-off characteris-
tics of the reference voltage present at the VTRK pin.
The tracking mode for all other devices can be set by
PMBus. All of the ENABLE pins in the tracking group
must be connected together and driven by a single
logic source.
Please refer to Application Note AN2013 for details
on how to configure tracking via the I2C/SMBus inter-
face.
FN6849.3
December 16, 2011
33
ZL2005P
2
Using this method, the user can theoretically configure
up to 625 unique SMBus addresses; however, the
SMBus is inherently limited to 128 devices so
attempting to configure an address higher than 128
will cause the device address to repeat (i.e, attempting
to configure a device address of 129 would result in a
device address of 1). Therefore, the user should use
index values 0-4 on the SA1 pin and the full range of
index values on the SA0 pin, which will provide 125
device address combinations.
6.9 I C/SMBus Device Address Selection
When communicating with multiple ZL2005Ps using
the I2C/SMBus serial interface, each device must have
its own unique address so the host can distinguish
between the devices. The device address can be set
according to the pin-strap options listed in Table 27 to
provide up to eight unique device addresses. Address
values are right-justified.
Table 27. Serial Bus Device Address Selection
SA1
Table 29. SMBus Address Index Values
SA0 or
SA1
Index
SA0 or
SA1 Index
R
R
SA
SA
LOW
OPEN
HIGH
LOW
OPEN
HIGH
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0
1
10 kΩ
11 kΩ
13
14
15
16
17
18
19
20
21
22
23
24
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
SA0
Reserved
2
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
If additional device addresses are required, a resistor
can be connected to the SA0 pin according to Table 28
to provide up to 25 unique device addresses. In this
case the SA1 pin should be tied to SGND with a zero
ohm resistor.
3
4
5
6
7
Table 28. SMBus Address Values
8
SMBus
Address
SMBus
Address
R
R
SA0
SA0
9
82.5 kΩ
90.9 kΩ
100 kΩ
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
10 kΩ
11 kΩ
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
34.8 kΩ
38.3kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
75 kΩ
10
11
12
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
6.10 Phase Spreading
When multiple point of load converters share a com-
mon DC input supply, it is desirable to adjust the clock
phase offset of each device such that not all devices
start to switch simultaneously. Setting each converter
to start its switching cycle at a different point in time
can dramatically reduce input capacitance require-
ments and efficiency losses. Since the peak current
drawn from the input supply is effectively spread out
over a period of time, the peak current drawn at any
given moment is reduced and the power losses propor-
tional to the IRMS2 are reduced dramatically.
82.5 kΩ
90.9 kΩ
100 kΩ
If more than 25 unique device addresses are required
or if other SMBus address values are desired, both the
SA0 and SA1 pins can be configured with a resistor to
SGND according to the equation (30) and Table 29.
In order to enable phase spreading, all converters must
be synchronized to the same switching clock. The
CFG pin is used to set the configuration of the SYNC
pin for each device as described in Section 5.7,
“Switching Frequency and PLL,” .
SMBus addr = 25x(SA1 index)+(SA0 index) (30)
FN6849.3
December 16, 2011
34
ZL2005P
Selecting the phase offset for the device is accom-
plished by selecting a device address according to the
following equation:
Autonomous sequencing mode configures sequencing
using status information broadcast by ZL2005P onto
the I2C/SMBus pins SCL and SDA. No I2C or SMBus
host device is involved in this method, but the SCL
and SDA pins must be interconnected between all
devices that the user wishes to sequence using this
method. Note: Pull-up resistors on SCL and SDA are
required and should be selected using the criteria in
the SMBus 2.0 specification.
Phase offset = device address x 45°
For example:
A device address of 0x00 or 0x20 would configure no
phase offset
The sequence order is determined using each device’s
A device address of 0x01 or 0x21 would config-
ure 45° of phase offset
I2C/SMBus device address.
Using autonomous
sequencing mode (configured using the CFG pin), the
devices must exhibit sequential device addresses with
no missing addresses in the chain. This mode will also
constrain each device to have a phase offset according
to its device address as described in Section 6.10,
“Phase Spreading,” on page 34.
A device address of 0x02 or 0x22 would config-
ure 90° of phase offset.
The phase offset of each device may also be set to any
value between 0° and 337.5° in 22.5° increments via
the I2C/SMBus interface. Please refer to Application
Note AN2013 for details.
The group will turn on in order starting with the device
with the lowest address and will continue to turn on
each device in the address chain until all devices con-
nected have been turned on. When turning off, the
device with the highest address will turn off first fol-
lowed in reverse order by the other devices in the
group.
6.11 Output Sequencing
A group of ZL2005P devices may be configured to
power up in a predetermined sequence. This feature is
especially useful when powering advanced processors,
FPGAs, and ASICs that require one supply to reach its
operating voltage prior to another supply reaching its
operating voltage. Multi-device sequencing can be
achieved by configuring each device through the I2C/
SMBus interface or by using Zilker Labs’ proprietary
Autonomous SequencingTM mode.
Sequencing is configured by connecting a resistor
from the CFG pin to ground as described in Table 30.
The CFG pin is used to set the configuration of the
SYNC pin as well as to determine the sequencing
method and order. Please refer to Switching Frequency
and PLL for more details on the operating parameters
of the SYNC pin.
FN6849.3
December 16, 2011
35
ZL2005P
.
Table 30. CFG Pin Configurations for Sequencing
RCFG
Sequencing Configuration
SYNC Pin Config
10 kΩ
Input
11 kΩ
Auto detect
Output
Sequencing is disabled
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
Auto detect
Input
The ZL2005P is configured as the first device in a nested
sequencing group. Turn-on order is based on the device SMBus
address.
Auto detect
Output
Auto detect
Input
Auto detect
Output
The ZL2005P is configured as a last device in a nested sequencing
group. Turn-on order is based on the device SMBus address.
Auto detect
Input
The ZL2005P is configured as the middle device in a nested
sequencing group. Turn-on order is based on the device SMBus
address.
Auto detect
Output
Auto detect
Input
Sequencing is disabled
2
Multiple device sequencing may also be achieved by
issuing PMBus commands to assign the preceding
device in the sequencing chain as well as the device
that will follow in the sequencing chain. This method
places fewer restrictions on device address (no need of
sequential address) and also allows the user to assign
any phase offset to any device irrespective of its
device address.
6.12 Monitoring via I C/SMBus
A system controller can monitor a wide variety of dif-
ferent ZL2005P system parameters through the I2C/
SMBus interface. The controller can monitor for fault
conditions by monitoring the SALRT pin, which will
be asserted when any number of pre-configured fault
or warning conditions occur. The system controller
can also continuously monitor for any number of
power conversion parameters including but not limited
to the following:
Event-based sequencing and fault spreading are broad-
cast in address groups of up to sixteen ZL2005P
devices. An address group consists of all devices
whose addresses differ in only the four least signifi-
cant bits of the address. For example, addresses 20, 25
and 2F are all within the same group. Addresses 1F, 20
and 35 are all in different groups. Devices in the same
address group can broadcast power on and power off
sequencing and fault spreading events with each other.
Devices in different groups cannot.
1. Input voltage
2. Output voltage
3. Output current
4. Internal junction temperature
5. Temperature of an external device
6. Switching frequency
7. Duty cycle
The Enable pins of all devices in a sequencing group
must be tied together and driven high to initiate a
sequenced turn-on of the group. Enable must be driven
low to initiate a sequenced turnoff of the group.
Please refer to Application Note AN2013 for details
on how to monitor specific parameters via the I2C/
SMBus interface.
Please refer to Application Note AN2013 for details
on sequencing via the I2C/SMBus interface.
When using the ZL2005P with other controllers on the
same bus, these controllers need to be compliant with
FN6849.3
December 16, 2011
36
ZL2005P
multi master specifications. Please refer to http://
www.i2c-bus.org/multimaster/ for more information.
6.14 Non-volatile Memory and Device
Security Features
6.13 Temperature Monitoring Using the
XTEMP Pin
The ZL2005P has internal non-volatile memory where
user configurations are stored. Integrated security
measures ensure that the user can only restore the
device to a level that has been made available to them.
During the initialization process, the ZL2005P checks
for stored values contained in its internal memory. The
ZL2005P offers one internal memory storage unit (two
for the ZL2005) called Default Store.
The ZL2005P supports measurement of an external
device temperature using either a thermal diode inte-
grated in a processor, FPGA or ASIC, or using a dis-
crete diode-connected NPN transistor such as a
2N3904 or equivalent. Figure 22 illustrates the typical
connections required.
A system designer or a power supply module manu-
facturer may want to protect the device by preventing
the user from being able to modify certain values. In
this case, he would use the Default Store and would
allow the user to restore the device to its default set-
ting but would restrict the user from restoring the
device to the factory setting. Please refer to Applica-
tion Note AN2013 for details on how to set specific
security measures via the I2C/SMBus interface.
XTEMP
100pF
2N3904
ZL2005P
SGND
Discrete NPN
µP
XTEMP
FPGA
DSP
100pF
ZL2005P
ASIC
SGND
Embedded Thermal Diode
Figure 22. External Temp Monitoring
FN6849.3
December 16, 2011
37
ZL2005P
7
Package Dimensions
L36.6x6C
36 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/10
4X 4.0
0.50
6.00
36X
A
6
B
PIN #1
INDEX AREA
28
36
6
27
PIN 1
INDEX AREA
1
4 .10 ± 0.10
9
19
(4X)
0.15
18
10
TOP VIEW
36X 0.60 ± 0.10
BOTTOM VIEW
36X 0.25 4
0.10 M C A B
SEE DETAIL "X"
C
0.10 C
MAX 1.00
0.08 C
( 5. 60 TYP )
( 36 X 0 . 50 )
SIDE VIEW
(
4. 10 )
(36X 0.25 )
5
0 . 2 REF
C
( 36X 0.80 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6849.3
December 16, 2011
38
ZL2005P
8
Ordering Information
PART NUMBER
(Notes 1, 2, 3, 4)
PART
MARKING
TEMP RANGE
(°C)
TAPE & REEL
QTY.
PACKAGE
(Pb-free)
PKG.
DWG. #
ZL2005PALRFT 2005P
-40 to +85
-40 to +85
100
36 Ld 6x6 QFN, 0.5mm pitch L36.6X6C
36 Ld 6x6 QFN, 0.5mm pitch L36.6X6C
ZL2005PALRFT1 2005P
1000
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus
anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ZL2005P. For more information on MSL please see tech brief TB363.
4. The “R” in the part number denotes firmware revision.
Related Documentation
The following application support documents and tools are available to help simplify your design.
Item
ZL2005PEVK4
AN2010
Description
Evaluation Kit: DC-DC Converter with Power Management
Application Note: ZL2005 and ZL2105 Thermal and Layout Guidelines
Application Note: ZL2005 Component Selection Guide
Application Note: PMBus Command Set
AN2011
AN2013
AN2015
Application Note: ZL2005 Current Protection and Measurement
Application Note: ZL2005 Digital Control Loop Compensation
Application Note: Loading Configuration Files in a Manufacturing Environment
Application Note: Autonomous Sequencing Technology
Application Note: Voltage Tracking with the ZL2005
AN2016
AN2028
AN2022
AN2023
Revision History
Revision Number
Description
Initial Release
Date
1.0
1.1
October 8, 2007
August 12, 2008
February 18, 2009
Updated Ordering Information
FN6849.0
Assigned file number FN6849 to datasheet as this will be the first
release with an Intersil file number. Replaced header and footer
with Intersil header and footer. Updated disclaimer information
to read "Intersil and it's subsidiaries including Zilker Labs, Inc."
No changes to datasheet content.
FN6849.0
Stamped datasheet “Not Recommended For New Designs
Recommended Replacement Part ZL2006”. No file rev, no
date change, no changes to datasheet content.
August 5, 2009
FN6849.3
December 16, 2011
39
ZL2005P
Revision Number
Description
Date
FN6849.1
1. Electrical Chracteristics, Table 1:
November 11, 2009
a. Added “ISENA” to “Analog input voltages” with value of -3 to
6.5 and removed it’s stand-alone row with value of -1.5 to +30.
b. Removed 120mA row for “MOSFET drive reference”
and”Logic reference”.
2. Electrical Specifications, Table 3:
a. Changed “Logic input bias current” to ““Logic input leakage
current” with condition of “Push-pull logic” with Min of -250nA
and Max of 250nA.
b. Added Note 5 of “Limits established by charcterization and
not production tested” and callouts to the following parameters:
“Soft start delay duration range”, “Soft start ramp duration
range”, “Logic input leakage current”, “Minimum SYNC pulse
width”, “High-side driver peak gate drive current (pull down)”,
“High-side driver pull-up resistance”, “High-side driver pull-
down resistance”, “Low-side driver peak gate drive current (pull-
up)”, “Low-side driver peak gate drive current (pull-down)”,
“Low-side driver pull-up resistance” , “Low-side driver pull-
down resistance”, “Switching timing - GH and GL rise and fall”,
“Power good delay range”, “VSEN undervoltage (and
overvolatge) threshold” with condition of “Configurable via I2C/
SMBus”, “VSEN undervoltage/overvoltage fault response
time” with condition of “Configurable via I2C/SMBus”, “Current
limit protection delay” with condition of “Configurable via I2C/
SMBus”, “Thermal protection threshold” with condition of
“Configurable via I2C/SMBus”.
3. Updated Ordering info to note R as the firmware revision
4. Updated Related documentation item numbers.
1. Updated Stamp on datasheet to read “Not Recommended
For New Designs Recommended Replacement Part
ZL6100”.
Page 5, Table 3, last row in the table "VTRK tracking threshold",
added a reference to Note 5.
November 12, 2009
August 12, 2010
FN6849.2
FN6849.3
December 16, 2011
40
ZL2005P
Revision Number
Description
Date
FN6849.3
Updated Caution statement in Table 1 on page 3 per legal's new
verbiage.
December 14, 2011
Updated ΘJA and ΘJC notes in Table 2 on page 4 to packaging's
standard notes.
Added standard over temp note to Min Max column of Table 3
on page 4 “Compliance to datasheet limits is assured by one or
more methods: production test, characterization and/or design."
Added standard "Boldface limits apply.." verbiage to common
conditions of Table 3. Bolded applicable specs.
Corrected Figure 3 on page 9 to new POLA resistor value.
Corrected wording of “POLA/DOSA Trim Method” on page 15
to page 16.
Changed Table 8 on page 16 and Table 9 on page 16 to reflect
new POLA/DOSA values.
Replaced Zilker package outline drawing on page 38 with Intersil
equivalent (L36.6x6C). Changes as follows:
-Lead length in bottom view changed from 0.6±0.05 to 0.6±0.1
-Added land pattern
-Removed the following notes:
6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm.
7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL
DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LASER MARKED.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE
EXPOSED HEAT SINK SLUG AS WELL AS THE
TERMINALS.
-Changed the JEDEC outline from MO-220 to MO-220VJJD.
Updated “Ordering Information” on page 39 from spider chart to
Intersil standard table, which includes lead finish note, MSL
note, tape and reel note and Intersil package outline drawing
number.
Updated sales disclaimer on last page to Intersil's verbiage
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6849.3
December 16, 2011
41
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