ZSSC3230BC3R_技术文档

Capacitive Sensor Signal

Conditioner IC

ZSSC3230

Datasheet

Description

Features

The ZSSC3230 is a CMOS integrated circuit for accurate capaci-

tance-to-digital conversion and sensor-specific correction of

capacitive sensor signals. Digital compensation of sensor offset,

sensitivity, and temperature drift is accomplished via an internal

digital signal processor running a correction algorithm with

calibration coefficients stored in a nonvolatile, multiple-time

programmable (NVM) memory. Programming the ZSSC3230 is

simple via the serial interface. The interface is used for the PC-

controlled calibration procedure, which programs the set of

calibration coefficients in memory. The ZSSC3230 is configurable

for capacitive sensors with capacitances up to 30pF and will

provide an output resolution that is scalable up to 18-bit. It is

compatible with single-ended capacitive sensors. Measured and

corrected sensor values can be output as I2C (≤ 3.4MHz).

.

Low current consumption: 1.3µA at 1 sample per second

Maximum target input capacitance: 30pF

Programmable capacitance span and offset

High sampling rate with 2ms at 14-bit resolution

ADC resolution: Adjustable in speed and resolution, 18-bit

maximum

.

Internal auto-compensated temperature sensor; not stress

sensitive

Programmable measurement sequence, single-shot and

automatic cycling of measurements with end-of-sequence

interrupt output

.

Oversampling modes using internal averaging

Interrupt features

The ZSSC3230 provides accelerated signal processing, increased

resolution, and improved noise immunity in order to support high-

speed control, safety, and real-time sensing applications with the

highest requirements for energy efficiency.

Integrated NVM for configuration and free space for

customer use

.

Small die size

External reset pin (low active)

No external trimming components required

Highly integrated CMOS design

Basic Application Diagram

VDD

VSS

Physical Characteristics

VDD

C0

.

Supply voltage V_DD: 1.68V to 3.6V

VSS

CC

.

Operating temperature: -40°C to 125°C depending on the part

code

C1

EOC

.

I2C Interface compatible, supporting

 Standard Mode(100kHz)

SDA

SCL

 Fast Mode (400kHz)

 High-Speed Mode (3.4MHz)

.

Capacitive input range 0 to 30pF

Capacitive offset compensation 0 to 15pF

Available in 4  4 mm²24-PQFN package or as die

ZSSC3230

SDA

SCL

Typical Applications

.

Humidity sensors

Pressure sensors, level sensors

Smart, digital, capacitive sensors for energy-efficient solutions

Consumer / white goods (e.g., HVAC)

Medical applications

1

October 15, 2019

ZSSC3230 Datasheet

Block Diagram

Vreg int

VDD

V_TP

Temperature

Reference

Sensor

AGND / CM

Generator

Bias Current

Generator

Voltage Regulator

V_TN

Power Ctr.

VSS

ZSSC3230

EOC

PDM

C0

DSP Core

(Calculations,

Communication)

A

D

SCL

18 Bit

CC

Pre-Amplifier

SDA

Cmeasure

CC

RESQ

MTP

ROM

I2C

Clock

Generator

System

Control Unit

Power-ON

Reset

Ring

Oscillator

2

October 15, 2019

ZSSC3230 Datasheet

Typical Application Examples

Figure 1. Isolated C Mode

Figure 2. Grounded C Mode

V_supply

VDD

ZSSC3230

GND

VSS

SDA

VSS

CC

SDA

SCL

CC

SCL

EOC

C0

EOC

C0

RESQ

CC

3

October 15, 2019

ZSSC3230 Datasheet

Contents

1. Pin Assignments...........................................................................................................................................................................................6

2. Pin Descriptions............................................................................................................................................................................................7

3. Absolute Maximum Ratings..........................................................................................................................................................................8

4. Recommended Operating Conditions ..........................................................................................................................................................8

5. Electrical Characteristics ..............................................................................................................................................................................9

6. Device Description......................................................................................................................................................................................11

6.1 Signal Flow........................................................................................................................................................................................12

6.2 Capacitive Sensor Front-End ............................................................................................................................................................13

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

Differential Mode ................................................................................................................................................................14

Single-Ended Mode............................................................................................................................................................14

Sensor Leakage Compensation .........................................................................................................................................14

Shield Driver Mode.............................................................................................................................................................15

Subtraction Mode ...............................................................................................................................................................16

6.3 Temperature Sensor..........................................................................................................................................................................16

6.4 Analog to Digital Converter (ADC).....................................................................................................................................................16

6.5 Calibration Math ................................................................................................................................................................................17

6.5.1

6.5.2

6.5.3

1/C Pre-compensation........................................................................................................................................................17

Sensor Signal Compensation Math....................................................................................................................................18

Temperature Signal Compensation....................................................................................................................................20

6.6 Output Stages....................................................................................................................................................................................20

6.6.1

6.6.2

6.6.3

PDM Output Stage .............................................................................................................................................................20

I2C Output ..........................................................................................................................................................................21

EOC and Output Interrupt Signaling...................................................................................................................................24

6.7 Measurement and Output Options ....................................................................................................................................................26

6.7.1

6.7.2

6.7.3

6.7.4

Single Measurements: Digital Raw and SSC Results ........................................................................................................26

Digital Commands ..............................................................................................................................................................27

Nonvolatile Memory (NVM) ................................................................................................................................................28

Memory Contents ...............................................................................................................................................................29

7. Package Outline Drawings .........................................................................................................................................................................34

8. Marking Diagram ........................................................................................................................................................................................34

9. Ordering Information...................................................................................................................................................................................34

10. Glossary .....................................................................................................................................................................................................35

11. Revision History..........................................................................................................................................................................................36

4

October 15, 2019

ZSSC3230 Datasheet

List of Figures

Figure 1. Isolated C Mode ..................................................................................................................................................................................3

Figure 2. Grounded C Mode...............................................................................................................................................................................3

Figure 3. Pin Assignments for 4  4 mm 24-PQFN Package – Top View ..........................................................................................................6

Figure 4. Pin (Pad) Assignments for Bare-Die....................................................................................................................................................6

Figure 5. Main Operating Modes of the ZSSC3230..........................................................................................................................................11

Figure 6. Capacitive Input Signal Conditions....................................................................................................................................................13

Figure 7. Capacitive Input in Differential Mode.................................................................................................................................................14

Figure 8. Capacitive Input in Single-Ended Mode.............................................................................................................................................15

Figure 9. Shield Driver Mode............................................................................................................................................................................15

Figure 10. Subtraction Mode ..............................................................................................................................................................................16

Figure 11. Principal Compensation Flow............................................................................................................................................................17

Figure 12. System Transfer Function for 1/C......................................................................................................................................................18

Figure 13. PDM Output Configuration ................................................................................................................................................................21

Figure 14. I2C Command Request.....................................................................................................................................................................22

Figure 15. I2C Read Data...................................................................................................................................................................................23

Figure 16. I2C Read Status................................................................................................................................................................................23

Figure 17 EOC and Interrupt Thresholds...........................................................................................................................................................25

List of Tables

Table 1. Pin Descriptions...................................................................................................................................................................................7

Table 2. Absolute Maximum Ratings.................................................................................................................................................................8

Table 3. Recommended Operating Conditions .................................................................................................................................................8

Table 4. Electrical Characteristics .....................................................................................................................................................................9

Table 5. Conversion Time for Full Temperature Compensated Measurement................................................................................................12

Table 6. ADC Resolution and Conversion Times for a Single Analog-to-Digital Conversion with Auto-Zero..................................................16

Table 7. Data Format of Calibration Coefficients in Memory...........................................................................................................................20

Table 8. Analog Output Performance by External Capacitor Value.................................................................................................................21

Table 9. General Status Byte ..........................................................................................................................................................................21

Table 10. Mode Status ......................................................................................................................................................................................22

Table 11. I2C Interface Parameters ..................................................................................................................................................................23

Table 12. Data Format of Interrupt Thresholds (TRSH1 and TRSH2)...............................................................................................................24

Table 13. Data Format of Raw ADC Readings..................................................................................................................................................26

Table 14. Data Format of Corrected SSC Results.............................................................................................................................................26

Table 15. Command List ...................................................................................................................................................................................27

Table 16. Memory (NVM) Content Assignments...............................................................................................................................................29

5

October 15, 2019

ZSSC3230 Datasheet

1. Pin Assignments

The ZSSC3230 is available as 8-inch wafer* and QFN24 package. Details about the package are provided in section 7.

Figure 3. Pin Assignments for 4  4 mm 24-PQFN Package – Top View

24

23

22

21

20

19

1

2

3

4

5

6

18

17

16

15

14

13

n.c.

C0

n.c.

CC

PDM

EOC

IDT-Test

n.c.

ZSSC3230

RESQ

IDT-Test

n.c.

7

8

9

10

11

12

Figure 4. Pin (Pad) Assignments for Bare-Die

IC Core

Seal Ring

VSS

VDD

CC

C0

PDM

EOC

CC‘

RESQ

IDT-Test

SCL

IDT-Test

SDA

* Detailed information about wafer-shipments, etc., is available on request. See last page for contact information.

6

October 15, 2019

ZSSC3230 Datasheet

2. Pin Descriptions

Table 1.

Pin Descriptions

Pin Number

Name

n.c.

Type

Description

No connection. Leave pin floating.

1

–

2

C0

Analog Input

Capacitor input signal.

3

CC’

Analog Input

Capacitor input signal, duplicate of CC (pin 17).

RESET, low active; internal pull-up.

4

RESQ

IDT-Test

n.c.

Digital Input

5

–

Connect to VSS; otherwise no connection; leave pin floating.

No connection. Leave pin floating.

Clock input for I2C interface.

6

–

7

n.c.

–

8

SCL

n.c.

Digital Input

9

–

No connection. Leave pin floating.

Bi-directional data I/O for I2C. Pull-up to VDD.

No connection. Leave pin floating.

Connect to VSS; otherwise no connection; leave pin floating.

End-of-conversion and output interrupt signal.

Digital output for pulse-density modulated output.

Capacitor input signal, duplicate to CC’ (pin 3).

No connection. Leave pin floating.

Power supply ground.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

n.c.

–

SDA

n.c.

Digital Input/Output

–

n.c.

–

IDT-Test

EOC

PDM

CC

–

Digital Output

Analog Input

n.c.

–

n.c.

–

VSS

n.c.

Ground

–

No connection. Leave pin floating.

Power supply.

n.c.

–

Supply

–

VDD

n.c.

No connection. Leave pin floating.

7

October 15, 2019

ZSSC3230 Datasheet

3. Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.

Functional operation of the ZSSC3230 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect

device reliability.

Table 2.

Symbol

Absolute Maximum Ratings

Parameter

Junction temperature

Storage temperature

Conditions

Minimum

Maximum

135

Units

°C

V

T_J

–

-45

–

T_S

150

ESD – Human Body Model

ESD – Charged Device Model

Latch-up

2000

750

–

V

-100

-0.3

+100

3.63

mA

V

VDD_max

V_{IF_max}

Voltage supply range

Voltage at digital interface pins

Referenced to VSS

I2C pins: SDA, SCL

VDD +0.5V

or 3.63V

max.

V

4. Recommended Operating Conditions

Table 3.

Recommended Operating Conditions

Symbol

V_DD

Parameter

Power supply voltage

Minimum

Typical

Maximum

Units

V

1.68

-40

0

–

3.6

125

–

T_A

Ambient temperature

°C

C_VDD

External (parasitic) capacitance between VDD and VSS

Recommended V_DDrise slew rate for power-on-reset (POR)^[a]

10

–

nF

SR_{VDD_POR}

10

–

V/ms

[a] Per design, there is no (theoretical) minimum V_DDslew-rate to trigger a clean POR; however, a reasonable slew rate is recommended.

8

October 15, 2019

ZSSC3230 Datasheet

5. Electrical Characteristics

All parameter values are valid only under specified operating conditions. All voltages are referenced to V_SS.

Table 4.

Electrical Characteristics

Symbol

IC Supply

I_IC

Parameter

Conditions

Minimum

Typical

Maximum

Units

Current consumption,

active ZSSC3230

Excluding connected sensor elements;

noise_mode = 0; see Table 16

–

750

1100

1

µA

I_IDLE

Idle current consumption,

ZSSC3230 in Sleep

State

0.07

I_AVE

Average current draw

Mean current consumption for one complete

SSC-measurement cycle per second at 14-bit

digital-only output, noise_mode = 0

–

1.7

40

3.3

µA

dB

PSRR

Static power supply

VDD = 3V

–

rejection ratio (PSRR)

CDC Characteristics

C_RANGE

C_OFFSET

C_SIGNAL

f_clk

Sensor capacitance

range

0

–

30

15

–

pF

Absolute sensor

capacitance offset

Effective sensor

capacitance

-15

–

pF

Analog base clock

frequency

750

14.4

kHz

Bit

ENOB

Effective number of bits,

r_ADC= 18-bit, no oversampling

–

±3_Noise

Analog-to-Digital Converter (ADC, A2D)

r_ADC

Resolution

12

94

–

18

Bit

Hz

f_S,RAW

Conversion rate;

conversions per second

Single external sensor A2D conversion

(including auto-zero measurement AZ);

resolution and mode dependent

1250

f_S,CORR

SSC-conversion rate for

full SSC cycle;

conversions per second

Full SSC-measurements per second:

temperature (14-bit) + capacitance (12 to18 bit)

86

–

555

Hz

f_S,TEMP

SSC-conversion rate for

temperature

14-bit resolution

–

960

measurement

ADCnoise

ENOB

r_ADC= 16-bit

–

ADC-noise sigma

1

LSB

Bit

Effective number of bits,

r_ADC= 18-bit, no oversampling

16

±3_Noise

9

October 15, 2019

ZSSC3230 Datasheet

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

Power-Up Conditions

t_stup1

t_stup2

t_wup1

t_wup2

Start-up time

communication

Delay between VDD ramp up and start of first

command (proven by design)

–

1

ms

Start-up time analog

operation

Delay between VDD ramp up and analog

operation (proven by design)

2.5

0.5

2

Wake-up time

communication

Delay between sleep state and start of first

command (proven by design)

Wake-up time analog

operation

Delay between sleep state and analog

operation (proven by design)

Sensor Signal Conditioning Performance

f_SSCout

Output (update) rate

SSC-corrected digital output rate;

capacitance sensor measurement: 16-bit;

temperature measurement: 14-bit;

noise_mode = 0; see Table 16

–

290

0.1

–

Hz

Err_A,IC

ZSSC3230 accuracy

error using internal SSC

calculation math

Accuracy error for sensor being ideally linear

(for temperature and measurand)

%FSO

Oscillator

f_CLK

Internal oscillator

frequency

–

3.0

55

–

MHz

Temperature Sensor(s)

r_TempInternal temperature

LSB/K

sensor resolution

Interface and Memory

f_C,I2CI2C clock frequency

t_PROG

–

20

3.4

–

MHz

ms

NVM program time

NVM endurance

Data retention

Programming time per 16-bit word

Number of reprogramming cycles

n_NVM

1000

10

10000

–

Numeric

Years

t_RET,NVM

–

10

October 15, 2019

ZSSC3230 Datasheet

6. Device Description

The ZSSC3230 can be set up for one of three main operating modes:

.

Sleep Mode – Sleep Mode based operation is recommended for smart sensors for the lowest average power consumption. The

ZSSC3230 automatically enters an idle state after command execution for minimum current consumption; however, the interface is still

listening and accepts commands. After receiving of a valid command, the ZSSC3230 wakes up, executes the command, and provides the

results at the digital interface and then returns to Sleep State.

Command Mode – Command Mode is most appropriate for evaluation, test, and calibration purposes. In this mode, all commands are

available, both digital and analog outputs are supported, and no restrictions for any functionality need to be considered. Command Mode

can be used for applications requiring re-occurring (or even continuous) digital interaction and minimum latency. Applications in

Command Mode are only active on command request. See Table 15 for definitions of the commands.

Cyclic Measurement Mode – Cyclic operation means autonomous, cyclically repeated sensor measurements and related digital and

output updates.

After power-on, the voltage regulators are switched on, and the ZSSC3230’s low-voltage section (LV) is active while the related interface

configuration information is read from memory. Then the LV section is switched off, the ZSSC3230 goes into Sleep Mode, and the interface is

ready to receive commands. The interface is always powered by V_DD, so it is referred to as the high voltage section (HV).

Figure 5 shows the ZSSC3230 main operation modes: Normal Mode (which uses two operation principles: “Sleep” and “Cyclic”) and Command

Mode. The Normal Mode automatically returns to Sleep Mode after executing the requested measurements, or periodically wakes up and

conducts another measurement according to the setting for the sleep duration configured by the CYC_period (bits[14:12] in memory register

02_HEX; see Table 16). In Command Mode, the ZSSC3230 remains active if a dedicated command (e.g., Start_NOM) is sent, which is helpful

during calibration. Command Mode can only be entered if a Start_CM (command A9_HEX; see Table 15) is the first command received after a

POR.

Figure 5. Main Operating Modes of the ZSSC3230

Power-On (V_DD)

Reset

Initialization

(Load from configurations from NVM,

interfaces, default_mode, etc.)

PDM_enable

Yes

No

Command Mode

(Activity on command; digital output

supported; fastest response; all

commands available)

Sleep Mode

(Wake-up on command; automatic sleep

after command execution; no PDM

output)

Cyclic Measurement Mode

(Autonomous measurements; digital

and PDM output supported; limited

commands)

START_CM

START_CYC

START_SLEEP

Stop PDM

START_SLEEP

START_CYC

11

October 15, 2019

ZSSC3230 Datasheet

6.1 Signal Flow

See Figure 1 and Figure 2 for the ZSSC3230 block diagram sensors input options. The CC pin is duplicated as CC’ depending on the preferred

physical sensor connection. Selecting CC or CC’ can be done using the signal setup CC_pin_selection bits[1:0] in memory register 19_HEX(see

Table 16).

Two sensor connections are possible:

.

Differential Measurement Mode, which is an isolated C mode with C_MEASconnected between CC and C0 or CC’ and C0 so that both ends

of the capacitor are connected to the ZSSC3230.

.

Single-Ended Measurement Mode, which is a grounded C mode with C_MEASconnected between CC and VSS or CC’ and VSS/ground. In

this mode, C0 is switched to VSS. In this mode, only one capacitor input pin needs to be directly connected to the ZSSC3230.

The capacitance amplifier (CapAmp), which is also referred to as the charge-voltage converter (CVC), measures an external capacitance value,

C_MEASand provides a differential output voltage proportional to the capacitance (change) to the subsequent ADC. Thereby C_MEASis connected

with both ends to the IC or with one pin to VSS.

The bias current for the stage (CapAmp) can be programmed (using the setup signal noise_mode bit 8 in the Sensor_config memory register

12_HEX; see Table 16) to allow a trade-off between current consumption and achievable signal to noise ratio (SNR).

The system control unit controls the analog circuitry to perform the measurement types for the external capacitive sensor and internal

temperature. The multiplexer selects the signal input to the amplifier, which can be the voltage-converted signals of the external capacitive

sensor or the internal temperature reference sensor signal. A full measurement request will trigger an automatic sequence of all measurement

types and all input signals.

The gain amplifier (PGA) adjusts the respective signal from the capacitance-to-voltage converter or internal temperature sensor. The ZSSC3230

employs a programmable analog-to-digital converter (ADC) optimized for conversion speed and noise suppression. The programmable

resolution from 12 to 18 bits provides flexibility for adapting the conversion characteristics.

The math core accomplishes the auto-zero, span, and 1^stand 2^ndorder temperature compensation of the measured external sensor signal. The

correction coefficients are stored in the nonvolatile memory. The ZSSC3230 supports I2C interface communication for controlling the

ZSSC3230, configuration, and measurement result output. An adequate PDM signal for the compensated sensor signal can be provided in

Cyclic Measurement Mode at the PDM pin.

Table 5 lists the conversion time of a full corrected and compensated measurement. The temperature measurement always has a 14-bit

resolution. The conversion time for the sensor channels includes a full ADC conversion plus auto-zero measurement and the corresponding

CVC conversion time for this channel and the respective temperature measurement and math calculation. The 2 noise modes (bit[8] in memory

register 12_HEX) are listed separately.

Table 5.

Conversion Time for Full Temperature Compensated Measurement

adc_bits[7:6]

Conversion Time for Full Temperature Compensated Measurement, Typical [µs]

ADC Resolution [Bits]

bit[7]

bit[6]

noise_mode = 0

1770

noise_mode = 1

2550

0

1

0

1

0

1

12

14

16

18

2310

3850

3390

6440

5520

11630

12

October 15, 2019

ZSSC3230 Datasheet

6.2 Capacitive Sensor Front-End

The capacitance amplifier input range (C_RANGE) must be adjusted to the external capacitance conditions for signal (C_SIGNAL) and offset shift

(C_OFFSET) as given in Equation 1. See Figure 6 for an illustration of the terms.

C_RANGE= C_OFFSET+ C_SIGNAL

Equation 1

C_OFFSEToperates as a zero-shift capacitance to cancel a given offset by the sensor. The offset-shift capacitance must not exceed the selected

input capacitance range C_RANGE. For C_OFFSET,the respective configuration must be set up in the EEPROM for the shift_cap parameter (bits[5:0]

in memory register 12_HEX; see Table 16).

The correlating setup for C_SIGNALmust be done in the EEPROM for parameter cap_range (bits[13:9] in memory register 12_HEX). In Table 16, the

respective values are given. These values can be measured in the positive and negative direction, so the effective range of C_SIGNALwill be

doubled compared to the cap_range setting. The principle is shown in Figure 6.

Figure 6. Capacitive Input Signal Conditions

VDD

ZSSC3230

VSS

CC

Sensor Characteristic

SDA

SCL

+ Capacitance Range

C_SIGNAL

C_OFFSET

– Capacitance Range

C_SIGNALC_OFFSET

EOC

C_OFFSET

C0

RESQ

CC

13

October 15, 2019

ZSSC3230 Datasheet

6.2.1 Differential Mode

The most relevant measurement mode is the Differential Measurement Mode, with C_MEASconnected between CC and C0 or CC’ and C0 so that

both ends of the capacitor are connected to the ZSSC3230. For electrical connections, see Figure 7.

For the ZSSC3230 for the Differential Measurement Mode, the configuration must be done in the EEPROM for parameter sensecap_type

(bit[15] in memory register 12_HEX; see Table 16). When the sensecap_type is 0, the differential mode is selected, which is the default

configuration.

Figure 7. Capacitive Input in Differential Mode

CC Configuration

CC ꢀConfiguration

Vsup

VDD

Vsup

VDD

ZSSC3230

VSS

CC

VSS

SDA

SCL

CC

SCL

EOC

C0

RESQ

CC

6.2.2 Single-Ended Mode

Another measurement mode is the single ended measurement mode, with C_MEASconnected between CC and VSS or CC’ and VSS/ground. In

this mode C0 is switched to VSS. In this mode only 1 Pin needs to be directly connected to the IC.

Configuring the ZSSC3230 for Single-Ended Input Mode must be done in the EEPROM via the parameter sensecap_type (bit[15] in memory

register 12_HEX; see Table 16). Since the respective bit is defined as “0” in the default configuration for Differential Mode, the bit must be

programmed to “1.”

6.2.3 Sensor Leakage Compensation

Sensor leakage compensation is an additional option for Single-Ended Mode to enable the sensor element’s leakage current compensation.

The leakage current is caused by the sensor element’s parasitic resistance. Enabling this function via the sensor_leakage bit[14] in memory

register 12_HEXleads to loss of dynamic range and a decrease in the SNR. With losing 1-bit effective resolution on leakage compensation, the

respective capacitive input range for C_SIGNALwill be doubled compared to the description in section 6.2.

14

October 15, 2019

ZSSC3230 Datasheet

Figure 8. Capacitive Input in Single-Ended Mode

CC Configuration

CC ꢀConfiguration

VDD

Vsup

ZSSC3230

VSS

CC

VSS

SDA

SCL

CC

SCL

EOC

Resq

EOC

C0

Resq

CC

6.2.4 Shield Driver Mode

The Shield Driver Mode is a special sub-mode for Single-Ended Mode. In this mode, the C0 pin will be forced to the same level as the CC/CC’

pin. This pin can be used to drive a shield, so the shield parasitic capacitance does not have an effect on the measurement. The Shield Driver

Mode can be enabled by setting the EEPROM parameter En_shlddrv (bit[4] in memory register 19_HEX) to “1” (see Table 16).

Figure 9. Shield Driver Mode

CC Configuration

CC ꢀConfiguration

VDD

Vsup

ZSSC3230

VSS

CC

VSS

SDA

SCL

CC

SCL

EOC

C0

RESQ

CC

15

October 15, 2019

ZSSC3230 Datasheet

6.2.5 Subtraction Mode

The Subtraction Mode is a special sub-mode for Single-Ended Mode. It is activated by setting the En_sh2 bit to “1” (bit[3] in memory register

19_HEX; see Table 16). In this mode, C0 is charged to the opposite reference of the CC/CC’ node level. In conversion phase the charge of CC/CC’

and C0 are integrated. In this mode, the integrated capacitance corresponds to “Cx-Cy”; thus this mode can provide an additional range

extension.

Figure 10. Subtraction Mode

CC Configuration

CC ꢀConfiguration

Vsup

VDD

Vsup

VDD

ZSSC3230

VSS

CC

VSS

SDA

SCL

CC

SCL

Cx

EOC

C0

Cy

RESQ

CC

Cx

6.3 Temperature Sensor

The ZSSC3230 provides a PTAT-based internal temperature sensor measurement to allow compensation for temperature effects. The

temperature output signal is a differential voltage that is adapted by the amplifier (PGA) for the ADC input. For IC-internal temperature

measurements, the respective settings are defined and programmed in the NVM by IDT. The resolution setting for temperature measurements

is defined as 14-bit.

6.4 Analog to Digital Converter (ADC)

An analog-to-digital converter (ADC) is used to digitize the amplifier signal. To allow optimizing the trade-off between conversion time and

resolution, the resolution can be programmed from 12-bit to 18-bit by configuring the parameter adc_bits, (bits [7:6] in memory register 12_HEX

;

see Table 16). The ADC processes differential input signals provided by the internal amplifier for sensor measurement and temperature

measurement. The application default setting is 16-bit. The corresponding conversion times are listed in Table 6. The conversion time for the

sensor channels includes a full ADC conversion as well as the corresponding CVC conversion time for this channel. There are 2 noise modes

(selected with bit[8] in memory register 12_HEX). The listed conversion times are valid for raw measurements including auto-zero compensation.

Table 6. ADC Resolution and Conversion Times for a Single Analog-to-Digital Conversion with Auto-Zero

adc_bits[7:6]

bit[7] bit[6]

Conversion Time ADC (including CVC), typical [µs]

Conversion Time

Temperature, Typical [µs]

ADC Resolution [Bits]

noise_mode = 0

noise_mode = 1

1550

0

1

0

1

0

1

12

14

16

18

770

630

1310

2390

4550

2850

1040

1810

3470

5440

10620

16

October 15, 2019

ZSSC3230 Datasheet

6.5 Calibration Math

The data path internally calculates with a 26-bit two’s-complement integer representation. The coefficients in the memory are stored as integers

in sign-magnitude representation (1-bit sign + 23-bit magnitude). Each multiplication scales the product by 2²³. There is an option to preprocess

the data by applying a 1/C algorithm. 1/C is typically used to pre-process transfer characteristics for capacitive pressure sensors. A principle

flow is shown in Figure 11.

Internal overflows and underflows are detected and the result is automatically saturated. The saturation is reported in the status byte.

Figure 11. Principal Compensation Flow

ADC-Conversion:

Raw-result SM

Yes

No

Apply 1-1/C

calculation?

S_raw:=S_raw

S_rawi:=1-1/S_raw

SSC-Correction Math (using S_raw or S_rawi;T_raw)

Result S

S_out = S

6.5.1 1/C Pre-compensation

For capacitive pressure sensors, a pre-compensation of the ADC signal might be beneficial. Using this function will help to fit the typical pressure

sensor transfer characteristic to matching the second-order compensation input requirements for more accurate compensation results. If the

1/C pre-compensation is activated, it will apply only in Normal Measurement Mode with math compensation, not in RAW measurements using

Command Mode. The respective 1/C calculation for determination of calibration coefficients is handled in the respective calibration.dll. This

feature can be enabled by setting the corresponding bit siginv (bit[11] in memory register 02_HEX; see Table 16). Before the 1/C math is applied,

the ADC value of the respective sensor input signal will be inverted.

This leads to the following transfer function for S_raw with the system transfer function that is shown in Figure 12.

25

2

- 1

2⁴⁶

S_rawi= [2²⁴−

]

Equation 2

S_raw

25

-2

Note: For the application, if a “C_range/C_Sens” inversion will be performed, the shift capacitor must to be set to “0.”

17

October 15, 2019

ZSSC3230 Datasheet

Figure 12. System Transfer Function for 1/C

Full transfer function

4

Normal

1/c

3

2

1

0

-1

-2

-3

-4

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

Relative input capacitance (S ) input

raw

6.5.2 Sensor Signal Compensation Math

The SOT_curve (bit [15] in EEPROM word 02_HEX; see Table 16) selects whether second-order equations compensate for sensor nonlinearity

with a parabolic or S-shaped curve. The parabolic compensation is recommended.

Equations for the Parabolic SOT_curve Setting (SOT_curve = 0):

The coefficients from the memory (23-bit absolute and 1-bit sign; see Table 7) are read into 26-bit-wide registers in the calculation block. The

24-bit-memory coefficients are shifted by two bits so that the MSB of the 24-bit memory coefficient is placed at the MSB of the 26-bit calculation

register coefficient.

Simplified:

T_Raw

2²³

4 ∙ SOT_tcg

K₁= 2²³+

∙ (

∙ T_{_Raw}+ 4 ∙ Tcg)

Equation 3

2²³

T_Raw

K₂= 4 ∙ Offset_S + S_Raw +

∙ ꢀ^{4 ∙ SOT_tco}∙ T_{_Raw}+ 4 ∙ Tcoꢁ

23

Equation 4

Equation 5

Equation 6

2

4 ∙ Gain_S

K

1

Z_SP

=

∙

∙ K₂+ 2²³

(Bounded to positive number range)

23

2

Z

SP

23

S =

∙ ꢀ^{4 ∙ SOT_sensor}∙ Z_SP+ 2²³ꢁ + Sensor_Shift

23

2

18

October 15, 2019

ZSSC3230 Datasheet

Equations for the S-shaped SOT_curve Setting (SOT_curve = 1):

Simplified:

4 ∙ Gain_S

K

1

Z_SS

=

∙

∙ K₂

23

Equation 7

Equation 8

2

Z

S =

∙ ꢀ^{4 ∙ SOT_sensor}∙ Z_SS+ 2 ꢁ + 2 + Sensor_Shift

(Bounded to positive number range)

23

SS

23

|

23

2

Complete:

2

²⁵1











Equation 9

K

2²³

Gain _S

2²¹





²



1

Z_SS





K₂

25

_2

25

_2

²⁴1

2

²⁵1





²



²⁵1

Equation 10









²⁵1

²



²

Z_SS

2²³

SOT_ sensor





 2²³Sensor _Shift



²³

S 



 Z_SS

 2





2²¹









25

_2



25

_2







25



_2







₀

Where the following representations are valid:

S

Corrected capacitive sensor reading output via I2C; range: [0 to FFFFFF_HEX

Raw capacitive sensor reading from ADC (after auto-zero correction); shifted range to: [-7FFFFF_HEXto 7FFFFF_HEX

Capacitive sensor gain term; range: [-7FFFFF_HEXto 7FFFFF_HEX

Capacitive sensor offset term; range: [-7FFFFF_HEXto 7FFFFF_HEX

Temperature coefficient gain term; range: [-7FFFFF_HEXto 7FFFFF_HEX

Temperature coefficient offset term; range: [-7FFFFF_HEXto 7FFFFF_HEX

Raw temperature reading (after AZ correction); shifted range to: [-7FFFFF_HEXto 7FFFFF_HEX

]

S_Raw

Gain_S

Offset_S

Tcg

]

Tco

]

T_Raw

SOT_tcg

SOT_tco

SOT_sensor

Sensor_shift

]

Second-order term for Tcg non-linearity; range: [-7FFFFF_HEXto 7FFFFF_HEX

Second-order term for Tco non-linearity; range: [-7FFFFF_HEXto 7FFFFF_HEX

]

Second-order term for sensor non-linearity; range: [-7FFFFF_HEXto 7FFFFF_HEX

]

Post-calibration, post-assembly offset shift; range: [-7FFFFF_HEXto 7FFFFF_HEX

Absolute value

]



ul

ll







Bound number range from ll to ul; if needed, apply saturation at the limits ll or ul and report overflow/underflow in the

status byte

19

October 15, 2019

ZSSC3230 Datasheet

6.5.3 Temperature Signal Compensation

Temperature is measured internally. Temperature correction contains both linear gain and offset terms as well as a second-order term to correct

for any nonlinearities. For temperature, second-order compensation for nonlinearity is always parabolic:

Simplified:

4 ∙ Gain_T

23

ꢂ

ꢃ

Z_T=

T =

∙ T_Raw + 4 ∙ Offset_T + 2

(Bounded to positive number range)

23

Equation 11

Equation 12

2

Z

∙ ꢀ^{4 ∙ SOT_T}∙ Z_T+ 2²³ꢁ + T_Shift

T

23

2

Where

T

Corrected Temperature reading output via I2C; range [0_HEXto 0xFFFFFF_HEX

Gain coefficient for temperature; range [-7FFFFF_HEXto 7FFFFF_HEX

Raw temperature reading after AZ correction; shifted range to [-7FFFFF_HEXto 7FFFFF_HEX

Offset coefficient for temperature; range [-7FFFFF_HEXto 7FFFFF_HEX

Second-order term for temperature source non-linearity; range [-7FFFFF_HEXto 7FFFFF_HEX

]

Gain_T

T_Raw

]

Offset_T

SOT_T

T_Shift

]

Shift for post-calibration/post-assembly offset compensation [-7FFFFF_HEXto 7FFFFF_HEX

]

Table 7.

Data Format of Calibration Coefficients in Memory

Bit Number:

23

22

21

20

…

2

1

0

Meaning, Weighting: 0 = Positive

2¹

2⁰

2^-1

…

2^-19

2^-20

2^-21

1 = Negative

6.6 Output Stages

The ZSSC3230 supports signal output via a PDM output pin and I2C output. Measured values are provided at an I2C output interface and at a

pulse-density modulation (PDM) output. The digital interface can be used for configuration and the calibration procedure using the user’s

computer in order to program a set of calibration coefficients into the on-chip memory.

6.6.1 PDM Output Stage

To use the ZSSC3230 in PDM Output Mode, the Cyclic Measurement Mode is required. The ZSSC3230 will not go into Sleep Mode or power-

down between measurements. The PDM Output Mode can be enabled via the PDM_enable bit (bit[9] in memory register 02_HEX; see Table 16).

In this case, the PDM output will be started after power-on reset.

Note: If the ZSSC3230 is not used in PDM Output Mode, the PDM pin should not be connected.

The ZSSC3230 provides a pseudo-analog output of a sigma-delta modulator, i.e. a pulse-density stream, which can be converted into an analog

DAC-like output by external low-pass filtering. The PDM signal will be output selectively at the PDM pin. The PDM output is available for the

compensated sensor signal. The PDM output is scaled to a 16-bit wide output signal.

When the PDM output is used, an external capacitor must be connected to the PDM output as shown in Figure 13.

20

October 15, 2019

ZSSC3230 Datasheet

Table 8.

Analog Output Performance by External Capacitor Value

Filter Capacitance (nF)

Vout Ripple (µV/V)

0 to 90%Settling Time (ms)

Analog Output Resolution (Bit)

100

400

1000.0

250

62

2.3

9.2

10

12

14

16

1600

6400

36.8

147.2

16

Figure 13. PDM Output Configuration

VDD

ZSSC3230

VSS

CC

A_OUT

PDM

C0

VSS

RESQ

CC

6.6.2 I2C Output

The ZSSC3230 supports an I2C slave interface for digital output operation. The implementation of the interfaces is such that the available

commands (see section 6.7.2) and request codes for the ZSSC3230 are the same regardless on the interface type used.

Initially after power-up or reset, the I2C slave address is loaded from the on-chip NVM from the Slave_Addr bits [6:0] in register 02_HEX; see

Table 16). There is a general status byte, which is part of the ZSSC3230’s digital response on READ requests. Every response starts with a

status byte followed by the data word. The data word depends on the previous command. It is possible to read the same data more than once

if the read request is repeated. The next command invalidates any previous data.

Table 9.

Bit-Number:

Meaning:

General Status Byte

7

6

5

4

3

2

1

0

Powered?

Busy?

Mode

Memory

Error?

ADC Overflow

Math

Saturation

.

Bit 7 is intentionally not assigned in order to allow for a 1 bit-length time.

Bit 6 indicates power: 1 if device is powered, 0 if not powered.

Bit 5 indicates whether the ZSSC3230 is busy. The data for the last command is not available yet. No new commands are processed if

the device is busy. It is “1” if the device is busy.

21

October 15, 2019

ZSSC3230 Datasheet

.

Bit 3 and 4 indicate the actual mode of the ZSSC3230: 00 = Normal Operation Mode; 01 = Command Mode; 10 = Test Mode. See Table

10.

Bit 2 shows whether there has been a memory integrity/error as indicated by whether the checksum-based integrity check passed or

failed: 0 if the integrity test passed; 1 if the test failed.

Bit 1 shows whether there has been an ADC overflow, which is detected if the raw ADC-output value for capacitive measurement

exceeded the nominal, digital ADC-output range, depending on the selected ADC resolution. This check is only for the raw results for the

capacitive measurement.

.

Bit 0 shows the status Information regarding ALU saturation. If the last executed command was a measurement request, this bit is 0 if any

intermediate value and the final SSC result are in a valid range and no SSC-calculation internal saturation occurred. If the last command

was a measurement request, this bit is 1 if an SSC-calculation internal saturation occurred. This bit is also 0 for any non-measurement

command.

Table 10. Mode Status

Status[4:3]

Mode

00

01

10

11

Normal Operation Mode (sleep and cyclic operations)

Command Mode

IDT Reserved for Test Mode

IDT Reserved

The I2C interface is compliant with the NXP I2C Bus Specification, Rev. 06 (UM10204, 4 April 2014). All modes up to High Speed Mode are

supported. Slave address codes 04_HEXto 07_HEXmust not be programmed to the ZSSC3230 since they are exclusively used for the High Speed

Mode. The ZSSC3230 will support 7 bit addressing only.

In I2C Mode, each command is started as shown in Figure 14. Only the number of bytes that are needed for the command must be sent. An

exception is the I2C High Speed Mode where 3 bytes must always be sent. After the execution of a command (busy = 0), the expected data

can be read as illustrated in Figure 15 or if no data are returned by the command, the next command can be sent. The status can be read at

any time as described in Figure 16.

Figure 14. I2C Command Request

Command Request (I2C Write)

from master to slave

from slave to master

S

P

A

N

START condition

STOP condition

acknowledge

S

SlaveAddr

0

A

Command

A

P

write

0

CmdDat

<15:8>

CmdDat

<7:0>

S

SlaveAddr

A

Command

A

P

not acknowledge

write

22

October 15, 2019

ZSSC3230 Datasheet

Figure 15. I2C Read Data

Read Data (I2C Read)

(a) Example: after the completion of a Memory Read command

MemDat

<15:8>

MemDat

<7:0>

S

SlaveAddr

1

A

Status

A

N P

read

(b) Example: after the completion of a Measure command (AA_HEX

)

SensorDat

<23:16>

SensorDat

<15:8>

SensorDat

<7:0>

TempDat

<23:16>

TempDat

<15:8>

TempDat

<7:0>

S

SlaveAddr

1

A

Status

A

N P

read

Figure 16. I2C Read Status

Read Status (I2C Read)

S

SlaveAddr

1

A

Status

N P

read

Table 11. I2C Interface Parameters

Symbol

f_SCL

Parameter

Interface clock

Conditions

Minimum

Typical

Maximum

3.4

Units

MHz

%

0.1

33

0.7

0.0

–

D_SPI

Duty cycle

50

V_high,I2C

V_low,I2C

C_SDA

Input HIGH level voltage

Input LOW level voltage

–

1.0

V_DD

pF

Referenced to the external supply voltage V_DD

–

0.3

Capacitive load at input

pin, SDA

.

100pF  maximum for Standard and

Fast Mode; in High-Speed Mode

f_SCL,max= 3.4MHz

100

400

.

400pF  only in High-Speed Mode,

f_SCL,max= 1.7MHz

V_SDA=0.4V, Standard and Fast Mode with

400kHz; 400pF load

I_OL

LOW level output current

3

6

40

mA

Details for timing and protocol of the ZSSC3230-supported I2C communication in Standard Mode, Fast Mode, and High-Speed Mode are given

in the I2C-Bus Specification, Rev.6, UM10204.

23

October 15, 2019

ZSSC3230 Datasheet

6.6.3 EOC and Output Interrupt Signaling

The EOC pin can be programmed to operate either as a “measurement busy” indicator and end-of-conversion (EOC) transducer, or as a

configurable interrupt transducer. The respective basic operation must be programmed into INT_setup bits in the memory (bits[8:7] in NVM

register 02_HEX; see Table 16). One or two 24-bit-quantized thresholds can be programmed (see the Interrupt Level Setup memory registers:

13_HEX, 14_HEXand 15_HEX). Depending on the INT_setup selection, the EOC pin provides a logic 1 or logic 0 according to the SSC-corrected

measurement result. The respective thresholds are programmed left-aligned in the memory, such that they must be programmed with the

threshold’s MSB in the memory register’s MSB, etc. The LSBs of the 24-bit threshold in the memory must be ignored according to the number

of bits of the selected ADC resolution (according to adc_bits).

If only the effective end-of-conversion is signalized (INT_setup = 00_BIN), the EOC signal is pulse of approximately 5µs. The next command will

be executed only after this EOC-signaling period.

The interrupt functionality is only available for digital values from the SSC-calculation unit. The interrupt feature cannot monitor any type of raw

values. The encoding and data format of the interrupt thresholds is the same as for SSC-corrected measurement results (see Table 12).

Table 12. Data Format of Interrupt Thresholds (TRSH1 and TRSH2)

Bit-Number:

23

22

21

20

…

2

1

0

Meaning, Weighting:

2⁰

2^-1

2^-2

2^-3

…

2^-21

2^-22

2^-23

24

October 15, 2019

ZSSC3230 Datasheet

Figure 17 EOC and Interrupt Thresholds

INT_setup = 01:

INT_setup = 10:

Measurement > threshold1

Measurement < threshold1

Measurement

Result

max.

threshold 1

0

Time

EOC / INT

1

0

1

0

Time

INT_setup = 11

Case A:

threshold1 > threshold2

Case B:

threshold1 < threshold2

Measurement

Result

max.

threshold 1

threshold 2

threshold 1

0

Time

EOC / INT

1

0

1

0

25

October 15, 2019

ZSSC3230 Datasheet

6.7 Measurement and Output Options

Sensor measurement results of the ZSSC3230 are provided in digital at the I2C interface. This will be the main active interaction path, and it

can combined with the PDM output configuration.

6.7.1 Single Measurements: Digital Raw and SSC Results

The ZSSC3230 generates digital raw values, which are processed by the IC-internal math-core generating the SSC-corrected (linearized,

temperature-compensated) output signal; see section 6.5.2 for details about SSC math, etc. In addition to the SSC-corrected digital

measurement results, the ZSSC3230 can provide raw values with or without SSC correction for evaluation and/or calibration purposes. The

respective results are provided at the digital interface as a 24-bit-wide data word. Raw values are LSB-aligned. SSC results are MSB-aligned.

Table 13. Data Format of Raw ADC Readings

Bit-Number:

23

22

21

20

…

2

1

0

Meaning, Weighting:

-2⁰

2^-1

2^-2

2^-3

…

2^-21

2^-22

2^-23

Table 14. Data Format of Corrected SSC Results

Bit-Number:

23

22

21

20

…

2

1

0

Meaning, Weighting:

2⁰

2^-1

2^-2

2^-3

…

2^-21

2^-22

2^-23

The ZSSC3230 can process and digitize the following signals:

.

Direct sensor signal inputs; i.e. perform sensor measurements, SM

Auto-zero signals for the sensor channel, referred to as AZS

Direct temperature signal inputs; i.e. perform temperature measurements, TM

Auto-zero signals for the temperature channel, referred to as AZT

The utilization of auto-zero measurements allows inherent compensation for long-term drift effects of the ZSSC3230, such that the risk of lifetime

signal degradation for the application and smart sensor is minimized. For the auto-zero measurement, the sensor signal remains the input for

the auto-zero measurement with the gain and ADC setups the same as for the original signal measurement, but with swapped inputs and offset

configurations of the PGA and ADC such that the following holds for the resulting raw value:

.

Sensor raw value with auto-zero: S_raw = 0.5  (SM – AZS)

Temperature raw value with auto-zero: T_raw = 0.5  (TM – AZT)

Enabling auto-zero measurements is strongly recommended.

The NVM configuration and measurement request commands can be used to select which effective measurements are conducted, processed,

and provided at the digital interface. The possible options for a single measurement request and output are the following:

.

SSC-corrected sensor readings (requested by the “Measure” command AA_HEX) generating an output of SSC-corrected, 24-bit sensor data

followed by SSC-corrected, 24-bit temperature data.

Raw sensor measurement with auto-zero correction (requested by the “Raw Sensor Measure” command A2_HEX) generating an output of

raw, 24-bit sensor data.

Raw temperature measurement with auto-zero correction (requested by the “Raw Temperature Measure” command A6_HEX) generating an

output of raw, 24-bit temperature data.

26

October 15, 2019

ZSSC3230 Datasheet

6.7.2 Digital Commands

The availability of commands depends on the active Main Operating Mode: Command, Sleep, or Cyclic Measurement Mode.

Table 15. Command List

Command Code

(Byte)

Return

16-bit data

Description

00_HEXto 1F _HEX

Memory Read: Read address 00_HEXto 1F_HEX

.

Yes

No

20_HEXto 3C_HEX

–

Memory Write: Write data to addresses 00_HEXto 1C_HEX(the

NVM-register address is the command minus 20_HEX). Note: If the

NVM is locked, write requests are not acknowledged or ignored.

followed by data

(0000_HEXto FFFF_HEX

)

90_HEX

–

Calculate NVM Checksum: Calculate the checksum for the

NVM and write it to the memory.

Yes

No

A2_HEXfollowed by data 24-bit raw data

0000_HEX

Raw Sensor Measurement:* Conduct a sensor measurement

without SSC correction. The configuration is loaded to the

controlling shadow registers from the Sensor_config register in

NVM.

Note: The auto-zero sensor measurement is also performed.

A3_HEXfollowed by data 24-bit raw data

ssss_HEX

Raw Sensor Measurement:* Conduct a sensor measurement

without SSC correction. The ssss is the user’s configuration

setting for the measurement provided via the interface. The

format and purpose of the configuration bits must be according

to the definitions for Sensor_config.

Yes

No

Yes

No

Note: The auto-zero sensor measurement is also performed.

A6_HEXfollowed by data 24-bit raw data

0000_HEX

Raw Temperature Measurement:* Conduct a temperature

measurement without SSC correction. The configuration is

loaded to the controlling shadow registers from the

extTemp_Config1/2 or T_config1/2 registers in NVM as well as

the SSF1/2 registers.

Note: Auto-zero-sensor measurement is performed.

A8_HEX

–

START_SLEEP: Exit Command Mode or Cyclic Measurement

Mode and transition to Sleep Mode.

Yes

Note: The response to Start_Sleep is only the status byte.

A9_HEX

AA_HEX

START_CM: Enter Command Mode and enable/allow

respective commands. This command must be sent as the first

command after power-up.

No

Yes

No

24-bit SSC-corrected Measure – trigger a full measurement (auto-zero-sensor,

sensor data and sensor, auto-zero-temperature, temperature) and perform the

Yes

24-bit SSC-corrected SSC correction.

temperature data

*

These commands can be used to conduct a measurement without SSC correction; e.g., during smart sensor calibration procedure. No digital correction is performed

on the measurement result.

27

October 15, 2019

ZSSC3230 Datasheet

Command Code

(Byte)

Return

Description

AB_HEX

24-bit SSC-corrected START_CYC: Enter Cyclic Measurement Mode: continuous

sensor data and measurement cycles, SSC corrections, and automatic,

24-bit SSC-corrected continuous digital output updates.

temperature data

Yes

No

AC_HEX

AD_HEX

AE_HEX

AF_HEX

Oversample-2 Measure:* Complete multiple measurements for

mean-value generation: 2 full measurements are performed (the

same as measurements triggered with AA_HEX, not cyclic) and the

resulting mean value is provided as output.

Oversample-4 Measure:* Complete multiple measurements for

mean-value generation: 4 full measurements are performed (the

same as AA_HEXmeasurements, not cyclic) and the resulting

mean value is provided as output.

24-bit SSC-corrected

sensor data and

24-bit SSC-corrected

temperature data

Oversample-8 Measure:* Complete multiple measurements for

mean-value generation: 8 full measurements are performed (the

same as AA_HEXmeasurements, not cyclic) and the resulting

mean value is provided as output.

Oversample-16 Measure:* Complete multiple measurements

for mean-value generation: 16 full measurements are performed

(the same as AA_HEXmeasurements, not cyclic) and the resulting

mean value is provided as output.

B0_HEX

B4_HEX

16-bit data output

0 pass / 1 fail

Broken Chip: Test resistance of corner wire.

Yes

No

Yes

No

-

Stop PDM: This command can be used to stop the PDM in

Yes

order to change the PDM enable in NVM.

This command does not sent an ack.

FX_{HEX X}followed by

data XX_HEX

-

Soft-Reset: Full reset of digital part.

Yes

Note: Any FX_HEXcommand extended by one arbitrary data byte

results in the soft reset. This command will not be answered by

an acknowledge

6.7.3 Nonvolatile Memory (NVM)

In the ZSSC3230, the memory is organized in 16-bit wide registers and can be programmed multiple times (approximately 10000). There are

28 x 16-bit registers available for customer use. Each register can be re-programmed. Basically, there are two NVM content sectors:

.

Customer Use – Accessible by means of regular WRITE operations: 20_HEXto 3C_HEX. It contains the customer ID, interface setup data,

measurement setup information, calibration coefficients, etc.

.

IDT Use – Only accessible for WRITE operations by IDT. This sector contains specific trim information and is programmed during

manufacturing test by IDT; e.g., configurations for the internal temperature sensor are stored there.

*

Use oversample measurements to obtain noise-minimized measurement results in Sleep or Command Mode. With higher oversampling factors, the command

execution time increases proportionally.

28

October 15, 2019

ZSSC3230 Datasheet

6.7.4 Memory Contents

Table 16. Memory (NVM) Content Assignments

NVM

Address

Word/Bit

Range

Default

Setting

Word/Bit Field

Name

Description

00_HEX

01_HEX

15:0

0000_HEX

Cust_ID0

Cust_ID1

Customer ID byte 0 (combines with memory word 01_HEXto form the customer ID).*

Customer ID byte 1 (combines with memory word 00_HEXto form the customer ID).

Interface Configuration

I2C and OWI slave address; valid range: 00_HEXto 7F_HEX(default: 00_HEX).

6:0

000 0000_BIN

Slave_Addr

Note: Address codes 04_HEXto 07_HEXare reserved for entering the I2C High

Speed Mode.

Interrupt configuration, EOC pin functionality:

00 End-of-conversion signal

01 0-1 transition if threshold1 (TRSH1) is exceeded and 1-0 transition if

threshold1 is underrun again

10 0-1 transition if threshold1 is underrun and 1-0 transition if threshold1 is

exceeded again

8:7

00_BIN

INT_setup

11 EOC is determined by threshold settings (see section 6.6.3):

If (TRSH1 > TRSH2) then EOC/INT (interrupt level) = 0 if (TRSH1 > MEAS ≥

TRSH2) where MEAS is the conditioned measurement result.

Otherwise EOC/INT=1.

If (TRSH1 ≤ TRSH2) then EOC = 1 if (TRSH1 ≤ MEAS < TRSH2).

Otherwise EOC = 0.

Enables PDM-output:

02_HEX

0  PDM output disabled

1  PDM output enabled

9

0_BIN

PDM_enable

If PDM_enable bit is 1, the ZSSC3230 will start after reset without any further

command in Cyclic Measurement Mode

10

11

0_BIN

Reserved

siginv

Enables input signal inversion (“1-1/C”) in conditioning math:

0  “1-1/C” disabled

1  “1-1/C” enabled

Update period (ZSSC3230 sleep time, except oscillator) in cyclic operation:

000  0.0ms (= PDM default)

001  167ms

100  1333ms

101  2667ms

110  5333ms

111  Not assigned

14:12

15

000_BIN

CYC_period

SOT_curve

010  333ms

011  666ms

Type/shape of second-order curve correction for the sensor signal.

0  parabolic curve 1  s-shaped curve

0_BIN

* For I³C operation, this should contain the Legacy Virtual Register “LVR” info: 0x1X … Index 0; Fast Mode supported.

29

October 15, 2019

ZSSC3230 Datasheet

NVM

Address

Word/Bit

Range

Default

Setting

Word/Bit Field

Name

Description

Signal Conditioning Parameters

03_HEX

04_HEX

05_HEX

15:0

0000_HEX

Offset_S[15:0]

Gain_S[15:0]

Tcg[15:0]

Bits [15:0] of the 24-bit-wide sensor offset correction coefficient Offset_S. (MSBs of

this coefficient including sign are Offset_S[23:16], which are bits [15:8] in 0D_HEX.)

Bits [15:0] of the 24-bit-wide value of the sensor gain coefficient Gain_S. (MSBs of

this coefficient including sign are Gain_S[23:16], which are bits [7:0] in 0D_HEX.)

Bits [15:0] of the 24-bit-wide coefficient Tcg for the temperature correction of the

sensor gain. (The MSBs of this coefficient including sign are Tcg[23:16], which

are bits [15:8] in 0E_HEX.)

06_HEX

15:0

0000_HEX

Tco[15:0]

Bits [15:0] of the 24-bit-wide coefficient Tco for temperature correction of the

sensor offset. (The MSBs of this coefficient including sign are Tco[23:16], which

are bits [7:0] in 0E_HEX.)

07_HEX

08_HEX

09_HEX

15:0

0000_HEX

SOT_tco[15:0]

SOT_tcg[15:0]

SOT_sens[15:0]

Bits [15:0] of the 24-bit-wide 2^ndorder term SOT_tco applied to Tco. (The MSBs of

this term including sign are SOT_tco[23:16], which are bits[15:8] in 0F_HEX.)

Bits [15:0] of the 24-bit-wide 2^ndorder term SOT_tcg applied to Tcg. (The MSBs of

this term including sign are SOT_tcg[23:16], which are bits[7:0] in 0F_HEX.)

Bits [15:0] of the 24-bit-wide 2^ndorder term SOT_sens applied to the sensor read-

out. (The MSBs of this term including sign are SOT_sens[23:16], which are

bits[15:8] in 10_HEX.)

0A_HEX

0B_HEX

15:0

0000_HEX

Offset_T[15:0]

Gain_T[15:0]

Bits [15:0] of the 24-bit-wide temperature offset correction coefficient Offset_T.

(MSBs of this coefficient including sign are Offset_T[23:16]; i.e., bits[7:0] in 10_HEX.)

Bits [15:0] of the 24-bit-wide absolute value of the temperature gain coefficient

Gain_T. (The MSBs of this coefficient including sign are Gain_T[23:16], which are

bits[15:8] in 11_HEX.)

0C_HEX

15:0

0000_HEX

SOT_T[15:0]

Bits [15:0] of the 24-bit-wide 2^nd-order term SOT_T applied to the temperature

reading. (The MSBs of this coefficient including sign are SOT_T[23:16], which are

bit[7:0] in 11_HEX.)

7:0

00_HEX

Gain_S[23:16]

Offset_S[23:16]

Tco[23:16]

Bits [23:16] including sign for the 24-bit-wide sensor gain correction coefficient

Gain_S. (The LSBs of this coefficient are Gain_S[15:0] in register 03_HEX.)

0D_HEX

0E_HEX

0F_HEX

10_HEX

15:8

7:0

Bits [23:16] including sign for the 24-bit-wide sensor offset correction coefficient

Offset_S. (The LSBs are Offset_S[15:0] in register 04_HEX.)

Bits [23:16] including sign for the 24-bit-wide coefficient Tco for temperature

correction for the sensor offset. (The LSBs are Tco[15:0] in register 05_HEX.)

15:8

Tcg[23:16]

Bits [23:16] including sign for the 24-bit-wide coefficient Tcg for the temperature

correction of the sensor gain. (The LSBs are Tcg[15:0] in register 06_HEX.)

Bits [23:16] including sign for the 24-bit-wide 2^ndorder term SOT_tcg applied to

Tcg. (The LSBs are SOT_tcg[15:0] in register 07_HEX.)

7:0

00_HEX

SOT_tcg[23:16]

Bits [23:16] including sign for the 24-bit-wide 2^ndorder term SOT_tco applied to

Tco. (The LSBs are SOT_tco[15:0] in register 08_HEX.)

15:8

7:0

00_HEX

SOT_tco[23:16]

Offset_T[23:16]

Bits [23:16] including sign for the 24-bit-wide temperature offset correction

coefficient Offset_T. (The LSBs are Offset_T[15:0] in register 09_HEX.)

Bits [23:16] including sign for the 24-bit-wide 2^ndorder term SOT_sens applied to

the sensor readout. (The LSBs are SOT_sens[15:0] in register 0A_HEX.)

15:8

00_HEX

SOT_sens[23:16]

30

October 15, 2019

ZSSC3230 Datasheet

NVM

Address

Word/Bit

Range

Default

Setting

Word/Bit Field

Name

Description

Bits [23:16] including sign for the 24-bit-wide 2^nd-order term SOT_T applied to the

temperature reading. (The LSBs are SOT_T[15:0] in register 0B_HEX.)

7:0

00_HEX

SOT_T[23:16]

Gain_T[23:16]

11_HEX

Bits [23:16] including sign for the 24-bit-wide absolute value of the temperature

gain coefficient Gain_T. (The LSBs are Gain_T[15:0] in register 0C_HEX.)

15:8

Measurement Configuration (Sensor_config) Register

Defines the zero shift capacitance input offset shift to cancel the static input

capacitance of the sensor:

00 0000  no offset shift

00 0001  0.25pF

00 0010 0.50pF

00 0011 0.75pF

00 0100 1.00pF

00 0101 1.25pF

00 0110 1.50pF

00 0111 1.75pF

00 1000 2.00pF

00 1001 2.25pF

…

5:0

00 0000_BIN

shift_cap

11 1101 15.00pF

11 1110 15.50pF

11 1111 15.75pF

Note: the offset shift capacitance must not exceed the selected input

capacitance’s range (see cap_range).

Defines the absolute number of bits for the A2D conversion:

7:6

8

00_BIN

adc_bits

00 12-bit

10 16-bit

11 18-bit

01 14-bit (default)

Select between control sequences for noise-quality vs. energy consumption

optimization:

0_BIN

noise_mode

12_HEX

0  Low Current Mode

1  Low Noise Mode

Selection maximum possible external signal capacitance; i.e. the capacitance

sensor range (without any offset):

00000  0.5pF

00001  1.0pF

00010  1.5pF

00011  2.0pF

00100  2.5pF

00101  3.0pF

00110  3.5pF

00111  4.0pF

01000  4.5pF

01001  5.0pF

01010  5.5pF

01011  6.0pF

01100  6.5pF

01101  7.0pF

01110  7.5pF

01111  8.0pF

10000  8.5pF

10001  9.0pF

10010  9.5pF

10011  10.0pF

10100  10.5pF

10101  11.0pF

10110  11.5pF

10111  12.0pF

11000  12.5pF

11001  13.0pF

11010  13.5pF

11011  14.0pF

11100  14.5pF

11101  15.0pF

11110  15.5pF

11111  16.0pF

13:9

0 0000_BIN

cap_range

31

October 15, 2019

ZSSC3230 Datasheet

NVM

Address

Word/Bit

Range

Default

Setting

Word/Bit Field

Name

Description

Option to enable sensor element’s leakage current compensation (due to sensor

element’s parasitic resistance)  leakage cancellation leads to loss of dynamic

range and decrease of SNR (loss of 1 bit of effective resolution).

The following setups are possible:

14

15

0_BIN

sensor_leakage

sensecap_type

0  no sensor leakage cancellation; full internal dynamic range; full Vref

applied to external sensor

12_HEX

(Continued)

1  sensor leakage cancellation enabled; applied voltage at external sensor

of 0.5  Vref (loss of 1 bit of effective resolution)

Selection of applied (external) sensor capacitance:

0  “differential” sensor capacitance between C0 and CC (CC’) pads

0_BIN

1  single ended sensor capacitance between VSS and CC (CC’) pad;

applied voltage at external sensor of 0.5 × Vref (loss of 1 bit of effective

resolution)

Interrupt Level Setup and Post-Calibration (Digital) Offset Calibration

Bits [15:0] of the 24-bit-wide interrupt threshold1, TRSH1. (The MSBs for this

threshold are TRSH1[23:16], which are bits [7:0] of register 15_HEX.)

13_HEX

14_HEX

15:0

7:0

0000_HEX

00_HEX

TRSH1[15:0]

Bits [15:0] of the 24-bit-wide interrupt threshold2, TRSH2. (The MSBs for this

threshold are TRSH2[23:16], which are bits[15:8] of register 15_HEX.)

TRSH2[15:0]

Bits [23:16] of the 24-bit-wide interrupt threshold1, TRSH1. (The LSBs for this

threshold are TRSH1[15:0], which are bits[15:0] of register 13_HEX.)

TRSH1[23:16]

TRSH2[23:16]

SENS_Shift[15:0]

T_Shift[15:0]

15_HEX

Bits [23:16] of the 24-bit-wide interrupt threshold2, TRSH2. (The LSBs for this

threshold are TRSH2[15:0], which are bits[15:0] of register 14_HEX.)

15:8

15:0

7:0

00_HEX

Bits [15:0] of the post-calibration sensor offset shift coefficient SENS_Shift. (The

MSBs of SENS_Shift are bits [7:0] of register 18_HEX.)

16_HEX

17_HEX

0000_HEX

00_HEX

Bits [15:0] of the post-calibration temperature offset shift coefficient T_Shift. (The

MSBs of T_Shift are bits [15:8] of register 18_HEX.)

Bits [23:16] of the post-calibration sensor offset shift coefficient SENS_Shift. (The

LSBs of SENS_Shift are in register 16_HEX.)

SENS_Shift[23:16]

T_Shift[23:16]

18_HEX

Bits [23:16] of the post-calibration temperature offset shift coefficient T_Shift. (The

LSBs of T_Shift are in register 17_HEX.)

15:8

00_HEX

32

October 15, 2019

ZSSC3230 Datasheet

NVM

Address

Word/Bit

Range

Default

Setting

Word/Bit Field

Name

Description

Configuration Register

Defines which pin is used for measurement (CC and/or CC’):

00  no input

01  CC

1:0

00_BIN

CC_pin_selection

10  CC’

11  CC and CC’

Enable/disable digital dithering to improve EMI performance:

2

3

0_BIN

Dither

0  No dithering

Enable Subtraction Mode in grounded mode (see section 6.2.5):

0  Disabled 1  Enabled

Enable active shield drive at the C0 pin (see section 6.2.4):

0  Disabled 1  Enabled

1  Dithering enabled

En_sh2

En_shlddrv

19_HEX

4

Enables higher drive current in analog front end, which will be needed if the

sensor range is much smaller than the shift capacitor:

5

0_BIN

Dyn_imp

Test_cap

0  Disabled

1  Enabled

Enables an internal reference sensor capacitor of approx. 2pF in parallel to

sensor input:

6

0_BIN

0  Disabled

1  Enabled

IDT lot tracking information; can be overwritten and used as free space for

customer use.

15:7

Reserved

IDT lot tracking information; can be overwritten and used as free space for

customer use.

1A_HEX

1B_HEX

15:0

0000_HEX

Reserved

CRC

IDT lot tracking information; can be overwritten and used as free space for

customer use.

Generated checksum (CRC) for whole memory through a linear feedback shift

register (LFSR); Signature is checked upon power-up to ensure memory content

integrity

1C_HEX

15:0

0000_HEX

The NVM-consistency checksum is calculated (IC-internally for the whole NVM) using the polynomial: x¹⁶+ x¹⁵+ x²+ 1. The checksum

verification is only realized directly after V_DDpower-on. If the checksum is successfully verified, then the “Memory Error” status bit is set to 0_BIN

.

33

October 15, 2019

ZSSC3230 Datasheet

7. Package Outline Drawings

The package outline drawings VFQFPN package are appended at the end of this document and are accessible from the link below. The package

information is the most current data available.

https://www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-090-mm-body050mm-pitchepad-245-x-245-mm-nlg24p1

8. Marking Diagram

1. Line 1 is the truncated part number.

2. Line 2 – “YYWW” are the last two digit of the year and week that the part was

assembled.

3. Line 3 – “XXXXX” denotes assembly lot number.

9. Ordering Information

Orderable Part Number

ZSSC3230BC1B

ZSSC3230BC2B

ZSSC3230BI1B

ZSSC3230BI2B

ZSSC3230BC5B

ZSSC3230BC6B

ZSSC3230BI5B

ZSSC3230BI6B

ZSSC3230BC3R

ZSSC3230BI3R

ZSSC3230BI3W

ZSSC3230KIT

Description and Package

Dice on 304µm wafer no inking

Dice on 725µm wafer no inking

Dice on 304µm wafer no inking

Dice on 725µm wafer no inking

Dice on 304µm wafer with inking

Dice on 725µm wafer with inking

Dice on 304µm wafer with inking

Dice on 725µm wafer with inking

4  4 mm²PQFN

MSL Rating

Not applicable

MSL1

Carrier Type

Wafer Box

13” Reel

Temperature

-40 to 85°C

-40 to 125°C

-40 to 85°C

-40 to 125°C

-40 to 85°C

-40 to 125°C

4  4 mm²PQFN

MSL1

13” Reel

4  4 mm²PQFN

MSL1

7” Reel

ZSSC3230 Evaluation Board with USB Cable and 5 Samples

34

October 15, 2019

ZSSC3230 Datasheet

10. Glossary

Term

Description

A2D

ACK

ADC

AGND

AZ

Analog-to-Digital

Acknowledge (interface’s protocol indicator for successful data/command transfer)

Analog-to-Digital Converter or Conversion

Analog Ground

Auto-Zero (unspecific)

AZS

AZT

CLK

CVC

DAC

EOC

FSO

HVAC

LFSR

LSB

MSB

MSL

NACK

NVM

OpAmp

PGA

POR

PSRR

PTAT

S

Auto-Zero Measurement for (External) Sensor Path

Auto-Zero Measurement for (External or Internal) Temperature Path

Clock

Charge-Voltage Converter

Digital-to-Analog Converter or Conversion

End of Conversion

Full Scale Output (value in percent relative to the ADC maximum output code; resolution dependent)

Heating, Ventilation, and Air Conditioning

Linear Feedback Shift Register

Least Significant Bit

Most Significant Bit

Moisture Sensitivity Level

Not Acknowledge (interface’s protocol indicator for unsuccessful data/command transfer)

Nonvolatile Memory

Operating Amplifier

Programmable Gain Amplifier

Power-On Reset

Power Supply (Disturbance) Rejection Ratio

Proportional to Absolute Temperature

SSC-Corrected Sensor Readout / Result

Sensor Measurement

SM

SNR

SOT

SSF

T

Signal to Noise Ratio

Second-Order Term

Smart-Sensor Function (specific NVM registers)

SSC-Corrected (additional) Temperature Readout / Result

Temperature Coefficient

TC

35

October 15, 2019

ZSSC3230 Datasheet

11. Revision History

Revision Date

Description of Change

Values updated for Power-up conditions

Conditions updated for equations for the S-shaped SOT_curve setting

October 15, 2019

.

September 10, 2019

Initial release.

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138

Sales

Tech Support

www.IDT.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

www.IDT.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the ri ght to modify the products and/or specifications described herein at any time,

without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independe nt state and are not guaranteed to perform the same

way when installed in customer products. The information contained herein is pr ovided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitabi lity

of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented only as a guide and does not

convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be

reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the

property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated

36

October 15, 2019

24-VFQFPN, Package Outline Drawing

4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm

NLG24P1, PSC-4192-01, Rev 02, Page 1

24-VFQFPN, Package Outline Drawing

4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm

NLG24P1, PSC-4192-01, Rev 02, Page 2

Package Revision History

Description

Date Created Rev No.

Sept 9, 2016

Rev 01 Add Chamfer on Epad

Sept 13, 2018 Rev 02 New Format, Recalculate Land Pattern Change QFN to VFQFPN

1RWLFH

ꢄꢃ 'HVFULSWLRQVꢀRIꢀFLUFXLWVꢅꢀVRIWZDUHꢀDQGꢀRWKHUꢀUHODWHGꢀLQIRUPDWLRQꢀLQꢀWKLVꢀGRFXPHQWꢀDUHꢀSURYLGHGꢀRQO\ꢀWRꢀLOOXVWUDWHꢀWKHꢀRSHUDWLRQꢀRIꢀVHPLFRQGXFWRUꢀSURGXFWVꢀ

DQGꢀDSSOLFDWLRQꢀH[DPSOHVꢃꢀ<RXꢀDUHꢀIXOO\ꢀUHVSRQVLEOHꢀIRUꢀWKHꢀLQFRUSRUDWLRQꢀRUꢀDQ\ꢀRWKHUꢀXVHꢀRIꢀWKHꢀFLUFXLWVꢅꢀVRIWZDUHꢅꢀDQGꢀLQIRUPDWLRQꢀLQꢀWKHꢀGHVLJQꢀRIꢀ\RXUꢀ

SURGXFWꢀRUꢀV\VWHPꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀDQGꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ

WKHVHꢀFLUFXLWVꢅꢀVRIWZDUHꢅꢀRUꢀLQIRUPDWLRQꢃ

ꢁꢃ 5HQHVDVꢀ(OHFWURQLFVꢀKHUHE\ꢀH[SUHVVO\ꢀGLVFODLPVꢀDQ\ꢀZDUUDQWLHVꢀDJDLQVWꢀDQGꢀOLDELOLW\ꢀIRUꢀLQIULQJHPHQWꢀRUꢀDQ\ꢀRWKHUꢀFODLPVꢀLQYROYLQJꢀSDWHQWVꢅꢀFRS\ULJKWVꢅꢀRUꢀ

RWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀWKLUGꢀSDUWLHVꢅꢀE\ꢀRUꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRUꢀWHFKQLFDOꢀLQIRUPDWLRQꢀGHVFULEHGꢀLQꢀWKLVꢀ

GRFXPHQWꢅꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢅꢀWKHꢀSURGXFWꢀGDWDꢅꢀGUDZLQJVꢅꢀFKDUWVꢅꢀSURJUDPVꢅꢀDOJRULWKPVꢅꢀDQGꢀDSSOLFDWLRQꢀH[DPSOHVꢃꢀ

ꢆꢃ 1RꢀOLFHQVHꢅꢀH[SUHVVꢅꢀLPSOLHGꢀRUꢀRWKHUZLVHꢅꢀLVꢀJUDQWHGꢀKHUHE\ꢀXQGHUꢀDQ\ꢀSDWHQWVꢅꢀFRS\ULJKWVꢀRUꢀRWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀRUꢀ

RWKHUVꢃ

ꢇꢃ <RXꢀVKDOOꢀQRWꢀDOWHUꢅꢀPRGLI\ꢅꢀFRS\ꢅꢀRUꢀUHYHUVHꢀHQJLQHHUꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢅꢀZKHWKHUꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀ

DQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀRUꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀVXFKꢀDOWHUDWLRQꢅꢀPRGLILFDWLRQꢅꢀFRS\LQJꢀRUꢀUHYHUVHꢀHQJLQHHULQJꢃ

ꢈꢃ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀFODVVLILHGꢀDFFRUGLQJꢀWRꢀWKHꢀIROORZLQJꢀWZRꢀTXDOLW\ꢀJUDGHVꢉꢀꢊ6WDQGDUGꢊꢀDQGꢀꢊ+LJKꢀ4XDOLW\ꢊꢃꢀ7KHꢀLQWHQGHGꢀDSSOLFDWLRQVꢀIRUꢀ

HDFKꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀGHSHQGVꢀRQꢀWKHꢀSURGXFWꢋVꢀTXDOLW\ꢀJUDGHꢅꢀDVꢀLQGLFDWHGꢀEHORZꢃ

ꢊ6WDQGDUGꢊꢉ

&RPSXWHUVꢌꢀRIILFHꢀHTXLSPHQWꢌꢀFRPPXQLFDWLRQVꢀHTXLSPHQWꢌꢀWHVWꢀDQGꢀPHDVXUHPHQWꢀHTXLSPHQWꢌꢀDXGLRꢀDQGꢀYLVXDOꢀHTXLSPHQWꢌꢀKRPHꢀ

HOHFWURQLFꢀDSSOLDQFHVꢌꢀPDFKLQHꢀWRROVꢌꢀSHUVRQDOꢀHOHFWURQLFꢀHTXLSPHQWꢌꢀLQGXVWULDOꢀURERWVꢌꢀHWFꢃ

ꢊ+LJKꢀ4XDOLW\ꢊꢉ 7UDQVSRUWDWLRQꢀHTXLSPHQWꢀꢍDXWRPRELOHVꢅꢀWUDLQVꢅꢀVKLSVꢅꢀHWFꢃꢎꢌꢀWUDIILFꢀFRQWUROꢀꢍWUDIILFꢀOLJKWVꢎꢌꢀODUJHꢏVFDOHꢀFRPPXQLFDWLRQꢀHTXLSPHQWꢌꢀNH\ꢀ

ILQDQFLDOꢀWHUPLQDOꢀV\VWHPVꢌꢀVDIHW\ꢀFRQWUROꢀHTXLSPHQWꢌꢀHWFꢃ

8QOHVVꢀH[SUHVVO\ꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀSURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ

(OHFWURQLFVꢀGRFXPHQWꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀQRWꢀLQWHQGHGꢀRUꢀDXWKRUL]HGꢀIRUꢀXVHꢀLQꢀSURGXFWVꢀRUꢀV\VWHPVꢀWKDWꢀPD\ꢀSRVHꢀDꢀGLUHFWꢀWKUHDWꢀWRꢀ

KXPDQꢀOLIHꢀRUꢀERGLO\ꢀLQMXU\ꢀꢍDUWLILFLDOꢀOLIHꢀVXSSRUWꢀGHYLFHVꢀRUꢀV\VWHPVꢌꢀVXUJLFDOꢀLPSODQWDWLRQVꢌꢀHWFꢃꢎꢅꢀRUꢀPD\ꢀFDXVHꢀVHULRXVꢀSURSHUW\ꢀGDPDJHꢀꢍVSDFHꢀV\VWHPꢌꢀ

XQGHUVHDꢀUHSHDWHUVꢌꢀQXFOHDUꢀSRZHUꢀFRQWUROꢀV\VWHPVꢌꢀDLUFUDIWꢀFRQWUROꢀV\VWHPVꢌꢀNH\ꢀSODQWꢀV\VWHPVꢌꢀPLOLWDU\ꢀHTXLSPHQWꢌꢀHWFꢃꢎꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀ

DQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀGDPDJHVꢀRUꢀORVVHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀDQ\ꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀWKDWꢀLVꢀ

LQFRQVLVWHQWꢀZLWKꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢅꢀXVHUꢋVꢀPDQXDOꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢃ

ꢐꢃ :KHQꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀUHIHUꢀWRꢀWKHꢀODWHVWꢀSURGXFWꢀLQIRUPDWLRQꢀꢍGDWDꢀVKHHWVꢅꢀXVHUꢋVꢀPDQXDOVꢅꢀDSSOLFDWLRQꢀQRWHVꢅꢀꢊ*HQHUDOꢀ1RWHVꢀIRUꢀ

+DQGOLQJꢀDQGꢀ8VLQJꢀ6HPLFRQGXFWRUꢀ'HYLFHVꢊꢀLQꢀWKHꢀUHOLDELOLW\ꢀKDQGERRNꢅꢀHWFꢃꢎꢅꢀDQGꢀHQVXUHꢀWKDWꢀXVDJHꢀFRQGLWLRQVꢀDUHꢀZLWKLQꢀWKHꢀUDQJHVꢀVSHFLILHGꢀE\ꢀ

5HQHVDVꢀ(OHFWURQLFVꢀZLWKꢀUHVSHFWꢀWRꢀPD[LPXPꢀUDWLQJVꢅꢀRSHUDWLQJꢀSRZHUꢀVXSSO\ꢀYROWDJHꢀUDQJHꢅꢀKHDWꢀGLVVLSDWLRQꢀFKDUDFWHULVWLFVꢅꢀLQVWDOODWLRQꢅꢀHWFꢃꢀ5HQHVDVꢀ

(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀPDOIXQFWLRQVꢅꢀIDLOXUHꢀRUꢀDFFLGHQWꢀDULVLQJꢀRXWꢀRIꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRXWVLGHꢀRIꢀVXFKꢀ

VSHFLILHGꢀUDQJHVꢃ

ꢑꢃ $OWKRXJKꢀ5HQHVDVꢀ(OHFWURQLFVꢀHQGHDYRUVꢀWRꢀLPSURYHꢀWKHꢀTXDOLW\ꢀDQGꢀUHOLDELOLW\ꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀVHPLFRQGXFWRUꢀSURGXFWVꢀKDYHꢀVSHFLILFꢀ

FKDUDFWHULVWLFVꢅꢀVXFKꢀDVꢀWKHꢀRFFXUUHQFHꢀRIꢀIDLOXUHꢀDWꢀDꢀFHUWDLQꢀUDWHꢀDQGꢀPDOIXQFWLRQVꢀXQGHUꢀFHUWDLQꢀXVHꢀFRQGLWLRQVꢃꢀ8QOHVVꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀ

SURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀ

DUHꢀQRWꢀVXEMHFWꢀWRꢀUDGLDWLRQꢀUHVLVWDQFHꢀGHVLJQꢃꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀLPSOHPHQWLQJꢀVDIHW\ꢀPHDVXUHVꢀWRꢀJXDUGꢀDJDLQVWꢀWKHꢀSRVVLELOLW\ꢀRIꢀERGLO\ꢀLQMXU\ꢅꢀ

LQMXU\ꢀRUꢀGDPDJHꢀFDXVHGꢀE\ꢀILUHꢅꢀDQGꢒRUꢀGDQJHUꢀWRꢀWKHꢀSXEOLFꢀLQꢀWKHꢀHYHQWꢀRIꢀDꢀIDLOXUHꢀRUꢀPDOIXQFWLRQꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀVXFKꢀDVꢀVDIHW\ꢀ

GHVLJQꢀIRUꢀKDUGZDUHꢀDQGꢀVRIWZDUHꢅꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢀUHGXQGDQF\ꢅꢀILUHꢀFRQWUROꢀDQGꢀPDOIXQFWLRQꢀSUHYHQWLRQꢅꢀDSSURSULDWHꢀWUHDWPHQWꢀIRUꢀDJLQJꢀ

GHJUDGDWLRQꢀRUꢀDQ\ꢀRWKHUꢀDSSURSULDWHꢀPHDVXUHVꢃꢀ%HFDXVHꢀWKHꢀHYDOXDWLRQꢀRIꢀPLFURFRPSXWHUꢀVRIWZDUHꢀDORQHꢀLVꢀYHU\ꢀGLIILFXOWꢀDQGꢀLPSUDFWLFDOꢅꢀ\RXꢀDUHꢀ

UHVSRQVLEOHꢀIRUꢀHYDOXDWLQJꢀWKHꢀVDIHW\ꢀRIꢀWKHꢀILQDOꢀSURGXFWVꢀRUꢀV\VWHPVꢀPDQXIDFWXUHGꢀE\ꢀ\RXꢃ

ꢓꢃ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀIRUꢀGHWDLOVꢀDVꢀWRꢀHQYLURQPHQWDOꢀPDWWHUVꢀVXFKꢀDVꢀWKHꢀHQYLURQPHQWDOꢀFRPSDWLELOLW\ꢀRIꢀHDFKꢀ5HQHVDVꢀ

(OHFWURQLFVꢀSURGXFWꢃꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀFDUHIXOO\ꢀDQGꢀVXIILFLHQWO\ꢀLQYHVWLJDWLQJꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢀWKDWꢀUHJXODWHꢀWKHꢀLQFOXVLRQꢀRUꢀXVHꢀRIꢀ

FRQWUROOHGꢀVXEVWDQFHVꢅꢀLQFOXGLQJꢀZLWKRXWꢀOLPLWDWLRQꢅꢀWKHꢀ(8ꢀ5R+6ꢀ'LUHFWLYHꢅꢀDQGꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀLQꢀFRPSOLDQFHꢀZLWKꢀDOOꢀWKHVHꢀ

DSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀGDPDJHVꢀRUꢀORVVHVꢀRFFXUULQJꢀDVꢀDꢀUHVXOWꢀRIꢀ\RXUꢀQRQFRPSOLDQFHꢀ

ZLWKꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢃ

ꢔꢃ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDQGꢀWHFKQRORJLHVꢀVKDOOꢀQRWꢀEHꢀXVHGꢀIRUꢀRUꢀLQFRUSRUDWHGꢀLQWRꢀDQ\ꢀSURGXFWVꢀRUꢀV\VWHPVꢀZKRVHꢀPDQXIDFWXUHꢅꢀXVHꢅꢀRUꢀVDOHꢀLVꢀ

SURKLELWHGꢀXQGHUꢀDQ\ꢀDSSOLFDEOHꢀGRPHVWLFꢀRUꢀIRUHLJQꢀODZVꢀRUꢀUHJXODWLRQVꢃꢀ<RXꢀVKDOOꢀFRPSO\ꢀZLWKꢀDQ\ꢀDSSOLFDEOHꢀH[SRUWꢀFRQWUROꢀODZVꢀDQGꢀUHJXODWLRQVꢀ

SURPXOJDWHGꢀDQGꢀDGPLQLVWHUHGꢀE\ꢀWKHꢀJRYHUQPHQWVꢀRIꢀDQ\ꢀFRXQWULHVꢀDVVHUWLQJꢀMXULVGLFWLRQꢀRYHUꢀWKHꢀSDUWLHVꢀRUꢀWUDQVDFWLRQVꢃ

ꢄꢂꢃ ,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀEX\HUꢀRUꢀGLVWULEXWRUꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀRUꢀDQ\ꢀRWKHUꢀSDUW\ꢀZKRꢀGLVWULEXWHVꢅꢀGLVSRVHVꢀRIꢅꢀRUꢀRWKHUZLVHꢀVHOOVꢀRUꢀ

WUDQVIHUVꢀWKHꢀSURGXFWꢀWRꢀDꢀWKLUGꢀSDUW\ꢅꢀWRꢀQRWLI\ꢀVXFKꢀWKLUGꢀSDUW\ꢀLQꢀDGYDQFHꢀRIꢀWKHꢀFRQWHQWVꢀDQGꢀFRQGLWLRQVꢀVHWꢀIRUWKꢀLQꢀWKLVꢀGRFXPHQWꢃ

ꢄꢄꢃ 7KLVꢀGRFXPHQWꢀVKDOOꢀQRWꢀEHꢀUHSULQWHGꢅꢀUHSURGXFHGꢀRUꢀGXSOLFDWHGꢀLQꢀDQ\ꢀIRUPꢅꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢅꢀZLWKRXWꢀSULRUꢀZULWWHQꢀFRQVHQWꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢃ

ꢄꢁꢃ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀLIꢀ\RXꢀKDYHꢀDQ\ꢀTXHVWLRQVꢀUHJDUGLQJꢀWKHꢀLQIRUPDWLRQꢀFRQWDLQHGꢀLQꢀWKLVꢀGRFXPHQWꢀRUꢀ5HQHVDVꢀ

(OHFWURQLFVꢀSURGXFWVꢃ

ꢍ1RWHꢄꢎ ꢊ5HQHVDVꢀ(OHFWURQLFVꢊꢀDVꢀXVHGꢀLQꢀWKLVꢀGRFXPHQWꢀPHDQVꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢀDQGꢀDOVRꢀLQFOXGHVꢀLWVꢀGLUHFWO\ꢀRUꢀLQGLUHFWO\ꢀFRQWUROOHGꢀ

VXEVLGLDULHVꢃ

ꢍ1RWHꢁꢎ ꢊ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢍVꢎꢊꢀPHDQVꢀDQ\ꢀSURGXFWꢀGHYHORSHGꢀRUꢀPDQXIDFWXUHGꢀE\ꢀRUꢀIRUꢀ5HQHVDVꢀ(OHFWURQLFVꢃ

ꢍ5HYꢃꢇꢃꢂꢏꢄꢀꢀ1RYHPEHUꢀꢁꢂꢄꢑꢎ

&RUSRUDWHꢀ+HDGTXDUWHUV

&RQWDFWꢀ,QIRUPDWLRQ

72<268ꢀ)25(6,$ꢅꢀꢆꢏꢁꢏꢁꢇꢀ7R\RVXꢅ

)RUꢀIXUWKHUꢀLQIRUPDWLRQꢀRQꢀDꢀSURGXFWꢅꢀWHFKQRORJ\ꢅꢀWKHꢀPRVWꢀXSꢏWRꢏGDWHꢀ

YHUVLRQꢀRIꢀDꢀGRFXPHQWꢅꢀRUꢀ\RXUꢀQHDUHVWꢀVDOHVꢀRIILFHꢅꢀSOHDVHꢀYLVLWꢉ

.RWRꢏNXꢅꢀ7RN\Rꢀꢄꢆꢈꢏꢂꢂꢐꢄꢅꢀ-DSDQ

Corporate Headquarters

Contact Information

ZZZꢃUHQHVDVꢃFRPꢒFRQWDFWꢒ

ZZZꢃUHQHVDVꢃFRP

TOYOSU FORESIA, 3-2-24 Toyosu,

For further information on a product, technology, the most up-to-date version

of a document, or your nearest sales office, please visit:

Koto-ku, Tokyo 135-0061, Japan

7UDGHPDUNV

www.renesas.com/contact/

www.renesas.com

5HQHVDVꢀDQGꢀWKHꢀ5HQHVDVꢀORJRꢀDUHꢀWUDGHPDUNVꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀ

&RUSRUDWLRQꢃꢀ$OOꢀWUDGHPDUNVꢀDQGꢀUHJLVWHUHGꢀWUDGHPDUNVꢀDUHꢀWKHꢀSURSHUW\ꢀ

RIꢀWKHLUꢀUHVSHFWLYHꢀRZQHUVꢃ

Trademarks

Renesas and the Renesas logo are trademarks of Renesas Electronics

Corporation. All trademarks and registered trademarks are the property of

their respective owners.

ꢀꢁꢂ20ꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢃꢀ$OOꢀULJKWVꢀUHVHUYHGꢃ


型号：	ZSSC3230BC3R
厂家：	RENESAS TECHNOLOGY CORP
描述：	Capacitive Sensor Signal Conditioner IC
文件：	总39页 (文件大小：1581K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ZSSC3230BC3R [RENESAS]

相关型号：

ZSSC3230BC5B

ZSSC3230BC6B

ZSSC3230BI1B

ZSSC3230BI2B

ZSSC3230BI3R

ZSSC3230BI3W

ZSSC3230BI5B

ZSSC3230BI6B

ZSSC3230KIT

ZSSC3240

ZSSC3240CC1B

ZSSC3240CC2B