DK2053 [RFMD]
HIGH PERFORMANCE FRACTIONAL-N SYNTHESIZER WITH INTEGRATED RF MIXER;
| 型号： | DK2053 |
| 厂家： | 
RF MICRO DEVICES |
| 描述： | HIGH PERFORMANCE FRACTIONAL-N SYNTHESIZER WITH INTEGRATED RF MIXER |
| 文件： | 总36页 (文件大小：1647K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF2053
RF2053
HIGH PERFORMANCE FRACTIONAL-N
SYNTHESIZER WITH INTEGRATED RF MIXER
Package: QFN, 32-Pin, 5mmx5mm
LO
divider
Features
Fractional-N Synthesizer
Very Fine Frequency Resolution
1.5Hz for 26MHz Reference
Synth
Frac-N
sequence
generator
300MHz to 2400MHz External
VCO Frequency Range
N
divider
On-Chip Crystal-Sustaining
Circuit With Programmable
Loading Capacitors
Phase/
freq
detector
Charge
pump
Integrated LO Buffer and LO
Divider
Ref
divider
High-Linearity RF Mixer
Mixer Input IP3 +23dBm Typ.
Functional Block Diagram
Mixer Bias Adjustable for Low
Power Operation
Product Description
Mixer Frequency Range 30MHz
The RF2053 is a low power, high performance, wideband RF frequency conversion
chip with integrated local oscillator (LO) generation and RF mixer. The RF synthe-
sizer includes an integrated fractional-N phase locked loop that can control an
external VCO to produce a low-phase noise LO signal with a very fine frequency res-
olution. The VCO output frequency can be divided by 1, 2, or 4 in the LO divider,
whose output is buffered and drives the built-in RF mixer which converts the signal
into the required frequency band. The mixer bias current can be programmed
dependent on the required performance and available supply current. The LO gen-
eration blocks have been designed to operate with external VCOs covering the fre-
quency range from 300MHz to 2400MHz. The RF mixer is very broad band and
operates from 30MHz to 2500MHz at the input and output, enabling both up and
down conversion. An external crystal of between 10MHz and 52MHz or an external
reference source of between 10MHz and 104MHz can be used with the RF2053 to
accommodate a variety of reference frequency options.
to 2500MHz
2.7V to 3.6V Power Supply
Low Current Consumption
50mA to 70mA at 3V
3-Wire Serial Interface
Applications
CATV Head-Ends
Digital TV Up/Down Converters
Digital TV Repeaters
Multi-Dwelling Units
Frequency Band Shifters
UHF/VHF Radios
All on-chip registers are controlled through a simple three-wire serial interface. The
RF2053 is designed for 2.7V to 3.6V operation for compatibility with portable, bat-
tery powered devices. It is available in a plastic 32-pin, 5mmx5mm QFN package.
Software Defined Radios
Satellite Communications
Super-Heterodyne Radios
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
RF MEMS
LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
1 of 36
RF2053
Detailed Functional Block Diagram
IP
ANA_VDD
DIG_VDD
RFIPN
RFIPP
ENBL
CONTROL
MODE
1:1
RESETB
ANA_DEC
ANA_VDD
SDATA
SCLK
ENX
RFOPP
RFOPN
SERIAL
BUS
OP
Analog
Regulator
Digital
Regulator
Serial Data Interface,
Control and Biasing
4:1
Mixer
REXT
LO Divider
/1, /2, or /4
EXTERNAL VCO
Vtune
VCOINP
VCOINN
LO Buffer
VCO Buffer
1:1
Frac-N
Sequence
Generator
N Divider
Synthesizer
Phase /
Freq
Detector
LFILT1
Charge
Pump
Vref
EXTERNAL
OP-AMP
XTALIPP
XTALIPN
Reference Oscillator
Circuitry and
Crystal Tuning
Reference Divider
/1 to /7
Pin Out
32 31 30 29 28 27 26 25
ENBL
1
2
3
4
5
6
7
8
24 RFIPP
23 RFIPN
22 ANA_VDD
21 NC
VCOINP
VCOINN
REXT
EP
ANA_DEC
LFILT1
NC
20 NC
19 DIG_VDD
18 NC
NC
17 NC
9
10 11 12 13 14 15 16
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2 of 36
DS140110
RF2053
Pin
1
Function
ENBL
Description
Ensure that the ENBL high voltage level is not greater than V . An RC low-pass filter could be used to reduce
digital noise.
DD
External VCO differential input. See note 1.
2
3
4
VCOINP
VCOINN
REXT
External VCO differential input. See note 1.
External bandgap bias resistor. Connect a 51k resistor from this pin to ground to set the bandgap reference
bias current. This could be a sensitive low frequency noise injection point.
Analog supply decoupling capacitor. Connect to analog supply and apply RF decoupling to a good quality ground
as close to the pin as possible.
5
ANA_DEC
Phase detector output. Low-frequency noise-sensitive node.
6
7
LFILT1
NC
8
NC
Mode select pin. Connect to DIG_VDD if mode switching is not required.
9
10
11
MODE
XTALIPP
XTALIPN
Reference crystal / reference oscillator input. Should be AC-coupled if an external reference is used. See note 3.
Reference crystal / reference oscillator input. Should be AC-coupled to ground if an external reference is used.
See note 3.
Connect to ground.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EP
GND
NC
NC
NC
NC
NC
NC
DIG_VDD
NC
Digital supply. Should be decoupled as close to the pin as possible.
NC
Analog supply. Should be decoupled as close to the pin as possible.
Differential input. See note 1.
ANA_VDD
RFIPN
RFIPP
NC
Differential input. See note 1.
NC
Differential output. See note 2.
RFOPN
RFOPP
RESETB
ENX
SCLK
SDATA
Exposed pad
Differential output. See note 2.
Chip reset (active low). Connect to DIG_VDD if external reset is not required.
Serial interface select (active low). An RC low-pass filter could be used to reduce digital noise.
Serial interface clock. An RC low-pass filter could be used to reduce digital noise.
Serial interface data. An RC low-pass filter could be used to reduce digital noise.
Connect to ground. This is the ground reference for the circuit. All decoupling should be connected here through
low impedance paths.
Note 1: The signal should be connected to this pin such that DC current cannot flow into or out of the chip, either by using AC
coupling capacitors or by use of a transformer (see evaluation board schematic).
Note 2: DC current needs to flow from ANA_VDD into this pin, either through an RF inductor, or transformer (see evaluation
board schematic).
Note 3: Alternatively an external reference can be AC-coupled to pin 11 XTALIPN, and pin 10 XTALIPP decoupled to ground. This
may make PCB routing simpler.
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DS140110
3 of 36
RF2053
Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage (V
)
-0.5 to +3.6
V
DD
Input Voltage (V ), any Pin
IN
-0.3 to V +0.3
DD
V
RF/IF Mixer Input Power
+15
dBm
°C
Operating Temperature Range
Storage Temperature Range
-40 to +85
-65 to +150
°C
Specification
Parameter
Unit
Condition
Min.
Typ.
Max.
ESD Requirements
Human Body Model
General
2000
1000
V
V
RF Pins
Machine Model
General
200
100
V
V
RF Pins
Operating Conditions
Supply Voltage (V
)
2.7
-40
3.0
3.6
V
DD
Temperature (T
)
+85
°C
OP
V
=Supply to DIG_VDD pin
Logic Inputs/Outputs
Input Low Voltage
DD
-0.3
+0.5
V
V
Input High Voltage
V
1.5
V
DD
DD /
Input Low Current
Input High Current
-10
+10
+10
uA
uA
Input=0V
Input=V
-10
0
DD
Output Low Voltage
Output High Voltage
0.2*V
V
V
DD
0.8*V
10
V
DD
DD
Load Resistance
Load Capacitance
Static
k
20
pF
Programmable Supply Current
(I
)
DD
Low Current Setting
High Linearity Setting
50
70
3
mA
mA
mA
A
Standby
Reference oscillator and bandgap only.
ENBL=0 and REF_STBY=0
Power Down Current
Mixer
140
Mixer output driving 4:1 balun.
Gain
-2
dB
Not including balun losses.
Noise Figure
Low Current Setting
High Linearity Setting
9.5
12
dB
dB
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4 of 36
DS140110
RF2053
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Mixer, cont.
IIP3
Low Current Setting
High Linearity Setting
+12
+23
dBm
dBm
Pin1dB
Low Current Setting
+2
dBm
dBm
MHz
dB
High Linearity Setting
RF and IF Port Frequency Range
Mixer Input Return Loss
+12
30
2500
10
-3
100 differential
Voltage Controlled Oscillator
Differential Input
External VCO Input Frequency
External VCO Input Level
300
-6
2400
0
MHz
dBm
Reference Oscillator
Xtal Frequency
10
10
1
52
104
7
MHz
MHz
External Reference Frequency
Reference Divider Ratio
External Reference Input Level
500
800
1500
mV
AC-coupled
P-P
Local Oscillator
Synthesizer Output Frequency
Phase Detector Frequency
75
2400
52
MHz
MHz
At LO divider output
Closed Loop Phase-Noise at 1kHz
Offset
26MHz phase detector frequency
26MHz phase detector frequency
2GHz LO Frequency
1GHz LO Frequency
500MHz LO Frequency
-85
-91
-97
dBc/Hz
dBc/Hz
dBc/Hz
Closed Loop Phase-Noise at
10kHz Offset
2GHz LO Frequency
1GHz LO Frequency
-90
-95
dBc/Hz
dBc/Hz
dBc/Hz
500MHz LO Frequency
Charge Pump
-102
Charge Pump Current
Charge Pump Output Voltage
120
240
A
+0.7
+1.1
+1.5
V
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DS140110
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RF2053
Typical Performance Characteristics for the RF2053 synthesizer
V
DD=3V, TA=25°C, as measured on RF2053 evaluation board, Phase Detector Frequency=26MHz.
Phase Noise of RF2053 and UMS-2150-R16 VCO
(Wideband EVB)
Phase Noise of RF2053 and UMX-236-D16 VCO
(NarrowbandEVB) at 1660MHz
-60.0
-70.0
-80.0
-90.0
-60.0
-70.0
-80.0
-90.0
-100.0
Phase
Noise
Phase
Noise -100.0
(dBc/Hz)
(dBc/Hz)
-110.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
-120.0
-130.0
-140.0
-150.0
-160.0
950MHz
1250MHz
1550MHz
1850MHz
2150MHz
Icp = 011111
Icp = 111111
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
Offset Frequency (kHz)
Offset Frequency (kHz)
Synthesizer Output Phase Noise Floor at
10kHz Offset versus Phase DetectorFrequency
Synthesizer Output Phase Noise Floor at
1kHz Offset versus Phase Detector Frequency
-70.0
-80.0
-90.0
-60.0
-70.0
-80.0
2GHz
1GHz
0.5GHz
Phase
Noise
(dBc/Hz)
Phase
Noise
(dBc/Hz)
-100.0
-110.0
-120.0
-90.0
2GHz
-100.0
-110.0
1GHz
0.5GHz
10
20
30
40
50
10
20
30
40
50
Phase Detector Frequency (MHz)
Phase Detector Frequency (MHz)
Typical Performance Characteristics for the RF2053
Operating Current versus Temperature and
Supply Voltage
80.0
75.0
70.0
65.0
60.0
55.0
50.0
45.0
40.0
Supply
Current
(mA)
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
001
010
011
100
101
Mixer Bias Current Setting (MIX2_IDD)
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6 of 36
DS140110
RF2053
Typical Performance Characteristics for the RF2053 mixer
V
DD=3V, TA=25°C, unless stated, as measured on RF2053 wideband evaluation board, Phase Detector Frequency=26MHz.
Gain versus Temperatureand Supply Voltage
RF2053 Mixer Conversion Gain
(Excluding losses in PCB and Baluns)
IF Output = 100MHz & LO = RF + IF
0.0
-1.0
0.0
-0.5
-2.0
2.7V
3.0V
3.6V
-3.0
-4.0
-1.0
Gain
(dB) -1.5
Conversion
Gain (dB)-5.0
-6.0
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
-7.0
-8.0
-2.0
-2.5
-3.0
-9.0
-10.0
250
500
750
1000
1250
1500
1750
2000
2250
-40
-20
0
20
40
60
80
100
RF Input Frequency (MHz)
Temperature (°C)
Mixer Noise Figureversus RF Input Frequency
IF = 100MHz, +27Deg C and +3.0V Supply
Mixer Noise Figureversus Temperature& Voltage
IF = 100MHz & MIX2 _IDD = 001
14.0
12.0
14.0
12.0
10.0
8.0
10.0
Noise
Figure
(dB)
Noise
Figure
(dB)
8.0
-40DegC, +2.7V
-40DegC, +3.0V
-40degC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
6.0
4.0
2.0
0.0
6.0
MIX2_IDD = 001
MIX2_IDD = 010
MIX2_IDD = 011
MIX2_IDD = 100
MIX2_IDD = 101
4.0
2.0
0.0
250
500
750
1000
1250
1500
1750
250
500
750
1000
1250
1500
1750
RF Input Frequency (MHz)
RF Input Frequency (MHz)
Mixer Input IP3 versus RF Input Frequency
IF = 100MHz & LO = RF - IF
NF versus Temperatureand SupplyVoltage
(Low Noise Mode MIX2_IDD=001)
+27DegC and +3.0V Supply
11.0
30.0
2.7V
3.0V
3.6V
10.5
10.0
9.5
25.0
20.0
Input IP3
(dBm)
NF
15.0
(dB)
10.0
5.0
9.0
MIX2_IDD = 001
MIX2_IDD = 010
MIX2_IDD = 011
MIX2_IDD = 100
MIX2_IDD = 101
8.5
0.0
8.0
250
500
750
1000
1250
1500
1750
2000
2250
-40
-20
0
20
40
60
80
100
RF Input Frequency (MHz)
Temperature (°C)
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DS140110
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RF2053
Typical Performance Characteristics for the RF2053 mixer
V
DD=3V, TA=25°C, unless stated, as measured on RF2053 wideband evaluation board, Phase Detector Frequency=26MHz
Mixer Input IP3 versus Temperature& Voltage
RF Input Frequency = 2000MHz & IF = 100MHz
Mixer Input IP3 versus Temperature& Voltage
RF Input Frequency = 1000MHz& IF = 100MHz
30.0
25.0
20.0
15.0
10.0
5.0
30.0
25.0
20.0
15.0
10.0
5.0
Input IP3
(dBm)
Input IP3
(dBm)
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
0.0
0.0
001
010
011
100
101
001
010
011
100
101
Mixer Bias Current Setting (MIX2_IDD)
Mixer Bias Current Setting (MIX2_IDD)
MixerInput Power for 1dB Compression
versus Temperature& Voltage
IF = 100MHz & MIX2_IDD = 101
Mixer Input Power for 1dB Compression
IF = 100MHz, +27DegC & 3.0V Supply
16.0
16.0
14.0
12.0
10.0
8.0
14.0
12.0
10.0
8.0
Pin
1dB
(dBm)
Pin 1dB
(dBm)
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
MIX2_IDD = 001
6.0
MIX2_IDD = 010
MIX2_IDD = 011
MIX2_IDD = 100
MIX2_IDD = 101
4.0
2.0
0.0
6.0
250
500
750
1000
1250
1500
1750
2000
2250
250
500
750
1000
1250
1500
1750
2000
2250
RF Input Frequency (MHz)
RF Input Frequency (MHz)
Mixer RF Input to IF Output Isolation
versus Temperatureand Supply Voltage
IF = 100MHz & LO = RF + IF
LO Leakage in dBm at Mixer IF Output
versus Temperatureand Supply Voltage
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
70.0
60.0
50.0
RF to
IF Isolation
(dB)
LO
Leakage
(dBm)
-40DegC, +2.7V
-40DegC, +3.0V
-40DegC, +3.6V
+27DegC, +2.7V
+27DegC, +3.0V
+27DegC, +3.6V
+85DegC, +2.7V
+85DegC, +3.0V
+85DegC, +3.6V
40.0
30.0
20.0
10.0
0.0
0
500
1000
1500
2000
2500
250
500
750
1000
1250
1500
1750
2000
2250
RF Input Frequency (MHz)
LO Frequency (MHz)
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DS140110
RF2053
Detailed Description
The RF2053 is a wideband RF frequency converter chip which includes a fractional-N phase-locked loop, a crystal oscillator cir-
cuit, an LO buffer, and an RF mixer. The PLL operates with an external VCO. Synthesizer programming, device configuration and
control are achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a sim-
ple three-wire serial interface.
VCO
The RF2053 has been designed for use with an external VCO. The VCO inputs on pins 2 and 3 are differential.
In order to route the VCO input through buffers to the PLL divide circuits then CFG1:EXT_VCO must be set high and the VCO
control word must be set to VCO3, PLL2x0:P2_VCOSEL=10.
The course tuning calibration (CT_CAL) which is not used by the RF2053 should be disabled in order to minimize the PLL lock
time. The VCO signal can be divided by 1, 2, or 4 in the LO divider circuit. The LO divide ratio is set by the PLL2x0:P2_LODIV
control words.
For applications where the required LO frequency is above 2GHz it is recommended that the LO buffer current be increased by
setting CFG5:LO2_I to 1100 (hex value C).
Fractional-N PLL
The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the external VCO. The PLL is intended
to use a reference frequency signal of 10MHz to 104MHz. A reference divider (divide by 1 to divide by 7) is supplied and
should be programmed to limit the frequency at the phase detector to a maximum of 52MHz. The reference divider bypass is
controlled by bit CLK_DIV_BYP, set low to enable the reference divider and set high for divider bypass (divide by 1). The remain-
ing three bits CLK_DIV<15:13> set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is
enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RF2053 the default programming bank is PLL2, selected by setting the MODE pin high.
The PLL will lock the VCO to the frequency FVCO according to:
FVCO=NEFF*FOSC/R
where NEFF is the programmed fractional N divider value, FOSC is the reference input frequency, and R is the programmed R
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, NEFF
:
NEFF=FVCO*R/FOSC
N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224=16777216.
Example: VCO operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is:
N
EFF=FVCO *R / FOSC=2220 *1 / 23.92=92.80936454895.
The N value is set to 92, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied
by 224
:
NUM=0.80936454895 * 224 =13,578,884.
Converting N and NUM into binary results in the following:
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DS140110
9 of 36
RF2053
N=0 0101 1100
NUM=1100 1111 0011 0010 1000 0100
So the registers would be programmed:
P2_N=0 0101 1100
P2_NUM_MSB=1100 1111 0011 0010
P2_NUM_LSB=1000 0100
The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode. The minimum step size is FOSC/R*224. Thus
for a 23.92MHz reference, the frequency step size would be 1.4Hz. The minimum reference frequency that can be used is sim-
ply the maximum VCO frequency required divided by 511. For example for a VCO frequency of 2400MHz, the minimum refer-
ence frequency, is 2400/511, 4.697MHz (approx).
Phase Detector and Charge Pump
The chip provides a current output to drive an external loop filter. An external low noise operational amplifier can be used to
design an active loop filter or a passive design can be implemented. This depends on the tuning range of the external VCO. The
maximum charge pump output current is set by the value contained in the P2_CP_DEF field and CP_LO_I.
In the default state (P2_CP_DEF=31 and CP_LO_I=0) the charge pump current (ICPset) is 120uA. If CP_LO_I is set to 1 this
current is reduced to 30uA. Note that lowest phase noise within the loop bandwidth is achieved with the maximum charge
pump current.
The charge pump current can be altered by changing the value of P2_CP_DEF. The charge pump current is defined as:
ICP= ICPset*CP_DEF / 31
Changing the charge pump current will vary the loop filter response, higher current corresponding to a wider loop bandwidth.
The phase detector will operate with a maximum input frequency of 52MHz.
The loop filter calibration (KV_CAL) is not used by the RF2053 and is disabled by default.
Loop Filter
The PLL may be designed to use an active or a passive loop filter as required. The active loop filter uses an external low noise
op-amp. The CFG1:LF_ACT bit is set low in both cases so that the internal op-amp is disabled and a high impedance is pre-
sented to the LFILT1 pin. The RF205x Programming Tool software can assist with loop filter designs. Because the op-amp is
used in an inverting configuration in active mode, when the passive loop filter mode is selected the phase-detector polarity
should be inverted. For active mode, CFG1:PDP=1, for passive mode, CFG1:PDP=0.
+1.1V
+
RF2053
Charge Pump
Typical active
loop filter
-
To VCO tuning
LFILT1
The charge pump output voltage compliance range is typically +0.7V to +1.5V. For applications using a passive loop filter the
required VCO tuning voltage must fall within this voltage range under all conditions. When using an external op-amp as an inte-
grator for the loop filter, as shown above, the non-inverting terminal should be referenced to +1.1V. This holds the charge
pump output at this voltage in the center of its compliance range. The op-amp power supplies must be adequate to provide the
necessary VCO tuning voltage.
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DS140110
RF2053
Crystal Oscillator
The PLL may be used with an external reference source, or its own crystal oscillator. If an external source (such as a TCXO) is
being used it should be AC-coupled into one of the XO inputs, and the other input should be AC-coupled to ground.
A crystal oscillator typically takes many milliseconds to settle, and so for applications requiring rapid pulsed operation of the
PLL (such as a TDMA system, or Rx/Tx half-duplex system) it is necessary to keep the XO running between bursts. However,
when the PLL is used less frequently, it is desirable to turn off the XO to minimize current draw. The REFSTBY register is pro-
vided to allow for either mode of operation. If REFSTBY is programmed high, the XO will continue to run even when ENBL is
asserted low. Thus the XO will be stable and a clock is immediately available when ENBL is asserted high, allowing the chip to
assume normal operation. On cold start, or if REFSTBY is programmed low, the XO will need a warm-up period before it can pro-
vide a stable clock. The length of this warm-up period will be dependant on the crystal characteristics.
The crystal oscillator circuit contains internal loading capacitors. No external loading capacitors are required, dependant on
the crystal loading specification. The internal loading capacitors are a combination of fixed capacitance, and an array of
switched capacitors. The switched capacitors can be used to tune the crystal oscillator onto the required center frequency and
minimize frequency error. The PCB stray capacitance and oscillator input and output capacitance will also contribute to the
crystal’s total load capacitance. The register settings in the CFG4 register for the switched capacitors are as follows:
• Coarse Tune XO_CT (4 bits) 15*0.55pF, default 0100
• Fine Step XO_CR_S (1 bit) 1*0.25pF, default 0
The on chip fixed capacitance is approximately 4.2pF.
Wideband Mixer
The RF2053 includes a wideband, double-balanced Gilbert cell mixer. It supports RF/IF frequencies of 30MHz to 2500MHz.
The mixer has an input port and an output port that can be used for either IF or RF, i.e. for up conversion or down conversion.
The mixer current can be programmed to between 15mA and 35mA depending on linearity requirements, using the MIX-
2_IDD<3:0> word in the CFG2 register. The majority of the mixer current is sourced through the output pins via either a centre-
tapped balun or an RF choke in the external matching circuitry to the supply.
The RF mixer input and output ports are differential and require simple matching circuits optimized to the specific application
frequencies. A conversion gain of approximately -3dB to 0dB is achieved with 100 differential input impedance, and the out-
puts driving 200 differential load impedance. Increasing the mixer output load increases the conversion gain.
The mixer has a broadband common gate input. The input impedance is dominated by the resistance set by the mixer 1/gm
term, which is inversely proportional to the mixer current setting. The resistance will be approximately 85 at the default mixer
current setting (100). There is also some shunt capacitance at the mixer input, and the inductance of the bond wires to con-
sider at higher frequencies.
The mixer output is high impedance, consisting of a resistance of approximately 2k in parallel with some capacitance. The
mixer output does not need to be matched as such, just to see a resistive load. A higher resistance load will give higher output
voltage and gain. A shunt inductor can be used to resonate with the mixer output capacitance at the frequency of interest. This
inductor may not be required at lower frequencies where the impedance of the output capacitance is less significant. At higher
output frequencies the inductance of the bond wires becomes more significant.
For more information about the mixer port impedances and matching, please refer to the RF205x Family Application Note on
Matching Circuits and Baluns.
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DS140110
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RF2053
General Programming Information
Serial Interface
All on-chip registers in the RF2053 are programmed using a 3-wire serial bus which supports both write and read operations.
Synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls.
Certain functions and operations require the use of hardware controls via the ENBL, MODE, and RESETB pins in addition to
programming via the serial bus. For most applications the MODE pin can be held high.
3-wire bus
ENX
SCLK
SDATA
MCU
RF2053
ENBL
RESETB
MODE
Hardware
Controls
Serial Data Timing Characteristics
RESETB
t1
ENX
t3
t5
SCLK
SDATA
ENBL
t2
t6
t4
t7
X
t8
t9
X
X
X
X
X
X
X
Reset
chip
Initial programming of device
Programming
updates
Parameter
Description
Reset delay
Time
>5ns
>5ns
>5ns
>5ns
>5ns
>5ns
>5ns
>0ns
>0ns
t1
t2
t3
t4
t5
t6
t7
t8
t9
Programming setup time
Programming hold time
ENX setup time
ENX hold time
Data setup time
Data hold time
ENBL setup time
ENBL hold time
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DS140110
RF2053
Write
ENX
SCLK
SDATA
X
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Initially ENX is high and SDATA is high impedance. The write operation begins with the controller starting SCLK. On the first fall-
ing edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and
the third rising edge is used to define whether the operation will be a write or a read operation. In write mode the baseband will
drive SDATA for the entire telegram. RF2053 will read the data bit on the rising edge of SCLK.
The next 7 data bits are the register address, MSB first. This is followed by the payload of 16 data bits for a total write mode
transfer of 24 bits. Data is latched into RF2053 on the last rising edge of SCLK (after ENX is asserted high).
For more information, please refer to the timing diagram on page 12.
The maximum clock speed for a register write is 19.2MHz. A register write therefore takes approximately 1.3us. The data is
latched on the rising edge of the clock. The datagram consists of a single start bit followed by a ‘0’ (to indicate a write opera-
tion). This is then followed by a seven bit address and a sixteen bit data word.
Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising
clock edge before the ENX line is set low to ensure the address/data are read correctly.
Read
ENX
SCLK
X
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDATA
Initially ENX is high and SDATA is high impedance. The read operation begins with the controller starting SCLK. The controller is
in control of the SDATA line during the address write operation. On the first falling edge of SCLK the baseband asserts ENX low.
The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the
operation will be a write or a read operation. In read mode the baseband will drive SDATA for the address portion of the tele-
gram, and then control will be handed over to RF2053 for the data portion. RF2053 will read the data bits of the address on
the rising edge of SCLK. After the address has been written, control of the SDATA line is handed over to RF2053. One and a half
clocks are reserved for turn-around, and then the data bits are presented by RF2053. The data is set up on the rising edge of
SCLK, and the controller latches the data on the falling edge of SCLK. At the end of the data transmission, RF2053 will release
control of the SDATA line, and the controller asserts ENX high. The SDATA port on RF2053 transitions from high impedance to
low impedance on the first rising edge of the data portion of the transaction (for example, 3 rising edges after the last address
bit has been read), so the controller chip should be presenting a high impedance by that time.
For more information, please refer to the timing diagram on page 12.
The maximum clock speed for a register read is 19.2MHz. A register read therefore takes approximately 1.4us. The address is
latched on the rising edge of the clock and the data output on the falling edge. The datagram consists of a single start bit fol-
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DS140110
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RF2053
lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit
data word representing the register content is presented to the receiver.
Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising
clock edge before the ENX line is set low to ensure the address is read correctly.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
ENBL Pin
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the PLL to lock.
ENBL Pin
Low
REFSTBY Bit
XO and Bias Block
Analogue Block
Digital Block
0
1
0
1
Off
On
On
On
Off
Off
On
On
On
On
On
On
Low
High
High
Every time the frequency of the synthesizer is re-programmed, ENBL has to be taken high to initiate PLL locking.
RESETB Pin
The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The
device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to
the positive supply.
MODE Pin
The MODE pin controls which PLL programming register bank is active.
For normal operation of the RF2053 the MODE pin should be set high to select the default PLL2 programming registers. It is
possible to set the FULLD bit in the CFG1 register high. This allows the MODE pin to select either PLL1 register bank
(MODE=low) or PLL2 register bank (MODE=high). This may be useful for some applications where two LO frequencies can be
programmed into the registers then the MODE pin used to toggle between them. The ENBL pin will also need to be cycled to re-
lock the synthesizer for each frequency.
ENBL
t1
MODE
t2
Parameter
Description
MODE setup time
MODE hold time
Time
>5ns
>5ns
t1
t2
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DS140110
RF2053
Programming the RF2053
The figure below shows an overview of the device programming.
Device off
Apply power to the device.
Apply power
Reset device
Ensure the device is set into a known and correct
state.
1
2
3
4
Set-up device
operation
To use the device it will be necessary to program the
registers with the desired contents to achieve the
required operating characteristics.
Set calibration
mode
See following sections for details.
Set operating
frequencies
When programming is complete the device can be
enabled.
ENABLE device
Note: The set-up processes 1 to 2, 2 to 3, and 3 to 4 are explained further below.
Additional information on device use and programming can be found on the RF205x family page of the RFMD web site
(http://www.rfmd.com/rf205x). The following documents may be particularly helpful:
• RF205x Frequency Synthesizer User Guide
• RF205x Calibration User Guide
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RF2053
Start-up
When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high approximately 500ecs.
before ENBL is taken high. This is to allow the XO to settle and will depend on XO characteristics. After taking ENBL high there
is typically 20usecs for the PLL state machine and charge pump to initialize, the VCO warm-up state, before PLL locking starts.
The time spent in the VCO warm-up state is set by CFG1:TVCO, which should be set to 00111 when using a 26MHz clock. Fol-
lowing the warm-up period there will be the additional time taken for the PLL to settle to the required frequency. All of these
timings will be dependent upon application specific factors such as loop filter bandwidth, reference clock frequency, and XO
characteristics. The fastest turn-on and lock time will be obtained by leaving REFSTBY asserted high, disabling all calibration
routines (always the case for the RF2053), minimizing the VCO warm-up time, and setting the PLL loop bandwidth as wide as
possible.
The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting
the RESETB pin low for at least 100ns.
Setting Up Device Operation
The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is
achieved as follows.
Set-up device
operation
1
To set up RF2053 operation w ith an external VCO it is
necessary to set the EXT_VCO bit in CFG 1 register high
and to alw ays select VCO3 to route the VCO input
through to the synthesizer. The LF_ACT bit in CFG 1
Program
EXT_VCO=1
P2_VCOSEL=10
LF_ACT=0
register should be set to
norm ally used in the loop filter.
0 as an external op-am p is
W hen setting up the device it is necessary to decide if
an active or passive loop filter w ill be used in the
phase locked loop. Set the phase detector polarity bit
in CFG 1 since the active filter inverts the loop filter
voltage. Norm ally active loop filter w ith an external op-
Active loop
filter?
N o
PDP set to 0
am p is used w ith the RF2053, so set PD P
default setting.
= 1, the
D efault
The m ixer linearity setting is then selected. The default
value is w ith being the low est setting and the
highest. The M IX2_ID D bits are located in the CFG 2
register.
M ixer
linearity
Program
M IX2_IDD
4
1
5
Internal
capacitors
used to set
Xtal load
The internal crystal loading capacitors are also
program m ed to present the correct load to the crystal.
The capacitance internal to the chip can be varied
from 8-16pF in 0.25pF steps (default=10pF). The
reference divider m ust also be set to determ ine the
phase detector frequency (default=1). These bits are
located in the CFG 4 register.
Program XO_CT,
XO_CR_S and
CLK_D IV
Set-up com plete
2
Three registers need to be written, taking 3.9us at the maximum clock speed.
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DS140110
RF2053
Disabling Calibration
The VCO coarse tune calibration should be disabled as it is not used on the RF5203. The loop filter calibration, also unused, is
disabled by default.
Set calibration
2
mode
P2_CT_EN
Set to 00
Disable coarse tune calibration. Not required for the
RF2053.
The loop filter (Kv) calibration is also not required for
the RF2053. The default setting is for the loop filter
calibration to be disabled so no programming is
required for this step.
Disable loop
filter calibration
Default
Operating mode set
3
One register needs to be written taking 1.3us at maximum clock speed. Since it is necessary to program this register when set-
ting the operating frequency (see next section) this operation usually carries no overhead.
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RF2053
Setting The Operating Frequency
Setting the operating frequency of the device requires a number of registers to be programmed.
Set operating
frequencies
3
When programming the operating frequency it is
necessary to select the appropriate LODIV value,
located in the PLL2x0 register. If the LO frequency is
above 2GHz the LO path current (CFG5) should be set
Program P2_LODIV
and LO2_I
to 0xC.
Program
P2_N
The integer part of the PLL division ratio is
programmed into the PLL2x3 register.
Program
P2_NUM_MSB
The MSB of the fractional part of the synthesizer PLL
divider value is programmed into the PLL2x1 register.
The LSB of the fractional part of the synthesizer PLL
divider value is programmed into the PLL2x2 register.
Program
P2_NUM_LSB
Frequency
programmed
4
A total of four registers must be programmed to set the device operating frequency. This will take 5.2us for each path at maxi-
mum clock speed.
To change the frequency of the VCO it will be necessary to repeat these operations. However, if the frequency shift is small it
may not be necessary to reprogram all the bits reducing the number of register writes to three.
For an example on how to determine the integer and fractional parts of the synthesizer PLL division ratio please refer to the
detailed description of the PLL on page 9.
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DS140110
RF2053
Programming Registers
Register Map Diagram
Data
Reg.
R/W
Add
Name
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
PLL1x0
15
14
13 12 11 10
TVCO
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00
01
02
03
04
05
08
LD_EN LD_LEV
MIX1_IDD
TKV1
PDP LF_ACT
CPL
Res
Res
CT_POL Res EXT_VCO FULLD CP_LO_I
MIX1_VB MIX2_IDD
TKV2
MIX2_VB
KV_RNG NBR_CT_AVG NBR_KV_AVG
FLL_FACT CT_CPOLREFSTBY
CLK_DIV_BYPASS
LO1_I
XO_CT
XO_I2 XO_I1 XO_CR_S
TCT
T_PH_ALGN
Res
LO2_I
SU_WAIT
P1_VCOSEL P1_CT_E P1_KV_E P1_LO-
Res
P1_CP_DEF
N
N
DIV
PLL1x1
PLL1x2
PLL1x3
PLL1x4
PLL1x5
PLL2x0
R/W
R/W
R/W
R/W
R/W
R/W
09
0A
0B
0C
0D
10
P1_NUM_MSB
P1_NUM_LSB
P1_N
P1_CT_DEF
Res
Res
Res
P1_CT_GAIN
Res
P1_VCOI
P1_KV_GAIN
P1_CT_V
P2_CP_DEF
P1_DN
P1_N_PHS_ADJ
P2_KV__E
P2_VCOSEL P2_CT_E
P2_LO-
DIV
Res
N
N
PLL2x1
PLL2x2
PLL2x3
PLL2x4
PLL2x5
GPO
R/W
R/W
R/W
R/W
R/W
R/W
11
12
13
14
15
18
P2_NUM_MSB
P2_NUM_LSB
P2_N
P2_CT_DEF
Res
Res
Res
P2_VCOI
P2_DN
P2_CT_GAIN
Res
P2_KV_GAIN
P2_CT_V
P2_N_PHS_ADJ
Res
P1_G- Res P1_ P1_
Res
P2_G-
PO1
Res
P2_G- P2_
Res
PO1
GPO GPO
PO3 GPO
4
3
4
CHIPREV
RB1
R
R
R
R
R
19
1C
1D
1E
1F
PARTNO
REVNO
LOCK
TEN
CT_CAL
V0_CAL
RSM_STATE
TMUX
CP_CAL
Res
RB2
V1_CAL
Res
DACTEST
RB3
TEST
CPU CPD FNZ LDO TSEL Res
Res
_BY
P
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RF2053
CFG1 (OOh) - Operational Configuration Parameters
#
15
14
13
12
11
10
9
Bit Name
LD_EN
Default
Function
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
9
Enable lock detector circuitry
LD_LEV
Modify lock range for lock detector
TVCO(4:0)
VCO warm-up time=TVCO/(F *256)
REF
1
C
0
8
PDP
Phase detector polarity: 0=positive, 1=negative
Active loop filter enable, 1=Active 0=Passive
7
LF_ACT
CPL(1:0)
6
Charge pump leakage current: 00=no leakage, 01=low leakage, 10=mid leakage, 11=high
leakage
5
4
CT_POL
Polarity of VCO coarse-tune word: 0=positive, 1=negative
3
2
EXT_VCO
FULLD
Set to 1=external VCO (VCO3 disabled, KV_CAL and CT_CAL must be disabled)
1
0=Half duplex, mixer is enabled according to MODE pin, 1=Full duplex, both mixers enabled.
For RF2053 setting FULLD high gives access to both PLL register banks using MODE pin.
0
CP_LO_I
0
0=High charge pump current, 1=low charge pump current
CFG2 (O1h) - Mixer Bias and PLL Calibration
#
15
14
13
12
11
10
9
Bit Name
MIX1_IDD
Default
Function
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
0
8
This register is not used for the RF2053.
MIX1_VB
This register is not used for the RF2053.
C
5
8
MIX2_IDD
Mixer 2 current setting: 000=0mA to 111=35mA in 5mA steps
Mixer 2 voltage bias
8
7
MIX2_VB
6
5
4
KV_RNG
Sets accuracy of voltage measurement during KV calibration: 0=8bits, 1=9bits
Number of averages during CT cal
3
NBR_CT_AVG
2
1
NBR_KV_AVG
Number of averages during KV cal
0
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DS140110
RF2053
CFG3 (O2h) - PLL Calibration
#
15
14
13
12
11
10
9
Bit Name
TKV1
Default
Function
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Settling time for first measurement in LO KV compensation
TKV2
4
0
4
Settling time for second measurement in LO KV compensation
8
7
6
5
4
3
FLL_FACT
Default setting 01. Needs to be set to 00 for N<28. This case can arise when higher phase
detector frequencies are used.
2
1
CT_CPOL
REFSTBY
0
Reference oscillator standby mode 0=XO is off in standby mode, 1=XO is on in standby mode
CFG4 (O3h) - Crystal Oscillator and Reference Divider
#
15
14
13
12
11
10
9
Bit Name
CLK_DIV
Default
Function
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Reference divider, divide by 2 (010) to 7 (111) when reference divider is enabled
CLK_DIV_BYPASS
XO_CT
Reference divider enabled=0, divider bypass (divide by 1)=1
8
0
F
Crystal oscillator coarse tune (approximately 0.5pF steps from 8pF to 16pF)
8
7
XO_I2
XO_I1
XO_CR_S
TCT
Crystal oscillator current setting
6
5
Crystal oscillator additional fixed capacitance (approximately 0.25pF)
Duration of coarse tune acquisition
4
3
2
1
0
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support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
21 of 36
RF2053
CFG5 (O4h) - LO Bias
#
15
14
13
12
11
10
9
Bit Name
LO1_I
Default
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Local oscillator Path1 current setting
Local oscillator Path2 current setting
Phase alignment timer
LO2_I
0
0
4
8
7
T_PH_ALGN
6
5
4
3
2
1
0
CFG6 (O5h) - Start-up Timer
#
15
14
13
12
11
10
9
Bit Name
SU_WAIT
Default
Function
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Crystal oscillator settling timer.
1
0
0
8
7
6
5
4
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
22 of 36
DS140110
RF2053
PLL1x0 (08h) - VCO, LO Divider and Calibration Select
#
15
14
13
12
11
10
9
Bit Name
P1_VCOSEL
Default
Function
0
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
7
Path 1 VCO band select: 00=VCO1, 01=VCO2, 10=VCO3, 11=Reserved
Always set to 10 for VCO3.
P1_CT_EN
P1_KV_EN
P1_LODIV
Path 1 VCO coarse tune: 00=disabled, 11=enabled
Set to 00 to disable VCO coarse tune.
1
1
F
Path 1 VCO tuning gain calibration: 00=disabled, 11=enabled
Set to 00 to disable calibration.
Path 1 local oscillator divider: 00=divide by 1, 01=divide by 2, 10=divide by 4, 11=reserved
8
7
6
5
P1_CP_DEF
Charge pump current setting
If P1_KV_EN=11 this value sets charge pump current during KV compensation only
4
3
2
1
0
PLL1x1 (09h) - MSB of Fractional Divider Ratio
#
15
14
13
12
11
10
9
Bit Name
P1_NUM_MSB
Default
Function
0
1
1
0
0
0
1
0
0
1
1
1
0
1
1
0
6
Path 1 VCO divider numerator value, most significant 16 bits
2
7
6
8
7
6
5
4
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
23 of 36
RF2053
PLL1x2 (0Ah) - LSB of Fractional Divider Ratio and CT Default
#
15
14
13
12
11
10
9
Bit Name
P1_NUM_LSB
Default
Function
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
2
Path 1 VCO divider numerator value, least significant 8 bits
7
7
E
8
7
P1_CT_DEF
Path 1 VCO coarse tuning value, not required for RF2053.
6
5
4
3
2
1
0
PLL1x3 (0Bh) - Integer Divider Ratio and VCO Current
#
15
14
13
12
11
10
9
Bit Name
P1_N
Default
Function
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
0
2
Path 1 VCO divider integer value
3
0
2
8
7
6
5
4
3
2
P1_VCOI
Path 1 VCO bias setting: 000=minimum value, 111=maximum value
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
24 of 36
DS140110
RF2053
PLL1x4 (0Ch) - Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P1_DN
Default
Function
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
Path 1 frequency step size used in VCO tuning gain calibration
7
E
4
8
7
6
P1_CT_GAIN
P1_KV_GAIN
Path 1 coarse tuning calibration gain
Path 1 VCO tuning gain calibration gain
5
4
3
2
1
0
PLL1x5 (0Dh) - More Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P1_N_PHS_ADJ
Default
Function
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Path 1 frequency step size used in VCO tuning gain calibration
0
1
0
8
7
6
5
4
P1_CT_V
Path 1 course tuning voltage setting when performing course tuning calibration. Not used by
RF2053.
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
25 of 36
RF2053
PLL2x0 (10h) - VCO, LO Divider and Calibration Select
#
15
14
13
12
11
10
9
Bit Name
P2_VCOSEL
Default
Function
0
1
1
1
0
0
0
1
7
Path 2 VCO band select: 00=VCO1, 01=VCO2, 10=VCO3, 11=Reserved.
Always set to 10 for VCO3.
P2_CT_EN
P2_KV_EN
P2_LODIV
Path 2 VCO coarse tune: 00=disabled, 11=enabled.
Set to 00 to disable VCO coarse tune.
1
1
F
Path 2 VCO tuning gain calibration: 00=disabled, 11=enabled.
Set to 00 to disable calibration.
Path 2 local oscillator divider: 00=divide by 1, 01=divide by 2, 10=divide by 4, 11=reserved
8
7
6
5
P2_CP_DEF
0
1
1
1
1
1
Charge pump current setting.
If P2_KV_EN=11 this value sets charge pump current during KV compensation only
4
3
2
1
0
PLL2x1 (11h) - MSB of Fractional Divider Ratio
#
15
14
13
12
11
10
9
Bit Name
P2_NUM_MSB
Default
Function
0
1
1
0
0
0
1
0
0
1
1
1
0
1
1
0
6
Path 2 VCO divider numerator value, most significant 16 bits
2
7
6
8
7
6
5
4
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
26 of 36
DS140110
RF2053
PLL2x2 (12h) - LSB of Fractional Divider Ratio and CT Default
#
15
14
13
12
11
10
9
Bit Name
P2_NUM_LSB
Default
Function
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
2
Path 2 VCO divider numerator value, least significant 8 bits.
7
7
E
8
7
P2_CT_DEF
Path 2 VCO coarse tuning value. Not required for RF2053.
6
5
4
3
2
1
0
PLL2x3 (13h) - Integer Divider Ratio and VCO Current
#
15
14
13
12
11
10
9
Bit Name
P2_N
Default
Function
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
0
2
Path 2 VCO divider integer value
3
0
2
8
7
6
5
4
3
2
P2_VCOI
Path 1 VCO bias setting: 000=minimum value, 111=maximum value
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
27 of 36
RF2053
PLL2x4 (14h) - Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P2_DN
Default
Function
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
Path 2 frequency step size used in VCO tuning gain calibration
7
E
4
8
7
6
P2_CT_GAIN
P2_KV_GAIN
Path 2 coarse tuning calibration gain
Path 2 VCO tuning gain calibration gain
5
4
3
2
1
0
PLL2x5 (15h) - More Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P2_N_PHS_ADJ
Default
Function
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Path 2 synthesizer phase adjustment
0
1
0
8
7
6
5
4
P2_CT_V
Path 2 course tuning voltage setting when performing course tuning calibration. Not used by
RF2053.
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
28 of 36
DS140110
RF2053
GPO (18h) - Internal Control Output Settings
#
15
14
13
12
11
10
9
Bit Name
Default
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1_GPO1
Setting of GPO1 when path 1 is active, used internally only
P1_GPO3
P1_GPO4
Setting of GPO3 when path 1 is active, used internally only
Setting of GPO4 when path 1 is active, used internally only
0
0
0
8
7
6
P2_GPO1
Setting of GPO1 when path 2 is active, used internally only
5
4
P2_GPO3
P2_GPO4
Setting of GPO3 when path 2 is active, used internally only
Setting of GPO4 when path 2 is active, used internally only
3
2
1
0
CHIPREV (19h) - Chip Revision Information
#
15
14
13
12
11
10
9
Bit Name
PARTNO
Default
Function
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
0
RFMD Part number for device
0
X
X
8
7
REVNO
Part revision number
6
5
4
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
29 of 36
RF2053
RB1 (1Ch) - PLL Lock and Calibration Results Read-back
#
15
14
12
11
10
9
Bit Name
LOCK
Default
Function
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
PLL lock detector, not used by RF2053.
CT setting, not used by RF2053.
CT_CAL
X
8
7
CP_CAL
X
X
CP setting, not used by RF2053.
5
4
3
2
1
0
RB2 (1Dh) - Calibration Results Read-Back
#
15
14
13
12
11
10
9
Bit Name
VO_CAL
Default
Function
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The VCO voltage measured at the start of a VCO gain calibration. Not used by RF2053.
X
X
X
8
7
V1_CAL
The VCO voltage measured at the end of a VCO gain calibration. Not used by RF2053.
6
5
4
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
30 of 36
DS140110
RF2053
RB3 (1Eh) - PLL state Read-Back
#
15
14
13
12
11
10
9
Bit Name
RSM_STATE
Default
Function
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
X
State of the radio state machine
X
0
0
8
7
6
5
4
3
2
1
0
TEST (1Fh) - Test Modes
#
15
14
13
12
11
10
9
Bit Name
TEN
Default
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Enables test mode
TMUX
Sets test multiplexer state
CPU
0
0
0
Set charge pump to pump up, 0=normal operation 1=pump down
Set charge pump to pump down, 0=normal operation 1=pump down
0=normal operation, 1=fractional divider modulator disabled
On chip low drop out regulator bypassed
CPD
FNZ
8
LDO_BYP
TSEL
7
6
5
4
DACTEST
DAC test
3
2
1
0
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
31 of 36
RF2053
Evaluation Board
The following diagrams show the schematic and PCB layout of the RF2053 evaluation boards.The standard evaluation board,
DK2053, has been configured with a narrowband VCO covering 1646MHz to 1670MHz. The wideband evaluation board,
DK2053-WB, has a VCO covering over an octave, 950MHz to 2150MHz. The mixer input and output on both boards have been
configured for broadband oeration. Application notes have been produced showing how the device is matched and on balun
implementations for narrowband applications. The evaluation boards are provided as part of a design kit (DK2053 and
DK2053-WB), along with the necessary cables and programming software tool to enable full evaluation of the RF2053.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
32 of 36
DS140110
RF2053
Evaluation Board Schematic
Narrowband with UMX-236-D16 VCO
50 strip
J7
LO_OP
R21
CB2
CB4
12
11
10
9
13
14
15
16
17
18
19
20
21
22
23
24
SLD
USB
VCC
PU2
PU1
CB3
18R
UMX-236-D16
VCO
16 15 14 13
22 pF
C41
R18
0R
12
2
11
1
R22
18R
R23
18R
T5
R7
10 K
50 strip
50 strip
50 Strip
TC1-1-13M
VDD_VCO
INDP
INDN
C38
10 nF
C39
22 pF
R24
DNI
R25
DNI
3
10
9
DSR#
8
C42
22 pF
4
R2
1K
7
VDD
5
6
7
8
17
V Tune
6
C30
3.3 nF
5
RST#
VCC
UIO
4
3
CB1
CB0
VDDA
2
C1
33 pF
C6
22 pF
C29
100 nF
1
Socket for USB
Interface
RESETB
L1
DNI
R8
DNI
C21
100 pF
R14
0 R
T1
50 strip
1
3
2
RESETB
ENX
J1
RF OP
4
C15
33 pF
C14
33 pF
C13
33 pF
C25
DNI
C20
100 pF
TC4-19+
5
6
SCLK
SDATA
ENBL
ENX
SCLK
7
8
SDATA
ENBL
C24
9
10
12
14
16
18
20
22
24
R15
0 R
R3
100 k
100 pF
C35
33 pF
50 strip
J2
RF IP
VDD
VDD
11
13
15
17
19
21
23
VDDA
C12
10 uF
C31
DNI
VDDD
C11
10 uF
32 31 30 29 28 27 26 25
T2
C23
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
100 pF
+V_OP
VDDA
INDP
VDDA
MODE
TC1-1-13M
R1
51 k
INDN
-V_OP
C34
10 nF
C2
33 pF
C18
10 nF
Active Loop Filter
C8
C10
100 nF
VDD_VCO
10 nF
C3
VDDD
33 pF
C43
10 nF
HDR_2X12
C5
LFILT1
33 pF
C19
10 nF
C16
R9
+V_OP
1.5 nF
1K5
C9
100 nF
C26
33 nF
9
10 11 12 13 14 15 16
FILT1
TP4
R11
1K
VTUNE
MODE
TP5
R6
6.8K
U1
OPA27
Note: For the UMX-236-D16 VCO
VDD_VCO is +5VDC
+V_OP is +5VDC
C36
33 pF
C27
3.3 nF
+1.2V
+V_OP
C28
100 nF
R10
2.2K
C16
DNI
-V_OP is -5VDC
C4
10 nF
-V_OP
26 MHz XTAL
J6
REF
C7
DNI
C22
DNI
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
33 of 36
RF2053
Wideband with UMS-2150-R16 VCO
50 Strip
J7
LO_OP
UMS-2150-R16
R21
Wideband VCO
68R
CB2
CB4
12
11
10
9
13
14
15
16
17
18
19
20
21
22
23
24
SLD
USB
VCC
PU2
PU1
CB3
950 MHz to 2150 MHz
16 15 14 13
33 pF
C41
R18
0R
12
2
11
1
R22
0R
R23
68R
T5
R7
10 K
LO
50 strip
50 Strip
TC1-1-13M
VDD_VCO
INDP
INDN
C40
33 pF
C38
10 nF
C39
33 pF
R24
100R
R25
100R
3
10
9
DSR#
8
C42
4
33 pF
R2
10R
7
VDD
5
6
7
8
17
V Tune
6
C30
6.8 nF
5
RST#
VCC
UIO
4
3
CB1
CB0
VDDA
2
C1
33 pF
C6
33 pF
C29
10 nF
1
Socket for USB
Interface
RESETB
L1
DNI
R8
DNI
C21
100 pF
R14
0 R
T1
50 strip
1
3
2
RESETB
ENX
J1
RF OP
4
C15
33 pF
C14
33 pF
C13
33 pF
C25
DNI
C20
100 pF
TC4-19+
5
6
SCLK
SDATA
ENBL
ENX
SCLK
7
8
SDATA
ENBL
C24
9
10
12
14
16
18
20
22
24
R15
0 R
R3
100 k
100 pF
C35
33 pF
50 strip
J2
RF IP
VDD
VDD
11
13
15
17
19
21
23
VDDA
C12
10 uF
C31
DNI
VDDD
C11
10 uF
32 31 30 29 28 27 26 25
T2
C23
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
100 pF
+V_OP
VDDA
INDP
VDDA
MODE
TC1-1-13M
R1
51 k
INDN
-V_OP
VDD_VCO
C34
10 nF
C2
33 pF
C18
10 nF
Active Loop Filter
C8
C10
100 nF
VDD_VCO
10 nF
C3
VDDD
33 pF
C43
1 uF
HDR_2X12
C5
LFILT1
33 pF
C19
10 nF
C17
1 nF
R9
680R
+V_OP
C9
Note: For the UMS-2150-R16
VDD_VCO is +12VDC
+V_OP is +16VDC
100 nF
C26
22 nF
9
10 11 12 13 14 15 16
LFILT1
TP4
R11
-V_OP is -5VDC
120R
VTUNE
MODE
TP5
R6
10K
U1
OPA27
C36
33 pF
C27
6.8 nF
+1.1V
+V_OP
C28
10 nF
R10
680R
C16
DNI
C4
10 nF
-V_OP
26 MHz XTAL
J6
REF
C7
DNI
C22
DNI
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
34 of 36
DS140110
RF2053
Evaluation Board Layout
Board Size 2.5”x2.5”
Board Thickness 0.040”, Board Material FR-4
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS140110
35 of 36
RF2053
Package Drawing
QFN, 32-Pin, 5mmx5mm
0.85±0.10
0.1 M
1
C A B
3.70±0.10
0.1
C
1
SEE DETAIL ‘D’
5.00
0.25 Typ.
0.50 Typ.
0.35±0.05
32x
-B-
-A-
0.23±0.05
32x
0.1 M
C A B
5.000
See Detail ‘D’
Dimensions in mm.
Shaded area indicates pin 1.
0.1
C
0.85±0.10
0.08
-C-
C
SEATING
PLANE
0.00
0.05
Detail ‘D’
Rotated CW
Support and Applications Information
Application notes and support material can be downloaded from the product web page: www.rfmd.com/rf205x.
Ordering Information
Part Number
RF2053
Package
32-Pin QFN
32-Pin QFN
32-Pin QFN
32-Pin QFN
32-Pin QFN
Quantity
25pcs sample bag
5pcs sample bag
100pcs reel
RF2053SB
RF2053SR
RF2053TR7
RF2053TR13
DK2053
750pcs reel
2500pcs reel
1 box
Complete Design Kit
Narrowband VCO Evaluation Board
DK2053WB
Complete Design Kit
1 box
Wideband VCO Evaluation Board
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
36 of 36
DS140110
相关型号：
DK208D
This DK208D 8A, 1200V rated standard recovery rectifier diode in a compact TO-252 surface mount package is ideal as a bypass diode or anti-parallel diode for active switching component
LITTELFUSE
DK208DRP
This DK208D 8A, 1200V rated standard recovery rectifier diode in a compact TO-252 surface mount package is ideal as a bypass diode or anti-parallel diode for active switching component
LITTELFUSE
DK2320-7EPB2
DC-DC Regulated Power Supply Module, 2 Output, 150W, Hybrid, METAL, CASE K02, MODULE
BEL
DK2320-7EPD0B1
DC-DC Regulated Power Supply Module, 2 Output, 150W, Hybrid, METAL, CASE K02, MODULE
BEL
DK2320-7EPD0T
DC-DC Regulated Power Supply Module, 2 Output, 150W, Hybrid, HEAT SINK, METAL, CASE K02, MODULE
BEL
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