RF5110PCBA [RFMD]
3V GSM POWER AMPLIFIER; 3V GSM功率放大器
| 型号： | RF5110PCBA |
| 厂家： | 
RF MICRO DEVICES |
| 描述： | 3V GSM POWER AMPLIFIER |
| 文件： | 总12页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF5110
3V GSM POWER AMPLIFIER
0
Typical Applications
• 3V GSM Cellular Handsets
• 3V Dual-Band/Triple-Band Handsets
• GPRS Compatible
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
Product Description
0.15
2 PLCS
C
A
0.05 C
-A-
1.00
0.85
3.00 SQ.
0.05
0.01
The RF5110 is a high-power, high-efficiency power ampli-
fier module offering high performance in GSM OR GPRS
applications. The device is manufactured on an advanced
GaAs HBT process, and has been designed for use as
the final RF amplifier in GSM hand-held digital cellular
equipment and other applications in the 800MHz to
950MHz band. On-board power control provides over
70dB of control range with an analog voltage input, and
provides power down with a logic “low” for standby opera-
tion. The device is self-contained with 50Ω input and the
output can be easily matched to obtain optimum power
and efficiency characteristics. The RF5110 can be used
together with the RF5111 for dual-band operation. The
device is packaged in an ultra-small 3mmx3mmx1mm
plastic package, minimizing the required board space.
1.50 TYP
0.80
0.65
2 PLCS
0.15
C B
12°
MAX
2 PLCS
C B
0.15
-B-
1.37 TYP
SEATING
PLANE
-C-
Dimensions in mm.
2.75 SQ.
2 PLCS
0.15
C
A
0.10 M
C A
B
0.60
0.24
TYP
0.30
0.18
Shaded lead is pin 1.
0.45
0.00
4 PLCS
1.65
1.35
SQ.
0.23
0.13
4 PLCS
0.55
0.30
0.50
Optimum Technology Matching® Applied
Package Style: QFN, 16-Pin, 3x3
Si BJT
GaAs HBT
SiGe HBT
GaN HEMT
GaAs MESFET
9
16
5
Si Bi-CMOS
InGaP/HBT
Si CMOS
Features
SiGe Bi-CMOS
• Single 2.7V to 4.8V Supply Voltage
• +36dBm Output Power at 3.5V
• 32dB Gain with Analog Gain Control
• 57% Efficiency
15
14
13
• 800MHz to 950MHz Operation
• Supports GSM and E-GSM
VCC1
GND1
RF IN
GND2
1
2
3
4
12 RF OUT
11 RF OUT
10 RF OUT
9
RF OUT
Ordering Information
6
7
8
RF5110
3V GSM Power Amplifier
RF5110 PCBA
Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Functional Block Diagram
Rev A0 050318
2-1
RF5110
Absolute Maximum Ratings
Parameter
Supply Voltage
Rating
-0.5 to +6.0
-0.5 to +3.0
Unit
V
DC
Caution! ESD sensitive device.
Power Control Voltage (V
)
V
APC1,2
DC Supply Current
Input RF Power
Duty Cycle at Max Power
Output Load VSWR
2400
+13
50
mA
dBm
%
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
10:1
Operating Case Temperature
Storage Temperature
-40 to +85
-55 to +150
°C
°C
Specification
Typ.
Parameter
Overall
Unit
Condition
Min.
Max.
Temp = 25°C, V =3.6V, V
=2.8V,
CC
APC1,2
P
=+4.5dBm, Freq=880MHz to 915MHz,
IN
37.5% Duty Cycle, pulse width=1731μs
See evaluation board schematic.
Using different evaluation board tune.
Operating Frequency Range
Usable Frequency Range
Maximum Output Power
880 to 915
800 to 950
34.5
MHz
MHz
dBm
33.8
33.1
50
Temp=25°C, V =3.6V, V
=2.8V
CC
APC1,2
dBm
%
Temp=+60°C, V =3.3V, V
=2.8V
CC
APC1,2
Total Efficiency
57
12
At P
, V =3.6V
OUT,MAX CC
%
P
=+20dBm
=+10dBm
OUT
5
%
P
OUT
Input Power for Max Output
Output Noise Power
+4.5
+7.0
+9.5
-72
dBm
dBm
RBW=100kHz, 925MHz to 935MHz,
P
<P
<P
,
OUT,MIN
OUT
OUT,MAX
P
<P <P
, V =3.3V to 5.0V
IN,MIN
IN
IN,MAX CC
-81
dBm
RBW=100kHz, 935MHz to 960MHz,
P
<P
<P
,
OUT,MIN
OUT
OUT,MAX
P
<P <P
, V =3.3V to 5.0V
IN,MIN
IN
IN,MAX CC
Forward Isolation
Second Harmonic
Third Harmonic
-22
-7
dBm
dBm
dBm
dBm
V
=0.3V, P =+9.5dBm
APC1,2 IN
-20
-25
P
=+9.5dBm
IN
IN
-7
P
=+9.5dBm
All Other Non-Harmonic
Spurious
-36
Input Impedance
Optimum Source Impedance
Input VSWR
50
40+j10
Ω
Ω
For best noise performance
-5dB<P <P
OUT,MAX
2.5:1
4:1
P
OUT,MAX
OUT
P
<P
-5dB
OUT
OUT,MAX
Output Load VSWR
Stability
8:1
Spurious<-36dBm, V
RBW=100kHz
No damage
=0.3V to 2.6V,
APC1,2
Ruggedness
10:1
Output Load Impedance
2.6-j1.5
0.5
Ω
Load Impedance presented at RF OUT pad
Power Control VAPC1 VAPC2
Power Control “ON”
2.6
V
Maximum P , Voltage supplied to the
OUT
input
Power Control “OFF”
Power Control Range
Gain Control Slope
0.2
75
5
V
Minimum P
, Voltage supplied to the input
OUT
dB
V
=0.2V to 2.6V
APC1,2
100
4.5
150
dB/V
P
=-10dBm to +35dBm
OUT
APC Input Capacitance
APC Input Current
10
5
pF
mA
DC to 2MHz
V
=2.8V
APC1,2
25
μA
V
=0V
APC1,2
Turn On/Off Time
100
ns
V
=0 to 2.8V
APC1,2
2-2
Rev A0 050318
RF5110
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Power Supply
Power Supply Voltage
3.5
V
V
Specifications
Nominal operating limits, P
2.7
4.8
5.5
<+35dBm
OUT
V
With maximum output load VSWR 6:1,
<+35dBm
P
OUT
Power Supply Current
2
200
1
A
DC Current at P
OUT,MAX
15
335
10
mA
μA
μA
Idle Current, P <-30dBm
IN
P
P
<-30dBm, V
<-30dBm, V
=0.2V
IN
IN
APC1,2
APC1,2
1
10
=0.2V, Temp=+85°C
Rev A0 050318
2-3
RF5110
Pin
Function Description
Interface Schematic
Power supply for the pre-amplifier stage and interstage matching. This See pin 3.
1
2
3
VCC1
GND1
RF IN
pin forms the shunt inductance needed for proper tuning of the inter-
stage match. Refer to the application schematic for proper configura-
tion. Note that position and value of the components are important.
Ground connection for the pre-amplifier stage. Keep traces physically
short and connect immediately to the ground plane for best perfor-
mance. It is important for stability that this pin has it’s own vias to the
groundplane, to minimize any common inductance.
See pin 1.
RF Input. This is a 50Ω input, but the actual impedance depends on the
interstage matching network connected to pin 1. An external DC block-
ing capacitor is required if this port is connected to a DC path to ground
or a DC voltage.
VCC1
GND1
RF IN
From Bias
Stages
Ground connection for the driver stage. To minimize the noise power at See pin 3.
the output, it is recommended to connect this pin with a trace of about
40mil to the ground plane. This will slightly reduce the small signal
gain, and lower the noise power. It is important for stability that this pin
have it’s own vias to the ground plane, minimizing common inductance.
4
5
GND2
VCC2
Power supply for the driver stage and interstage matching. This pin
forms the shunt inductance needed for proper tuning of the interstage
match. Please refer to the application schematic for proper configura-
tion, and note that position and value of the components are important.
VCC2
GND2
From Bias
Stages
Same as pin 5.
Not connected.
6
7
8
VCC2
NC
2F0
Connection for the second harmonic trap. This pin is internally con-
nected to the RF OUT pins. The bonding wire together with an external
capacitor form a series resonator that should be tuned to the second
harmonic frequency in order to increase efficiency and reduce spurious
outputs.
Same as pin 9.
RF Output and power supply for the output stage. Bias voltage for the
final stage is provided through this wide output pin. An external match-
ing network is required to provide the optimum load impedance.
9
RF OUT
RF OUT
From Bias
Stages
GND
PCKG BAS
Same as pin 9.
Same as pin 9.
Same as pin 9.
10
11
12
13
14
15
16
RF OUT
RF OUT
RF OUT
NC
VCC
APC2
APC1
Same as pin 9.
Same as pin 9.
Not connected.
Power supply for the bias circuits.
Power Control for the output stage. See pin 16 for more details.
See pin 16.
Power Control for the driver stage and pre-amplifier. When this pin is
"low," all circuits are shut off. A "low" is typically 0.5V or less at room
temperature. A shunt bypass capacitor is required. During normal oper-
ation this pin is the power control. Control range varies from about 1.0V
for -10dBm to 2.6V for +35dBm RF output power. The maximum power
that can be achieved depends on the actual output matching; see the
application information for more details. The maximum current into this
APC VCC
To RF
Stages
pin is 5mA when V
=2.6V, and 0mA when V
=0V.
APC1
APC
GND
GND
Ground connection for the output stage. This pad should be connected
to the ground plane by vias directly under the device. A short path is
required to obtain optimum performance, as well as to provide a good
thermal path to the PCB for maximum heat dissipation.
Pkg
Base
GND
2-4
Rev A0 050318
RF5110
Theory of Operation and Application Information
The RF5110 is a three-stage device with 32 dB gain at full power. Therefore, the drive required to fully saturate the out-
put is +3dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part requires only a single positive
3V supply to operate to full specification. Power control is provided through a single pin interface, with a separate Power
Down control pin. The final stage ground is achieved through the large pad in the middle of the backside of the package.
First and second stage grounds are brought out through separate ground pins for isolation from the output. These
grounds should be connected directly with vias to the PCB ground plane, and not connected with the output ground to
form a so called “local ground plane” on the top layer of the PCB. The output is brought out through the wide output pad,
and forms the RF output signal path.
The amplifier operates in near Class C bias mode. The final stage is “deep AB”, meaning the quiescent current is very
low. As the RF drive is increased, the final stage self-biases, causing the bias point to shift up and, at full power, draws
about 2000mA. The optimum load for the output stage is approximately 2.6Ω. This is the load at the output collector, and
is created by the series inductance formed by the output bond wires, vias, and microstrip, and 2 shunt capacitors exter-
nal to the part. The optimum load impedance at the RF Output pad is 2.6-j1.5Ω. With this match, a 50Ω terminal imped-
ance is achieved. The input is internally matched to 50Ω with just a blocking capacitor needed. This data sheet defines
the configuration for GSM operation.
The input is DC coupled; thus, a blocking cap must be inserted in series. Also, the first stage bias may be adjusted by a
resistive divider with high value resistors on this pin to VPC and ground. For nominal operation, however, no external
adjustment is necessary as internal resistors set the bias point optimally.
VCC1 and VCC2 provide supply voltage to the first and second stage, as well as provides some frequency selectivity to
tune to the operating band. Essentially, the bias is fed to this pin through a short microstrip. A bypass capacitor sets the
inductance seen by the part, so placement of the bypass cap can affect the frequency of the gain peak. This supply
should be bypassed individually with 100pF capacitors before being combined with VCC for the output stage to prevent
feedback and oscillations.
The RF OUT pin provides the output power. Bias for the final stage is fed to this output line, and the feed must be capa-
ble of supporting the approximately 2A of current required. Care should be taken to keep the losses low in the bias feed
and output components. A narrow microstrip line is recommended because DC losses in a bias choke will degrade effi-
ciency and power.
While the part is safe under CW operation, maximum power and reliability will be achieved under pulsed conditions. The
data shown in this data sheet is based on a 12.5% duty cycle and a 600μs pulse, unless specified otherwise.
The part will operate over a 3.0V to 5.0V range. Under nominal conditions, the power at 3.5V will be greater than
+34.5dBm at +90°C. As the voltage is increased, however, the output power will increase. Thus, in a system design, the
ALC (Automatic Level Control) Loop will back down the power to the desired level. This must occur during operation, or
the device may be damaged from too much power dissipation. At 5.0V, over +38dBm may be produced; however, this
level of power is not recommended, and can cause damage to the device.
The HBT breakdown voltage is >20V, so there are no issue with overvoltage. However, under worst-case conditions, with
the RF drive at full power during transmit, and the output VSWR extremely high, a low load impedance at the collector of
the output transistors can cause currents much higher than normal. Due to the bipolar nature of the devices, there is no
limitation on the amount of current de device will sink, and the safe current densities could be exceeded.
High current conditions are potentially dangerous to any RF device. High currents lead to high channel temperatures and
may force early failures. The RF5110 includes temperature compensation circuits in the bias network to stabilize the RF
transistors, thus limiting the current through the amplifier and protecting the devices from damage. The same mechanism
works to compensate the currents due to ambient temperature variations.
To avoid excessively high currents it is important to control the VAPC when operating at supply voltages higher than 4.0V,
such that the maximum output power is not exceeded.
Rev A0 050318
2-5
RF5110
Internal Schematic
VCC1
VCC2
RF OUT
5 Ω
4.5 pF
APC1
VCC
APC2
VCC
RF IN
5 Ω
400 Ω
300 Ω
1.0 kΩ
APC1
PKG BASE
GND2
PKG BASE
2-6
Rev A0 050318
RF5110
Evaluation Board Schematic
GSM850 Lumped Element
VCC
VCC
50 Ω μstrip
J3
P1
1
P2
VAPC
1
2
P1-1
P1-2
VCC
VCC
GND
GND
P2-1
VAPC
GND
GND
2
3
VAPC
VCC1
3
C18
3.3 μF
CON3
4
C17
10 nF
C16
10 nF
C15
33 pF
CON4
C13
1 nF
C2
C3
C19
L1
10 nF
1 nF
27 pF
11 nH
16
15
14
13
C14
33 pF
1
2
3
4
12
11
10
9
L3
8.8 nH
L4
1.8 nH
C12
56 pF
C1
56 pF
50 Ω μstrip
50 Ω μstrip
J1
RF IN
J2
RF OUT
60 mils
65 mils
40 mils
R1
C9
15 pF
C10
2 pF
C11
180 Ω
9.1 pF
5
6
7
8
C9 and C10 share
the same pad.
L2
L6
C8
1.5 pF
10 Ω Ferrite 1.6 nH
VCC2
+
C21
3.3 μF
C5
10 nF
C6
1 nF
C20
13 pF
C7
33 pF
Rev A0 050318
2-7
RF5110
Evaluation Board Schematic
GSM900 Lumped Element
VCC
VCC
50 Ω μstrip
J3
P1
1
P2
1
VAPC
P1-1
P1-2
VCC
VCC
GND
GND
P2-1
VAPC
GND
GND
2
3
2
VAPC
3
C18
3.3 μF
CON3
4
C17
10 nF
C16
10 nF
C15
47 pF
CON4
VCC1
C13
1 nF
C2
C3
C19
L1
10 nF
1 nF
27 pF
11 nH
16
15
14
13
C14
47 pF
1
2
3
4
12
11
10
9
L3
8.8 nH
L4
C12
C1
3.6 nH
56 pF
56 pF
50 Ω μstrip
50 Ω μstrip
J1
RF IN
J2
RF OUT
55 mils
39 mils
R1
C9
15 pF
C10
11 pF
C11*
180 Ω
5.6 pF
5
6
7
8
*C11 is
adjacent to L4.
C9 and C10 share
the same pad.
L2
L6
C8
1.5 pF
10 Ω Ferrite 1.6 nH
VCC2
+
C6
1 nF
C21
3.3 μF
C5
10 nF
C20
15 pF
C23
27 pF
C7
27 pF
C23 and C27 share
the same pad.
2-8
Rev A0 050318
RF5110
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.032”; Board Material FR-4; Multi-Layer
Rev A0 050318
2-9
RF5110
Typical Test Setup
Power Supply
V- V+ S+ S-
RF Generator
Spectrum
Analyzer
3dB
10dB/5W
Buffer
x1 OpAmp
Pulse
Generator
A buffer amplifier is recommended because the current into the
APC changes with voltage. As an alternative, the voltage may be
monitored with an oscilloscope.
V
Notes about testing the RF5110
The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effect on the signal
generator as a result of switching the input impedance of the PA. When VAPC is switched quickly, the resulting input
impedance change can cause the signal generator to vary its output signal, either in output level or in frequency. Instead
of an attenuator an isolator may also be used. The attenuator at the output is to prevent damage to the spectrum ana-
lyzer, and should be sized accordingly to handle the power.
It is important not to exceed the rated supply current and output power. When testing the device at higher than nominal
supply voltage, the VAPC should be adjusted to avoid the output power exceeding +36dBm. During load-pull testing at
the output it is important to monitor the forward power through a directional coupler. The forward power should not
exceed +36dBm, and VAPC needs to be adjusted accordingly. This simulates the behavior for the power control loop. To
avoid damage, it is recommended to set the power supply to limit the current during the burst not to exceed the maximum
current rating.
2-10
Rev A0 050318
RF5110
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is
3μinch to 8μinch gold over 180μinch nickel.
PCB Land Pattern Recommendation
PCB land patterns for PFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern
shown has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to
accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful
process development is recommended.
PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ.
B = 0.28 x 0.64 (mm) Typ.
C = 1.50 (mm) Sq.
Dimensions in mm.
1.50 Typ.
0.50 Typ.
Pin 16
B
B
B
B
Pin 1
Pin 12
A
A
A
A
A
A
A
A
0.50 Typ.
0.55 Typ.
0.75 Typ.
1.50
Typ.
C
B
B
B
B
Pin 8
0.55 Typ.
0.75 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
Rev A0 050318
2-11
RF5110
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the
PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all
pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask
clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.74 x 0.38 (mm) Typ.
B = 0.38 x 0.74 (mm) Typ.
C = 1.60 (mm) Sq.
Dimensions in mm.
1.50 Typ.
0.50 Typ.
Pin 16
B
B
B
B
Pin 1
Pin 12
A
A
A
A
A
A
A
A
0.50 Typ.
0.55 Typ.
0.75 Typ.
1.50
Typ.
C
B
B
B
B
Pin 8
0.55 Typ.
0.75 Typ.
Figure 2. PCB Solder Mask Pattern (Top View)
Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the
device.
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating
routing strategies.
The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size
on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested
that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
2-12
Rev A0 050318
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