ECJ4YB0J226M [RICHTEK]

3A, 2MHz, Synchronous Step-Down Converter; 3A， 2MHz的，同步降压型转换器


型号：	ECJ4YB0J226M
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	3A, 2MHz, Synchronous Step-Down Converter 3A， 2MHz的，同步降压型转换器转换器
文件：	总14页 (文件大小：537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT8015D

3A, 2MHz, Synchronous Step-Down Converter

General Description

Features

^zHigh Efficiency : Up to 95%

The RT8015D is a high efficiency synchronous, step-down

DC/DC converter. Its input voltage range is from 2.6V to

5.5V and provides an adjustable regulated output voltage

from 0.8V to 5V while delivering up to 3A of output current.

^zLow R_DS(ON)Internal Switches : 110mΩ

^zProgrammable Frequency : 300kHz to 2MHz

^zNo Schottky Diode Required

^z0.8V Reference Allows for Low Output Voltage

^zForced Continuous Mode Operation

^zLow Dropout Operation : 100% Duty Cycle

^zPower Good Output Voltage Indicator

^zRoHS Compliant and Halogen Free

The internal synchronous low on-resistance power

switches increase efficiency and eliminate the need for

an external Schottky diode. The switching frequency is

set by an external resistor. The 100% duty cycle provides

low dropout operation extending battery life in portable

systems. Current mode operation with external

compensation allows the transient response to be

optimized over a wide range of loads and output capacitors.

Applications

z Portable Instruments

z Battery-Powered Equipment

z Notebook Computers

z Distributed Power Systems

z IP Phones

The RT8015D is operated in forced continuous PWM Mode

which minimizes ripple voltage and reduces the noise and

RF interference.

The 100% duty cycle in Low Dropout Operation further

maximize battery life.

z Digital Cameras

Pin Configurations

The RT8015Dis available in the WDFN-10L 3x3 package.

(TOP VIEW)

Ordering Information

RT8015D

COMP

PGOOD

VDD

PVDD

SHDN/RT

GND

Package Type

QW : WDFN-10L 3x3

PGND

WDFN-10L 3x3

Lead Plating System

G : Green (Halogen Free and Pb Free)

Note :

Marking Information

Richtek products are :

For marking information, contact our sales representative

directly or through a Richtek distributor located in your

area.

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8015D-02 March 2011

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RT8015D

Typical Application Circuit

2.2µH

RT8015D

PVDD

OUT

3, 4

2.5V/3A

510k

22pF

22µF

OUT

22µF x 2

100k

VDD

0.1µF

COMP

1nF

27k

COMP

240k

COMP

PGOOD

OSC

332k

GND

SHDN/RT

PGND

Note : Using all Ceramic Capacitors

Table 1. Recommended Component Selection

(V)

R1 (kΩ )

750

R2 (kΩ )

240

(kΩ) C

(nF)

L1 (μH)

2.2

OUT

(μF)

OUT

COMP

3.3

22 x 2

2.5

1.8

1.5

1.2

1.0

510

240

2.2

300

240

2.2

210

240

2.2

120

240

1.0

240

1.0

Functional Pin Description

Pin No.

Pin Name

Pin Function

Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the

SHDN/RT

switching frequency. Forcing this pin to V causes the device to be shut down.

Signal Ground. All small-signal components and compensation components should

connect to this ground, which in turn connects to PGND at one point.

GND

3, 4

Internal Power MOSFET Switches Output. Connect this pin to the inductor.

PGND

PVDD

Power Ground. Connect this pin close to the negative terminal of C and C

OUT

Power Input Supply. Decouple this pin to PGND with a capacitor.

Signal Input Supply. Decouple this pin to GND with a capacitor. Normally V is equal

VDD

to PVDD.

Power Good Indicator. This pin is open-drain logic output that is pulled to ground

when the output voltage is not within ±12.5% of regulation point.

PGOOD

Feedback Pin. This pin receives the feedback voltage from a resistive divider

connected across the output.

Error Amplifier Compensation Point. The current comparator threshold increases with

this control voltage. Connect external compensation elements to this pin to stabilize

the control loop.

COMP

No Internal Connection. The exposed pad must be soldered to a large PCB and

connected to GND for maximum power dissipation.

Exposed Pad

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DS8015D-02 March 2011

RT8015D

Function Block Diagram

SHDN/RT

PVDD

ISEN

Slope

Com

OSC

COMP

0.8V

Output

Clamp

Limit

Driver

Int-SS

0.9V

Control

Logic

0.7V

0.2V

NISEN

PGND

NMOS I Limit

POR

PGOOD

GND

OTP

REF

VDD

Layout Guide

Place the input and output

capacitors as close to the

IC as possible.

LX should be

GND

OUT

connected to Inductor

by wide and short

trace, keep sensitive

components away

from this trace

RT8015D

Bottom Layer

PVDD

PGND

GND

VDD

PGOOD

COMP ¹⁰

SHDN/RT

OSC

COMP

OUT

GND

Place the feedback and

compensation components as

close to the IC as possible.

DS8015D-02 March 2011

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RT8015D

Operation

Slope Compensation and Inductor Peak Current

Main Control Loop

Slope compensation provides stability in constant

frequency architectures by preventing sub-harmonic

oscillations at duty cycles greater than 50%. It is

accomplished internally by adding a compensating ramp

to the inductor current signal. Normally, the maximum

inductor peak current is reduced when slope compensation

is added. In the RT8015D, however, separated inductor

current signals are used to monitor over current condition.

This keeps the maximum output current relatively constant

regardless of duty cycle.

The RT8015Dis a monolithic, constant-frequency, current

mode step-down DC/DC converter. During normal

operation, the internal top power switch (P-Channel

MOSFET) is turned on at the beginning of each clock

cycle. Current in the inductor increases until the peak

inductor current reach the value defined by the voltage on

the COMP pin. The error amplifier adjusts the voltage on

the COMP pin by comparing the feedback signal from a

resistor divider on the FB pin with an internal 0.8V

reference. When the load current increases, it causes a

reduction in the feedback voltage relative to the reference.

The error amplifier raises the COMP voltage until the

average inductor current matches the new load current.

When the top power MOSFET shuts off, the synchronous

power switch (N-MOSFET) turns on until either the bottom

current limit is reached or the beginning of the next clock

cycle.

Short Circuit Protection

When the output is shorted to ground, the inductor current

decays very slowly during a single switching cycle. A

current runaway detector is used to monitor inductor

current.As current increasing beyond the control of current

loop, switching cycles will be skipped to prevent current

runaway from occurring.

The operating frequency is set by an external resistor

connected between the RT pin and ground. The practical

switching frequency can range from 300kHz to 2MHz.

Dropout Operation

When the input supply voltage decreases toward the output

voltage, the duty cycle increases toward the maximum

on-time. Further reduction of the supply voltage forces

the main switch to remain on for more than one cycle

eventually reaching 100% duty cycle.

The output voltage will then be determined by the input

voltage minus the voltage drop across the internal

P-Channel MOSFET and the inductor.

Low Supply Operation

The RT8015D is designed to operate down to an input

supply voltage of 2.6V. One important consideration at

low input supply voltages is that the R_DS(ON)of the

P-Channel andN-Channel power switches increases. The

user should calculate the power dissipation when the

RT8015D is used at 100% duty cycle with low input

voltages to ensure that thermal limits are not exceeded.

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DS8015D-02 March 2011

RT8015D

Absolute Maximum Ratings (Note 1)

z Supply Input Voltage, VDD, PVDD ---------------------------------------------------------------------------- −0.3V to 6V

z LX Pin Switch Voltage -------------------------------------------------------------------------------------------- −0.3V to (PVDD+ 0.3V)

<200ns --------------------------------------------------------------------------------------------------------------- −5V to 7.5V

z Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V)

z LX Pin Switch Current -------------------------------------------------------------------------------------------- 4A

z Power Dissipation, P_D@ T_A= 25°C

WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------- 1.429W

z Package Thermal Resistance (Note 2)

WDFN-10L 3x3, θ_JA----------------------------------------------------------------------------------------------- 70°C/W

WDFN-10L 3x3, θ_JC----------------------------------------------------------------------------------------------- 7.8°C/W

z Junction Temperature --------------------------------------------------------------------------------------------- 150°C

z Lead Temperature (Soldering, 10 sec.)----------------------------------------------------------------------- 260°C

z Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

z Supply Input Voltage---------------------------------------------------------------------------------------------- 2.6V to 5.5V

z Junction Temperature Range------------------------------------------------------------------------------------ −40°C to 125°C

z Ambient Temperature Range------------------------------------------------------------------------------------ −40°C to 85°C

Electrical Characteristics

(V_DD= 3.3V, T_A= 25°C, unless otherwise specified)

Parameter

Symbol

V_DD

V_REF

I_FB

Test Conditions

Min

2.6

0.792

Typ

Max Unit

Input Voltage Range

5.5

0.808

0.4

Feedback Reference Voltage

Feedback Leakage Current

0.8

0.1

460

μA

%/V

Active , V_FB= 0.78V, Not Switching

Shutdown

DC Bias Current

Output Voltage Line Regulation

Output Voltage Load Regulation

V_IN= 2.7V to 5.5V

0.03

Measured in Servo Loop,

V_COMP= 0.2V to 0.7V (Note 5)

−0.2 ±0.02

0.2

Error Amplifier

Transconductance

g_m

800

0.4

μs

Current Sense Transresistance R_T

Switching Leakage Current

SHDN/RT = VIN = 5.5V

R_OSC= 332k

1.2

μA

0.8

0.3

MHz

Switching Frequency

Switch On Resistance, High

Switch On Resistance, Low

R_{DS(ON)_P}I_SW= 0.5A

R_{DS(ON)_N}I_SW= 0.5A

110

160

170

mΩ

To be continued

DS8015D-02 March 2011

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RT8015D

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Power Good Range

±12.5

±15

Power Good Pull-Down

Resistance

120

Peak Current Limit

I_LIM

3.2

3.8

2.4

2.3

V_DDRising

V_DDFalling

Under Voltage Lockout

Threshold

Shutdown Threshold

V_IN− 0.7 V_IN− 0.4

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θ_JAis measured in the natural convection at T_A= 25°C on a high effective four layers thermal conductivity test board of

JEDEC 51-7 thermal measurement standard.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. The specifications over the -40°C to 85°C operation ambient temperature range are assured by design, characterization

and correlation with statistical process controls.

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DS8015D-02 March 2011

RT8015D

Typical Operating Characteristics

Efficiency vs. Load Current

Output Voltage vs. Load Current

100

2.492

2.488

2.484

2.480

2.476

2.472

2.468

2.464

2.460

2.456

V_IN= 5.5V

V_IN= 5V

V_IN= 4.5V

V_OUT= 2.5V

V_IN= 5V

0.01

0.1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Load Current (A)

Frequency vs. Temperature

Peak Current Limit vs. Input Voltage

1.08

1.06

1.04

1.02

1.00

0.98

5.0

4.5

4.0

3.5

3.0

2.5

2.0

V_IN= 5V, V_OUT= 2.5V, I_OUT= 0A

V_OUT= 2.5V

5 5.25 5.5

3.5

3.75

4.25 4.5 4.75

Input Voltage (V)

-50

-25

100

125

Temperature (°C)

Quiescent Current vs. Input Voltage

Quiescent Current vs. Temperature

450

440

430

420

410

400

390

380

370

360

450

440

430

420

410

400

390

380

V_IN= 5V

2.5

3.5

4.5

5.5

-50

-25

100

125

Temperature (°C)

Input Voltage (V)

DS8015D-02 March 2011

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RT8015D

Output Voltage vs. Temperature

UVP

3.34

3.32

3.30

3.28

3.26

3.24

3.22

V_IN= 5V, V_OUT= 1.05V

V_OUT

(1V/Div)

V_LX

(5V/Div)

I_LX

(5A/Div)

PGOOD

(5V/Div)

V_IN= 5V

100 125

-50

-25

Time (4μs/Div)

Temperature (°C)

Output Ripple

Load Transient Response

V_IN= 5V, V_OUT= 2.5V

_OUT= 0A to 3A

V_LX

(5V/Div)

V_{OUT_ac}

(100mV/Div)

V_{OUT_ac}

(10mV/Div)

I_LX

(2A/Div)

I_LOAD

(1A/Div)

V_IN= 5V, V_OUT= 2.5V

I_OUT= 3A

Time (400ns/Div)

Time (100μs/Div)

Start-up with No Load

Start-up with Heavy Load

V_IN

(5V/Div)

V_IN

(5V/Div)

V_LX

(5V/Div)

V_LX

(5V/Div)

V_OUT

(1V/Div)

V_OUT

(1V/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

V_IN= 5V, V_OUT= 10.5V, I_OUT= 0A

V_IN= 5V, V_OUT= 1.05V, I_OUT= 3A

Time (400μs/Div)

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RT8015D

Application Information

Power-Good Output

The basic RT8015Dapplication circuit is shown in Typical

Application Circuit. External component selection is

determined by the maximum load current and begins with

the selection of the inductor value and operating frequency

The power good output is an open-drain output and requires

a pull-up resistor. When the output voltage is 12.5% above

or 12.5% below its set voltage, PGOOD will be pulled

low. It is held low until the output voltage returns to within

the allowed tolerances once more. In soft start, PGOOD

is actively held low and is allowed to transition high until

soft start finished over and the output voltage reaches

87.5% of its set voltage.

followed by C_INand C_OUT

Output Voltage Programming

The output voltage is set by an external resistive divider

according to the following equation :

⎛

⎞

⎟

OUT

= V

× 1+

⎜

REF

⎝

⎠

Operating Frequency

where V_REFequals to 0.8V typical.

Selection of the operating frequency is a tradeoff between

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequency improves efficiency by

reducing internal gate charge and switching losses but

requires larger inductance and/or capacitance to maintain

low output ripple voltage.

The resistive divider allows the FB pin to sense a fraction

of the output voltage as shown in Figure 1.

OUT

RT8015D

GND

The operating frequency of the RT8015D is determined

by an external resistor that is connected between the RT

pin and ground. The value of the resistor sets the ramp

current that is used to charge and discharge an internal

timing capacitor within the oscillator. The RT resistor value

can be determined by examining the frequency vs. RT

curve.Although frequencies as high as 2MHz are possible,

the minimum on-time of the RT8015D imposes a minimum

limit on the operating duty cycle. The minimum on-time

is typically 110ns. Therefore, the minimum duty cycle is

equal to 100 x 110ns x f(Hz).

Figure 1. Setting the Output Voltage

Soft-Start

The RT8015D contains an internal soft-start clamp that

gradually raises the clamp on the COMP pin. The full

current range becomes available on COMP after 2048

switching cycles as shown in Figure 2.

2.5

RT = 152k for 2MHz

V_IN

(2V/Div)

1.5

V_OUT

(500mV/Div)

RT = 330k for 1MHz

I_LX

(1A/Div)

0.5

V_IN= 5V, V_OUT= 1.05V, I_OUT= 2A

Time (1ms/Div)

200

400

600

800

1000

Figure 2. Soft-Start

(k )

R_OS_S_C_C(kٛΩ)

Figure 3

DS8015D-02 March 2011

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RT8015D

Inductor Selection

small and don't radiate energy but generally cost more

than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price vs. size requirements and

any radiated field/EMI requirements.

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ΔI_Lincreases with higher V_INand decreases

with higher inductance.

f ×L

OUT

⎡

⎤⎡

⎦⎣

⎤

OUT

C_INand C_OUTSelection

ΔI =

1−

⎥⎢

⎢

⎣

⎥

⎦

The input capacitance, C_IN, is needed to filter the

trapezoidal current at the source of the top MOSFET. To

prevent large ripple voltage, a low ESR input capacitor

sized for the maximum RMS current should be used. RMS

current is given by :

Having a lower ripple current reduces the ESR losses in

the output capacitors and the output voltage ripple. Highest

efficiency operation is achieved at low frequency with small

ripple current. This, however, requires a large inductor. A

reasonable starting point for selecting the ripple current

is ΔI = 0.4(I_MAX). The largest ripple current occurs at the

highest V_IN. To guarantee that the ripple current stays

below a specified maximum, the inductor value should be

chosen according to the following equation :

OUT

= I

−1

RMS

OUT(MAX)

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT/2. This simple worst-case condition is

commonly used for design because even significant

deviations do not offer much relief. Choose a capacitor

rated at a higher temperature than required.

⎡

⎤⎡

1−

⎤

OUT

L =

⎢

⎣

⎥⎢

⎥

⎦

f × ΔI

IN(MAX)

L(MAX)

⎦⎣

Inductor Core Selection

Several capacitors may also be paralleled to meet size or

height requirements in the design.

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

afford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite or mollypermalloy

cores. Actual core loss is independent of core size for a

fixed inductor value but it is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

The selection of C_OUTis determined by the effective series

resistance (ESR) that is required to minimize voltage ripple

and load step transients, as well as the amount of bulk

capacitance that is necessary to ensure that the control

loop is stable. Loop stability can be checked by viewing

the load transient response as described in a later section.

The output ripple, ΔV_OUT, is determined by :

⎡

⎣

⎤

ΔV

≤ ΔI ESR +

OUT

⎢

⎥

⎦

8fC

OUT

Ferrite designs have very low core losses and are preferred

at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates “hard”, which means that

inductance collapses abruptly when the peak design

current is exceeded.

The output ripple is highest at maximum input voltage

since ΔI_Lincreases with input voltage. Multiple capacitors

placed in parallel may be needed to meet the ESR and

RMS current handling requirements.Dry tantalum, special

polymer, aluminum electrolytic and ceramic capacitors are

all available in surface mount packages. Special polymer

capacitors offer very low ESR but have lower capacitance

density than other types. Tantalum capacitors have the

highest capacitance density but it is important to only

use types that have been surge tested for use in switching

power supplies. Aluminum electrolytic capacitors have

significantly higher ESR but can be used in cost-sensitive

This result in an abrupt increase in inductor ripple current

and consequent output voltage ripple.

Do not allow the core to saturate!

Different core materials and shapes will change the size/

current and price/current relationship of an inductor. Toroid

or shielded pot cores in ferrite or permalloy materials are

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DS8015D-02 March 2011

RT8015D

applications provided that consideration is given to ripple

current ratings and long term reliability. Ceramic capacitors

have excellent low ESR characteristics but can have a

high voltage coefficient and audible piezoelectric effects.

The high Q of ceramic capacitors with trace inductance

can also lead to significant ringing.

are the individual losses as a percentage of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses: V_DDquiescent current and I²R losses.

The V_DDquiescent current loss dominates the efficiency

loss at very low load currents whereas the I²R loss

dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve

at very low load currents can be misleading since the

actual power lost is of no consequence.

Using Ceramic Input and Output Capacitors

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

be taken when these capacitors are used at the input and

output. When a ceramic capacitor is used at the input

and the power is supplied by a wall adapter through long

wires, a load step at the output can induce ringing at the

input, V_IN. At best, this ringing can couple to the output

and be mistaken as loop instability. At worst, a sudden

inrush of current through the long wires can potentially

cause a voltage spike at V_INlarge enough to damage the

part.

1. The V_DDquiescent current is due to two components :

theDC bias current as given in the electrical characteristics

and the internal main switch and synchronous switch gate

charge currents. The gate charge current results from

switching the gate capacitance of the internal power

MOSFET switches. Each time the gate is switched from

high to low to high again, a packet of charge ΔQ moves

from V_DDto ground. The resulting ΔQ/Δt is the current out

of V_DDthat is typically larger than the DC bias current. In

continuous mode, I_GATECHG= f(QT+QB) where QT and QB

are the gate charges of the internal top and bottom

switches.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, V_OUTimmediately shifts by an amount

equal to ΔI_LOAD(ESR), where ESR is the effective series

resistance of C_OUT. ΔI_LOADalso begins to charge or

discharge C_OUTgenerating a feedback error signal used

by the regulator to return V_OUTto its steady-state value.

During this recovery time, V_OUTcan be monitored for

overshoot or ringing that would indicate a stability problem.

The COMP pin external components and output capacitor

shown in TypicalApplication Circuit will provide adequate

compensation for most applications.

Both theDC bias and gate charge losses are proportional

to V_DDand thus their effects will be more pronounced at

higher supply voltages.

2. I²R losses are calculated from the resistances of the

internal switches, RSW and external inductor RL. In

continuous mode, the average output current flowing

through inductor L is “chopped” between the main switch

and the synchronous switch. Thus, the series resistance

looking into the LX pin is a function of both top and bottom

MOSFET R_DS(ON)and the duty cycle (D) as follows :

R_SW= R_DS(ON)TOP x D + R_DS(ON)BOT x (1"D) The R_DS(ON)

for both the top and bottom MOSFETs can be obtained

from the Typical Performance Characteristics curves. Thus,

to obtain I²R losses, simply add RSW to RL and multiply

the result by the square of the average output current.

Other losses including C_INand C_OUTESR dissipative

losses and inductor core losses generally account for less

than 2% of the total loss.

Efficiency Considerations

The efficiency of a switching regulator is equal to the output

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as :

Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc.

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RT8015D

Current Limit

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Four Layers PCB

RT8015Dhas cycle-by-cycle current limiting control. The

current-limit circuit employs a “peak” current sensing

algorithm. If the magnitude of the current-sense signal is

above the current-limit threshold, the controller will turn

off high-side MOSFET and turn on low-side MOSFET.

WDFN-10L 3x3

Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage protection. When the output voltage is less than

25% of its set voltage threshold, the under voltage

protection circuit will be triggered to terminate switching

operation and the controller will be latched unless VDD

POR is detected again. During soft-start, the UVP will be

blanked until soft-start finish.

100

125

Ambient Temperature (°C)

Figure 4.Derating Curves for RT8015DPackage

Layout Considerations

Thermal Considerations

Follow the PCB layout guidelines for optimal performance

of RT8015D.

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

` Aground plane is recommended. If a ground plane layer

is not used, the signal and power grounds should be

segregated with all small-signal components returning

to the GND pin at one point that is then connected to

the PGND pin close to the IC. The exposed pad should

be connected to GND.

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

` Connect the terminal of the input capacitor(s), C_IN, as

close as possible to the PVDD pin. This capacitor

provides the AC current into the internal power

MOSFETs.

Where T_J(MAX)is the maximum operation junction

temperature, T_Ais the ambient temperature and the θ_JAis

the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT8015D, The maximum junction temperature is 125°C.

The junction to ambient thermal resistance θ_JAis layout

dependent. For WDFN-10L 3x3 packages, the thermal

resistance θ_JAis 70°C/W on the standard JEDEC 51-7

four layers thermal test board. The maximum power

dissipation at T_A= 25°C can be calculated by following

formula :

` LX node is with high frequency voltage swing and should

be kept within small area. Keep all sensitive small-signal

nodes away from the LX node to prevent stray capacitive

noise pick-up.

` Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise

of powercomponents. You can connect the copper areas

to anyDC net (PVDD, VDD, VOUT, PGND, GND, or any

other DC rail in your system).

P_D(MAX)= (125°C − 25°C) / (70°C/W) = 1.429W for

WDFN-10L 3x3 packages

` Connect the FB pin directly to the feedback resistors.

The resistor divider must be connected between V_OUT

andGND.

The maximum power dissipation depends on operating

ambient temperature for fixed T_J(MAX)and thermal

resistance θ_JA. For RT8015D packages, the Figure 4 of

derating curves allows the designer to see the effect of

rising ambient temperature on the maximum power

allowed.

www.richtek.com

DS8015D-02 March 2011

RT8015D

Recommended component selection for Typical Application

Table 1. Inductors

Inductance (μH) DCR (mΩ) Current Rating (mA) Dimensions (mm)

Component Supplier Series

TAIYO YUDEN

NR 8040

7800

8x8x4

Table 2. Capacitors for C_INand C_OUT

Component Supplier

TDK

Part No.

Capacitance (μF)

Case Size

1210

C3225X5R0J226M

C2012X5R0J106M

ECJ4YB0J226M

ECJ4YB1A106M

LMK325BJ226ML

JMK316BJ226ML

JMK212BJ106ML

TDK

0805

1210

1206

0805

Panasonic

TAIYO YUDEN

DS8015D-02 March 2011

www.richtek.com

RT8015D

Outline Dimension

SEE DETAIL A

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

0.700

0.000

0.175

0.180

2.950

2.300

2.950

1.500

0.800

0.050

0.250

0.300

3.050

2.650

3.050

1.750

0.028

0.000

0.007

0.116

0.091

0.116

0.059

0.031

0.002

0.010

0.012

0.120

0.104

0.120

0.069

0.500

0.020

0.350

0.450

0.014

0.018

W-Type 10L DFN 3x3 Package

Richtek Technology Corporation

Headquarter

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Tel: (8862)86672399 Fax: (8862)86672377

Email: marketing@richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

www.richtek.com

DS8015D-02 March 2011

ECJ4YB0J226M [RICHTEK]

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