RT5028CGQW [RICHTEK]
Integrated PMIC;
| 型号： | RT5028CGQW |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Integrated PMIC 集成电源管理电路 |
| 文件： | 总41页 (文件大小：624K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RT5028C
Integrated PMIC with 4-Channel Synchronous Buck
Converters, 8 LDOs, and MTP Non-Volatile Memory for
Industrial Applications
General Description
Features
z Input Voltage Operating Range is 3.3V to 5.5V
z Step-Down Regulator : VIN Range is 3.3V to 5.5V
` Max Current 2.4A/2A/1.6A/2A
The RT5028C is a highly-integrated low-power high-
performance analog SOC with PMIC in one single chip
designed for Industrial applications.
` Programmable Frequency from 500kHz to 2MHz
` I2C Programmable Output Level
` I2C Programmable Operation Mode (Force PWM
or Auto PSM/PWM)
The RT5028C includes four synchronous step-downDC-
DC converters and eight LDOs for system power.
The RT5028C also embeds one EEPROM (MTP) for
setting sequence and timing etc.
` I2C Programmable Output Discharge Mode
(Discharge or Flatting)
Additionally, the RT5028C PMIC also includes one IRQ
report.
z Linear Regulators : VIN Range is 2.5V to 5.5V
` Max Current 0.3A
` I2C Programmable Output Level
z Embedded 32Bytes MTP for Factory Tuning
` External MTP Pin for Write Protection
z Sequence can be Controlled by I2C or each EN pins
Defined by MASK_GPIO pin.
Ordering Information
RT5028C
Package Type
QW : WQFN-56L 7x7 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
z OT/UVP/VIN LV/POWRON press Time Interrupt
(IRQ).
` I2C Control Interface: Support Fast Mode up to
Note :
Richtek products are :
400kb/s
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
z RoHS Compliant and Halogen Free
Applications
z Industrial
Simplified Application Circuit
RT5028C
VIN
VOUTLx
VDDP
SCL
SDA
VINL123
VINL456
VINL78
LXBx
IRQ
RESET
PWRHOLD
PWRON
REBOOT
MTP
VOUTBxS
VINBx
MASK_GPIO
SADDR
ENBx
ENLx
AGND
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
www.richtek.com
1
RT5028C
Marking Information
Pin Configurations
RT5028CGQW : Product Number
(TOP VIEW)
RT5028C
GQW
YMDNN : Date Code
YMDNN
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VOUTL1
VINL123
VOUTL2
VOUTL3
VOUTL6
VOUTL5
VINL456
VOUTL4
VOUTL7
VINL78
VOUTL8
ENL4
LXB2
LXB2
ENB2
VOUTB2S
VINB3
VINB3
LXB3
3
4
5
6
7
AGND
8
LXB3
9
AGND
VOUTB3S
VINB4
LXB4
ENB3
VOUTB4S
10
11
12
13
14
57
ENL5
ENL6
15 16 17 18 19 20 21 22 23 24 25 26 27 28
WQFN-56L 7x7
Functional Pin Description
Pin No.
Pin Name
VOUTL1
VINL123
VOUTL2
VOUTL3
VOUTL6
VOUTL5
VINL456
VOUTL4
VOUTL7
VINL78
VOUTL8
ENL4
Pin Function
1
2
Output voltage regulation node for LDO1.
Input power for LDO1, LDO2 and LDO3.
3
Output voltage regulation node for LDO2.
4
Output voltage regulation node for LDO3.
5
Output voltage regulation node for LDO6.
6
Output voltage regulation node for LDO5.
7
Input power for LDO4, LDO5 and LDO6.
8
Output voltage regulation node for LDO4.
9
Output voltage regulation node for LDO7.
10
11
12
13
14
15
Input power for LDO7 and LDO8.
Output Voltage Regulation Node for LDO8.
Enable control input for LDO4. Connect a 100kΩ pull-low resistor.
Enable control input for LDO5. Connect a 100kΩ pull-low resistor.
Enable control input for LDO6. Connect a 100kΩ pull-low resistor.
ENL5
ENL6
SCL
Clock input for I2C. Open-drain output, connect a 10kΩ pull-up resistor.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DS5028C-03 September 2016
RT5028C
Pin No.
16
Pin Name
SDA
Pin Function
Data input for I2C. Open-drain output, connect a 10kΩ pull-up resistor.
Enable control input for LDO7. Connect a 100kΩ pull-low resistor.
Enable control input for LDO8. Connect a 100kΩ pull-low resistor.
Open-drain IRQ output node.
17
ENL7
ENL8
IRQ
18
19
20
Reset output.
RESET
21, 34, 56, 57
(Exposed Pad)
Analog ground. The exposed pad must be soldered to a large PCB and
connected to AGND for maximum power dissipation.
AGND
22
23
PWRON
REBOOT
Manual power on. Connect a 100kΩ pull-up resistor.
System power reboot. Connect a 100kΩ pull-low resistor.
MTP write protection pin. Connect a 100kΩ pull-low resistor, logic low is inhibited
and logic high is permit to write.
24
MTP
Select I2C or use EN pin for Bucks and LDOs. Connect a 100kΩ pull-low resistor.
As MASK_GPIO is high, ignore all EN pins.
As MASK_GPIO is low, EN pins and I2C both can control. EN pins priority is
higher than I2C.
25
26
MASK_GPIO
PWRHOLD
Power hold input. Connect a 100kΩ pull-low resistor.
27
28
SADDR
ENB4
I2C slave address. Connect a 100kΩ pull-low resistor.
Enable control input for Buck4. Connect a 100kΩ pull-low resistor.
Output voltage regulation node for Buck4.
29
VOUTB4S
ENB3
30
Enable control input for Buck3. Connect a 100kΩ pull-low resistor.
Internal switch node to output inductor connection for Buck4.
Input power for Buck4.
31
LXB4
32
VINB4
VOUTB3S
LXB3
33
Output voltage regulation node for Buck3.
35, 36
37, 38
39
Internal switch node to output inductor connection for Buck3.
Input power for Buck3.
VINB3
VOUTB2S
ENB2
Output voltage regulation node for Buck2.
40
Enable control input for Buck2. Connect a 100kΩ pull-low resistor.
Internal switch node to output inductor connection for Buck2.
Input power for Buck2.
41, 42
43, 44
45, 46
47, 48
49
LXB2
VINB2
VINB1
LXB1
Input power for Buck1.
Internal switch node to output inductor connection for Buck1.
Enable control input for Buck1. Connect a 100kΩ pull-low resistor.
Output voltage regulation node for Buck1
ENB1
50
VOUTB1S
VDDP
VIN
51
Internal bias regulator voltage. External load on this pin is not allowed.
Input power for analog base.
52
53
ENL1
Enable control input for LDO1. Connect a 100kΩ pull-low resistor.
Enable control input for LDO2. Connect a 100kΩ pull-low resistor.
Enable control input for LDO3. Connect a 100kΩ pull-low resistor.
54
ENL2
55
ENL3
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
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3
RT5028C
Functional Block Diagram
VOUTL1
VINL123
LDO1
300mA
VIN
Analog
Base
VDDP
VOUTL2
LDO2
300mA
VINB1
LXB1
LDO3
300mA
VOUTL3
Buck1
2.4A
VOUTL4
VINL456
LDO4
300mA
GND
LDO5
300mA
VOUTB1S
VINB2
VOUTL5
VOUTL6
LDO6
300mA
Buck2
2A
VOUTL7
VINL78
LDO7
300mA
LXB2
Central
Controller
LDO8
300mA
2
I C
GND
VOUTL8
Programmable
VOUTB2S
VINB3
SDA
SCL
IRQ
Buck3
1.6A
LXB3
RESET
PWRHOLD
REBOOT
MTP
GND
State
Machine
VOUTB3S
VINB4
MASK_GPIO
SADDR
PWRON
Buck4
2A
LXB4
ENB1 to ENB4
ENL1 to ENL8
GND
AGND
VOUTB4S
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS5028C-03 September 2016
RT5028C
Operation
The RT5028C is a highly-integrated solution for industrial
system including 4-CH step-downDC-DC converters and
8-CH LDOs. The RT5028C application mechanism will be
introduced in later sections.
Over-Temperature Protection
An Over-Temperature Protection (OTP) is contained in the
device. The protection is triggered to force the device
shutdown for protecting itself when the junction
temperature exceeds 165°C typically. Once the junction
temperature drops below the hysteresis 10°C typically,
the device must be re-send PWRON to start system.
The power-on and power-off sequences can be controlled
by I2C or each EN pin and detected in MASK_GPIO pin.
When the MASK_GPIO pin is at Hi level, the PMIC follows
the power-on sequence to turn on channels. When the
MASK_GPIO pin is at Lo level, the channels of PMIC will
be controlled by the EN pin.
Output Under-Voltage Protection
The output under-voltage protection is implemented in order
to prevent operation at low output voltage conditions.
When the step-downDC-DC converters output voltage is
lower than 1/2 x (VOUT), the UVP event triggers and PMIC
turns off immediately.
Synchronous Step-Down DC-DC Converter
Four current mode synchronous step-down DC-DC
converters operate with internal power MOSFETs, FB
resistors and compensation network. These channels are
suitable for core power in industrial system. They can be
operated at 100% maximum duty cycle to extend battery
operating voltage range. When the input voltage is close
to the output voltage, the converter enters low dropout
mode with low output ripple. The operating frequency of
step-down converter is adjustable from 500kHz to 2MHz
and is controlled by I2C. Besides, the I2C interface also
can be used to select different operation modes, On/Off
Sequence, programmable the output voltage, RAMP
control and discharge function. To enableAUTO Mode, it
is used to improve the efficiency at light load. If theAUTO
Mode is disabled, the converter operates in force PWM
mode with fixed switching frequency.
Linear Regulator
Eight generic low voltage LDOs for multiple purpose power.
The LDOs are stable over the entire operating load range
with the use of external ceramic capacitors. The LDOs
also have I2C programmable power on/off sequence and
discharge function. The output voltage is adjustable by
the I2C interface in the range of 1.6V to 3.6V.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
www.richtek.com
5
RT5028C
Absolute Maximum Ratings (Note 1)
z Analog Base Input Voltage, VIN --------------------------------------------------------------------------------------- −0.3V to 6V
z PMIC Input Voltage, VINL123/456/78, VINB1/2/3/4 --------------------------------------------------------------- −0.3V to 6V
z PMIC Output Voltage, VOUTLx, VOUTBxS, LXBx ---------------------------------------------------------------- −0.3V to 6V
z PMIC related Other Pins ------------------------------------------------------------------------------------------------ −0.3V to 6V
z PowerDissipation, PD @ TA = 25°C
WQFN-56L7x7 ------------------------------------------------------------------------------------------------------------ 3.7W
z Package Thermal Resistance (Note 2)
WQFN-56L 7x7, θJA ------------------------------------------------------------------------------------------------------ 27°C/W
WQFN-56L 7x7, θJC ------------------------------------------------------------------------------------------------------ 7°C/W
z Junction Temperature ---------------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------ 260°C
z Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------------- 2kV
MM (Machine Model)----------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
z Junction Temperature Range ------------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range ------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(Note 5)
Parameter
Operation Voltage of VIN
PMIC
Symbol
Test Conditions
Min Typ Max Unit
As fSW > 1MHz, 3.3V ≤ VIN ≤ 5.5V.
If fSW ≤ 1MHz, VIN ≥ 4V.
3.3
--
5.5
V
V
IN = 5V, LDOs, Bucks are ON with no load. 300 450 600
μA
μA
Quiescent Current
IIN
VIN = 5V, LDOs, Bucks are OFF.
SCL = SDA = 0V
5
20
40
Temperature 1
Temperature 2
--
--
100
125
--
--
Warning for Die
Temperature
OTW
OTP
°C
°C
Over-Temperature
Protection
--
165
10
--
--
OTP and Warning
Hysteresis
--
°C
Input Pull-low 100k Resistor RLow
VIN = 5V, Temperature = −40°C to 85°C
70
115 160
kΩ
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS5028C-03 September 2016
RT5028C
Parameter
Buck1 to Buck4
Symbol
Test Conditions
Min
Typ Max
Unit
Input Voltage
VINB
IVINB
VOUTAcc
3.3
10
--
5.5
40
V
Consumption Current
AUTO mode IOUT = 0mA, each buck
20
μA
3.1V < VIN < 5.5V,
1mA < IOUT < IMAX, −40 < TA < 85°C
Output Voltage Accuracy
Switching Frequency
−3
--
--
3
2
%
fSW
I2C programmable
0.43
MHz
1MHz < fSW
fSW ≤ 1MHz
Buck1
−10
−20
3.1
2.8
2.6
2.8
--
--
10
20
Switching Frequency
Accuracy
%
4.4
4
5.8
5.2
4.8
5.3
Buck2
Peak Current Limit
OCP
UVP
IMAX
A
%
A
Buck3
3.7
4.1
Buck4
VOUTB1S to VOUTB4S < 0.66 x (VOUT
Target)
Under-Voltage Protection
Maximum Output Current
High-Side On-Resistance
56
66
76
Buck1
Buck2
Buck3
Buck4
2.4
2
--
--
--
--
--
--
--
--
1.6
2.0
Rpon
Rnon
VIN = 3.7V
VIN = 3.7V
50
40
150
110
250
160
mΩ
mΩ
Low-Side On-Resistance
LDO1 to LDO8
Input Voltage for
VINL123/456/78
VINL
2.5
--
5.5
V
3.1V ≤ VIN ≤ 5.5V, 50μA ≤ IOUT ≤ IMAX
−40 < TA < 85°C
3.1V ≤ VIN ≤ 5.5V, 50μA ≤ IOUT ≤ IMAX
−40 < TA < 85°C
Output Voltage LDO123/78 VOUTL
−3
−3
--
--
3
3
%
%
Output Voltage LDO456
VOUTL
Output Current
IOUT
Isht
300
330
0.05
--
--
600
0.3
0.5
60
2
mA
mA
Output Short Current
450
0.1
VIN > 3.1V
VIN
−
V
IN = VSET, IOUT
=
Voltage Difference
V
VOUT
IOUTMAX
VIN > 2.5V
0.05 0.11
Supply Current
ISS
IOUT = 0mA
10
0
35
1
μA
μA
Shutdown Current
IOFF
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
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7
RT5028C
Parameter
Symbol
Test Conditions
Min Typ Max
Unit
Control Input Pin Electrical Characteristics
Voltage Output Low VOL
High-Level VIH
Low-Level VIL
--
1.5
--
--
--
--
0.4
--
V
V
Input Voltage
0.4
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Limits apply to the recommended operating temperature range of −40°C to 85°C, unless otherwise noted. Minimum
and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TA = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply : VIN = 3.3V to 5.5V.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS5028C-03 September 2016
RT5028C
Typical Application Circuit
1µF
1µF
1µF
1µF
1µF
1µF
1µF
RT5028C
52
1
3
4
VIN
VOUTL1
VOUTL2
1µF
51
VDDP
1µF
2
VINL123
VOUTL3
1µF
7
VINL456
8
VOUTL4
VOUTL5
1µF
10
VINL78
6
5
45, 46
VINB1
VOUTL6
10µF
1µF
1µF
9
VOUTL7
VOUTL8
2.2µH
47, 48
LXB1
22µF
VIN
50
11
VOUTB1S
43, 44
VINB2
SADDR
MASK_GPIOMTP
15
16
SCL
SDA
10µF
2.2µH
41, 42
19
20
26
IRQ
AGND
LXB2
22µF
AP
RESET
39
VOUTB2S
As SADDR connect to AGND
slave address
PWRHOLD
REBOOT
23
37, 38
VINB3
=0111111
24
25
27
As SADDR connect to VIN
slave address
10µF
MTP
MASK_GPIO
SADDR
=0110111
2.2µH
35, 36
LXB3
22µF
As MASK_GPIO connect to AGND
EN pins can control.
33
22
VOUTB3S
PWRON
As MASK_GPIO connect to VIN
Ignore all EN pins.
32
VINB4
10µF
As MTP connect to AGND
Inhibit to write MTP.
As MTP connect to VIN
Permit to write MTP.
ENL1 to ENL8
ENB1 to ENB4
2.2µH
31
LXB4
22µF
21, 34, 56,
57 (Exposed Pad)
29
AGND
VOUTB4S
Suggested Components for Typical Application Circuit
Description
Inductor for Buck-2.2μH
CIN for Buck-10μF
P/N
Manufacture
Murata
LQH43PB2R2M26L
C1206X7R1E516DT
C1206X7R22E416DT
C0603X7R1E216DT
Murata
COUT for Buck-22μF
CIN/COUT for LDO-1μF
Murata
Murata
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
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9
RT5028C
Typical Operating Characteristics
CH1 Buck Efficiency vs. Output Current
CH2 Buck Efficiency vs. Output Current
100
100
90
80
70
60
50
40
30
20
10
0
90
80
VIN = 3.3V
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 5V
VIN = 3.3V
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 5V
70
60
50
40
30
20
10
0
VIN = 5.5V
VIN = 5.5V
VOUT = 1.5V, L = 2.2μH, COUT = 10μF
VOUT = 1.35V, L = 2.2μH, COUT = 10μF
100 1000 10000
10
10
100
1000
10000
Output Current (mA)
Output Current (mA)
CH3 Buck Efficiency vs. Output Current
CH4 Buck Efficiency vs. Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 4.5V
VIN = 5V
VIN = 3.3V
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 5V
VIN = 5.5V
VIN = 5.5V
VOUT = 1.2V, L = 2.2μH, COUT = 10μF
VOUT = 3.3V, L = 2.2μH, COUT = 10μF
10
100
1000
10000
10
100
1000
10000
Output Current (mA)
Output Current (mA)
CH1 Buck Output Voltage vs. Output Current
1.39
CH2 Buck Output Voltage vs. Output Current
1.53
VIN = 3.3V
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 5V
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.52
1.51
1.50
1.49
1.48
1.47
VIN = 3.3V
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 5V
VIN = 5.5V
VIN = 5.5V
L = 2.2μH, COUT = 10μF
L = 2.2μH, COUT = 10μF
1000 1500 2000
0
300 600 900 1200 1500 1800 2100 2400
Output Current (mA)
0
500
Output Current (A)
Copyright 2016 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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10
DS5028C-03 September 2016
RT5028C
CH3 Buck Output Voltage vs. Output Current
1.25
CH4 Buck Output Voltage vs. Output Current
3.38
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 4.5V
VIN = 5V
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
3.33
3.28
3.23
3.18
3.13
3.08
VIN = 3.3V
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 5V
VIN = 5.5V
VIN = 5.5V
L = 2.2μH, COUT = 10μF
L = 2.2μH, COUT = 10μF
0
500
1000
1500
2000
0
200 400 600 800 1000 1200 1400 1600
Output Current (mA)
Output Current (mA)
CH1 Buck Output Voltage vs. Input Voltage
1.40
CH2 Buck Output Voltage vs. Input Voltage
1.55
1.39
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.31
1.30
1.53
1.51
1.49
1.47
1.45
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
IOUT = 2400mA
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
L = 2.2μH, COUT = 10μF
4.8 5.3 5.8
L = 2.2μH, COUT = 10μF
4.8 5.3 5.8
3.3
3.8
4.3
3.3
3.8
4.3
Input Voltage (V)
Input Voltage (V)
CH3 Buck Output Voltage vs. Input Voltage
1.24
CH4 Buck Output Voltage vs. Input Voltage
3.80
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
1.14
3.60
3.40
3.20
3.00
2.80
2.60
2.40
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1600mA
L = 2.2μH, COUT = 10μF
4.8 5.3 5.8
L = 2.2μH, COUT = 10μF
4.8 5.3 5.8
3.3
3.8
4.3
3.3
3.8
4.3
Input Voltage (V)
Input Voltage (V)
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11
RT5028C
LDO2 Output Voltage vs. Output Current
LDO5 Output Voltage vs. Output Current
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
3.32
3.30
3.28
3.26
3.24
3.22
3.20
VIN = 2.5V
VIN = 3V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
VIN = 3.3V
VIN = 3.6V
VIN = 3.9V
VIN = 4.2V
VIN = 5V
VIN = 5.5V
VIN = 5.5V
COUT = 1μF
COUT = 1μF
250 300
0
50
100
150
200
250
300
0
50
100
150
200
Output Current (mA)
Output Current (mA)
LDO7 Output Voltage vs. Output Current
LDO2 Output Voltage vs. Input Voltage
2.52
2.50
2.48
2.46
2.44
2.42
2.40
1.78
1.78
1.77
1.77
1.76
1.76
1.75
IOUT = 0mA
IOUT = 100mA
IOUT = 200mA
VIN = 2.5V
VIN = 3V
VIN = 3.6V
VIN = 4.2V
VIN = 5V
IOUT = 300mA
VIN = 5.5V
COUT = 1μF
COUT = 1μF
0
50
100
150
200
250
300
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Output Current (mA)
LDO5 Output Voltage vs. Input Voltage
LDO7 Output Voltage vs. Input Voltage
3.50
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
2.50
2.48
2.46
2.44
2.42
2.40
IOUT = 0mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
IOUT = 0mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
COUT = 1μF
COUT = 1μF
3.3
3.8
4.3
4.8
5.3
5.8
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
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12
DS5028C-03 September 2016
RT5028C
Application Information
The RT5028C is a highly-integrated solution for industrial
system including PMIC and memory system. The
RT5028C application mechanism and I2C compatible
interface are introduced in later sections. The system's
slave address is 0110111 (As SADDR = high) or
0111111(As SADDR = low).
Detail time sequence control is described in Power ON/
OFF diagram. The I2C interface can program individual
regulator output voltage as well as on/off control and
voltage setting.
I2C Interface Timing Diagram
The RT5028C acts as an I2C -bus slave. The I2C-bus master
configures the settings for all function blocks by sending
command bytes to the RT5028C via the 2-wire I2C-bus.
The I2C timing diagrams are list in the following.
PMIC - Power management system provides 8 low dropout
linear regulator and 4 high efficiency synchronous step-
down DC-DC converters. Power-On and Power-Off
sequences are control by PWRONand RESET input pins.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
I2C Interface Electrical Characteristics
SDA, SCLK Input High Level
Threshold
0.7 x
VDDA
--
--
V
SDA, SCLK Input Low Level
Threshold
0.3 x
VDDA
--
--
--
--
V
SCLK Clock Rate
fSCL
400
--
kHz
Hold Time (Repeated) START
Condition.
After this period, the first clock
pulse is generated
tHD;STA
0.6
--
μs
LOW Period of the SCL Clock tLOW
1.3
0.6
--
--
--
--
μs
μs
HIGH Period of the SCL Clock tHIGH
Set-Up Time for a Repeated
tSU;STA
0.6
--
--
μs
START Condition
Data Hold Time
Data Set-Up Time
tHD;DAT
tSU;DAT
0
--
--
0.9
--
μs
100
ns
Set-Up Time for STOP
Condition
tSU;STO
tBUF
tR
0.6
1.3
20
20
2
--
--
--
--
--
μs
μs
Bus Free Time Between a
STOP and START Condition
--
300
300
--
Rise Time of Both SDA and
SCL Signals
ns
Fall Time of Both SDA and
SCL Signals
tF
ns
SDA and SCL Output Low Sink
Current
IOL
SDA or SCL voltage = 0.4V
mA
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13
RT5028C
Read Function
Reading One Indexed Byte ofData from RT (With 1-Byte)
Acknowledge from RT
Slave Address
R/W
Acknowledge from RT
Acknowledge from RT
Slave Address
R/W
Acknowledge from Master
Data Byte
S
0
A
Register Address
A
Sr
1
A
A
P
Repeated Start
1Byte
Reading n Indexed Words ofData from RT (WithN-Byte)
Acknowledge from RT
Slave Address
R/W
Acknowledge from RT
Acknowledge from RT
Slave Address
R/W
S
0
A
Register Address
A
Sr
1
A
Repeated Start
Acknowledge from Master
Data Byte
Acknowledge from Master
Data Byte
Acknowledge from Master
Data Byte
Acknowledge from Master
Data Byte
A
A
……
A
A
P
1st Byte
2nd Byte
(n-1)th Byte
nth Byte
Write Function
Writing One Byte of Data to RT (With 1-Byte)
Acknowledge from RT
Slave Address
R/W
Acknowledge from RT
Acknowledge from RT
Data Byte
S
0
A
Register Address
A
A
P
1Byte
Writing n Bytes of Data to RT (With N-Byte)
Acknowledge from RT
Slave Address
R/W
Acknowledge from RT
Acknowledge from RT
Acknowledge from RT
S
0
A
Register Address
A
Data Byte
A
A
Data Byte
A
…
1st Byte
Acknowledge from RT
Data Byte
2nd Byte
Acknowledge from RT
Data Byte
A
P
(n-1)th Byte
nth Byte
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14
DS5028C-03 September 2016
RT5028C
PMIC
Power Channels Control Methodology
to restart PMIC again. Another PWROFF event, OTP or
UVP occurs, PMIC will execute the power off. In the
RT5028C PMIC, the UVP event will be set out when the
Buck1 to Buck4s' output voltage is lower than 1/2 x (VOUT).
When VINpowerGood or PWRONevent occurs, the PMIC
will follow the power on sequence to turn on channels.
During normal operation, users can use the REBOOT pin
Power Off
Edge
trigger
Edge
trigger
No
No
VIN Power
Good
PWRON
Check
Yes
Yes
1
Mask_GPIO
0
2
(External Enable Control)
(Internal I C)
No
External EN
Check
Power On
Sequence
Yes
Yes
Yes
REBOOT
Check
REBOOT
Check
Normal Operation
No
No
No
No
PWROFF
Check
OTP Check
UVP Check
Yes
Yes
Yes
Power Off
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15
RT5028C
PMIC - POWER ON/OFF Setting
The circuit setting for communication between RT5028C
and AP is showed as below.
VIN
SADDR
SCL
SDA
IRQ
MASK_GPIOMTP
AGND
AP
RESET
As SADDR connect ot AGND
slave address
PWRHOLD
=0111111
As SADDR connect ot VIN
slave address
REBOOT
State
Machine
MTP
=0110111
MASK_GPIO
SADDR
PWRON
As MASK_GPIO connect ot
AGND
EN pins can control.
As MASK_GPIO connect ot VIN
Ignore all EN pins.
ENL1 to ENL8
ENB1 to ENB4
As MTP connect ot AGND
Inhibit to write MTP.
As MTP connect ot VIN
Permit to write MTP.
Power Hold Function
If users want to disable power hold function, set
“DisTHOLD” bit in I2C register 10 bit[0] to disable this
function. In the timing diagram below, the “THOLD” and
“RESET_DLY” can be set by MTP program.
When the “PWRHOLD” signal does not come during
THOLD time, the RT5028C will do shutdown sequence.
START_TIME
PWRON
BUCK1
……
BUCK4
LDO1
……
LDO8
RESET_DLY
THOLD
Turn off sequence :
First-on-last-Off
RESET
Always Low
PWRHOLD
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16
DS5028C-03 September 2016
RT5028C
WhenAP sends the “PWRHOLD” signal during THOLDtime, the RT5028C will keep power-on.
START_TIME
PWRON
BUCK1
……
BUCK4
LDO1
……
LDO8
RESET_DLY
THOLD
RESET
Low to High signal from AP.
PWRHOLD
Timing Based ON/OFF Sequence
Normal power off
Normal power on
START_TIME
PWRON
SHDN_PRESS
TSS
BUCK1
TSS
BUCK2
……
BUCK4
TSS
TSS
...
LDO1
……
LDO8
RESET_DLY
RESET
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17
RT5028C
Level Based ON/OFF Sequence
Normal power on
Normal power off
START_TIME
PWRON
SHDN_PRESS
8ms
>80 %
>80 %
>80 %
BUCK1
BUCK2
……
BUCK4
8ms
>80 %
LDO1
……
LDO8
RESET_DLY
RESET
Abnormal OFF
Normal power on
START_TIME
PWRON
Abnormal power off
IRQ Even Occur
IRQ
SHDN_DLYTIME
BUCK1
TSS
BUCK2
……
BUCK4
TSS
LDO1
……
LDO8
RESET_DLY
RESET
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DS5028C-03 September 2016
RT5028C
PMU On/Off Sequence Setting
In the RT5028C, users can set the power on/off sequence and output voltage by I2C register 0x01 to 0x04 for Buck
output voltage, 0x07 to 0x0E for LDO output voltage and 0x2C to 0X32 for startup sequence setting.
In the table below, users must set one by one (continues number) and missing code is not allowed.
If users miss sequence code, the RT5028C will wait for next channel and the IC will be hold in waiting status.
Startup Enable Method
Output Voltage Setting
Startup Sequence Setting
(Soft-Start Control)
Buck1Output[5:0]
[000000]
Buck1_Seq[3:0]
[0001]
Buck1
Buck2
Buck3
Buck4
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
LDO8
Buck2Output[5:0]
[101100]
Buck2_Seq[3:0]
[0010]
Buck3Output[5:0]
[000000]
Buck3_Seq[3:0]
[0011]
Buck4Output[5:0]
[101100]
Buck4_Seq[3:0]
[0100]
LDO1OUT[6:0]
[0000000]
LDO1_Seq[3:0]
[0101]
LDO2OUT[6:0]
[0101000]
LDO2_Seq[3:0]
[0110]
[10]
LDO3OUT[6:0]
[0000000]
LDO3_Seq[3:0]
[0111]
LDO4OUT[6:0]
[0101000]
LDO4_Seq[3:0]
[1000]
LDO5OUT[6:0]
[0000000]
LDO5_Seq[3:0]
[1001]
LDO6OUT[6:0]
[0101000]
LDO6_Seq[3:0]
[1010]
LDO7OUT[6:0]
[0000000]
LDO7_Seq[3:0]
[1011]
LDO8OUT[6:0]
[0101000]
LDO8_Seq[3:0]
[1100]
Note :
* Output Voltage Setting: fill relative binary code to set the output voltage.
* Startup Sequence Setting :
“0000” denotes no operation (disable).
“0001” denotes first-startup.
“1100 to 1111” denotes last-startup.
If same number, it means startup at the same time.
*Startup Enable Method :
[01] to [11] : each startup enable interval time (1ms, 4ms, 8ms).
[00] : start end voltage (the output voltage's 80%)
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19
RT5028C
Synchronous Step-Down DC-DC Converter
REBOOT Function
Four current mode synchronous step-down DC-DC
converters operate with internal power MOSFETs and
compensation network. These channels supply the power
core chip of portable system. They can be operated at
100% maximum duty cycle to extend battery operating
voltage range. When the input voltage is close to the output
voltage, the converter enters low dropout mode with low
output ripple. The operating frequency range of step-down
converter is 0.5MHz to 2MHz.
As the REBOOT pin is set from low to high, the REBOOT
function will be active. The REBOOT's FSM is shown as
below. It concludes 100ms de-bouncing time and delay1/
delay2 power off delay time.
Table 1. REBOOT Input Control Setting
Description
Default
10
delayed2
delayed1
00 : 100ms 10 : 1s
01 : 500ms 11 : 2s
10
delayed1 power-off then
delayed2 power-on PMIC
Action
Four step-down converters have RAMP control function
as the following diagram.
From “LOW“ to “HIGH” rising
input into REBOOT pin with
100ms debouncing time
DC/DC 1/2/3/4
Output Voltage4
DC/DC 1/2/3/4
Output Voltage2
Wait for delayed1 time
Power off the PMIC
Wait for delayed2 time
Power on the PMIC
DC/DC 1/2/3/4
Output Voltage1
DC/DC 1/2/3/4
Output Voltage3
IRQ Table
We summarize all IRQ items in the register table. All IRQ_status registers are implemented as reset after read. If
IRQ_enable bit is Low, the IRQ_status bit will not update status. IRQ_enable will mask IRQ_status to trigger IRQ_PMIC
Low, so the system can decide which interrupt is necessary.
Waveform - (when the other IRQ_status are low)
Mask
IRQ_Status
IRQ_Enable_OVP
OVP
Reset after
Read
Reset after
Read
IRQ_Status_OVP
IRQ_PMIC
Waveform - (when the other IRQ_status are low)
* OTW125/OTW100 means the 125°C/100°C pre-warming over temperature. It only change IRQ status bits and don't
trigger IRQ pin.
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DS5028C-03 September 2016
RT5028C
EEPROM (MTP) Control Flow
Thermal Considerations
The RT5028C embeds 32 bytes MTPmemory, and it allows
users to save some I2C register bank data to MTP. When
the I2C register 0x3A Bit[0]/Bit[1] is wrote to “1”, the
MTP Page1/Page2 will execute erase process firstly.
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Because the erase process will be done in every writing
time, the MTP data will be missed. So it would be best
for users to read data from MTP to I2C first before
executing writing process.
PD(MAX) = (TJ(MAX) − TA) / θJA
Page 1 writing follow :
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
Set I2C Register 0x3A Bit[4] =1
Reading MTP process
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-56L 7x7 package, the thermal resistance, θJA, is
27°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
PMU will read MTP data to
relative I2C register bank.
Set I2C Register 0x3A Bit[0]
PMU will erase the MTP page1
Writing MTP process
data
PD(MAX) = (125°C − 25°C) / (27°C/W) = 3.7W for
WQFN-56L 7x7 package
PMU will move relative I2C
register bank data to MTP
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Page 2 writing follow :
Set I2C Register 0x3A Bit[5] =1
Reading MTP process
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
PMU will read MTP data to
relative I2C register bank.
Set I2C Register 0x3A Bit[1]
PMU will erase the MTP page2
Writing MTP process
data
0
25
50
75
100
125
PMU will move relative I2C
register bank data to MTP
Ambient Temperature (°C)
Figure 1.Derating Curve of Maximum PowerDissipation
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21
RT5028C
Layout Consideration
` The switching node area connected to LX and inductor
should be minimized for lower EMI.
For the best performance of the RT5028C, the following
PCB layout guidelines must be strictly followed.
` Connect theGNDand Exposed Pad to a strong ground
plane for maximum thermal dissipation and noise
` Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
protection.
` Directly connect the output capacitors to the feedback
network of each channel to avoid bouncing caused by
parasitic resistance and inductance from the PCB trace.
` Keep the main power traces as wide and short as
possible.
VOUTB1
GND
GND
LX should be connected to Inductor by wide and short
trace, keep sensitive compontents away from this trace.
Input/Output capacitors must be
placed as close as possible to the
Input/Output pins.
56 55 54 53 52 51 50 49 48 47 46 45 44 43
LXB2
VOUTL1
VIN VINL123
VOUTL2
1
2
3
4
5
6
7
8
9
42
41
40
39
38
37
36
VOUTB2
LXB2
GND
GND
ENB2
VOUTB2S
VOUTL3
VOUTL6
VIN
VINB3
VINB3
LXB3
VOUTL5
VIN VINL456
VOUTL4
GND
VOUTB3
GND
35 LXB3
AGND
GND
VOUTL7
34
33
32
31
VOUTB3S
VINB4
VIN
10
VINL78
VIN
VOUTL8 11
ENL4 12
GND
LXB4
VOUTB4
30 ENB3
ENL5 13
GND
GND
29 VOUTB4S
14
ENL6
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Connect the Exposed
Pad to a ground plane.
GND
GND
Figure 2. PCB LayoutGuide
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DS5028C-03 September 2016
RT5028C
Table 2. I2C Register Table
Detail Description
Address 00
Bit
Device ID
Name
Description
Vendor Identification : Richtek : 1000b
Chip Revision
Read/Write Reset Value
[7:4]
[3:0]
VENDOR_ID
CHIP_REV
R
R
1000
0001
Address 01
BUCKcontrol1
Bit
Name
Description
R/W
R/W
Reset Value
Option
Buck1 output voltage regulation
000000 : 0.7V, 25mV per step
000001 : 0.725V
…
[7:2]
Buck1Output[5:0]
101100 : 1.8V
…
111111 : 1.8V
VRC setting
[1:0]
Buck1VRC
00 : 25mV/10μs, 01 : 50mV/10μs,
10 : 100mV/10μs, 11 : 200mV/10μs
R/W
R/W
Option
Address
Bit
02
BUCKcontrol2
Description
Name
Reset Value
Buck2 output voltage regulation
000000 : 0.7V, 25mV per step
000001 : 0.725V
…
[7:2]
Buck2Output[5:0]
R/W
Option
101100 : 1.8V
…
111111 : 1.8V
VRC setting
[1:0]
Buck2VRC
00 : 25mV/10μs, 01 : 50mV/10μs,
10 : 100mV/10μs, 11 : 200mV/10μs
R/W
R/W
Option
Address 03
BUCKcontrol3
Description
Bit
Name
Reset Value
Buck3 output voltage regulation
000000 : 0.7V, 50mV per step
000001 : 0.75V
…
111010 : 3.6V
…
[7:2]
Buck3Output[5:0]
Buck3VRC
R/W
R/W
Option
Option
111111 : 3.6V
VRC setting
00 : 50mV/10μs, 01 : 100mV/10μs,
10 : 200mV/10μs, 11 : 400mV/10μs
[1:0]
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RT5028C
Address 04
Bit
BUCKcontrol4
Name
Description
R/W
R/W
Reset Value
Option
Buck4 output voltage regulation
000000 : 0.7V, 50mV per step
000001 : 0.75V
…
[7:2]
Buck4Output[5:0]
111010 : 3.6V
…
111111 : 3.6V
VRC setting
[1:0]
Buck4VRC
00 : 50mV/10μs, 01 : 100mV/10μs,
10 : 200mV/10μs, 11 : 400mV/10μs
R/W
Option
Address 05
Bit
VRC Control
Description
Name
R/W
R/W
Reset Value
Option
Buck1 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
7
6
5
Buck1VRC_EN
Buck2VRC_EN
Buck3VRC_EN
Buck2 VRC
0 - disable - voltage ramps up to target voltage
with one time
1 - enable - voltage ramps up to target voltage
with slope control
R/W
R/W
Option
Option
Buck3 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
Buck4 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
4
Buck4VRC_EN
Reserved
R/W
R/W
Option
0000
[3:0]
Address 06
Bit
BUCK Mode
Description
Name
R/W
R/W
Reset Value
1
Buck1 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
7
6
5
Buck1mode
Buck2 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
Buck2mode
R/W
R/W
1
1
Buck3 mode
0 : Force PWM
Buck3mode
1 : Auto Mode (PSM/PWM)
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DS5028C-03 September 2016
RT5028C
Buck4 mode
4
3
2
1
0
Buck4mode
Buck1oms
Buck2oms
Buck3oms
Buck4oms
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
Buck1 output off mode state
0 : floating
1 : Ground-discharged
Buck2 output off mode state
0 : floating
1 : Ground-discharged
Buck3 output off mode state
0 : floating
1 : Ground-discharged
Buck4 output off mode state
0 : floating
1 : Ground-discharged
Address 07
LDOcontrol1
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO1 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
[6:0]
LDO1OUT[6:0]
R/W
Option
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Address 08
LDOcontrol2
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO2 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
[6:0]
LDO2OUT[6:0]
R/W
Option
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Address 09
LDOcontrol3
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO3 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
[6:0]
LDO3OUT[6:0]
R/W
Option
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
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RT5028C
Address 0A
LDOcontrol4
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO4 output voltage regulation
0000000 : 3 V, 25mV per step
0000001 : 3.025V
...
[6:0]
LDO4OUT[6:0]
R/W
Option
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Address 0B
LDOcontrol5
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO5 output voltage regulation
0000000 : 3V, 25mV per step
0000001 : 3.025V
...
[6:0]
LDO5OUT[6:0]
R/W
Option
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Address 0C
LDOcontrol6
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO6 output voltage regulation
0000000 : 3.0V, 25mV per step
0000001 : 3.025V
...
[6:0]
LDO6OUT[6:0]
R/W
Option
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Address 0D
LDOcontrol7
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO7output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
[6:0]
LDO7UT[6:0]
R/W
Option
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
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DS5028C-03 September 2016
RT5028C
Address 0E
LDOcontrol8
Description
Bit
7
Name
R/W
R/W
Reset Value
0
Reserved
LDO8utput voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
[6:0]
LDO8T[6:0]
R/W
Option
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Address 0F
LDOs off mode state
Description
Bit
Name
R/W
R/W
Reset Value
1
LDO8 output off mode state
0 : floating
1 : Ground-discharged
7
LDO8oms
LDO7oms
LDO6oms
LDO5oms
LDO4oms
LDO3oms
LDO2oms
LDO1ms
LDO7 output off mode state
0 : floating
1 : Ground-discharged
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
LDO6 output off mode state
0 : floating
1 : Ground-discharged
LDO5 output off mode state
0 : floating
1 : Ground-discharged
LDO4 output off mode state
0 : floating
1 : Ground-discharged
LDO3 output off mode state
0 : floating
1 : Ground-discharged
LDO2 output off mode state
0 : floating
1 : Ground-discharged
LDO1output off mode state
0 : floating
1 : Ground-discharged
Address 10
REBOOT/PWRHOLD delay time control
Description
Bit
Name
R/W
R/W
Reset Value
Option
Delayed2 setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
[7:6]
Delayed2[1:0]
Delayed1[1:0]
Delayed1 setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
[5:4]
R/W
Option
THOLD setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
[3:2]
1
THOLD[1:0]
Reserved
R/W
R/W
Option
0
Ignore THOLD Time.
0
DisTHOLD
0 : Keep PWRHOLD function.
1 : Ignore PWRHOLD function.
R/W
Option
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27
RT5028C
Address 11
ON Event Setting
Description
Bit
Name
R/W
R
Reset Value
111
Powered on because of
000 : PWRON key-pressed
001 : VIN plugged in
[7:5]
On_Event
010 : from REBOOT pin event
111 : No event happen
[4:0]
Reserved
R/W
R/W
0
Address 12
VIN UVLO/Buck On/Off
Description
Bit
Name
Reset Value
VIN UVLO 2.8V to 3.5V per 0.1V to power off
PMIC
000 : 2.8V
001 : 2.9V
010 : 3V
011 : 3.1V (Default)
100 : 3.2V
101 : 3.3V
110 : 3.4V
111 : 3.5V
[7:5]
VOFF setting
R/W
Option
4
3
Reserved
Buck4
R/W
R/W
0
Buck4 control
(0 : Disable Buck4/1 : Enable Buck4)
Option
Buck3 control
(0 : Disable Buck3/1 : Enable Buck3)
2
1
0
Buck3
Buck2
Buck1
R/W
R/W
R/W
Option
Option
Option
Buck2 control
(0 : Disable Buck2/1 : Enable Buck2)
Buck1 control
(0 : Disable Buck1/1 : Enable Buck1)
Address 13
LDOs On/Off
Description
Bit
Name
R/W
R/W
Reset Value
Option
LDO8 control
(0 : Disable LDO8 / 1 : Enable LDO8)
7
LDO8
LDO7
LDO6
LDO5
LDO4
LDO3
LDO2
LDO1
LDO7 control
(0 : Disable LDO7 / 1 : Enable LDO7)
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Option
Option
Option
Option
Option
Option
Option
LDO6 control
(0 : Disable LDO6 / 1 : Enable LDO6)
LDO5 control
(0 : Disable LDO5 / 1 : Enable LDO5)
LDO4 control (0 : Disable LDO4 / 1 : Enable
LDO4)
LDO3 control
(0 : Disable LDO3 / 1 : Enable LDO3)
LDO2 control
(0 : Disable LDO2 / 1 : Enable LDO2)
LDO1 control
(0 : Disable LDO1 / 1 : Enable LDO1)
Copyright 2016 Richtek Technology Corporation. All rights reserved.
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28
DS5028C-03 September 2016
RT5028C
PWRON(Power On Key) time Parameters
Setting / RESET delay
Address 14
Bit
Name
Description
R/W
R/W
Reset Value
Option
Startup time setting
00 : 100us (pressing time - low level)
01 : 100ms
[7:6]
START_TIME
10 : 1s
11 : 2s
Long-press time setting (after Power-On,
00 : 1s (falling edge to rising edge)
01 : 1.5s
10 : 2s
11 : 2.5s
[5:4]
L_PRESS_TIME
Sending short/long-press IRQ to CPU
ex :1.5s
R/W
Option
=> low time < 1.5s (short IRQ)
=> low time > 1.5s but < 6s(shutdown time)
(long IRQ)
=> low time > 6s(shutdown time) (shutdown)
Key-press forced shutdown time setting
00 : 4s (pressing time : low level)
[3:2]
[1:0]
SHDN_PRESS
RESET_DLY
01 : 6s
10 : 8s
11 : 10s
R/W
R/W
Option
Option
RESET signal delay after the last power startup
is done
00 : 10ms
01 : 50ms
10 : 100ms
11 : 200ms
Address 15
SHDN Control
Description
Bit
Name
Read/Write
R/W
Reset Value
Option
Power Off setting by CPU, after set, 100ms
delayed power off
0 : Normal operation
7
SHDN_CTRL
1 : Disable the PMIC output
Disable Buck/LDO only for normal power off
(SHDN_CTRL=1)
6
SHDN_TIMING
0 : disable at the same time
1 : contrary to the startup timing
(first_on-last_off)
R/W
Option
Delayed shutdown time after send the
(PWRON)key-press-forced-shutdown IRQ
(when IRQ is disable, there is no delay)
[5:4]
[3:0]
SHDN_DLYTIME
Reserved
00 : 100ms
01 : 500ms
10 : 1s
R/W
R/W
Option
0000
11 : 2s
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RT5028C
Address 16
Powered off conditions enable setting
Description
Bit
Name
Read/Write
R/W
Reset Value
0
Buck1 output voltage low SHDN
0 : disable this event. 1 : enable this event
7
BCK1LV_ENSHDN
Buck2 output voltage low SHDN
0 : disable this event. 1 : enable this event
6
5
4
3
2
BCK2LV_ENSHDN
BCK3LV_ENSHDN
BCK4LV_ENSHDN
PWRON_ENSHDN
OT_ENSHDN
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
Buck3 output voltage low SHDN
0 : disable this event. 1 : enable this event
Buck4 output voltage low SHDN
0 : disable this event. 1 : enable this event
PWRON key-pressed forced SHDN
0 : disable this event. 1 : enable this event
Over temperature SHDN
0 : disable this event. 1 : enable this event
VIN voltage low (VOFF) (Set by reg) SHDN
0 : disable this event. 1 : enable this event
1
0
VINLV_ENSHDN
Reserved
R/W
R/W
0
0
Address 17
OFF Event (Only reset by POR)
Description
Bit
Name
Read/Write
Reset Value
Powered off because of (Only shows last
power-off event)
0000 : VIN voltage low (VOFF) (Set by reg)
0001 : Buck1 output voltage low
0010 : Buck2 output voltage low
0011 : Buck3 output voltage low
0100 : PWRON key-pressed forced shutdown
0101 : Power Off register setting
0110 : Over temperature event
0111 : Reboot restart.
[7:4]
OFF_Event
R
1111
1000 : Buck4 output voltage low
1001 : PWR_HOLD fail.
1010 : No event happen.
….
1111 : No event happen
[3:0]
Reserved
R
0000
0
16 bytes registers Data Cache (Only reset by
POR)
Address 18 to 27
R/W
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DS5028C-03 September 2016
RT5028C
IRQ_PMIC (Power Channels)
IRQ Enable1
Address 28
Bit
Name
Description
Read/Write
Reset Value
1
Internal over-temperature was triggered, IRQ
enable
7
OT_IRQ
R/W
R/W
R/W
R/W
R/W
R/W
Buck1 output voltage equal 66% x VTarget , IRQ
enable
6
5
4
3
2
Bck1LV_IRQ
Bck2LV_IRQ
Bck3LV_IRQ
Bck4LV_IRQ
PWRONSP_IRQ
1
1
1
1
0
Buck2 output voltage equal 66% x VTarget, IRQ
enable
Buck3 output voltage equal 66% x VTarget, IRQ
enable
Buck4 output voltage equal 66% x VTarget, IRQ
enable
PWRON short press, IRQ enable
(32μs deglitch time)
PWRON long press, IRQ enable
(32μs deglitch time)
1
0
PWRONLP_IRQ
SYSLV_IRQ
R/W
R/W
0
0
VIN voltage is lower than VOFF, IRQ enable
IRQ Status1
Address 29
Bit
7
Name
Description
Read/Write
Reset Value
OT
Internal over-temperature
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
6
Bck1LV
Bck2LV
Bck3LV
Bck4LV
PWRONSP
PWRONLP
VINLV
Buck1 output voltage equal 66% x VTarget
Buck2 output voltage equal 66% x VTarget
Buck3 output voltage equal 66% x VTarget
Buck4 output voltage equal 66% x VTarget
PWRON short press (32μs deglitch time)
PWRON long press (32μs deglitch time)
VIN voltage is lower than VOFF
IRQ Enable2
5
4
3
2
1
0
Address 2A
Bit
7
Name
Description
Read/Write
R/W
Reset Value
KPSHDN_IRQ
PWRONR_IRQ
PWRONF_IRQ
Reserved
Key-press forced shutdown, IRQ enable
PWRON press rising edge, IRQ enable
PWRON press falling edge, IRQ enable
1
0
6
R/W
5
R/W
0
[4:0]
R
0000
Address 2B
IRQ Status2
Bit
7
Name
Description
Read/Write
Reset Value
KPSHDN
PWRONR
PWRONF
Reserved
OTW125
OTW100
Key-press forced shutdown
PWRON press rising edge
PWRON press falling edge
R
R
R
R
R
R
0
0
6
5
0
[4:2]
1
000
0
Internal 125°C pre-warning over-temperature.
Internal 100°C pre-warning over-temperature.
0
0
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RT5028C
Address 2C
PMU On/Off Sequence1
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
Bit
Name
Read/Write
Reset Value
[7:4]
[3:0]
Buck2_Seq[3:0]
Buck1_Seq[3:0]
Setting Buck2 on/off sequence priority
Setting Buck1 on/off sequence priority
PMU On/Off Sequence2
R/W
R/W
Option
Option
Address 2D
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
Bit
Name
Read/Write
Reset Value
[7:4]
[3:0]
Buck4_Seq[3:0]
Buck3_Seq[3:0]
Setting Buck4 on/off sequence priority
Setting Buck3 on/off sequence priority
PMU On/Off Sequence3
R/W
R/W
Option
Option
Address 2E
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
Bit
Name
Read/Write
Reset Value
[7:4]
[3:0]
LDO2_Seq[3:0]
LDO1_Seq[3:0]
Setting LDO2 on/off sequence priority
Setting LDO1 on/off sequence priority
PMU On/Off Sequence4
R/W
R/W
Option
Option
Address 2F
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
Bit
Name
Read/Write
Reset Value
[7:4]
[3:0]
LDO4_Seq[3:0]
LDO3_Seq[3:0]
Setting LDO4 on/off sequence priority
Setting LDO3 on/off sequence priority
PMU On/Off Sequence5
R/W
R/W
Option
Option
Address 30
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
Bit
Name
Read/Write
Reset Value
[7:4]
[3:0]
LDO6_Seq[3:0]
LDO5_Seq[3:0]
Setting LDO6 on/off sequence priority
Setting LDO5 on/off sequence priority
PMU On/Off Sequence5
R/W
R/W
Option
Option
Address 31
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
Bit
Name
Read/Write
Reset Value
[7:4]
[3:0]
LDO8_Seq[3:0]
LDO7_Seq[3:0]
Setting LDO8 on/off sequence priority
Setting LDO7 on/off sequence priority
Soft-Start Control
R/W
R/W
Option
Option
Address 32
Bit
Name
Reserved
Description
Read/Write
R
Reset Value
Option
[7:6]
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DS5028C-03 September 2016
RT5028C
0000 : First turn on channel decide the
RESET_DLY time.
0001 : Buck1 decide the RESET_DLY time.
….
0100 : Buck1 decide the RESET_DLY time.
0101 : LDO1 decide the RESET_DLY time.
….
Soft-Start End Control
@ MASK_GPIO = 0
(External Enable pin
define)
[5:2]
R/W
Option
1100 : LDO8 decide the RESET_DLY time.
….
1111 : LDO8 decide the RESET_DLY time.
Voltage Level
00 : When output voltage arrives to 80%
VTarget, next channel will turn on.
Soft-start time interval (TSS) :
01 : 1ms
Soft-Start Voltage level
/ time soft-start control.
[1:0]
R/W
Option
10 : 4ms
11 : 8ms
Address 33
Buck Syn-Clock Control
Description
Bit
Name
Read/Write Reset Value
VCO input voltage slop.
00: 25mV/10μs, 01: 25mV/20μs
10: 25mV/40μs, 11: 25mV/80μs
Note :
The VCO’s voltage input range is 0.375V to
1.8V and the output frequency is 450kHz to
2MHz.
[7:6]
VCO_VRC
VCO_DVS
R/W
R/W
Option
Option
VCO input voltage DVS control
000000 : 0.375V (450kHz)
………
111001 : 1.8V (2MHz)
………
[5:0]
111111 : 1.8V (2MHz)
Address 34
Buck Syn-Clock Spread Spectrum Control
Description
Bit
Name
Read/Write Reset Value
[7:1]
Reserved
R/W
0000000
Buck Clock Spread Spectrum Control
0 : Disable spread spectrum function.
1 : Turn on spread spectrum function.
0
SSOSC
R/W
Option
Address 3A
EEPROM (MTP) Control
Description
Bit
[7:6]
5
Name
Read/Write Reset Value
Reserved
R/W
R
00
0
MTP Page 2 Read
MTP Page 1 Read
Reserved
Read MTP Page 2
Read MTP Page 1
4
R
0
[3:2]
R/W
00
Write MTP Page 2, and MTP also needs to be
logic high.
1
0
MTP Page 2 write
MTP Page 1 write
W
W
0
0
Write MTP Page 1, and MTP also needs to be
logic high.
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33
RT5028C
Table 3. I2C to MTP Mapping Table
MTP Page-1
MTP
Address
I2C Register Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Meaning
BUCKcontrol1
Buck1Output[5:0]
Buck1VRC
0x00
0x01
0x02
0x03
0x04
Default
0
R/W
A
1
R/W
A
0
R/W
A
1
R/W
A
0
1
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
R/W
A
BUCKcontrol2
Meaning
Buck2Output[5:0]
Buck2VRC
0x01
0x02
0x03
Default
0
R/W
A
1
R/W
A
1
R/W
A
0
R/W
A
0
1
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
R/W
A
BUCKcontrol3
Meaning
Buck3Output[5:0]
Buck3VRC
Default
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
1
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
R/W
A
BUCKcontrol4
Meaning
Buck4Output[5:0]
Buck4VRC
Default
1
R/W
A
1
R/W
A
0
R/W
A
1
R/W
A
0
R/W
1
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
A
VRC Control
Buck1V Buck2V Buck3V Buck4V
RC_EN RC_EN RC_EN RC_EN
Meaning
Reserved Reserved Reserved Reserved
0x0D
0x05
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Condition
A
A
A
A
A
A
A
A
Function
Meaning
LDOcontrol1
Reserved
LDO1OUT[6:0]
0x04
0x07
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
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DS5028C-03 September 2016
RT5028C
MTP
Address
I2C Register Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Meaning
LDOcontrol2
Reserved
LDO2OUT[6:0]
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Default
Read/Write
Reset Condition
Function
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
LDOcontrol3
Meaning
Reserved
LDO3OUT[6:0]
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
LDOcontrol4
Meaning
Reserved
LDO4OUT[6:0]
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
LDOcontrol5
Meaning
Reserved
LDO5OUT[6:0]
Default
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
LDOcontrol6
Meaning
Reserved
LDO6OUT[6:0]
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
LDOcontrol7
Meaning
Reserved
LDO7OUT[6:0]
Default
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
LDOcontrol8
Meaning
Reserved
LDO8OUT[6:0]
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
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35
RT5028C
MTP
Address
I2C Register Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Meaning
VIN UVLO (update default value after power on)
VOFF setting
Reserved Reserved Reserved Reserved Reserved
0x0C
0x12
Default
1
R/W
A
1
R/W
A
1
R/W
A
0
R/W
A
0
R/W
B
0
R/W
B
0
R/W
B
0
R/W
B
Read/Write
Reset Condition
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
No
mapping
0x0F
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
36
DS5028C-03 September 2016
RT5028C
MTP Page-2
Bit5
MTP
Address
I2C Register Address
Bit7
Bit6
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Meaning
REBOOT/PWRHOLD delay time control
Delayed1[1:0] THOLD
Delayed2[1:0]
Reserved DisTHOLD
0x00
0x01
0x10
0x14
Default
Read/Write
Reset Condition
Function
1
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
0
R/W
A
1
R/W
A
R/W
A
PWRON time Parameters Setting / RESET delay
L_PRESS_TIME SHDN_PRESS
Meaning
START_TIME
RESET_DLY
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
SHDN Control
SHDN_
CTRL
SHDN_
TIMING
Meaning
SHDN_DLYTIME
Reserved Reserved Reserved Reserved
0x02
0x15
Default
Read/Write
Reset Condition
Function
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
PMU On/Off Sequence1
Meaning
Buck2_Seq[3:0]
Buck1_Seq[3:0]
0x03
0x04
0x05
0x2C
0x2D
0x2E
Default
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
Read/Write
Reset Condition
Function
PMU On/Off Sequence2
Meaning
Buck4_Seq[3:0]
Buck3_Seq[3:0]
Default
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
PMU On/Off Sequence3
Meaning
LDO2_Seq[3:0]
LDO1_Seq[3:0]
Default
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
www.richtek.com
37
RT5028C
MTP
Address
I2C Register Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Meaning
PMU On/Off Sequence4
LDO4_Seq[3:0]
LDO3_Seq[3:0]
0x06
0x2F
0x30
0x31
0x32
0x33
0x34
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
PMU On/Off Sequence5
Meaning
LDO6_Seq[3:0]
LDO5_Seq[3:0]
0x07
0x08
0x09
0x0A
0x0B
0x0C
Default
0
R/W
A
0
R/W
A
1
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
PMU On/Off Sequence6
Meaning
LDO8_Seq[3:0]
LDO7_Seq[3:0]
Default
0
R/W
A
0
R/W
A
1
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
1
R/W
A
Read/Write
Reset Condition
Function
Soft-Start Control
Soft-Start End Select @MASK_GPIO=1
Meaning
Reversed Reversed
Soft-Start Control
Default
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
Buck Syn-Clock Control
VCO_DVS
Meaning
VCO_VRC
Default
0
R/W
A
0
R/W
A
1
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
Buck Syn-Clock Spread Spectrum Control
Reversed Reversed Reversed Reversed Reversed Reversed Reversed SSOSC
Meaning
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
1
R/W
A
Read/Write
Reset Condition
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
No
mapping
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
38
DS5028C-03 September 2016
RT5028C
MTP
Address
I2C Register Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Meaning
x
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
No
mapping
0x0D
0x0E
0x0F
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
No
mapping
Default
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
No
Default
mapping
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
0
R/W
A
Read/Write
Reset Condition
Reset Condition
A
B
Reset by MTP (Register 0x12 VOFF Setting).
Reset when VIN <1.7V.
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5028C-03 September 2016
www.richtek.com
39
RT5028C
Outline Dimension
1
2
1
2
DETAILA
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.700
0.000
0.175
0.150
6.900
5.150
6.900
5.150
0.800
0.050
0.250
0.250
7.100
5.250
7.100
5.250
0.028
0.000
0.007
0.006
0.272
0.203
0.272
0.203
0.031
0.002
0.010
0.010
0.280
0.207
0.280
0.207
D
D2
E
E2
e
0.400
0.016
L
0.350
0.450
0.014
0.018
W-Type 56L QFN 7x7 Package
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
40
DS5028C-03 September 2016
RT5028C
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS5028C-03 September 2016
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41
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