RT6541A_技术文档

®

RT6541A

High Efficiency Single Synchronous Buck PWM Controller

General Description

Features

^Intel SKL VR support

The RT6541A PWM controller provides high efficiency,

excellent transient response, and highDC output accuracy

needed for stepping down high voltage batteries to

generate low voltage CPU core, I/O, and chipset RAM

supplies in notebook computers.

^Built-in 1% Reference Voltage

^2-Bit Programmable Output Voltage with Integrated

Transition Support

^Support Intel LPM (Low-Power Mode) Feature

^4700ppm/°C Programmable Current Limit by Low-

Side R_DS(ON)Sensing

The RT6541A supports on chip voltage programming

function between 0.8V and 1.05V by controllingGX digital

inputs.

^3V to 26V Battery Input Range

^Internal Voltage Ramp Soft-Start Control

^Drives Large Synchronous Rectifier FETs

^Integrated Boost Switch

The constant-on-time PWM control scheme handles wide

input/output voltage ratios with ease and provides 100ns

“instant-on” response to load transients while maintaining

a relatively constant switching frequency.

^Over/Under-Voltage Protection

 Thermal Shutdown

 Power Good Indicator

The RT6541A achieves high efficiency at a reduced cost

by eliminating the current-sense resistor found in

traditional current-mode PWMs. Efficiency is further

enhanced by its ability to drive very large synchronous

rectifier MOSFETs and enter diode emulation mode at

light load condition. The buck conversion allows this device

to directly step down high voltage batteries at the highest

possible efficiency. The RT6541Ais intended for CPU core,

chipset, DRAM, or other low voltage supplies as low as

0.8V.

 RoHS Compliant and Halogen Free

 Tiny 14-Lead WDFN Package

Applications

 Notebook Computers

 CPU/GPU Core Supply

 Chipset/RAM Supply

 GenericDC-DC Power Regulator

The RT6541Ais available in a WDFN-14L 3x2 package.

Simplified Application Circuit

V

IN

RT6541A

Q1

C

IN

R4

R3

V

CC

UGATE

VCC

C

BYPASS

BOOT

C1

R2

PGOOD

EN

L

OUT

PHASE

LGATE

V

OUT

R5*

C2*

C

OUT

Q2

R

CS

LPM

CS

RGND

FB

GND

MODE

G0

G1

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

1

RT6541A

Ordering Information

RT6541A

Pin Configuration

(TOP VIEW)

Package Type

QW : WDFN-14L 3x2 (W-Type)

(Exposed Pad-Option 1)

1

2

3

4

5

6

7

14

13

12

11

10

9

MODE

PGOOD

EN

CS

FB

RGND

G1

G0

VCC

LGATE

GND

LPM

BOOT

UGATE

PHASE

Lead Plating System

G : Green (Halogen Free and Pb Free)

15

8

Note :

Richtek products are :

WDFN-14L 3x2

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Marking Information

0T : Product Code

W : Date Code

0TW

Functional Pin Description

Pin No.

Pin Name

MODE

PGOOD

EN

Pin Function

1

2

3

4

5

6

VCCIO/PCH_Core/EDRAM select pin.

Open drain power good indicator. High impedance indicates power is good.

PWM enable control input. Do not leave this pin floating.

Low power mode control pin.

LPM

BOOT

UGATE

BOOT bootstrap supply for high-side gate driver.

High-side gate driver output.

Switch node. External inductor connection for VDDQ and behave as the

current sense comparator input for Low-Side MOSFET R_DS(ON₎sensing.

7

PHASE

8

LGATE

VCC

G0

Low-side gate driver output.

9

Supply voltage input for the analog supply and LGATE gate driver.

2-bit input pin.

10

11

12

13

G1

2-bit input pin.

RGND

FB

Remote voltage sense ground pin.

Output voltage feedback input. Connect VOUT to converter output node.

Current limit threshold setting input. Connect a setting resistor to GND and

the current limit threshold is equal to 1/10 of the voltage at this pin.

14

CS

Ground. The Exposed Pad must be soldered to a large PCB and connected

to GND for maximum power dissipation.

15 (Exposed Pad) GND

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

2

DS6541A-02 September 2019

RT6541A

Functional Block Diagram

BOOT

TRIG

PHASE

On-time compute

One shot

R

S

UGATE

PHASE

DRV

Q

Comp

-

+

FB

Min Toff

TRIG

One shot

Q

VCC

LGATE

GND

DRV

Latch

+

OV

UV

S1

Q

-

1.2V

0.3V

ZCD

+

-

Latch

S1

-

+

PGOOD

-

+

0.675V

LPM

G0

Voltage

Programmer

Thermal

Shutdown

SS Timer

DEM

G1

10µA

MODE

OC threshold

1/10

+

RGND

EN

CS

-

Operation

The RT6541A is a constant on-time synchronous step-

down controller. In normal operation, the high-side N-

MOSFET is turned on when the output voltage is lower

than VREF, and is turned off after the internal one-shot

timer expires. While the high-side N-MOSFET is turned

off, the low-side N-MOSFET is turned on to conduct the

inductor current until next cycle begins.

Current Limit

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASE is above the current limit threshold, the

PWM is not allowed to initiate a new cycle. The current

limit threshold can be set with an external voltage setting

resistor on the CS pin.

Soft-Start (SS)

Over-Voltage Protection (OVP) & Under-Voltage

Protection (UVP)

For internal soft-start function, an internal current source

charges an internal capacitor to build the soft-start ramp

voltage. The output voltage will track the internal ramp

voltage during soft-start interval.

The output voltage is continuously monitored for over-

voltage and under-voltage protection. When the output

voltage exceeds 1.2V (typ.), UGATE goes low and LGATE

is forced high. When the feedback voltage is less than

0.3V (typ.), under-voltage protection is triggered and then

both UGATE and LGATE gate drivers are forced low. The

controller is latched until VCC is re-supplied and exceeds

the POR rising threshold voltage or EN is reset.

PGOOD

The power good output is an open-drain architecture. When

the soft-start is finished, the PGOOD open-drain output

will be high impedance.

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

3

RT6541A

Absolute Maximum Ratings (Note 1)

 VCC, VOUT, PGOOD, EN, CS, G0, G1, LPM to GND ----------------------------------------------------- −0.3V to 6.5V

 PHASE to GND

DC----------------------------------------------------------------------------------------------------------------------- −0.3V to 32V

< 100ns ---------------------------------------------------------------------------------------------------------------- −8V to 38V

 BOOT to PHASE

DC----------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 100ns ---------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 UGATE to PHASE

DC----------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 100ns ---------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 LGATE toGND

DC----------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 100ns ---------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

 Power Dissipation, P_D@ T_A= 25°C

WDFN-14L 3x2 ------------------------------------------------------------------------------------------------------- 2.71W

 Package Thermal Resistance (Note 2)

WDFN-14L 3x2, θ_JA------------------------------------------------------------------------------------------------- 36.9°C/W

WDFN-14L 3x2, θ_JC------------------------------------------------------------------------------------------------- 10.9°C/W

 Junction Temperature ----------------------------------------------------------------------------------------------- 150°C

 Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------- 260°C

 Storage Temperature Range -------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Input Voltage, PHASE --------------------------------------------------------------------------------------------- 3V to 26V

 Control Voltage, V_CC----------------------------------------------------------------------------------------------- 4.5V to 5.5V

 Junction Temperature Range-------------------------------------------------------------------------------------- −40°C to 125°C

Electrical Characteristics

(V_CC= 5V, V_IN= 8V, V_EN= 5V, V_CS= 1V, T_A= 25°C, unless otherwise specified)

Parameter

PWM Controller

Supply Voltage

Symbol

Test Conditions

Min

Typ

Max

Unit

V_CC

4.5

--

5.5

--

V

FB forced above the regulation point,

I_Q

140

A

EN = 5V,

= 5V

LPM

V_CCQuiescent Supply

Current

FB forced above the regulation point,

I_{Q_LPM}

EN = 5V,

Mode3

= 0V, only Mode1,

--

30

--

A

LPM

V_CCShutdown Supply

Current

I_SD

EN = 0V

--

10

A

VFB Error Comparator

Threshold

G0 = 5V, G1 = 5V, MODE = floating

0.5

0.5

%

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

4

DS6541A-02 September 2019

RT6541A

Parameter

Switching Frequency

Minimum Off-Time

Current Sensing

CS Current

Symbol

Test Conditions

V_IN= 12V , CCM

Min

--

Typ

560

400

Max

--

Unit

kHz

ns

250

550

9

--

10

4700

--

11

--

A

PPM/C

mV

CS Current TC

Zero Crossing Threshold

Protection Function

Current Limit Threshold Offset

GND  PHASE

8

4

GND  PHASE = VCS/10

PHASE  GND = VCS/10

10

15

--

10

15

mV

Negative Current Limit

Threshold Offset

UV Trip Level

UV detect, falling edge

V_FB= 0.2V

0.25

--

0.3

5

0.35

--

V

s

V

UVP Delay

OV Trip Level

OV detect, rising edge

V_FB= 1.31V

1.14

--

1.2

5

1.26

--

OVP Delay

s

V

V_CCUVLO Threshold

V_CCUVLO Hysteresis

Thermal Shutdown

Start Up & VID

Rising edge

3.9

--

4.2

100

150

4.5

--

mV

C

Latch

--

V_OUTSoft-Start

EN high to V_OUT= 1.05V

From EN = high

--

1.2

3.4

--

ms

Start Up Blanking Time

Driver On-Resistance

UGATE Driver (pull up)

UGATE Driver (sink)

LGATE Driver (pull up)

LGATE Driver (pull down)

R_UGATEsr

R_UGATEsk

R_LGATEsr

R_LGATEsk

BOOT-PHASE forced to 5V

LGATE, high state

LGATE, low state

--

2.5

1.5

2.5

0.8

20

5

3



5

1.6

--

UGATE rising

Dead Time

ns

LGATE rising

30

--

Internal Boost Charging Switch

On-Resistance

VCC to BOOT, 10mA

--

80



LOGIC I/O

Controller OFF

Controller ON

Logic Low

--

1.2

--

0.4

--

EN Input Voltage

V

0.3

--

G0, G1, LPM Input Voltage

MODE Select

Logic High

0.8

--

Logic-Low VCCIO

0.8

--

Logic-High EDRAM/EOPIO

2.7

1.8

V

Float

V_CCPRIM_Core

2.2

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

5

RT6541A

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

PGOOD (upper side threshold decide by OV threshold)

Trip Threshold (falling)

Propagation Delay

Hys = 3%

0.625 0.675 0.725

V

Falling edge, with respect to PGOOD

threshold

--

3

--

s

Output Low Voltage

Leakage Current

I_SINK= 1mA

--

0.4

1

V

High state, forced to 5.0V

A

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Note 2. θ_JAis measured under natural convection (still air) at T_A= 25°C with the component mounted on a high effective-

thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θ_JCis measured at the

exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

6

DS6541A-02 September 2019

RT6541A

Typical Application Circuit

V

IN

SM3380EHQG

0

RT6541A

20µF

6

5

9

UGATE

VCC

V

: 0.95V/5.35A

: 1V/3.3A

VCCIO

0

1µF/16V

VCCOPC

BOOT

: 1V/3.2A

VCCEOPIO

100k

0.1µF

2

PGOOD

1µH

R5*

C2*

7

8

PHASE

LGATE

On

3

EN

220µF x 2

Off

4

156k

LPM

RGND

FB

14

CS

12

15 (Exposed Pad)

1

GND

MODE

13

10

11

G0

G1

I

= (0% to 70%) x I

MAX

LOAD

(30% to 100%) x I

MAX

SR = 2.5A/µs

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

7

RT6541A

Typical Operating Characteristics

Efficiency vs. Output Current

Switching Frequency vs. Output Current

100

800

700

600

500

400

300

200

100

0

V_CC= V_EN= 5V, VID = 1V

90

80

V_IN= 5V

V_IN= 7.4V

V_IN= 12V

V_IN= 20V

V_IN= 5V

V_IN= 7.4V

V_IN= 12V

V_IN= 20V

70

60

50

V_CC= V_EN= 5V, VID = 1V

40

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

Output Voltage vs. Output Current

Quiescent Current vs. Input Voltage

200

180

160

140

120

100

80

1.06

1.04

1.02

1.00

0.98

0.96

LPM= 1

V_IN= 20V

V_IN= 12V

V_IN= 7.4V

V_IN= 5V

60

LPM= 0

40

20

V_CC= V_EN= 5V, No Switching

V_CC= V_EN= 5V, VID = 1V

0.1 10

0

5

10

15

20

25

0.001

0.01

1

Input Voltage (V)

Output Current (A)

Shutdown Current vs. Input Voltage

Load Transient Response

6

5

4

3

2

1

V_IN= 12V, V_CC= V_EN= 5V, V_OUT= 1.05V,

I_LOAD= 0A to 4.55A

V_OUT

(40mV/Div)

I_LOAD

(5V/Div)

PHASE

(20V/Div)

LGATE

(50V/Div)

V_CC= 5V, V_EN= 0V

0

5

10

15

20

25

Time (500μs/Div)

Input Voltage (V)

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

8

DS6541A-02 September 2019

RT6541A

Power On from EN

Power Off from EN



V_IN= 12V, V_CC= 5V, V_EN= 0V 5V,VID = 1.05V,



V_IN= 12V, V_CC= 5V, V_EN= 5V 0V,VID = 1.05V,

I_Load= 0.1A

I_LOAD= 0.1A

V_OUT

(1V/Div)

V_OUT

(1V/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

EN

(5V/Div)

PHASE

(20V/Div)

EN

(5V/Div)

PHASE

(20V/Div)

Time (500μs/Div)

Dynamic VID Up

Dynamic VID Down

No load, V_IN= 12V, V_CC= V_EN= 5V,

V_OUT= 0.8V to 1.05V

No load, V_IN= 12V, V_CC= V_EN= 5V

V_OUT= 1.05V to 0.8V

V_OUT

(500mV/Div)

V_OUT

(500mV/Div)

G0 = G1

(5V/Div)

G0 = G1

(5V/Div)

LGATE

(10V/Div)

PHASE

(20V/Div)

Time (20μs/Div)

Over-Voltage Protection

Under-Voltage Protection

No load, V_IN= 12V, V_CC= V_EN= 5V

V_OUT= 1.05V

V_OUT

(1V/Div)

V_OUT

(500mV/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

PHASE

(20V/Div)

LGATE

(5V/Div)

V_OUT= 1.05V

No load, V_IN= 12V, V_CC= V_EN= 5V

(10V/Div)

Time (20μs/Div)

Time (100μs/Div)

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

9

RT6541A

Application Information

The RT6541A is of a constant on-time PWM controller

which provides four DC feedback voltages by controlling

the G0 and G1 digital input. The constant on-time PWM

control

Diode-Emulation Mode

The RT6541A automatically reduces switching frequency

at light load conditions to maintain high efficiency. This

reduction of frequency is achieved smoothly and without

increasing V_OUTripple or load regulation. As the output

current decreases from heavy load condition, the inductor

current is also reduced, and eventually comes to the point

that its valley touches zero current, which is the boundary

between continuous conduction and discontinuous

conduction modes. By emulating the behavior of diodes,

the low-side MOSFET allows only partial negative current

when the inductor freewheeling current becomes negative.

As the load current is further decreased, it takes longer

and longer to discharge the output capacitor to the level

that is required for the next “ON” cycle. The on-time is

kept the same as that in the heavy-load condition. In

reverse, when the output current increases from light load

to heavy load, the switching frequency increases to the

preset value as the inductor current reaches the continuous

condition. The transition load point to the light-load

operation can be calculated as follows (Figure 1) :

scheme handles wide input / output ratios with ease and

provides 100ns “instant-on” response to load steps while

maintaining a relatively constant operating frequency and

inductor operating point over a wide range of input voltages.

The topology circumvents the poor load transient timing

problems of fixed-frequency current mode PWMs, while

avoiding the problems caused by widely varying switching

frequencies in conventional constant on-time and constant

off-time PWM schemes. The DRV^TMmode PWM

modulator is specifically designed to have better noise

immunity for such a single output application.

PWM Operation

The Mach Response^TM, DRV^TMmode controller relies on

the output filter capacitor's Effective Series Resistance

(ESR) to act as a current sense resistor, so the output

ripple voltage provides the PWM ramp signal. Referring to

the function diagrams of the RT6541A, the synchronous

high-side MOSFET is turned on at the beginning of each

cycle. After the internal one-shot timer expires, the high-

side MOSFET is turned off. The pulse width of this one

shot is determined by the converter's input and output

voltages to keep the frequency fairly constant over the

input voltage range. Another one-shot sets a minimum

off-time (400ns typ.)

(V_IN V_OUT

)

I_LOAD



t_ON

2L

where t_ONis the on-time.

I

L

Slope = (V -V

) / L

IN OUT

I

L_Peak

I

= I

/2

LOAD

L_Peak

t

On-Time Control (t_ON

)

0

t

ON

The on-time one-shot comparator has two inputs. One

input monitors the output voltage, while the other input

samples the input voltage and converts it to a current.

This input voltage proportional current is used to charge

an internal on-time capacitor. The on-time is the time

required for the voltage on this capacitor to charge from

zero volts to V_OUT, thereby making the on-time of the high-

side switch directly proportional to the output voltage and

inversely proportional to the input voltage. The

implementation results in a nearly constant switching

frequency without the need of a clock generator.

Figure 1. Boundary Condition of CCM/DCM

The switching waveforms may appear noisy and

asynchronous when light loading causes diode-emulation

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs inDEM noise

vs. light-load efficiency is made by varying the inductor

value. Generally, low inductor values produce a broader

efficiency vs. load curve, while higher values result in higher

full-load efficiency (assuming that the coil resistance

remains fixed) and less output voltage ripple. The

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

10

DS6541A-02 September 2019

RT6541A

disadvantages for using higher inductor values include

larger physical size and degraded load-transient response

(especially at low input voltage levels).

output voltage is reduced or disabled by using the LPM

pin. While the LPM pin is asserted, the PGOOD output

remains high impedance. The device also achieves a

dynamic output-voltage change by using the G0 and G1

pins. This feature helps the system to minimize power

consumption in standby or idle mode. The M2 mode

provide the full current even if the output voltage is set at

0.7 V in LPM mode.

LPM (Low-Power Mode) and Output Voltage

Setting

The output voltage of the RT6541Ais selected by twoG0

and G1 pins and one LPM pin as listed in Table 1.

The RT6541A has a low power mode (LPM) where the

Table 1. VID Table Definition

VID Setting

Mode

logic

Timing

Slew Rate

(mv/us)

Mode

VR

LPM

V_OUT(V)

(LPM L to H)

G1 logic G0 logic

0

1

0

1

0

1

x

0

1

x

0

1

x

0

1

x

0

1

0

1

x

0

1

0

1

x

0

1

0

1

0(LPM)

0.85

Tramp-up<240us

(0V to 0.975V)

Mode1

VCCIO

0

0.875

0.95

6

15

6

0.975

0.7V(LPM)

0.85

Tramp-up<45us

(0.7V to 1V)

Mode2 VPRIMCORE Floating

0.9

0.95

1

0(LPM)

0.8

VccEDRAM/

VccEOPIO

Tramp-up<240us

(0V to 1.05V)

Mode3

1

0.95

1

1.05

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

11

RT6541A

Output Voltage Transition Operation

Gx

GND

The digital input control pins G0 and G1 allows V_OUTto

transition to both higher and lower values. For a downward

transition, the rapid change of Gx from high to low will

suddenly cause V_FBto drop to a new internal V_REF. At

this time the LGATE will drive high to turn on the low-side

MOSFET and draw current from the output capacitor via

the inductor. LGATE will remain on until V_FBfalls to the

new internal V_REF, at which point a normal UGATE

switching cycle begins, as shown in Figure 2. For a down

transition, the low-side MOSFET remains on until VFB

reaches the new internal V_REF. Thus, the negative inductor

current will be increased. If the negative current become

large enough to triggerNOCP, the low-side MOSFET will

be turned off to prevent large negative current from

damaging the component. Refer to the Negative Over

Current Limit section for a full description.

Final V

REF

V

REF

Initial V

REF

V

FB

UGATE

LGATE

Final V

OUT

V

OUT

Initial V

OUT

Figure 3. Output Voltage Up Transition

If the V_OUTchange is significant, there can be several

consecutive cycle of UGATE on-time followed by

minimum LGATE time. This can cause a rapid increase in

inductor current : typically it only takes a few switching

cycles for inductor current to rise up to the current limit.

At some point the V_FBwill rise up to the new internal

VREF and the UGATE pulses will cease, but the inductor's

LI²energy must then flow into the output capacitor. This

can create a significant overshoot, as shown in Figure 4.

Gx

GND

Initial V

REF

V

REF

Final V

REF

V

FB

UGATE

Gx

GND

Final V

LGATE

REF

Initial V

OUT

V

REF

V

Initial V

OUT

REF

Final V

OUT

V

FB

Figure 2. Output VoltageDown Transition

UGATE

For an upward transition (from lower to higher V_OUT) as

shown in Figure 3,Gx changes from low to high and causes

V_FBto rise to a new internal V_REF. This quickly trips the

V_FBcomparator regardless of whether DEM is active or

not, generating an UGATE on-time and causing a

subsequent LGATE to be turned on. At the end of the

minimum off-time (400ns), if V_FBis still below the new

internal V_REF, another UGATE on-time will be started. This

sequence continues until the FB pin exceeds the new

LGATE

Final V

OUT

V

OUT

Initial V

OUT

Figure 4. Output Voltage Up Transition with

Overshooting

This overshoot can be approximated by the following

equation, where I_CLis the current limit, V_FINALis the

desired set point for the final voltage, L is in μH and C_OUT

is in μF.

internal V_REF

.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

12

DS6541A-02 September 2019

RT6541A

I

L

I_CL²L

C_OUT

2

V_MAX (

) V_FINAL

I

L_Peak

LOAD

LIM

Current Limit Setting (OCP)

The RT6541Ahas a cycle-by-cycle current limiting control.

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at the CS pin is above the current limit threshold,

the PWM is not allowed to initiate a new cycle (Figure.5).

In order to provide both good accuracy and a cost effective

solution, the RT6541A supports temperature compensated

MOSFET R_DS(ON)sensing. The CS pin should be

connected toGNDthrough the trip voltage setting resistor,

R_CS. The 10μA CS terminal source current, I_CS, and the

trip voltage setting resistor, R_CS, set the CS trip voltage,

V_CS, as in the following equation.

t

0

Figure 5. “Vally” Current Limit

Negative Over Current Limit (PWM Only Mode)

The RT6541A supports cycle-by-cycle negative over

current limiting in CCM Mode only. The over current limit

is set to be negative but is the same absolute value as

the positive over current limit. If output voltage continues

to rise, the low-side MOSEFT remains on. Thus, the

inductor current is reduced and reverses direction after it

reaches zero. When there is too much negative current in

the inductor, the low-side MOSFET is turned off and the

current flows towards VIN through the body diode of the

high-side MOSFET. Because this protection limits the

discharge current of the output capacitor, the output voltage

tends to rise, eventually hitting the over-voltage protection

threshold and shutting down the device. If the device hits

the negative over current threshold again before output

voltage is discharged to the target level, the low-side

MOSFET is turned off and the process repeats. It ensures

maximum allowable discharge capability when output

voltage continues to rise. On the other hand, if the output

is discharged to the target level before negative current

threshold is reached, the low-side MOSFET is turned off,

the high-side MOSFET is then turned on, and the device

resumes normal operation.

V_CS(mV) = R_CS(k)10(A)

The Inductor current can be monitored by the voltage

between GND and the PHASE pin. Hence, the PHASE

pin should be connected to the drain terminal of the low-

side MOSFET. ICS has temperature coefficient to

compensate the temperature dependency of the R_DS(ON)

.

GND is used as the positive current sensing node, so

GND should be connected to the source terminal of the

bottom MOSFET.

While the comparison is being done during the OFF state,

V_CSsets the valley level of the inductor current. Thus, the

load current at over-current threshold, I_{LOAD_OC}, can be

calculated as follows :

I_ripple

V_CS

I_{LOAD_OC}





10R_DS(ON)

2

V_CS

(V_IN V_OUT) V_OUT

1

MOSFET Gate Driver (UGATE, LGATE)







10R_DS(ON)2Lf_SW

V

IN

The high-side driver is designed to drive high current, low

R_DS(ON)N-MOSFET(s). When configured as a floating

driver, 5V bias voltage is delivered from the VCC supply.

In an over-current condition, the current to the load exceeds

the current to the output capacitor, thus causing the output

voltage to fall. Eventually the voltage crosses the under-

voltage protection threshold and the device shuts down.

The average drive current is proportional to the gate charge

at V_GS= 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

the BOOT and PHASE pins. Adead time to prevent shoot

through is internally generated between high-side

MOSFET off to low-side MOSFET on, and low-side

MOSFET off to high-side MOSFET on. The low-side driver

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

13

RT6541A

is designed to drive high current, low R_DS(ON)

NMOSFET(s). The internal pull-down transistor that drives

LGATE low is robust, with a 0.8Ω typical on resistance. A

5V bias voltage is delivered from the V_CCsupply. The

instantaneous drive current is supplied by the flying

capacitor between VCC andGND.

Over-Voltage Protection (OVP)

The output voltage can be continuously monitored for over-

voltage protection. When V_FBexceeds 1.2V, over-voltage

protection is triggered and the low-side MOSFET is latched

on. This activates the low-side MOSFET to discharge the

output capacitor. The RT6541A is latched once OVP is

triggered and can only be released by VCC or EN power

on reset. There is a 5μs delay built into the over voltage

protection circuit to prevent false transitions.

For high current applications, some combinations of high

and low-side MOSFETs might be encountered that will

cause excessive gate drain coupling, which can lead to

efficiency killing, EMI-producing shoot through currents.

This is often remedied by adding a resistor in series with

BOOT, which increases the turn-on time of the high-side

MOSFET without degrading the turn-off time, as shown in

Figure 6.

Under-Voltage Protection (UVP)

The output voltage can be continuously monitored for under-

voltage protection. When VFB is less than 0.3V, under-

voltage protection is triggered and then both UGATE and

LGATE gate drivers are forced low. In order to remove the

residual charge on the output capacitor during the under

voltage period, if PHASE is greater than 1V, the LGATE

is forced high until PHASE is lower than 1V. There is a

5μs delay built into the under-voltage protection circuit to

prevent false transitions.During soft-start, the UVP blanking

time is 3.4ms.

V

IN

C

IN

UGATE

Q1

R

BOOT

PHASE

Figure 6. Reducing the UGATE Rise Time

Output Inductor Selection

Power Good Output (PGOOD)

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as follows :

The power good output is an open-drain output and requires

a pull-up resistor. When the feedback voltage is above

1.2V or below 0.3V, PGOOD will be pulled low. PGOOD

is allowed to be high until soft-start ends and the output

reaches 85% of its set voltage. There is a 3μs delay built

into PGOOD circuitry to prevent false transition. When

G0 or G1 changes, PGOOD remains in its present state

for 32 clock cycles. Meanwhile, V_OUTor V_FBregulates to

the new level.

T

(V  V

)

ON

IN

OUT

L 

LIRI

LOAD(MAX)

where LIR is the ratio of peak-to-peak ripple current to the

maximum average inductor current. Select a low pass

inductor having the lowest possible DC resistance that

fits in the allowed dimensions. Ferrite cores are often the

best choice, although powdered iron is inexpensive and

can work well at 200kHz. The core must be large enough

not to saturate at the peak inductor current (I_PEAK) :

LIR

POR , UVLO and Soft-Start

Power On Reset (POR) occurs when VCC rises above

4.2V (typ). After POR is triggered, the RT6541Awill reset

the fault latch and prepare the PWM for operation. Below

3.6V (typ.), the VCC Under-Voltage Lockout (UVLO)

circuitry inhibits switching by keeping UGATE and LGATE

low. A built-in soft-start is used to prevent surge current

from the power supply input after ENis enabled. It clamps

the ramping of the internal reference voltage which is

compared with the FB signal. The typical soft-start duration

is 1.2ms.

I_PEAK I_LOAD(MAX)



I_LOAD(MAX)

2

Output Capacitor Selection

The output filter capacitor must have ESR low enough to

meet output ripple and load transient requirement, yet have

high enough ESR to satisfy stability requirements. Also,

the capacitance must be high enough to absorb the inductor

energy going from a full load to no load condition without

tripping the OVP circuit. For CPU core voltage converters

and other applications where the output is subject to violent

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

14

DS6541A-02 September 2019

RT6541A

load transient, the output capacitor's size depends on how

much ESR is needed to prevent the output from dipping

too low under a load transient. Ignoring the sag due to

finite capacitance :

resistance, θ_JA. The derating curves in Figure 7 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

3.0

Four-Layer PCB

V

PP

2.5

2.0

1.5

1.0

0.5

0.0

ESR 

I

LOAD(MAX)

In non-CPU applications, the output capacitor's size

depends on how much ESR is needed to maintain at an

acceptable level of output voltage ripple :

V

PP

ESR 

LIRI

LOAD(MAX)

Organic semiconductor capacitor(s) or special polymer

capacitor(s) are recommended.

0

25

50

75

100

125

Ambient Temperature (°C)

Thermal Considerations

Figure 7. Derating Curve of Maximum PowerDissipation

The junction temperature should never exceed the

absolute maximum junction temperature T_J(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

Layout Considerations

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to converter

instability. For best performance of the RT6541A, the

following guidelines should be strictly followed.

 Connect an RC low-pass filter from VCC, (1μF and 10Ω

are recommended). Place the filter capacitor close to

the IC.

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction-to-ambient

thermal resistance.

 Keep current limit setting network as close as possible

to the IC. Routing of the network should be kept away

from high voltage switching nodes to prevent it from

coupling.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125°C. The junction-to-ambient thermal

resistance, θ_JA, is highly package dependent. For a

WDFN-14L 3x2 package, the thermal resistance, θ_JA, is

36.9°C/Won a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at T_A= 25°C can be calculated as below :

 Connections from the drivers to the respective gate of

the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance.

 All sensitive analog traces and components pertaining

to FB, GND, EN, PGOOD, CS and VCC should be

placed away from high voltage switching nodes such as

PHASE, LGATE, UGATE, or BOOT nodes to prevent it

from coupling. Use internal layer(s) as ground plane(s)

and shield the feedback trace from power traces and

components.

P_D(MAX)= (125°C − 25°C) / (36.9°C/W) = 2.71W for a

WDFN-14L 3x2 package.

The maximum power dissipation depends on the operating

ambient temperature for the fixed T_J(MAX)and the thermal

©

is a registered trademark of Richtek Technology Corporation.

DS6541A-02 September 2019

www.richtek.com

15

RT6541A

 Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with

the current limit resistor located at the device.

 Power sections should connect directly to ground

plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

16

DS6541A-02 September 2019

RT6541A

Outline Dimension

2

1

2

1

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min.

0.700

0.000

0.175

0.150

2.950

2.450

2.550

1.950

0.750

0.850

Max.

0.800

0.050

0.250

3.050

2.550

2.650

2.050

0.850

0.950

Min.

0.028

0.000

0.007

0.006

0.116

0.096

0.100

0.077

0.030

0.033

Max.

0.031

0.002

0.010

0.120

0.100

0.104

0.081

0.033

0.037

A

A1

A3

b

D

Option1

Option2

D2

E

Option1

Option2

E2

e

L

0.400

0.016

0.300

0.400

0.012

0.016

W-Type 14L DFN 3x2 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify

that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek

product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;

nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent

or patent rights of Richtek or its subsidiaries.

DS6541A-02 September 2019

www.richtek.com

17


型号：	RT6541A
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总17页 (文件大小：215K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT6541A [RICHTEK]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E